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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.50


Total test records in report: 1237
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T1031 /workspace/coverage/default/154.uart_fifo_reset.3923976915 Jul 01 12:44:23 PM PDT 24 Jul 01 12:46:50 PM PDT 24 181778604616 ps
T1032 /workspace/coverage/default/37.uart_smoke.86784491 Jul 01 12:40:50 PM PDT 24 Jul 01 12:41:06 PM PDT 24 6060852884 ps
T1033 /workspace/coverage/default/5.uart_fifo_overflow.795866711 Jul 01 12:35:46 PM PDT 24 Jul 01 12:35:52 PM PDT 24 28443551890 ps
T1034 /workspace/coverage/default/31.uart_smoke.592012065 Jul 01 12:39:48 PM PDT 24 Jul 01 12:39:58 PM PDT 24 5358489331 ps
T1035 /workspace/coverage/default/210.uart_fifo_reset.291563185 Jul 01 12:45:03 PM PDT 24 Jul 01 12:46:14 PM PDT 24 135410901187 ps
T1036 /workspace/coverage/default/87.uart_fifo_reset.1772041639 Jul 01 12:43:25 PM PDT 24 Jul 01 12:44:02 PM PDT 24 112639450753 ps
T1037 /workspace/coverage/default/129.uart_fifo_reset.3620660778 Jul 01 12:44:01 PM PDT 24 Jul 01 12:44:15 PM PDT 24 25758968347 ps
T1038 /workspace/coverage/default/47.uart_rx_parity_err.4211128213 Jul 01 12:42:26 PM PDT 24 Jul 01 12:43:00 PM PDT 24 44780453561 ps
T1039 /workspace/coverage/default/46.uart_noise_filter.1185477072 Jul 01 12:42:14 PM PDT 24 Jul 01 12:42:52 PM PDT 24 66870558790 ps
T1040 /workspace/coverage/default/73.uart_fifo_reset.2538983906 Jul 01 12:43:18 PM PDT 24 Jul 01 12:44:25 PM PDT 24 131661886626 ps
T1041 /workspace/coverage/default/173.uart_fifo_reset.410101273 Jul 01 12:44:39 PM PDT 24 Jul 01 12:47:03 PM PDT 24 105892537755 ps
T1042 /workspace/coverage/default/30.uart_fifo_full.3882931814 Jul 01 12:39:40 PM PDT 24 Jul 01 12:42:49 PM PDT 24 129019822100 ps
T1043 /workspace/coverage/default/41.uart_rx_parity_err.3311607277 Jul 01 12:41:30 PM PDT 24 Jul 01 12:41:52 PM PDT 24 18086217370 ps
T1044 /workspace/coverage/default/32.uart_tx_ovrd.1193724016 Jul 01 12:40:04 PM PDT 24 Jul 01 12:40:07 PM PDT 24 1373696383 ps
T1045 /workspace/coverage/default/23.uart_long_xfer_wo_dly.2614100165 Jul 01 12:38:35 PM PDT 24 Jul 01 01:05:36 PM PDT 24 178017767510 ps
T1046 /workspace/coverage/default/48.uart_fifo_full.1951990712 Jul 01 12:42:29 PM PDT 24 Jul 01 12:44:39 PM PDT 24 256575619968 ps
T1047 /workspace/coverage/default/6.uart_tx_rx.3728336362 Jul 01 12:35:54 PM PDT 24 Jul 01 12:35:59 PM PDT 24 2795672821 ps
T1048 /workspace/coverage/default/41.uart_fifo_reset.1564112400 Jul 01 12:41:25 PM PDT 24 Jul 01 12:42:03 PM PDT 24 23849555276 ps
T1049 /workspace/coverage/default/10.uart_alert_test.599070855 Jul 01 12:36:38 PM PDT 24 Jul 01 12:36:40 PM PDT 24 12841855 ps
T1050 /workspace/coverage/default/16.uart_rx_oversample.1447471693 Jul 01 12:37:27 PM PDT 24 Jul 01 12:37:29 PM PDT 24 1393202330 ps
T1051 /workspace/coverage/default/39.uart_smoke.2663123983 Jul 01 12:41:11 PM PDT 24 Jul 01 12:41:15 PM PDT 24 684010236 ps
T1052 /workspace/coverage/default/33.uart_stress_all_with_rand_reset.622201182 Jul 01 12:40:21 PM PDT 24 Jul 01 12:43:24 PM PDT 24 166921888815 ps
T1053 /workspace/coverage/default/45.uart_alert_test.3196078274 Jul 01 12:42:10 PM PDT 24 Jul 01 12:42:12 PM PDT 24 13706405 ps
T1054 /workspace/coverage/default/10.uart_stress_all.4138162383 Jul 01 12:36:38 PM PDT 24 Jul 01 12:38:19 PM PDT 24 60742612891 ps
T1055 /workspace/coverage/default/5.uart_rx_start_bit_filter.1158186163 Jul 01 12:35:49 PM PDT 24 Jul 01 12:35:54 PM PDT 24 1993221895 ps
T1056 /workspace/coverage/default/22.uart_alert_test.3933969377 Jul 01 12:38:29 PM PDT 24 Jul 01 12:38:30 PM PDT 24 19976137 ps
T1057 /workspace/coverage/default/32.uart_fifo_full.3994154211 Jul 01 12:40:02 PM PDT 24 Jul 01 12:41:00 PM PDT 24 51610387600 ps
T1058 /workspace/coverage/default/28.uart_tx_ovrd.3209428035 Jul 01 12:39:28 PM PDT 24 Jul 01 12:39:32 PM PDT 24 2679901110 ps
T1059 /workspace/coverage/default/42.uart_tx_ovrd.1975026515 Jul 01 12:41:40 PM PDT 24 Jul 01 12:41:42 PM PDT 24 1128613244 ps
T1060 /workspace/coverage/default/42.uart_loopback.3602987119 Jul 01 12:41:39 PM PDT 24 Jul 01 12:41:53 PM PDT 24 11984202600 ps
T1061 /workspace/coverage/default/14.uart_rx_oversample.2965668789 Jul 01 12:37:07 PM PDT 24 Jul 01 12:37:26 PM PDT 24 2606769893 ps
T1062 /workspace/coverage/default/15.uart_rx_start_bit_filter.2420613521 Jul 01 12:37:21 PM PDT 24 Jul 01 12:37:32 PM PDT 24 6115320328 ps
T1063 /workspace/coverage/default/18.uart_fifo_overflow.3424322552 Jul 01 12:37:46 PM PDT 24 Jul 01 12:39:15 PM PDT 24 112341113820 ps
T1064 /workspace/coverage/default/118.uart_fifo_reset.449123055 Jul 01 12:44:04 PM PDT 24 Jul 01 12:44:23 PM PDT 24 32894987057 ps
T1065 /workspace/coverage/default/34.uart_rx_oversample.1579879661 Jul 01 12:40:26 PM PDT 24 Jul 01 12:40:35 PM PDT 24 4317624169 ps
T1066 /workspace/coverage/default/39.uart_rx_oversample.3620220799 Jul 01 12:41:11 PM PDT 24 Jul 01 12:41:19 PM PDT 24 3394570383 ps
T1067 /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1701320271 Jul 01 12:38:22 PM PDT 24 Jul 01 12:42:25 PM PDT 24 42137688395 ps
T1068 /workspace/coverage/default/41.uart_smoke.78611954 Jul 01 12:41:21 PM PDT 24 Jul 01 12:41:24 PM PDT 24 481834651 ps
T1069 /workspace/coverage/default/50.uart_fifo_reset.3822746493 Jul 01 12:42:46 PM PDT 24 Jul 01 12:43:06 PM PDT 24 46674881248 ps
T1070 /workspace/coverage/default/37.uart_loopback.3969228373 Jul 01 12:40:54 PM PDT 24 Jul 01 12:41:03 PM PDT 24 4739963904 ps
T1071 /workspace/coverage/default/2.uart_rx_oversample.455310258 Jul 01 12:35:35 PM PDT 24 Jul 01 12:35:38 PM PDT 24 1504534055 ps
T1072 /workspace/coverage/default/195.uart_fifo_reset.2483229802 Jul 01 12:44:54 PM PDT 24 Jul 01 12:46:27 PM PDT 24 223618029727 ps
T1073 /workspace/coverage/default/48.uart_stress_all.1630358615 Jul 01 12:42:35 PM PDT 24 Jul 01 12:47:09 PM PDT 24 363481378235 ps
T1074 /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2997576250 Jul 01 12:41:16 PM PDT 24 Jul 01 12:57:33 PM PDT 24 81255425105 ps
T1075 /workspace/coverage/default/12.uart_fifo_full.780957123 Jul 01 12:36:47 PM PDT 24 Jul 01 12:37:22 PM PDT 24 75198612124 ps
T97 /workspace/coverage/default/1.uart_sec_cm.661667996 Jul 01 12:35:27 PM PDT 24 Jul 01 12:35:29 PM PDT 24 70017109 ps
T1076 /workspace/coverage/default/27.uart_rx_oversample.3862757452 Jul 01 12:39:08 PM PDT 24 Jul 01 12:39:29 PM PDT 24 5663113335 ps
T1077 /workspace/coverage/default/117.uart_fifo_reset.2138340206 Jul 01 12:43:59 PM PDT 24 Jul 01 12:44:24 PM PDT 24 18621560541 ps
T1078 /workspace/coverage/default/15.uart_loopback.3026269903 Jul 01 12:37:24 PM PDT 24 Jul 01 12:37:31 PM PDT 24 11280618817 ps
T1079 /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3407017362 Jul 01 12:43:27 PM PDT 24 Jul 01 12:47:57 PM PDT 24 89262509075 ps
T1080 /workspace/coverage/default/4.uart_tx_rx.986279246 Jul 01 12:35:44 PM PDT 24 Jul 01 12:35:51 PM PDT 24 40353551000 ps
T1081 /workspace/coverage/default/1.uart_rx_start_bit_filter.3793030287 Jul 01 12:35:27 PM PDT 24 Jul 01 12:35:33 PM PDT 24 5149694036 ps
T1082 /workspace/coverage/default/8.uart_fifo_overflow.1437683352 Jul 01 12:36:10 PM PDT 24 Jul 01 12:36:45 PM PDT 24 20396716576 ps
T1083 /workspace/coverage/default/22.uart_rx_parity_err.4108923719 Jul 01 12:38:25 PM PDT 24 Jul 01 12:38:53 PM PDT 24 27818195063 ps
T1084 /workspace/coverage/default/17.uart_smoke.1332205732 Jul 01 12:37:33 PM PDT 24 Jul 01 12:37:36 PM PDT 24 811415488 ps
T1085 /workspace/coverage/default/23.uart_alert_test.975980543 Jul 01 12:38:39 PM PDT 24 Jul 01 12:38:40 PM PDT 24 44025357 ps
T1086 /workspace/coverage/default/15.uart_fifo_reset.1480472162 Jul 01 12:37:16 PM PDT 24 Jul 01 12:37:48 PM PDT 24 17375281261 ps
T1087 /workspace/coverage/default/239.uart_fifo_reset.1485146540 Jul 01 12:45:24 PM PDT 24 Jul 01 12:45:57 PM PDT 24 195056305082 ps
T1088 /workspace/coverage/default/8.uart_rx_parity_err.793866314 Jul 01 12:36:11 PM PDT 24 Jul 01 12:37:20 PM PDT 24 34998581202 ps
T1089 /workspace/coverage/default/29.uart_rx_start_bit_filter.114046345 Jul 01 12:39:37 PM PDT 24 Jul 01 12:39:40 PM PDT 24 4695721507 ps
T1090 /workspace/coverage/default/52.uart_fifo_reset.86609897 Jul 01 12:42:49 PM PDT 24 Jul 01 12:43:58 PM PDT 24 85541660170 ps
T1091 /workspace/coverage/default/9.uart_noise_filter.1680255717 Jul 01 12:36:18 PM PDT 24 Jul 01 12:36:21 PM PDT 24 2271845687 ps
T1092 /workspace/coverage/default/34.uart_fifo_reset.2004225830 Jul 01 12:40:25 PM PDT 24 Jul 01 12:42:45 PM PDT 24 230280664673 ps
T1093 /workspace/coverage/default/20.uart_stress_all.563418759 Jul 01 12:38:05 PM PDT 24 Jul 01 12:42:40 PM PDT 24 166447528312 ps
T1094 /workspace/coverage/default/13.uart_intr.3809268019 Jul 01 12:36:57 PM PDT 24 Jul 01 12:37:11 PM PDT 24 9007377985 ps
T1095 /workspace/coverage/default/32.uart_rx_start_bit_filter.4098971046 Jul 01 12:40:03 PM PDT 24 Jul 01 12:40:58 PM PDT 24 35561471265 ps
T1096 /workspace/coverage/default/26.uart_rx_parity_err.2534428311 Jul 01 12:39:04 PM PDT 24 Jul 01 12:40:34 PM PDT 24 57633276529 ps
T1097 /workspace/coverage/default/10.uart_stress_all_with_rand_reset.639499404 Jul 01 12:36:34 PM PDT 24 Jul 01 01:03:22 PM PDT 24 194528291812 ps
T1098 /workspace/coverage/default/30.uart_tx_rx.2467917206 Jul 01 12:39:40 PM PDT 24 Jul 01 12:41:43 PM PDT 24 72170265081 ps
T1099 /workspace/coverage/default/19.uart_intr.2536329764 Jul 01 12:37:55 PM PDT 24 Jul 01 12:38:13 PM PDT 24 8959530700 ps
T1100 /workspace/coverage/default/14.uart_loopback.4219803783 Jul 01 12:37:17 PM PDT 24 Jul 01 12:37:37 PM PDT 24 9740211371 ps
T1101 /workspace/coverage/default/6.uart_fifo_full.3767857510 Jul 01 12:35:55 PM PDT 24 Jul 01 12:40:04 PM PDT 24 157071554572 ps
T81 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1477403581 Jul 01 10:43:41 AM PDT 24 Jul 01 10:43:43 AM PDT 24 65395742 ps
T1102 /workspace/coverage/cover_reg_top/19.uart_intr_test.338407719 Jul 01 10:43:17 AM PDT 24 Jul 01 10:43:19 AM PDT 24 72186831 ps
T1103 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2974282373 Jul 01 10:42:56 AM PDT 24 Jul 01 10:43:00 AM PDT 24 31475795 ps
T89 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1822531606 Jul 01 10:43:35 AM PDT 24 Jul 01 10:43:37 AM PDT 24 82302858 ps
T1104 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2613036653 Jul 01 10:43:29 AM PDT 24 Jul 01 10:43:30 AM PDT 24 89789344 ps
T82 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3646491345 Jul 01 10:43:32 AM PDT 24 Jul 01 10:43:34 AM PDT 24 174386790 ps
T83 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1991531324 Jul 01 10:43:25 AM PDT 24 Jul 01 10:43:27 AM PDT 24 75578578 ps
T84 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3326614051 Jul 01 10:43:07 AM PDT 24 Jul 01 10:43:12 AM PDT 24 42087165 ps
T1105 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1966011917 Jul 01 10:43:14 AM PDT 24 Jul 01 10:43:16 AM PDT 24 119621096 ps
T1106 /workspace/coverage/cover_reg_top/19.uart_tl_errors.1508659871 Jul 01 10:43:24 AM PDT 24 Jul 01 10:43:25 AM PDT 24 48983324 ps
T1107 /workspace/coverage/cover_reg_top/9.uart_csr_rw.63740240 Jul 01 10:43:35 AM PDT 24 Jul 01 10:43:36 AM PDT 24 28644346 ps
T1108 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.157519762 Jul 01 10:43:13 AM PDT 24 Jul 01 10:43:15 AM PDT 24 57477945 ps
T1109 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2950119236 Jul 01 10:42:57 AM PDT 24 Jul 01 10:42:59 AM PDT 24 55024084 ps
T1110 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.289029565 Jul 01 10:43:04 AM PDT 24 Jul 01 10:43:10 AM PDT 24 129755088 ps
T1111 /workspace/coverage/cover_reg_top/43.uart_intr_test.2964474016 Jul 01 10:43:46 AM PDT 24 Jul 01 10:43:47 AM PDT 24 14787212 ps
T90 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1996195055 Jul 01 10:43:28 AM PDT 24 Jul 01 10:43:29 AM PDT 24 149368659 ps
T1112 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2041962495 Jul 01 10:42:56 AM PDT 24 Jul 01 10:42:59 AM PDT 24 17664128 ps
T1113 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2429338443 Jul 01 10:43:10 AM PDT 24 Jul 01 10:43:13 AM PDT 24 150380060 ps
T1114 /workspace/coverage/cover_reg_top/30.uart_intr_test.1039464960 Jul 01 10:43:30 AM PDT 24 Jul 01 10:43:31 AM PDT 24 42965229 ps
T1115 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3022045707 Jul 01 10:43:05 AM PDT 24 Jul 01 10:43:11 AM PDT 24 70458588 ps
T1116 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3008249004 Jul 01 10:43:06 AM PDT 24 Jul 01 10:43:12 AM PDT 24 22412774 ps
T60 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2049659446 Jul 01 10:43:30 AM PDT 24 Jul 01 10:43:34 AM PDT 24 15259392 ps
T1117 /workspace/coverage/cover_reg_top/36.uart_intr_test.3800408707 Jul 01 10:43:19 AM PDT 24 Jul 01 10:43:20 AM PDT 24 22855612 ps
T1118 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3940235932 Jul 01 10:42:57 AM PDT 24 Jul 01 10:43:00 AM PDT 24 142152697 ps
T61 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3344494890 Jul 01 10:43:01 AM PDT 24 Jul 01 10:43:07 AM PDT 24 224021519 ps
T91 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3827098156 Jul 01 10:43:04 AM PDT 24 Jul 01 10:43:10 AM PDT 24 286078037 ps
T1119 /workspace/coverage/cover_reg_top/35.uart_intr_test.2814913187 Jul 01 10:43:35 AM PDT 24 Jul 01 10:43:36 AM PDT 24 15755379 ps
T62 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2779168162 Jul 01 10:43:22 AM PDT 24 Jul 01 10:43:23 AM PDT 24 12806843 ps
T92 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2933086316 Jul 01 10:43:34 AM PDT 24 Jul 01 10:43:37 AM PDT 24 83886291 ps
T85 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2825551570 Jul 01 10:42:59 AM PDT 24 Jul 01 10:43:02 AM PDT 24 26335390 ps
T86 /workspace/coverage/cover_reg_top/8.uart_csr_rw.4011859504 Jul 01 10:43:33 AM PDT 24 Jul 01 10:43:35 AM PDT 24 220040102 ps
T87 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1957151922 Jul 01 10:42:58 AM PDT 24 Jul 01 10:43:00 AM PDT 24 14664317 ps
T1120 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3816742956 Jul 01 10:42:55 AM PDT 24 Jul 01 10:42:57 AM PDT 24 45148890 ps
T1121 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1252085403 Jul 01 10:43:15 AM PDT 24 Jul 01 10:43:18 AM PDT 24 104905293 ps
T1122 /workspace/coverage/cover_reg_top/44.uart_intr_test.2575678581 Jul 01 10:43:54 AM PDT 24 Jul 01 10:43:56 AM PDT 24 14718623 ps
T93 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.4216487034 Jul 01 10:43:10 AM PDT 24 Jul 01 10:43:13 AM PDT 24 90254768 ps
T1123 /workspace/coverage/cover_reg_top/40.uart_intr_test.375368967 Jul 01 10:43:26 AM PDT 24 Jul 01 10:43:27 AM PDT 24 26244465 ps
T1124 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1196233693 Jul 01 10:43:01 AM PDT 24 Jul 01 10:43:06 AM PDT 24 114382344 ps
T88 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.520008046 Jul 01 10:43:01 AM PDT 24 Jul 01 10:43:06 AM PDT 24 41629440 ps
T1125 /workspace/coverage/cover_reg_top/11.uart_tl_errors.972155201 Jul 01 10:43:35 AM PDT 24 Jul 01 10:43:37 AM PDT 24 36397814 ps
T1126 /workspace/coverage/cover_reg_top/33.uart_intr_test.156680863 Jul 01 10:43:26 AM PDT 24 Jul 01 10:43:27 AM PDT 24 12860467 ps
T1127 /workspace/coverage/cover_reg_top/27.uart_intr_test.339385416 Jul 01 10:43:16 AM PDT 24 Jul 01 10:43:17 AM PDT 24 28202428 ps
T1128 /workspace/coverage/cover_reg_top/24.uart_intr_test.3786596370 Jul 01 10:43:41 AM PDT 24 Jul 01 10:43:42 AM PDT 24 60021920 ps
T1129 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1725911372 Jul 01 10:43:00 AM PDT 24 Jul 01 10:43:03 AM PDT 24 85220454 ps
T1130 /workspace/coverage/cover_reg_top/16.uart_intr_test.3181186685 Jul 01 10:43:35 AM PDT 24 Jul 01 10:43:37 AM PDT 24 13283952 ps
T1131 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1006090933 Jul 01 10:43:09 AM PDT 24 Jul 01 10:43:13 AM PDT 24 44789297 ps
T1132 /workspace/coverage/cover_reg_top/8.uart_intr_test.669533430 Jul 01 10:43:36 AM PDT 24 Jul 01 10:43:38 AM PDT 24 53638906 ps
T1133 /workspace/coverage/cover_reg_top/15.uart_intr_test.2445610233 Jul 01 10:43:10 AM PDT 24 Jul 01 10:43:13 AM PDT 24 77759610 ps
T66 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2772223181 Jul 01 10:43:12 AM PDT 24 Jul 01 10:43:14 AM PDT 24 30434436 ps
T1134 /workspace/coverage/cover_reg_top/46.uart_intr_test.3413336339 Jul 01 10:43:40 AM PDT 24 Jul 01 10:43:41 AM PDT 24 41632990 ps
T94 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3365309274 Jul 01 10:43:06 AM PDT 24 Jul 01 10:43:12 AM PDT 24 55107833 ps
T1135 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2681959497 Jul 01 10:42:54 AM PDT 24 Jul 01 10:42:57 AM PDT 24 70111288 ps
T1136 /workspace/coverage/cover_reg_top/13.uart_intr_test.314836896 Jul 01 10:43:32 AM PDT 24 Jul 01 10:43:34 AM PDT 24 42137293 ps
T1137 /workspace/coverage/cover_reg_top/17.uart_intr_test.985005511 Jul 01 10:43:16 AM PDT 24 Jul 01 10:43:17 AM PDT 24 14488856 ps
T1138 /workspace/coverage/cover_reg_top/0.uart_tl_errors.791769574 Jul 01 10:42:54 AM PDT 24 Jul 01 10:42:56 AM PDT 24 88220015 ps
T63 /workspace/coverage/cover_reg_top/18.uart_csr_rw.675816374 Jul 01 10:43:41 AM PDT 24 Jul 01 10:43:42 AM PDT 24 12502150 ps
T1139 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2531682011 Jul 01 10:43:40 AM PDT 24 Jul 01 10:43:42 AM PDT 24 69074175 ps
T1140 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2864646773 Jul 01 10:44:30 AM PDT 24 Jul 01 10:44:31 AM PDT 24 12718700 ps
T1141 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3685906088 Jul 01 10:43:22 AM PDT 24 Jul 01 10:43:29 AM PDT 24 56524471 ps
T1142 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3533428944 Jul 01 10:43:44 AM PDT 24 Jul 01 10:43:45 AM PDT 24 62736716 ps
T95 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2768945608 Jul 01 10:43:27 AM PDT 24 Jul 01 10:43:28 AM PDT 24 88020175 ps
T1143 /workspace/coverage/cover_reg_top/37.uart_intr_test.1849648077 Jul 01 10:43:17 AM PDT 24 Jul 01 10:43:19 AM PDT 24 56761925 ps
T1144 /workspace/coverage/cover_reg_top/10.uart_tl_errors.699035623 Jul 01 10:43:45 AM PDT 24 Jul 01 10:43:47 AM PDT 24 320057618 ps
T1145 /workspace/coverage/cover_reg_top/32.uart_intr_test.426805558 Jul 01 10:43:16 AM PDT 24 Jul 01 10:43:17 AM PDT 24 61152735 ps
T1146 /workspace/coverage/cover_reg_top/21.uart_intr_test.724854138 Jul 01 10:43:25 AM PDT 24 Jul 01 10:43:26 AM PDT 24 14518790 ps
T1147 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3797061630 Jul 01 10:42:59 AM PDT 24 Jul 01 10:43:03 AM PDT 24 462681407 ps
T130 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3975062197 Jul 01 10:43:21 AM PDT 24 Jul 01 10:43:23 AM PDT 24 213346940 ps
T1148 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3362529111 Jul 01 10:43:02 AM PDT 24 Jul 01 10:43:07 AM PDT 24 241592060 ps
T1149 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3873074260 Jul 01 10:43:41 AM PDT 24 Jul 01 10:43:42 AM PDT 24 69661657 ps
T1150 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.244704113 Jul 01 10:43:32 AM PDT 24 Jul 01 10:43:34 AM PDT 24 113586023 ps
T64 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1721620567 Jul 01 10:43:43 AM PDT 24 Jul 01 10:43:44 AM PDT 24 23228293 ps
T1151 /workspace/coverage/cover_reg_top/28.uart_intr_test.1365685956 Jul 01 10:43:31 AM PDT 24 Jul 01 10:43:32 AM PDT 24 13530409 ps
T1152 /workspace/coverage/cover_reg_top/11.uart_intr_test.1536337696 Jul 01 10:43:04 AM PDT 24 Jul 01 10:43:09 AM PDT 24 27519710 ps
T65 /workspace/coverage/cover_reg_top/3.uart_csr_rw.549686368 Jul 01 10:43:00 AM PDT 24 Jul 01 10:43:03 AM PDT 24 19954537 ps
T1153 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3112830286 Jul 01 10:42:58 AM PDT 24 Jul 01 10:43:00 AM PDT 24 128990201 ps
T1154 /workspace/coverage/cover_reg_top/49.uart_intr_test.3887741980 Jul 01 10:43:54 AM PDT 24 Jul 01 10:43:57 AM PDT 24 37493502 ps
T1155 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1712609999 Jul 01 10:43:05 AM PDT 24 Jul 01 10:43:10 AM PDT 24 37761295 ps
T1156 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2248033908 Jul 01 10:43:28 AM PDT 24 Jul 01 10:43:29 AM PDT 24 59747830 ps
T78 /workspace/coverage/cover_reg_top/13.uart_csr_rw.819590250 Jul 01 10:43:08 AM PDT 24 Jul 01 10:43:13 AM PDT 24 95362659 ps
T1157 /workspace/coverage/cover_reg_top/12.uart_tl_errors.740947041 Jul 01 10:43:22 AM PDT 24 Jul 01 10:43:23 AM PDT 24 81377280 ps
T75 /workspace/coverage/cover_reg_top/1.uart_csr_rw.22647447 Jul 01 10:43:01 AM PDT 24 Jul 01 10:43:06 AM PDT 24 25941999 ps
T1158 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2289828817 Jul 01 10:43:28 AM PDT 24 Jul 01 10:43:29 AM PDT 24 34218007 ps
T1159 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3434943175 Jul 01 10:43:00 AM PDT 24 Jul 01 10:43:03 AM PDT 24 80519158 ps
T1160 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.499953399 Jul 01 10:43:24 AM PDT 24 Jul 01 10:43:30 AM PDT 24 18717339 ps
T1161 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2284712156 Jul 01 10:42:56 AM PDT 24 Jul 01 10:42:59 AM PDT 24 32805726 ps
T1162 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1332807736 Jul 01 10:43:03 AM PDT 24 Jul 01 10:43:09 AM PDT 24 288751369 ps
T1163 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.580899372 Jul 01 10:43:13 AM PDT 24 Jul 01 10:43:15 AM PDT 24 267318894 ps
T1164 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1225594565 Jul 01 10:43:17 AM PDT 24 Jul 01 10:43:19 AM PDT 24 15468064 ps
T1165 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1609292271 Jul 01 10:43:39 AM PDT 24 Jul 01 10:43:40 AM PDT 24 49108788 ps
T1166 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3279324977 Jul 01 10:43:17 AM PDT 24 Jul 01 10:43:19 AM PDT 24 39895900 ps
T1167 /workspace/coverage/cover_reg_top/25.uart_intr_test.303735052 Jul 01 10:43:16 AM PDT 24 Jul 01 10:43:17 AM PDT 24 18285813 ps
T1168 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2971078521 Jul 01 10:43:06 AM PDT 24 Jul 01 10:43:12 AM PDT 24 36351972 ps
T1169 /workspace/coverage/cover_reg_top/45.uart_intr_test.3564595226 Jul 01 10:43:41 AM PDT 24 Jul 01 10:43:43 AM PDT 24 21184020 ps
T1170 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3016757870 Jul 01 10:43:21 AM PDT 24 Jul 01 10:43:22 AM PDT 24 77166027 ps
T1171 /workspace/coverage/cover_reg_top/20.uart_intr_test.1406640479 Jul 01 10:43:15 AM PDT 24 Jul 01 10:43:17 AM PDT 24 21927066 ps
T1172 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3060502237 Jul 01 10:43:34 AM PDT 24 Jul 01 10:43:37 AM PDT 24 106557275 ps
T1173 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4037694888 Jul 01 10:42:57 AM PDT 24 Jul 01 10:43:00 AM PDT 24 142625022 ps
T1174 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.840551850 Jul 01 10:43:36 AM PDT 24 Jul 01 10:43:38 AM PDT 24 42412040 ps
T1175 /workspace/coverage/cover_reg_top/48.uart_intr_test.3474504358 Jul 01 10:43:42 AM PDT 24 Jul 01 10:43:43 AM PDT 24 22851734 ps
T1176 /workspace/coverage/cover_reg_top/31.uart_intr_test.3090439600 Jul 01 10:43:27 AM PDT 24 Jul 01 10:43:27 AM PDT 24 41049965 ps
T1177 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.911668717 Jul 01 10:43:28 AM PDT 24 Jul 01 10:43:30 AM PDT 24 461120120 ps
T1178 /workspace/coverage/cover_reg_top/7.uart_tl_errors.4187044193 Jul 01 10:43:02 AM PDT 24 Jul 01 10:43:08 AM PDT 24 46442517 ps
T1179 /workspace/coverage/cover_reg_top/22.uart_intr_test.3672188546 Jul 01 10:43:20 AM PDT 24 Jul 01 10:43:21 AM PDT 24 52959312 ps
T1180 /workspace/coverage/cover_reg_top/9.uart_intr_test.37524863 Jul 01 10:43:25 AM PDT 24 Jul 01 10:43:26 AM PDT 24 35351065 ps
T1181 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1944828355 Jul 01 10:43:10 AM PDT 24 Jul 01 10:43:13 AM PDT 24 55697441 ps
T1182 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.599476892 Jul 01 10:43:01 AM PDT 24 Jul 01 10:43:05 AM PDT 24 48882821 ps
T1183 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3027486245 Jul 01 10:43:10 AM PDT 24 Jul 01 10:43:13 AM PDT 24 64440444 ps
T1184 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4066526462 Jul 01 10:43:32 AM PDT 24 Jul 01 10:43:35 AM PDT 24 584938366 ps
T76 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2478944047 Jul 01 10:43:52 AM PDT 24 Jul 01 10:43:53 AM PDT 24 80099154 ps
T79 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3775342305 Jul 01 10:43:03 AM PDT 24 Jul 01 10:43:08 AM PDT 24 26805402 ps
T1185 /workspace/coverage/cover_reg_top/13.uart_tl_errors.207046692 Jul 01 10:43:08 AM PDT 24 Jul 01 10:43:13 AM PDT 24 32679917 ps
T1186 /workspace/coverage/cover_reg_top/2.uart_intr_test.995086560 Jul 01 10:43:01 AM PDT 24 Jul 01 10:43:05 AM PDT 24 27196540 ps
T80 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1459657770 Jul 01 10:43:33 AM PDT 24 Jul 01 10:43:35 AM PDT 24 58011197 ps
T1187 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2360197417 Jul 01 10:43:07 AM PDT 24 Jul 01 10:43:12 AM PDT 24 20301606 ps
T1188 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.728515991 Jul 01 10:42:54 AM PDT 24 Jul 01 10:42:55 AM PDT 24 37511214 ps
T1189 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3196854409 Jul 01 10:42:55 AM PDT 24 Jul 01 10:42:57 AM PDT 24 75766277 ps
T1190 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2838117448 Jul 01 10:42:57 AM PDT 24 Jul 01 10:43:00 AM PDT 24 65007904 ps
T77 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3036803975 Jul 01 10:43:21 AM PDT 24 Jul 01 10:43:23 AM PDT 24 706326966 ps
T1191 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3680415073 Jul 01 10:43:09 AM PDT 24 Jul 01 10:43:13 AM PDT 24 64719080 ps
T1192 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1226406040 Jul 01 10:43:00 AM PDT 24 Jul 01 10:43:03 AM PDT 24 41779990 ps
T1193 /workspace/coverage/cover_reg_top/41.uart_intr_test.1536793465 Jul 01 10:43:49 AM PDT 24 Jul 01 10:43:50 AM PDT 24 15206754 ps
T1194 /workspace/coverage/cover_reg_top/1.uart_intr_test.2318359797 Jul 01 10:43:14 AM PDT 24 Jul 01 10:43:15 AM PDT 24 43617958 ps
T1195 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.250947026 Jul 01 10:42:55 AM PDT 24 Jul 01 10:42:57 AM PDT 24 168038664 ps
T1196 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1703351562 Jul 01 10:43:23 AM PDT 24 Jul 01 10:43:24 AM PDT 24 18507887 ps
T1197 /workspace/coverage/cover_reg_top/0.uart_csr_rw.843763223 Jul 01 10:42:53 AM PDT 24 Jul 01 10:42:55 AM PDT 24 46666098 ps
T1198 /workspace/coverage/cover_reg_top/18.uart_intr_test.2544364922 Jul 01 10:43:14 AM PDT 24 Jul 01 10:43:15 AM PDT 24 25994595 ps
T1199 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2508675589 Jul 01 10:43:37 AM PDT 24 Jul 01 10:43:39 AM PDT 24 100182028 ps
T1200 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.592859017 Jul 01 10:43:05 AM PDT 24 Jul 01 10:43:11 AM PDT 24 57572520 ps
T1201 /workspace/coverage/cover_reg_top/12.uart_csr_rw.389114652 Jul 01 10:43:08 AM PDT 24 Jul 01 10:43:12 AM PDT 24 14713786 ps
T1202 /workspace/coverage/cover_reg_top/5.uart_intr_test.3904801999 Jul 01 10:42:57 AM PDT 24 Jul 01 10:42:59 AM PDT 24 172504704 ps
T1203 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2680179432 Jul 01 10:43:01 AM PDT 24 Jul 01 10:43:07 AM PDT 24 509815593 ps
T1204 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3362543233 Jul 01 10:43:35 AM PDT 24 Jul 01 10:43:37 AM PDT 24 69203516 ps
T1205 /workspace/coverage/cover_reg_top/7.uart_intr_test.6790434 Jul 01 10:43:39 AM PDT 24 Jul 01 10:43:40 AM PDT 24 15741919 ps
T1206 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1250874436 Jul 01 10:42:59 AM PDT 24 Jul 01 10:43:02 AM PDT 24 76970591 ps
T1207 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1596998282 Jul 01 10:43:10 AM PDT 24 Jul 01 10:43:13 AM PDT 24 37260243 ps
T1208 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3861038026 Jul 01 10:42:56 AM PDT 24 Jul 01 10:42:57 AM PDT 24 18304750 ps
T1209 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.489914163 Jul 01 10:43:05 AM PDT 24 Jul 01 10:43:10 AM PDT 24 12657332 ps
T1210 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2223877387 Jul 01 10:42:59 AM PDT 24 Jul 01 10:43:02 AM PDT 24 55181140 ps
T1211 /workspace/coverage/cover_reg_top/6.uart_intr_test.3735471898 Jul 01 10:43:09 AM PDT 24 Jul 01 10:43:13 AM PDT 24 17912896 ps
T1212 /workspace/coverage/cover_reg_top/42.uart_intr_test.2527973197 Jul 01 10:43:23 AM PDT 24 Jul 01 10:43:24 AM PDT 24 15613364 ps
T1213 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3559304883 Jul 01 10:43:17 AM PDT 24 Jul 01 10:43:19 AM PDT 24 384294016 ps
T1214 /workspace/coverage/cover_reg_top/34.uart_intr_test.2730664023 Jul 01 10:43:32 AM PDT 24 Jul 01 10:43:34 AM PDT 24 40244641 ps
T1215 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3600423515 Jul 01 10:43:00 AM PDT 24 Jul 01 10:43:03 AM PDT 24 93027833 ps
T1216 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3476501725 Jul 01 10:43:06 AM PDT 24 Jul 01 10:43:11 AM PDT 24 139492743 ps
T1217 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3827785126 Jul 01 10:43:35 AM PDT 24 Jul 01 10:43:37 AM PDT 24 267234419 ps
T1218 /workspace/coverage/cover_reg_top/38.uart_intr_test.1730094832 Jul 01 10:43:42 AM PDT 24 Jul 01 10:43:44 AM PDT 24 14406496 ps
T1219 /workspace/coverage/cover_reg_top/4.uart_intr_test.2014898120 Jul 01 10:43:04 AM PDT 24 Jul 01 10:43:09 AM PDT 24 13272451 ps
T1220 /workspace/coverage/cover_reg_top/23.uart_intr_test.601798651 Jul 01 10:43:29 AM PDT 24 Jul 01 10:43:34 AM PDT 24 32001539 ps
T1221 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2708247763 Jul 01 10:43:14 AM PDT 24 Jul 01 10:43:16 AM PDT 24 118442696 ps
T1222 /workspace/coverage/cover_reg_top/29.uart_intr_test.1596682605 Jul 01 10:43:46 AM PDT 24 Jul 01 10:43:47 AM PDT 24 42414767 ps
T1223 /workspace/coverage/cover_reg_top/14.uart_intr_test.124751834 Jul 01 10:43:34 AM PDT 24 Jul 01 10:43:36 AM PDT 24 31308425 ps
T1224 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2254707539 Jul 01 10:43:05 AM PDT 24 Jul 01 10:43:11 AM PDT 24 60646595 ps
T1225 /workspace/coverage/cover_reg_top/3.uart_intr_test.241172431 Jul 01 10:43:00 AM PDT 24 Jul 01 10:43:03 AM PDT 24 12690703 ps
T1226 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1740892987 Jul 01 10:43:16 AM PDT 24 Jul 01 10:43:18 AM PDT 24 22119541 ps
T1227 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2529558598 Jul 01 10:43:08 AM PDT 24 Jul 01 10:43:13 AM PDT 24 28726627 ps
T1228 /workspace/coverage/cover_reg_top/12.uart_intr_test.143327223 Jul 01 10:43:21 AM PDT 24 Jul 01 10:43:22 AM PDT 24 15959348 ps
T1229 /workspace/coverage/cover_reg_top/5.uart_tl_errors.817107142 Jul 01 10:43:17 AM PDT 24 Jul 01 10:43:18 AM PDT 24 171577899 ps
T1230 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3514282436 Jul 01 10:43:01 AM PDT 24 Jul 01 10:43:05 AM PDT 24 69810157 ps
T1231 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1755761466 Jul 01 10:43:04 AM PDT 24 Jul 01 10:43:09 AM PDT 24 17806707 ps
T1232 /workspace/coverage/cover_reg_top/10.uart_intr_test.1653910995 Jul 01 10:43:06 AM PDT 24 Jul 01 10:43:11 AM PDT 24 27490543 ps
T1233 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1825643946 Jul 01 10:43:08 AM PDT 24 Jul 01 10:43:12 AM PDT 24 41833462 ps
T1234 /workspace/coverage/cover_reg_top/26.uart_intr_test.2041292630 Jul 01 10:43:29 AM PDT 24 Jul 01 10:43:30 AM PDT 24 29200527 ps
T1235 /workspace/coverage/cover_reg_top/39.uart_intr_test.1085629962 Jul 01 10:43:50 AM PDT 24 Jul 01 10:43:51 AM PDT 24 19465678 ps
T1236 /workspace/coverage/cover_reg_top/0.uart_intr_test.254626826 Jul 01 10:43:03 AM PDT 24 Jul 01 10:43:07 AM PDT 24 33092544 ps
T1237 /workspace/coverage/cover_reg_top/47.uart_intr_test.3098467318 Jul 01 10:43:54 AM PDT 24 Jul 01 10:43:57 AM PDT 24 13560557 ps

Test location /workspace/coverage/default/48.uart_fifo_overflow.3751778844
Short name T9
Test name
Test status
Simulation time 298691137710 ps
CPU time 325.3 seconds
Started Jul 01 12:42:31 PM PDT 24
Finished Jul 01 12:47:58 PM PDT 24
Peak memory 199932 kb
Host smart-72538184-de0a-43c8-8b7e-81a4cc631981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751778844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3751778844
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.400319046
Short name T16
Test name
Test status
Simulation time 67640506918 ps
CPU time 963.29 seconds
Started Jul 01 12:43:29 PM PDT 24
Finished Jul 01 12:59:33 PM PDT 24
Peak memory 216524 kb
Host smart-e91caf46-0375-4359-84e6-c9c0952a7386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400319046 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.400319046
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.1959274965
Short name T134
Test name
Test status
Simulation time 423369601643 ps
CPU time 398.88 seconds
Started Jul 01 12:38:39 PM PDT 24
Finished Jul 01 12:45:19 PM PDT 24
Peak memory 199812 kb
Host smart-d05dbb97-50ec-4817-a0b2-18e74a9b6513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959274965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1959274965
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2728860373
Short name T15
Test name
Test status
Simulation time 228305479949 ps
CPU time 519.41 seconds
Started Jul 01 12:43:21 PM PDT 24
Finished Jul 01 12:52:01 PM PDT 24
Peak memory 216336 kb
Host smart-d40c21e7-62b8-4762-8c6c-154d19834398
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728860373 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2728860373
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1616864668
Short name T37
Test name
Test status
Simulation time 104033447342 ps
CPU time 1167.13 seconds
Started Jul 01 12:40:01 PM PDT 24
Finished Jul 01 12:59:29 PM PDT 24
Peak memory 216456 kb
Host smart-3d9aa8bd-94ce-4066-aea4-d9f3685c2b2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616864668 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1616864668
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all.500734726
Short name T26
Test name
Test status
Simulation time 174251450817 ps
CPU time 347.52 seconds
Started Jul 01 12:38:59 PM PDT 24
Finished Jul 01 12:44:48 PM PDT 24
Peak memory 199880 kb
Host smart-8a41136b-437d-4fd5-81da-3a0b65688aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500734726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.500734726
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2729150783
Short name T41
Test name
Test status
Simulation time 182695375253 ps
CPU time 796.27 seconds
Started Jul 01 12:40:31 PM PDT 24
Finished Jul 01 12:53:48 PM PDT 24
Peak memory 216424 kb
Host smart-647c2b16-a1f5-4f34-bae0-4e9d6cff77f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729150783 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2729150783
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.210558513
Short name T70
Test name
Test status
Simulation time 145264754760 ps
CPU time 1219.93 seconds
Started Jul 01 12:37:41 PM PDT 24
Finished Jul 01 12:58:01 PM PDT 24
Peak memory 199932 kb
Host smart-6c81e51e-bbc5-4638-9c2e-56dece2c303e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210558513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.210558513
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2785344434
Short name T33
Test name
Test status
Simulation time 124870982 ps
CPU time 0.8 seconds
Started Jul 01 12:35:31 PM PDT 24
Finished Jul 01 12:35:32 PM PDT 24
Peak memory 218184 kb
Host smart-86b776d3-9f27-4819-850a-04f2c60bde3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785344434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2785344434
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2094955614
Short name T40
Test name
Test status
Simulation time 141248361655 ps
CPU time 876.71 seconds
Started Jul 01 12:43:05 PM PDT 24
Finished Jul 01 12:57:43 PM PDT 24
Peak memory 215096 kb
Host smart-9ea7d146-af7a-431e-a082-0d415096e8fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094955614 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2094955614
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3121787414
Short name T14
Test name
Test status
Simulation time 350223540302 ps
CPU time 56.46 seconds
Started Jul 01 12:38:19 PM PDT 24
Finished Jul 01 12:39:16 PM PDT 24
Peak memory 200016 kb
Host smart-e00e1fdc-4995-491d-9820-624bcf20afcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121787414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3121787414
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_stress_all.1825283198
Short name T128
Test name
Test status
Simulation time 390861495822 ps
CPU time 236.69 seconds
Started Jul 01 12:35:21 PM PDT 24
Finished Jul 01 12:39:18 PM PDT 24
Peak memory 199932 kb
Host smart-993bef3e-95bc-49c7-81f1-9457506b7b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825283198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1825283198
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all.3677054
Short name T21
Test name
Test status
Simulation time 184758363820 ps
CPU time 433.08 seconds
Started Jul 01 12:38:01 PM PDT 24
Finished Jul 01 12:45:15 PM PDT 24
Peak memory 199944 kb
Host smart-a6045360-ca91-4a77-bf9a-eca3d1d3e54c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3677054
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3172079750
Short name T49
Test name
Test status
Simulation time 222419928989 ps
CPU time 152.42 seconds
Started Jul 01 12:40:56 PM PDT 24
Finished Jul 01 12:43:29 PM PDT 24
Peak memory 199928 kb
Host smart-4e8274b6-a7f5-4c79-a778-6c67ea3d9619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172079750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3172079750
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3222692036
Short name T133
Test name
Test status
Simulation time 108101863833 ps
CPU time 168.2 seconds
Started Jul 01 12:41:37 PM PDT 24
Finished Jul 01 12:44:26 PM PDT 24
Peak memory 199976 kb
Host smart-de6e7c3f-a54b-4ec2-aeae-592ac85b1e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222692036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3222692036
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3827098156
Short name T91
Test name
Test status
Simulation time 286078037 ps
CPU time 1.28 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 199652 kb
Host smart-7e2bb4a9-35c9-4927-9d31-3b919a371816
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827098156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3827098156
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3564273786
Short name T132
Test name
Test status
Simulation time 180409003517 ps
CPU time 387.86 seconds
Started Jul 01 12:36:29 PM PDT 24
Finished Jul 01 12:42:57 PM PDT 24
Peak memory 199952 kb
Host smart-8c2ae37f-50f2-4720-9c8c-be9a9f1de7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564273786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3564273786
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_stress_all.1826769986
Short name T263
Test name
Test status
Simulation time 613311214763 ps
CPU time 407.66 seconds
Started Jul 01 12:38:29 PM PDT 24
Finished Jul 01 12:45:17 PM PDT 24
Peak memory 199968 kb
Host smart-34e7f7bd-fddf-4486-b211-2689cc2ca99c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826769986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1826769986
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1740736205
Short name T149
Test name
Test status
Simulation time 59825446436 ps
CPU time 48.39 seconds
Started Jul 01 12:43:50 PM PDT 24
Finished Jul 01 12:44:39 PM PDT 24
Peak memory 199896 kb
Host smart-2e83522b-0795-41a3-8dfa-5ee5815a2511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740736205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1740736205
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3406915638
Short name T338
Test name
Test status
Simulation time 39017873 ps
CPU time 0.56 seconds
Started Jul 01 12:37:40 PM PDT 24
Finished Jul 01 12:37:42 PM PDT 24
Peak memory 195536 kb
Host smart-d6af8057-bc14-456d-bc37-1e2369438cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406915638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3406915638
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2779168162
Short name T62
Test name
Test status
Simulation time 12806843 ps
CPU time 0.59 seconds
Started Jul 01 10:43:22 AM PDT 24
Finished Jul 01 10:43:23 AM PDT 24
Peak memory 195796 kb
Host smart-b59cfdda-937f-4bf5-9e06-3e9567619f6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779168162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2779168162
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3979946567
Short name T247
Test name
Test status
Simulation time 117200050795 ps
CPU time 14.95 seconds
Started Jul 01 12:40:07 PM PDT 24
Finished Jul 01 12:40:23 PM PDT 24
Peak memory 200004 kb
Host smart-fa523736-9e2a-4f14-9e76-249ae032ef7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979946567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3979946567
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3667240715
Short name T125
Test name
Test status
Simulation time 448269722092 ps
CPU time 549.42 seconds
Started Jul 01 12:39:19 PM PDT 24
Finished Jul 01 12:48:29 PM PDT 24
Peak memory 216576 kb
Host smart-7f375f3f-3a7b-44a3-ac2a-f455865eb301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667240715 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3667240715
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.306346493
Short name T20
Test name
Test status
Simulation time 49162602476 ps
CPU time 1632.53 seconds
Started Jul 01 12:42:57 PM PDT 24
Finished Jul 01 01:10:10 PM PDT 24
Peak memory 211528 kb
Host smart-ffb42800-d8ee-4fdb-a421-f2bf1ff66dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306346493 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.306346493
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.47002933
Short name T641
Test name
Test status
Simulation time 396032032721 ps
CPU time 1332.31 seconds
Started Jul 01 12:40:10 PM PDT 24
Finished Jul 01 01:02:23 PM PDT 24
Peak memory 216516 kb
Host smart-4739f1be-8d39-4691-a6cc-67daeba783ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47002933 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.47002933
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1338246906
Short name T188
Test name
Test status
Simulation time 163093049821 ps
CPU time 222.27 seconds
Started Jul 01 12:44:42 PM PDT 24
Finished Jul 01 12:48:25 PM PDT 24
Peak memory 199828 kb
Host smart-0b57909b-7ead-4912-a461-2c14b843645a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338246906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1338246906
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2411898186
Short name T108
Test name
Test status
Simulation time 153269749517 ps
CPU time 1607.5 seconds
Started Jul 01 12:41:22 PM PDT 24
Finished Jul 01 01:08:11 PM PDT 24
Peak memory 216508 kb
Host smart-fa30f0e5-17fe-4deb-9440-78d2d1cc1a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411898186 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2411898186
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.551201404
Short name T146
Test name
Test status
Simulation time 201110791662 ps
CPU time 87.69 seconds
Started Jul 01 12:45:13 PM PDT 24
Finished Jul 01 12:46:42 PM PDT 24
Peak memory 199944 kb
Host smart-17590e12-c36f-4a51-b18f-2b9479bd4bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551201404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.551201404
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1655607430
Short name T196
Test name
Test status
Simulation time 118801875085 ps
CPU time 76.1 seconds
Started Jul 01 12:43:16 PM PDT 24
Finished Jul 01 12:44:33 PM PDT 24
Peak memory 199848 kb
Host smart-62ef8eea-66e5-477c-9e5a-54acd40b2f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655607430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1655607430
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2135909328
Short name T306
Test name
Test status
Simulation time 62573309367 ps
CPU time 122.41 seconds
Started Jul 01 12:44:48 PM PDT 24
Finished Jul 01 12:46:52 PM PDT 24
Peak memory 200020 kb
Host smart-5732bdd3-13db-4ed1-b056-b98e7c1d66f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135909328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2135909328
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4066526462
Short name T1184
Test name
Test status
Simulation time 584938366 ps
CPU time 1.25 seconds
Started Jul 01 10:43:32 AM PDT 24
Finished Jul 01 10:43:35 AM PDT 24
Peak memory 199684 kb
Host smart-df51abd1-fbb4-4873-8e17-9253ea3e3290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066526462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4066526462
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1663168215
Short name T180
Test name
Test status
Simulation time 26853797202 ps
CPU time 20.61 seconds
Started Jul 01 12:43:59 PM PDT 24
Finished Jul 01 12:44:20 PM PDT 24
Peak memory 199948 kb
Host smart-829a4495-d805-4d40-afda-9f8f3d613db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663168215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1663168215
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2689595886
Short name T232
Test name
Test status
Simulation time 39628617794 ps
CPU time 14.32 seconds
Started Jul 01 12:44:52 PM PDT 24
Finished Jul 01 12:45:07 PM PDT 24
Peak memory 199880 kb
Host smart-04e8526c-8de5-407a-9510-e219f7b99d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689595886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2689595886
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1563439622
Short name T353
Test name
Test status
Simulation time 229493346284 ps
CPU time 333.2 seconds
Started Jul 01 12:38:49 PM PDT 24
Finished Jul 01 12:44:23 PM PDT 24
Peak memory 199672 kb
Host smart-f62d82a9-f96c-4ad2-937f-131a77aa0965
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563439622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1563439622
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2014901789
Short name T218
Test name
Test status
Simulation time 85936804441 ps
CPU time 26.25 seconds
Started Jul 01 12:45:58 PM PDT 24
Finished Jul 01 12:46:27 PM PDT 24
Peak memory 199876 kb
Host smart-66594fb2-b212-4ee0-b94d-b5b2062c14b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014901789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2014901789
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.23594649
Short name T156
Test name
Test status
Simulation time 142082633274 ps
CPU time 77.93 seconds
Started Jul 01 12:35:32 PM PDT 24
Finished Jul 01 12:36:50 PM PDT 24
Peak memory 199960 kb
Host smart-1aff6c8d-7018-4860-a4b0-d7e14c040fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23594649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.23594649
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2943877155
Short name T179
Test name
Test status
Simulation time 150992599922 ps
CPU time 75.42 seconds
Started Jul 01 12:45:18 PM PDT 24
Finished Jul 01 12:46:35 PM PDT 24
Peak memory 200020 kb
Host smart-750dd78d-d926-4734-b5e9-3fcd4df457bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943877155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2943877155
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.1149909524
Short name T174
Test name
Test status
Simulation time 360419949629 ps
CPU time 679.3 seconds
Started Jul 01 12:40:09 PM PDT 24
Finished Jul 01 12:51:30 PM PDT 24
Peak memory 199920 kb
Host smart-4a25e873-0e7e-46bb-a18b-5efb1111a861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149909524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1149909524
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1789604734
Short name T206
Test name
Test status
Simulation time 45468266313 ps
CPU time 67.56 seconds
Started Jul 01 12:42:56 PM PDT 24
Finished Jul 01 12:44:04 PM PDT 24
Peak memory 199920 kb
Host smart-d0a0bbaa-9086-434d-aa9a-29b6c9c27edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789604734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1789604734
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.329886987
Short name T190
Test name
Test status
Simulation time 59264012661 ps
CPU time 95.93 seconds
Started Jul 01 12:44:54 PM PDT 24
Finished Jul 01 12:46:30 PM PDT 24
Peak memory 199980 kb
Host smart-5701c8d1-7e4d-476b-bc8c-5033b74e8973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329886987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.329886987
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1342165932
Short name T168
Test name
Test status
Simulation time 9011092889 ps
CPU time 16.41 seconds
Started Jul 01 12:45:40 PM PDT 24
Finished Jul 01 12:45:57 PM PDT 24
Peak memory 199680 kb
Host smart-14988551-103e-4d39-a34f-e0c186eed3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342165932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1342165932
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.82045280
Short name T630
Test name
Test status
Simulation time 36323614591 ps
CPU time 773.63 seconds
Started Jul 01 12:39:04 PM PDT 24
Finished Jul 01 12:51:58 PM PDT 24
Peak memory 216460 kb
Host smart-0da252c6-a48b-440a-a4ef-8f501961e446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82045280 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.82045280
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.95831492
Short name T186
Test name
Test status
Simulation time 26187851403 ps
CPU time 39.49 seconds
Started Jul 01 12:44:34 PM PDT 24
Finished Jul 01 12:45:15 PM PDT 24
Peak memory 199920 kb
Host smart-bc2983aa-1536-45d1-8db5-4b7567f7119f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95831492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.95831492
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3237359778
Short name T214
Test name
Test status
Simulation time 87896759117 ps
CPU time 61.22 seconds
Started Jul 01 12:45:18 PM PDT 24
Finished Jul 01 12:46:20 PM PDT 24
Peak memory 199944 kb
Host smart-e716a1d4-ee1e-4720-925c-6490f08c2d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237359778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3237359778
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.815673557
Short name T129
Test name
Test status
Simulation time 492956262713 ps
CPU time 115.93 seconds
Started Jul 01 12:38:47 PM PDT 24
Finished Jul 01 12:40:44 PM PDT 24
Peak memory 199904 kb
Host smart-aa916153-04bf-4cfd-8416-4b46bee03bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815673557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.815673557
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2248713565
Short name T238
Test name
Test status
Simulation time 388957142700 ps
CPU time 354.24 seconds
Started Jul 01 12:38:58 PM PDT 24
Finished Jul 01 12:44:54 PM PDT 24
Peak memory 216472 kb
Host smart-791e7a55-fab4-49ef-9f82-ca1afe380e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248713565 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2248713565
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3130594589
Short name T193
Test name
Test status
Simulation time 73475234180 ps
CPU time 129.39 seconds
Started Jul 01 12:45:40 PM PDT 24
Finished Jul 01 12:47:50 PM PDT 24
Peak memory 199936 kb
Host smart-93fe0c04-7bed-4b73-996f-e37042dc618a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130594589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3130594589
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3044553622
Short name T157
Test name
Test status
Simulation time 106316352856 ps
CPU time 138.97 seconds
Started Jul 01 12:45:51 PM PDT 24
Finished Jul 01 12:48:11 PM PDT 24
Peak memory 199992 kb
Host smart-89ce23b5-b2cf-4562-9fda-ce0b095685b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044553622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3044553622
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.562950753
Short name T211
Test name
Test status
Simulation time 110357862363 ps
CPU time 30.03 seconds
Started Jul 01 12:42:21 PM PDT 24
Finished Jul 01 12:42:52 PM PDT 24
Peak memory 200152 kb
Host smart-8333f630-b1f2-49f8-aa6e-47790a276e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562950753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.562950753
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.410492453
Short name T312
Test name
Test status
Simulation time 154947714123 ps
CPU time 1040.49 seconds
Started Jul 01 12:43:15 PM PDT 24
Finished Jul 01 01:00:36 PM PDT 24
Peak memory 224632 kb
Host smart-0a4fb10c-0771-43c3-aaec-7d091ae1f1a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410492453 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.410492453
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3136013909
Short name T45
Test name
Test status
Simulation time 125508782945 ps
CPU time 108.07 seconds
Started Jul 01 12:35:22 PM PDT 24
Finished Jul 01 12:37:11 PM PDT 24
Peak memory 199964 kb
Host smart-63aa8df2-5ea6-43a0-a1d1-59c7502b0596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136013909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3136013909
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2798857844
Short name T777
Test name
Test status
Simulation time 490187042906 ps
CPU time 41.65 seconds
Started Jul 01 12:43:46 PM PDT 24
Finished Jul 01 12:44:28 PM PDT 24
Peak memory 199928 kb
Host smart-95a54584-1b33-4312-bd8c-0e323d876616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798857844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2798857844
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.4122096626
Short name T701
Test name
Test status
Simulation time 12404367320 ps
CPU time 21.31 seconds
Started Jul 01 12:43:51 PM PDT 24
Finished Jul 01 12:44:12 PM PDT 24
Peak memory 199968 kb
Host smart-1e760aad-6ed6-4872-ba09-fc0c30a861a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122096626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4122096626
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.807342008
Short name T165
Test name
Test status
Simulation time 110848376772 ps
CPU time 60.11 seconds
Started Jul 01 12:43:50 PM PDT 24
Finished Jul 01 12:44:51 PM PDT 24
Peak memory 199956 kb
Host smart-333b675a-5e86-4daf-bce8-18c4dfab2f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807342008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.807342008
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.653963189
Short name T239
Test name
Test status
Simulation time 26160858887 ps
CPU time 105.49 seconds
Started Jul 01 12:44:01 PM PDT 24
Finished Jul 01 12:45:47 PM PDT 24
Peak memory 199876 kb
Host smart-0a598a8a-5352-4ac9-b2db-cba8a6438bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653963189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.653963189
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.166061091
Short name T243
Test name
Test status
Simulation time 81094143030 ps
CPU time 97.92 seconds
Started Jul 01 12:43:58 PM PDT 24
Finished Jul 01 12:45:37 PM PDT 24
Peak memory 200008 kb
Host smart-e5ad7f1b-b425-45c8-a480-563e1e97235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166061091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.166061091
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1878441183
Short name T176
Test name
Test status
Simulation time 35138863344 ps
CPU time 13.55 seconds
Started Jul 01 12:44:12 PM PDT 24
Finished Jul 01 12:44:26 PM PDT 24
Peak memory 199932 kb
Host smart-14665909-f832-4165-b27a-aa0b42b94897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878441183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1878441183
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.233284894
Short name T227
Test name
Test status
Simulation time 62555550952 ps
CPU time 96.3 seconds
Started Jul 01 12:44:22 PM PDT 24
Finished Jul 01 12:45:59 PM PDT 24
Peak memory 199996 kb
Host smart-fdb70147-5475-4e74-94f9-cda9e55f91b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233284894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.233284894
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.877442284
Short name T242
Test name
Test status
Simulation time 56685353168 ps
CPU time 186.79 seconds
Started Jul 01 12:44:27 PM PDT 24
Finished Jul 01 12:47:34 PM PDT 24
Peak memory 199940 kb
Host smart-9d24a621-ad73-409c-b41c-2995a42caa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877442284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.877442284
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1447790394
Short name T219
Test name
Test status
Simulation time 80585858527 ps
CPU time 61.22 seconds
Started Jul 01 12:44:35 PM PDT 24
Finished Jul 01 12:45:37 PM PDT 24
Peak memory 199908 kb
Host smart-4f300fce-3861-4f49-b148-d9c7232d29a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447790394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1447790394
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2519194667
Short name T216
Test name
Test status
Simulation time 20106685416 ps
CPU time 30.02 seconds
Started Jul 01 12:44:37 PM PDT 24
Finished Jul 01 12:45:08 PM PDT 24
Peak memory 199968 kb
Host smart-7a5f3115-e2ef-448f-8e4d-ae89acddb0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519194667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2519194667
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.68361433
Short name T235
Test name
Test status
Simulation time 195314952030 ps
CPU time 73.93 seconds
Started Jul 01 12:44:48 PM PDT 24
Finished Jul 01 12:46:03 PM PDT 24
Peak memory 199932 kb
Host smart-a71ca7d3-f201-4f82-843d-0e58eb61b946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68361433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.68361433
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2080797019
Short name T209
Test name
Test status
Simulation time 31793255821 ps
CPU time 29.41 seconds
Started Jul 01 12:45:03 PM PDT 24
Finished Jul 01 12:45:33 PM PDT 24
Peak memory 199960 kb
Host smart-ff1d99b5-14ec-42d9-90db-a58c832a37d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080797019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2080797019
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all.2626148847
Short name T139
Test name
Test status
Simulation time 219594639265 ps
CPU time 106.67 seconds
Started Jul 01 12:35:46 PM PDT 24
Finished Jul 01 12:37:33 PM PDT 24
Peak memory 199912 kb
Host smart-a80ee5ed-1ca0-488f-a955-87e95820bb61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626148847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2626148847
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.532169416
Short name T222
Test name
Test status
Simulation time 114675372071 ps
CPU time 108.75 seconds
Started Jul 01 12:41:55 PM PDT 24
Finished Jul 01 12:43:45 PM PDT 24
Peak memory 200008 kb
Host smart-f514c3e1-5b69-4bef-a67c-49f6303755cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532169416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.532169416
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1339960923
Short name T223
Test name
Test status
Simulation time 106141090057 ps
CPU time 165.8 seconds
Started Jul 01 12:35:54 PM PDT 24
Finished Jul 01 12:38:40 PM PDT 24
Peak memory 199936 kb
Host smart-675e7d38-2a18-4dd3-9df1-0c6f773fd66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339960923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1339960923
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.149198122
Short name T233
Test name
Test status
Simulation time 71984508595 ps
CPU time 119.6 seconds
Started Jul 01 12:43:01 PM PDT 24
Finished Jul 01 12:45:01 PM PDT 24
Peak memory 199936 kb
Host smart-74c005cb-687d-45a3-baf6-e120b497df93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149198122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.149198122
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2264017450
Short name T210
Test name
Test status
Simulation time 78391333035 ps
CPU time 64.45 seconds
Started Jul 01 12:43:16 PM PDT 24
Finished Jul 01 12:44:22 PM PDT 24
Peak memory 199948 kb
Host smart-55b24781-955c-418c-82a3-23eea990b70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264017450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2264017450
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.599476892
Short name T1182
Test name
Test status
Simulation time 48882821 ps
CPU time 0.78 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 196740 kb
Host smart-fa97d78c-502c-40b2-80ef-f5568b135076
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599476892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.599476892
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2680179432
Short name T1203
Test name
Test status
Simulation time 509815593 ps
CPU time 2.64 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 198260 kb
Host smart-0479de63-0e75-4e21-add4-3602b8cffa81
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680179432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2680179432
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.728515991
Short name T1188
Test name
Test status
Simulation time 37511214 ps
CPU time 0.61 seconds
Started Jul 01 10:42:54 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 195832 kb
Host smart-78b56c2e-cd8f-4523-b8f8-f171e15a1d7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728515991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.728515991
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2041962495
Short name T1112
Test name
Test status
Simulation time 17664128 ps
CPU time 0.97 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:42:59 AM PDT 24
Peak memory 200056 kb
Host smart-80101b1a-a4ef-4b66-9ed9-f83f058ebe24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041962495 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2041962495
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.843763223
Short name T1197
Test name
Test status
Simulation time 46666098 ps
CPU time 0.62 seconds
Started Jul 01 10:42:53 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 195936 kb
Host smart-139919e2-0a42-4255-be7d-993855771aae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843763223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.843763223
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.254626826
Short name T1236
Test name
Test status
Simulation time 33092544 ps
CPU time 0.57 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 194704 kb
Host smart-e0163489-fcfa-4ba8-a64c-cb7a36d0cc98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254626826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.254626826
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1957151922
Short name T87
Test name
Test status
Simulation time 14664317 ps
CPU time 0.68 seconds
Started Jul 01 10:42:58 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 197000 kb
Host smart-45b5dae6-0f15-49ef-8b97-23444da84189
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957151922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1957151922
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.791769574
Short name T1138
Test name
Test status
Simulation time 88220015 ps
CPU time 1.4 seconds
Started Jul 01 10:42:54 AM PDT 24
Finished Jul 01 10:42:56 AM PDT 24
Peak memory 200388 kb
Host smart-17a42684-d00d-4f95-8a41-190b88539996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791769574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.791769574
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2681959497
Short name T1135
Test name
Test status
Simulation time 70111288 ps
CPU time 1.3 seconds
Started Jul 01 10:42:54 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 199808 kb
Host smart-14c2b6c5-223d-4d7c-bf82-151cbb2ca02a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681959497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2681959497
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3861038026
Short name T1208
Test name
Test status
Simulation time 18304750 ps
CPU time 0.64 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 195380 kb
Host smart-8ab48072-edbb-45f2-a430-a9f1de9d7095
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861038026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3861038026
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3940235932
Short name T1118
Test name
Test status
Simulation time 142152697 ps
CPU time 1.43 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 198020 kb
Host smart-2178f09d-c041-42bd-819a-3afb049ecabb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940235932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3940235932
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2864646773
Short name T1140
Test name
Test status
Simulation time 12718700 ps
CPU time 0.58 seconds
Started Jul 01 10:44:30 AM PDT 24
Finished Jul 01 10:44:31 AM PDT 24
Peak memory 195676 kb
Host smart-ad1b5e49-37c6-4f0b-8d6b-1e6bce80e506
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864646773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2864646773
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2974282373
Short name T1103
Test name
Test status
Simulation time 31475795 ps
CPU time 1.41 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 200436 kb
Host smart-bb4f1584-7b65-42ef-b9cf-67d69672173c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974282373 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2974282373
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.22647447
Short name T75
Test name
Test status
Simulation time 25941999 ps
CPU time 0.63 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:06 AM PDT 24
Peak memory 195796 kb
Host smart-f858e753-ef5d-45ce-ba8c-74fedef723a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22647447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.22647447
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2318359797
Short name T1194
Test name
Test status
Simulation time 43617958 ps
CPU time 0.65 seconds
Started Jul 01 10:43:14 AM PDT 24
Finished Jul 01 10:43:15 AM PDT 24
Peak memory 194780 kb
Host smart-badbdcb6-ef8a-426d-bb35-cafeee2d15e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318359797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2318359797
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1755761466
Short name T1231
Test name
Test status
Simulation time 17806707 ps
CPU time 0.7 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:09 AM PDT 24
Peak memory 197228 kb
Host smart-1fe24de2-84cc-4c33-8d73-412ff1ed8373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755761466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1755761466
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3816742956
Short name T1120
Test name
Test status
Simulation time 45148890 ps
CPU time 1.18 seconds
Started Jul 01 10:42:55 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 200292 kb
Host smart-e2419655-818b-473d-9126-257245d5c305
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816742956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3816742956
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.250947026
Short name T1195
Test name
Test status
Simulation time 168038664 ps
CPU time 1.37 seconds
Started Jul 01 10:42:55 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 199720 kb
Host smart-5fe42306-0910-497c-91ff-f50c79c7e83a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250947026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.250947026
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3008249004
Short name T1116
Test name
Test status
Simulation time 22412774 ps
CPU time 1.04 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 200212 kb
Host smart-18e6500b-34e5-40bc-a246-b98bdc9125b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008249004 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3008249004
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2971078521
Short name T1168
Test name
Test status
Simulation time 36351972 ps
CPU time 0.56 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 195804 kb
Host smart-5607d712-20ee-434d-84c5-affccd32d079
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971078521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2971078521
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1653910995
Short name T1232
Test name
Test status
Simulation time 27490543 ps
CPU time 0.56 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 194776 kb
Host smart-94b939a8-e85e-4cba-84a3-5842b8b2b8c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653910995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1653910995
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2360197417
Short name T1187
Test name
Test status
Simulation time 20301606 ps
CPU time 0.64 seconds
Started Jul 01 10:43:07 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 196004 kb
Host smart-fcf8e96f-5b82-4154-bb57-35ac155e6e5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360197417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2360197417
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.699035623
Short name T1144
Test name
Test status
Simulation time 320057618 ps
CPU time 1.64 seconds
Started Jul 01 10:43:45 AM PDT 24
Finished Jul 01 10:43:47 AM PDT 24
Peak memory 200312 kb
Host smart-89df1865-ffd3-46a7-8e5a-2d719f4f3402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699035623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.699035623
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3365309274
Short name T94
Test name
Test status
Simulation time 55107833 ps
CPU time 1 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 199444 kb
Host smart-956b7d46-850b-4784-b11d-0e7e2700d5e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365309274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3365309274
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3022045707
Short name T1115
Test name
Test status
Simulation time 70458588 ps
CPU time 0.78 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 199876 kb
Host smart-73cb8706-568d-4a1a-ab43-4b05dc4ec078
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022045707 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3022045707
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2478944047
Short name T76
Test name
Test status
Simulation time 80099154 ps
CPU time 0.56 seconds
Started Jul 01 10:43:52 AM PDT 24
Finished Jul 01 10:43:53 AM PDT 24
Peak memory 195784 kb
Host smart-05ba46e5-b231-4817-be64-82a28388de78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478944047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2478944047
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1536337696
Short name T1152
Test name
Test status
Simulation time 27519710 ps
CPU time 0.63 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:09 AM PDT 24
Peak memory 194820 kb
Host smart-45968bcd-cc1c-425e-8fee-ec3151c80111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536337696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1536337696
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1825643946
Short name T1233
Test name
Test status
Simulation time 41833462 ps
CPU time 0.64 seconds
Started Jul 01 10:43:08 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 195784 kb
Host smart-b1b88a2a-a498-4c61-a6a5-e9a099c98568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825643946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1825643946
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.972155201
Short name T1125
Test name
Test status
Simulation time 36397814 ps
CPU time 1.8 seconds
Started Jul 01 10:43:35 AM PDT 24
Finished Jul 01 10:43:37 AM PDT 24
Peak memory 200416 kb
Host smart-e2aaa796-b03c-497e-991a-0b78a2bf351c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972155201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.972155201
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3827785126
Short name T1217
Test name
Test status
Simulation time 267234419 ps
CPU time 0.95 seconds
Started Jul 01 10:43:35 AM PDT 24
Finished Jul 01 10:43:37 AM PDT 24
Peak memory 199168 kb
Host smart-3ab79333-2493-4b92-94f3-1115cae56019
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827785126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3827785126
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2429338443
Short name T1113
Test name
Test status
Simulation time 150380060 ps
CPU time 0.67 seconds
Started Jul 01 10:43:10 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 198088 kb
Host smart-de7d4a15-0e31-4c1b-a505-141abf652a9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429338443 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2429338443
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.389114652
Short name T1201
Test name
Test status
Simulation time 14713786 ps
CPU time 0.64 seconds
Started Jul 01 10:43:08 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 195880 kb
Host smart-778246a5-9111-4242-8820-3868d267a49f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389114652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.389114652
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.143327223
Short name T1228
Test name
Test status
Simulation time 15959348 ps
CPU time 0.59 seconds
Started Jul 01 10:43:21 AM PDT 24
Finished Jul 01 10:43:22 AM PDT 24
Peak memory 194780 kb
Host smart-57e58e3d-6368-420a-b145-e852ffa9bd28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143327223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.143327223
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3680415073
Short name T1191
Test name
Test status
Simulation time 64719080 ps
CPU time 0.64 seconds
Started Jul 01 10:43:09 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 195848 kb
Host smart-e4ec7c79-444b-445c-a476-8a983820d258
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680415073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3680415073
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.740947041
Short name T1157
Test name
Test status
Simulation time 81377280 ps
CPU time 1.14 seconds
Started Jul 01 10:43:22 AM PDT 24
Finished Jul 01 10:43:23 AM PDT 24
Peak memory 200380 kb
Host smart-09a6bc03-5954-4515-9e03-36b1b94b7505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740947041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.740947041
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3279324977
Short name T1166
Test name
Test status
Simulation time 39895900 ps
CPU time 0.88 seconds
Started Jul 01 10:43:17 AM PDT 24
Finished Jul 01 10:43:19 AM PDT 24
Peak memory 199152 kb
Host smart-2ae90794-1778-4551-83ed-aae65a566f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279324977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3279324977
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3027486245
Short name T1183
Test name
Test status
Simulation time 64440444 ps
CPU time 0.72 seconds
Started Jul 01 10:43:10 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 198628 kb
Host smart-5b73a55c-cfe1-4ffb-b746-2df5a8b27b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027486245 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3027486245
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.819590250
Short name T78
Test name
Test status
Simulation time 95362659 ps
CPU time 0.67 seconds
Started Jul 01 10:43:08 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 195936 kb
Host smart-d325b497-41a0-451e-9c36-efefcfbc1b7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819590250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.819590250
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.314836896
Short name T1136
Test name
Test status
Simulation time 42137293 ps
CPU time 0.56 seconds
Started Jul 01 10:43:32 AM PDT 24
Finished Jul 01 10:43:34 AM PDT 24
Peak memory 194704 kb
Host smart-0bd90c51-8ee1-4f67-9b9f-9b1107e51135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314836896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.314836896
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3326614051
Short name T84
Test name
Test status
Simulation time 42087165 ps
CPU time 0.63 seconds
Started Jul 01 10:43:07 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 195856 kb
Host smart-8faac886-2a50-43d1-9f36-4cf8605f395e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326614051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3326614051
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.207046692
Short name T1185
Test name
Test status
Simulation time 32679917 ps
CPU time 1.58 seconds
Started Jul 01 10:43:08 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 200388 kb
Host smart-06e0af62-7c3d-4a1d-a96d-97900122d5b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207046692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.207046692
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.4216487034
Short name T93
Test name
Test status
Simulation time 90254768 ps
CPU time 0.92 seconds
Started Jul 01 10:43:10 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 198968 kb
Host smart-13d530ef-0966-455c-b2d4-110015c5278d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216487034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.4216487034
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2529558598
Short name T1227
Test name
Test status
Simulation time 28726627 ps
CPU time 0.88 seconds
Started Jul 01 10:43:08 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 200148 kb
Host smart-e96c21f0-0cc0-420c-9725-494eee5de40b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529558598 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2529558598
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1459657770
Short name T80
Test name
Test status
Simulation time 58011197 ps
CPU time 0.61 seconds
Started Jul 01 10:43:33 AM PDT 24
Finished Jul 01 10:43:35 AM PDT 24
Peak memory 195800 kb
Host smart-5ebba455-6ec3-43e3-a9b2-2e9024de5911
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459657770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1459657770
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.124751834
Short name T1223
Test name
Test status
Simulation time 31308425 ps
CPU time 0.61 seconds
Started Jul 01 10:43:34 AM PDT 24
Finished Jul 01 10:43:36 AM PDT 24
Peak memory 194792 kb
Host smart-471f9cd3-dab6-4960-b5c5-9219d98899d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124751834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.124751834
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2248033908
Short name T1156
Test name
Test status
Simulation time 59747830 ps
CPU time 0.67 seconds
Started Jul 01 10:43:28 AM PDT 24
Finished Jul 01 10:43:29 AM PDT 24
Peak memory 195868 kb
Host smart-8dc4a328-23d0-4ebd-9516-58b1ed8a9930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248033908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2248033908
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3362543233
Short name T1204
Test name
Test status
Simulation time 69203516 ps
CPU time 1.53 seconds
Started Jul 01 10:43:35 AM PDT 24
Finished Jul 01 10:43:37 AM PDT 24
Peak memory 200404 kb
Host smart-d287002a-0202-4fb7-a34d-a4741910f83b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362543233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3362543233
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3533428944
Short name T1142
Test name
Test status
Simulation time 62736716 ps
CPU time 0.94 seconds
Started Jul 01 10:43:44 AM PDT 24
Finished Jul 01 10:43:45 AM PDT 24
Peak memory 200140 kb
Host smart-fa28a068-745f-4a28-ba31-34d8651ea010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533428944 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3533428944
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2049659446
Short name T60
Test name
Test status
Simulation time 15259392 ps
CPU time 0.63 seconds
Started Jul 01 10:43:30 AM PDT 24
Finished Jul 01 10:43:34 AM PDT 24
Peak memory 196212 kb
Host smart-41d64cdf-c87a-4f1f-ae2b-5707e5b70c7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049659446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2049659446
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2445610233
Short name T1133
Test name
Test status
Simulation time 77759610 ps
CPU time 0.61 seconds
Started Jul 01 10:43:10 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 194792 kb
Host smart-13b48692-cefd-4ec8-8d57-fd2ac079b7d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445610233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2445610233
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3873074260
Short name T1149
Test name
Test status
Simulation time 69661657 ps
CPU time 0.66 seconds
Started Jul 01 10:43:41 AM PDT 24
Finished Jul 01 10:43:42 AM PDT 24
Peak memory 196036 kb
Host smart-59dda37a-6e15-4411-b83e-a3725b26d85b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873074260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3873074260
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3559304883
Short name T1213
Test name
Test status
Simulation time 384294016 ps
CPU time 1.84 seconds
Started Jul 01 10:43:17 AM PDT 24
Finished Jul 01 10:43:19 AM PDT 24
Peak memory 200372 kb
Host smart-95be4145-00c2-494b-af21-6a547363fa5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559304883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3559304883
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3060502237
Short name T1172
Test name
Test status
Simulation time 106557275 ps
CPU time 1.34 seconds
Started Jul 01 10:43:34 AM PDT 24
Finished Jul 01 10:43:37 AM PDT 24
Peak memory 199528 kb
Host smart-17f90159-8099-40b8-9285-aca8b211797d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060502237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3060502237
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1609292271
Short name T1165
Test name
Test status
Simulation time 49108788 ps
CPU time 0.66 seconds
Started Jul 01 10:43:39 AM PDT 24
Finished Jul 01 10:43:40 AM PDT 24
Peak memory 198768 kb
Host smart-a2dc18c3-8a42-4343-9bc4-e00bd0778b83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609292271 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1609292271
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2289828817
Short name T1158
Test name
Test status
Simulation time 34218007 ps
CPU time 0.63 seconds
Started Jul 01 10:43:28 AM PDT 24
Finished Jul 01 10:43:29 AM PDT 24
Peak memory 195912 kb
Host smart-c6bdccb1-9265-4765-8d1d-a48e9db94be9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289828817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2289828817
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3181186685
Short name T1130
Test name
Test status
Simulation time 13283952 ps
CPU time 0.57 seconds
Started Jul 01 10:43:35 AM PDT 24
Finished Jul 01 10:43:37 AM PDT 24
Peak memory 194688 kb
Host smart-09160b33-668e-4fe2-9a2d-09da6d5d5561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181186685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3181186685
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1477403581
Short name T81
Test name
Test status
Simulation time 65395742 ps
CPU time 0.65 seconds
Started Jul 01 10:43:41 AM PDT 24
Finished Jul 01 10:43:43 AM PDT 24
Peak memory 194952 kb
Host smart-01ecdf2e-53de-4f22-84d6-2f04fafd94cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477403581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1477403581
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1252085403
Short name T1121
Test name
Test status
Simulation time 104905293 ps
CPU time 1.95 seconds
Started Jul 01 10:43:15 AM PDT 24
Finished Jul 01 10:43:18 AM PDT 24
Peak memory 200404 kb
Host smart-28b7fb24-dc4a-4a96-b4c7-e32d1beabb6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252085403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1252085403
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2768945608
Short name T95
Test name
Test status
Simulation time 88020175 ps
CPU time 1.31 seconds
Started Jul 01 10:43:27 AM PDT 24
Finished Jul 01 10:43:28 AM PDT 24
Peak memory 199456 kb
Host smart-ade0bc48-9200-412a-9da0-13d52d87423a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768945608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2768945608
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.244704113
Short name T1150
Test name
Test status
Simulation time 113586023 ps
CPU time 1.36 seconds
Started Jul 01 10:43:32 AM PDT 24
Finished Jul 01 10:43:34 AM PDT 24
Peak memory 200468 kb
Host smart-005534ef-00bb-46f0-8da9-3a715648a6e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244704113 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.244704113
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.985005511
Short name T1137
Test name
Test status
Simulation time 14488856 ps
CPU time 0.62 seconds
Started Jul 01 10:43:16 AM PDT 24
Finished Jul 01 10:43:17 AM PDT 24
Peak memory 194776 kb
Host smart-f10f8c0b-c07b-4797-9fe7-d7e4802b3acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985005511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.985005511
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.580899372
Short name T1163
Test name
Test status
Simulation time 267318894 ps
CPU time 0.72 seconds
Started Jul 01 10:43:13 AM PDT 24
Finished Jul 01 10:43:15 AM PDT 24
Peak memory 196092 kb
Host smart-7417f9cd-c33e-4eea-b81c-00c25418fdc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580899372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.580899372
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2708247763
Short name T1221
Test name
Test status
Simulation time 118442696 ps
CPU time 1.68 seconds
Started Jul 01 10:43:14 AM PDT 24
Finished Jul 01 10:43:16 AM PDT 24
Peak memory 200336 kb
Host smart-75f4ea13-501e-46a7-84af-285d392f621f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708247763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2708247763
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2933086316
Short name T92
Test name
Test status
Simulation time 83886291 ps
CPU time 1.53 seconds
Started Jul 01 10:43:34 AM PDT 24
Finished Jul 01 10:43:37 AM PDT 24
Peak memory 200344 kb
Host smart-34c0cb32-796c-4516-aab2-79f3f30e55a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933086316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2933086316
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1740892987
Short name T1226
Test name
Test status
Simulation time 22119541 ps
CPU time 0.92 seconds
Started Jul 01 10:43:16 AM PDT 24
Finished Jul 01 10:43:18 AM PDT 24
Peak memory 200164 kb
Host smart-70087ba4-d432-4ee5-8d67-f45f38b840fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740892987 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1740892987
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.675816374
Short name T63
Test name
Test status
Simulation time 12502150 ps
CPU time 0.61 seconds
Started Jul 01 10:43:41 AM PDT 24
Finished Jul 01 10:43:42 AM PDT 24
Peak memory 195956 kb
Host smart-192c147e-1582-47af-b379-e9f96bbed6ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675816374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.675816374
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2544364922
Short name T1198
Test name
Test status
Simulation time 25994595 ps
CPU time 0.58 seconds
Started Jul 01 10:43:14 AM PDT 24
Finished Jul 01 10:43:15 AM PDT 24
Peak memory 194740 kb
Host smart-eb1a59cb-07de-476f-9a3c-c189ab8a9168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544364922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2544364922
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3646491345
Short name T82
Test name
Test status
Simulation time 174386790 ps
CPU time 0.79 seconds
Started Jul 01 10:43:32 AM PDT 24
Finished Jul 01 10:43:34 AM PDT 24
Peak memory 197784 kb
Host smart-a66eb21e-aee3-4c5f-bbbb-fd479be7e970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646491345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3646491345
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1966011917
Short name T1105
Test name
Test status
Simulation time 119621096 ps
CPU time 1.66 seconds
Started Jul 01 10:43:14 AM PDT 24
Finished Jul 01 10:43:16 AM PDT 24
Peak memory 200452 kb
Host smart-854d2761-b965-4f54-b893-0745c8bdbe12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966011917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1966011917
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3975062197
Short name T130
Test name
Test status
Simulation time 213346940 ps
CPU time 1.01 seconds
Started Jul 01 10:43:21 AM PDT 24
Finished Jul 01 10:43:23 AM PDT 24
Peak memory 199356 kb
Host smart-ebc6e0c4-d5e8-44e4-982a-5cbf3a84e341
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975062197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3975062197
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.157519762
Short name T1108
Test name
Test status
Simulation time 57477945 ps
CPU time 0.87 seconds
Started Jul 01 10:43:13 AM PDT 24
Finished Jul 01 10:43:15 AM PDT 24
Peak memory 200160 kb
Host smart-3d17abab-ee55-4771-810a-1ecbe1c4c97a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157519762 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.157519762
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2772223181
Short name T66
Test name
Test status
Simulation time 30434436 ps
CPU time 0.61 seconds
Started Jul 01 10:43:12 AM PDT 24
Finished Jul 01 10:43:14 AM PDT 24
Peak memory 195844 kb
Host smart-d7ced07f-7213-4c8d-b682-efba79c95136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772223181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2772223181
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.338407719
Short name T1102
Test name
Test status
Simulation time 72186831 ps
CPU time 0.62 seconds
Started Jul 01 10:43:17 AM PDT 24
Finished Jul 01 10:43:19 AM PDT 24
Peak memory 194756 kb
Host smart-d9649aa6-fd8f-41f3-95d5-23e5ac4f908c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338407719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.338407719
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1703351562
Short name T1196
Test name
Test status
Simulation time 18507887 ps
CPU time 0.74 seconds
Started Jul 01 10:43:23 AM PDT 24
Finished Jul 01 10:43:24 AM PDT 24
Peak memory 196400 kb
Host smart-86d713b4-8ebf-4350-bb1c-f79a57f805a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703351562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1703351562
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1508659871
Short name T1106
Test name
Test status
Simulation time 48983324 ps
CPU time 1.35 seconds
Started Jul 01 10:43:24 AM PDT 24
Finished Jul 01 10:43:25 AM PDT 24
Peak memory 200408 kb
Host smart-5951e782-c871-4eea-b078-a7c30ccea8f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508659871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1508659871
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.911668717
Short name T1177
Test name
Test status
Simulation time 461120120 ps
CPU time 1.3 seconds
Started Jul 01 10:43:28 AM PDT 24
Finished Jul 01 10:43:30 AM PDT 24
Peak memory 199724 kb
Host smart-2e2a62d2-2c90-46d7-89e0-9e591da0fcc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911668717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.911668717
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.592859017
Short name T1200
Test name
Test status
Simulation time 57572520 ps
CPU time 0.67 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 195696 kb
Host smart-6cb2f5de-ec94-41da-9747-904e77740102
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592859017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.592859017
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3036803975
Short name T77
Test name
Test status
Simulation time 706326966 ps
CPU time 1.57 seconds
Started Jul 01 10:43:21 AM PDT 24
Finished Jul 01 10:43:23 AM PDT 24
Peak memory 197720 kb
Host smart-a748417f-78ec-4a29-bea4-1d8d71f29ae7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036803975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3036803975
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1006090933
Short name T1131
Test name
Test status
Simulation time 44789297 ps
CPU time 0.61 seconds
Started Jul 01 10:43:09 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 195848 kb
Host smart-67c724e1-bc18-4d40-a500-6796bee0fbf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006090933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1006090933
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3112830286
Short name T1153
Test name
Test status
Simulation time 128990201 ps
CPU time 0.84 seconds
Started Jul 01 10:42:58 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 200084 kb
Host smart-6b86a6f8-208d-4418-abea-3fc772dd338c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112830286 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3112830286
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2284712156
Short name T1161
Test name
Test status
Simulation time 32805726 ps
CPU time 0.65 seconds
Started Jul 01 10:42:56 AM PDT 24
Finished Jul 01 10:42:59 AM PDT 24
Peak memory 196176 kb
Host smart-ab9f67a2-ea0a-41c4-8c63-20f7743c15f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284712156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2284712156
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.995086560
Short name T1186
Test name
Test status
Simulation time 27196540 ps
CPU time 0.59 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 194796 kb
Host smart-b20f877e-a940-47cb-8be7-198f90ba0154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995086560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.995086560
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1991531324
Short name T83
Test name
Test status
Simulation time 75578578 ps
CPU time 0.64 seconds
Started Jul 01 10:43:25 AM PDT 24
Finished Jul 01 10:43:27 AM PDT 24
Peak memory 196224 kb
Host smart-971ff687-42ce-48b5-82a3-4cc166c3c2dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991531324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1991531324
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2254707539
Short name T1224
Test name
Test status
Simulation time 60646595 ps
CPU time 1.47 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 200384 kb
Host smart-d5958419-3105-4ad8-9ff1-1a3e05eef413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254707539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2254707539
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3196854409
Short name T1189
Test name
Test status
Simulation time 75766277 ps
CPU time 1.23 seconds
Started Jul 01 10:42:55 AM PDT 24
Finished Jul 01 10:42:57 AM PDT 24
Peak memory 199576 kb
Host smart-eb231646-bc7a-400f-8394-a774b81d53ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196854409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3196854409
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1406640479
Short name T1171
Test name
Test status
Simulation time 21927066 ps
CPU time 0.58 seconds
Started Jul 01 10:43:15 AM PDT 24
Finished Jul 01 10:43:17 AM PDT 24
Peak memory 194720 kb
Host smart-1bb3b90f-1c7d-447f-bbde-e47085312dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406640479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1406640479
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.724854138
Short name T1146
Test name
Test status
Simulation time 14518790 ps
CPU time 0.6 seconds
Started Jul 01 10:43:25 AM PDT 24
Finished Jul 01 10:43:26 AM PDT 24
Peak memory 194736 kb
Host smart-e927d6f3-eb2c-4aea-927f-98678bccafca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724854138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.724854138
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3672188546
Short name T1179
Test name
Test status
Simulation time 52959312 ps
CPU time 0.58 seconds
Started Jul 01 10:43:20 AM PDT 24
Finished Jul 01 10:43:21 AM PDT 24
Peak memory 194772 kb
Host smart-0bc85e89-98cd-47d8-ac36-3f2a187aa908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672188546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3672188546
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.601798651
Short name T1220
Test name
Test status
Simulation time 32001539 ps
CPU time 0.58 seconds
Started Jul 01 10:43:29 AM PDT 24
Finished Jul 01 10:43:34 AM PDT 24
Peak memory 194796 kb
Host smart-825f5767-e9fb-47a0-9e2b-9d48db6968d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601798651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.601798651
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3786596370
Short name T1128
Test name
Test status
Simulation time 60021920 ps
CPU time 0.57 seconds
Started Jul 01 10:43:41 AM PDT 24
Finished Jul 01 10:43:42 AM PDT 24
Peak memory 194784 kb
Host smart-e0fbd47e-576b-4046-b4d2-06d4bc92221d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786596370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3786596370
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.303735052
Short name T1167
Test name
Test status
Simulation time 18285813 ps
CPU time 0.57 seconds
Started Jul 01 10:43:16 AM PDT 24
Finished Jul 01 10:43:17 AM PDT 24
Peak memory 194672 kb
Host smart-fd789deb-1ec0-48ac-b01b-b3639eb00fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303735052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.303735052
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2041292630
Short name T1234
Test name
Test status
Simulation time 29200527 ps
CPU time 0.58 seconds
Started Jul 01 10:43:29 AM PDT 24
Finished Jul 01 10:43:30 AM PDT 24
Peak memory 194808 kb
Host smart-01514e2d-d23c-4b80-b04a-eee22633700c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041292630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2041292630
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.339385416
Short name T1127
Test name
Test status
Simulation time 28202428 ps
CPU time 0.59 seconds
Started Jul 01 10:43:16 AM PDT 24
Finished Jul 01 10:43:17 AM PDT 24
Peak memory 194712 kb
Host smart-bee125d0-c43d-4b30-a55e-fbf69b091325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339385416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.339385416
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1365685956
Short name T1151
Test name
Test status
Simulation time 13530409 ps
CPU time 0.57 seconds
Started Jul 01 10:43:31 AM PDT 24
Finished Jul 01 10:43:32 AM PDT 24
Peak memory 194764 kb
Host smart-390c892f-4b4a-44ac-b4c5-2a1abe1d5072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365685956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1365685956
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1596682605
Short name T1222
Test name
Test status
Simulation time 42414767 ps
CPU time 0.57 seconds
Started Jul 01 10:43:46 AM PDT 24
Finished Jul 01 10:43:47 AM PDT 24
Peak memory 194828 kb
Host smart-98c1155c-0b26-42a7-8609-b2dae0011609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596682605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1596682605
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3600423515
Short name T1215
Test name
Test status
Simulation time 93027833 ps
CPU time 0.82 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 196476 kb
Host smart-9fbe0066-1aaf-4697-81ad-953c38ec2f7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600423515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3600423515
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3344494890
Short name T61
Test name
Test status
Simulation time 224021519 ps
CPU time 2.18 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 198156 kb
Host smart-c05cca9d-4630-4573-bbb0-c4f6d7db47ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344494890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3344494890
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2950119236
Short name T1109
Test name
Test status
Simulation time 55024084 ps
CPU time 0.62 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:42:59 AM PDT 24
Peak memory 195796 kb
Host smart-841a57dd-aaa1-4ac9-9dd0-07d28c6a76d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950119236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2950119236
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2223877387
Short name T1210
Test name
Test status
Simulation time 55181140 ps
CPU time 1 seconds
Started Jul 01 10:42:59 AM PDT 24
Finished Jul 01 10:43:02 AM PDT 24
Peak memory 200092 kb
Host smart-f874f7e1-cf1d-4dd5-b785-38adab7bbfa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223877387 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2223877387
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.549686368
Short name T65
Test name
Test status
Simulation time 19954537 ps
CPU time 0.61 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 195792 kb
Host smart-c150e1e3-2a94-4641-8fac-ef0f495af087
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549686368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.549686368
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.241172431
Short name T1225
Test name
Test status
Simulation time 12690703 ps
CPU time 0.54 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 194780 kb
Host smart-fe6eb5b8-e425-45f1-89b2-c2002c99fda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241172431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.241172431
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.520008046
Short name T88
Test name
Test status
Simulation time 41629440 ps
CPU time 0.65 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:06 AM PDT 24
Peak memory 195984 kb
Host smart-d5924c8b-894a-4d1c-9085-0adb8fbced49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520008046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.520008046
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2838117448
Short name T1190
Test name
Test status
Simulation time 65007904 ps
CPU time 1.52 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 200400 kb
Host smart-9e3f8e18-9d59-4de3-bf3e-ccad1be72b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838117448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2838117448
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1996195055
Short name T90
Test name
Test status
Simulation time 149368659 ps
CPU time 0.93 seconds
Started Jul 01 10:43:28 AM PDT 24
Finished Jul 01 10:43:29 AM PDT 24
Peak memory 199504 kb
Host smart-3aa54701-b063-4e07-b46e-b6b90c445f5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996195055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1996195055
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1039464960
Short name T1114
Test name
Test status
Simulation time 42965229 ps
CPU time 0.59 seconds
Started Jul 01 10:43:30 AM PDT 24
Finished Jul 01 10:43:31 AM PDT 24
Peak memory 194772 kb
Host smart-a8162a26-63a5-4a41-b2b3-1ae6633bd5da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039464960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1039464960
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3090439600
Short name T1176
Test name
Test status
Simulation time 41049965 ps
CPU time 0.58 seconds
Started Jul 01 10:43:27 AM PDT 24
Finished Jul 01 10:43:27 AM PDT 24
Peak memory 194788 kb
Host smart-de18de74-e5b3-4051-a7c7-e14a0b7234b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090439600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3090439600
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.426805558
Short name T1145
Test name
Test status
Simulation time 61152735 ps
CPU time 0.61 seconds
Started Jul 01 10:43:16 AM PDT 24
Finished Jul 01 10:43:17 AM PDT 24
Peak memory 194676 kb
Host smart-426e93f8-3944-46ff-86fb-873bd8e1c28d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426805558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.426805558
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.156680863
Short name T1126
Test name
Test status
Simulation time 12860467 ps
CPU time 0.59 seconds
Started Jul 01 10:43:26 AM PDT 24
Finished Jul 01 10:43:27 AM PDT 24
Peak memory 194776 kb
Host smart-82c958ee-06ba-4064-b75f-433551f942d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156680863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.156680863
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2730664023
Short name T1214
Test name
Test status
Simulation time 40244641 ps
CPU time 0.59 seconds
Started Jul 01 10:43:32 AM PDT 24
Finished Jul 01 10:43:34 AM PDT 24
Peak memory 194804 kb
Host smart-377ce869-c78d-4aba-ad3d-dfb5a6e07b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730664023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2730664023
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2814913187
Short name T1119
Test name
Test status
Simulation time 15755379 ps
CPU time 0.55 seconds
Started Jul 01 10:43:35 AM PDT 24
Finished Jul 01 10:43:36 AM PDT 24
Peak memory 194792 kb
Host smart-a00024a6-77b0-421f-9944-ebc3e2b2ae33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814913187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2814913187
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3800408707
Short name T1117
Test name
Test status
Simulation time 22855612 ps
CPU time 0.6 seconds
Started Jul 01 10:43:19 AM PDT 24
Finished Jul 01 10:43:20 AM PDT 24
Peak memory 194764 kb
Host smart-931f6418-419f-486a-b799-77c09571e833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800408707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3800408707
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1849648077
Short name T1143
Test name
Test status
Simulation time 56761925 ps
CPU time 0.58 seconds
Started Jul 01 10:43:17 AM PDT 24
Finished Jul 01 10:43:19 AM PDT 24
Peak memory 194752 kb
Host smart-db5cd380-3b74-4981-830a-f7335ac4c7c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849648077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1849648077
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1730094832
Short name T1218
Test name
Test status
Simulation time 14406496 ps
CPU time 0.58 seconds
Started Jul 01 10:43:42 AM PDT 24
Finished Jul 01 10:43:44 AM PDT 24
Peak memory 194776 kb
Host smart-553bf0eb-5988-4fe7-973e-bc3034e38f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730094832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1730094832
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1085629962
Short name T1235
Test name
Test status
Simulation time 19465678 ps
CPU time 0.58 seconds
Started Jul 01 10:43:50 AM PDT 24
Finished Jul 01 10:43:51 AM PDT 24
Peak memory 194732 kb
Host smart-99910b70-1720-4e1f-8d7e-eac480830df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085629962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1085629962
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3514282436
Short name T1230
Test name
Test status
Simulation time 69810157 ps
CPU time 0.69 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:05 AM PDT 24
Peak memory 195696 kb
Host smart-11473245-b0f2-43d3-86b9-7b33ed207a8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514282436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3514282436
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1196233693
Short name T1124
Test name
Test status
Simulation time 114382344 ps
CPU time 1.67 seconds
Started Jul 01 10:43:01 AM PDT 24
Finished Jul 01 10:43:06 AM PDT 24
Peak memory 198272 kb
Host smart-2be9c889-7445-422e-86a2-9c79f06b961b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196233693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1196233693
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3434943175
Short name T1159
Test name
Test status
Simulation time 80519158 ps
CPU time 0.61 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 195772 kb
Host smart-06e9a1ed-8f44-4a49-85bc-8c0e290cb045
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434943175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3434943175
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2531682011
Short name T1139
Test name
Test status
Simulation time 69074175 ps
CPU time 0.74 seconds
Started Jul 01 10:43:40 AM PDT 24
Finished Jul 01 10:43:42 AM PDT 24
Peak memory 199296 kb
Host smart-b5930f05-0211-4db5-9205-c656084ee189
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531682011 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2531682011
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1721620567
Short name T64
Test name
Test status
Simulation time 23228293 ps
CPU time 0.62 seconds
Started Jul 01 10:43:43 AM PDT 24
Finished Jul 01 10:43:44 AM PDT 24
Peak memory 195824 kb
Host smart-455b04da-cc20-4c0e-9bb8-081037ff41b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721620567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1721620567
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2014898120
Short name T1219
Test name
Test status
Simulation time 13272451 ps
CPU time 0.57 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:09 AM PDT 24
Peak memory 194708 kb
Host smart-03a9e78d-a4ee-415d-918b-788c638e19b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014898120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2014898120
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1225594565
Short name T1164
Test name
Test status
Simulation time 15468064 ps
CPU time 0.64 seconds
Started Jul 01 10:43:17 AM PDT 24
Finished Jul 01 10:43:19 AM PDT 24
Peak memory 196020 kb
Host smart-df916cf1-d21f-4d94-82e6-9875eafc6a7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225594565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1225594565
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1250874436
Short name T1206
Test name
Test status
Simulation time 76970591 ps
CPU time 1.93 seconds
Started Jul 01 10:42:59 AM PDT 24
Finished Jul 01 10:43:02 AM PDT 24
Peak memory 200388 kb
Host smart-900a2f70-ce70-47a1-88aa-3c039ff4079a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250874436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1250874436
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4037694888
Short name T1173
Test name
Test status
Simulation time 142625022 ps
CPU time 1.31 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 199652 kb
Host smart-7ecc8141-ca40-4566-82c9-0d5e715616b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037694888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4037694888
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.375368967
Short name T1123
Test name
Test status
Simulation time 26244465 ps
CPU time 0.58 seconds
Started Jul 01 10:43:26 AM PDT 24
Finished Jul 01 10:43:27 AM PDT 24
Peak memory 194688 kb
Host smart-e38cd2b5-c812-478f-a366-520b0939620e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375368967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.375368967
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1536793465
Short name T1193
Test name
Test status
Simulation time 15206754 ps
CPU time 0.59 seconds
Started Jul 01 10:43:49 AM PDT 24
Finished Jul 01 10:43:50 AM PDT 24
Peak memory 194752 kb
Host smart-2b9ca867-1acb-4bb8-bf06-f2b560839b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536793465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1536793465
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2527973197
Short name T1212
Test name
Test status
Simulation time 15613364 ps
CPU time 0.56 seconds
Started Jul 01 10:43:23 AM PDT 24
Finished Jul 01 10:43:24 AM PDT 24
Peak memory 194764 kb
Host smart-ccd9624e-181a-4fda-98a7-6162a03d71a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527973197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2527973197
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2964474016
Short name T1111
Test name
Test status
Simulation time 14787212 ps
CPU time 0.56 seconds
Started Jul 01 10:43:46 AM PDT 24
Finished Jul 01 10:43:47 AM PDT 24
Peak memory 194772 kb
Host smart-b4e9b622-5fee-4d2d-b541-4a233970e9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964474016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2964474016
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2575678581
Short name T1122
Test name
Test status
Simulation time 14718623 ps
CPU time 0.56 seconds
Started Jul 01 10:43:54 AM PDT 24
Finished Jul 01 10:43:56 AM PDT 24
Peak memory 194728 kb
Host smart-415c7594-152f-4af1-8ce9-72cf6d07c631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575678581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2575678581
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3564595226
Short name T1169
Test name
Test status
Simulation time 21184020 ps
CPU time 0.56 seconds
Started Jul 01 10:43:41 AM PDT 24
Finished Jul 01 10:43:43 AM PDT 24
Peak memory 194648 kb
Host smart-7c53f2df-5618-4cdd-98b2-3543ca81c9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564595226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3564595226
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3413336339
Short name T1134
Test name
Test status
Simulation time 41632990 ps
CPU time 0.58 seconds
Started Jul 01 10:43:40 AM PDT 24
Finished Jul 01 10:43:41 AM PDT 24
Peak memory 194668 kb
Host smart-076d1307-5134-4fff-9af8-a6358813c20f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413336339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3413336339
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3098467318
Short name T1237
Test name
Test status
Simulation time 13560557 ps
CPU time 0.62 seconds
Started Jul 01 10:43:54 AM PDT 24
Finished Jul 01 10:43:57 AM PDT 24
Peak memory 194796 kb
Host smart-589daf03-f945-4f5d-9276-2c87b3b6f3ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098467318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3098467318
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3474504358
Short name T1175
Test name
Test status
Simulation time 22851734 ps
CPU time 0.56 seconds
Started Jul 01 10:43:42 AM PDT 24
Finished Jul 01 10:43:43 AM PDT 24
Peak memory 194752 kb
Host smart-3f378eca-81e8-4c75-8297-f54140c34e23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474504358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3474504358
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3887741980
Short name T1154
Test name
Test status
Simulation time 37493502 ps
CPU time 0.58 seconds
Started Jul 01 10:43:54 AM PDT 24
Finished Jul 01 10:43:57 AM PDT 24
Peak memory 194804 kb
Host smart-36d53d37-0c1c-4978-b67b-eee58aed1be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887741980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3887741980
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.289029565
Short name T1110
Test name
Test status
Simulation time 129755088 ps
CPU time 0.73 seconds
Started Jul 01 10:43:04 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 198728 kb
Host smart-3465b411-de18-4a83-b1fe-9085e1239a17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289029565 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.289029565
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1596998282
Short name T1207
Test name
Test status
Simulation time 37260243 ps
CPU time 0.57 seconds
Started Jul 01 10:43:10 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 195804 kb
Host smart-bd578ae1-f4c1-40b4-bad3-f87e5433b503
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596998282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1596998282
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3904801999
Short name T1202
Test name
Test status
Simulation time 172504704 ps
CPU time 0.6 seconds
Started Jul 01 10:42:57 AM PDT 24
Finished Jul 01 10:42:59 AM PDT 24
Peak memory 194720 kb
Host smart-9b048eda-5198-4b89-a3bb-09b453847209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904801999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3904801999
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2825551570
Short name T85
Test name
Test status
Simulation time 26335390 ps
CPU time 0.65 seconds
Started Jul 01 10:42:59 AM PDT 24
Finished Jul 01 10:43:02 AM PDT 24
Peak memory 196160 kb
Host smart-779d796a-d99b-4682-a756-72f100615b6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825551570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2825551570
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.817107142
Short name T1229
Test name
Test status
Simulation time 171577899 ps
CPU time 1.09 seconds
Started Jul 01 10:43:17 AM PDT 24
Finished Jul 01 10:43:18 AM PDT 24
Peak memory 200276 kb
Host smart-276b6cc7-296b-4e37-8df1-1276635005e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817107142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.817107142
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1822531606
Short name T89
Test name
Test status
Simulation time 82302858 ps
CPU time 1.43 seconds
Started Jul 01 10:43:35 AM PDT 24
Finished Jul 01 10:43:37 AM PDT 24
Peak memory 199676 kb
Host smart-97dc6a82-4564-491c-bb58-afee31a462c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822531606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1822531606
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1944828355
Short name T1181
Test name
Test status
Simulation time 55697441 ps
CPU time 0.91 seconds
Started Jul 01 10:43:10 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 200136 kb
Host smart-4c672c1b-7af7-48ef-a9b8-607f6cc06691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944828355 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1944828355
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3775342305
Short name T79
Test name
Test status
Simulation time 26805402 ps
CPU time 0.6 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:08 AM PDT 24
Peak memory 195796 kb
Host smart-bc08d5c6-c902-46ec-9f2c-9831387a2248
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775342305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3775342305
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3735471898
Short name T1211
Test name
Test status
Simulation time 17912896 ps
CPU time 0.58 seconds
Started Jul 01 10:43:09 AM PDT 24
Finished Jul 01 10:43:13 AM PDT 24
Peak memory 194792 kb
Host smart-5bee875e-c09d-4cca-97f7-e705773ff8eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735471898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3735471898
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1725911372
Short name T1129
Test name
Test status
Simulation time 85220454 ps
CPU time 0.7 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 195180 kb
Host smart-1546c5fb-d875-4d22-a112-d4196e51576c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725911372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1725911372
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3797061630
Short name T1147
Test name
Test status
Simulation time 462681407 ps
CPU time 2.53 seconds
Started Jul 01 10:42:59 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 200396 kb
Host smart-5edd9cb7-b0c4-4a4a-9d22-c09b1b55e116
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797061630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3797061630
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1226406040
Short name T1192
Test name
Test status
Simulation time 41779990 ps
CPU time 0.9 seconds
Started Jul 01 10:43:00 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 199264 kb
Host smart-0823535a-8b04-47c1-b539-eb61d3bbcaca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226406040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1226406040
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.840551850
Short name T1174
Test name
Test status
Simulation time 42412040 ps
CPU time 0.69 seconds
Started Jul 01 10:43:36 AM PDT 24
Finished Jul 01 10:43:38 AM PDT 24
Peak memory 198336 kb
Host smart-a773b785-55d1-4d49-b1ec-1367e9837813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840551850 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.840551850
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1712609999
Short name T1155
Test name
Test status
Simulation time 37761295 ps
CPU time 0.61 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 195828 kb
Host smart-96cb5ca3-ed79-4176-a093-a832b0a771a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712609999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1712609999
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.6790434
Short name T1205
Test name
Test status
Simulation time 15741919 ps
CPU time 0.59 seconds
Started Jul 01 10:43:39 AM PDT 24
Finished Jul 01 10:43:40 AM PDT 24
Peak memory 194756 kb
Host smart-ddc22915-8cf6-4b1e-99d4-179515ff0294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6790434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.6790434
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3476501725
Short name T1216
Test name
Test status
Simulation time 139492743 ps
CPU time 0.66 seconds
Started Jul 01 10:43:06 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 195860 kb
Host smart-8a5defbf-077a-45c4-bf8f-2ff26c3c09be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476501725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3476501725
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.4187044193
Short name T1178
Test name
Test status
Simulation time 46442517 ps
CPU time 1.08 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:08 AM PDT 24
Peak memory 200424 kb
Host smart-121ce794-47e2-448f-a14d-b12c04693f74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187044193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4187044193
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3362529111
Short name T1148
Test name
Test status
Simulation time 241592060 ps
CPU time 0.9 seconds
Started Jul 01 10:43:02 AM PDT 24
Finished Jul 01 10:43:07 AM PDT 24
Peak memory 200196 kb
Host smart-7bcb274b-52e5-4480-8578-857598ce37ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362529111 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3362529111
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.4011859504
Short name T86
Test name
Test status
Simulation time 220040102 ps
CPU time 0.61 seconds
Started Jul 01 10:43:33 AM PDT 24
Finished Jul 01 10:43:35 AM PDT 24
Peak memory 195836 kb
Host smart-78eafaba-ee38-4a9f-b419-e1d19d2357c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011859504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.4011859504
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.669533430
Short name T1132
Test name
Test status
Simulation time 53638906 ps
CPU time 0.55 seconds
Started Jul 01 10:43:36 AM PDT 24
Finished Jul 01 10:43:38 AM PDT 24
Peak memory 194728 kb
Host smart-ded3c758-f08d-4394-8621-6002097e4c2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669533430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.669533430
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.499953399
Short name T1160
Test name
Test status
Simulation time 18717339 ps
CPU time 0.71 seconds
Started Jul 01 10:43:24 AM PDT 24
Finished Jul 01 10:43:30 AM PDT 24
Peak memory 197268 kb
Host smart-ddd18259-91dc-42f1-b643-52b35e1cc860
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499953399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.499953399
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3016757870
Short name T1170
Test name
Test status
Simulation time 77166027 ps
CPU time 1.26 seconds
Started Jul 01 10:43:21 AM PDT 24
Finished Jul 01 10:43:22 AM PDT 24
Peak memory 200624 kb
Host smart-7e5912b7-deee-4861-b05f-83a57e4e624f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016757870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3016757870
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1332807736
Short name T1162
Test name
Test status
Simulation time 288751369 ps
CPU time 1.39 seconds
Started Jul 01 10:43:03 AM PDT 24
Finished Jul 01 10:43:09 AM PDT 24
Peak memory 199732 kb
Host smart-89d31f48-ff6f-49d7-a280-73fcbdee5f33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332807736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1332807736
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2613036653
Short name T1104
Test name
Test status
Simulation time 89789344 ps
CPU time 0.91 seconds
Started Jul 01 10:43:29 AM PDT 24
Finished Jul 01 10:43:30 AM PDT 24
Peak memory 200180 kb
Host smart-063fdcc2-dd25-47b5-97db-b4f39b67db82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613036653 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2613036653
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.63740240
Short name T1107
Test name
Test status
Simulation time 28644346 ps
CPU time 0.63 seconds
Started Jul 01 10:43:35 AM PDT 24
Finished Jul 01 10:43:36 AM PDT 24
Peak memory 196028 kb
Host smart-e0853974-c338-4cc3-8029-cd8678cfa373
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63740240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.63740240
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.37524863
Short name T1180
Test name
Test status
Simulation time 35351065 ps
CPU time 0.59 seconds
Started Jul 01 10:43:25 AM PDT 24
Finished Jul 01 10:43:26 AM PDT 24
Peak memory 194636 kb
Host smart-914ee24f-1144-424c-b6e9-f1eac9d658f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37524863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.37524863
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.489914163
Short name T1209
Test name
Test status
Simulation time 12657332 ps
CPU time 0.63 seconds
Started Jul 01 10:43:05 AM PDT 24
Finished Jul 01 10:43:10 AM PDT 24
Peak memory 195752 kb
Host smart-4cdbc762-cb22-46e1-83b0-227239f6c358
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489914163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.489914163
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3685906088
Short name T1141
Test name
Test status
Simulation time 56524471 ps
CPU time 1.43 seconds
Started Jul 01 10:43:22 AM PDT 24
Finished Jul 01 10:43:29 AM PDT 24
Peak memory 200444 kb
Host smart-c9c414b3-f921-4e7c-b2c7-eacf8d3c2d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685906088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3685906088
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2508675589
Short name T1199
Test name
Test status
Simulation time 100182028 ps
CPU time 0.99 seconds
Started Jul 01 10:43:37 AM PDT 24
Finished Jul 01 10:43:39 AM PDT 24
Peak memory 199556 kb
Host smart-39c41585-95a8-4363-9441-339a1f8857b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508675589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2508675589
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.703329263
Short name T337
Test name
Test status
Simulation time 20968004 ps
CPU time 0.55 seconds
Started Jul 01 12:35:20 PM PDT 24
Finished Jul 01 12:35:21 PM PDT 24
Peak memory 194572 kb
Host smart-9523d971-0642-488a-854a-29806c580643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703329263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.703329263
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1471279716
Short name T110
Test name
Test status
Simulation time 11310072828 ps
CPU time 15.8 seconds
Started Jul 01 12:35:14 PM PDT 24
Finished Jul 01 12:35:30 PM PDT 24
Peak memory 198840 kb
Host smart-3af07d56-1676-4ff4-a285-89b1f8759b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471279716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1471279716
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.831749495
Short name T122
Test name
Test status
Simulation time 12261364620 ps
CPU time 17.97 seconds
Started Jul 01 12:35:15 PM PDT 24
Finished Jul 01 12:35:34 PM PDT 24
Peak memory 199820 kb
Host smart-332b29ea-95aa-4f7e-9cc1-8cb51e3e607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831749495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.831749495
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2852506528
Short name T302
Test name
Test status
Simulation time 43718924609 ps
CPU time 67.78 seconds
Started Jul 01 12:35:21 PM PDT 24
Finished Jul 01 12:36:30 PM PDT 24
Peak memory 199964 kb
Host smart-55e181fc-af88-4095-970a-0ed9b628688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852506528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2852506528
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3511343484
Short name T801
Test name
Test status
Simulation time 71602808639 ps
CPU time 118.02 seconds
Started Jul 01 12:35:20 PM PDT 24
Finished Jul 01 12:37:19 PM PDT 24
Peak memory 200012 kb
Host smart-c1ae8fb8-6d77-435c-93e9-ea3cd1a0f730
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511343484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3511343484
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2775315449
Short name T525
Test name
Test status
Simulation time 189102346538 ps
CPU time 886.61 seconds
Started Jul 01 12:35:21 PM PDT 24
Finished Jul 01 12:50:08 PM PDT 24
Peak memory 199908 kb
Host smart-6e484c5e-06d5-4c10-906c-a22ccd891b3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2775315449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2775315449
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2748670883
Short name T446
Test name
Test status
Simulation time 6311859932 ps
CPU time 7.42 seconds
Started Jul 01 12:35:21 PM PDT 24
Finished Jul 01 12:35:30 PM PDT 24
Peak memory 198532 kb
Host smart-f72575d9-a9e1-44bf-a317-7db98a576b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748670883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2748670883
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.992940067
Short name T803
Test name
Test status
Simulation time 53113444620 ps
CPU time 19.06 seconds
Started Jul 01 12:35:23 PM PDT 24
Finished Jul 01 12:35:43 PM PDT 24
Peak memory 198324 kb
Host smart-85cd596b-f27a-49be-9161-3a14cd297d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992940067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.992940067
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.4199209349
Short name T290
Test name
Test status
Simulation time 15564795569 ps
CPU time 649.2 seconds
Started Jul 01 12:35:21 PM PDT 24
Finished Jul 01 12:46:11 PM PDT 24
Peak memory 199956 kb
Host smart-34700fd0-30f0-4023-9cea-5c61f4960d22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199209349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4199209349
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3599359018
Short name T1022
Test name
Test status
Simulation time 4404922558 ps
CPU time 19.25 seconds
Started Jul 01 12:35:20 PM PDT 24
Finished Jul 01 12:35:41 PM PDT 24
Peak memory 198172 kb
Host smart-9d4315d4-c956-4411-8be3-2f8e68d2885f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599359018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3599359018
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1391149416
Short name T746
Test name
Test status
Simulation time 11436349086 ps
CPU time 7.66 seconds
Started Jul 01 12:35:20 PM PDT 24
Finished Jul 01 12:35:29 PM PDT 24
Peak memory 199564 kb
Host smart-543a84df-9578-40fd-97ea-7522055a3bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391149416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1391149416
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1543223611
Short name T949
Test name
Test status
Simulation time 3589681298 ps
CPU time 5.63 seconds
Started Jul 01 12:35:22 PM PDT 24
Finished Jul 01 12:35:29 PM PDT 24
Peak memory 196460 kb
Host smart-1c1018b7-5771-4bc9-ab3b-d5c3a7303479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543223611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1543223611
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3074119244
Short name T96
Test name
Test status
Simulation time 61109307 ps
CPU time 0.85 seconds
Started Jul 01 12:35:21 PM PDT 24
Finished Jul 01 12:35:23 PM PDT 24
Peak memory 218280 kb
Host smart-eef44d10-90eb-44c4-8174-9b90d45ef00f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074119244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3074119244
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2298555912
Short name T289
Test name
Test status
Simulation time 942458183 ps
CPU time 2.3 seconds
Started Jul 01 12:35:20 PM PDT 24
Finished Jul 01 12:35:24 PM PDT 24
Peak memory 199420 kb
Host smart-8b7e8757-a493-4747-a3eb-59c1f1507b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298555912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2298555912
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3582500839
Short name T533
Test name
Test status
Simulation time 653654176 ps
CPU time 2.41 seconds
Started Jul 01 12:35:24 PM PDT 24
Finished Jul 01 12:35:28 PM PDT 24
Peak memory 199012 kb
Host smart-d54e051b-f834-4394-89d8-6497f9e39691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582500839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3582500839
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.486832630
Short name T654
Test name
Test status
Simulation time 17846636959 ps
CPU time 20.01 seconds
Started Jul 01 12:35:16 PM PDT 24
Finished Jul 01 12:35:38 PM PDT 24
Peak memory 197220 kb
Host smart-86ca7be9-6150-48eb-92fe-74f847d722e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486832630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.486832630
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.770651386
Short name T760
Test name
Test status
Simulation time 13938884 ps
CPU time 0.57 seconds
Started Jul 01 12:35:25 PM PDT 24
Finished Jul 01 12:35:27 PM PDT 24
Peak memory 195300 kb
Host smart-e20c01e7-1b60-4b35-b1a4-5128d5964b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770651386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.770651386
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1937026119
Short name T1014
Test name
Test status
Simulation time 121650388341 ps
CPU time 60.88 seconds
Started Jul 01 12:35:24 PM PDT 24
Finished Jul 01 12:36:27 PM PDT 24
Peak memory 199856 kb
Host smart-26ec2ed6-fd2d-461f-a18d-5aa751c79d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937026119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1937026119
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3381705089
Short name T426
Test name
Test status
Simulation time 7822192217 ps
CPU time 11.83 seconds
Started Jul 01 12:35:23 PM PDT 24
Finished Jul 01 12:35:36 PM PDT 24
Peak memory 199804 kb
Host smart-d61f45b1-cd29-473a-a587-cc50b3d9c337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381705089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3381705089
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.1428126122
Short name T635
Test name
Test status
Simulation time 50108283313 ps
CPU time 54.6 seconds
Started Jul 01 12:35:26 PM PDT 24
Finished Jul 01 12:36:21 PM PDT 24
Peak memory 200000 kb
Host smart-6e422ab6-bcd7-4bec-a88b-1f9cb74e41f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428126122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1428126122
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3306893566
Short name T832
Test name
Test status
Simulation time 100800665232 ps
CPU time 717.06 seconds
Started Jul 01 12:35:28 PM PDT 24
Finished Jul 01 12:47:26 PM PDT 24
Peak memory 199992 kb
Host smart-ff7df89d-44b0-4171-a59f-d769d96f9c70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306893566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3306893566
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3066127710
Short name T349
Test name
Test status
Simulation time 3654698729 ps
CPU time 6.81 seconds
Started Jul 01 12:35:30 PM PDT 24
Finished Jul 01 12:35:37 PM PDT 24
Peak memory 198700 kb
Host smart-fec49fba-9260-4039-894f-a00206375b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066127710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3066127710
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.115033050
Short name T460
Test name
Test status
Simulation time 31165614997 ps
CPU time 351.73 seconds
Started Jul 01 12:35:25 PM PDT 24
Finished Jul 01 12:41:18 PM PDT 24
Peak memory 199976 kb
Host smart-ff458b27-5b6d-4f94-8cde-e25c1122c426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115033050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.115033050
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2311845122
Short name T404
Test name
Test status
Simulation time 2653522833 ps
CPU time 9.16 seconds
Started Jul 01 12:35:24 PM PDT 24
Finished Jul 01 12:35:34 PM PDT 24
Peak memory 199024 kb
Host smart-9fdea844-91be-4686-86ed-5a231c68ed0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311845122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2311845122
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.343294560
Short name T360
Test name
Test status
Simulation time 28907161199 ps
CPU time 46.5 seconds
Started Jul 01 12:35:30 PM PDT 24
Finished Jul 01 12:36:17 PM PDT 24
Peak memory 199964 kb
Host smart-308c8fbb-0cfe-42aa-8ca7-410290ae60e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343294560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.343294560
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3793030287
Short name T1081
Test name
Test status
Simulation time 5149694036 ps
CPU time 4.23 seconds
Started Jul 01 12:35:27 PM PDT 24
Finished Jul 01 12:35:33 PM PDT 24
Peak memory 196140 kb
Host smart-fd971198-847d-4308-b28a-c62c413e41e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793030287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3793030287
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.661667996
Short name T97
Test name
Test status
Simulation time 70017109 ps
CPU time 0.88 seconds
Started Jul 01 12:35:27 PM PDT 24
Finished Jul 01 12:35:29 PM PDT 24
Peak memory 218236 kb
Host smart-bfbcaf8d-86db-4ec4-bbad-3552ccb9e2df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661667996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.661667996
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3783155910
Short name T274
Test name
Test status
Simulation time 657856832 ps
CPU time 1.5 seconds
Started Jul 01 12:35:23 PM PDT 24
Finished Jul 01 12:35:25 PM PDT 24
Peak memory 198728 kb
Host smart-4dde9ef2-fca0-49ba-8b54-4b0869aa437a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783155910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3783155910
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2771938348
Short name T729
Test name
Test status
Simulation time 461542716198 ps
CPU time 128.08 seconds
Started Jul 01 12:35:28 PM PDT 24
Finished Jul 01 12:37:37 PM PDT 24
Peak memory 199952 kb
Host smart-4e31fe7a-2b87-488f-9ca6-827e955e6948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771938348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2771938348
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1820091377
Short name T1002
Test name
Test status
Simulation time 908809427 ps
CPU time 2.82 seconds
Started Jul 01 12:35:28 PM PDT 24
Finished Jul 01 12:35:32 PM PDT 24
Peak memory 198372 kb
Host smart-aa48e7be-b7e7-4857-9a98-d5d79a5be127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820091377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1820091377
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1985295217
Short name T658
Test name
Test status
Simulation time 78681204956 ps
CPU time 154.45 seconds
Started Jul 01 12:35:23 PM PDT 24
Finished Jul 01 12:37:59 PM PDT 24
Peak memory 199952 kb
Host smart-7376ce02-5bfc-4b36-8864-a8f5962ddee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985295217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1985295217
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.599070855
Short name T1049
Test name
Test status
Simulation time 12841855 ps
CPU time 0.57 seconds
Started Jul 01 12:36:38 PM PDT 24
Finished Jul 01 12:36:40 PM PDT 24
Peak memory 195272 kb
Host smart-5918a1fa-0ff9-4809-a459-00d153a64160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599070855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.599070855
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2157679293
Short name T549
Test name
Test status
Simulation time 35960361480 ps
CPU time 59.29 seconds
Started Jul 01 12:36:29 PM PDT 24
Finished Jul 01 12:37:29 PM PDT 24
Peak memory 200004 kb
Host smart-407ed4ca-8303-4750-972d-1de7fc0dba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157679293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2157679293
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.479063144
Short name T607
Test name
Test status
Simulation time 217988570037 ps
CPU time 40.75 seconds
Started Jul 01 12:36:28 PM PDT 24
Finished Jul 01 12:37:09 PM PDT 24
Peak memory 199972 kb
Host smart-ddb43a28-9f08-4261-8e81-6f48e28c3bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479063144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.479063144
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2595851861
Short name T690
Test name
Test status
Simulation time 223854862691 ps
CPU time 62.53 seconds
Started Jul 01 12:36:29 PM PDT 24
Finished Jul 01 12:37:32 PM PDT 24
Peak memory 199912 kb
Host smart-cd895428-ec3b-4870-8169-5f0ab6000320
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595851861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2595851861
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2145362523
Short name T114
Test name
Test status
Simulation time 52223446092 ps
CPU time 275.4 seconds
Started Jul 01 12:36:33 PM PDT 24
Finished Jul 01 12:41:10 PM PDT 24
Peak memory 199952 kb
Host smart-b8fd68eb-0f33-408a-a211-ab6882595c6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145362523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2145362523
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1531086371
Short name T458
Test name
Test status
Simulation time 103819587 ps
CPU time 0.73 seconds
Started Jul 01 12:36:34 PM PDT 24
Finished Jul 01 12:36:36 PM PDT 24
Peak memory 195780 kb
Host smart-c85da542-06b1-45d0-bdd7-6e132f6511eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531086371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1531086371
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.291303528
Short name T854
Test name
Test status
Simulation time 8024187873 ps
CPU time 155.56 seconds
Started Jul 01 12:36:36 PM PDT 24
Finished Jul 01 12:39:12 PM PDT 24
Peak memory 199944 kb
Host smart-5d29ba9e-9187-4070-8d26-9a37c34c73ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291303528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.291303528
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.617769402
Short name T744
Test name
Test status
Simulation time 5937571886 ps
CPU time 11.83 seconds
Started Jul 01 12:36:29 PM PDT 24
Finished Jul 01 12:36:42 PM PDT 24
Peak memory 199920 kb
Host smart-1e95dac4-8f7b-4370-916e-46f4e58b19d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617769402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.617769402
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1717616957
Short name T461
Test name
Test status
Simulation time 56774776988 ps
CPU time 61.12 seconds
Started Jul 01 12:36:29 PM PDT 24
Finished Jul 01 12:37:31 PM PDT 24
Peak memory 199944 kb
Host smart-49b7d610-bd49-44cf-a1f3-93d30e8d3dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717616957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1717616957
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.43512938
Short name T287
Test name
Test status
Simulation time 3512338862 ps
CPU time 5.96 seconds
Started Jul 01 12:36:28 PM PDT 24
Finished Jul 01 12:36:35 PM PDT 24
Peak memory 196256 kb
Host smart-78c0ae07-b5c9-47cb-8370-41adf193512f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43512938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.43512938
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3698395824
Short name T507
Test name
Test status
Simulation time 269363755 ps
CPU time 1.51 seconds
Started Jul 01 12:36:25 PM PDT 24
Finished Jul 01 12:36:27 PM PDT 24
Peak memory 198208 kb
Host smart-daf6d616-ae59-42dd-aade-200f34e296ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698395824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3698395824
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.4138162383
Short name T1054
Test name
Test status
Simulation time 60742612891 ps
CPU time 100.89 seconds
Started Jul 01 12:36:38 PM PDT 24
Finished Jul 01 12:38:19 PM PDT 24
Peak memory 199920 kb
Host smart-7b728fd5-a85b-4818-a571-e093c04ee7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138162383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4138162383
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.639499404
Short name T1097
Test name
Test status
Simulation time 194528291812 ps
CPU time 1606.14 seconds
Started Jul 01 12:36:34 PM PDT 24
Finished Jul 01 01:03:22 PM PDT 24
Peak memory 216452 kb
Host smart-5192ed4f-7b4b-4962-ade9-381273909c26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639499404 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.639499404
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3690972879
Short name T406
Test name
Test status
Simulation time 6895316871 ps
CPU time 25.76 seconds
Started Jul 01 12:36:34 PM PDT 24
Finished Jul 01 12:37:01 PM PDT 24
Peak memory 199444 kb
Host smart-50a9b4c2-be84-4914-abd3-c061317801a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690972879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3690972879
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3904590272
Short name T546
Test name
Test status
Simulation time 125077999530 ps
CPU time 83.83 seconds
Started Jul 01 12:36:24 PM PDT 24
Finished Jul 01 12:37:48 PM PDT 24
Peak memory 199996 kb
Host smart-7d235c3d-abbc-4729-9dfa-6bb850f9ed56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904590272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3904590272
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4285305538
Short name T441
Test name
Test status
Simulation time 102323289727 ps
CPU time 95.73 seconds
Started Jul 01 12:43:45 PM PDT 24
Finished Jul 01 12:45:21 PM PDT 24
Peak memory 199844 kb
Host smart-8b655a62-804d-446c-b352-29091532c23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285305538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4285305538
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2944095868
Short name T67
Test name
Test status
Simulation time 141529604364 ps
CPU time 102.06 seconds
Started Jul 01 12:43:44 PM PDT 24
Finished Jul 01 12:45:27 PM PDT 24
Peak memory 199668 kb
Host smart-e1f93345-e732-4808-a7fc-a9a06f90fcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944095868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2944095868
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3119486022
Short name T260
Test name
Test status
Simulation time 8903305848 ps
CPU time 24.65 seconds
Started Jul 01 12:43:45 PM PDT 24
Finished Jul 01 12:44:11 PM PDT 24
Peak memory 199964 kb
Host smart-2e8ec730-38c3-4c40-815f-9204389271be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119486022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3119486022
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.6696765
Short name T513
Test name
Test status
Simulation time 133237931167 ps
CPU time 214.04 seconds
Started Jul 01 12:43:45 PM PDT 24
Finished Jul 01 12:47:19 PM PDT 24
Peak memory 199916 kb
Host smart-efb4c414-c564-4ecd-8f22-8040d5159f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6696765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.6696765
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1146209393
Short name T612
Test name
Test status
Simulation time 165024822222 ps
CPU time 153.76 seconds
Started Jul 01 12:43:50 PM PDT 24
Finished Jul 01 12:46:24 PM PDT 24
Peak memory 199908 kb
Host smart-805a8e29-a776-4782-a8d5-0d9defada0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146209393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1146209393
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2199495083
Short name T1007
Test name
Test status
Simulation time 48580702297 ps
CPU time 19.88 seconds
Started Jul 01 12:43:50 PM PDT 24
Finished Jul 01 12:44:10 PM PDT 24
Peak memory 199916 kb
Host smart-97d6d5fd-c512-4592-bfc4-d06c4f472c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199495083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2199495083
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3775368760
Short name T868
Test name
Test status
Simulation time 30181681 ps
CPU time 0.55 seconds
Started Jul 01 12:36:47 PM PDT 24
Finished Jul 01 12:36:49 PM PDT 24
Peak memory 195312 kb
Host smart-082010a5-dd6a-460c-9acc-1d150c3316fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775368760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3775368760
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.4213924839
Short name T849
Test name
Test status
Simulation time 128251082213 ps
CPU time 29.49 seconds
Started Jul 01 12:36:38 PM PDT 24
Finished Jul 01 12:37:08 PM PDT 24
Peak memory 199876 kb
Host smart-fe891119-d66b-4ecc-9a02-58237cc35441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213924839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.4213924839
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.343638115
Short name T171
Test name
Test status
Simulation time 25020194311 ps
CPU time 13.13 seconds
Started Jul 01 12:36:39 PM PDT 24
Finished Jul 01 12:36:53 PM PDT 24
Peak memory 199976 kb
Host smart-efb45f58-b170-43c2-9444-a72ef7b419c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343638115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.343638115
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1698914362
Short name T696
Test name
Test status
Simulation time 331616604409 ps
CPU time 99.25 seconds
Started Jul 01 12:36:38 PM PDT 24
Finished Jul 01 12:38:17 PM PDT 24
Peak memory 199996 kb
Host smart-feaa0d4b-96fe-46f8-8504-038081aba464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698914362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1698914362
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.29369827
Short name T618
Test name
Test status
Simulation time 53062393326 ps
CPU time 11.93 seconds
Started Jul 01 12:36:44 PM PDT 24
Finished Jul 01 12:36:57 PM PDT 24
Peak memory 199928 kb
Host smart-f95304a5-0330-4d1b-a363-18050af3e9b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29369827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.29369827
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3264008050
Short name T939
Test name
Test status
Simulation time 34713211246 ps
CPU time 272.76 seconds
Started Jul 01 12:36:47 PM PDT 24
Finished Jul 01 12:41:22 PM PDT 24
Peak memory 199932 kb
Host smart-19b908b9-f6ae-4b3a-894c-4c9f2cf07920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264008050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3264008050
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.622514273
Short name T455
Test name
Test status
Simulation time 4268660847 ps
CPU time 7.53 seconds
Started Jul 01 12:36:46 PM PDT 24
Finished Jul 01 12:36:55 PM PDT 24
Peak memory 195924 kb
Host smart-bf122d5d-5281-439b-b3f8-0541da5fe038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622514273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.622514273
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.158162169
Short name T894
Test name
Test status
Simulation time 28318110757 ps
CPU time 296.74 seconds
Started Jul 01 12:36:49 PM PDT 24
Finished Jul 01 12:41:47 PM PDT 24
Peak memory 199960 kb
Host smart-45ee58e8-3ebd-4195-bdf0-c65a03dc7877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158162169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.158162169
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.448287416
Short name T969
Test name
Test status
Simulation time 3601348818 ps
CPU time 7.86 seconds
Started Jul 01 12:36:39 PM PDT 24
Finished Jul 01 12:36:48 PM PDT 24
Peak memory 199184 kb
Host smart-34756494-9bae-4ed2-95df-f5d7b4793019
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448287416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.448287416
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.960571090
Short name T357
Test name
Test status
Simulation time 42281129167 ps
CPU time 16.29 seconds
Started Jul 01 12:36:44 PM PDT 24
Finished Jul 01 12:37:01 PM PDT 24
Peak memory 199956 kb
Host smart-bab6d307-fe78-4926-a655-39d02fee1e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960571090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.960571090
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.947721730
Short name T352
Test name
Test status
Simulation time 3887426037 ps
CPU time 1.29 seconds
Started Jul 01 12:36:48 PM PDT 24
Finished Jul 01 12:36:51 PM PDT 24
Peak memory 196732 kb
Host smart-716e7ed7-81eb-4d4a-827f-2c0285aaef04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947721730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.947721730
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2464410807
Short name T556
Test name
Test status
Simulation time 5815636926 ps
CPU time 5.69 seconds
Started Jul 01 12:36:38 PM PDT 24
Finished Jul 01 12:36:45 PM PDT 24
Peak memory 200004 kb
Host smart-b2a7eb51-304a-444e-b419-81f8841c4a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464410807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2464410807
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3539045663
Short name T591
Test name
Test status
Simulation time 181731722768 ps
CPU time 23.54 seconds
Started Jul 01 12:36:47 PM PDT 24
Finished Jul 01 12:37:11 PM PDT 24
Peak memory 199912 kb
Host smart-ab679d92-f2c1-46f2-ba23-dff3bbc50489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539045663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3539045663
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3450858132
Short name T413
Test name
Test status
Simulation time 1021880793 ps
CPU time 2.16 seconds
Started Jul 01 12:36:46 PM PDT 24
Finished Jul 01 12:36:49 PM PDT 24
Peak memory 199456 kb
Host smart-cd158d4a-b991-405b-9504-657afadb0378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450858132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3450858132
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.941110061
Short name T469
Test name
Test status
Simulation time 19245087356 ps
CPU time 34.87 seconds
Started Jul 01 12:36:39 PM PDT 24
Finished Jul 01 12:37:15 PM PDT 24
Peak memory 199912 kb
Host smart-81c47cc8-464d-4f06-b845-c7cb96e20693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941110061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.941110061
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1490211269
Short name T526
Test name
Test status
Simulation time 118098060373 ps
CPU time 99.88 seconds
Started Jul 01 12:43:49 PM PDT 24
Finished Jul 01 12:45:30 PM PDT 24
Peak memory 199804 kb
Host smart-697ffc11-b05d-436b-92c8-e9285089a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490211269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1490211269
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1925994258
Short name T480
Test name
Test status
Simulation time 107626450007 ps
CPU time 79.01 seconds
Started Jul 01 12:43:50 PM PDT 24
Finished Jul 01 12:45:09 PM PDT 24
Peak memory 199992 kb
Host smart-74bd8228-3892-4f53-b982-b651cf3e9f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925994258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1925994258
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.237088560
Short name T320
Test name
Test status
Simulation time 33247486036 ps
CPU time 23.54 seconds
Started Jul 01 12:43:58 PM PDT 24
Finished Jul 01 12:44:23 PM PDT 24
Peak memory 199992 kb
Host smart-f60fdf42-7c1b-432b-9fcb-d32e8f841d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237088560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.237088560
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3533772105
Short name T325
Test name
Test status
Simulation time 121584228243 ps
CPU time 191.35 seconds
Started Jul 01 12:43:59 PM PDT 24
Finished Jul 01 12:47:11 PM PDT 24
Peak memory 199916 kb
Host smart-bc756a86-fa54-40ce-bd24-7b8e97f7c3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533772105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3533772105
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2138340206
Short name T1077
Test name
Test status
Simulation time 18621560541 ps
CPU time 24.91 seconds
Started Jul 01 12:43:59 PM PDT 24
Finished Jul 01 12:44:24 PM PDT 24
Peak memory 199916 kb
Host smart-fa197e74-2c97-4110-9691-022a021c3bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138340206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2138340206
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.449123055
Short name T1064
Test name
Test status
Simulation time 32894987057 ps
CPU time 17.51 seconds
Started Jul 01 12:44:04 PM PDT 24
Finished Jul 01 12:44:23 PM PDT 24
Peak memory 199876 kb
Host smart-247196de-6afe-40eb-9808-ae7e66345a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449123055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.449123055
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3252877156
Short name T368
Test name
Test status
Simulation time 427842356806 ps
CPU time 61.43 seconds
Started Jul 01 12:44:03 PM PDT 24
Finished Jul 01 12:45:05 PM PDT 24
Peak memory 200008 kb
Host smart-83e16ac0-a5be-444c-b5d7-02397b7c2706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252877156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3252877156
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.263130594
Short name T833
Test name
Test status
Simulation time 85528999 ps
CPU time 0.54 seconds
Started Jul 01 12:36:53 PM PDT 24
Finished Jul 01 12:36:54 PM PDT 24
Peak memory 195204 kb
Host smart-5313bd57-0043-4734-9598-37035b9aec5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263130594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.263130594
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.780957123
Short name T1075
Test name
Test status
Simulation time 75198612124 ps
CPU time 33.8 seconds
Started Jul 01 12:36:47 PM PDT 24
Finished Jul 01 12:37:22 PM PDT 24
Peak memory 199836 kb
Host smart-b42a5e45-311b-4a9a-910b-289437bb528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780957123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.780957123
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.248452740
Short name T728
Test name
Test status
Simulation time 109041369173 ps
CPU time 35.28 seconds
Started Jul 01 12:36:47 PM PDT 24
Finished Jul 01 12:37:24 PM PDT 24
Peak memory 199924 kb
Host smart-7a469f6f-00ba-4ec1-8966-5f860f92bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248452740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.248452740
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1330829147
Short name T48
Test name
Test status
Simulation time 212778652648 ps
CPU time 101.38 seconds
Started Jul 01 12:36:48 PM PDT 24
Finished Jul 01 12:38:31 PM PDT 24
Peak memory 199852 kb
Host smart-de087ecf-26df-487f-bbe6-8af971035744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330829147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1330829147
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.4245831248
Short name T24
Test name
Test status
Simulation time 15920373433 ps
CPU time 7.9 seconds
Started Jul 01 12:36:46 PM PDT 24
Finished Jul 01 12:36:55 PM PDT 24
Peak memory 199036 kb
Host smart-ddcdec85-b261-4c2d-b82e-8218332d68fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245831248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.4245831248
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1848675441
Short name T398
Test name
Test status
Simulation time 139726233471 ps
CPU time 527.12 seconds
Started Jul 01 12:36:52 PM PDT 24
Finished Jul 01 12:45:40 PM PDT 24
Peak memory 199984 kb
Host smart-645668ae-4b6e-4730-b5d1-9411952f72cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848675441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1848675441
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.992578406
Short name T558
Test name
Test status
Simulation time 7128250195 ps
CPU time 13.47 seconds
Started Jul 01 12:36:51 PM PDT 24
Finished Jul 01 12:37:05 PM PDT 24
Peak memory 199916 kb
Host smart-a9c8f9b6-ed5a-4787-b9d3-a04657061f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992578406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.992578406
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.3176402504
Short name T2
Test name
Test status
Simulation time 14943154005 ps
CPU time 840.6 seconds
Started Jul 01 12:36:54 PM PDT 24
Finished Jul 01 12:50:55 PM PDT 24
Peak memory 199908 kb
Host smart-e18cc714-31b2-4b72-9734-8edc21e6ab18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176402504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3176402504
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3972491704
Short name T115
Test name
Test status
Simulation time 2036825845 ps
CPU time 2.75 seconds
Started Jul 01 12:36:46 PM PDT 24
Finished Jul 01 12:36:49 PM PDT 24
Peak memory 199168 kb
Host smart-9ac269ee-fba6-4c01-b42d-85b939c38e97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972491704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3972491704
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1568819119
Short name T834
Test name
Test status
Simulation time 112528816649 ps
CPU time 47.68 seconds
Started Jul 01 12:36:53 PM PDT 24
Finished Jul 01 12:37:41 PM PDT 24
Peak memory 199972 kb
Host smart-2ff59104-c83e-45d4-b06d-05253b372bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568819119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1568819119
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1865606264
Short name T415
Test name
Test status
Simulation time 1744626339 ps
CPU time 3.41 seconds
Started Jul 01 12:36:51 PM PDT 24
Finished Jul 01 12:36:56 PM PDT 24
Peak memory 195356 kb
Host smart-ea80d528-9f19-4ad3-bf3d-b45400884b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865606264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1865606264
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1146113540
Short name T602
Test name
Test status
Simulation time 5767550173 ps
CPU time 8.95 seconds
Started Jul 01 12:36:48 PM PDT 24
Finished Jul 01 12:36:58 PM PDT 24
Peak memory 199896 kb
Host smart-7815255f-c505-4b9a-926e-0cb8c5ef4870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146113540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1146113540
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3500911447
Short name T747
Test name
Test status
Simulation time 254650552349 ps
CPU time 324.46 seconds
Started Jul 01 12:36:52 PM PDT 24
Finished Jul 01 12:42:17 PM PDT 24
Peak memory 199944 kb
Host smart-20aff308-66b9-41f9-8ef5-d275d4787451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500911447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3500911447
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1990899972
Short name T823
Test name
Test status
Simulation time 191503258813 ps
CPU time 215.16 seconds
Started Jul 01 12:36:53 PM PDT 24
Finished Jul 01 12:40:29 PM PDT 24
Peak memory 216508 kb
Host smart-4f3a9640-cb9c-4c3f-adf0-edb6fe262bc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990899972 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1990899972
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1191647683
Short name T571
Test name
Test status
Simulation time 6235608826 ps
CPU time 16.1 seconds
Started Jul 01 12:36:52 PM PDT 24
Finished Jul 01 12:37:09 PM PDT 24
Peak memory 199296 kb
Host smart-b1bd364a-6f57-4a2c-94ba-9ac91ba5dce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191647683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1191647683
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.131766460
Short name T609
Test name
Test status
Simulation time 2441618658 ps
CPU time 1.42 seconds
Started Jul 01 12:36:49 PM PDT 24
Finished Jul 01 12:36:52 PM PDT 24
Peak memory 199932 kb
Host smart-4bab4aa9-0f30-4b39-9035-c0f9f68496cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131766460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.131766460
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1914478069
Short name T968
Test name
Test status
Simulation time 24990425826 ps
CPU time 16.74 seconds
Started Jul 01 12:44:02 PM PDT 24
Finished Jul 01 12:44:20 PM PDT 24
Peak memory 199900 kb
Host smart-84ac6302-00e7-442b-b5ef-603de3a922ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914478069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1914478069
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3479832389
Short name T204
Test name
Test status
Simulation time 14835838517 ps
CPU time 26.9 seconds
Started Jul 01 12:44:03 PM PDT 24
Finished Jul 01 12:44:31 PM PDT 24
Peak memory 199936 kb
Host smart-8c9466cb-c716-44d8-b427-4916e49a4293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479832389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3479832389
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.857280318
Short name T518
Test name
Test status
Simulation time 53474207429 ps
CPU time 70.76 seconds
Started Jul 01 12:44:02 PM PDT 24
Finished Jul 01 12:45:13 PM PDT 24
Peak memory 200000 kb
Host smart-342adca8-4c4d-468a-9610-301fcb46defd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857280318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.857280318
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2676451321
Short name T240
Test name
Test status
Simulation time 19810074766 ps
CPU time 29.68 seconds
Started Jul 01 12:44:02 PM PDT 24
Finished Jul 01 12:44:32 PM PDT 24
Peak memory 199924 kb
Host smart-105e8c33-687e-4bfa-b542-a4330cf55cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676451321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2676451321
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3873413063
Short name T183
Test name
Test status
Simulation time 33771494202 ps
CPU time 23.23 seconds
Started Jul 01 12:44:03 PM PDT 24
Finished Jul 01 12:44:28 PM PDT 24
Peak memory 199960 kb
Host smart-add458c4-0a8f-4331-839f-2cc0cbae3c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873413063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3873413063
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3058229139
Short name T98
Test name
Test status
Simulation time 84576714670 ps
CPU time 85.4 seconds
Started Jul 01 12:44:02 PM PDT 24
Finished Jul 01 12:45:29 PM PDT 24
Peak memory 199960 kb
Host smart-57eab3cb-5c81-4f09-9348-141dfac5c48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058229139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3058229139
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.4290502147
Short name T127
Test name
Test status
Simulation time 167262788404 ps
CPU time 129.84 seconds
Started Jul 01 12:44:04 PM PDT 24
Finished Jul 01 12:46:15 PM PDT 24
Peak memory 200020 kb
Host smart-5996cb3e-7dd2-4aad-91f4-3c61a5028c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290502147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4290502147
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.479375981
Short name T781
Test name
Test status
Simulation time 14260681279 ps
CPU time 34.18 seconds
Started Jul 01 12:44:03 PM PDT 24
Finished Jul 01 12:44:38 PM PDT 24
Peak memory 199984 kb
Host smart-5654bd60-dc10-4388-9993-75572d3b5db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479375981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.479375981
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3005119040
Short name T177
Test name
Test status
Simulation time 38335517039 ps
CPU time 32.2 seconds
Started Jul 01 12:44:03 PM PDT 24
Finished Jul 01 12:44:37 PM PDT 24
Peak memory 199936 kb
Host smart-3488ce1c-167a-4b14-80ee-745dc3539cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005119040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3005119040
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3620660778
Short name T1037
Test name
Test status
Simulation time 25758968347 ps
CPU time 13.23 seconds
Started Jul 01 12:44:01 PM PDT 24
Finished Jul 01 12:44:15 PM PDT 24
Peak memory 199976 kb
Host smart-4d0d7d4a-96c2-4bb4-a1d0-edc6d8f865eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620660778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3620660778
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2831859639
Short name T475
Test name
Test status
Simulation time 63459956 ps
CPU time 0.55 seconds
Started Jul 01 12:37:04 PM PDT 24
Finished Jul 01 12:37:06 PM PDT 24
Peak memory 195192 kb
Host smart-de559b86-7875-43fc-a906-ecd8891166ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831859639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2831859639
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.6241735
Short name T655
Test name
Test status
Simulation time 108904665856 ps
CPU time 106.48 seconds
Started Jul 01 12:36:57 PM PDT 24
Finished Jul 01 12:38:45 PM PDT 24
Peak memory 199912 kb
Host smart-a7383200-8c8e-43a5-b1e1-e307625d9948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6241735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.6241735
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2117954660
Short name T141
Test name
Test status
Simulation time 136107948596 ps
CPU time 100.08 seconds
Started Jul 01 12:36:59 PM PDT 24
Finished Jul 01 12:38:40 PM PDT 24
Peak memory 199980 kb
Host smart-831e2415-871f-4c52-bfe9-1939a6fadca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117954660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2117954660
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3315684260
Short name T323
Test name
Test status
Simulation time 14187220121 ps
CPU time 7.88 seconds
Started Jul 01 12:36:58 PM PDT 24
Finished Jul 01 12:37:07 PM PDT 24
Peak memory 199716 kb
Host smart-9ccbdf4d-5755-4280-82ac-25216bb069d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315684260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3315684260
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3809268019
Short name T1094
Test name
Test status
Simulation time 9007377985 ps
CPU time 12.83 seconds
Started Jul 01 12:36:57 PM PDT 24
Finished Jul 01 12:37:11 PM PDT 24
Peak memory 196832 kb
Host smart-25e55879-ae42-4288-bd92-4f4bce5828cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809268019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3809268019
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3395543642
Short name T538
Test name
Test status
Simulation time 53928777575 ps
CPU time 565.66 seconds
Started Jul 01 12:37:01 PM PDT 24
Finished Jul 01 12:46:28 PM PDT 24
Peak memory 199964 kb
Host smart-0417908a-59ce-42ec-ab01-878fc41983c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395543642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3395543642
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1406054969
Short name T495
Test name
Test status
Simulation time 7452890887 ps
CPU time 5.55 seconds
Started Jul 01 12:37:04 PM PDT 24
Finished Jul 01 12:37:11 PM PDT 24
Peak memory 200044 kb
Host smart-092c750f-0c47-46b2-8038-b95448d691ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406054969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1406054969
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3480662836
Short name T576
Test name
Test status
Simulation time 35861035753 ps
CPU time 14.34 seconds
Started Jul 01 12:37:04 PM PDT 24
Finished Jul 01 12:37:20 PM PDT 24
Peak memory 197896 kb
Host smart-034d9ecf-d9d2-43f1-9132-0f3a08c9d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480662836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3480662836
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3349905681
Short name T391
Test name
Test status
Simulation time 14518403442 ps
CPU time 257.14 seconds
Started Jul 01 12:37:02 PM PDT 24
Finished Jul 01 12:41:20 PM PDT 24
Peak memory 199840 kb
Host smart-e4ef10a3-fff3-417e-8bb3-120587ea76dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349905681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3349905681
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.895273481
Short name T390
Test name
Test status
Simulation time 3252619754 ps
CPU time 24.69 seconds
Started Jul 01 12:37:00 PM PDT 24
Finished Jul 01 12:37:25 PM PDT 24
Peak memory 198836 kb
Host smart-3ee56c58-4afa-4592-aa20-5940859717f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895273481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.895273481
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2266434783
Short name T154
Test name
Test status
Simulation time 195550027410 ps
CPU time 172.23 seconds
Started Jul 01 12:37:03 PM PDT 24
Finished Jul 01 12:39:56 PM PDT 24
Peak memory 199960 kb
Host smart-845de282-a307-44f1-8fff-6fb4ca46c6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266434783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2266434783
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.960652271
Short name T335
Test name
Test status
Simulation time 2503858923 ps
CPU time 2.44 seconds
Started Jul 01 12:37:02 PM PDT 24
Finished Jul 01 12:37:05 PM PDT 24
Peak memory 196440 kb
Host smart-2d281704-759e-49d1-81f9-273b11db2379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960652271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.960652271
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.475321786
Short name T381
Test name
Test status
Simulation time 302923928 ps
CPU time 1.18 seconds
Started Jul 01 12:36:57 PM PDT 24
Finished Jul 01 12:36:58 PM PDT 24
Peak memory 198292 kb
Host smart-dbbd5049-288c-49e8-aa29-a713dce59295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475321786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.475321786
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2934623535
Short name T575
Test name
Test status
Simulation time 36245212405 ps
CPU time 232.43 seconds
Started Jul 01 12:37:03 PM PDT 24
Finished Jul 01 12:40:57 PM PDT 24
Peak memory 208348 kb
Host smart-c15abcca-aa96-422b-8225-ab0b0cc816c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934623535 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2934623535
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.421457149
Short name T534
Test name
Test status
Simulation time 1989577465 ps
CPU time 2.21 seconds
Started Jul 01 12:37:03 PM PDT 24
Finished Jul 01 12:37:06 PM PDT 24
Peak memory 199484 kb
Host smart-46421f0c-ad38-43c4-a0e8-a2b3443a31b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421457149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.421457149
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2277889650
Short name T514
Test name
Test status
Simulation time 62837693247 ps
CPU time 114.04 seconds
Started Jul 01 12:36:58 PM PDT 24
Finished Jul 01 12:38:52 PM PDT 24
Peak memory 200040 kb
Host smart-c5b6babe-d7ab-4c43-a60d-02335f885b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277889650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2277889650
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.379256098
Short name T873
Test name
Test status
Simulation time 83103042661 ps
CPU time 33.35 seconds
Started Jul 01 12:44:04 PM PDT 24
Finished Jul 01 12:44:39 PM PDT 24
Peak memory 199908 kb
Host smart-4007c5b4-9f19-435c-8a3f-a729287be417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379256098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.379256098
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2510881345
Short name T484
Test name
Test status
Simulation time 14111098655 ps
CPU time 21.57 seconds
Started Jul 01 12:44:06 PM PDT 24
Finished Jul 01 12:44:28 PM PDT 24
Peak memory 200016 kb
Host smart-c1f53356-c408-4286-90ab-ec20d68c1596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510881345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2510881345
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.708311063
Short name T779
Test name
Test status
Simulation time 153962825117 ps
CPU time 39.63 seconds
Started Jul 01 12:44:10 PM PDT 24
Finished Jul 01 12:44:50 PM PDT 24
Peak memory 199920 kb
Host smart-52ca5de9-f7c5-4616-a58d-f7d87d6ea0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708311063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.708311063
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2405415678
Short name T201
Test name
Test status
Simulation time 28728260471 ps
CPU time 28.69 seconds
Started Jul 01 12:44:10 PM PDT 24
Finished Jul 01 12:44:39 PM PDT 24
Peak memory 200000 kb
Host smart-8b03ac92-2150-4956-ab6f-4e9e17c20f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405415678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2405415678
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2791683698
Short name T624
Test name
Test status
Simulation time 14183109659 ps
CPU time 10.19 seconds
Started Jul 01 12:44:08 PM PDT 24
Finished Jul 01 12:44:19 PM PDT 24
Peak memory 199764 kb
Host smart-bbab54f0-90f9-4c9e-9447-3c4a98aa0620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791683698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2791683698
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3030110318
Short name T1009
Test name
Test status
Simulation time 22953577026 ps
CPU time 11.92 seconds
Started Jul 01 12:44:07 PM PDT 24
Finished Jul 01 12:44:20 PM PDT 24
Peak memory 199960 kb
Host smart-eb2d1b28-2287-4d35-8afa-dec42d325e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030110318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3030110318
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1814567119
Short name T252
Test name
Test status
Simulation time 189684752296 ps
CPU time 45.59 seconds
Started Jul 01 12:44:07 PM PDT 24
Finished Jul 01 12:44:53 PM PDT 24
Peak memory 199912 kb
Host smart-77d2e053-f8ad-4714-99c0-d48dd863d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814567119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1814567119
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1648067596
Short name T54
Test name
Test status
Simulation time 122343099400 ps
CPU time 79.81 seconds
Started Jul 01 12:44:13 PM PDT 24
Finished Jul 01 12:45:33 PM PDT 24
Peak memory 199864 kb
Host smart-269e0738-2f6e-4f30-a736-e4cc9a30b7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648067596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1648067596
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4269518711
Short name T736
Test name
Test status
Simulation time 144119871150 ps
CPU time 314.17 seconds
Started Jul 01 12:44:12 PM PDT 24
Finished Jul 01 12:49:28 PM PDT 24
Peak memory 199996 kb
Host smart-c59281a9-1189-4fe8-a836-cb633eaf0959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269518711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4269518711
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1161956978
Short name T482
Test name
Test status
Simulation time 13317475 ps
CPU time 0.55 seconds
Started Jul 01 12:37:13 PM PDT 24
Finished Jul 01 12:37:15 PM PDT 24
Peak memory 194556 kb
Host smart-812bc40a-eec3-4eec-831d-bf9ffdfcc8d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161956978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1161956978
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2776133185
Short name T160
Test name
Test status
Simulation time 150470886891 ps
CPU time 110.79 seconds
Started Jul 01 12:37:01 PM PDT 24
Finished Jul 01 12:38:53 PM PDT 24
Peak memory 200012 kb
Host smart-0eaae0ae-1aba-4c83-8772-9d1f1d815ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776133185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2776133185
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2713637857
Short name T36
Test name
Test status
Simulation time 78928552318 ps
CPU time 75.48 seconds
Started Jul 01 12:37:09 PM PDT 24
Finished Jul 01 12:38:25 PM PDT 24
Peak memory 199864 kb
Host smart-5d25f288-2ec4-4a3e-b460-ae106cebf6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713637857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2713637857
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3445428610
Short name T278
Test name
Test status
Simulation time 81357053838 ps
CPU time 15.14 seconds
Started Jul 01 12:37:07 PM PDT 24
Finished Jul 01 12:37:22 PM PDT 24
Peak memory 199920 kb
Host smart-de5b596f-2f73-4da9-bd15-335c94d32582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445428610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3445428610
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.4150896049
Short name T57
Test name
Test status
Simulation time 154843341147 ps
CPU time 212.94 seconds
Started Jul 01 12:37:06 PM PDT 24
Finished Jul 01 12:40:39 PM PDT 24
Peak memory 199912 kb
Host smart-4b8f7764-f606-4589-ba33-9b01337f974c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150896049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.4150896049
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2011496162
Short name T886
Test name
Test status
Simulation time 268510446231 ps
CPU time 395.03 seconds
Started Jul 01 12:37:13 PM PDT 24
Finished Jul 01 12:43:49 PM PDT 24
Peak memory 199964 kb
Host smart-1df150f7-aa84-4336-a6f7-fb832fe14eac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011496162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2011496162
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.4219803783
Short name T1100
Test name
Test status
Simulation time 9740211371 ps
CPU time 17.67 seconds
Started Jul 01 12:37:17 PM PDT 24
Finished Jul 01 12:37:37 PM PDT 24
Peak memory 199812 kb
Host smart-2c767842-e1f8-4754-8d8c-45eaed163602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219803783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.4219803783
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.15824627
Short name T1005
Test name
Test status
Simulation time 18308555825 ps
CPU time 933.22 seconds
Started Jul 01 12:37:10 PM PDT 24
Finished Jul 01 12:52:44 PM PDT 24
Peak memory 199916 kb
Host smart-3c0544c7-cd91-44bd-a905-163528960d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15824627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.15824627
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2965668789
Short name T1061
Test name
Test status
Simulation time 2606769893 ps
CPU time 18.47 seconds
Started Jul 01 12:37:07 PM PDT 24
Finished Jul 01 12:37:26 PM PDT 24
Peak memory 198132 kb
Host smart-38f9aafe-09f4-4521-8c6f-1a035941a5dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965668789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2965668789
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3153811488
Short name T862
Test name
Test status
Simulation time 218220327213 ps
CPU time 20.26 seconds
Started Jul 01 12:37:07 PM PDT 24
Finished Jul 01 12:37:28 PM PDT 24
Peak memory 199816 kb
Host smart-8cd48da7-e3d7-4ba8-9613-1e4e36def65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153811488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3153811488
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.880057436
Short name T456
Test name
Test status
Simulation time 4030178947 ps
CPU time 2.16 seconds
Started Jul 01 12:37:07 PM PDT 24
Finished Jul 01 12:37:10 PM PDT 24
Peak memory 196228 kb
Host smart-07b4e543-3e64-4917-8009-282880a61696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880057436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.880057436
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2550755397
Short name T932
Test name
Test status
Simulation time 464817418 ps
CPU time 1.29 seconds
Started Jul 01 12:37:03 PM PDT 24
Finished Jul 01 12:37:05 PM PDT 24
Peak memory 198280 kb
Host smart-f1faaef6-2721-46c5-a514-94244f0638b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550755397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2550755397
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.4248985978
Short name T172
Test name
Test status
Simulation time 164381936336 ps
CPU time 246.71 seconds
Started Jul 01 12:37:12 PM PDT 24
Finished Jul 01 12:41:20 PM PDT 24
Peak memory 199900 kb
Host smart-1cf11cb3-42a3-4808-a3cf-dc24d6d90fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248985978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.4248985978
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.450947922
Short name T879
Test name
Test status
Simulation time 223036027499 ps
CPU time 622.73 seconds
Started Jul 01 12:37:12 PM PDT 24
Finished Jul 01 12:47:36 PM PDT 24
Peak memory 216364 kb
Host smart-a22b9675-97c9-4c6a-af45-bc647d08c15d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450947922 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.450947922
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2335948097
Short name T502
Test name
Test status
Simulation time 676400792 ps
CPU time 1.41 seconds
Started Jul 01 12:37:11 PM PDT 24
Finished Jul 01 12:37:14 PM PDT 24
Peak memory 198020 kb
Host smart-d6d5cfa1-8db7-4120-84dc-d4adcb2169e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335948097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2335948097
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3646372453
Short name T1023
Test name
Test status
Simulation time 61957200117 ps
CPU time 109.82 seconds
Started Jul 01 12:37:04 PM PDT 24
Finished Jul 01 12:38:54 PM PDT 24
Peak memory 199960 kb
Host smart-4542014e-9f9b-4dce-9e78-4a3685a39fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646372453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3646372453
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3495483578
Short name T952
Test name
Test status
Simulation time 20016851976 ps
CPU time 35.03 seconds
Started Jul 01 12:44:14 PM PDT 24
Finished Jul 01 12:44:49 PM PDT 24
Peak memory 199992 kb
Host smart-9c75822d-8daa-477e-ae08-9ab781660b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495483578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3495483578
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3613754718
Short name T804
Test name
Test status
Simulation time 86930418843 ps
CPU time 125.67 seconds
Started Jul 01 12:44:14 PM PDT 24
Finished Jul 01 12:46:20 PM PDT 24
Peak memory 199900 kb
Host smart-b3c3d89c-ab4e-4a92-bcef-f5cabe9e5f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613754718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3613754718
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.168781885
Short name T442
Test name
Test status
Simulation time 79629552633 ps
CPU time 61.97 seconds
Started Jul 01 12:44:22 PM PDT 24
Finished Jul 01 12:45:25 PM PDT 24
Peak memory 199896 kb
Host smart-863a51e6-b558-452c-ae80-554d54bdbf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168781885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.168781885
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2621550461
Short name T145
Test name
Test status
Simulation time 52338491547 ps
CPU time 27.8 seconds
Started Jul 01 12:44:17 PM PDT 24
Finished Jul 01 12:44:46 PM PDT 24
Peak memory 199828 kb
Host smart-fbf8efb0-7b36-46b9-a8a2-e5ae346a9eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621550461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2621550461
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1937725864
Short name T993
Test name
Test status
Simulation time 57005331879 ps
CPU time 41.91 seconds
Started Jul 01 12:44:18 PM PDT 24
Finished Jul 01 12:45:01 PM PDT 24
Peak memory 199976 kb
Host smart-9bf25832-dd3d-40be-9685-9c7565977f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937725864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1937725864
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1548543276
Short name T268
Test name
Test status
Simulation time 44107252417 ps
CPU time 35.89 seconds
Started Jul 01 12:44:22 PM PDT 24
Finished Jul 01 12:44:59 PM PDT 24
Peak memory 199932 kb
Host smart-d173bb2e-fce8-4b87-b2e9-780b500543bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548543276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1548543276
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1891152218
Short name T225
Test name
Test status
Simulation time 64722252353 ps
CPU time 28.49 seconds
Started Jul 01 12:44:20 PM PDT 24
Finished Jul 01 12:44:49 PM PDT 24
Peak memory 199968 kb
Host smart-3362c591-a6a2-4c37-b378-d632c08e1cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891152218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1891152218
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3968345043
Short name T194
Test name
Test status
Simulation time 128220650253 ps
CPU time 164.54 seconds
Started Jul 01 12:44:17 PM PDT 24
Finished Jul 01 12:47:02 PM PDT 24
Peak memory 199964 kb
Host smart-aaa83ed2-a849-44e1-8160-a32c4594a26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968345043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3968345043
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3377658933
Short name T869
Test name
Test status
Simulation time 117835779791 ps
CPU time 57.39 seconds
Started Jul 01 12:44:17 PM PDT 24
Finished Jul 01 12:45:15 PM PDT 24
Peak memory 199932 kb
Host smart-a68d5aa7-42a5-44ce-a317-7bc288bd419a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377658933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3377658933
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3290300573
Short name T837
Test name
Test status
Simulation time 30166368014 ps
CPU time 14.15 seconds
Started Jul 01 12:44:18 PM PDT 24
Finished Jul 01 12:44:33 PM PDT 24
Peak memory 199952 kb
Host smart-ae566580-720d-457f-92ec-d21e3c29e9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290300573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3290300573
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2101021573
Short name T464
Test name
Test status
Simulation time 36651504 ps
CPU time 0.57 seconds
Started Jul 01 12:37:25 PM PDT 24
Finished Jul 01 12:37:26 PM PDT 24
Peak memory 195324 kb
Host smart-888e0e53-bb24-41bf-9ad4-57b72c51b8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101021573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2101021573
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.4033052171
Short name T844
Test name
Test status
Simulation time 91008308581 ps
CPU time 39.6 seconds
Started Jul 01 12:37:12 PM PDT 24
Finished Jul 01 12:37:53 PM PDT 24
Peak memory 199928 kb
Host smart-8dcbc408-f8d8-4238-84d7-c29cbcb96831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033052171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4033052171
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3164702499
Short name T681
Test name
Test status
Simulation time 19593361213 ps
CPU time 21.08 seconds
Started Jul 01 12:37:15 PM PDT 24
Finished Jul 01 12:37:37 PM PDT 24
Peak memory 199280 kb
Host smart-31dd6012-34de-4433-b3e7-451fac94f212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164702499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3164702499
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1480472162
Short name T1086
Test name
Test status
Simulation time 17375281261 ps
CPU time 30.05 seconds
Started Jul 01 12:37:16 PM PDT 24
Finished Jul 01 12:37:48 PM PDT 24
Peak memory 199916 kb
Host smart-c81b06ee-6387-47d9-9e22-388373bbdc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480472162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1480472162
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.4065684586
Short name T264
Test name
Test status
Simulation time 26987014824 ps
CPU time 19.98 seconds
Started Jul 01 12:37:16 PM PDT 24
Finished Jul 01 12:37:38 PM PDT 24
Peak memory 200076 kb
Host smart-8ab0bf00-573b-4671-ba54-68d104a1e296
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065684586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4065684586
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.956331091
Short name T674
Test name
Test status
Simulation time 188636284357 ps
CPU time 1176.49 seconds
Started Jul 01 12:37:21 PM PDT 24
Finished Jul 01 12:56:59 PM PDT 24
Peak memory 199932 kb
Host smart-1f7cf99a-4ce1-49df-b675-4e1024bbbf9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956331091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.956331091
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3026269903
Short name T1078
Test name
Test status
Simulation time 11280618817 ps
CPU time 5.69 seconds
Started Jul 01 12:37:24 PM PDT 24
Finished Jul 01 12:37:31 PM PDT 24
Peak memory 198936 kb
Host smart-5d7a2ad8-3f59-42d4-9d18-fe52bed5752e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026269903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3026269903
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.716162542
Short name T483
Test name
Test status
Simulation time 18394502686 ps
CPU time 1035.1 seconds
Started Jul 01 12:37:22 PM PDT 24
Finished Jul 01 12:54:38 PM PDT 24
Peak memory 199964 kb
Host smart-c7a8ca32-2ff3-4430-badd-e54d2fcafaef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716162542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.716162542
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3607015121
Short name T723
Test name
Test status
Simulation time 7308681301 ps
CPU time 29.87 seconds
Started Jul 01 12:37:17 PM PDT 24
Finished Jul 01 12:37:49 PM PDT 24
Peak memory 198524 kb
Host smart-e1b4cd97-9af9-4f80-bb42-ac95ea097ce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607015121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3607015121
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3555723877
Short name T735
Test name
Test status
Simulation time 55513885126 ps
CPU time 88.93 seconds
Started Jul 01 12:37:20 PM PDT 24
Finished Jul 01 12:38:50 PM PDT 24
Peak memory 199752 kb
Host smart-bdde63c3-e73f-487f-a824-0f9323b53b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555723877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3555723877
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2420613521
Short name T1062
Test name
Test status
Simulation time 6115320328 ps
CPU time 8.97 seconds
Started Jul 01 12:37:21 PM PDT 24
Finished Jul 01 12:37:32 PM PDT 24
Peak memory 196688 kb
Host smart-71f41db5-9421-4e68-927d-f4ec9067ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420613521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2420613521
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1686540782
Short name T964
Test name
Test status
Simulation time 5798365982 ps
CPU time 27.58 seconds
Started Jul 01 12:37:11 PM PDT 24
Finished Jul 01 12:37:39 PM PDT 24
Peak memory 199036 kb
Host smart-bba5f784-3d00-4376-8cc1-4f7ea6279d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686540782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1686540782
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2380662020
Short name T907
Test name
Test status
Simulation time 33692796944 ps
CPU time 190.82 seconds
Started Jul 01 12:37:25 PM PDT 24
Finished Jul 01 12:40:36 PM PDT 24
Peak memory 199964 kb
Host smart-e7ae87e2-8bee-466e-8758-4a0b564377a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380662020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2380662020
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.119832085
Short name T29
Test name
Test status
Simulation time 45096088553 ps
CPU time 277.18 seconds
Started Jul 01 12:37:25 PM PDT 24
Finished Jul 01 12:42:03 PM PDT 24
Peak memory 215516 kb
Host smart-a90a4c71-7e8e-49e9-8041-32035d0a2650
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119832085 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.119832085
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.4261215239
Short name T856
Test name
Test status
Simulation time 1659079733 ps
CPU time 1.44 seconds
Started Jul 01 12:37:24 PM PDT 24
Finished Jul 01 12:37:26 PM PDT 24
Peak memory 198332 kb
Host smart-dd5aa5c7-bf8e-4611-b51b-601b930ceb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261215239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.4261215239
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.665491410
Short name T494
Test name
Test status
Simulation time 47519097108 ps
CPU time 70.16 seconds
Started Jul 01 12:37:12 PM PDT 24
Finished Jul 01 12:38:23 PM PDT 24
Peak memory 199968 kb
Host smart-7438bb70-f1ee-4bb7-9a12-744000bdf588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665491410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.665491410
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3016709470
Short name T960
Test name
Test status
Simulation time 137729767722 ps
CPU time 49.68 seconds
Started Jul 01 12:44:22 PM PDT 24
Finished Jul 01 12:45:12 PM PDT 24
Peak memory 199988 kb
Host smart-c8ad78f5-e82e-4fde-a7e6-57735914fda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016709470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3016709470
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1996132298
Short name T1029
Test name
Test status
Simulation time 105699477531 ps
CPU time 259.85 seconds
Started Jul 01 12:44:16 PM PDT 24
Finished Jul 01 12:48:37 PM PDT 24
Peak memory 199996 kb
Host smart-11a3ff72-52b6-4ed0-8ba3-10ac36c7b2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996132298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1996132298
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2887620551
Short name T246
Test name
Test status
Simulation time 95626155036 ps
CPU time 235.49 seconds
Started Jul 01 12:44:23 PM PDT 24
Finished Jul 01 12:48:19 PM PDT 24
Peak memory 199980 kb
Host smart-39505eea-79df-4a4f-870c-0e9a16d93bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887620551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2887620551
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2258732994
Short name T825
Test name
Test status
Simulation time 197077963552 ps
CPU time 282.91 seconds
Started Jul 01 12:44:23 PM PDT 24
Finished Jul 01 12:49:06 PM PDT 24
Peak memory 199980 kb
Host smart-48869206-c500-40b3-84e7-d13edca2c9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258732994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2258732994
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3923976915
Short name T1031
Test name
Test status
Simulation time 181778604616 ps
CPU time 146.32 seconds
Started Jul 01 12:44:23 PM PDT 24
Finished Jul 01 12:46:50 PM PDT 24
Peak memory 200004 kb
Host smart-8df845e2-11d4-45b8-9e39-47160ace92db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923976915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3923976915
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3570870685
Short name T759
Test name
Test status
Simulation time 17992758833 ps
CPU time 32.51 seconds
Started Jul 01 12:44:23 PM PDT 24
Finished Jul 01 12:44:56 PM PDT 24
Peak memory 200068 kb
Host smart-05f4ce35-aeb5-42a7-9b17-c68841e5fb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570870685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3570870685
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.4037383037
Short name T192
Test name
Test status
Simulation time 16771095064 ps
CPU time 15.53 seconds
Started Jul 01 12:44:27 PM PDT 24
Finished Jul 01 12:44:43 PM PDT 24
Peak memory 199960 kb
Host smart-91b48cb9-fcdb-4147-a235-20b403f58dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037383037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.4037383037
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3825281385
Short name T224
Test name
Test status
Simulation time 106461995241 ps
CPU time 49.68 seconds
Started Jul 01 12:44:30 PM PDT 24
Finished Jul 01 12:45:20 PM PDT 24
Peak memory 200116 kb
Host smart-4f20a653-3658-41f6-826d-49371d221b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825281385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3825281385
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.605438956
Short name T926
Test name
Test status
Simulation time 10987254834 ps
CPU time 25.13 seconds
Started Jul 01 12:44:27 PM PDT 24
Finished Jul 01 12:44:52 PM PDT 24
Peak memory 199980 kb
Host smart-8e8e5617-60ca-4efe-9d34-97107b2a2f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605438956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.605438956
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2090503458
Short name T884
Test name
Test status
Simulation time 12392382 ps
CPU time 0.56 seconds
Started Jul 01 12:37:30 PM PDT 24
Finished Jul 01 12:37:32 PM PDT 24
Peak memory 195596 kb
Host smart-9dc94337-6348-41e5-8797-c4842e7fc93e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090503458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2090503458
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1550330272
Short name T272
Test name
Test status
Simulation time 83135942019 ps
CPU time 60.91 seconds
Started Jul 01 12:37:25 PM PDT 24
Finished Jul 01 12:38:27 PM PDT 24
Peak memory 199912 kb
Host smart-c0226850-c4e7-4a3c-ab79-77cdb6769a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550330272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1550330272
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3348681894
Short name T481
Test name
Test status
Simulation time 149002543778 ps
CPU time 40.59 seconds
Started Jul 01 12:37:26 PM PDT 24
Finished Jul 01 12:38:08 PM PDT 24
Peak memory 199944 kb
Host smart-09ff9e31-86e4-4c87-b1e0-35312b73f57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348681894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3348681894
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2909542712
Short name T665
Test name
Test status
Simulation time 49442878615 ps
CPU time 32.44 seconds
Started Jul 01 12:37:28 PM PDT 24
Finished Jul 01 12:38:01 PM PDT 24
Peak memory 199876 kb
Host smart-d5a519bb-e32b-4de9-b66e-c9b53a904a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909542712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2909542712
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1757906567
Short name T25
Test name
Test status
Simulation time 26474553653 ps
CPU time 34.56 seconds
Started Jul 01 12:37:27 PM PDT 24
Finished Jul 01 12:38:02 PM PDT 24
Peak memory 198360 kb
Host smart-a5504c07-ff86-49e0-91e9-f73657d84d81
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757906567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1757906567
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2658696558
Short name T489
Test name
Test status
Simulation time 74581974394 ps
CPU time 187.43 seconds
Started Jul 01 12:37:30 PM PDT 24
Finished Jul 01 12:40:39 PM PDT 24
Peak memory 199960 kb
Host smart-67c3078e-7964-4021-89a0-2b6bfd402334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658696558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2658696558
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3870410152
Short name T1003
Test name
Test status
Simulation time 1633535722 ps
CPU time 1.89 seconds
Started Jul 01 12:37:31 PM PDT 24
Finished Jul 01 12:37:34 PM PDT 24
Peak memory 197356 kb
Host smart-3f67603b-d54e-4fc1-a6d8-8a01964a054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870410152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3870410152
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.1017394
Short name T307
Test name
Test status
Simulation time 15815542979 ps
CPU time 190.15 seconds
Started Jul 01 12:37:31 PM PDT 24
Finished Jul 01 12:40:42 PM PDT 24
Peak memory 199956 kb
Host smart-95f1867d-9835-4dad-bd90-60790d9de47d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1017394
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1447471693
Short name T1050
Test name
Test status
Simulation time 1393202330 ps
CPU time 1.06 seconds
Started Jul 01 12:37:27 PM PDT 24
Finished Jul 01 12:37:29 PM PDT 24
Peak memory 195596 kb
Host smart-82d486fd-2cb2-4f46-a930-4fafc1d82fcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447471693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1447471693
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2247658591
Short name T888
Test name
Test status
Simulation time 116231727598 ps
CPU time 176.41 seconds
Started Jul 01 12:37:32 PM PDT 24
Finished Jul 01 12:40:29 PM PDT 24
Peak memory 199972 kb
Host smart-910b73ef-80a3-4dd8-99ac-0e805d28f35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247658591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2247658591
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.877253554
Short name T788
Test name
Test status
Simulation time 2940746407 ps
CPU time 2.89 seconds
Started Jul 01 12:37:27 PM PDT 24
Finished Jul 01 12:37:30 PM PDT 24
Peak memory 196400 kb
Host smart-666b5271-2ce4-4830-b713-49d90e2f4f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877253554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.877253554
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1638621659
Short name T543
Test name
Test status
Simulation time 6411153543 ps
CPU time 4.89 seconds
Started Jul 01 12:37:25 PM PDT 24
Finished Jul 01 12:37:31 PM PDT 24
Peak memory 199928 kb
Host smart-3cee82f0-3606-4022-aa60-3ffc17b39091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638621659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1638621659
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3079975106
Short name T169
Test name
Test status
Simulation time 151303031860 ps
CPU time 341.66 seconds
Started Jul 01 12:37:30 PM PDT 24
Finished Jul 01 12:43:12 PM PDT 24
Peak memory 199948 kb
Host smart-48e8e436-09e2-4e58-8b58-31406ea12091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079975106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3079975106
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.851118491
Short name T953
Test name
Test status
Simulation time 51746720105 ps
CPU time 247.16 seconds
Started Jul 01 12:37:31 PM PDT 24
Finished Jul 01 12:41:39 PM PDT 24
Peak memory 216024 kb
Host smart-0a0cc4fc-2f1c-42bf-aceb-71fa6af18b76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851118491 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.851118491
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2254150640
Short name T695
Test name
Test status
Simulation time 6865159114 ps
CPU time 33.99 seconds
Started Jul 01 12:37:30 PM PDT 24
Finished Jul 01 12:38:05 PM PDT 24
Peak memory 199888 kb
Host smart-13c22a28-5179-4289-b8e7-96a24f4364e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254150640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2254150640
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1429929599
Short name T787
Test name
Test status
Simulation time 44584483660 ps
CPU time 79.35 seconds
Started Jul 01 12:37:27 PM PDT 24
Finished Jul 01 12:38:48 PM PDT 24
Peak memory 199968 kb
Host smart-2ce5f565-7283-4914-940e-8b4f2aed1389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429929599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1429929599
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1380859768
Short name T370
Test name
Test status
Simulation time 123835448954 ps
CPU time 216.59 seconds
Started Jul 01 12:44:27 PM PDT 24
Finished Jul 01 12:48:04 PM PDT 24
Peak memory 199956 kb
Host smart-bbfc0a1e-1224-4d71-8118-7885e755265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380859768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1380859768
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2009500215
Short name T356
Test name
Test status
Simulation time 41661062669 ps
CPU time 67.52 seconds
Started Jul 01 12:44:32 PM PDT 24
Finished Jul 01 12:45:40 PM PDT 24
Peak memory 199980 kb
Host smart-182cdd95-ecfd-4bf8-8740-85633dbd2fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009500215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2009500215
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1737521019
Short name T199
Test name
Test status
Simulation time 47874716001 ps
CPU time 68.1 seconds
Started Jul 01 12:44:33 PM PDT 24
Finished Jul 01 12:45:42 PM PDT 24
Peak memory 199868 kb
Host smart-55437dc6-8cf6-4d69-a9f0-e393a39ff782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737521019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1737521019
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.131727848
Short name T731
Test name
Test status
Simulation time 133523013743 ps
CPU time 41.13 seconds
Started Jul 01 12:44:34 PM PDT 24
Finished Jul 01 12:45:16 PM PDT 24
Peak memory 200152 kb
Host smart-19ea6a2b-e0e6-4214-a0a3-1e7537787985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131727848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.131727848
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2126663432
Short name T436
Test name
Test status
Simulation time 34862620956 ps
CPU time 106.33 seconds
Started Jul 01 12:44:33 PM PDT 24
Finished Jul 01 12:46:20 PM PDT 24
Peak memory 199996 kb
Host smart-6feab5ae-5bea-461e-ba4f-3d3dbd7b0d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126663432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2126663432
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.4061988432
Short name T881
Test name
Test status
Simulation time 127998164887 ps
CPU time 213.54 seconds
Started Jul 01 12:44:32 PM PDT 24
Finished Jul 01 12:48:06 PM PDT 24
Peak memory 199828 kb
Host smart-c8d2ce2d-d3ef-419d-8f42-b9b7a06efa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061988432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.4061988432
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3065358727
Short name T234
Test name
Test status
Simulation time 31198285067 ps
CPU time 20.5 seconds
Started Jul 01 12:44:32 PM PDT 24
Finished Jul 01 12:44:53 PM PDT 24
Peak memory 199992 kb
Host smart-61fa7c20-eefc-4b5b-bf7b-632c1606dd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065358727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3065358727
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_full.795458814
Short name T947
Test name
Test status
Simulation time 20446659956 ps
CPU time 23.72 seconds
Started Jul 01 12:37:36 PM PDT 24
Finished Jul 01 12:38:00 PM PDT 24
Peak memory 199884 kb
Host smart-ff8271ba-4c8a-4c73-ae89-a62b2df69bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795458814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.795458814
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3868872668
Short name T864
Test name
Test status
Simulation time 61431225170 ps
CPU time 49.12 seconds
Started Jul 01 12:37:37 PM PDT 24
Finished Jul 01 12:38:27 PM PDT 24
Peak memory 199696 kb
Host smart-121067f3-a74e-4f42-8d2e-a93ff7429b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868872668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3868872668
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3027141336
Short name T136
Test name
Test status
Simulation time 11125666863 ps
CPU time 10.15 seconds
Started Jul 01 12:37:37 PM PDT 24
Finished Jul 01 12:37:48 PM PDT 24
Peak memory 199708 kb
Host smart-7eb0dea9-3dc0-447c-9900-ca1c989cec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027141336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3027141336
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3531753009
Short name T318
Test name
Test status
Simulation time 45160281186 ps
CPU time 20.75 seconds
Started Jul 01 12:37:40 PM PDT 24
Finished Jul 01 12:38:01 PM PDT 24
Peak memory 199940 kb
Host smart-93e17e97-5a29-4f9a-bf31-30df9ae0d90b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531753009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3531753009
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3511560155
Short name T465
Test name
Test status
Simulation time 69209892513 ps
CPU time 103.18 seconds
Started Jul 01 12:37:45 PM PDT 24
Finished Jul 01 12:39:29 PM PDT 24
Peak memory 199900 kb
Host smart-920aa738-e3a2-4bf4-8764-58c9ca73d87c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511560155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3511560155
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.4285521195
Short name T799
Test name
Test status
Simulation time 1757242465 ps
CPU time 3.66 seconds
Started Jul 01 12:37:43 PM PDT 24
Finished Jul 01 12:37:47 PM PDT 24
Peak memory 198700 kb
Host smart-dbc9e88a-7f08-494f-88d5-e1790dffc458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285521195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.4285521195
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.2385414008
Short name T652
Test name
Test status
Simulation time 24602705687 ps
CPU time 1246.29 seconds
Started Jul 01 12:37:44 PM PDT 24
Finished Jul 01 12:58:31 PM PDT 24
Peak memory 199852 kb
Host smart-b77a3539-8060-4878-8bcb-e2735e47a9f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385414008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2385414008
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3020906992
Short name T329
Test name
Test status
Simulation time 3150981488 ps
CPU time 18.51 seconds
Started Jul 01 12:37:35 PM PDT 24
Finished Jul 01 12:37:54 PM PDT 24
Peak memory 198428 kb
Host smart-e55c4d62-2ba1-4c54-8481-cea13c8ddfc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020906992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3020906992
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.4056707457
Short name T43
Test name
Test status
Simulation time 96229704828 ps
CPU time 30.57 seconds
Started Jul 01 12:37:41 PM PDT 24
Finished Jul 01 12:38:12 PM PDT 24
Peak memory 199612 kb
Host smart-1faf5cdf-58b8-4382-90d4-b1c82de46172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056707457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4056707457
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1349437429
Short name T301
Test name
Test status
Simulation time 3928951634 ps
CPU time 2.05 seconds
Started Jul 01 12:37:45 PM PDT 24
Finished Jul 01 12:37:48 PM PDT 24
Peak memory 196384 kb
Host smart-c00902fd-355f-46e4-9bf5-3e60fa7ac9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349437429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1349437429
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1332205732
Short name T1084
Test name
Test status
Simulation time 811415488 ps
CPU time 2.55 seconds
Started Jul 01 12:37:33 PM PDT 24
Finished Jul 01 12:37:36 PM PDT 24
Peak memory 198720 kb
Host smart-1d4f90f6-2f7b-4c98-8426-6e2112bfebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332205732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1332205732
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3234691519
Short name T769
Test name
Test status
Simulation time 147359332479 ps
CPU time 617.95 seconds
Started Jul 01 12:37:41 PM PDT 24
Finished Jul 01 12:47:59 PM PDT 24
Peak memory 216560 kb
Host smart-1d1c35e9-a289-414c-844e-dd52227b0529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234691519 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3234691519
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2615967564
Short name T948
Test name
Test status
Simulation time 612107599 ps
CPU time 2.05 seconds
Started Jul 01 12:37:42 PM PDT 24
Finished Jul 01 12:37:45 PM PDT 24
Peak memory 198496 kb
Host smart-97e945a7-cd91-4909-bc50-c6cbd06aadf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615967564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2615967564
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.959365763
Short name T639
Test name
Test status
Simulation time 161063472772 ps
CPU time 18.58 seconds
Started Jul 01 12:37:37 PM PDT 24
Finished Jul 01 12:37:56 PM PDT 24
Peak memory 199836 kb
Host smart-c517f0e2-6053-42b5-ab63-a2568de35a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959365763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.959365763
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1460382077
Short name T487
Test name
Test status
Simulation time 47068201768 ps
CPU time 30.08 seconds
Started Jul 01 12:44:39 PM PDT 24
Finished Jul 01 12:45:10 PM PDT 24
Peak memory 199652 kb
Host smart-0324c044-fb93-4373-b678-f90b6210fa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460382077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1460382077
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2096358670
Short name T1025
Test name
Test status
Simulation time 218761194801 ps
CPU time 25.93 seconds
Started Jul 01 12:44:38 PM PDT 24
Finished Jul 01 12:45:04 PM PDT 24
Peak memory 199908 kb
Host smart-6d68f248-a3b3-48e9-812a-7f7c89be3c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096358670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2096358670
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.410101273
Short name T1041
Test name
Test status
Simulation time 105892537755 ps
CPU time 143.73 seconds
Started Jul 01 12:44:39 PM PDT 24
Finished Jul 01 12:47:03 PM PDT 24
Peak memory 200008 kb
Host smart-4f97f39e-82d9-48c9-adef-ae3bcd067ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410101273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.410101273
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.155437177
Short name T120
Test name
Test status
Simulation time 19227482725 ps
CPU time 39.09 seconds
Started Jul 01 12:44:38 PM PDT 24
Finished Jul 01 12:45:17 PM PDT 24
Peak memory 199864 kb
Host smart-404eeb24-fa37-433c-8b33-406c0d38591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155437177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.155437177
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.97044313
Short name T5
Test name
Test status
Simulation time 48489360015 ps
CPU time 10.6 seconds
Started Jul 01 12:44:48 PM PDT 24
Finished Jul 01 12:45:00 PM PDT 24
Peak memory 199652 kb
Host smart-2eac06a2-9989-402e-91a6-48ee5426a674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97044313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.97044313
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2832879179
Short name T895
Test name
Test status
Simulation time 107992774946 ps
CPU time 99.2 seconds
Started Jul 01 12:44:43 PM PDT 24
Finished Jul 01 12:46:23 PM PDT 24
Peak memory 199912 kb
Host smart-a48700fa-e931-4f96-9ddb-caddd33f21f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832879179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2832879179
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2166441179
Short name T923
Test name
Test status
Simulation time 36618362757 ps
CPU time 17.45 seconds
Started Jul 01 12:44:47 PM PDT 24
Finished Jul 01 12:45:06 PM PDT 24
Peak memory 199940 kb
Host smart-6ca09370-4524-4fa8-b6e2-e3cf543a07b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166441179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2166441179
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3092647148
Short name T72
Test name
Test status
Simulation time 36662236795 ps
CPU time 59.94 seconds
Started Jul 01 12:44:43 PM PDT 24
Finished Jul 01 12:45:44 PM PDT 24
Peak memory 199980 kb
Host smart-919a3433-e502-44d0-af28-21d43ae3cbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092647148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3092647148
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1187866825
Short name T401
Test name
Test status
Simulation time 11634960 ps
CPU time 0.58 seconds
Started Jul 01 12:37:50 PM PDT 24
Finished Jul 01 12:37:51 PM PDT 24
Peak memory 195288 kb
Host smart-f59989e0-f825-4ec4-b623-45a6cd672983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187866825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1187866825
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.470354029
Short name T748
Test name
Test status
Simulation time 154419838433 ps
CPU time 502.54 seconds
Started Jul 01 12:37:45 PM PDT 24
Finished Jul 01 12:46:09 PM PDT 24
Peak memory 200088 kb
Host smart-380d4d1b-442b-4dfe-9523-448fa4501273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470354029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.470354029
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3424322552
Short name T1063
Test name
Test status
Simulation time 112341113820 ps
CPU time 88.77 seconds
Started Jul 01 12:37:46 PM PDT 24
Finished Jul 01 12:39:15 PM PDT 24
Peak memory 199996 kb
Host smart-70c8b9c2-a5dd-4f4a-a33c-eb17a1e1c23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424322552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3424322552
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.317902054
Short name T586
Test name
Test status
Simulation time 73197342310 ps
CPU time 24.29 seconds
Started Jul 01 12:37:45 PM PDT 24
Finished Jul 01 12:38:10 PM PDT 24
Peak memory 199964 kb
Host smart-1d3a4397-6862-4a09-bd3e-3e8827c6a7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317902054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.317902054
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.231123913
Short name T292
Test name
Test status
Simulation time 264005883684 ps
CPU time 126.53 seconds
Started Jul 01 12:37:44 PM PDT 24
Finished Jul 01 12:39:51 PM PDT 24
Peak memory 199888 kb
Host smart-b87a1c1f-8d6c-462d-99d0-695735bfb13c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231123913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.231123913
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2782542323
Short name T109
Test name
Test status
Simulation time 79902088817 ps
CPU time 212.38 seconds
Started Jul 01 12:37:54 PM PDT 24
Finished Jul 01 12:41:27 PM PDT 24
Peak memory 200060 kb
Host smart-55675bb3-4f0f-4e7f-88a7-e27ac081b8b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782542323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2782542323
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3205658265
Short name T554
Test name
Test status
Simulation time 5583718214 ps
CPU time 5.88 seconds
Started Jul 01 12:37:50 PM PDT 24
Finished Jul 01 12:37:57 PM PDT 24
Peak memory 198604 kb
Host smart-aed87307-828e-476a-b8f2-c7da32bf443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205658265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3205658265
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.3350472199
Short name T627
Test name
Test status
Simulation time 8555000611 ps
CPU time 119 seconds
Started Jul 01 12:37:53 PM PDT 24
Finished Jul 01 12:39:52 PM PDT 24
Peak memory 199980 kb
Host smart-58fff378-f3a6-4953-9500-86fe11971bf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350472199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3350472199
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1605546562
Short name T772
Test name
Test status
Simulation time 4700423944 ps
CPU time 3.06 seconds
Started Jul 01 12:37:45 PM PDT 24
Finished Jul 01 12:37:49 PM PDT 24
Peak memory 198728 kb
Host smart-dfc28ae7-2fc9-40a3-a59c-33f7d9a4817b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605546562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1605546562
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3401796189
Short name T477
Test name
Test status
Simulation time 55896915298 ps
CPU time 91.48 seconds
Started Jul 01 12:37:49 PM PDT 24
Finished Jul 01 12:39:21 PM PDT 24
Peak memory 199956 kb
Host smart-fc5d3c21-049a-477d-914a-2089be8dba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401796189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3401796189
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1741037439
Short name T664
Test name
Test status
Simulation time 2690302728 ps
CPU time 4.2 seconds
Started Jul 01 12:37:45 PM PDT 24
Finished Jul 01 12:37:50 PM PDT 24
Peak memory 196496 kb
Host smart-ee89aba2-ed61-49b5-b704-c67760008c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741037439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1741037439
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3537103749
Short name T676
Test name
Test status
Simulation time 6253541436 ps
CPU time 23.65 seconds
Started Jul 01 12:37:41 PM PDT 24
Finished Jul 01 12:38:05 PM PDT 24
Peak memory 199604 kb
Host smart-9ddb92b7-c363-4803-9dec-95944cd50454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537103749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3537103749
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.284038079
Short name T544
Test name
Test status
Simulation time 988237671 ps
CPU time 1.8 seconds
Started Jul 01 12:37:53 PM PDT 24
Finished Jul 01 12:37:55 PM PDT 24
Peak memory 198228 kb
Host smart-1b7ff48d-7cc7-4fa8-9b87-23e9a6cf8222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284038079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.284038079
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3177443399
Short name T719
Test name
Test status
Simulation time 110063544292 ps
CPU time 13.86 seconds
Started Jul 01 12:37:45 PM PDT 24
Finished Jul 01 12:37:59 PM PDT 24
Peak memory 199872 kb
Host smart-74034c0a-58b3-4e95-86a2-e88e1baca986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177443399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3177443399
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3033588724
Short name T628
Test name
Test status
Simulation time 24370542938 ps
CPU time 28.08 seconds
Started Jul 01 12:44:47 PM PDT 24
Finished Jul 01 12:45:17 PM PDT 24
Peak memory 199916 kb
Host smart-c812d851-7b38-4886-b1c9-20bb06f32cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033588724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3033588724
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1407341437
Short name T767
Test name
Test status
Simulation time 72824759601 ps
CPU time 30.71 seconds
Started Jul 01 12:44:48 PM PDT 24
Finished Jul 01 12:45:21 PM PDT 24
Peak memory 199740 kb
Host smart-58aea0d1-6574-4cad-9a59-34466c10c6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407341437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1407341437
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1648259620
Short name T1016
Test name
Test status
Simulation time 124828020431 ps
CPU time 52.95 seconds
Started Jul 01 12:44:48 PM PDT 24
Finished Jul 01 12:45:43 PM PDT 24
Peak memory 199948 kb
Host smart-8a64c591-b569-4e90-8443-3e0fcc1b07b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648259620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1648259620
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1374053735
Short name T631
Test name
Test status
Simulation time 223242259013 ps
CPU time 26.95 seconds
Started Jul 01 12:44:48 PM PDT 24
Finished Jul 01 12:45:17 PM PDT 24
Peak memory 199972 kb
Host smart-bbde4171-8a25-4fe2-bf6d-81c916a0231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374053735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1374053735
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1087982021
Short name T972
Test name
Test status
Simulation time 142063328486 ps
CPU time 47.57 seconds
Started Jul 01 12:44:49 PM PDT 24
Finished Jul 01 12:45:38 PM PDT 24
Peak memory 199940 kb
Host smart-fe24edf2-dee9-457b-b4a7-2daee074063c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087982021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1087982021
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3897384643
Short name T764
Test name
Test status
Simulation time 121511373714 ps
CPU time 197.88 seconds
Started Jul 01 12:44:48 PM PDT 24
Finished Jul 01 12:48:07 PM PDT 24
Peak memory 200020 kb
Host smart-6693bc49-f15b-4190-89df-6ebc412483e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897384643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3897384643
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1931380047
Short name T386
Test name
Test status
Simulation time 20939984694 ps
CPU time 34.51 seconds
Started Jul 01 12:44:49 PM PDT 24
Finished Jul 01 12:45:25 PM PDT 24
Peak memory 199832 kb
Host smart-b8185a8d-4558-474b-b3b6-b9e02d55992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931380047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1931380047
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1197085405
Short name T212
Test name
Test status
Simulation time 62844141840 ps
CPU time 45.09 seconds
Started Jul 01 12:44:50 PM PDT 24
Finished Jul 01 12:45:36 PM PDT 24
Peak memory 199880 kb
Host smart-d08219be-6d2c-4bb3-a797-ac9ff3635e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197085405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1197085405
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.4136398357
Short name T958
Test name
Test status
Simulation time 88012646334 ps
CPU time 99.77 seconds
Started Jul 01 12:44:47 PM PDT 24
Finished Jul 01 12:46:28 PM PDT 24
Peak memory 199908 kb
Host smart-f759674f-ed0c-4692-bbb6-31ab63169da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136398357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4136398357
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2112171348
Short name T588
Test name
Test status
Simulation time 14511610 ps
CPU time 0.56 seconds
Started Jul 01 12:38:01 PM PDT 24
Finished Jul 01 12:38:02 PM PDT 24
Peak memory 195324 kb
Host smart-ff28f97a-d454-458e-afe3-35835e333132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112171348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2112171348
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.4248746465
Short name T164
Test name
Test status
Simulation time 113505393889 ps
CPU time 27.2 seconds
Started Jul 01 12:37:58 PM PDT 24
Finished Jul 01 12:38:26 PM PDT 24
Peak memory 199892 kb
Host smart-21382b97-eb38-42aa-b022-bc152fe0fbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248746465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4248746465
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3871984753
Short name T944
Test name
Test status
Simulation time 65036462404 ps
CPU time 87.25 seconds
Started Jul 01 12:37:55 PM PDT 24
Finished Jul 01 12:39:23 PM PDT 24
Peak memory 199916 kb
Host smart-d8c2dce0-8f1e-4c6a-bbb2-9f553a529622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871984753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3871984753
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3121617794
Short name T229
Test name
Test status
Simulation time 49257473364 ps
CPU time 21.51 seconds
Started Jul 01 12:37:59 PM PDT 24
Finished Jul 01 12:38:21 PM PDT 24
Peak memory 199928 kb
Host smart-82fd6674-c686-4a3f-89b9-2888757d543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121617794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3121617794
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2536329764
Short name T1099
Test name
Test status
Simulation time 8959530700 ps
CPU time 17.23 seconds
Started Jul 01 12:37:55 PM PDT 24
Finished Jul 01 12:38:13 PM PDT 24
Peak memory 199968 kb
Host smart-47236ac3-c5db-44cf-bb72-3c2cdb9c49b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536329764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2536329764
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2977790711
Short name T985
Test name
Test status
Simulation time 117713262261 ps
CPU time 149.82 seconds
Started Jul 01 12:38:01 PM PDT 24
Finished Jul 01 12:40:32 PM PDT 24
Peak memory 199944 kb
Host smart-5a8b881e-fdb6-48a7-8b82-781b6ed3e9c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977790711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2977790711
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3540295781
Short name T345
Test name
Test status
Simulation time 9331154528 ps
CPU time 13.61 seconds
Started Jul 01 12:38:01 PM PDT 24
Finished Jul 01 12:38:16 PM PDT 24
Peak memory 199396 kb
Host smart-eb77e4c4-bc8e-4b3a-9d97-960987e2f23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540295781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3540295781
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.131372445
Short name T408
Test name
Test status
Simulation time 12465746067 ps
CPU time 548.22 seconds
Started Jul 01 12:38:02 PM PDT 24
Finished Jul 01 12:47:11 PM PDT 24
Peak memory 199924 kb
Host smart-62bf04a6-c7b2-429b-b2d4-8b4c7468d0c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131372445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.131372445
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2170868974
Short name T342
Test name
Test status
Simulation time 5374948109 ps
CPU time 12.68 seconds
Started Jul 01 12:37:55 PM PDT 24
Finished Jul 01 12:38:08 PM PDT 24
Peak memory 199444 kb
Host smart-f24ad792-b880-4b5e-bec2-aea0396dfcdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170868974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2170868974
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2458261418
Short name T761
Test name
Test status
Simulation time 127790464332 ps
CPU time 210.63 seconds
Started Jul 01 12:37:56 PM PDT 24
Finished Jul 01 12:41:27 PM PDT 24
Peak memory 200012 kb
Host smart-3a126545-97ad-4e26-be1b-950136561875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458261418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2458261418
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1709836444
Short name T463
Test name
Test status
Simulation time 5122841972 ps
CPU time 2.68 seconds
Started Jul 01 12:37:56 PM PDT 24
Finished Jul 01 12:37:59 PM PDT 24
Peak memory 196080 kb
Host smart-269e8b4e-648d-4646-9f79-d5d82892ca3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709836444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1709836444
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.148557439
Short name T331
Test name
Test status
Simulation time 5447374786 ps
CPU time 14.64 seconds
Started Jul 01 12:37:50 PM PDT 24
Finished Jul 01 12:38:05 PM PDT 24
Peak memory 199796 kb
Host smart-908393ed-27f4-403a-b4e7-3c13d7222b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148557439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.148557439
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1760988062
Short name T555
Test name
Test status
Simulation time 736462536 ps
CPU time 2.75 seconds
Started Jul 01 12:37:57 PM PDT 24
Finished Jul 01 12:38:00 PM PDT 24
Peak memory 199820 kb
Host smart-2147427e-aee2-42b8-bb75-33af281b0072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760988062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1760988062
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2011152630
Short name T560
Test name
Test status
Simulation time 62445654276 ps
CPU time 99.34 seconds
Started Jul 01 12:37:56 PM PDT 24
Finished Jul 01 12:39:36 PM PDT 24
Peak memory 199920 kb
Host smart-965c8626-5fa2-4a12-b221-490639b51fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011152630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2011152630
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3355645915
Short name T906
Test name
Test status
Simulation time 78459163837 ps
CPU time 299.94 seconds
Started Jul 01 12:44:49 PM PDT 24
Finished Jul 01 12:49:51 PM PDT 24
Peak memory 200152 kb
Host smart-a17b65c7-4427-4bfd-b507-dc77aab0d866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355645915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3355645915
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2273125554
Short name T842
Test name
Test status
Simulation time 29013770878 ps
CPU time 46.69 seconds
Started Jul 01 12:44:55 PM PDT 24
Finished Jul 01 12:45:42 PM PDT 24
Peak memory 199980 kb
Host smart-5a188ec6-779f-4f1f-b02d-f0fa39203dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273125554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2273125554
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1169322242
Short name T265
Test name
Test status
Simulation time 23532937987 ps
CPU time 52.01 seconds
Started Jul 01 12:44:52 PM PDT 24
Finished Jul 01 12:45:45 PM PDT 24
Peak memory 199892 kb
Host smart-43a74751-e714-41b8-a708-fdb487efd687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169322242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1169322242
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2483229802
Short name T1072
Test name
Test status
Simulation time 223618029727 ps
CPU time 91.6 seconds
Started Jul 01 12:44:54 PM PDT 24
Finished Jul 01 12:46:27 PM PDT 24
Peak memory 199980 kb
Host smart-81d3e768-2d67-4277-a5c8-9991b6da3636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483229802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2483229802
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4188593679
Short name T757
Test name
Test status
Simulation time 54593184639 ps
CPU time 22.16 seconds
Started Jul 01 12:44:52 PM PDT 24
Finished Jul 01 12:45:15 PM PDT 24
Peak memory 199916 kb
Host smart-100c9606-f213-40db-97b3-b89a2fc5cabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188593679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4188593679
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2211144757
Short name T878
Test name
Test status
Simulation time 74620331560 ps
CPU time 24.68 seconds
Started Jul 01 12:44:54 PM PDT 24
Finished Jul 01 12:45:19 PM PDT 24
Peak memory 199888 kb
Host smart-db1eebcd-8b45-4892-8efb-3655734b7c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211144757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2211144757
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.138479523
Short name T786
Test name
Test status
Simulation time 44519991233 ps
CPU time 60.68 seconds
Started Jul 01 12:44:52 PM PDT 24
Finished Jul 01 12:45:54 PM PDT 24
Peak memory 199864 kb
Host smart-4bfe60a1-b552-49ee-b566-f8f2ccba2594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138479523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.138479523
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2695414320
Short name T851
Test name
Test status
Simulation time 12140793 ps
CPU time 0.56 seconds
Started Jul 01 12:35:35 PM PDT 24
Finished Jul 01 12:35:37 PM PDT 24
Peak memory 194732 kb
Host smart-7c260409-65f5-4d11-aa83-24295f169cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695414320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2695414320
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3692868580
Short name T610
Test name
Test status
Simulation time 101357471290 ps
CPU time 32.49 seconds
Started Jul 01 12:35:30 PM PDT 24
Finished Jul 01 12:36:03 PM PDT 24
Peak memory 199948 kb
Host smart-597987c4-9260-40c3-9670-f1214cb42c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692868580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3692868580
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3973378814
Short name T716
Test name
Test status
Simulation time 213062174486 ps
CPU time 53.69 seconds
Started Jul 01 12:35:35 PM PDT 24
Finished Jul 01 12:36:30 PM PDT 24
Peak memory 199552 kb
Host smart-a7324086-4cf4-430b-ba27-d939ec2dac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973378814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3973378814
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2485843852
Short name T980
Test name
Test status
Simulation time 34644198334 ps
CPU time 13.91 seconds
Started Jul 01 12:35:32 PM PDT 24
Finished Jul 01 12:35:47 PM PDT 24
Peak memory 199976 kb
Host smart-f620aa77-cda0-42ab-b867-71851fc62a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485843852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2485843852
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.135206733
Short name T709
Test name
Test status
Simulation time 41114212134 ps
CPU time 17.73 seconds
Started Jul 01 12:35:30 PM PDT 24
Finished Jul 01 12:35:49 PM PDT 24
Peak memory 200004 kb
Host smart-b5a4b560-84da-4187-9564-bd874302167d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135206733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.135206733
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4098819386
Short name T515
Test name
Test status
Simulation time 82787823211 ps
CPU time 105.97 seconds
Started Jul 01 12:35:34 PM PDT 24
Finished Jul 01 12:37:21 PM PDT 24
Peak memory 199920 kb
Host smart-49745e75-c56d-4bd1-80e3-d747c662caa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098819386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4098819386
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1513575275
Short name T532
Test name
Test status
Simulation time 8119370175 ps
CPU time 5.2 seconds
Started Jul 01 12:35:30 PM PDT 24
Finished Jul 01 12:35:36 PM PDT 24
Peak memory 199680 kb
Host smart-8dda0e3a-959d-4582-b3d3-2e9e1335b256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513575275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1513575275
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.1834673545
Short name T679
Test name
Test status
Simulation time 18928571685 ps
CPU time 488.2 seconds
Started Jul 01 12:35:31 PM PDT 24
Finished Jul 01 12:43:40 PM PDT 24
Peak memory 199792 kb
Host smart-4ca14dc8-6e26-4a5c-b83b-157e93d891a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1834673545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1834673545
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.455310258
Short name T1071
Test name
Test status
Simulation time 1504534055 ps
CPU time 1.81 seconds
Started Jul 01 12:35:35 PM PDT 24
Finished Jul 01 12:35:38 PM PDT 24
Peak memory 198136 kb
Host smart-8700e484-e35f-4611-93c8-5f65a82f913a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=455310258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.455310258
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2269551220
Short name T485
Test name
Test status
Simulation time 3150742280 ps
CPU time 4.89 seconds
Started Jul 01 12:35:30 PM PDT 24
Finished Jul 01 12:35:36 PM PDT 24
Peak memory 195888 kb
Host smart-716d8d2d-7a5e-4203-9007-a5e1051a29c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269551220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2269551220
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.3851443977
Short name T267
Test name
Test status
Simulation time 6326686277 ps
CPU time 16.61 seconds
Started Jul 01 12:35:25 PM PDT 24
Finished Jul 01 12:35:43 PM PDT 24
Peak memory 199836 kb
Host smart-4de5af96-46ca-476c-8c33-34902a516aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851443977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3851443977
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.587771464
Short name T573
Test name
Test status
Simulation time 154472622314 ps
CPU time 659.36 seconds
Started Jul 01 12:35:35 PM PDT 24
Finished Jul 01 12:46:35 PM PDT 24
Peak memory 216528 kb
Host smart-1ab91c07-b926-4af8-8fad-8c40bea5bdda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587771464 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.587771464
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.644603663
Short name T403
Test name
Test status
Simulation time 918278604 ps
CPU time 3.3 seconds
Started Jul 01 12:35:32 PM PDT 24
Finished Jul 01 12:35:36 PM PDT 24
Peak memory 198424 kb
Host smart-6e233550-fece-441b-a165-1e91d3c803b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644603663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.644603663
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2235296327
Short name T1019
Test name
Test status
Simulation time 67526301937 ps
CPU time 23.61 seconds
Started Jul 01 12:35:30 PM PDT 24
Finished Jul 01 12:35:55 PM PDT 24
Peak memory 199916 kb
Host smart-7916261f-33fa-42e3-91d7-5ebe4e473cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235296327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2235296327
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3445873540
Short name T374
Test name
Test status
Simulation time 69574608 ps
CPU time 0.56 seconds
Started Jul 01 12:38:05 PM PDT 24
Finished Jul 01 12:38:06 PM PDT 24
Peak memory 195596 kb
Host smart-8063fb2b-61c0-4650-9fc6-dbfe34c1013b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445873540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3445873540
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1694987850
Short name T508
Test name
Test status
Simulation time 96722857159 ps
CPU time 50.13 seconds
Started Jul 01 12:38:02 PM PDT 24
Finished Jul 01 12:38:53 PM PDT 24
Peak memory 199928 kb
Host smart-97d1852d-5e60-455f-8d57-8b498d0ecf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694987850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1694987850
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.606487666
Short name T450
Test name
Test status
Simulation time 29156880964 ps
CPU time 23.88 seconds
Started Jul 01 12:38:01 PM PDT 24
Finished Jul 01 12:38:25 PM PDT 24
Peak memory 199896 kb
Host smart-f4764859-7bb1-4f83-a859-d22d4268557f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606487666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.606487666
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1378498325
Short name T811
Test name
Test status
Simulation time 145978969462 ps
CPU time 315.75 seconds
Started Jul 01 12:38:10 PM PDT 24
Finished Jul 01 12:43:27 PM PDT 24
Peak memory 199900 kb
Host smart-7758d978-b5fd-494b-9a4f-228992936252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378498325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1378498325
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1306711646
Short name T566
Test name
Test status
Simulation time 53687126946 ps
CPU time 94.36 seconds
Started Jul 01 12:38:10 PM PDT 24
Finished Jul 01 12:39:45 PM PDT 24
Peak memory 199932 kb
Host smart-bb250dab-90a1-4b6e-941c-17876c71bd33
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306711646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1306711646
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2514081784
Short name T250
Test name
Test status
Simulation time 137477747758 ps
CPU time 618.04 seconds
Started Jul 01 12:38:10 PM PDT 24
Finished Jul 01 12:48:29 PM PDT 24
Peak memory 199888 kb
Host smart-2fcb6395-ff63-4e48-ac85-ae009c6a0147
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514081784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2514081784
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.462673310
Short name T327
Test name
Test status
Simulation time 7550690206 ps
CPU time 12.19 seconds
Started Jul 01 12:38:08 PM PDT 24
Finished Jul 01 12:38:21 PM PDT 24
Peak memory 199224 kb
Host smart-885abfc9-0118-49ce-9ee7-6649ee3072ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462673310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.462673310
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.4223010301
Short name T911
Test name
Test status
Simulation time 9544091130 ps
CPU time 132.36 seconds
Started Jul 01 12:38:05 PM PDT 24
Finished Jul 01 12:40:18 PM PDT 24
Peak memory 199864 kb
Host smart-2575add9-224b-4c6a-969d-cee8814e0470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4223010301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4223010301
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2842348737
Short name T439
Test name
Test status
Simulation time 2614477817 ps
CPU time 11.78 seconds
Started Jul 01 12:38:05 PM PDT 24
Finished Jul 01 12:38:17 PM PDT 24
Peak memory 197992 kb
Host smart-72d66e9e-ac32-4cdd-b637-f333ef2063c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2842348737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2842348737
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1915854638
Short name T138
Test name
Test status
Simulation time 23772296392 ps
CPU time 18.69 seconds
Started Jul 01 12:38:07 PM PDT 24
Finished Jul 01 12:38:27 PM PDT 24
Peak memory 199404 kb
Host smart-6bf994b1-197e-434b-b0a7-ae7ab62c51ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915854638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1915854638
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1625709713
Short name T589
Test name
Test status
Simulation time 2988866135 ps
CPU time 4.66 seconds
Started Jul 01 12:38:04 PM PDT 24
Finished Jul 01 12:38:09 PM PDT 24
Peak memory 196480 kb
Host smart-c17137c9-710d-4916-9d3e-76946b332a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625709713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1625709713
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2015440006
Short name T617
Test name
Test status
Simulation time 265536023 ps
CPU time 1.49 seconds
Started Jul 01 12:38:02 PM PDT 24
Finished Jul 01 12:38:04 PM PDT 24
Peak memory 199012 kb
Host smart-0b24a5a7-14e0-4320-bf79-988027dc5b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015440006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2015440006
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.563418759
Short name T1093
Test name
Test status
Simulation time 166447528312 ps
CPU time 273.68 seconds
Started Jul 01 12:38:05 PM PDT 24
Finished Jul 01 12:42:40 PM PDT 24
Peak memory 199952 kb
Host smart-4733d8c3-14dd-4f7d-bfff-608cc683309a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563418759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.563418759
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2838879221
Short name T420
Test name
Test status
Simulation time 6656813074 ps
CPU time 19.58 seconds
Started Jul 01 12:38:05 PM PDT 24
Finished Jul 01 12:38:25 PM PDT 24
Peak memory 199912 kb
Host smart-19b1b401-8fa7-4eaf-95e6-f9a6c6212eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838879221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2838879221
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2916011030
Short name T286
Test name
Test status
Simulation time 36902078405 ps
CPU time 57.84 seconds
Started Jul 01 12:38:01 PM PDT 24
Finished Jul 01 12:39:00 PM PDT 24
Peak memory 199908 kb
Host smart-8f77e6b8-5890-4a78-b2ab-14972f9daf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916011030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2916011030
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1444759245
Short name T584
Test name
Test status
Simulation time 123472315433 ps
CPU time 51.99 seconds
Started Jul 01 12:44:58 PM PDT 24
Finished Jul 01 12:45:50 PM PDT 24
Peak memory 199988 kb
Host smart-84f63828-f18a-489c-8dd2-948d405ac2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444759245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1444759245
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3421461482
Short name T778
Test name
Test status
Simulation time 102896974020 ps
CPU time 44.74 seconds
Started Jul 01 12:44:57 PM PDT 24
Finished Jul 01 12:45:43 PM PDT 24
Peak memory 199920 kb
Host smart-c33a18c3-c242-4aa7-8466-7620ce9a3716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421461482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3421461482
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.4028327130
Short name T388
Test name
Test status
Simulation time 14492604931 ps
CPU time 20.38 seconds
Started Jul 01 12:44:57 PM PDT 24
Finished Jul 01 12:45:19 PM PDT 24
Peak memory 199948 kb
Host smart-ac0bc208-16cf-45c2-85cf-2191421bd6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028327130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.4028327130
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2722435091
Short name T497
Test name
Test status
Simulation time 53776167001 ps
CPU time 48.5 seconds
Started Jul 01 12:44:57 PM PDT 24
Finished Jul 01 12:45:47 PM PDT 24
Peak memory 199968 kb
Host smart-839ce1c4-ece6-4aba-a552-e0145970b3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722435091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2722435091
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2564900508
Short name T1011
Test name
Test status
Simulation time 7567343756 ps
CPU time 12.85 seconds
Started Jul 01 12:44:57 PM PDT 24
Finished Jul 01 12:45:11 PM PDT 24
Peak memory 198836 kb
Host smart-138becde-5e6f-4761-86f1-cf4baa29bb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564900508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2564900508
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.387753367
Short name T200
Test name
Test status
Simulation time 81599115014 ps
CPU time 99.87 seconds
Started Jul 01 12:44:57 PM PDT 24
Finished Jul 01 12:46:37 PM PDT 24
Peak memory 200012 kb
Host smart-139d0205-9a11-4976-8456-d8e61a3cbf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387753367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.387753367
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2313005727
Short name T13
Test name
Test status
Simulation time 40115029381 ps
CPU time 23.78 seconds
Started Jul 01 12:44:58 PM PDT 24
Finished Jul 01 12:45:22 PM PDT 24
Peak memory 199920 kb
Host smart-7b03a04a-9a50-4182-a2ac-9518016c4743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313005727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2313005727
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2607623767
Short name T784
Test name
Test status
Simulation time 100158400534 ps
CPU time 15.78 seconds
Started Jul 01 12:44:57 PM PDT 24
Finished Jul 01 12:45:14 PM PDT 24
Peak memory 199892 kb
Host smart-79930296-2195-456d-a685-0663f823439f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607623767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2607623767
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1304464173
Short name T1030
Test name
Test status
Simulation time 91918657319 ps
CPU time 91.79 seconds
Started Jul 01 12:45:03 PM PDT 24
Finished Jul 01 12:46:35 PM PDT 24
Peak memory 199936 kb
Host smart-9a7df1d0-0de0-4e1a-8fba-b83d6aa50951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304464173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1304464173
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1785262312
Short name T330
Test name
Test status
Simulation time 34879438 ps
CPU time 0.56 seconds
Started Jul 01 12:38:20 PM PDT 24
Finished Jul 01 12:38:20 PM PDT 24
Peak memory 195252 kb
Host smart-6b7c1346-2068-4911-8f28-4576c2cc9671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785262312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1785262312
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2624200491
Short name T793
Test name
Test status
Simulation time 19342920203 ps
CPU time 17.68 seconds
Started Jul 01 12:38:10 PM PDT 24
Finished Jul 01 12:38:28 PM PDT 24
Peak memory 199996 kb
Host smart-e461dde8-42f6-484d-9e02-ca363c104a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624200491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2624200491
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.662481276
Short name T422
Test name
Test status
Simulation time 104469031662 ps
CPU time 154.95 seconds
Started Jul 01 12:38:09 PM PDT 24
Finished Jul 01 12:40:45 PM PDT 24
Peak memory 199928 kb
Host smart-ffecf6de-47f5-4f4b-bf46-465d3445dae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662481276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.662481276
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2378182046
Short name T245
Test name
Test status
Simulation time 159196685335 ps
CPU time 64.47 seconds
Started Jul 01 12:38:11 PM PDT 24
Finished Jul 01 12:39:16 PM PDT 24
Peak memory 200016 kb
Host smart-a3e01c3a-0363-40a8-97de-e387287ae899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378182046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2378182046
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.335842141
Short name T521
Test name
Test status
Simulation time 131948269168 ps
CPU time 219.76 seconds
Started Jul 01 12:38:10 PM PDT 24
Finished Jul 01 12:41:51 PM PDT 24
Peak memory 199980 kb
Host smart-acd8c90d-b40f-47ee-9ec2-c9cbdca8a814
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335842141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.335842141
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1001117930
Short name T443
Test name
Test status
Simulation time 127474311181 ps
CPU time 323.19 seconds
Started Jul 01 12:38:21 PM PDT 24
Finished Jul 01 12:43:45 PM PDT 24
Peak memory 199904 kb
Host smart-e411a42f-0802-468a-af22-6da494ee77d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001117930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1001117930
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.4014958804
Short name T491
Test name
Test status
Simulation time 113124832 ps
CPU time 0.75 seconds
Started Jul 01 12:38:14 PM PDT 24
Finished Jul 01 12:38:16 PM PDT 24
Peak memory 195796 kb
Host smart-d92ae81d-afaf-4267-a016-60a34b0ab1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014958804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.4014958804
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.1912285791
Short name T47
Test name
Test status
Simulation time 16497578670 ps
CPU time 70.86 seconds
Started Jul 01 12:38:18 PM PDT 24
Finished Jul 01 12:39:30 PM PDT 24
Peak memory 200028 kb
Host smart-efe57a39-a5fd-4fb3-ba69-a79a0ce15d00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912285791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1912285791
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.70547390
Short name T662
Test name
Test status
Simulation time 2991437523 ps
CPU time 5.06 seconds
Started Jul 01 12:38:10 PM PDT 24
Finished Jul 01 12:38:16 PM PDT 24
Peak memory 198072 kb
Host smart-81efe752-0a2a-435b-a9e1-559659c7ceaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70547390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.70547390
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3629165366
Short name T418
Test name
Test status
Simulation time 25890061500 ps
CPU time 42.79 seconds
Started Jul 01 12:38:15 PM PDT 24
Finished Jul 01 12:38:59 PM PDT 24
Peak memory 199988 kb
Host smart-b8a3a3bc-dda1-427c-acb2-494c54cfbdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629165366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3629165366
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.41164074
Short name T663
Test name
Test status
Simulation time 2253493645 ps
CPU time 4.26 seconds
Started Jul 01 12:38:14 PM PDT 24
Finished Jul 01 12:38:19 PM PDT 24
Peak memory 195460 kb
Host smart-3ef1aa68-2b23-4697-8e98-f9713faa5ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41164074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.41164074
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1152520709
Short name T297
Test name
Test status
Simulation time 975290636 ps
CPU time 5.32 seconds
Started Jul 01 12:38:04 PM PDT 24
Finished Jul 01 12:38:10 PM PDT 24
Peak memory 198764 kb
Host smart-71e452be-29c3-4494-a836-f006b24617ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152520709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1152520709
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1602362103
Short name T503
Test name
Test status
Simulation time 282364821665 ps
CPU time 1217.43 seconds
Started Jul 01 12:38:21 PM PDT 24
Finished Jul 01 12:58:39 PM PDT 24
Peak memory 199808 kb
Host smart-c4099d95-d6e3-475f-8f5f-50043f66f1e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602362103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1602362103
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1701320271
Short name T1067
Test name
Test status
Simulation time 42137688395 ps
CPU time 242.89 seconds
Started Jul 01 12:38:22 PM PDT 24
Finished Jul 01 12:42:25 PM PDT 24
Peak memory 215580 kb
Host smart-c0cd68b7-3ad5-404f-a34c-bf62701d980e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701320271 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1701320271
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3691238129
Short name T276
Test name
Test status
Simulation time 2319649895 ps
CPU time 1.89 seconds
Started Jul 01 12:38:15 PM PDT 24
Finished Jul 01 12:38:17 PM PDT 24
Peak memory 199276 kb
Host smart-03a5ee52-f622-4565-b8a5-21fb4858ef21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691238129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3691238129
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2901145876
Short name T999
Test name
Test status
Simulation time 44101823952 ps
CPU time 15.71 seconds
Started Jul 01 12:38:09 PM PDT 24
Finished Jul 01 12:38:25 PM PDT 24
Peak memory 199056 kb
Host smart-f2fbb5b3-445b-41d3-b641-2b3fce2a7fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901145876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2901145876
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.291563185
Short name T1035
Test name
Test status
Simulation time 135410901187 ps
CPU time 69.88 seconds
Started Jul 01 12:45:03 PM PDT 24
Finished Jul 01 12:46:14 PM PDT 24
Peak memory 200008 kb
Host smart-3a2239ba-b00c-4c11-8dd0-756da680e5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291563185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.291563185
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.255595220
Short name T668
Test name
Test status
Simulation time 30904419032 ps
CPU time 14.45 seconds
Started Jul 01 12:45:03 PM PDT 24
Finished Jul 01 12:45:18 PM PDT 24
Peak memory 199824 kb
Host smart-978f941d-6ddd-4761-8d92-cc75c71a7b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255595220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.255595220
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1496811818
Short name T541
Test name
Test status
Simulation time 201618012549 ps
CPU time 34.96 seconds
Started Jul 01 12:45:03 PM PDT 24
Finished Jul 01 12:45:38 PM PDT 24
Peak memory 199976 kb
Host smart-e646e06f-260b-4422-9a99-b4e964dca4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496811818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1496811818
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1420579383
Short name T739
Test name
Test status
Simulation time 104729796354 ps
CPU time 142.24 seconds
Started Jul 01 12:45:03 PM PDT 24
Finished Jul 01 12:47:26 PM PDT 24
Peak memory 199960 kb
Host smart-7f4c69b9-fde6-46a9-9da0-a5cab3af38e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420579383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1420579383
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2878589688
Short name T198
Test name
Test status
Simulation time 25198390361 ps
CPU time 34.08 seconds
Started Jul 01 12:45:03 PM PDT 24
Finished Jul 01 12:45:38 PM PDT 24
Peak memory 199640 kb
Host smart-1904e3c1-37e5-4184-92a4-d3e05fdbae14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878589688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2878589688
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.439765990
Short name T454
Test name
Test status
Simulation time 62232036874 ps
CPU time 28.51 seconds
Started Jul 01 12:45:07 PM PDT 24
Finished Jul 01 12:45:36 PM PDT 24
Peak memory 199892 kb
Host smart-c04da4d2-c4a9-4147-ab27-17ddfb0495bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439765990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.439765990
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2624490763
Short name T343
Test name
Test status
Simulation time 114533338529 ps
CPU time 11.13 seconds
Started Jul 01 12:45:07 PM PDT 24
Finished Jul 01 12:45:19 PM PDT 24
Peak memory 198596 kb
Host smart-61913974-8ab3-4414-9aa4-a9e5d22e1e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624490763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2624490763
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.293574675
Short name T725
Test name
Test status
Simulation time 90176426952 ps
CPU time 27.8 seconds
Started Jul 01 12:45:08 PM PDT 24
Finished Jul 01 12:45:36 PM PDT 24
Peak memory 199832 kb
Host smart-fb1dc6cd-9375-48e9-af45-d17fabfc4605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293574675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.293574675
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4193456318
Short name T853
Test name
Test status
Simulation time 91570299969 ps
CPU time 37.97 seconds
Started Jul 01 12:45:09 PM PDT 24
Finished Jul 01 12:45:48 PM PDT 24
Peak memory 199740 kb
Host smart-6e776d07-a6c3-475f-9611-7b1e7d6f429c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193456318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4193456318
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1459186317
Short name T226
Test name
Test status
Simulation time 29351826359 ps
CPU time 14.68 seconds
Started Jul 01 12:45:07 PM PDT 24
Finished Jul 01 12:45:22 PM PDT 24
Peak memory 199960 kb
Host smart-de682bed-847e-42aa-ba7b-1b47eff14ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459186317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1459186317
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3933969377
Short name T1056
Test name
Test status
Simulation time 19976137 ps
CPU time 0.56 seconds
Started Jul 01 12:38:29 PM PDT 24
Finished Jul 01 12:38:30 PM PDT 24
Peak memory 195296 kb
Host smart-64669bd9-e9a9-4ea8-a51f-791b8abecf01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933969377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3933969377
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3083003122
Short name T785
Test name
Test status
Simulation time 28637361890 ps
CPU time 37.92 seconds
Started Jul 01 12:38:24 PM PDT 24
Finished Jul 01 12:39:03 PM PDT 24
Peak memory 199588 kb
Host smart-caacc23e-b72e-4554-a3d8-66cc18041ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083003122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3083003122
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.380115258
Short name T324
Test name
Test status
Simulation time 248033912034 ps
CPU time 86.74 seconds
Started Jul 01 12:38:24 PM PDT 24
Finished Jul 01 12:39:52 PM PDT 24
Peak memory 199976 kb
Host smart-762c094c-710d-4e69-95a3-d4b3def60ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380115258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.380115258
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1899292960
Short name T512
Test name
Test status
Simulation time 52099400521 ps
CPU time 28.67 seconds
Started Jul 01 12:38:25 PM PDT 24
Finished Jul 01 12:38:54 PM PDT 24
Peak memory 199912 kb
Host smart-46943469-61c3-4339-be0a-18ec0224c69b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899292960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1899292960
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3712191571
Short name T798
Test name
Test status
Simulation time 57268349382 ps
CPU time 219.73 seconds
Started Jul 01 12:38:30 PM PDT 24
Finished Jul 01 12:42:10 PM PDT 24
Peak memory 199972 kb
Host smart-848332ec-88f0-45a3-b8ed-7c797029c2bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712191571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3712191571
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3690927240
Short name T751
Test name
Test status
Simulation time 6732169459 ps
CPU time 6.79 seconds
Started Jul 01 12:38:24 PM PDT 24
Finished Jul 01 12:38:31 PM PDT 24
Peak memory 198656 kb
Host smart-d1481ac1-f158-449e-b601-078be4dc6b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690927240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3690927240
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.3809250617
Short name T389
Test name
Test status
Simulation time 16458002922 ps
CPU time 470.9 seconds
Started Jul 01 12:38:25 PM PDT 24
Finished Jul 01 12:46:17 PM PDT 24
Peak memory 199964 kb
Host smart-70a37f1b-ca7b-4e12-9120-4f52316cac37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3809250617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3809250617
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1995142671
Short name T377
Test name
Test status
Simulation time 5652137710 ps
CPU time 47.92 seconds
Started Jul 01 12:38:27 PM PDT 24
Finished Jul 01 12:39:16 PM PDT 24
Peak memory 199324 kb
Host smart-d48bf33d-3d1b-4eb7-8f5d-6cf548986c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995142671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1995142671
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.4108923719
Short name T1083
Test name
Test status
Simulation time 27818195063 ps
CPU time 27.55 seconds
Started Jul 01 12:38:25 PM PDT 24
Finished Jul 01 12:38:53 PM PDT 24
Peak memory 199896 kb
Host smart-65c341e2-9a53-4d9e-9bda-6356fe41f2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108923719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.4108923719
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2460261842
Short name T870
Test name
Test status
Simulation time 4463055863 ps
CPU time 6.83 seconds
Started Jul 01 12:38:26 PM PDT 24
Finished Jul 01 12:38:33 PM PDT 24
Peak memory 196328 kb
Host smart-7af67273-af4f-4f4e-a048-07259ea3d839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460261842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2460261842
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1631443014
Short name T956
Test name
Test status
Simulation time 447895102 ps
CPU time 2.07 seconds
Started Jul 01 12:38:21 PM PDT 24
Finished Jul 01 12:38:24 PM PDT 24
Peak memory 199476 kb
Host smart-ae6a289b-665b-4142-aac3-c49a6813371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631443014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1631443014
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1603405295
Short name T99
Test name
Test status
Simulation time 274089803150 ps
CPU time 783.49 seconds
Started Jul 01 12:38:30 PM PDT 24
Finished Jul 01 12:51:34 PM PDT 24
Peak memory 216500 kb
Host smart-075f09aa-7957-41c1-b5b9-303da5841d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603405295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1603405295
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2217960136
Short name T599
Test name
Test status
Simulation time 1229309801 ps
CPU time 3.89 seconds
Started Jul 01 12:38:24 PM PDT 24
Finished Jul 01 12:38:29 PM PDT 24
Peak memory 199592 kb
Host smart-b28491ef-f26b-4416-92e7-0ac95e823405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217960136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2217960136
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2824449468
Short name T959
Test name
Test status
Simulation time 58715767188 ps
CPU time 14.94 seconds
Started Jul 01 12:38:21 PM PDT 24
Finished Jul 01 12:38:36 PM PDT 24
Peak memory 198280 kb
Host smart-1c9b6a03-2f22-40e0-8bec-b6d35f77e703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824449468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2824449468
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.736987509
Short name T150
Test name
Test status
Simulation time 46267124516 ps
CPU time 43.46 seconds
Started Jul 01 12:45:14 PM PDT 24
Finished Jul 01 12:45:58 PM PDT 24
Peak memory 199940 kb
Host smart-83d35e2f-4ff1-42a1-8bf8-e8cb88a6023e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736987509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.736987509
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.485049347
Short name T537
Test name
Test status
Simulation time 44004227953 ps
CPU time 65.3 seconds
Started Jul 01 12:45:13 PM PDT 24
Finished Jul 01 12:46:19 PM PDT 24
Peak memory 200012 kb
Host smart-8d1885a6-8245-46a4-95b6-4daedb1f5984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485049347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.485049347
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1237268222
Short name T266
Test name
Test status
Simulation time 36422676060 ps
CPU time 17.98 seconds
Started Jul 01 12:45:12 PM PDT 24
Finished Jul 01 12:45:31 PM PDT 24
Peak memory 199784 kb
Host smart-f4654776-6a60-476e-b2cc-0ca82e7f6e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237268222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1237268222
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1429812673
Short name T412
Test name
Test status
Simulation time 57989651228 ps
CPU time 46.72 seconds
Started Jul 01 12:45:13 PM PDT 24
Finished Jul 01 12:46:00 PM PDT 24
Peak memory 199840 kb
Host smart-2bbd34c5-792d-4ad9-a6b7-e7783595aa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429812673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1429812673
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1636623988
Short name T622
Test name
Test status
Simulation time 55074813680 ps
CPU time 41.14 seconds
Started Jul 01 12:45:14 PM PDT 24
Finished Jul 01 12:45:56 PM PDT 24
Peak memory 199748 kb
Host smart-ed1dbd32-36d5-455f-9165-0f571ab211be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636623988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1636623988
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3386997402
Short name T158
Test name
Test status
Simulation time 65120671450 ps
CPU time 94.94 seconds
Started Jul 01 12:45:13 PM PDT 24
Finished Jul 01 12:46:48 PM PDT 24
Peak memory 199960 kb
Host smart-c69ba5fc-c49f-4a3a-be35-418115916180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386997402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3386997402
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2335142835
Short name T207
Test name
Test status
Simulation time 97753396999 ps
CPU time 70.52 seconds
Started Jul 01 12:45:13 PM PDT 24
Finished Jul 01 12:46:24 PM PDT 24
Peak memory 199660 kb
Host smart-6086ad40-616a-4b93-a072-5d15cafb1d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335142835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2335142835
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1474406527
Short name T231
Test name
Test status
Simulation time 25580692856 ps
CPU time 74.38 seconds
Started Jul 01 12:45:17 PM PDT 24
Finished Jul 01 12:46:33 PM PDT 24
Peak memory 199916 kb
Host smart-c75eabf1-d09c-4ac0-af1e-ee6ac820a315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474406527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1474406527
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1504282369
Short name T321
Test name
Test status
Simulation time 112171097795 ps
CPU time 78.97 seconds
Started Jul 01 12:45:24 PM PDT 24
Finished Jul 01 12:46:44 PM PDT 24
Peak memory 199956 kb
Host smart-f79d1fe6-4684-4e4b-a88d-197f8c5637eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504282369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1504282369
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.975980543
Short name T1085
Test name
Test status
Simulation time 44025357 ps
CPU time 0.56 seconds
Started Jul 01 12:38:39 PM PDT 24
Finished Jul 01 12:38:40 PM PDT 24
Peak memory 195252 kb
Host smart-f3dd288a-58c2-481d-b11f-d6cf69380d9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975980543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.975980543
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1178194647
Short name T935
Test name
Test status
Simulation time 145226370564 ps
CPU time 29.92 seconds
Started Jul 01 12:38:31 PM PDT 24
Finished Jul 01 12:39:01 PM PDT 24
Peak memory 199956 kb
Host smart-2e0d2251-915d-416e-8d8d-c7403f631a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178194647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1178194647
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3091722336
Short name T839
Test name
Test status
Simulation time 72171278404 ps
CPU time 13.38 seconds
Started Jul 01 12:38:29 PM PDT 24
Finished Jul 01 12:38:43 PM PDT 24
Peak memory 199304 kb
Host smart-e9508843-bb60-43d7-93b5-f437e1a378fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091722336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3091722336
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3913541789
Short name T750
Test name
Test status
Simulation time 16318613955 ps
CPU time 22.42 seconds
Started Jul 01 12:38:30 PM PDT 24
Finished Jul 01 12:38:53 PM PDT 24
Peak memory 199784 kb
Host smart-8ef0037b-41db-44a9-a411-9224a97378e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913541789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3913541789
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.307901571
Short name T4
Test name
Test status
Simulation time 36394010654 ps
CPU time 12.86 seconds
Started Jul 01 12:38:34 PM PDT 24
Finished Jul 01 12:38:48 PM PDT 24
Peak memory 199388 kb
Host smart-e2b9ab37-3cc2-4890-94aa-b59632462422
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307901571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.307901571
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2614100165
Short name T1045
Test name
Test status
Simulation time 178017767510 ps
CPU time 1620.72 seconds
Started Jul 01 12:38:35 PM PDT 24
Finished Jul 01 01:05:36 PM PDT 24
Peak memory 199936 kb
Host smart-d75b3061-548a-4a1b-b6d2-0e0faa7766a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614100165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2614100165
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3411674035
Short name T813
Test name
Test status
Simulation time 61033713 ps
CPU time 0.84 seconds
Started Jul 01 12:38:35 PM PDT 24
Finished Jul 01 12:38:36 PM PDT 24
Peak memory 198040 kb
Host smart-c09c7271-8c0e-4a0c-a22f-3ddb88695b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411674035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3411674035
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.1003374061
Short name T841
Test name
Test status
Simulation time 12037567901 ps
CPU time 422.52 seconds
Started Jul 01 12:38:39 PM PDT 24
Finished Jul 01 12:45:42 PM PDT 24
Peak memory 199844 kb
Host smart-318bfb7b-585f-4f93-a5cc-dab539d023b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003374061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1003374061
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1940045138
Short name T407
Test name
Test status
Simulation time 3699523042 ps
CPU time 30.22 seconds
Started Jul 01 12:38:34 PM PDT 24
Finished Jul 01 12:39:05 PM PDT 24
Peak memory 198436 kb
Host smart-36083093-064f-40d2-b670-e36b1f9f04d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1940045138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1940045138
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3817525360
Short name T876
Test name
Test status
Simulation time 40167283803 ps
CPU time 62.69 seconds
Started Jul 01 12:38:35 PM PDT 24
Finished Jul 01 12:39:38 PM PDT 24
Peak memory 199920 kb
Host smart-225a36df-c2ee-46bc-b60e-459646134f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817525360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3817525360
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.4269376492
Short name T363
Test name
Test status
Simulation time 3924148130 ps
CPU time 3.63 seconds
Started Jul 01 12:38:35 PM PDT 24
Finished Jul 01 12:38:39 PM PDT 24
Peak memory 196052 kb
Host smart-3db44083-613b-4202-81dd-4d544b6dc9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269376492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.4269376492
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.50216632
Short name T992
Test name
Test status
Simulation time 607069764 ps
CPU time 2.64 seconds
Started Jul 01 12:38:30 PM PDT 24
Finished Jul 01 12:38:33 PM PDT 24
Peak memory 198780 kb
Host smart-2d9ce282-e1ce-4591-904a-be5a6d876bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50216632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.50216632
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.342446326
Short name T104
Test name
Test status
Simulation time 48206845408 ps
CPU time 477.46 seconds
Started Jul 01 12:38:33 PM PDT 24
Finished Jul 01 12:46:31 PM PDT 24
Peak memory 216468 kb
Host smart-b151677a-9ee8-4ae0-9841-8ebde8ad88f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342446326 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.342446326
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2582666708
Short name T347
Test name
Test status
Simulation time 379398478 ps
CPU time 1.53 seconds
Started Jul 01 12:38:34 PM PDT 24
Finished Jul 01 12:38:36 PM PDT 24
Peak memory 198664 kb
Host smart-977717bd-1ece-4a4f-b52c-19d6ab12fb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582666708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2582666708
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3460877183
Short name T281
Test name
Test status
Simulation time 25640364537 ps
CPU time 42.7 seconds
Started Jul 01 12:38:29 PM PDT 24
Finished Jul 01 12:39:12 PM PDT 24
Peak memory 199704 kb
Host smart-08116844-dfb8-4b68-8373-3d469e8dcfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460877183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3460877183
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.962632654
Short name T752
Test name
Test status
Simulation time 239678591238 ps
CPU time 54.4 seconds
Started Jul 01 12:45:19 PM PDT 24
Finished Jul 01 12:46:14 PM PDT 24
Peak memory 199976 kb
Host smart-92000eaf-b4b8-4279-8181-599dfd685269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962632654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.962632654
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.814218923
Short name T989
Test name
Test status
Simulation time 27302183668 ps
CPU time 21.9 seconds
Started Jul 01 12:45:19 PM PDT 24
Finished Jul 01 12:45:42 PM PDT 24
Peak memory 199996 kb
Host smart-1c392ac1-edfe-477d-b39c-0edcf6e5103e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814218923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.814218923
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.954013879
Short name T113
Test name
Test status
Simulation time 52673660713 ps
CPU time 39.4 seconds
Started Jul 01 12:45:19 PM PDT 24
Finished Jul 01 12:45:59 PM PDT 24
Peak memory 199892 kb
Host smart-2d0c5e2b-a74f-4b51-9bf3-d4faea0db150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954013879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.954013879
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.4047474802
Short name T522
Test name
Test status
Simulation time 168527826065 ps
CPU time 178.74 seconds
Started Jul 01 12:45:24 PM PDT 24
Finished Jul 01 12:48:23 PM PDT 24
Peak memory 200016 kb
Host smart-631f4835-2085-46ed-9063-611bff1c30c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047474802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.4047474802
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.4282081054
Short name T707
Test name
Test status
Simulation time 35549060941 ps
CPU time 12.96 seconds
Started Jul 01 12:45:26 PM PDT 24
Finished Jul 01 12:45:40 PM PDT 24
Peak memory 199932 kb
Host smart-8e1abc64-5e1f-49c4-990b-3a3c77773ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282081054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.4282081054
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.464927621
Short name T322
Test name
Test status
Simulation time 110383889090 ps
CPU time 152.14 seconds
Started Jul 01 12:45:23 PM PDT 24
Finished Jul 01 12:47:56 PM PDT 24
Peak memory 199928 kb
Host smart-947cf96e-9f1b-4747-9a3f-9e073a8e6f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464927621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.464927621
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2393151275
Short name T910
Test name
Test status
Simulation time 93257843919 ps
CPU time 41.9 seconds
Started Jul 01 12:45:24 PM PDT 24
Finished Jul 01 12:46:07 PM PDT 24
Peak memory 199792 kb
Host smart-eab5ebb3-1d99-4fd5-990a-485cedc91928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393151275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2393151275
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1485146540
Short name T1087
Test name
Test status
Simulation time 195056305082 ps
CPU time 32.34 seconds
Started Jul 01 12:45:24 PM PDT 24
Finished Jul 01 12:45:57 PM PDT 24
Peak memory 199844 kb
Host smart-5598ce0e-1bd0-4d9c-91ec-fb4a95ba05b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485146540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1485146540
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1614298484
Short name T332
Test name
Test status
Simulation time 40826681 ps
CPU time 0.55 seconds
Started Jul 01 12:38:48 PM PDT 24
Finished Jul 01 12:38:50 PM PDT 24
Peak memory 195324 kb
Host smart-eca48fab-61bc-4c74-a058-9430e34d75a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614298484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1614298484
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3790184251
Short name T140
Test name
Test status
Simulation time 90874259478 ps
CPU time 89.55 seconds
Started Jul 01 12:38:38 PM PDT 24
Finished Jul 01 12:40:08 PM PDT 24
Peak memory 199980 kb
Host smart-5961c2d2-c47c-4f7a-a745-9f76daee6e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790184251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3790184251
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1143000458
Short name T493
Test name
Test status
Simulation time 40792620822 ps
CPU time 17.4 seconds
Started Jul 01 12:38:39 PM PDT 24
Finished Jul 01 12:38:57 PM PDT 24
Peak memory 199852 kb
Host smart-5b456b81-8515-42cc-b71e-0ef84c961e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143000458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1143000458
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2369405807
Short name T686
Test name
Test status
Simulation time 19509694258 ps
CPU time 29.07 seconds
Started Jul 01 12:38:38 PM PDT 24
Finished Jul 01 12:39:08 PM PDT 24
Peak memory 199916 kb
Host smart-3e46c0fd-a1af-429d-9034-4cef33b23cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369405807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2369405807
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2446191095
Short name T824
Test name
Test status
Simulation time 28103355154 ps
CPU time 56.3 seconds
Started Jul 01 12:38:45 PM PDT 24
Finished Jul 01 12:39:42 PM PDT 24
Peak memory 199968 kb
Host smart-27555cf7-a29e-4fa9-b47e-cd66ced9f681
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446191095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2446191095
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1466939833
Short name T585
Test name
Test status
Simulation time 80452899408 ps
CPU time 175.75 seconds
Started Jul 01 12:38:44 PM PDT 24
Finished Jul 01 12:41:41 PM PDT 24
Peak memory 199876 kb
Host smart-4b0eff2f-9a06-43c0-8866-27cd4c04d7eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466939833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1466939833
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.855558662
Short name T553
Test name
Test status
Simulation time 6915830826 ps
CPU time 22.96 seconds
Started Jul 01 12:38:45 PM PDT 24
Finished Jul 01 12:39:09 PM PDT 24
Peak memory 199892 kb
Host smart-9c7485c3-1426-42e2-a7f1-d38bf57628ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855558662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.855558662
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.3653754144
Short name T536
Test name
Test status
Simulation time 19693628694 ps
CPU time 1086.24 seconds
Started Jul 01 12:38:44 PM PDT 24
Finished Jul 01 12:56:51 PM PDT 24
Peak memory 200000 kb
Host smart-b02c7951-f9fa-45fb-8108-8fe55c4fbd2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3653754144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3653754144
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2776771238
Short name T53
Test name
Test status
Simulation time 2000077936 ps
CPU time 12.24 seconds
Started Jul 01 12:38:40 PM PDT 24
Finished Jul 01 12:38:53 PM PDT 24
Peak memory 198000 kb
Host smart-5961a0ef-2414-4054-9f29-d637e2fa9247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776771238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2776771238
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1168351055
Short name T927
Test name
Test status
Simulation time 183896809889 ps
CPU time 44.45 seconds
Started Jul 01 12:38:44 PM PDT 24
Finished Jul 01 12:39:30 PM PDT 24
Peak memory 199660 kb
Host smart-ba894a4d-4968-4e10-8235-b11b2bed9131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168351055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1168351055
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2413086467
Short name T692
Test name
Test status
Simulation time 33343975672 ps
CPU time 12.65 seconds
Started Jul 01 12:38:45 PM PDT 24
Finished Jul 01 12:38:59 PM PDT 24
Peak memory 195956 kb
Host smart-3e713fa3-763e-42f4-8152-04ac1c6e4184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413086467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2413086467
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.4231185540
Short name T660
Test name
Test status
Simulation time 875405385 ps
CPU time 1.74 seconds
Started Jul 01 12:38:42 PM PDT 24
Finished Jul 01 12:38:45 PM PDT 24
Peak memory 199188 kb
Host smart-0aeaecb3-6405-4be2-9905-436762bda7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231185540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.4231185540
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1039894399
Short name T344
Test name
Test status
Simulation time 991888952 ps
CPU time 2.27 seconds
Started Jul 01 12:38:44 PM PDT 24
Finished Jul 01 12:38:47 PM PDT 24
Peak memory 198764 kb
Host smart-412416e3-62d0-4830-acc1-15ccff05ddbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039894399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1039894399
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2479222342
Short name T570
Test name
Test status
Simulation time 57047172218 ps
CPU time 54.02 seconds
Started Jul 01 12:38:38 PM PDT 24
Finished Jul 01 12:39:33 PM PDT 24
Peak memory 199948 kb
Host smart-d8538be0-32aa-4243-96cc-80bb9e1fcb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479222342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2479222342
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2679286435
Short name T866
Test name
Test status
Simulation time 16716811055 ps
CPU time 51.52 seconds
Started Jul 01 12:45:23 PM PDT 24
Finished Jul 01 12:46:15 PM PDT 24
Peak memory 199980 kb
Host smart-1be1fecf-ca28-4bb1-a1c3-ad1b01c0e0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679286435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2679286435
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1161438858
Short name T974
Test name
Test status
Simulation time 59156704005 ps
CPU time 36.74 seconds
Started Jul 01 12:45:24 PM PDT 24
Finished Jul 01 12:46:01 PM PDT 24
Peak memory 200000 kb
Host smart-1b74537b-fd73-4567-9f69-b43f720fb5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161438858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1161438858
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.552202914
Short name T896
Test name
Test status
Simulation time 19084613979 ps
CPU time 29.13 seconds
Started Jul 01 12:45:26 PM PDT 24
Finished Jul 01 12:45:55 PM PDT 24
Peak memory 199916 kb
Host smart-92bfe5ec-928a-4fb2-9d73-3f125bc70020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552202914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.552202914
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.211738136
Short name T937
Test name
Test status
Simulation time 36598639178 ps
CPU time 30.14 seconds
Started Jul 01 12:45:23 PM PDT 24
Finished Jul 01 12:45:54 PM PDT 24
Peak memory 199900 kb
Host smart-3893bde6-e818-46b3-8bb0-1b1391841a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211738136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.211738136
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1487058964
Short name T831
Test name
Test status
Simulation time 30055786463 ps
CPU time 15.23 seconds
Started Jul 01 12:45:29 PM PDT 24
Finished Jul 01 12:45:45 PM PDT 24
Peak memory 199940 kb
Host smart-99e2cd1c-03f8-4cdb-b3d5-f12f928fab31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487058964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1487058964
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.121988992
Short name T938
Test name
Test status
Simulation time 35032202144 ps
CPU time 13.64 seconds
Started Jul 01 12:45:29 PM PDT 24
Finished Jul 01 12:45:43 PM PDT 24
Peak memory 200008 kb
Host smart-109c9e58-3b92-48b3-812b-535fd24efe8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121988992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.121988992
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.747086484
Short name T155
Test name
Test status
Simulation time 71519257452 ps
CPU time 29.02 seconds
Started Jul 01 12:45:29 PM PDT 24
Finished Jul 01 12:45:59 PM PDT 24
Peak memory 199916 kb
Host smart-1b421b56-d64b-4b59-9fa1-16e4cfe41d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747086484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.747086484
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1481009379
Short name T448
Test name
Test status
Simulation time 12103683700 ps
CPU time 45.92 seconds
Started Jul 01 12:45:30 PM PDT 24
Finished Jul 01 12:46:17 PM PDT 24
Peak memory 199876 kb
Host smart-fddfc05d-85a8-4c93-9873-9f097e27c9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481009379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1481009379
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3722032115
Short name T997
Test name
Test status
Simulation time 12280102622 ps
CPU time 46.31 seconds
Started Jul 01 12:45:41 PM PDT 24
Finished Jul 01 12:46:28 PM PDT 24
Peak memory 199848 kb
Host smart-33bddc07-36b9-433a-9a9c-07d797f00281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722032115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3722032115
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.22140248
Short name T520
Test name
Test status
Simulation time 62552978471 ps
CPU time 92.85 seconds
Started Jul 01 12:45:39 PM PDT 24
Finished Jul 01 12:47:12 PM PDT 24
Peak memory 199936 kb
Host smart-efbfb671-8091-4bb6-9580-c038f73624d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22140248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.22140248
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.403269090
Short name T883
Test name
Test status
Simulation time 10861447 ps
CPU time 0.6 seconds
Started Jul 01 12:38:59 PM PDT 24
Finished Jul 01 12:39:01 PM PDT 24
Peak memory 195300 kb
Host smart-303f77ab-21f5-467e-aea0-27ddb079bfa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403269090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.403269090
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3425804099
Short name T1001
Test name
Test status
Simulation time 25473422164 ps
CPU time 48.52 seconds
Started Jul 01 12:38:49 PM PDT 24
Finished Jul 01 12:39:39 PM PDT 24
Peak memory 199908 kb
Host smart-11c2ca88-1353-4942-985e-6822774ddc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425804099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3425804099
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3794423683
Short name T303
Test name
Test status
Simulation time 142654872924 ps
CPU time 16.24 seconds
Started Jul 01 12:38:49 PM PDT 24
Finished Jul 01 12:39:07 PM PDT 24
Peak memory 198420 kb
Host smart-bc77215a-0ff6-4d33-b3ef-ede01ec1a702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794423683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3794423683
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2930455540
Short name T632
Test name
Test status
Simulation time 127327871073 ps
CPU time 238.34 seconds
Started Jul 01 12:38:52 PM PDT 24
Finished Jul 01 12:42:51 PM PDT 24
Peak memory 199952 kb
Host smart-2e709dff-4635-49dd-9c71-df7a1022dfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930455540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2930455540
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2811583738
Short name T365
Test name
Test status
Simulation time 99023386199 ps
CPU time 200 seconds
Started Jul 01 12:38:54 PM PDT 24
Finished Jul 01 12:42:15 PM PDT 24
Peak memory 199976 kb
Host smart-4e82e351-f793-45c4-9501-232d9d1495a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811583738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2811583738
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3742293034
Short name T416
Test name
Test status
Simulation time 4941323029 ps
CPU time 11.4 seconds
Started Jul 01 12:38:53 PM PDT 24
Finished Jul 01 12:39:05 PM PDT 24
Peak memory 199356 kb
Host smart-c6b75f86-8437-4dc2-a466-2dbad67df66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742293034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3742293034
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.128449688
Short name T780
Test name
Test status
Simulation time 9924255741 ps
CPU time 154.44 seconds
Started Jul 01 12:38:55 PM PDT 24
Finished Jul 01 12:41:30 PM PDT 24
Peak memory 199876 kb
Host smart-0669e853-c009-48e3-aa6f-a7d09365fcd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128449688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.128449688
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1262767198
Short name T1028
Test name
Test status
Simulation time 6086182386 ps
CPU time 24.22 seconds
Started Jul 01 12:38:49 PM PDT 24
Finished Jul 01 12:39:14 PM PDT 24
Peak memory 199360 kb
Host smart-67924381-6ffb-49ac-b66f-50332d94598c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262767198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1262767198
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2062925763
Short name T621
Test name
Test status
Simulation time 13318963127 ps
CPU time 20.44 seconds
Started Jul 01 12:38:53 PM PDT 24
Finished Jul 01 12:39:14 PM PDT 24
Peak memory 199636 kb
Host smart-22119bc3-1bc1-43e2-86e1-8064cbc53bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062925763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2062925763
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3447535074
Short name T427
Test name
Test status
Simulation time 3521375607 ps
CPU time 1.77 seconds
Started Jul 01 12:38:48 PM PDT 24
Finished Jul 01 12:38:51 PM PDT 24
Peak memory 196780 kb
Host smart-963406a8-98db-44ae-ab5f-e24664c45a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447535074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3447535074
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.799119669
Short name T433
Test name
Test status
Simulation time 6307783402 ps
CPU time 7.4 seconds
Started Jul 01 12:38:50 PM PDT 24
Finished Jul 01 12:38:58 PM PDT 24
Peak memory 199916 kb
Host smart-e9073130-c9f7-4678-a8be-2ce987dc7cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799119669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.799119669
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2707287598
Short name T1000
Test name
Test status
Simulation time 2495630594 ps
CPU time 2.2 seconds
Started Jul 01 12:38:54 PM PDT 24
Finished Jul 01 12:38:57 PM PDT 24
Peak memory 198564 kb
Host smart-781ba176-4774-47ab-ae01-f0b796b6a7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707287598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2707287598
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1107831426
Short name T597
Test name
Test status
Simulation time 9678449191 ps
CPU time 4.02 seconds
Started Jul 01 12:38:49 PM PDT 24
Finished Jul 01 12:38:54 PM PDT 24
Peak memory 197720 kb
Host smart-52cc5c90-ff5f-4c15-a6ff-520821b5e145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107831426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1107831426
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2440516338
Short name T181
Test name
Test status
Simulation time 73212103955 ps
CPU time 79.93 seconds
Started Jul 01 12:45:39 PM PDT 24
Finished Jul 01 12:47:00 PM PDT 24
Peak memory 199908 kb
Host smart-b23e6d00-3077-4a27-a96c-194edea8981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440516338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2440516338
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2947123823
Short name T73
Test name
Test status
Simulation time 13997953161 ps
CPU time 53.72 seconds
Started Jul 01 12:45:40 PM PDT 24
Finished Jul 01 12:46:35 PM PDT 24
Peak memory 199996 kb
Host smart-c2fc7081-1565-4293-8fc5-f2d875125344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947123823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2947123823
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.509639497
Short name T687
Test name
Test status
Simulation time 59820261187 ps
CPU time 98.77 seconds
Started Jul 01 12:45:42 PM PDT 24
Finished Jul 01 12:47:22 PM PDT 24
Peak memory 199920 kb
Host smart-0ab48b9f-ca90-4433-abf8-075fbb324ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509639497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.509639497
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1122655776
Short name T904
Test name
Test status
Simulation time 42610039879 ps
CPU time 19.14 seconds
Started Jul 01 12:45:41 PM PDT 24
Finished Jul 01 12:46:01 PM PDT 24
Peak memory 199916 kb
Host smart-4892a3e3-f177-463e-8c1e-4d9ee09adaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122655776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1122655776
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1745613758
Short name T116
Test name
Test status
Simulation time 164414988429 ps
CPU time 71.35 seconds
Started Jul 01 12:45:40 PM PDT 24
Finished Jul 01 12:46:53 PM PDT 24
Peak memory 199936 kb
Host smart-3d33bcb9-318c-4948-926f-7902deff3f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745613758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1745613758
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.494238253
Short name T530
Test name
Test status
Simulation time 268059058176 ps
CPU time 153.05 seconds
Started Jul 01 12:45:41 PM PDT 24
Finished Jul 01 12:48:16 PM PDT 24
Peak memory 199832 kb
Host smart-bddacbf3-78a6-4ca2-9530-adefd47ac69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494238253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.494238253
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1117216088
Short name T913
Test name
Test status
Simulation time 14937460474 ps
CPU time 24.81 seconds
Started Jul 01 12:45:44 PM PDT 24
Finished Jul 01 12:46:09 PM PDT 24
Peak memory 199988 kb
Host smart-f844a994-4880-4c5c-bcde-f64fba2f52a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117216088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1117216088
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.4188790062
Short name T982
Test name
Test status
Simulation time 116467714605 ps
CPU time 68.64 seconds
Started Jul 01 12:45:41 PM PDT 24
Finished Jul 01 12:46:51 PM PDT 24
Peak memory 199956 kb
Host smart-4ea41f4b-bad9-4943-86b9-81698efe978b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188790062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.4188790062
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2752770337
Short name T378
Test name
Test status
Simulation time 31373806637 ps
CPU time 49.19 seconds
Started Jul 01 12:45:41 PM PDT 24
Finished Jul 01 12:46:31 PM PDT 24
Peak memory 199892 kb
Host smart-dfab7ab1-ef39-42fa-a9b4-0a059bb16740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752770337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2752770337
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.720887552
Short name T488
Test name
Test status
Simulation time 24566392 ps
CPU time 0.55 seconds
Started Jul 01 12:39:09 PM PDT 24
Finished Jul 01 12:39:10 PM PDT 24
Peak memory 194184 kb
Host smart-91cef418-ebe0-42f7-b4d1-db2abb3076bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720887552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.720887552
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1735635359
Short name T269
Test name
Test status
Simulation time 31083913890 ps
CPU time 47.24 seconds
Started Jul 01 12:39:02 PM PDT 24
Finished Jul 01 12:39:50 PM PDT 24
Peak memory 199936 kb
Host smart-a3a56294-fbee-4a01-b602-f52a11b12cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735635359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1735635359
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.793623786
Short name T131
Test name
Test status
Simulation time 34253073188 ps
CPU time 51.82 seconds
Started Jul 01 12:38:58 PM PDT 24
Finished Jul 01 12:39:51 PM PDT 24
Peak memory 200004 kb
Host smart-3fb816a8-36ff-4147-8a13-8f8be676292e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793623786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.793623786
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1209025589
Short name T167
Test name
Test status
Simulation time 165045176051 ps
CPU time 53.75 seconds
Started Jul 01 12:38:59 PM PDT 24
Finished Jul 01 12:39:54 PM PDT 24
Peak memory 199984 kb
Host smart-ad33d8a8-dbc1-4be7-99ef-331c9c706669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209025589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1209025589
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.684346718
Short name T564
Test name
Test status
Simulation time 43312886798 ps
CPU time 21.59 seconds
Started Jul 01 12:38:59 PM PDT 24
Finished Jul 01 12:39:22 PM PDT 24
Peak memory 199952 kb
Host smart-9b70ed39-4561-44c4-bd2d-f297d6f074c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684346718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.684346718
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3917960653
Short name T253
Test name
Test status
Simulation time 110518690917 ps
CPU time 696.23 seconds
Started Jul 01 12:39:05 PM PDT 24
Finished Jul 01 12:50:42 PM PDT 24
Peak memory 199932 kb
Host smart-ec813bd1-9518-4f1d-9123-64a29558f886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3917960653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3917960653
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.499114097
Short name T930
Test name
Test status
Simulation time 12711830406 ps
CPU time 29.86 seconds
Started Jul 01 12:39:04 PM PDT 24
Finished Jul 01 12:39:35 PM PDT 24
Peak memory 199876 kb
Host smart-fa4bf33e-6b19-4c6a-89f2-8484655733bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499114097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.499114097
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.3117038317
Short name T955
Test name
Test status
Simulation time 14206959424 ps
CPU time 787.41 seconds
Started Jul 01 12:39:05 PM PDT 24
Finished Jul 01 12:52:13 PM PDT 24
Peak memory 199936 kb
Host smart-7e6395ef-0ed7-439a-bacc-24a8dd216159
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117038317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3117038317
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3803221494
Short name T649
Test name
Test status
Simulation time 6166065354 ps
CPU time 35.87 seconds
Started Jul 01 12:39:02 PM PDT 24
Finished Jul 01 12:39:39 PM PDT 24
Peak memory 198196 kb
Host smart-1b498323-e8c0-4253-9431-a0032d545ebd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803221494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3803221494
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2534428311
Short name T1096
Test name
Test status
Simulation time 57633276529 ps
CPU time 89.29 seconds
Started Jul 01 12:39:04 PM PDT 24
Finished Jul 01 12:40:34 PM PDT 24
Peak memory 199968 kb
Host smart-0ce3aacb-0fe4-4b47-8246-f876e6814983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534428311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2534428311
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1714676257
Short name T645
Test name
Test status
Simulation time 4895506762 ps
CPU time 1.24 seconds
Started Jul 01 12:38:59 PM PDT 24
Finished Jul 01 12:39:02 PM PDT 24
Peak memory 196060 kb
Host smart-1eb3e56a-bd90-4a97-9da9-447b780f28f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714676257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1714676257
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1233118066
Short name T898
Test name
Test status
Simulation time 310980796 ps
CPU time 1.03 seconds
Started Jul 01 12:39:00 PM PDT 24
Finished Jul 01 12:39:02 PM PDT 24
Peak memory 198376 kb
Host smart-0f1915a8-6130-422e-8805-383b5bc4ff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233118066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1233118066
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4243718855
Short name T397
Test name
Test status
Simulation time 5878709743 ps
CPU time 1.89 seconds
Started Jul 01 12:39:05 PM PDT 24
Finished Jul 01 12:39:07 PM PDT 24
Peak memory 199616 kb
Host smart-96a15435-b901-424c-b724-c12bcba86127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243718855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4243718855
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.12892654
Short name T783
Test name
Test status
Simulation time 69633644292 ps
CPU time 85.53 seconds
Started Jul 01 12:39:01 PM PDT 24
Finished Jul 01 12:40:27 PM PDT 24
Peak memory 199940 kb
Host smart-d74e6faf-3c07-40a4-ae99-1907095fda58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12892654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.12892654
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2132270676
Short name T741
Test name
Test status
Simulation time 40733362065 ps
CPU time 13.03 seconds
Started Jul 01 12:45:42 PM PDT 24
Finished Jul 01 12:45:56 PM PDT 24
Peak memory 199708 kb
Host smart-72d7e229-425f-4a13-a7a2-d980513bb4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132270676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2132270676
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2365582238
Short name T809
Test name
Test status
Simulation time 86788920634 ps
CPU time 30.32 seconds
Started Jul 01 12:45:40 PM PDT 24
Finished Jul 01 12:46:11 PM PDT 24
Peak memory 199948 kb
Host smart-d14ba038-23c7-4b22-9e57-cc7f78d3d620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365582238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2365582238
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.236723885
Short name T574
Test name
Test status
Simulation time 62104420541 ps
CPU time 29.6 seconds
Started Jul 01 12:45:41 PM PDT 24
Finished Jul 01 12:46:12 PM PDT 24
Peak memory 199944 kb
Host smart-5dee9e8a-b318-40f5-8ea4-2a07828eb03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236723885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.236723885
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2425567483
Short name T387
Test name
Test status
Simulation time 16410066069 ps
CPU time 8.6 seconds
Started Jul 01 12:45:44 PM PDT 24
Finished Jul 01 12:45:54 PM PDT 24
Peak memory 199932 kb
Host smart-5556081f-69b9-417f-8bae-39c4adbd7101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425567483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2425567483
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.558712247
Short name T971
Test name
Test status
Simulation time 81816093952 ps
CPU time 46.55 seconds
Started Jul 01 12:45:44 PM PDT 24
Finished Jul 01 12:46:32 PM PDT 24
Peak memory 199936 kb
Host smart-e13b1240-710b-40a0-af8b-6b955626886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558712247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.558712247
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.4245636146
Short name T135
Test name
Test status
Simulation time 25496668197 ps
CPU time 22.52 seconds
Started Jul 01 12:45:45 PM PDT 24
Finished Jul 01 12:46:09 PM PDT 24
Peak memory 199832 kb
Host smart-b09f91d0-33a0-40ac-a9c7-69cb6cc29062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245636146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4245636146
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1920658439
Short name T205
Test name
Test status
Simulation time 51450108527 ps
CPU time 101.65 seconds
Started Jul 01 12:45:45 PM PDT 24
Finished Jul 01 12:47:28 PM PDT 24
Peak memory 199992 kb
Host smart-6715b8e3-e355-49af-9fee-488f4aadfb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920658439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1920658439
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.54253430
Short name T273
Test name
Test status
Simulation time 17948725242 ps
CPU time 14.39 seconds
Started Jul 01 12:45:45 PM PDT 24
Finished Jul 01 12:46:00 PM PDT 24
Peak memory 199424 kb
Host smart-82e401a9-2059-4afa-a738-f83996b8e50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54253430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.54253430
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2379402686
Short name T195
Test name
Test status
Simulation time 4725733220 ps
CPU time 3.97 seconds
Started Jul 01 12:45:46 PM PDT 24
Finished Jul 01 12:45:50 PM PDT 24
Peak memory 198804 kb
Host smart-b8324e6a-832b-49e4-9844-0b4c556bd57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379402686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2379402686
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.285360541
Short name T737
Test name
Test status
Simulation time 76808739 ps
CPU time 0.57 seconds
Started Jul 01 12:39:19 PM PDT 24
Finished Jul 01 12:39:20 PM PDT 24
Peak memory 195308 kb
Host smart-53552c47-ce83-49bf-a78d-47351b1f0ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285360541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.285360541
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.625616171
Short name T417
Test name
Test status
Simulation time 77333079564 ps
CPU time 119.21 seconds
Started Jul 01 12:39:10 PM PDT 24
Finished Jul 01 12:41:10 PM PDT 24
Peak memory 200012 kb
Host smart-1266cf0a-9c1f-4767-a088-8f7eb9c4929b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625616171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.625616171
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.853320189
Short name T178
Test name
Test status
Simulation time 44131464967 ps
CPU time 26.73 seconds
Started Jul 01 12:39:08 PM PDT 24
Finished Jul 01 12:39:36 PM PDT 24
Peak memory 199568 kb
Host smart-ca38e265-124b-4a01-9211-4e811e466456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853320189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.853320189
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.4043464405
Short name T790
Test name
Test status
Simulation time 115637239516 ps
CPU time 48.59 seconds
Started Jul 01 12:39:07 PM PDT 24
Finished Jul 01 12:39:56 PM PDT 24
Peak memory 199892 kb
Host smart-88b4d9dc-ac35-4c0e-b3b7-a9af5b29490e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043464405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4043464405
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1537185016
Short name T936
Test name
Test status
Simulation time 24889175409 ps
CPU time 14.24 seconds
Started Jul 01 12:39:08 PM PDT 24
Finished Jul 01 12:39:23 PM PDT 24
Peak memory 199800 kb
Host smart-857ace02-5dd8-433d-aa48-493ae8450461
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537185016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1537185016
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1669791362
Short name T775
Test name
Test status
Simulation time 92410178027 ps
CPU time 988.1 seconds
Started Jul 01 12:39:13 PM PDT 24
Finished Jul 01 12:55:42 PM PDT 24
Peak memory 199932 kb
Host smart-eb167e04-e8d3-46a4-916b-298f88ab18c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669791362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1669791362
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.928063323
Short name T724
Test name
Test status
Simulation time 9260550197 ps
CPU time 3.4 seconds
Started Jul 01 12:39:12 PM PDT 24
Finished Jul 01 12:39:16 PM PDT 24
Peak memory 198056 kb
Host smart-caaa7e7c-d256-4390-83fe-78e00edab9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928063323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.928063323
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.2053778095
Short name T726
Test name
Test status
Simulation time 18661909071 ps
CPU time 686.42 seconds
Started Jul 01 12:39:15 PM PDT 24
Finished Jul 01 12:50:42 PM PDT 24
Peak memory 199924 kb
Host smart-e869f1de-836c-4651-ad16-fd2a3748c749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2053778095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2053778095
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3862757452
Short name T1076
Test name
Test status
Simulation time 5663113335 ps
CPU time 20.15 seconds
Started Jul 01 12:39:08 PM PDT 24
Finished Jul 01 12:39:29 PM PDT 24
Peak memory 198104 kb
Host smart-6192f542-d073-4c31-9e53-db020526dc2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3862757452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3862757452
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2856408381
Short name T733
Test name
Test status
Simulation time 96805045599 ps
CPU time 205.92 seconds
Started Jul 01 12:39:16 PM PDT 24
Finished Jul 01 12:42:43 PM PDT 24
Peak memory 199976 kb
Host smart-ddef442b-3b25-4190-a26c-cf0a929542f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856408381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2856408381
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1875167259
Short name T742
Test name
Test status
Simulation time 5745449152 ps
CPU time 2.65 seconds
Started Jul 01 12:39:13 PM PDT 24
Finished Jul 01 12:39:17 PM PDT 24
Peak memory 196228 kb
Host smart-2a17e1d3-ea77-4d85-a70f-013a92bb6ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875167259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1875167259
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.375300354
Short name T721
Test name
Test status
Simulation time 85955203 ps
CPU time 0.97 seconds
Started Jul 01 12:39:09 PM PDT 24
Finished Jul 01 12:39:11 PM PDT 24
Peak memory 199812 kb
Host smart-ba34f781-65ea-4eb5-bf0a-aae1c38cfa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375300354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.375300354
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.133177871
Short name T957
Test name
Test status
Simulation time 306965111418 ps
CPU time 355.76 seconds
Started Jul 01 12:39:18 PM PDT 24
Finished Jul 01 12:45:14 PM PDT 24
Peak memory 199888 kb
Host smart-c5525661-d993-4c3f-aa32-bf6572d4e447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133177871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.133177871
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2744207376
Short name T770
Test name
Test status
Simulation time 796200393 ps
CPU time 3.4 seconds
Started Jul 01 12:39:13 PM PDT 24
Finished Jul 01 12:39:17 PM PDT 24
Peak memory 199900 kb
Host smart-3241ec90-efda-4f2f-8e06-5a6a7d5a042d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744207376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2744207376
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3895444701
Short name T279
Test name
Test status
Simulation time 60588545466 ps
CPU time 50.01 seconds
Started Jul 01 12:39:10 PM PDT 24
Finished Jul 01 12:40:01 PM PDT 24
Peak memory 199864 kb
Host smart-f0a39cfb-1cb7-4360-b020-2d44496bd349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895444701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3895444701
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3127501248
Short name T221
Test name
Test status
Simulation time 34391960177 ps
CPU time 55.49 seconds
Started Jul 01 12:45:54 PM PDT 24
Finished Jul 01 12:46:50 PM PDT 24
Peak memory 199876 kb
Host smart-469d3e36-568e-4e55-826d-e0b74aa21041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127501248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3127501248
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1701490604
Short name T215
Test name
Test status
Simulation time 5375252437 ps
CPU time 10.75 seconds
Started Jul 01 12:45:46 PM PDT 24
Finished Jul 01 12:45:57 PM PDT 24
Peak memory 200004 kb
Host smart-04c7a32f-f47e-42c2-a60c-a704e475f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701490604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1701490604
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2590512489
Short name T191
Test name
Test status
Simulation time 61306708592 ps
CPU time 19.62 seconds
Started Jul 01 12:45:46 PM PDT 24
Finished Jul 01 12:46:06 PM PDT 24
Peak memory 199940 kb
Host smart-405e49fc-b9fe-4bbd-b346-80d9ca5c2edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590512489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2590512489
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2462786559
Short name T382
Test name
Test status
Simulation time 8962826473 ps
CPU time 18.02 seconds
Started Jul 01 12:45:45 PM PDT 24
Finished Jul 01 12:46:04 PM PDT 24
Peak memory 199856 kb
Host smart-a7b88e21-8dff-4505-abda-e596c1004234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462786559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2462786559
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3501413624
Short name T569
Test name
Test status
Simulation time 162572389614 ps
CPU time 120.81 seconds
Started Jul 01 12:45:45 PM PDT 24
Finished Jul 01 12:47:47 PM PDT 24
Peak memory 199948 kb
Host smart-c0824a17-25c7-4059-9b9c-3713a25863c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501413624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3501413624
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.369126541
Short name T187
Test name
Test status
Simulation time 55640685363 ps
CPU time 74.38 seconds
Started Jul 01 12:45:50 PM PDT 24
Finished Jul 01 12:47:05 PM PDT 24
Peak memory 199956 kb
Host smart-06c4708f-9664-4a32-9d00-d12e40007616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369126541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.369126541
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3110797251
Short name T142
Test name
Test status
Simulation time 86633754664 ps
CPU time 62.02 seconds
Started Jul 01 12:45:52 PM PDT 24
Finished Jul 01 12:46:54 PM PDT 24
Peak memory 199980 kb
Host smart-7892709b-0770-4bca-a1e0-4f6a1de70a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110797251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3110797251
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2033833281
Short name T941
Test name
Test status
Simulation time 233625418774 ps
CPU time 336.49 seconds
Started Jul 01 12:45:59 PM PDT 24
Finished Jul 01 12:51:38 PM PDT 24
Peak memory 199964 kb
Host smart-d4f6e3bd-0505-4f0c-8dfa-f3b26c91f2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033833281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2033833281
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.165050764
Short name T411
Test name
Test status
Simulation time 47264819866 ps
CPU time 19.2 seconds
Started Jul 01 12:45:58 PM PDT 24
Finished Jul 01 12:46:19 PM PDT 24
Peak memory 199880 kb
Host smart-d4746dab-cf4f-44d5-8a0f-f905d22ef52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165050764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.165050764
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1181999810
Short name T1015
Test name
Test status
Simulation time 32164797 ps
CPU time 0.55 seconds
Started Jul 01 12:39:33 PM PDT 24
Finished Jul 01 12:39:35 PM PDT 24
Peak memory 194496 kb
Host smart-b5195cd9-080a-47d1-9c33-0b0775be0203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181999810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1181999810
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.81924987
Short name T963
Test name
Test status
Simulation time 110551763021 ps
CPU time 139.88 seconds
Started Jul 01 12:39:22 PM PDT 24
Finished Jul 01 12:41:43 PM PDT 24
Peak memory 199864 kb
Host smart-61f3e90f-b720-489b-bcdf-cdbbddedb77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81924987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.81924987
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1581567325
Short name T309
Test name
Test status
Simulation time 38097756220 ps
CPU time 62.2 seconds
Started Jul 01 12:39:24 PM PDT 24
Finished Jul 01 12:40:27 PM PDT 24
Peak memory 199916 kb
Host smart-39e1382a-70ab-487c-b406-c52326e6c17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581567325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1581567325
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.255034130
Short name T228
Test name
Test status
Simulation time 23998562745 ps
CPU time 27.27 seconds
Started Jul 01 12:39:24 PM PDT 24
Finished Jul 01 12:39:53 PM PDT 24
Peak memory 199924 kb
Host smart-a43a636d-5849-497a-8396-701cb3847bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255034130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.255034130
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3742006222
Short name T339
Test name
Test status
Simulation time 7176684550 ps
CPU time 11.45 seconds
Started Jul 01 12:39:24 PM PDT 24
Finished Jul 01 12:39:36 PM PDT 24
Peak memory 196592 kb
Host smart-0151978d-c810-45fd-9ece-ed1792c6138c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742006222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3742006222
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2046194015
Short name T740
Test name
Test status
Simulation time 56172184487 ps
CPU time 274.37 seconds
Started Jul 01 12:39:33 PM PDT 24
Finished Jul 01 12:44:09 PM PDT 24
Peak memory 199928 kb
Host smart-841ff71e-e22c-4c9c-8ef8-53fff9a2c750
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046194015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2046194015
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.4043522717
Short name T10
Test name
Test status
Simulation time 4396716157 ps
CPU time 5.06 seconds
Started Jul 01 12:39:33 PM PDT 24
Finished Jul 01 12:39:38 PM PDT 24
Peak memory 198544 kb
Host smart-f60e5f2b-4450-4f6b-b561-83aff98309c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043522717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.4043522717
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.3262964897
Short name T734
Test name
Test status
Simulation time 4772458916 ps
CPU time 68.74 seconds
Started Jul 01 12:39:35 PM PDT 24
Finished Jul 01 12:40:44 PM PDT 24
Peak memory 199924 kb
Host smart-485eb7f1-d945-48d4-a170-eccdf8311d03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3262964897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3262964897
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.750007253
Short name T773
Test name
Test status
Simulation time 7447746152 ps
CPU time 33.61 seconds
Started Jul 01 12:39:23 PM PDT 24
Finished Jul 01 12:39:57 PM PDT 24
Peak memory 197932 kb
Host smart-e26ba45a-3b8d-4550-81c2-4e00b2f1b255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750007253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.750007253
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3542987008
Short name T577
Test name
Test status
Simulation time 132803697749 ps
CPU time 53.28 seconds
Started Jul 01 12:39:28 PM PDT 24
Finished Jul 01 12:40:23 PM PDT 24
Peak memory 199920 kb
Host smart-9946e9ce-8a1e-4c64-8cc8-b38a8b9f2070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542987008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3542987008
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1652754854
Short name T634
Test name
Test status
Simulation time 5691769274 ps
CPU time 7.11 seconds
Started Jul 01 12:39:23 PM PDT 24
Finished Jul 01 12:39:31 PM PDT 24
Peak memory 196236 kb
Host smart-0a4b9577-5f10-437d-8fff-5a1bde0ffe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652754854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1652754854
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3453367897
Short name T977
Test name
Test status
Simulation time 863329469 ps
CPU time 1.63 seconds
Started Jul 01 12:39:18 PM PDT 24
Finished Jul 01 12:39:21 PM PDT 24
Peak memory 198680 kb
Host smart-10e34b1a-5076-4acc-a499-4b894cc24a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453367897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3453367897
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2149103076
Short name T182
Test name
Test status
Simulation time 182963807211 ps
CPU time 83.93 seconds
Started Jul 01 12:39:36 PM PDT 24
Finished Jul 01 12:41:00 PM PDT 24
Peak memory 199916 kb
Host smart-6f5f066f-13a1-4d42-9617-b954cffb0f58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149103076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2149103076
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3209428035
Short name T1058
Test name
Test status
Simulation time 2679901110 ps
CPU time 2.11 seconds
Started Jul 01 12:39:28 PM PDT 24
Finished Jul 01 12:39:32 PM PDT 24
Peak memory 198232 kb
Host smart-1129d515-dc09-4a0a-bd5a-597c40dd63ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209428035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3209428035
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.617161865
Short name T720
Test name
Test status
Simulation time 37036108987 ps
CPU time 16.84 seconds
Started Jul 01 12:39:24 PM PDT 24
Finished Jul 01 12:39:41 PM PDT 24
Peak memory 199948 kb
Host smart-729c3e7f-73b6-4de4-9683-a27363bdaa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617161865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.617161865
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1267500043
Short name T673
Test name
Test status
Simulation time 37131392210 ps
CPU time 17.32 seconds
Started Jul 01 12:45:50 PM PDT 24
Finished Jul 01 12:46:08 PM PDT 24
Peak memory 200028 kb
Host smart-9ae90781-85e9-4b12-8dfc-d0c38b4abc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267500043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1267500043
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2312016321
Short name T613
Test name
Test status
Simulation time 91618216276 ps
CPU time 144.38 seconds
Started Jul 01 12:45:59 PM PDT 24
Finished Jul 01 12:48:25 PM PDT 24
Peak memory 199920 kb
Host smart-4fc2e1e6-95cb-480a-a9a8-90a5f57d3cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312016321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2312016321
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1056816632
Short name T830
Test name
Test status
Simulation time 77713727645 ps
CPU time 65.18 seconds
Started Jul 01 12:45:50 PM PDT 24
Finished Jul 01 12:46:56 PM PDT 24
Peak memory 199936 kb
Host smart-1a13b0eb-f10f-45da-82bd-47caa8d1d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056816632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1056816632
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2673596641
Short name T691
Test name
Test status
Simulation time 38083154002 ps
CPU time 14.75 seconds
Started Jul 01 12:45:59 PM PDT 24
Finished Jul 01 12:46:16 PM PDT 24
Peak memory 199880 kb
Host smart-f02f84b2-2896-4966-b61f-22531a7e190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673596641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2673596641
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3476446111
Short name T882
Test name
Test status
Simulation time 10092113948 ps
CPU time 15.71 seconds
Started Jul 01 12:45:52 PM PDT 24
Finished Jul 01 12:46:08 PM PDT 24
Peak memory 200012 kb
Host smart-73ef042e-2651-4450-8383-e63e3054bd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476446111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3476446111
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.4136480738
Short name T236
Test name
Test status
Simulation time 33860098519 ps
CPU time 23.21 seconds
Started Jul 01 12:45:59 PM PDT 24
Finished Jul 01 12:46:25 PM PDT 24
Peak memory 199936 kb
Host smart-e2b772e9-756b-4e78-93e4-b79f5dc35b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136480738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.4136480738
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3074657059
Short name T291
Test name
Test status
Simulation time 137928804445 ps
CPU time 101.59 seconds
Started Jul 01 12:45:59 PM PDT 24
Finished Jul 01 12:47:44 PM PDT 24
Peak memory 199920 kb
Host smart-16298cc5-5bb0-438e-b745-1065f9dce507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074657059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3074657059
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2088593218
Short name T425
Test name
Test status
Simulation time 129413548797 ps
CPU time 74.36 seconds
Started Jul 01 12:45:50 PM PDT 24
Finished Jul 01 12:47:05 PM PDT 24
Peak memory 199912 kb
Host smart-7e4144cb-cdb0-4d14-b78e-2f70b661d005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088593218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2088593218
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3962091373
Short name T704
Test name
Test status
Simulation time 22480716599 ps
CPU time 35.78 seconds
Started Jul 01 12:45:51 PM PDT 24
Finished Jul 01 12:46:27 PM PDT 24
Peak memory 199932 kb
Host smart-7220085d-eda9-49f9-b4b5-48b76f6ad567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962091373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3962091373
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3106382883
Short name T623
Test name
Test status
Simulation time 66592636 ps
CPU time 0.58 seconds
Started Jul 01 12:39:40 PM PDT 24
Finished Jul 01 12:39:42 PM PDT 24
Peak memory 195604 kb
Host smart-489de8ac-7d5c-4206-83a0-44b21ddec8d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106382883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3106382883
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.830587469
Short name T1004
Test name
Test status
Simulation time 64384450237 ps
CPU time 26.21 seconds
Started Jul 01 12:39:28 PM PDT 24
Finished Jul 01 12:39:56 PM PDT 24
Peak memory 200012 kb
Host smart-c80eb132-7ac1-41a1-ad86-2066e592d5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830587469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.830587469
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3426999868
Short name T887
Test name
Test status
Simulation time 144286519920 ps
CPU time 214.05 seconds
Started Jul 01 12:39:28 PM PDT 24
Finished Jul 01 12:43:03 PM PDT 24
Peak memory 199840 kb
Host smart-91175243-9c98-411c-a45a-284db7af6de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426999868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3426999868
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1433742090
Short name T810
Test name
Test status
Simulation time 141805921540 ps
CPU time 46.3 seconds
Started Jul 01 12:39:28 PM PDT 24
Finished Jul 01 12:40:16 PM PDT 24
Peak memory 199916 kb
Host smart-7631b478-5fb3-406f-8b75-5950114ab4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433742090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1433742090
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2838571481
Short name T840
Test name
Test status
Simulation time 21853454024 ps
CPU time 33.59 seconds
Started Jul 01 12:39:37 PM PDT 24
Finished Jul 01 12:40:12 PM PDT 24
Peak memory 199000 kb
Host smart-5c042b28-edf1-402b-9a92-13f6bbf62cdd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838571481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2838571481
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.866742694
Short name T375
Test name
Test status
Simulation time 96793182814 ps
CPU time 923.37 seconds
Started Jul 01 12:39:34 PM PDT 24
Finished Jul 01 12:54:58 PM PDT 24
Peak memory 199944 kb
Host smart-852a07cf-61cb-4765-87ea-be1199bb330c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=866742694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.866742694
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3636749888
Short name T978
Test name
Test status
Simulation time 5815930486 ps
CPU time 10.02 seconds
Started Jul 01 12:39:37 PM PDT 24
Finished Jul 01 12:39:48 PM PDT 24
Peak memory 197404 kb
Host smart-7a7f7c82-b998-42d3-9ec4-422002e6cb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636749888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3636749888
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.4275125075
Short name T511
Test name
Test status
Simulation time 15947988394 ps
CPU time 589.2 seconds
Started Jul 01 12:39:33 PM PDT 24
Finished Jul 01 12:49:24 PM PDT 24
Peak memory 199944 kb
Host smart-06490ae0-ed71-402a-8f9b-442b48acca3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4275125075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.4275125075
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.853386142
Short name T880
Test name
Test status
Simulation time 5816943761 ps
CPU time 6.75 seconds
Started Jul 01 12:39:30 PM PDT 24
Finished Jul 01 12:39:37 PM PDT 24
Peak memory 199212 kb
Host smart-683670fe-7cf2-48b9-8888-7611f2e431af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853386142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.853386142
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.165190775
Short name T478
Test name
Test status
Simulation time 32451064172 ps
CPU time 69.84 seconds
Started Jul 01 12:39:34 PM PDT 24
Finished Jul 01 12:40:44 PM PDT 24
Peak memory 199924 kb
Host smart-f14e50bf-f644-4858-83cb-62adf4feb616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165190775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.165190775
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.114046345
Short name T1089
Test name
Test status
Simulation time 4695721507 ps
CPU time 2.2 seconds
Started Jul 01 12:39:37 PM PDT 24
Finished Jul 01 12:39:40 PM PDT 24
Peak memory 196232 kb
Host smart-0b711812-2534-4379-95f1-50b29430fa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114046345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.114046345
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2989123621
Short name T259
Test name
Test status
Simulation time 5806087993 ps
CPU time 14.96 seconds
Started Jul 01 12:39:29 PM PDT 24
Finished Jul 01 12:39:45 PM PDT 24
Peak memory 199912 kb
Host smart-b4651b3c-f839-4e44-8aff-c5616c67ad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989123621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2989123621
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2986717095
Short name T175
Test name
Test status
Simulation time 331997563625 ps
CPU time 1191.25 seconds
Started Jul 01 12:39:39 PM PDT 24
Finished Jul 01 12:59:31 PM PDT 24
Peak memory 199980 kb
Host smart-b3052711-8b6c-4fcb-a87b-97cf30aa0b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986717095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2986717095
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3054314514
Short name T795
Test name
Test status
Simulation time 3014123143 ps
CPU time 38.33 seconds
Started Jul 01 12:39:36 PM PDT 24
Finished Jul 01 12:40:16 PM PDT 24
Peak memory 216516 kb
Host smart-39497467-03ee-4151-9f92-fdfaca10f790
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054314514 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3054314514
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3727847175
Short name T998
Test name
Test status
Simulation time 7597230847 ps
CPU time 13.04 seconds
Started Jul 01 12:39:33 PM PDT 24
Finished Jul 01 12:39:47 PM PDT 24
Peak memory 199904 kb
Host smart-690624ab-9cc7-40fc-b859-c31947109db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727847175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3727847175
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1176995099
Short name T991
Test name
Test status
Simulation time 35777152834 ps
CPU time 15.75 seconds
Started Jul 01 12:39:33 PM PDT 24
Finished Jul 01 12:39:50 PM PDT 24
Peak memory 199880 kb
Host smart-fd0d5c2e-44d3-4603-b0ab-1c6587aa9fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176995099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1176995099
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3340193508
Short name T237
Test name
Test status
Simulation time 10770502048 ps
CPU time 17.08 seconds
Started Jul 01 12:45:49 PM PDT 24
Finished Jul 01 12:46:07 PM PDT 24
Peak memory 199936 kb
Host smart-ec2fd2be-c3ac-4e6a-bac3-c7658dc7ba81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340193508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3340193508
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.4261252982
Short name T620
Test name
Test status
Simulation time 54374667995 ps
CPU time 8.24 seconds
Started Jul 01 12:45:50 PM PDT 24
Finished Jul 01 12:45:59 PM PDT 24
Peak memory 199784 kb
Host smart-43c35653-12d2-49d4-b522-ae5991f74d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261252982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.4261252982
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.406845733
Short name T1026
Test name
Test status
Simulation time 28913341257 ps
CPU time 14.8 seconds
Started Jul 01 12:45:51 PM PDT 24
Finished Jul 01 12:46:07 PM PDT 24
Peak memory 199996 kb
Host smart-2598a203-63ff-424e-b555-6250fa801935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406845733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.406845733
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1908858848
Short name T1027
Test name
Test status
Simulation time 121730943948 ps
CPU time 78.26 seconds
Started Jul 01 12:45:50 PM PDT 24
Finished Jul 01 12:47:09 PM PDT 24
Peak memory 199940 kb
Host smart-6d732eef-3695-4fe0-aa17-2c1e906533f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908858848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1908858848
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3404616949
Short name T137
Test name
Test status
Simulation time 61731178445 ps
CPU time 24.57 seconds
Started Jul 01 12:45:55 PM PDT 24
Finished Jul 01 12:46:20 PM PDT 24
Peak memory 199832 kb
Host smart-6f199edc-d2d0-4a35-97b6-5c206e1f4c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404616949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3404616949
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1111453961
Short name T925
Test name
Test status
Simulation time 45252197744 ps
CPU time 64.54 seconds
Started Jul 01 12:45:57 PM PDT 24
Finished Jul 01 12:47:03 PM PDT 24
Peak memory 199880 kb
Host smart-7b55b942-5bd5-4db7-8a06-4d692d1184b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111453961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1111453961
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1281791574
Short name T430
Test name
Test status
Simulation time 21742558885 ps
CPU time 12.58 seconds
Started Jul 01 12:45:57 PM PDT 24
Finished Jul 01 12:46:11 PM PDT 24
Peak memory 199968 kb
Host smart-8918b932-86d5-4c15-83df-7f8eb51b5c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281791574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1281791574
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2003942860
Short name T827
Test name
Test status
Simulation time 113401636630 ps
CPU time 342.96 seconds
Started Jul 01 12:45:55 PM PDT 24
Finished Jul 01 12:51:39 PM PDT 24
Peak memory 199976 kb
Host smart-1c117349-7530-490a-bc79-5fd8025fc853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003942860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2003942860
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1976334563
Short name T703
Test name
Test status
Simulation time 63989937571 ps
CPU time 24.46 seconds
Started Jul 01 12:45:56 PM PDT 24
Finished Jul 01 12:46:22 PM PDT 24
Peak memory 200092 kb
Host smart-aaa763a1-ade9-4c84-ae01-0dcda1ba04de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976334563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1976334563
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.4029330288
Short name T298
Test name
Test status
Simulation time 164312932801 ps
CPU time 141.76 seconds
Started Jul 01 12:45:55 PM PDT 24
Finished Jul 01 12:48:18 PM PDT 24
Peak memory 199972 kb
Host smart-58e312fc-fbfe-4e39-b6b0-dcd1eb09ad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029330288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4029330288
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.4272032819
Short name T976
Test name
Test status
Simulation time 40889505 ps
CPU time 0.61 seconds
Started Jul 01 12:35:44 PM PDT 24
Finished Jul 01 12:35:45 PM PDT 24
Peak memory 195580 kb
Host smart-612e203c-d4f5-4b0b-8996-6e69c7f8ea00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272032819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.4272032819
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.800815919
Short name T946
Test name
Test status
Simulation time 204168073459 ps
CPU time 123.51 seconds
Started Jul 01 12:35:41 PM PDT 24
Finished Jul 01 12:37:45 PM PDT 24
Peak memory 199992 kb
Host smart-7a96f0bf-4a2e-4b18-8c8f-454e4a92bc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800815919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.800815919
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.911557744
Short name T395
Test name
Test status
Simulation time 113815214952 ps
CPU time 59.4 seconds
Started Jul 01 12:35:40 PM PDT 24
Finished Jul 01 12:36:40 PM PDT 24
Peak memory 200020 kb
Host smart-8aee25b9-c8df-4a16-ba31-c4be7faab42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911557744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.911557744
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1408271144
Short name T348
Test name
Test status
Simulation time 101613171438 ps
CPU time 65.24 seconds
Started Jul 01 12:35:35 PM PDT 24
Finished Jul 01 12:36:40 PM PDT 24
Peak memory 199672 kb
Host smart-0a7b8282-0cb4-4040-aee8-7ab9598832ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408271144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1408271144
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2745504566
Short name T805
Test name
Test status
Simulation time 238349983993 ps
CPU time 373.93 seconds
Started Jul 01 12:35:35 PM PDT 24
Finished Jul 01 12:41:50 PM PDT 24
Peak memory 196996 kb
Host smart-fb7a05af-756c-408a-b34a-7722f121c16d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745504566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2745504566
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3573972370
Short name T256
Test name
Test status
Simulation time 114372935017 ps
CPU time 850.34 seconds
Started Jul 01 12:35:40 PM PDT 24
Finished Jul 01 12:49:51 PM PDT 24
Peak memory 200080 kb
Host smart-ee1be56b-9c45-4c55-ad07-23f1578a69e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573972370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3573972370
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2280356931
Short name T473
Test name
Test status
Simulation time 980729008 ps
CPU time 1.61 seconds
Started Jul 01 12:35:35 PM PDT 24
Finished Jul 01 12:35:37 PM PDT 24
Peak memory 198480 kb
Host smart-1c4d9114-c3a6-45a2-881b-04c3b3dcc828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280356931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2280356931
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.3050182086
Short name T973
Test name
Test status
Simulation time 2843594594 ps
CPU time 100.6 seconds
Started Jul 01 12:35:36 PM PDT 24
Finished Jul 01 12:37:17 PM PDT 24
Peak memory 199948 kb
Host smart-6b01a82a-4a4b-4f2b-9420-2c62362f769b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3050182086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3050182086
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3985573355
Short name T1012
Test name
Test status
Simulation time 2216342848 ps
CPU time 10.03 seconds
Started Jul 01 12:35:33 PM PDT 24
Finished Jul 01 12:35:44 PM PDT 24
Peak memory 197984 kb
Host smart-64ff7510-7bdf-4a40-ae07-081d1d865a4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985573355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3985573355
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1333087912
Short name T802
Test name
Test status
Simulation time 42572960489 ps
CPU time 47.2 seconds
Started Jul 01 12:35:40 PM PDT 24
Finished Jul 01 12:36:28 PM PDT 24
Peak memory 199932 kb
Host smart-4f293234-9c70-4483-a281-7074fd384948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333087912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1333087912
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.703668426
Short name T42
Test name
Test status
Simulation time 4683094171 ps
CPU time 7.36 seconds
Started Jul 01 12:35:40 PM PDT 24
Finished Jul 01 12:35:48 PM PDT 24
Peak memory 196368 kb
Host smart-5c805208-79a3-4f0c-8e12-71a6c5fe80d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703668426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.703668426
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3129375651
Short name T34
Test name
Test status
Simulation time 43379923 ps
CPU time 0.78 seconds
Started Jul 01 12:35:42 PM PDT 24
Finished Jul 01 12:35:43 PM PDT 24
Peak memory 218100 kb
Host smart-c991fc38-720e-4997-9f92-0c5ce5da78f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129375651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3129375651
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1396079075
Short name T295
Test name
Test status
Simulation time 5337705766 ps
CPU time 16.25 seconds
Started Jul 01 12:35:38 PM PDT 24
Finished Jul 01 12:35:54 PM PDT 24
Peak memory 199744 kb
Host smart-30ff5325-ebea-4715-9269-339aed3ad5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396079075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1396079075
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1858171040
Short name T768
Test name
Test status
Simulation time 175590398193 ps
CPU time 29.73 seconds
Started Jul 01 12:35:40 PM PDT 24
Finished Jul 01 12:36:11 PM PDT 24
Peak memory 199896 kb
Host smart-541ba2d4-d3f7-4c00-8a60-33f02beae2da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858171040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1858171040
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2718644091
Short name T23
Test name
Test status
Simulation time 1165433058 ps
CPU time 3.7 seconds
Started Jul 01 12:35:40 PM PDT 24
Finished Jul 01 12:35:44 PM PDT 24
Peak memory 198820 kb
Host smart-b1c71481-54ae-436b-8c0e-07560e1f9036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718644091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2718644091
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2121915421
Short name T444
Test name
Test status
Simulation time 36435166072 ps
CPU time 64.18 seconds
Started Jul 01 12:35:34 PM PDT 24
Finished Jul 01 12:36:39 PM PDT 24
Peak memory 199968 kb
Host smart-4058587c-d2e8-47a6-9aa4-dc910b73da9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121915421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2121915421
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1263934009
Short name T394
Test name
Test status
Simulation time 11793675 ps
CPU time 0.57 seconds
Started Jul 01 12:39:47 PM PDT 24
Finished Jul 01 12:39:48 PM PDT 24
Peak memory 195244 kb
Host smart-6d419a99-aff2-431d-9416-8f3f4464a707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263934009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1263934009
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3882931814
Short name T1042
Test name
Test status
Simulation time 129019822100 ps
CPU time 188.82 seconds
Started Jul 01 12:39:40 PM PDT 24
Finished Jul 01 12:42:49 PM PDT 24
Peak memory 199976 kb
Host smart-c205e67c-bd2d-4437-be29-eec739880136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882931814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3882931814
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.47634138
Short name T432
Test name
Test status
Simulation time 98264503048 ps
CPU time 196.25 seconds
Started Jul 01 12:39:39 PM PDT 24
Finished Jul 01 12:42:56 PM PDT 24
Peak memory 199904 kb
Host smart-0b5a7315-1537-4d90-8905-e8137778904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47634138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.47634138
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.129065393
Short name T644
Test name
Test status
Simulation time 186154799944 ps
CPU time 65.06 seconds
Started Jul 01 12:39:38 PM PDT 24
Finished Jul 01 12:40:43 PM PDT 24
Peak memory 199840 kb
Host smart-0d9093c4-a7af-4453-a1bf-e857c7704412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129065393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.129065393
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1495031804
Short name T815
Test name
Test status
Simulation time 19462513773 ps
CPU time 30.43 seconds
Started Jul 01 12:39:42 PM PDT 24
Finished Jul 01 12:40:14 PM PDT 24
Peak memory 199844 kb
Host smart-1f5f41fa-043a-4beb-9c9b-9bbf62cc8264
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495031804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1495031804
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3090598106
Short name T410
Test name
Test status
Simulation time 102084658652 ps
CPU time 351.79 seconds
Started Jul 01 12:39:44 PM PDT 24
Finished Jul 01 12:45:36 PM PDT 24
Peak memory 199928 kb
Host smart-b3c30228-69d7-4e36-8f52-a1b46e0b7cd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3090598106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3090598106
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.44864812
Short name T28
Test name
Test status
Simulation time 5097810889 ps
CPU time 3.46 seconds
Started Jul 01 12:39:48 PM PDT 24
Finished Jul 01 12:39:52 PM PDT 24
Peak memory 198372 kb
Host smart-09654c47-1d3a-419c-beac-bd5648eec777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44864812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.44864812
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.3859105203
Short name T706
Test name
Test status
Simulation time 6185804895 ps
CPU time 266.8 seconds
Started Jul 01 12:39:41 PM PDT 24
Finished Jul 01 12:44:08 PM PDT 24
Peak memory 199992 kb
Host smart-194509f6-b442-462d-aa58-87dc62a46f5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859105203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3859105203
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2405258471
Short name T714
Test name
Test status
Simulation time 6851048830 ps
CPU time 19.08 seconds
Started Jul 01 12:39:41 PM PDT 24
Finished Jul 01 12:40:01 PM PDT 24
Peak memory 199200 kb
Host smart-34a41f4a-b9da-4cc6-954d-75f96933e277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405258471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2405258471
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.119258571
Short name T685
Test name
Test status
Simulation time 42984698246 ps
CPU time 70.13 seconds
Started Jul 01 12:39:42 PM PDT 24
Finished Jul 01 12:40:53 PM PDT 24
Peak memory 200004 kb
Host smart-61f1acb1-3b2d-4e2b-964e-9a15dc19068a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119258571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.119258571
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.873385800
Short name T550
Test name
Test status
Simulation time 675792067 ps
CPU time 1.19 seconds
Started Jul 01 12:39:43 PM PDT 24
Finished Jul 01 12:39:45 PM PDT 24
Peak memory 195384 kb
Host smart-cb7cd3d8-d260-4fb8-8d21-1a671c7d1764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873385800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.873385800
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3490115989
Short name T248
Test name
Test status
Simulation time 5455624119 ps
CPU time 12.25 seconds
Started Jul 01 12:39:39 PM PDT 24
Finished Jul 01 12:39:52 PM PDT 24
Peak memory 199104 kb
Host smart-67687d87-01c9-4ac8-8ebc-e03e60272795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490115989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3490115989
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1542282458
Short name T614
Test name
Test status
Simulation time 75525955180 ps
CPU time 1127.15 seconds
Started Jul 01 12:39:49 PM PDT 24
Finished Jul 01 12:58:37 PM PDT 24
Peak memory 200000 kb
Host smart-add2a309-b394-4d07-894a-5ce9f9973dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542282458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1542282458
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.508918896
Short name T316
Test name
Test status
Simulation time 110972134303 ps
CPU time 361.05 seconds
Started Jul 01 12:39:50 PM PDT 24
Finished Jul 01 12:45:52 PM PDT 24
Peak memory 216576 kb
Host smart-31079322-b232-4f10-a19b-83944202010a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508918896 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.508918896
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2658095276
Short name T545
Test name
Test status
Simulation time 7318122281 ps
CPU time 13.48 seconds
Started Jul 01 12:39:41 PM PDT 24
Finished Jul 01 12:39:55 PM PDT 24
Peak memory 199924 kb
Host smart-062ccfb3-9c4c-4896-a115-40887f75b507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658095276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2658095276
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2467917206
Short name T1098
Test name
Test status
Simulation time 72170265081 ps
CPU time 122.16 seconds
Started Jul 01 12:39:40 PM PDT 24
Finished Jul 01 12:41:43 PM PDT 24
Peak memory 199988 kb
Host smart-4541d8fb-3a8f-4725-914b-09d69c660669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467917206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2467917206
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3528107974
Short name T30
Test name
Test status
Simulation time 19397026 ps
CPU time 0.57 seconds
Started Jul 01 12:39:59 PM PDT 24
Finished Jul 01 12:40:00 PM PDT 24
Peak memory 195312 kb
Host smart-e3800483-f5ae-4086-901a-81299678f5ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528107974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3528107974
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.90944169
Short name T875
Test name
Test status
Simulation time 14282632210 ps
CPU time 11.25 seconds
Started Jul 01 12:39:54 PM PDT 24
Finished Jul 01 12:40:06 PM PDT 24
Peak memory 199604 kb
Host smart-d2e3e374-ccb7-4c83-902c-d0d4fb8ad486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90944169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.90944169
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3100596209
Short name T12
Test name
Test status
Simulation time 52140973423 ps
CPU time 18.35 seconds
Started Jul 01 12:39:53 PM PDT 24
Finished Jul 01 12:40:12 PM PDT 24
Peak memory 199932 kb
Host smart-f5811b9c-456b-4a5a-bf5f-d0f80d8f7992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100596209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3100596209
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3842850910
Short name T244
Test name
Test status
Simulation time 40316065709 ps
CPU time 14.47 seconds
Started Jul 01 12:39:53 PM PDT 24
Finished Jul 01 12:40:09 PM PDT 24
Peak memory 200044 kb
Host smart-1522b009-fe9e-448d-ac9e-3087d15f4d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842850910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3842850910
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1340499417
Short name T319
Test name
Test status
Simulation time 28516917498 ps
CPU time 15.72 seconds
Started Jul 01 12:39:55 PM PDT 24
Finished Jul 01 12:40:12 PM PDT 24
Peak memory 199960 kb
Host smart-5612143c-a123-476b-be06-a578f9842d29
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340499417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1340499417
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2249606693
Short name T1008
Test name
Test status
Simulation time 96610387600 ps
CPU time 174.1 seconds
Started Jul 01 12:39:58 PM PDT 24
Finished Jul 01 12:42:53 PM PDT 24
Peak memory 199932 kb
Host smart-096ffca9-74a5-416e-90f8-8a4f940ea045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249606693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2249606693
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.469722307
Short name T754
Test name
Test status
Simulation time 4185617658 ps
CPU time 7.59 seconds
Started Jul 01 12:39:54 PM PDT 24
Finished Jul 01 12:40:02 PM PDT 24
Peak memory 197532 kb
Host smart-d93031ed-6038-4767-96ad-d5809f863a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469722307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.469722307
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.4211934181
Short name T1021
Test name
Test status
Simulation time 16138313787 ps
CPU time 493.09 seconds
Started Jul 01 12:39:59 PM PDT 24
Finished Jul 01 12:48:13 PM PDT 24
Peak memory 200004 kb
Host smart-487a2a3b-3a0e-46b0-bdd2-f3ea4b00af45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4211934181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4211934181
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.832644409
Short name T56
Test name
Test status
Simulation time 6398319073 ps
CPU time 4.33 seconds
Started Jul 01 12:39:54 PM PDT 24
Finished Jul 01 12:40:00 PM PDT 24
Peak memory 198392 kb
Host smart-df56160d-4893-4536-a28f-a65928c6b273
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832644409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.832644409
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2955099646
Short name T379
Test name
Test status
Simulation time 34735645520 ps
CPU time 51.79 seconds
Started Jul 01 12:39:54 PM PDT 24
Finished Jul 01 12:40:47 PM PDT 24
Peak memory 199932 kb
Host smart-d06fa06c-bf95-44a1-af62-c29dd60d50a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955099646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2955099646
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3181328216
Short name T74
Test name
Test status
Simulation time 2084601905 ps
CPU time 2.08 seconds
Started Jul 01 12:39:54 PM PDT 24
Finished Jul 01 12:39:57 PM PDT 24
Peak memory 195600 kb
Host smart-6bdbeae0-4741-4b0b-9daa-d429738e1c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181328216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3181328216
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.592012065
Short name T1034
Test name
Test status
Simulation time 5358489331 ps
CPU time 9.09 seconds
Started Jul 01 12:39:48 PM PDT 24
Finished Jul 01 12:39:58 PM PDT 24
Peak memory 199800 kb
Host smart-f71eaf07-359c-48c8-a169-d04f8473b163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592012065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.592012065
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1219584652
Short name T967
Test name
Test status
Simulation time 126913024235 ps
CPU time 1708.03 seconds
Started Jul 01 12:39:57 PM PDT 24
Finished Jul 01 01:08:26 PM PDT 24
Peak memory 199964 kb
Host smart-e6db5ecf-ff7b-421f-8473-34cb68232def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219584652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1219584652
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1333498539
Short name T915
Test name
Test status
Simulation time 6554317576 ps
CPU time 38.29 seconds
Started Jul 01 12:39:55 PM PDT 24
Finished Jul 01 12:40:34 PM PDT 24
Peak memory 199116 kb
Host smart-080a22d4-730d-407f-b6d2-908335d92cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333498539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1333498539
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1104611419
Short name T539
Test name
Test status
Simulation time 18769220974 ps
CPU time 8.6 seconds
Started Jul 01 12:39:47 PM PDT 24
Finished Jul 01 12:39:56 PM PDT 24
Peak memory 199212 kb
Host smart-6b146ca3-80dd-470b-ac1d-46f05fb83b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104611419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1104611419
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2475485876
Short name T562
Test name
Test status
Simulation time 29068963 ps
CPU time 0.58 seconds
Started Jul 01 12:40:10 PM PDT 24
Finished Jul 01 12:40:12 PM PDT 24
Peak memory 194712 kb
Host smart-d3c24aaa-ee20-47c8-8b66-88a58a3b2022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475485876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2475485876
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3994154211
Short name T1057
Test name
Test status
Simulation time 51610387600 ps
CPU time 56.98 seconds
Started Jul 01 12:40:02 PM PDT 24
Finished Jul 01 12:41:00 PM PDT 24
Peak memory 200120 kb
Host smart-6be5dec0-d182-4df8-8b34-594e7ec12d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994154211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3994154211
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.4115906778
Short name T846
Test name
Test status
Simulation time 184170501216 ps
CPU time 40.27 seconds
Started Jul 01 12:40:00 PM PDT 24
Finished Jul 01 12:40:41 PM PDT 24
Peak memory 199732 kb
Host smart-fcf43439-e93a-4e7d-a282-13b801d90825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115906778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4115906778
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.800461952
Short name T500
Test name
Test status
Simulation time 20880608702 ps
CPU time 36.65 seconds
Started Jul 01 12:40:00 PM PDT 24
Finished Jul 01 12:40:37 PM PDT 24
Peak memory 199868 kb
Host smart-21b11c82-ba89-45ae-aba1-929947a4a918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800461952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.800461952
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3284510488
Short name T593
Test name
Test status
Simulation time 190762279684 ps
CPU time 70.87 seconds
Started Jul 01 12:40:04 PM PDT 24
Finished Jul 01 12:41:16 PM PDT 24
Peak memory 196928 kb
Host smart-0727a714-5d0c-41c0-9bba-48328eae8876
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284510488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3284510488
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3603324396
Short name T653
Test name
Test status
Simulation time 92893492819 ps
CPU time 594.01 seconds
Started Jul 01 12:40:09 PM PDT 24
Finished Jul 01 12:50:03 PM PDT 24
Peak memory 199980 kb
Host smart-2d5330d7-5d2c-496f-b087-c5dcad2271b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3603324396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3603324396
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.4125362950
Short name T670
Test name
Test status
Simulation time 13576878172 ps
CPU time 5.27 seconds
Started Jul 01 12:40:06 PM PDT 24
Finished Jul 01 12:40:12 PM PDT 24
Peak memory 199948 kb
Host smart-0bbaeec8-ac1c-4755-aa1c-ff14c4fa00ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125362950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.4125362950
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.2078350029
Short name T438
Test name
Test status
Simulation time 11213391024 ps
CPU time 583.44 seconds
Started Jul 01 12:40:05 PM PDT 24
Finished Jul 01 12:49:50 PM PDT 24
Peak memory 199864 kb
Host smart-e7978053-ea68-4938-854c-f8de5d75de37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2078350029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2078350029
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2420973304
Short name T677
Test name
Test status
Simulation time 5668328607 ps
CPU time 51.23 seconds
Started Jul 01 12:40:05 PM PDT 24
Finished Jul 01 12:40:57 PM PDT 24
Peak memory 197988 kb
Host smart-212991df-02b3-4d9a-ad68-c3f919583a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420973304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2420973304
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.735839276
Short name T429
Test name
Test status
Simulation time 29568290643 ps
CPU time 26.94 seconds
Started Jul 01 12:40:06 PM PDT 24
Finished Jul 01 12:40:34 PM PDT 24
Peak memory 200000 kb
Host smart-99fa7422-5770-499d-b142-6c0124273026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735839276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.735839276
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.4098971046
Short name T1095
Test name
Test status
Simulation time 35561471265 ps
CPU time 55 seconds
Started Jul 01 12:40:03 PM PDT 24
Finished Jul 01 12:40:58 PM PDT 24
Peak memory 196008 kb
Host smart-e7318869-6844-4c61-93dc-ad7a802b3b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098971046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4098971046
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1184046136
Short name T3
Test name
Test status
Simulation time 5911567834 ps
CPU time 20.33 seconds
Started Jul 01 12:40:00 PM PDT 24
Finished Jul 01 12:40:21 PM PDT 24
Peak memory 199960 kb
Host smart-66e5623f-6fe9-4350-b537-648b15667e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184046136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1184046136
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1193724016
Short name T1044
Test name
Test status
Simulation time 1373696383 ps
CPU time 1.84 seconds
Started Jul 01 12:40:04 PM PDT 24
Finished Jul 01 12:40:07 PM PDT 24
Peak memory 198788 kb
Host smart-52cb02f5-4fbf-493b-ad51-dc447e83eb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193724016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1193724016
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3522785636
Short name T119
Test name
Test status
Simulation time 16781880687 ps
CPU time 31.2 seconds
Started Jul 01 12:39:59 PM PDT 24
Finished Jul 01 12:40:31 PM PDT 24
Peak memory 200004 kb
Host smart-7f58aba8-1a27-4daf-b30f-b76ad54d5e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522785636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3522785636
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3783201463
Short name T467
Test name
Test status
Simulation time 32108765 ps
CPU time 0.55 seconds
Started Jul 01 12:40:18 PM PDT 24
Finished Jul 01 12:40:19 PM PDT 24
Peak memory 194932 kb
Host smart-4fc04c80-ccf2-4eda-9af6-380f70220b58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783201463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3783201463
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2702053995
Short name T462
Test name
Test status
Simulation time 86470993638 ps
CPU time 136.28 seconds
Started Jul 01 12:40:12 PM PDT 24
Finished Jul 01 12:42:29 PM PDT 24
Peak memory 200120 kb
Host smart-0ed84137-3af0-4335-8a1c-850da3c2730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702053995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2702053995
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.190222852
Short name T557
Test name
Test status
Simulation time 85879841238 ps
CPU time 109.82 seconds
Started Jul 01 12:40:10 PM PDT 24
Finished Jul 01 12:42:01 PM PDT 24
Peak memory 199832 kb
Host smart-e2a36e9a-3b03-41a8-80f4-0ea1db501a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190222852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.190222852
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3131099834
Short name T288
Test name
Test status
Simulation time 215878420117 ps
CPU time 502.78 seconds
Started Jul 01 12:40:14 PM PDT 24
Finished Jul 01 12:48:38 PM PDT 24
Peak memory 199872 kb
Host smart-0f8ccfa6-aa03-4259-9800-0cdecbdfd62e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131099834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3131099834
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3916541222
Short name T405
Test name
Test status
Simulation time 200876744860 ps
CPU time 1896.99 seconds
Started Jul 01 12:40:21 PM PDT 24
Finished Jul 01 01:11:59 PM PDT 24
Peak memory 199928 kb
Host smart-cb19e67d-04cf-4b6b-99db-ba8ab87ec180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916541222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3916541222
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3171513016
Short name T459
Test name
Test status
Simulation time 3312457560 ps
CPU time 3.93 seconds
Started Jul 01 12:40:16 PM PDT 24
Finished Jul 01 12:40:21 PM PDT 24
Peak memory 199804 kb
Host smart-10b480a4-e052-4cf1-b929-5cd93f7fbee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171513016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3171513016
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.626798275
Short name T756
Test name
Test status
Simulation time 18730067145 ps
CPU time 857.1 seconds
Started Jul 01 12:40:14 PM PDT 24
Finished Jul 01 12:54:32 PM PDT 24
Peak memory 199960 kb
Host smart-ca2a65ad-81ae-429b-a83e-9920b69404c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626798275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.626798275
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3041439610
Short name T504
Test name
Test status
Simulation time 6360443087 ps
CPU time 4.39 seconds
Started Jul 01 12:40:15 PM PDT 24
Finished Jul 01 12:40:20 PM PDT 24
Peak memory 199196 kb
Host smart-5aacfb5b-1d2b-4e75-8590-cd6256de4bb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3041439610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3041439610
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2775983567
Short name T855
Test name
Test status
Simulation time 132441261917 ps
CPU time 112.64 seconds
Started Jul 01 12:40:15 PM PDT 24
Finished Jul 01 12:42:08 PM PDT 24
Peak memory 199932 kb
Host smart-8923290d-8eba-40a9-9742-d49ad895b9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775983567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2775983567
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3029548124
Short name T435
Test name
Test status
Simulation time 1404501351 ps
CPU time 2.94 seconds
Started Jul 01 12:40:15 PM PDT 24
Finished Jul 01 12:40:18 PM PDT 24
Peak memory 195416 kb
Host smart-111c3c98-37c2-42e8-a715-0902ae4599cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029548124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3029548124
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.512953727
Short name T755
Test name
Test status
Simulation time 6117569423 ps
CPU time 7.63 seconds
Started Jul 01 12:40:12 PM PDT 24
Finished Jul 01 12:40:20 PM PDT 24
Peak memory 199292 kb
Host smart-1fef71e5-19bc-4acb-8d3f-48ef375560ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512953727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.512953727
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.622201182
Short name T1052
Test name
Test status
Simulation time 166921888815 ps
CPU time 182.69 seconds
Started Jul 01 12:40:21 PM PDT 24
Finished Jul 01 12:43:24 PM PDT 24
Peak memory 216384 kb
Host smart-795470df-f9de-4d42-8426-57089bcc62c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622201182 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.622201182
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2189652940
Short name T745
Test name
Test status
Simulation time 6925112392 ps
CPU time 14.76 seconds
Started Jul 01 12:40:14 PM PDT 24
Finished Jul 01 12:40:29 PM PDT 24
Peak memory 199920 kb
Host smart-549d84ed-311b-4660-abaa-f628bae5e5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189652940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2189652940
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2119502912
Short name T835
Test name
Test status
Simulation time 51240639485 ps
CPU time 41.34 seconds
Started Jul 01 12:40:10 PM PDT 24
Finished Jul 01 12:40:52 PM PDT 24
Peak memory 199812 kb
Host smart-eb2e7ac6-131c-4c4d-92c3-23a9cf687aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119502912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2119502912
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.420668025
Short name T452
Test name
Test status
Simulation time 37870037 ps
CPU time 0.56 seconds
Started Jul 01 12:40:28 PM PDT 24
Finished Jul 01 12:40:29 PM PDT 24
Peak memory 195588 kb
Host smart-40c23e92-8aa6-4e22-9c07-628babad7fee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420668025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.420668025
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.343452357
Short name T933
Test name
Test status
Simulation time 23400632099 ps
CPU time 35.35 seconds
Started Jul 01 12:40:19 PM PDT 24
Finished Jul 01 12:40:55 PM PDT 24
Peak memory 199996 kb
Host smart-eccaa7ec-35ff-4117-aa33-7da1f8790259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343452357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.343452357
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.498119124
Short name T559
Test name
Test status
Simulation time 221755155419 ps
CPU time 41.01 seconds
Started Jul 01 12:40:20 PM PDT 24
Finished Jul 01 12:41:01 PM PDT 24
Peak memory 199736 kb
Host smart-6fe96d5b-3202-4c3f-b2a2-efec683aeecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498119124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.498119124
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2004225830
Short name T1092
Test name
Test status
Simulation time 230280664673 ps
CPU time 140.16 seconds
Started Jul 01 12:40:25 PM PDT 24
Finished Jul 01 12:42:45 PM PDT 24
Peak memory 199908 kb
Host smart-02f48d57-cbc3-473b-bfc4-d000c9d9cf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004225830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2004225830
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.504077708
Short name T423
Test name
Test status
Simulation time 264699441001 ps
CPU time 384.41 seconds
Started Jul 01 12:40:24 PM PDT 24
Finished Jul 01 12:46:49 PM PDT 24
Peak memory 197092 kb
Host smart-19c15000-16f4-4d32-95d2-f61fe3fb9b7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504077708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.504077708
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2432215803
Short name T354
Test name
Test status
Simulation time 56238210504 ps
CPU time 277.38 seconds
Started Jul 01 12:40:29 PM PDT 24
Finished Jul 01 12:45:07 PM PDT 24
Peak memory 199968 kb
Host smart-cd14d74e-d588-42cd-a4b6-3fc2a4e56017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432215803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2432215803
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1326840046
Short name T857
Test name
Test status
Simulation time 10345807312 ps
CPU time 19.97 seconds
Started Jul 01 12:40:30 PM PDT 24
Finished Jul 01 12:40:50 PM PDT 24
Peak memory 199508 kb
Host smart-f71b3e1f-5183-4270-b355-302bd336b972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326840046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1326840046
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.3161695540
Short name T251
Test name
Test status
Simulation time 12598110080 ps
CPU time 205.59 seconds
Started Jul 01 12:40:32 PM PDT 24
Finished Jul 01 12:43:58 PM PDT 24
Peak memory 199908 kb
Host smart-34ac7522-25b2-4b89-a826-5604a0e59a3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161695540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3161695540
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1579879661
Short name T1065
Test name
Test status
Simulation time 4317624169 ps
CPU time 9.07 seconds
Started Jul 01 12:40:26 PM PDT 24
Finished Jul 01 12:40:35 PM PDT 24
Peak memory 198072 kb
Host smart-f2732d21-3b5e-4a72-9179-f80577d1ab86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579879661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1579879661
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.654832655
Short name T717
Test name
Test status
Simulation time 21615651104 ps
CPU time 37.43 seconds
Started Jul 01 12:40:28 PM PDT 24
Finished Jul 01 12:41:06 PM PDT 24
Peak memory 199936 kb
Host smart-78758317-7291-42e4-9900-93defa1107a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654832655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.654832655
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2327048079
Short name T814
Test name
Test status
Simulation time 3313808294 ps
CPU time 5.26 seconds
Started Jul 01 12:40:24 PM PDT 24
Finished Jul 01 12:40:30 PM PDT 24
Peak memory 196360 kb
Host smart-3f40c749-7112-4304-a7b0-ab9caa8c3850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327048079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2327048079
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2540641029
Short name T865
Test name
Test status
Simulation time 663531032 ps
CPU time 1.72 seconds
Started Jul 01 12:40:19 PM PDT 24
Finished Jul 01 12:40:21 PM PDT 24
Peak memory 199908 kb
Host smart-abf5a215-c626-43ab-b123-1c88bff937eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540641029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2540641029
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1190206133
Short name T68
Test name
Test status
Simulation time 736820351 ps
CPU time 3.54 seconds
Started Jul 01 12:40:27 PM PDT 24
Finished Jul 01 12:40:31 PM PDT 24
Peak memory 199176 kb
Host smart-b226dafa-64cd-4216-b7e2-750474294fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190206133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1190206133
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1525967420
Short name T828
Test name
Test status
Simulation time 12500171146 ps
CPU time 20.58 seconds
Started Jul 01 12:40:19 PM PDT 24
Finished Jul 01 12:40:40 PM PDT 24
Peak memory 199964 kb
Host smart-605ef40d-e212-41a2-88ec-0ce8acf4ad6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525967420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1525967420
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3823065732
Short name T713
Test name
Test status
Simulation time 36073235 ps
CPU time 0.58 seconds
Started Jul 01 12:40:35 PM PDT 24
Finished Jul 01 12:40:36 PM PDT 24
Peak memory 195324 kb
Host smart-ec18f87e-ddd6-4180-8591-b55363a72ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823065732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3823065732
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.169223535
Short name T563
Test name
Test status
Simulation time 127501246288 ps
CPU time 323.19 seconds
Started Jul 01 12:40:29 PM PDT 24
Finished Jul 01 12:45:53 PM PDT 24
Peak memory 199948 kb
Host smart-d69fe826-6d86-43b2-9a08-45d06b280a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169223535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.169223535
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1848060238
Short name T400
Test name
Test status
Simulation time 33204911126 ps
CPU time 41.47 seconds
Started Jul 01 12:40:28 PM PDT 24
Finished Jul 01 12:41:10 PM PDT 24
Peak memory 200024 kb
Host smart-be2ab729-154f-4474-af26-28e046bfe594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848060238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1848060238
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3678595369
Short name T595
Test name
Test status
Simulation time 18840680437 ps
CPU time 26.96 seconds
Started Jul 01 12:40:28 PM PDT 24
Finished Jul 01 12:40:56 PM PDT 24
Peak memory 199996 kb
Host smart-3a997e22-f9cc-4938-b839-80971c9718ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678595369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3678595369
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2084309544
Short name T749
Test name
Test status
Simulation time 33283208997 ps
CPU time 16.93 seconds
Started Jul 01 12:40:28 PM PDT 24
Finished Jul 01 12:40:46 PM PDT 24
Peak memory 199976 kb
Host smart-7cd85c4d-b2d2-4263-bcdf-877ed7114e50
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084309544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2084309544
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.208378618
Short name T384
Test name
Test status
Simulation time 125670987707 ps
CPU time 299.89 seconds
Started Jul 01 12:40:35 PM PDT 24
Finished Jul 01 12:45:35 PM PDT 24
Peak memory 199924 kb
Host smart-b16cdbec-3e45-4af9-a7e2-7cb9291586b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208378618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.208378618
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1161452332
Short name T594
Test name
Test status
Simulation time 12722514277 ps
CPU time 7.93 seconds
Started Jul 01 12:40:35 PM PDT 24
Finished Jul 01 12:40:44 PM PDT 24
Peak memory 198616 kb
Host smart-cd74aa0e-09e5-42cc-adef-1400ee264760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161452332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1161452332
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.1558693728
Short name T255
Test name
Test status
Simulation time 26575180570 ps
CPU time 1201.77 seconds
Started Jul 01 12:40:36 PM PDT 24
Finished Jul 01 01:00:38 PM PDT 24
Peak memory 199984 kb
Host smart-5e03db29-7310-4525-8b94-9dfa03a56951
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558693728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1558693728
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3554811002
Short name T396
Test name
Test status
Simulation time 1273044166 ps
CPU time 2.56 seconds
Started Jul 01 12:40:30 PM PDT 24
Finished Jul 01 12:40:33 PM PDT 24
Peak memory 198204 kb
Host smart-a518312e-e862-4037-9e42-6026d8896031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3554811002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3554811002
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2755979380
Short name T506
Test name
Test status
Simulation time 108894894475 ps
CPU time 376.46 seconds
Started Jul 01 12:40:38 PM PDT 24
Finished Jul 01 12:46:55 PM PDT 24
Peak memory 199888 kb
Host smart-93945065-e9c3-4c0c-8c3b-b8e55ba4731f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755979380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2755979380
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1363313090
Short name T355
Test name
Test status
Simulation time 2374004781 ps
CPU time 1.68 seconds
Started Jul 01 12:40:35 PM PDT 24
Finished Jul 01 12:40:38 PM PDT 24
Peak memory 195916 kb
Host smart-cefda2e0-4d57-4795-a100-544b782089e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363313090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1363313090
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1732921627
Short name T893
Test name
Test status
Simulation time 5685565353 ps
CPU time 18.77 seconds
Started Jul 01 12:40:28 PM PDT 24
Finished Jul 01 12:40:48 PM PDT 24
Peak memory 199856 kb
Host smart-124f0f2d-d0a4-44bc-b2c5-4a272a7660b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732921627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1732921627
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3439194413
Short name T498
Test name
Test status
Simulation time 294473535252 ps
CPU time 192.34 seconds
Started Jul 01 12:40:35 PM PDT 24
Finished Jul 01 12:43:47 PM PDT 24
Peak memory 198792 kb
Host smart-b46b302c-7f5e-4e57-9990-ee7a964b918f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439194413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3439194413
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1796350428
Short name T230
Test name
Test status
Simulation time 74384565807 ps
CPU time 777.35 seconds
Started Jul 01 12:40:35 PM PDT 24
Finished Jul 01 12:53:33 PM PDT 24
Peak memory 216532 kb
Host smart-d324f629-aa06-4a33-bfd9-7cd8504c53b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796350428 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1796350428
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2137577132
Short name T304
Test name
Test status
Simulation time 858870421 ps
CPU time 2.68 seconds
Started Jul 01 12:40:34 PM PDT 24
Finished Jul 01 12:40:37 PM PDT 24
Peak memory 198784 kb
Host smart-97b1584a-e874-4376-a69a-ebd054932fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137577132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2137577132
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1327747875
Short name T606
Test name
Test status
Simulation time 49509227379 ps
CPU time 78.62 seconds
Started Jul 01 12:40:30 PM PDT 24
Finished Jul 01 12:41:49 PM PDT 24
Peak memory 199936 kb
Host smart-a36033c6-0605-4dc3-bff6-bd53879fd6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327747875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1327747875
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3451262500
Short name T657
Test name
Test status
Simulation time 12283593 ps
CPU time 0.57 seconds
Started Jul 01 12:40:50 PM PDT 24
Finished Jul 01 12:40:52 PM PDT 24
Peak memory 195280 kb
Host smart-69d2f784-8a9d-4193-a15a-2e3a71357bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451262500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3451262500
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1199442341
Short name T931
Test name
Test status
Simulation time 115413405500 ps
CPU time 266.22 seconds
Started Jul 01 12:40:39 PM PDT 24
Finished Jul 01 12:45:06 PM PDT 24
Peak memory 199812 kb
Host smart-762a01e5-b0e2-4033-a9cf-d7b36d4ad2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199442341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1199442341
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3584339185
Short name T867
Test name
Test status
Simulation time 20186089286 ps
CPU time 17.68 seconds
Started Jul 01 12:40:41 PM PDT 24
Finished Jul 01 12:40:59 PM PDT 24
Peak memory 200000 kb
Host smart-8d510f57-f3b1-410e-9333-cf6cee0222d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584339185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3584339185
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2287938447
Short name T776
Test name
Test status
Simulation time 103603927268 ps
CPU time 198.63 seconds
Started Jul 01 12:40:39 PM PDT 24
Finished Jul 01 12:43:58 PM PDT 24
Peak memory 199936 kb
Host smart-c5b48ef5-d2fb-44bc-b2c9-c41333dea6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287938447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2287938447
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3305709887
Short name T684
Test name
Test status
Simulation time 646325467739 ps
CPU time 998.85 seconds
Started Jul 01 12:40:41 PM PDT 24
Finished Jul 01 12:57:21 PM PDT 24
Peak memory 199604 kb
Host smart-e6e2bb20-1ab6-463d-bf3e-c035ddd1f9eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305709887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3305709887
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1962579886
Short name T284
Test name
Test status
Simulation time 81315603792 ps
CPU time 197.51 seconds
Started Jul 01 12:40:45 PM PDT 24
Finished Jul 01 12:44:03 PM PDT 24
Peak memory 199944 kb
Host smart-31a9b244-a7c8-4856-8dd5-b556d4327a47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1962579886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1962579886
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1995912059
Short name T796
Test name
Test status
Simulation time 3427893107 ps
CPU time 6.65 seconds
Started Jul 01 12:40:43 PM PDT 24
Finished Jul 01 12:40:50 PM PDT 24
Peak memory 199908 kb
Host smart-631c12a6-92ce-4fda-811d-076dfdf57195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995912059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1995912059
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.3063257661
Short name T807
Test name
Test status
Simulation time 12897815421 ps
CPU time 724.9 seconds
Started Jul 01 12:40:43 PM PDT 24
Finished Jul 01 12:52:48 PM PDT 24
Peak memory 199940 kb
Host smart-296802f4-c1c6-47c1-ad5b-6be2ec977ac2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063257661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3063257661
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1411553372
Short name T524
Test name
Test status
Simulation time 6823164863 ps
CPU time 63.88 seconds
Started Jul 01 12:40:39 PM PDT 24
Finished Jul 01 12:41:44 PM PDT 24
Peak memory 198984 kb
Host smart-7aadf5ad-72e6-45d4-93b1-3ff713e5bf7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411553372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1411553372
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3651481940
Short name T647
Test name
Test status
Simulation time 17455032591 ps
CPU time 25.04 seconds
Started Jul 01 12:40:45 PM PDT 24
Finished Jul 01 12:41:11 PM PDT 24
Peak memory 200008 kb
Host smart-3d3c95ae-e90e-48c9-9559-6aadccfdaeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651481940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3651481940
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3119294968
Short name T659
Test name
Test status
Simulation time 38285107326 ps
CPU time 29.03 seconds
Started Jul 01 12:40:40 PM PDT 24
Finished Jul 01 12:41:09 PM PDT 24
Peak memory 195940 kb
Host smart-be4f376e-1842-4e17-8963-18525ca361f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119294968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3119294968
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2259808709
Short name T346
Test name
Test status
Simulation time 840931686 ps
CPU time 3.53 seconds
Started Jul 01 12:40:41 PM PDT 24
Finished Jul 01 12:40:45 PM PDT 24
Peak memory 198916 kb
Host smart-1b8dcd6d-5929-43a0-a456-be85d17a6e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259808709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2259808709
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2412267733
Short name T988
Test name
Test status
Simulation time 30274903648 ps
CPU time 34.35 seconds
Started Jul 01 12:40:43 PM PDT 24
Finished Jul 01 12:41:18 PM PDT 24
Peak memory 199936 kb
Host smart-9f8bd032-774a-4563-801a-436cdc3317bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412267733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2412267733
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2266528198
Short name T961
Test name
Test status
Simulation time 14972894830 ps
CPU time 5.62 seconds
Started Jul 01 12:40:45 PM PDT 24
Finished Jul 01 12:40:51 PM PDT 24
Peak memory 199864 kb
Host smart-1fad9948-4556-4d76-b735-d5d9bd08ca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266528198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2266528198
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.563685927
Short name T922
Test name
Test status
Simulation time 160125445727 ps
CPU time 149.12 seconds
Started Jul 01 12:40:40 PM PDT 24
Finished Jul 01 12:43:10 PM PDT 24
Peak memory 199924 kb
Host smart-c1c30b2d-9b97-44a5-bcca-4eeed4267532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563685927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.563685927
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1474876992
Short name T680
Test name
Test status
Simulation time 40412212 ps
CPU time 0.56 seconds
Started Jul 01 12:40:59 PM PDT 24
Finished Jul 01 12:41:00 PM PDT 24
Peak memory 194440 kb
Host smart-c711083a-0a70-48a9-b035-4d44437b8d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474876992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1474876992
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.4241460663
Short name T730
Test name
Test status
Simulation time 62518133791 ps
CPU time 96.84 seconds
Started Jul 01 12:40:50 PM PDT 24
Finished Jul 01 12:42:27 PM PDT 24
Peak memory 199884 kb
Host smart-c22bcfe2-79cb-45da-a046-4475c13764d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241460663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4241460663
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2259229487
Short name T568
Test name
Test status
Simulation time 99276552893 ps
CPU time 46.93 seconds
Started Jul 01 12:40:55 PM PDT 24
Finished Jul 01 12:41:43 PM PDT 24
Peak memory 199932 kb
Host smart-09cd2ef3-e05d-436c-b6f3-1c99ef5b5283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259229487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2259229487
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.4176374239
Short name T688
Test name
Test status
Simulation time 5063407951 ps
CPU time 9.26 seconds
Started Jul 01 12:40:56 PM PDT 24
Finished Jul 01 12:41:06 PM PDT 24
Peak memory 199908 kb
Host smart-5eba0db3-be35-41f4-9c87-d28338f172b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176374239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4176374239
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3981075259
Short name T587
Test name
Test status
Simulation time 145631444750 ps
CPU time 272.63 seconds
Started Jul 01 12:40:54 PM PDT 24
Finished Jul 01 12:45:27 PM PDT 24
Peak memory 199968 kb
Host smart-79ac1a7e-57df-45d3-a010-7125c2dfd3a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981075259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3981075259
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3969228373
Short name T1070
Test name
Test status
Simulation time 4739963904 ps
CPU time 7.93 seconds
Started Jul 01 12:40:54 PM PDT 24
Finished Jul 01 12:41:03 PM PDT 24
Peak memory 199788 kb
Host smart-8d71a7e1-d883-4fbe-9c21-9fcd870913bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969228373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3969228373
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.1715422610
Short name T727
Test name
Test status
Simulation time 21068263680 ps
CPU time 223.63 seconds
Started Jul 01 12:40:56 PM PDT 24
Finished Jul 01 12:44:41 PM PDT 24
Peak memory 199884 kb
Host smart-c8e09ce6-c67f-40da-a3c2-959c761583c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715422610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1715422610
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1539189679
Short name T979
Test name
Test status
Simulation time 3385338940 ps
CPU time 12.84 seconds
Started Jul 01 12:40:53 PM PDT 24
Finished Jul 01 12:41:06 PM PDT 24
Peak memory 198288 kb
Host smart-cd6018dc-6018-4be5-b7bf-652ed1ee8571
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539189679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1539189679
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3809082000
Short name T797
Test name
Test status
Simulation time 46855802610 ps
CPU time 73.17 seconds
Started Jul 01 12:40:53 PM PDT 24
Finished Jul 01 12:42:06 PM PDT 24
Peak memory 199980 kb
Host smart-93212eb0-64ca-491b-8820-e9d0f5dd83a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809082000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3809082000
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.848083008
Short name T689
Test name
Test status
Simulation time 2397924444 ps
CPU time 2.4 seconds
Started Jul 01 12:40:53 PM PDT 24
Finished Jul 01 12:40:56 PM PDT 24
Peak memory 196420 kb
Host smart-64594dd7-4f93-4947-b9b8-f74b86ca3907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848083008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.848083008
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.86784491
Short name T1032
Test name
Test status
Simulation time 6060852884 ps
CPU time 15.29 seconds
Started Jul 01 12:40:50 PM PDT 24
Finished Jul 01 12:41:06 PM PDT 24
Peak memory 199632 kb
Host smart-d25bc824-c89a-45b1-bf1e-d9eb29043132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86784491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.86784491
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2526093831
Short name T615
Test name
Test status
Simulation time 348686930842 ps
CPU time 1114.18 seconds
Started Jul 01 12:40:59 PM PDT 24
Finished Jul 01 12:59:35 PM PDT 24
Peak memory 224756 kb
Host smart-95754f00-b112-40b2-829e-daef4d00d53e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526093831 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2526093831
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1650926679
Short name T421
Test name
Test status
Simulation time 6236193498 ps
CPU time 32.8 seconds
Started Jul 01 12:40:56 PM PDT 24
Finished Jul 01 12:41:29 PM PDT 24
Peak memory 199824 kb
Host smart-e4af1f07-9e0a-4996-8c26-bbe858dd2e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650926679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1650926679
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2084527229
Short name T372
Test name
Test status
Simulation time 40097370727 ps
CPU time 12.16 seconds
Started Jul 01 12:40:49 PM PDT 24
Finished Jul 01 12:41:02 PM PDT 24
Peak memory 196724 kb
Host smart-adb15bb1-2e78-41e7-801b-c15b19fe2e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084527229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2084527229
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2381736522
Short name T351
Test name
Test status
Simulation time 12244080 ps
CPU time 0.56 seconds
Started Jul 01 12:41:10 PM PDT 24
Finished Jul 01 12:41:13 PM PDT 24
Peak memory 195296 kb
Host smart-de4a792e-0e74-4bda-bb3a-359165b702ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381736522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2381736522
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3023578543
Short name T293
Test name
Test status
Simulation time 30208033650 ps
CPU time 45.57 seconds
Started Jul 01 12:41:02 PM PDT 24
Finished Jul 01 12:41:48 PM PDT 24
Peak memory 199968 kb
Host smart-603d4257-da12-493e-b2e3-c366136d33f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023578543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3023578543
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3857684724
Short name T916
Test name
Test status
Simulation time 219783444220 ps
CPU time 98.8 seconds
Started Jul 01 12:41:07 PM PDT 24
Finished Jul 01 12:42:47 PM PDT 24
Peak memory 199932 kb
Host smart-a3518169-cc86-4efa-a701-a297cec75cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857684724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3857684724
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2693395424
Short name T203
Test name
Test status
Simulation time 25486250109 ps
CPU time 15.68 seconds
Started Jul 01 12:41:07 PM PDT 24
Finished Jul 01 12:41:23 PM PDT 24
Peak memory 200044 kb
Host smart-644db6df-eca2-4c8b-9e48-92428a68854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693395424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2693395424
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2132629638
Short name T308
Test name
Test status
Simulation time 171810797303 ps
CPU time 235.95 seconds
Started Jul 01 12:41:09 PM PDT 24
Finished Jul 01 12:45:06 PM PDT 24
Peak memory 198320 kb
Host smart-6fb10cfd-d8fc-4f8d-8e08-fb5d0c728a1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132629638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2132629638
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3774563853
Short name T642
Test name
Test status
Simulation time 103690115421 ps
CPU time 980.32 seconds
Started Jul 01 12:41:04 PM PDT 24
Finished Jul 01 12:57:25 PM PDT 24
Peak memory 199924 kb
Host smart-dcf5308d-2ca5-459e-8d0a-5dea2530d749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774563853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3774563853
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1333293591
Short name T848
Test name
Test status
Simulation time 7911981170 ps
CPU time 6.48 seconds
Started Jul 01 12:41:05 PM PDT 24
Finished Jul 01 12:41:12 PM PDT 24
Peak memory 199644 kb
Host smart-2b28fd2f-b546-41eb-b0da-89b6f2c4db69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333293591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1333293591
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.2592569773
Short name T605
Test name
Test status
Simulation time 16962200974 ps
CPU time 809.33 seconds
Started Jul 01 12:41:09 PM PDT 24
Finished Jul 01 12:54:40 PM PDT 24
Peak memory 199912 kb
Host smart-bc511b07-211f-499f-b240-d1bf7f81ccf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2592569773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2592569773
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4004285667
Short name T640
Test name
Test status
Simulation time 4548960928 ps
CPU time 10.07 seconds
Started Jul 01 12:41:04 PM PDT 24
Finished Jul 01 12:41:15 PM PDT 24
Peak memory 197852 kb
Host smart-73bf4860-1caf-4daf-a3da-a372c7a619ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004285667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4004285667
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1259208814
Short name T471
Test name
Test status
Simulation time 114327862773 ps
CPU time 180.08 seconds
Started Jul 01 12:41:05 PM PDT 24
Finished Jul 01 12:44:06 PM PDT 24
Peak memory 200000 kb
Host smart-ee13d98d-9f2f-497b-917e-63a463ab8d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259208814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1259208814
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1362852688
Short name T535
Test name
Test status
Simulation time 37202242793 ps
CPU time 53.42 seconds
Started Jul 01 12:41:05 PM PDT 24
Finished Jul 01 12:41:59 PM PDT 24
Peak memory 195748 kb
Host smart-1e40f1f4-80c5-47b6-b59f-87b9dbccce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362852688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1362852688
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1353690941
Short name T800
Test name
Test status
Simulation time 5330981837 ps
CPU time 27.31 seconds
Started Jul 01 12:41:00 PM PDT 24
Finished Jul 01 12:41:28 PM PDT 24
Peak memory 199356 kb
Host smart-9b3065f8-0dfe-44b2-8f87-354376dc84bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353690941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1353690941
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2033992900
Short name T629
Test name
Test status
Simulation time 6480554423 ps
CPU time 24.55 seconds
Started Jul 01 12:41:05 PM PDT 24
Finished Jul 01 12:41:30 PM PDT 24
Peak memory 199316 kb
Host smart-68a4f2be-670a-40ef-b514-10b4177b7444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033992900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2033992900
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.882274741
Short name T305
Test name
Test status
Simulation time 23233693750 ps
CPU time 30.35 seconds
Started Jul 01 12:41:01 PM PDT 24
Finished Jul 01 12:41:32 PM PDT 24
Peak memory 199912 kb
Host smart-22c4b721-ec3c-457c-94a9-f33da850e784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882274741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.882274741
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1803512368
Short name T694
Test name
Test status
Simulation time 14374801 ps
CPU time 0.6 seconds
Started Jul 01 12:41:19 PM PDT 24
Finished Jul 01 12:41:21 PM PDT 24
Peak memory 195296 kb
Host smart-8e737ba2-846d-4ce6-a215-361f945c7014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803512368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1803512368
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1880958787
Short name T161
Test name
Test status
Simulation time 35243468968 ps
CPU time 57.65 seconds
Started Jul 01 12:41:11 PM PDT 24
Finished Jul 01 12:42:10 PM PDT 24
Peak memory 199940 kb
Host smart-d1ae1ed0-73a9-401b-b0bb-702998518ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880958787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1880958787
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2449839498
Short name T361
Test name
Test status
Simulation time 90035522069 ps
CPU time 142.69 seconds
Started Jul 01 12:41:10 PM PDT 24
Finished Jul 01 12:43:34 PM PDT 24
Peak memory 199792 kb
Host smart-af88dab0-85fc-470a-9381-f00fd5024d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449839498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2449839498
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1214947138
Short name T213
Test name
Test status
Simulation time 267366269265 ps
CPU time 112.12 seconds
Started Jul 01 12:41:12 PM PDT 24
Finished Jul 01 12:43:06 PM PDT 24
Peak memory 199936 kb
Host smart-f252592d-304f-4e7d-8d19-c030c4be9842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214947138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1214947138
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1899231154
Short name T486
Test name
Test status
Simulation time 2763376010 ps
CPU time 4.81 seconds
Started Jul 01 12:41:10 PM PDT 24
Finished Jul 01 12:41:17 PM PDT 24
Peak memory 195776 kb
Host smart-12c59cdc-2847-4345-a57d-fb205bf64390
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899231154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1899231154
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2928132238
Short name T565
Test name
Test status
Simulation time 68079071655 ps
CPU time 313.86 seconds
Started Jul 01 12:41:16 PM PDT 24
Finished Jul 01 12:46:32 PM PDT 24
Peak memory 199876 kb
Host smart-b061cb4a-ca39-44a4-8805-1b9178baf176
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928132238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2928132238
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.854280326
Short name T328
Test name
Test status
Simulation time 2648251665 ps
CPU time 4.38 seconds
Started Jul 01 12:41:11 PM PDT 24
Finished Jul 01 12:41:18 PM PDT 24
Peak memory 197196 kb
Host smart-d75ca3bb-0b70-4947-a54a-d33f27cc98f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854280326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.854280326
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.1783622846
Short name T270
Test name
Test status
Simulation time 3097556725 ps
CPU time 31.85 seconds
Started Jul 01 12:41:17 PM PDT 24
Finished Jul 01 12:41:50 PM PDT 24
Peak memory 200000 kb
Host smart-53197be4-b09a-44c1-8506-3e0241a521c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1783622846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1783622846
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3620220799
Short name T1066
Test name
Test status
Simulation time 3394570383 ps
CPU time 6.2 seconds
Started Jul 01 12:41:11 PM PDT 24
Finished Jul 01 12:41:19 PM PDT 24
Peak memory 197820 kb
Host smart-07d28e1b-64eb-42d6-84f8-314f300065c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3620220799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3620220799
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.52851069
Short name T474
Test name
Test status
Simulation time 48219092950 ps
CPU time 50.91 seconds
Started Jul 01 12:41:09 PM PDT 24
Finished Jul 01 12:42:00 PM PDT 24
Peak memory 199976 kb
Host smart-23911f5c-cdf6-4a3c-927a-3b240109a423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52851069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.52851069
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1635232569
Short name T909
Test name
Test status
Simulation time 3337532315 ps
CPU time 1.33 seconds
Started Jul 01 12:41:10 PM PDT 24
Finished Jul 01 12:41:14 PM PDT 24
Peak memory 196184 kb
Host smart-8b873d54-8cb7-4a59-b71e-02962fdc6d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635232569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1635232569
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2663123983
Short name T1051
Test name
Test status
Simulation time 684010236 ps
CPU time 1.53 seconds
Started Jul 01 12:41:11 PM PDT 24
Finished Jul 01 12:41:15 PM PDT 24
Peak memory 199868 kb
Host smart-e9bc8430-ad74-4487-8b99-e6d00fb04b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663123983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2663123983
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2997576250
Short name T1074
Test name
Test status
Simulation time 81255425105 ps
CPU time 974.2 seconds
Started Jul 01 12:41:16 PM PDT 24
Finished Jul 01 12:57:33 PM PDT 24
Peak memory 216420 kb
Host smart-e8197680-657d-4a8c-96e7-ea8af389b083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997576250 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2997576250
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.4056102832
Short name T636
Test name
Test status
Simulation time 6242464113 ps
CPU time 12.08 seconds
Started Jul 01 12:41:10 PM PDT 24
Finished Jul 01 12:41:24 PM PDT 24
Peak memory 199712 kb
Host smart-4c606797-672d-451e-887d-087651c778c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056102832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.4056102832
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3141141900
Short name T871
Test name
Test status
Simulation time 85564239667 ps
CPU time 14.7 seconds
Started Jul 01 12:41:10 PM PDT 24
Finished Jul 01 12:41:27 PM PDT 24
Peak memory 200020 kb
Host smart-8cc88da6-78da-4121-ab22-49018ffa1274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141141900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3141141900
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.831063252
Short name T32
Test name
Test status
Simulation time 15198915 ps
CPU time 0.55 seconds
Started Jul 01 12:35:44 PM PDT 24
Finished Jul 01 12:35:45 PM PDT 24
Peak memory 194152 kb
Host smart-39c928ee-df7f-418b-ae6a-8694ddf2bd16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831063252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.831063252
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.750627455
Short name T341
Test name
Test status
Simulation time 21546884922 ps
CPU time 30.97 seconds
Started Jul 01 12:35:40 PM PDT 24
Finished Jul 01 12:36:11 PM PDT 24
Peak memory 199976 kb
Host smart-f6e7ceab-b406-4ec6-8cee-e7f51c23089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750627455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.750627455
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3938199780
Short name T877
Test name
Test status
Simulation time 63617091613 ps
CPU time 12.81 seconds
Started Jul 01 12:35:39 PM PDT 24
Finished Jul 01 12:35:52 PM PDT 24
Peak memory 199868 kb
Host smart-4cbf514d-e758-4b2b-a57a-1c0a83bba130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938199780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3938199780
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1312452472
Short name T693
Test name
Test status
Simulation time 106903248602 ps
CPU time 37.07 seconds
Started Jul 01 12:35:43 PM PDT 24
Finished Jul 01 12:36:20 PM PDT 24
Peak memory 200056 kb
Host smart-50b584a0-a54e-4942-bbd1-92d09320747d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312452472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1312452472
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.577535461
Short name T715
Test name
Test status
Simulation time 142936231216 ps
CPU time 189.04 seconds
Started Jul 01 12:35:44 PM PDT 24
Finished Jul 01 12:38:53 PM PDT 24
Peak memory 199932 kb
Host smart-86eb3063-9218-4aa7-b84b-6e5b3e4f18ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577535461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.577535461
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2184183125
Short name T820
Test name
Test status
Simulation time 112737908426 ps
CPU time 456.1 seconds
Started Jul 01 12:35:46 PM PDT 24
Finished Jul 01 12:43:23 PM PDT 24
Peak memory 199944 kb
Host smart-3c2214f4-09d2-4a2f-8854-c728c6d78fe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184183125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2184183125
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3524503067
Short name T8
Test name
Test status
Simulation time 2537974517 ps
CPU time 4.54 seconds
Started Jul 01 12:35:43 PM PDT 24
Finished Jul 01 12:35:49 PM PDT 24
Peak memory 198764 kb
Host smart-0950811e-70a3-450e-8ab5-16525b76b375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524503067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3524503067
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.1659918552
Short name T371
Test name
Test status
Simulation time 16026044361 ps
CPU time 383.13 seconds
Started Jul 01 12:35:45 PM PDT 24
Finished Jul 01 12:42:09 PM PDT 24
Peak memory 199952 kb
Host smart-0a767b06-bd29-4fee-ad0d-0246fc07314e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659918552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1659918552
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2281086355
Short name T499
Test name
Test status
Simulation time 7158304073 ps
CPU time 67.83 seconds
Started Jul 01 12:35:41 PM PDT 24
Finished Jul 01 12:36:49 PM PDT 24
Peak memory 198128 kb
Host smart-6579cd06-a91e-4872-aea6-a1ded881cdfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281086355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2281086355
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3796780067
Short name T362
Test name
Test status
Simulation time 46388254569 ps
CPU time 73.2 seconds
Started Jul 01 12:35:45 PM PDT 24
Finished Jul 01 12:36:58 PM PDT 24
Peak memory 199996 kb
Host smart-6ebaad70-5e1e-444c-82ef-369a483daf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796780067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3796780067
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1858787562
Short name T334
Test name
Test status
Simulation time 1433984330 ps
CPU time 1.23 seconds
Started Jul 01 12:35:46 PM PDT 24
Finished Jul 01 12:35:47 PM PDT 24
Peak memory 195408 kb
Host smart-f681f736-aeb5-49bc-8510-c7fa3ea31f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858787562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1858787562
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.158760691
Short name T35
Test name
Test status
Simulation time 186465352 ps
CPU time 0.79 seconds
Started Jul 01 12:35:45 PM PDT 24
Finished Jul 01 12:35:46 PM PDT 24
Peak memory 218416 kb
Host smart-91c7cd26-1fa9-47f0-9810-828571391554
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158760691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.158760691
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2395362218
Short name T366
Test name
Test status
Simulation time 461212884 ps
CPU time 1.14 seconds
Started Jul 01 12:35:39 PM PDT 24
Finished Jul 01 12:35:41 PM PDT 24
Peak memory 198484 kb
Host smart-ffcd6706-d7fb-4578-a4e3-ed2847a837e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395362218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2395362218
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3760810577
Short name T651
Test name
Test status
Simulation time 7351448261 ps
CPU time 9.8 seconds
Started Jul 01 12:35:46 PM PDT 24
Finished Jul 01 12:35:56 PM PDT 24
Peak memory 199932 kb
Host smart-fc8d5a2c-6f7d-43ae-be7c-0427ceb28949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760810577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3760810577
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.986279246
Short name T1080
Test name
Test status
Simulation time 40353551000 ps
CPU time 6.9 seconds
Started Jul 01 12:35:44 PM PDT 24
Finished Jul 01 12:35:51 PM PDT 24
Peak memory 199968 kb
Host smart-68a19363-0636-4add-bf32-625a773682bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986279246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.986279246
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1140619972
Short name T367
Test name
Test status
Simulation time 198596574 ps
CPU time 0.54 seconds
Started Jul 01 12:41:19 PM PDT 24
Finished Jul 01 12:41:21 PM PDT 24
Peak memory 195212 kb
Host smart-a2eac578-50bc-4ee3-b5f6-f936231153ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140619972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1140619972
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.878942398
Short name T258
Test name
Test status
Simulation time 58606551959 ps
CPU time 270.71 seconds
Started Jul 01 12:41:18 PM PDT 24
Finished Jul 01 12:45:50 PM PDT 24
Peak memory 199984 kb
Host smart-2b1aacea-88f2-43cf-a0fa-e2b5381bf0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878942398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.878942398
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2003114660
Short name T170
Test name
Test status
Simulation time 110200733556 ps
CPU time 60.73 seconds
Started Jul 01 12:41:19 PM PDT 24
Finished Jul 01 12:42:21 PM PDT 24
Peak memory 199912 kb
Host smart-2935d3d2-828d-463b-bf5f-8eb7c077d054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003114660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2003114660
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.25483689
Short name T468
Test name
Test status
Simulation time 117819332569 ps
CPU time 17.14 seconds
Started Jul 01 12:41:15 PM PDT 24
Finished Jul 01 12:41:34 PM PDT 24
Peak memory 199908 kb
Host smart-6ed206eb-5dba-43da-90f5-7b94eddf7859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25483689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.25483689
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1627016921
Short name T765
Test name
Test status
Simulation time 31886902563 ps
CPU time 16.13 seconds
Started Jul 01 12:41:19 PM PDT 24
Finished Jul 01 12:41:37 PM PDT 24
Peak memory 199980 kb
Host smart-c2b744fa-7a21-469f-8617-7b7a21c1058e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627016921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1627016921
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3427135203
Short name T600
Test name
Test status
Simulation time 130257234410 ps
CPU time 450.37 seconds
Started Jul 01 12:41:22 PM PDT 24
Finished Jul 01 12:48:54 PM PDT 24
Peak memory 199948 kb
Host smart-1a56e487-790c-4b66-b8c7-913eeb0a47eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3427135203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3427135203
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2554463144
Short name T490
Test name
Test status
Simulation time 6709823247 ps
CPU time 13.46 seconds
Started Jul 01 12:41:20 PM PDT 24
Finished Jul 01 12:41:36 PM PDT 24
Peak memory 199708 kb
Host smart-002f1021-75f4-4103-b3a3-53c554c21e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554463144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2554463144
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.562183616
Short name T966
Test name
Test status
Simulation time 7497070145 ps
CPU time 433.04 seconds
Started Jul 01 12:41:22 PM PDT 24
Finished Jul 01 12:48:36 PM PDT 24
Peak memory 199884 kb
Host smart-a67f5e65-1340-41df-b95a-acfb29135123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562183616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.562183616
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1719234051
Short name T1020
Test name
Test status
Simulation time 6902645997 ps
CPU time 60.55 seconds
Started Jul 01 12:41:20 PM PDT 24
Finished Jul 01 12:42:22 PM PDT 24
Peak memory 199172 kb
Host smart-c0e3ad9d-a6a9-40ca-b751-b7e46bc6d9db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719234051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1719234051
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3858925419
Short name T317
Test name
Test status
Simulation time 56027439025 ps
CPU time 40.15 seconds
Started Jul 01 12:41:20 PM PDT 24
Finished Jul 01 12:42:02 PM PDT 24
Peak memory 199968 kb
Host smart-cdffec6c-2884-4e03-950c-d19d005f0423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858925419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3858925419
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.20069299
Short name T616
Test name
Test status
Simulation time 56941440615 ps
CPU time 22.11 seconds
Started Jul 01 12:41:21 PM PDT 24
Finished Jul 01 12:41:45 PM PDT 24
Peak memory 196232 kb
Host smart-e787d86e-c49a-498c-93c9-773e2c836892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20069299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.20069299
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.4091984228
Short name T294
Test name
Test status
Simulation time 487871124 ps
CPU time 1.59 seconds
Started Jul 01 12:41:14 PM PDT 24
Finished Jul 01 12:41:18 PM PDT 24
Peak memory 198228 kb
Host smart-c606c061-8309-46aa-a5a7-eabda8336abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091984228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.4091984228
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3267091149
Short name T552
Test name
Test status
Simulation time 174853039581 ps
CPU time 37.59 seconds
Started Jul 01 12:41:20 PM PDT 24
Finished Jul 01 12:41:59 PM PDT 24
Peak memory 199904 kb
Host smart-ea5c9f41-f6cd-4f6b-b136-0107c8e65c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267091149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3267091149
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3550748752
Short name T402
Test name
Test status
Simulation time 4476909235 ps
CPU time 1.79 seconds
Started Jul 01 12:41:20 PM PDT 24
Finished Jul 01 12:41:23 PM PDT 24
Peak memory 198420 kb
Host smart-e6731642-924e-4444-a322-5046eedd8e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550748752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3550748752
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4196815913
Short name T885
Test name
Test status
Simulation time 65069823618 ps
CPU time 74.13 seconds
Started Jul 01 12:41:15 PM PDT 24
Finished Jul 01 12:42:31 PM PDT 24
Peak memory 200040 kb
Host smart-449110e4-9d47-4e31-ada2-287519613016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196815913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4196815913
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3361169142
Short name T683
Test name
Test status
Simulation time 20537569 ps
CPU time 0.58 seconds
Started Jul 01 12:41:29 PM PDT 24
Finished Jul 01 12:41:30 PM PDT 24
Peak memory 195308 kb
Host smart-338df4f3-17b0-4a7a-9246-1bb9f42b04da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361169142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3361169142
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1625311721
Short name T675
Test name
Test status
Simulation time 152440262981 ps
CPU time 95.09 seconds
Started Jul 01 12:41:25 PM PDT 24
Finished Jul 01 12:43:01 PM PDT 24
Peak memory 199992 kb
Host smart-0b1d34ae-d1f1-4dea-b123-01f060394015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625311721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1625311721
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3565703904
Short name T626
Test name
Test status
Simulation time 69748775087 ps
CPU time 28.66 seconds
Started Jul 01 12:41:25 PM PDT 24
Finished Jul 01 12:41:55 PM PDT 24
Peak memory 199944 kb
Host smart-dc39e8e0-9ef6-46e7-874e-67bf8b99e1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565703904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3565703904
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1564112400
Short name T1048
Test name
Test status
Simulation time 23849555276 ps
CPU time 36.58 seconds
Started Jul 01 12:41:25 PM PDT 24
Finished Jul 01 12:42:03 PM PDT 24
Peak memory 199972 kb
Host smart-d3d60822-ffce-43db-a6dc-2904f31e14e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564112400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1564112400
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.603238973
Short name T282
Test name
Test status
Simulation time 29561578772 ps
CPU time 8.84 seconds
Started Jul 01 12:41:25 PM PDT 24
Finished Jul 01 12:41:34 PM PDT 24
Peak memory 200004 kb
Host smart-badac16d-1e91-4d05-944e-8169896e8fa4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603238973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.603238973
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1222821354
Short name T449
Test name
Test status
Simulation time 106468895889 ps
CPU time 255.45 seconds
Started Jul 01 12:41:31 PM PDT 24
Finished Jul 01 12:45:47 PM PDT 24
Peak memory 199928 kb
Host smart-dccb4c9e-5175-43a5-887a-6d6519933874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222821354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1222821354
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3884393812
Short name T350
Test name
Test status
Simulation time 7913943950 ps
CPU time 4.52 seconds
Started Jul 01 12:41:31 PM PDT 24
Finished Jul 01 12:41:36 PM PDT 24
Peak memory 199760 kb
Host smart-cb0d2560-a593-4b07-a00e-c1ac75c7b835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884393812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3884393812
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.1088943777
Short name T428
Test name
Test status
Simulation time 14361769804 ps
CPU time 364.71 seconds
Started Jul 01 12:41:31 PM PDT 24
Finished Jul 01 12:47:36 PM PDT 24
Peak memory 199944 kb
Host smart-3c926ccf-52ac-475d-9c21-2859c3c137a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088943777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1088943777
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2640877884
Short name T705
Test name
Test status
Simulation time 6607939422 ps
CPU time 26.51 seconds
Started Jul 01 12:41:25 PM PDT 24
Finished Jul 01 12:41:52 PM PDT 24
Peak memory 199316 kb
Host smart-49b9e58e-d6b1-4c49-83b1-a9bc8c2c4cb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640877884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2640877884
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3311607277
Short name T1043
Test name
Test status
Simulation time 18086217370 ps
CPU time 21.12 seconds
Started Jul 01 12:41:30 PM PDT 24
Finished Jul 01 12:41:52 PM PDT 24
Peak memory 199972 kb
Host smart-8944a317-9b08-41b1-ba3b-baa684f77c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311607277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3311607277
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1993429620
Short name T280
Test name
Test status
Simulation time 3270075731 ps
CPU time 3.31 seconds
Started Jul 01 12:41:26 PM PDT 24
Finished Jul 01 12:41:30 PM PDT 24
Peak memory 196052 kb
Host smart-da0834e2-53cd-42f2-908c-c7e26dd115be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993429620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1993429620
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.78611954
Short name T1068
Test name
Test status
Simulation time 481834651 ps
CPU time 1.3 seconds
Started Jul 01 12:41:21 PM PDT 24
Finished Jul 01 12:41:24 PM PDT 24
Peak memory 198300 kb
Host smart-6f8738d2-8e2b-4818-b563-62755701da64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78611954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.78611954
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1750735599
Short name T118
Test name
Test status
Simulation time 151261445845 ps
CPU time 357.69 seconds
Started Jul 01 12:41:30 PM PDT 24
Finished Jul 01 12:47:29 PM PDT 24
Peak memory 199972 kb
Host smart-419f7ff1-c071-42d7-a9f6-d69bbf9302e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750735599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1750735599
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.733840191
Short name T453
Test name
Test status
Simulation time 918538114 ps
CPU time 1.9 seconds
Started Jul 01 12:41:30 PM PDT 24
Finished Jul 01 12:41:32 PM PDT 24
Peak memory 198312 kb
Host smart-e8c2f491-6fc7-4aeb-b440-3e1c633d0ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733840191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.733840191
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3187713130
Short name T732
Test name
Test status
Simulation time 15214130012 ps
CPU time 23.32 seconds
Started Jul 01 12:41:20 PM PDT 24
Finished Jul 01 12:41:45 PM PDT 24
Peak memory 199940 kb
Host smart-976760fa-8b00-4b84-9924-f2db1a65f52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187713130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3187713130
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3274257690
Short name T583
Test name
Test status
Simulation time 40086409 ps
CPU time 0.55 seconds
Started Jul 01 12:41:45 PM PDT 24
Finished Jul 01 12:41:46 PM PDT 24
Peak memory 195324 kb
Host smart-94597c8f-850a-49ca-8530-5382ed3c265a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274257690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3274257690
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1589584861
Short name T547
Test name
Test status
Simulation time 105514546156 ps
CPU time 14.3 seconds
Started Jul 01 12:41:34 PM PDT 24
Finished Jul 01 12:41:49 PM PDT 24
Peak memory 199852 kb
Host smart-3d7033a7-9a62-45cd-9b98-acce2bae1931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589584861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1589584861
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.464174100
Short name T712
Test name
Test status
Simulation time 35151926216 ps
CPU time 44.47 seconds
Started Jul 01 12:41:34 PM PDT 24
Finished Jul 01 12:42:19 PM PDT 24
Peak memory 199948 kb
Host smart-43964064-face-4e3d-a70d-5097fa7736b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464174100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.464174100
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_intr.413534926
Short name T986
Test name
Test status
Simulation time 32314350838 ps
CPU time 16.33 seconds
Started Jul 01 12:41:37 PM PDT 24
Finished Jul 01 12:41:54 PM PDT 24
Peak memory 199880 kb
Host smart-6be7374d-7f83-4180-b602-c50f22467c78
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413534926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.413534926
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3173967908
Short name T254
Test name
Test status
Simulation time 282397820252 ps
CPU time 388.91 seconds
Started Jul 01 12:41:42 PM PDT 24
Finished Jul 01 12:48:11 PM PDT 24
Peak memory 199976 kb
Host smart-25d0768c-6dc8-4d5d-9549-713b565393f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3173967908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3173967908
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3602987119
Short name T1060
Test name
Test status
Simulation time 11984202600 ps
CPU time 13.51 seconds
Started Jul 01 12:41:39 PM PDT 24
Finished Jul 01 12:41:53 PM PDT 24
Peak memory 198724 kb
Host smart-d953a594-a992-42cd-86c5-3752253a7c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602987119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3602987119
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.3949766215
Short name T929
Test name
Test status
Simulation time 14879636119 ps
CPU time 824.52 seconds
Started Jul 01 12:41:40 PM PDT 24
Finished Jul 01 12:55:25 PM PDT 24
Peak memory 199988 kb
Host smart-e92c6e37-b020-40ac-9f05-b6de67095f3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949766215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3949766215
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1934626774
Short name T19
Test name
Test status
Simulation time 6535320447 ps
CPU time 60.29 seconds
Started Jul 01 12:41:34 PM PDT 24
Finished Jul 01 12:42:35 PM PDT 24
Peak memory 198232 kb
Host smart-21a3b36e-8da8-465d-99e8-52a1a7ee8f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1934626774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1934626774
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.304284602
Short name T445
Test name
Test status
Simulation time 193838858783 ps
CPU time 340 seconds
Started Jul 01 12:41:42 PM PDT 24
Finished Jul 01 12:47:23 PM PDT 24
Peak memory 199976 kb
Host smart-bb6bc6f6-5012-4437-a416-3b9cf9e3db32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304284602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.304284602
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3848452661
Short name T44
Test name
Test status
Simulation time 7125653701 ps
CPU time 1.97 seconds
Started Jul 01 12:41:36 PM PDT 24
Finished Jul 01 12:41:39 PM PDT 24
Peak memory 196164 kb
Host smart-25f42f39-e7f7-432f-994d-d71897ba177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848452661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3848452661
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3349445481
Short name T296
Test name
Test status
Simulation time 915635740 ps
CPU time 1.16 seconds
Started Jul 01 12:41:35 PM PDT 24
Finished Jul 01 12:41:36 PM PDT 24
Peak memory 198576 kb
Host smart-df03500c-a744-435f-ac14-d17bc8583337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349445481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3349445481
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3918540992
Short name T774
Test name
Test status
Simulation time 345984272536 ps
CPU time 149.37 seconds
Started Jul 01 12:41:44 PM PDT 24
Finished Jul 01 12:44:14 PM PDT 24
Peak memory 199876 kb
Host smart-f24e1030-ad93-447c-91d4-c2fa04b8b43c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918540992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3918540992
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3643350803
Short name T283
Test name
Test status
Simulation time 353912767968 ps
CPU time 830.08 seconds
Started Jul 01 12:41:45 PM PDT 24
Finished Jul 01 12:55:36 PM PDT 24
Peak memory 216456 kb
Host smart-b63bac1b-d1f4-4f7d-be63-621aa6cc9a72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643350803 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3643350803
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1975026515
Short name T1059
Test name
Test status
Simulation time 1128613244 ps
CPU time 2.19 seconds
Started Jul 01 12:41:40 PM PDT 24
Finished Jul 01 12:41:42 PM PDT 24
Peak memory 199756 kb
Host smart-1b95acd2-01e7-4e67-96b6-425f4140e1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975026515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1975026515
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2749325088
Short name T447
Test name
Test status
Simulation time 157173400640 ps
CPU time 80.11 seconds
Started Jul 01 12:41:37 PM PDT 24
Finished Jul 01 12:42:57 PM PDT 24
Peak memory 199984 kb
Host smart-563db05b-413e-4eee-a611-63e6acfe1ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749325088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2749325088
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2963241483
Short name T874
Test name
Test status
Simulation time 13794459 ps
CPU time 0.62 seconds
Started Jul 01 12:41:55 PM PDT 24
Finished Jul 01 12:41:57 PM PDT 24
Peak memory 195304 kb
Host smart-19afa505-3a2a-4f03-ade1-2c2776562113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963241483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2963241483
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1083048591
Short name T872
Test name
Test status
Simulation time 47855693115 ps
CPU time 34.85 seconds
Started Jul 01 12:41:47 PM PDT 24
Finished Jul 01 12:42:22 PM PDT 24
Peak memory 200024 kb
Host smart-e8a00921-aa7c-49c5-a786-0aec7696a85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083048591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1083048591
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.554222001
Short name T126
Test name
Test status
Simulation time 24647316546 ps
CPU time 12.03 seconds
Started Jul 01 12:41:49 PM PDT 24
Finished Jul 01 12:42:03 PM PDT 24
Peak memory 199752 kb
Host smart-585fd8e2-ff7d-44ee-a257-c78e340f2bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554222001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.554222001
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1414065288
Short name T551
Test name
Test status
Simulation time 20735159656 ps
CPU time 9.73 seconds
Started Jul 01 12:41:51 PM PDT 24
Finished Jul 01 12:42:02 PM PDT 24
Peak memory 199944 kb
Host smart-dbe9e4c0-2b02-4a20-bc69-6db82efcd438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414065288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1414065288
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.831496606
Short name T528
Test name
Test status
Simulation time 303622806577 ps
CPU time 93.29 seconds
Started Jul 01 12:41:50 PM PDT 24
Finished Jul 01 12:43:25 PM PDT 24
Peak memory 198760 kb
Host smart-74c057bf-6d16-476b-9eda-3bb18b92bb2a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831496606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.831496606
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3691832470
Short name T257
Test name
Test status
Simulation time 86582060495 ps
CPU time 470.47 seconds
Started Jul 01 12:41:56 PM PDT 24
Finished Jul 01 12:49:47 PM PDT 24
Peak memory 199916 kb
Host smart-94ade8b6-cbdd-440d-8282-933ac9829d33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691832470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3691832470
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1056328445
Short name T697
Test name
Test status
Simulation time 5164413605 ps
CPU time 4.72 seconds
Started Jul 01 12:41:55 PM PDT 24
Finished Jul 01 12:42:01 PM PDT 24
Peak memory 199576 kb
Host smart-eb5d9327-a9ef-4c3c-91e4-f4a2acd9b076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056328445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1056328445
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1117138773
Short name T650
Test name
Test status
Simulation time 5627297078 ps
CPU time 4.15 seconds
Started Jul 01 12:41:49 PM PDT 24
Finished Jul 01 12:41:55 PM PDT 24
Peak memory 199780 kb
Host smart-1d81a318-2c44-4f75-8f03-a45fc3ce1dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117138773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1117138773
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1041594936
Short name T479
Test name
Test status
Simulation time 5463077708 ps
CPU time 229.94 seconds
Started Jul 01 12:41:58 PM PDT 24
Finished Jul 01 12:45:48 PM PDT 24
Peak memory 199996 kb
Host smart-7358f85a-da8d-4e9c-b019-b95b9c40d448
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1041594936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1041594936
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2778063204
Short name T18
Test name
Test status
Simulation time 5906009946 ps
CPU time 47.01 seconds
Started Jul 01 12:41:51 PM PDT 24
Finished Jul 01 12:42:39 PM PDT 24
Peak memory 199348 kb
Host smart-d105bc90-0f9f-4fae-8dad-07d78b5c5d06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2778063204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2778063204
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1108475336
Short name T476
Test name
Test status
Simulation time 33765981976 ps
CPU time 53.5 seconds
Started Jul 01 12:41:51 PM PDT 24
Finished Jul 01 12:42:45 PM PDT 24
Peak memory 199836 kb
Host smart-3254aa23-232c-4e4b-9c0f-4dc343ecc7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108475336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1108475336
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1784156890
Short name T792
Test name
Test status
Simulation time 3837264344 ps
CPU time 1.99 seconds
Started Jul 01 12:41:50 PM PDT 24
Finished Jul 01 12:41:53 PM PDT 24
Peak memory 196428 kb
Host smart-0d7ccc20-fda4-483e-8cb5-29ba5aade8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784156890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1784156890
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.4029044745
Short name T492
Test name
Test status
Simulation time 11098384001 ps
CPU time 36.81 seconds
Started Jul 01 12:41:47 PM PDT 24
Finished Jul 01 12:42:24 PM PDT 24
Peak memory 199804 kb
Host smart-47fe9f91-fb91-46ae-b438-aad9b10af63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029044745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.4029044745
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1640150680
Short name T117
Test name
Test status
Simulation time 39492031201 ps
CPU time 32.8 seconds
Started Jul 01 12:41:55 PM PDT 24
Finished Jul 01 12:42:29 PM PDT 24
Peak memory 199960 kb
Host smart-3d029b94-c373-42c8-8504-57732977c9c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640150680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1640150680
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2875726684
Short name T708
Test name
Test status
Simulation time 1029818732 ps
CPU time 2.45 seconds
Started Jul 01 12:41:49 PM PDT 24
Finished Jul 01 12:41:54 PM PDT 24
Peak memory 199536 kb
Host smart-b4b4ae1d-6f0f-4992-820c-a05e7dc5ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875726684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2875726684
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.822707585
Short name T111
Test name
Test status
Simulation time 40116040450 ps
CPU time 28 seconds
Started Jul 01 12:41:45 PM PDT 24
Finished Jul 01 12:42:14 PM PDT 24
Peak memory 199920 kb
Host smart-da486614-eb01-418b-9fe3-446bb450b148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822707585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.822707585
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1992138175
Short name T393
Test name
Test status
Simulation time 128321970 ps
CPU time 0.56 seconds
Started Jul 01 12:42:09 PM PDT 24
Finished Jul 01 12:42:11 PM PDT 24
Peak memory 195308 kb
Host smart-34ecbd95-0162-4ffa-bf51-78db153811b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992138175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1992138175
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2970537512
Short name T995
Test name
Test status
Simulation time 34780973315 ps
CPU time 49.15 seconds
Started Jul 01 12:41:54 PM PDT 24
Finished Jul 01 12:42:44 PM PDT 24
Peak memory 200016 kb
Host smart-e6595bda-843b-4b73-9c56-9231379d9f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970537512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2970537512
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.819055196
Short name T843
Test name
Test status
Simulation time 7282704840 ps
CPU time 11.66 seconds
Started Jul 01 12:41:56 PM PDT 24
Finished Jul 01 12:42:08 PM PDT 24
Peak memory 199988 kb
Host smart-9c2cf624-9517-4920-b579-ecfce174b8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819055196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.819055196
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.1791172061
Short name T669
Test name
Test status
Simulation time 6448075167 ps
CPU time 8.45 seconds
Started Jul 01 12:42:00 PM PDT 24
Finished Jul 01 12:42:09 PM PDT 24
Peak memory 199832 kb
Host smart-1ed6dcb2-353a-40fc-b765-a062294a222c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791172061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1791172061
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4263518491
Short name T847
Test name
Test status
Simulation time 73823481672 ps
CPU time 229.02 seconds
Started Jul 01 12:41:59 PM PDT 24
Finished Jul 01 12:45:50 PM PDT 24
Peak memory 199920 kb
Host smart-4924a919-6d0d-4b14-a7f2-af79371314aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263518491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4263518491
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3476108727
Short name T340
Test name
Test status
Simulation time 7299469328 ps
CPU time 4.78 seconds
Started Jul 01 12:42:00 PM PDT 24
Finished Jul 01 12:42:06 PM PDT 24
Peak memory 199060 kb
Host smart-b9713eb4-fb1e-487d-a360-19ec32954385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476108727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3476108727
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.1041238481
Short name T51
Test name
Test status
Simulation time 8162811352 ps
CPU time 383.7 seconds
Started Jul 01 12:41:59 PM PDT 24
Finished Jul 01 12:48:24 PM PDT 24
Peak memory 199920 kb
Host smart-c156bf42-0582-4536-a69a-889494374aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1041238481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1041238481
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3388619542
Short name T766
Test name
Test status
Simulation time 1483177906 ps
CPU time 5.68 seconds
Started Jul 01 12:42:00 PM PDT 24
Finished Jul 01 12:42:07 PM PDT 24
Peak memory 199216 kb
Host smart-ecfb1547-b916-4d38-b413-adfb18c69128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388619542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3388619542
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.4208463518
Short name T924
Test name
Test status
Simulation time 23308117133 ps
CPU time 24.23 seconds
Started Jul 01 12:41:59 PM PDT 24
Finished Jul 01 12:42:24 PM PDT 24
Peak memory 199804 kb
Host smart-9693d62b-3bf8-42ac-b52e-9e066adc0d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208463518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.4208463518
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1349709123
Short name T808
Test name
Test status
Simulation time 3395892336 ps
CPU time 5.98 seconds
Started Jul 01 12:41:59 PM PDT 24
Finished Jul 01 12:42:06 PM PDT 24
Peak memory 195764 kb
Host smart-203ca6a4-26af-4b0e-852c-7b2893c68b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349709123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1349709123
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1165720501
Short name T7
Test name
Test status
Simulation time 5355909685 ps
CPU time 15.1 seconds
Started Jul 01 12:41:58 PM PDT 24
Finished Jul 01 12:42:14 PM PDT 24
Peak memory 199808 kb
Host smart-553cf8ed-a001-4b96-9c02-e4914fa1a3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165720501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1165720501
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3817675353
Short name T861
Test name
Test status
Simulation time 225334880300 ps
CPU time 461.32 seconds
Started Jul 01 12:42:05 PM PDT 24
Finished Jul 01 12:49:47 PM PDT 24
Peak memory 199960 kb
Host smart-136943e9-fd54-467e-99b4-a310d7cadb15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817675353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3817675353
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.445641320
Short name T208
Test name
Test status
Simulation time 36032943868 ps
CPU time 248.59 seconds
Started Jul 01 12:42:06 PM PDT 24
Finished Jul 01 12:46:15 PM PDT 24
Peak memory 216640 kb
Host smart-a7384ac6-8363-4eee-8b17-6421fb03e403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445641320 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.445641320
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1393444202
Short name T817
Test name
Test status
Simulation time 1450698792 ps
CPU time 1.62 seconds
Started Jul 01 12:42:01 PM PDT 24
Finished Jul 01 12:42:04 PM PDT 24
Peak memory 198216 kb
Host smart-f6ebb123-2acb-4ca8-887d-730630ad58b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393444202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1393444202
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.4234775106
Short name T818
Test name
Test status
Simulation time 46756080441 ps
CPU time 121.8 seconds
Started Jul 01 12:41:57 PM PDT 24
Finished Jul 01 12:43:59 PM PDT 24
Peak memory 199956 kb
Host smart-6dc0ea87-0b16-46ee-a668-4e153504ba83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234775106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4234775106
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3196078274
Short name T1053
Test name
Test status
Simulation time 13706405 ps
CPU time 0.55 seconds
Started Jul 01 12:42:10 PM PDT 24
Finished Jul 01 12:42:12 PM PDT 24
Peak memory 195268 kb
Host smart-1377bf09-4023-4467-b5ff-a3a0d52db53a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196078274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3196078274
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1089892210
Short name T472
Test name
Test status
Simulation time 119554442738 ps
CPU time 127.39 seconds
Started Jul 01 12:42:08 PM PDT 24
Finished Jul 01 12:44:15 PM PDT 24
Peak memory 199984 kb
Host smart-20f57a71-372f-40ea-87e9-3f8d5c755141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089892210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1089892210
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1927448626
Short name T608
Test name
Test status
Simulation time 180502919885 ps
CPU time 42.1 seconds
Started Jul 01 12:42:06 PM PDT 24
Finished Jul 01 12:42:49 PM PDT 24
Peak memory 199996 kb
Host smart-7142d48c-b39c-457a-84a7-48993611858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927448626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1927448626
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.562516306
Short name T816
Test name
Test status
Simulation time 23174763725 ps
CPU time 16.7 seconds
Started Jul 01 12:42:05 PM PDT 24
Finished Jul 01 12:42:23 PM PDT 24
Peak memory 199916 kb
Host smart-2e0639a8-dfba-458b-9682-6eb51983afc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562516306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.562516306
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.915998401
Short name T970
Test name
Test status
Simulation time 21186081462 ps
CPU time 26.96 seconds
Started Jul 01 12:42:07 PM PDT 24
Finished Jul 01 12:42:34 PM PDT 24
Peak memory 198000 kb
Host smart-1a1d2e99-ecc6-40a0-870d-ac141cceb5af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915998401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.915998401
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3794282796
Short name T762
Test name
Test status
Simulation time 136293576701 ps
CPU time 993.92 seconds
Started Jul 01 12:42:09 PM PDT 24
Finished Jul 01 12:58:44 PM PDT 24
Peak memory 199968 kb
Host smart-ca7e56da-6a6e-479d-92b2-c739eab42a2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794282796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3794282796
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3689086448
Short name T897
Test name
Test status
Simulation time 10080325690 ps
CPU time 4.97 seconds
Started Jul 01 12:42:10 PM PDT 24
Finished Jul 01 12:42:16 PM PDT 24
Peak memory 199528 kb
Host smart-b651bf72-830d-4179-a058-4b0cb27302dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689086448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3689086448
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.903580785
Short name T46
Test name
Test status
Simulation time 12765440379 ps
CPU time 771.33 seconds
Started Jul 01 12:42:10 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 199804 kb
Host smart-2aed5453-71e9-4b5f-816d-2200231dd7f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903580785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.903580785
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.75351841
Short name T899
Test name
Test status
Simulation time 4625905507 ps
CPU time 18.92 seconds
Started Jul 01 12:42:05 PM PDT 24
Finished Jul 01 12:42:25 PM PDT 24
Peak memory 198164 kb
Host smart-43789bb8-4b46-4690-ae08-e2f81561974b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75351841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.75351841
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.412115731
Short name T457
Test name
Test status
Simulation time 21608815254 ps
CPU time 66.74 seconds
Started Jul 01 12:42:11 PM PDT 24
Finished Jul 01 12:43:19 PM PDT 24
Peak memory 200000 kb
Host smart-64e97f35-8044-4a37-8078-b2e2229af363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412115731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.412115731
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3419854598
Short name T409
Test name
Test status
Simulation time 22163333506 ps
CPU time 8.18 seconds
Started Jul 01 12:42:11 PM PDT 24
Finished Jul 01 12:42:20 PM PDT 24
Peak memory 196040 kb
Host smart-c03e09ed-f28d-4c0a-bd90-af1e89819240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419854598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3419854598
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.4139952998
Short name T1
Test name
Test status
Simulation time 577261191 ps
CPU time 1.3 seconds
Started Jul 01 12:42:04 PM PDT 24
Finished Jul 01 12:42:06 PM PDT 24
Peak memory 199496 kb
Host smart-38393752-018f-4d17-9988-6baeb8967e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139952998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.4139952998
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.988567788
Short name T625
Test name
Test status
Simulation time 82870278357 ps
CPU time 78.53 seconds
Started Jul 01 12:42:10 PM PDT 24
Finished Jul 01 12:43:29 PM PDT 24
Peak memory 199892 kb
Host smart-e5390a82-7973-4614-bb79-edc0eae7ee16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988567788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.988567788
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.116154941
Short name T561
Test name
Test status
Simulation time 11444948905 ps
CPU time 124.56 seconds
Started Jul 01 12:42:11 PM PDT 24
Finished Jul 01 12:44:17 PM PDT 24
Peak memory 215772 kb
Host smart-c6055d26-a84e-4bc8-b376-23dbe4b9840d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116154941 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.116154941
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3210198539
Short name T440
Test name
Test status
Simulation time 7087717444 ps
CPU time 17.83 seconds
Started Jul 01 12:42:11 PM PDT 24
Finished Jul 01 12:42:30 PM PDT 24
Peak memory 199812 kb
Host smart-7d1e5d63-7763-44f1-9812-9b5a2bb3bdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210198539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3210198539
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2311197231
Short name T743
Test name
Test status
Simulation time 57047872163 ps
CPU time 80.51 seconds
Started Jul 01 12:42:05 PM PDT 24
Finished Jul 01 12:43:26 PM PDT 24
Peak memory 199988 kb
Host smart-9b652dd2-1030-4bca-963a-1ea1bcca6cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311197231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2311197231
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1153313576
Short name T819
Test name
Test status
Simulation time 11361608 ps
CPU time 0.54 seconds
Started Jul 01 12:42:20 PM PDT 24
Finished Jul 01 12:42:22 PM PDT 24
Peak memory 195324 kb
Host smart-ba4ae100-4efe-4c81-851e-905cfca0559f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153313576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1153313576
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2852327139
Short name T261
Test name
Test status
Simulation time 177763414713 ps
CPU time 76.53 seconds
Started Jul 01 12:42:17 PM PDT 24
Finished Jul 01 12:43:34 PM PDT 24
Peak memory 199808 kb
Host smart-a6e4fb0c-f00d-4dd5-a887-4b3ca9418380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852327139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2852327139
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3783150816
Short name T603
Test name
Test status
Simulation time 76518848192 ps
CPU time 160.22 seconds
Started Jul 01 12:42:16 PM PDT 24
Finished Jul 01 12:44:57 PM PDT 24
Peak memory 199920 kb
Host smart-dccecc0d-4cad-4849-ba1b-188dae663a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783150816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3783150816
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.317160604
Short name T50
Test name
Test status
Simulation time 23160158750 ps
CPU time 38.86 seconds
Started Jul 01 12:42:18 PM PDT 24
Finished Jul 01 12:42:57 PM PDT 24
Peak memory 199580 kb
Host smart-0bccfc02-6ea0-4cc4-9efb-fe631289e8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317160604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.317160604
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.4182032676
Short name T908
Test name
Test status
Simulation time 36616252874 ps
CPU time 16.21 seconds
Started Jul 01 12:42:15 PM PDT 24
Finished Jul 01 12:42:33 PM PDT 24
Peak memory 199164 kb
Host smart-48267369-4a28-4911-a03e-fa6a4f61d710
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182032676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4182032676
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2745924324
Short name T596
Test name
Test status
Simulation time 95029781818 ps
CPU time 142.47 seconds
Started Jul 01 12:42:21 PM PDT 24
Finished Jul 01 12:44:45 PM PDT 24
Peak memory 199852 kb
Host smart-97be0ae2-fd74-40a7-bbb9-e94f798ded4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745924324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2745924324
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1833201431
Short name T496
Test name
Test status
Simulation time 2633400643 ps
CPU time 5.03 seconds
Started Jul 01 12:42:14 PM PDT 24
Finished Jul 01 12:42:19 PM PDT 24
Peak memory 195932 kb
Host smart-39784329-450c-49bc-849e-633f5032e5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833201431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1833201431
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1185477072
Short name T1039
Test name
Test status
Simulation time 66870558790 ps
CPU time 36.47 seconds
Started Jul 01 12:42:14 PM PDT 24
Finished Jul 01 12:42:52 PM PDT 24
Peak memory 200080 kb
Host smart-5aa4987d-f77c-4bc3-bc30-7f532d04d211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185477072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1185477072
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3959253565
Short name T590
Test name
Test status
Simulation time 33908138750 ps
CPU time 1755.85 seconds
Started Jul 01 12:42:16 PM PDT 24
Finished Jul 01 01:11:33 PM PDT 24
Peak memory 199912 kb
Host smart-afda0d61-2117-4507-91e6-c6dd7f912e0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959253565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3959253565
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2101002394
Short name T1010
Test name
Test status
Simulation time 2483830099 ps
CPU time 2.52 seconds
Started Jul 01 12:42:15 PM PDT 24
Finished Jul 01 12:42:19 PM PDT 24
Peak memory 199172 kb
Host smart-8592b660-6071-4eb5-bcf5-485262762d0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2101002394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2101002394
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.4244436692
Short name T852
Test name
Test status
Simulation time 21045485969 ps
CPU time 51.84 seconds
Started Jul 01 12:42:15 PM PDT 24
Finished Jul 01 12:43:07 PM PDT 24
Peak memory 199988 kb
Host smart-89ad77a9-24d5-4cd5-9252-b18c1024b6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244436692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4244436692
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3349552008
Short name T300
Test name
Test status
Simulation time 2794503708 ps
CPU time 1.69 seconds
Started Jul 01 12:42:16 PM PDT 24
Finished Jul 01 12:42:19 PM PDT 24
Peak memory 196356 kb
Host smart-016527be-26af-4abc-a910-19ed8902fcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349552008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3349552008
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3329894149
Short name T667
Test name
Test status
Simulation time 451408520 ps
CPU time 2.02 seconds
Started Jul 01 12:42:12 PM PDT 24
Finished Jul 01 12:42:15 PM PDT 24
Peak memory 199828 kb
Host smart-5e574ceb-8211-4fee-ad1c-18f378a226da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329894149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3329894149
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2705465865
Short name T987
Test name
Test status
Simulation time 352677022998 ps
CPU time 346.74 seconds
Started Jul 01 12:42:19 PM PDT 24
Finished Jul 01 12:48:07 PM PDT 24
Peak memory 199964 kb
Host smart-cc19e3b8-aa8d-47b5-b391-7255d5e99b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705465865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2705465865
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.733915268
Short name T71
Test name
Test status
Simulation time 6865053577 ps
CPU time 23.34 seconds
Started Jul 01 12:42:16 PM PDT 24
Finished Jul 01 12:42:40 PM PDT 24
Peak memory 199808 kb
Host smart-9bb5de5b-89e1-447b-9a7c-ea552089f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733915268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.733915268
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2981767080
Short name T666
Test name
Test status
Simulation time 118115628289 ps
CPU time 69.02 seconds
Started Jul 01 12:42:15 PM PDT 24
Finished Jul 01 12:43:25 PM PDT 24
Peak memory 200008 kb
Host smart-179286ab-130a-41a9-9c79-52c9927a9773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981767080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2981767080
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1120269711
Short name T996
Test name
Test status
Simulation time 17735615 ps
CPU time 0.53 seconds
Started Jul 01 12:42:29 PM PDT 24
Finished Jul 01 12:42:31 PM PDT 24
Peak memory 195208 kb
Host smart-cff212cd-3267-4545-902c-3aac1a62f8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120269711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1120269711
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2258529961
Short name T892
Test name
Test status
Simulation time 87385691581 ps
CPU time 300.58 seconds
Started Jul 01 12:42:23 PM PDT 24
Finished Jul 01 12:47:25 PM PDT 24
Peak memory 199932 kb
Host smart-8c9b9719-29f9-4041-9ae4-9341fc528769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258529961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2258529961
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.266964228
Short name T771
Test name
Test status
Simulation time 340619948494 ps
CPU time 64.64 seconds
Started Jul 01 12:42:20 PM PDT 24
Finished Jul 01 12:43:26 PM PDT 24
Peak memory 199892 kb
Host smart-5325da20-0634-4212-af9d-3491f4182410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266964228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.266964228
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_intr.2142108319
Short name T285
Test name
Test status
Simulation time 201175407597 ps
CPU time 94.54 seconds
Started Jul 01 12:42:29 PM PDT 24
Finished Jul 01 12:44:05 PM PDT 24
Peak memory 199836 kb
Host smart-908d2091-6f0e-4429-93fa-e840060a269e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142108319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2142108319
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2994492622
Short name T572
Test name
Test status
Simulation time 156996480846 ps
CPU time 325.14 seconds
Started Jul 01 12:42:29 PM PDT 24
Finished Jul 01 12:47:55 PM PDT 24
Peak memory 199788 kb
Host smart-3e3a0ef3-ce5b-4805-9096-150e47160080
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994492622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2994492622
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1949185277
Short name T943
Test name
Test status
Simulation time 4712413824 ps
CPU time 7.47 seconds
Started Jul 01 12:42:26 PM PDT 24
Finished Jul 01 12:42:35 PM PDT 24
Peak memory 198500 kb
Host smart-b595b9ff-a66d-49f2-bcf0-496e70d1eb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949185277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1949185277
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.250373199
Short name T567
Test name
Test status
Simulation time 45191121110 ps
CPU time 15.47 seconds
Started Jul 01 12:42:27 PM PDT 24
Finished Jul 01 12:42:43 PM PDT 24
Peak memory 200076 kb
Host smart-947507d2-51df-46aa-ae58-84fb773c2791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250373199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.250373199
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2406564418
Short name T822
Test name
Test status
Simulation time 9843830246 ps
CPU time 137.17 seconds
Started Jul 01 12:42:25 PM PDT 24
Finished Jul 01 12:44:43 PM PDT 24
Peak memory 199972 kb
Host smart-564964e1-b11b-4ebe-9cf1-c55ce7765b80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2406564418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2406564418
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.292208086
Short name T710
Test name
Test status
Simulation time 1914405044 ps
CPU time 3.24 seconds
Started Jul 01 12:42:20 PM PDT 24
Finished Jul 01 12:42:24 PM PDT 24
Peak memory 197964 kb
Host smart-806c0d51-ea76-449f-9e74-4755518db4f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292208086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.292208086
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.4211128213
Short name T1038
Test name
Test status
Simulation time 44780453561 ps
CPU time 32.21 seconds
Started Jul 01 12:42:26 PM PDT 24
Finished Jul 01 12:43:00 PM PDT 24
Peak memory 199852 kb
Host smart-f50002f3-6886-4502-bac8-2edd0290c0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211128213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.4211128213
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3617401985
Short name T542
Test name
Test status
Simulation time 5100675884 ps
CPU time 8.5 seconds
Started Jul 01 12:42:25 PM PDT 24
Finished Jul 01 12:42:34 PM PDT 24
Peak memory 196232 kb
Host smart-d2f1672a-1f1f-4de5-a7ff-656ba99561a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617401985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3617401985
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2501883411
Short name T392
Test name
Test status
Simulation time 466982106 ps
CPU time 2.07 seconds
Started Jul 01 12:42:20 PM PDT 24
Finished Jul 01 12:42:23 PM PDT 24
Peak memory 199780 kb
Host smart-65457776-a4eb-4ae4-a042-4997c3ba8e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501883411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2501883411
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4213869342
Short name T151
Test name
Test status
Simulation time 397443270495 ps
CPU time 698.65 seconds
Started Jul 01 12:42:37 PM PDT 24
Finished Jul 01 12:54:17 PM PDT 24
Peak memory 199856 kb
Host smart-fce24cb4-9833-4828-90c4-b29c3c7cacf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213869342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4213869342
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3492308331
Short name T310
Test name
Test status
Simulation time 209204015272 ps
CPU time 359.3 seconds
Started Jul 01 12:42:30 PM PDT 24
Finished Jul 01 12:48:30 PM PDT 24
Peak memory 216560 kb
Host smart-9ee70123-e3b4-483c-80bd-57016593c0fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492308331 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3492308331
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.193683599
Short name T981
Test name
Test status
Simulation time 6805115880 ps
CPU time 13.86 seconds
Started Jul 01 12:42:25 PM PDT 24
Finished Jul 01 12:42:40 PM PDT 24
Peak memory 199968 kb
Host smart-4dc4370e-634f-4162-bd48-f108c237f61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193683599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.193683599
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1328383684
Short name T672
Test name
Test status
Simulation time 18870527668 ps
CPU time 3.07 seconds
Started Jul 01 12:42:22 PM PDT 24
Finished Jul 01 12:42:26 PM PDT 24
Peak memory 199680 kb
Host smart-00c12d48-e17b-4c6a-8e40-5c5ae76727d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328383684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1328383684
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.947070980
Short name T419
Test name
Test status
Simulation time 12028603 ps
CPU time 0.56 seconds
Started Jul 01 12:42:38 PM PDT 24
Finished Jul 01 12:42:39 PM PDT 24
Peak memory 194584 kb
Host smart-a1892ba0-46a3-46c5-b9ad-febe90bb1b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947070980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.947070980
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1951990712
Short name T1046
Test name
Test status
Simulation time 256575619968 ps
CPU time 129.53 seconds
Started Jul 01 12:42:29 PM PDT 24
Finished Jul 01 12:44:39 PM PDT 24
Peak memory 199988 kb
Host smart-689fb856-09f4-4618-8b4b-22dfd18ec3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951990712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1951990712
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.455077981
Short name T470
Test name
Test status
Simulation time 244223984093 ps
CPU time 95.74 seconds
Started Jul 01 12:42:31 PM PDT 24
Finished Jul 01 12:44:08 PM PDT 24
Peak memory 199968 kb
Host smart-e7714eb7-0f04-4ce2-b46d-b8b3789e541d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455077981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.455077981
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3737093056
Short name T789
Test name
Test status
Simulation time 14402080057 ps
CPU time 6.38 seconds
Started Jul 01 12:42:37 PM PDT 24
Finished Jul 01 12:42:44 PM PDT 24
Peak memory 199780 kb
Host smart-e109c9ff-2fb7-4856-96a6-08fe1eefee48
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737093056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3737093056
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1657564148
Short name T358
Test name
Test status
Simulation time 107230951223 ps
CPU time 223.39 seconds
Started Jul 01 12:42:37 PM PDT 24
Finished Jul 01 12:46:22 PM PDT 24
Peak memory 199956 kb
Host smart-179f4814-684e-4800-b86d-df7baefd0854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1657564148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1657564148
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3893986109
Short name T1024
Test name
Test status
Simulation time 7882718412 ps
CPU time 14.5 seconds
Started Jul 01 12:42:35 PM PDT 24
Finished Jul 01 12:42:51 PM PDT 24
Peak memory 199756 kb
Host smart-64d61b07-aa24-4c25-b074-e1a637951cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893986109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3893986109
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.2221349817
Short name T437
Test name
Test status
Simulation time 17938805273 ps
CPU time 208.85 seconds
Started Jul 01 12:42:35 PM PDT 24
Finished Jul 01 12:46:05 PM PDT 24
Peak memory 199952 kb
Host smart-c353f182-1e1b-426d-9234-912a99a166be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2221349817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2221349817
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1212760740
Short name T954
Test name
Test status
Simulation time 1907618734 ps
CPU time 12.16 seconds
Started Jul 01 12:42:35 PM PDT 24
Finished Jul 01 12:42:48 PM PDT 24
Peak memory 197844 kb
Host smart-406b5a3d-5cd2-49f4-9fae-780a13c14471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1212760740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1212760740
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.261711004
Short name T890
Test name
Test status
Simulation time 25038791782 ps
CPU time 41.86 seconds
Started Jul 01 12:42:34 PM PDT 24
Finished Jul 01 12:43:17 PM PDT 24
Peak memory 199996 kb
Host smart-27075361-b881-4388-ba39-c5feb3343db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261711004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.261711004
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2261312847
Short name T702
Test name
Test status
Simulation time 27409130840 ps
CPU time 37.65 seconds
Started Jul 01 12:42:35 PM PDT 24
Finished Jul 01 12:43:14 PM PDT 24
Peak memory 196340 kb
Host smart-bc1b799c-7f2e-42ad-8fc2-500993501856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261312847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2261312847
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2852971974
Short name T359
Test name
Test status
Simulation time 5462497985 ps
CPU time 7.22 seconds
Started Jul 01 12:42:30 PM PDT 24
Finished Jul 01 12:42:38 PM PDT 24
Peak memory 199644 kb
Host smart-5b93380b-8465-4eee-b96b-3302a5dc2cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852971974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2852971974
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1630358615
Short name T1073
Test name
Test status
Simulation time 363481378235 ps
CPU time 272.37 seconds
Started Jul 01 12:42:35 PM PDT 24
Finished Jul 01 12:47:09 PM PDT 24
Peak memory 199960 kb
Host smart-06ee1ef1-f27a-496b-bcef-cd9e6464d469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630358615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1630358615
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3830152004
Short name T859
Test name
Test status
Simulation time 33537431855 ps
CPU time 275.19 seconds
Started Jul 01 12:42:36 PM PDT 24
Finished Jul 01 12:47:12 PM PDT 24
Peak memory 216088 kb
Host smart-e8c5238a-a05e-4e68-bf57-1ef31fadab05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830152004 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3830152004
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1875705917
Short name T531
Test name
Test status
Simulation time 8733048675 ps
CPU time 9.55 seconds
Started Jul 01 12:42:37 PM PDT 24
Finished Jul 01 12:42:47 PM PDT 24
Peak memory 199596 kb
Host smart-6b471609-5db1-43b5-ae03-017c8377c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875705917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1875705917
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1212110495
Short name T646
Test name
Test status
Simulation time 17652928558 ps
CPU time 31.61 seconds
Started Jul 01 12:42:32 PM PDT 24
Finished Jul 01 12:43:04 PM PDT 24
Peak memory 199872 kb
Host smart-9641362f-2932-4b49-9331-59af34919b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212110495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1212110495
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2044011782
Short name T661
Test name
Test status
Simulation time 36208227 ps
CPU time 0.57 seconds
Started Jul 01 12:42:45 PM PDT 24
Finished Jul 01 12:42:46 PM PDT 24
Peak memory 195244 kb
Host smart-9ebf108a-4fb9-45cf-8fa7-ba84f76b795a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044011782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2044011782
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2316526602
Short name T143
Test name
Test status
Simulation time 167530747490 ps
CPU time 117.63 seconds
Started Jul 01 12:42:41 PM PDT 24
Finished Jul 01 12:44:39 PM PDT 24
Peak memory 199900 kb
Host smart-6039fe4f-f280-49cd-8996-3cbe4d11d6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316526602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2316526602
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.412211044
Short name T173
Test name
Test status
Simulation time 56016851094 ps
CPU time 30.2 seconds
Started Jul 01 12:42:41 PM PDT 24
Finished Jul 01 12:43:12 PM PDT 24
Peak memory 199892 kb
Host smart-f7a2d157-19a8-4833-8f49-460969727e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412211044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.412211044
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.788792900
Short name T578
Test name
Test status
Simulation time 20139655126 ps
CPU time 42.55 seconds
Started Jul 01 12:42:39 PM PDT 24
Finished Jul 01 12:43:23 PM PDT 24
Peak memory 199936 kb
Host smart-4f4a90fe-6562-4c21-8d39-b245e23bf958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788792900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.788792900
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.4280287753
Short name T983
Test name
Test status
Simulation time 20292534563 ps
CPU time 4.62 seconds
Started Jul 01 12:42:40 PM PDT 24
Finished Jul 01 12:42:45 PM PDT 24
Peak memory 196904 kb
Host smart-089b7a68-e0ad-4cae-8537-2581607f6a81
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280287753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4280287753
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4038524761
Short name T648
Test name
Test status
Simulation time 109884113338 ps
CPU time 162.51 seconds
Started Jul 01 12:42:43 PM PDT 24
Finished Jul 01 12:45:27 PM PDT 24
Peak memory 200176 kb
Host smart-2be43577-4d70-4c70-8381-5557a468b50d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038524761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4038524761
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.4014370338
Short name T994
Test name
Test status
Simulation time 5508029851 ps
CPU time 9.82 seconds
Started Jul 01 12:42:41 PM PDT 24
Finished Jul 01 12:42:52 PM PDT 24
Peak memory 198008 kb
Host smart-a77b13b5-5c79-4490-8090-48e2d279b026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014370338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.4014370338
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.88467006
Short name T965
Test name
Test status
Simulation time 26961846678 ps
CPU time 360.95 seconds
Started Jul 01 12:42:45 PM PDT 24
Finished Jul 01 12:48:47 PM PDT 24
Peak memory 199948 kb
Host smart-072f7fa5-0002-46cf-8f6f-747b9001bc00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88467006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.88467006
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2713425427
Short name T27
Test name
Test status
Simulation time 4533635525 ps
CPU time 19.69 seconds
Started Jul 01 12:42:41 PM PDT 24
Finished Jul 01 12:43:01 PM PDT 24
Peak memory 199148 kb
Host smart-2a1e04ed-2310-45fd-a4c8-62842530d3a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713425427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2713425427
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2207078446
Short name T385
Test name
Test status
Simulation time 30168694969 ps
CPU time 25.89 seconds
Started Jul 01 12:42:39 PM PDT 24
Finished Jul 01 12:43:06 PM PDT 24
Peak memory 199892 kb
Host smart-c0b0ab96-cdca-433e-bb18-62aa04046ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207078446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2207078446
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.4049571955
Short name T11
Test name
Test status
Simulation time 5103935439 ps
CPU time 1.35 seconds
Started Jul 01 12:42:40 PM PDT 24
Finished Jul 01 12:42:43 PM PDT 24
Peak memory 196136 kb
Host smart-6bd94719-e3a7-4e19-860b-ae04e81fd182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049571955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.4049571955
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.678014267
Short name T912
Test name
Test status
Simulation time 85552436 ps
CPU time 0.92 seconds
Started Jul 01 12:42:35 PM PDT 24
Finished Jul 01 12:42:37 PM PDT 24
Peak memory 197224 kb
Host smart-699bdeb3-91d6-4bd3-bdda-27f6515a310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678014267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.678014267
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.860042837
Short name T523
Test name
Test status
Simulation time 335670171592 ps
CPU time 147.95 seconds
Started Jul 01 12:42:45 PM PDT 24
Finished Jul 01 12:45:14 PM PDT 24
Peak memory 199908 kb
Host smart-35ad185d-23cc-4a23-b7ad-d9e9451d3698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860042837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.860042837
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3482606700
Short name T934
Test name
Test status
Simulation time 63745608944 ps
CPU time 472.3 seconds
Started Jul 01 12:42:45 PM PDT 24
Finished Jul 01 12:50:38 PM PDT 24
Peak memory 216484 kb
Host smart-90a5ae2e-f4f6-40d4-b313-d12d631641ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482606700 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3482606700
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2486595644
Short name T782
Test name
Test status
Simulation time 635210289 ps
CPU time 2.26 seconds
Started Jul 01 12:42:39 PM PDT 24
Finished Jul 01 12:42:41 PM PDT 24
Peak memory 198652 kb
Host smart-7d8b6c09-294f-4f5d-b799-4cd270207a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486595644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2486595644
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.761957219
Short name T466
Test name
Test status
Simulation time 42378413345 ps
CPU time 63 seconds
Started Jul 01 12:42:37 PM PDT 24
Finished Jul 01 12:43:41 PM PDT 24
Peak memory 199964 kb
Host smart-54863284-a4fd-4d18-9f0d-56dde901bd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761957219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.761957219
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1187838776
Short name T376
Test name
Test status
Simulation time 13066053 ps
CPU time 0.58 seconds
Started Jul 01 12:35:54 PM PDT 24
Finished Jul 01 12:35:55 PM PDT 24
Peak memory 195252 kb
Host smart-b03a2c97-1c61-49a0-83b8-9d84680c0f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187838776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1187838776
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1457593454
Short name T763
Test name
Test status
Simulation time 140421459017 ps
CPU time 90.16 seconds
Started Jul 01 12:35:47 PM PDT 24
Finished Jul 01 12:37:18 PM PDT 24
Peak memory 199980 kb
Host smart-c56b736e-3a78-420b-abc7-8906134065ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457593454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1457593454
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.795866711
Short name T1033
Test name
Test status
Simulation time 28443551890 ps
CPU time 5.36 seconds
Started Jul 01 12:35:46 PM PDT 24
Finished Jul 01 12:35:52 PM PDT 24
Peak memory 199912 kb
Host smart-6a4f9f5d-00f7-47f0-8353-c8796d95247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795866711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.795866711
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3665468820
Short name T6
Test name
Test status
Simulation time 44391115003 ps
CPU time 27.14 seconds
Started Jul 01 12:35:48 PM PDT 24
Finished Jul 01 12:36:16 PM PDT 24
Peak memory 199868 kb
Host smart-fb77f3bf-0c48-4e4b-bce9-03740c04220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665468820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3665468820
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1282647299
Short name T678
Test name
Test status
Simulation time 30410249695 ps
CPU time 12.37 seconds
Started Jul 01 12:35:53 PM PDT 24
Finished Jul 01 12:36:06 PM PDT 24
Peak memory 200116 kb
Host smart-7aefc9a4-1246-41ef-9e0b-cc54a8e6bbce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282647299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1282647299
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2105585846
Short name T962
Test name
Test status
Simulation time 96795518428 ps
CPU time 252.43 seconds
Started Jul 01 12:35:49 PM PDT 24
Finished Jul 01 12:40:02 PM PDT 24
Peak memory 199944 kb
Host smart-ba46d0a5-6829-4c15-aead-275163df6156
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2105585846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2105585846
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3932195023
Short name T112
Test name
Test status
Simulation time 8901932636 ps
CPU time 7.67 seconds
Started Jul 01 12:35:49 PM PDT 24
Finished Jul 01 12:35:58 PM PDT 24
Peak memory 199924 kb
Host smart-213dc44d-30c0-41c8-93ed-dba44de3df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932195023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3932195023
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2862145692
Short name T580
Test name
Test status
Simulation time 36881653965 ps
CPU time 14.56 seconds
Started Jul 01 12:35:49 PM PDT 24
Finished Jul 01 12:36:05 PM PDT 24
Peak memory 199808 kb
Host smart-0ec48af7-71e6-4d47-b736-234fa85b6d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862145692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2862145692
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3585644683
Short name T277
Test name
Test status
Simulation time 6343920863 ps
CPU time 356.41 seconds
Started Jul 01 12:35:49 PM PDT 24
Finished Jul 01 12:41:47 PM PDT 24
Peak memory 199924 kb
Host smart-96fbdf09-589c-40bb-98c8-21699ce5772d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585644683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3585644683
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1201775556
Short name T517
Test name
Test status
Simulation time 3977196474 ps
CPU time 28.87 seconds
Started Jul 01 12:35:48 PM PDT 24
Finished Jul 01 12:36:17 PM PDT 24
Peak memory 197960 kb
Host smart-c9c339a9-91ce-45d0-8dc7-ec7a4430a2d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201775556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1201775556
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1075345362
Short name T700
Test name
Test status
Simulation time 34794012076 ps
CPU time 14.17 seconds
Started Jul 01 12:35:48 PM PDT 24
Finished Jul 01 12:36:03 PM PDT 24
Peak memory 199960 kb
Host smart-238f2523-f1b8-40fc-a8ff-5fd61b97ec25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075345362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1075345362
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1158186163
Short name T1055
Test name
Test status
Simulation time 1993221895 ps
CPU time 3.39 seconds
Started Jul 01 12:35:49 PM PDT 24
Finished Jul 01 12:35:54 PM PDT 24
Peak memory 195412 kb
Host smart-54cfd800-a11c-4781-a2f9-0b6dbdfd7388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158186163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1158186163
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1419521031
Short name T55
Test name
Test status
Simulation time 6092157918 ps
CPU time 15.75 seconds
Started Jul 01 12:35:46 PM PDT 24
Finished Jul 01 12:36:02 PM PDT 24
Peak memory 199932 kb
Host smart-f549bd7a-3580-45b1-b2f3-fa5146e4cf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419521031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1419521031
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2674760526
Short name T434
Test name
Test status
Simulation time 56915317336 ps
CPU time 44.22 seconds
Started Jul 01 12:35:49 PM PDT 24
Finished Jul 01 12:36:34 PM PDT 24
Peak memory 199932 kb
Host smart-cdb0eb6b-83f5-4858-a199-385151900735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674760526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2674760526
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.620828333
Short name T829
Test name
Test status
Simulation time 24393629209 ps
CPU time 233.16 seconds
Started Jul 01 12:35:48 PM PDT 24
Finished Jul 01 12:39:42 PM PDT 24
Peak memory 215592 kb
Host smart-d951f889-f5d0-42bb-82c8-f2114fbadb30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620828333 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.620828333
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.186127793
Short name T902
Test name
Test status
Simulation time 994471001 ps
CPU time 2.88 seconds
Started Jul 01 12:35:49 PM PDT 24
Finished Jul 01 12:35:53 PM PDT 24
Peak memory 199912 kb
Host smart-7f876fe7-2257-4b01-a421-7e0bf6e7ec9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186127793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.186127793
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2593581241
Short name T920
Test name
Test status
Simulation time 4612917803 ps
CPU time 4.02 seconds
Started Jul 01 12:35:43 PM PDT 24
Finished Jul 01 12:35:47 PM PDT 24
Peak memory 197196 kb
Host smart-ea42d022-cd3d-44b9-b76c-16a30cd7d1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593581241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2593581241
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3822746493
Short name T1069
Test name
Test status
Simulation time 46674881248 ps
CPU time 19.71 seconds
Started Jul 01 12:42:46 PM PDT 24
Finished Jul 01 12:43:06 PM PDT 24
Peak memory 199936 kb
Host smart-5c27987a-fd06-4c2f-b2a2-c7fef090d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822746493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3822746493
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3236555500
Short name T858
Test name
Test status
Simulation time 130082463804 ps
CPU time 30.91 seconds
Started Jul 01 12:42:43 PM PDT 24
Finished Jul 01 12:43:15 PM PDT 24
Peak memory 199972 kb
Host smart-46b7c702-8e71-4ac5-a2a4-2ee9a51fbbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236555500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3236555500
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1272480647
Short name T103
Test name
Test status
Simulation time 65932119946 ps
CPU time 133.07 seconds
Started Jul 01 12:42:44 PM PDT 24
Finished Jul 01 12:44:58 PM PDT 24
Peak memory 216260 kb
Host smart-0f144eab-00c9-415f-9522-6514ee7dc339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272480647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1272480647
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.86609897
Short name T1090
Test name
Test status
Simulation time 85541660170 ps
CPU time 67.67 seconds
Started Jul 01 12:42:49 PM PDT 24
Finished Jul 01 12:43:58 PM PDT 24
Peak memory 200000 kb
Host smart-1a1aac5e-f8c1-4e1a-8ead-05fe1b58e103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86609897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.86609897
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1824702394
Short name T313
Test name
Test status
Simulation time 43532623084 ps
CPU time 521.02 seconds
Started Jul 01 12:42:51 PM PDT 24
Finished Jul 01 12:51:34 PM PDT 24
Peak memory 216488 kb
Host smart-a9a44c17-88cc-45f1-9d25-5c6e2e43b02c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824702394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1824702394
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1004472381
Short name T914
Test name
Test status
Simulation time 311018723456 ps
CPU time 34.54 seconds
Started Jul 01 12:42:51 PM PDT 24
Finished Jul 01 12:43:27 PM PDT 24
Peak memory 199896 kb
Host smart-f8a9b2c6-7590-48dd-a663-5ba1d750a023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004472381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1004472381
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.186773335
Short name T984
Test name
Test status
Simulation time 46950128408 ps
CPU time 143.29 seconds
Started Jul 01 12:42:50 PM PDT 24
Finished Jul 01 12:45:14 PM PDT 24
Peak memory 216048 kb
Host smart-ac85c42d-15bb-4b66-a258-94f88a0c4a19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186773335 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.186773335
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2126131295
Short name T52
Test name
Test status
Simulation time 113732075369 ps
CPU time 63.54 seconds
Started Jul 01 12:42:50 PM PDT 24
Finished Jul 01 12:43:55 PM PDT 24
Peak memory 199996 kb
Host smart-3ece58ec-9556-4286-ad9e-5918f74e3851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126131295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2126131295
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1010788973
Short name T633
Test name
Test status
Simulation time 51438825318 ps
CPU time 654.74 seconds
Started Jul 01 12:42:52 PM PDT 24
Finished Jul 01 12:53:48 PM PDT 24
Peak memory 216428 kb
Host smart-3ad7f53c-3176-413e-82eb-291233940d89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010788973 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1010788973
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.618931240
Short name T860
Test name
Test status
Simulation time 174275652841 ps
CPU time 137.84 seconds
Started Jul 01 12:42:51 PM PDT 24
Finished Jul 01 12:45:10 PM PDT 24
Peak memory 199772 kb
Host smart-6aa2fda8-59c9-41a3-9280-c41e48be4243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618931240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.618931240
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3962413675
Short name T940
Test name
Test status
Simulation time 101275092565 ps
CPU time 1241.13 seconds
Started Jul 01 12:42:50 PM PDT 24
Finished Jul 01 01:03:32 PM PDT 24
Peak memory 227336 kb
Host smart-58abda35-844c-4171-b26b-a5a53f7ca649
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962413675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3962413675
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.569268275
Short name T184
Test name
Test status
Simulation time 51681278586 ps
CPU time 20.37 seconds
Started Jul 01 12:42:55 PM PDT 24
Finished Jul 01 12:43:16 PM PDT 24
Peak memory 199872 kb
Host smart-49ed629d-cccd-4c9e-bbe3-7a234dff3c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569268275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.569268275
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.152081691
Short name T845
Test name
Test status
Simulation time 70988824792 ps
CPU time 106.73 seconds
Started Jul 01 12:42:57 PM PDT 24
Finished Jul 01 12:44:44 PM PDT 24
Peak memory 199880 kb
Host smart-9fce1737-1256-45f6-b72e-e4a0ff3add67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152081691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.152081691
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3880349215
Short name T364
Test name
Test status
Simulation time 11385819391 ps
CPU time 24.03 seconds
Started Jul 01 12:42:55 PM PDT 24
Finished Jul 01 12:43:19 PM PDT 24
Peak memory 199852 kb
Host smart-f66df0f2-ce5d-48c6-8e6e-42b1ac816bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880349215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3880349215
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2488963089
Short name T102
Test name
Test status
Simulation time 185020726430 ps
CPU time 485.09 seconds
Started Jul 01 12:42:56 PM PDT 24
Finished Jul 01 12:51:01 PM PDT 24
Peak memory 216376 kb
Host smart-45417a75-fcd0-411e-b5d4-5f53dd835b11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488963089 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2488963089
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.4190037043
Short name T698
Test name
Test status
Simulation time 24133333 ps
CPU time 0.57 seconds
Started Jul 01 12:36:00 PM PDT 24
Finished Jul 01 12:36:01 PM PDT 24
Peak memory 195328 kb
Host smart-f8d6afe0-3892-4b68-add3-b1fa1b0160c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190037043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.4190037043
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3767857510
Short name T1101
Test name
Test status
Simulation time 157071554572 ps
CPU time 248.98 seconds
Started Jul 01 12:35:55 PM PDT 24
Finished Jul 01 12:40:04 PM PDT 24
Peak memory 199892 kb
Host smart-c648dfb9-1e69-4d28-9cc2-4044cd345586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767857510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3767857510
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1966175538
Short name T921
Test name
Test status
Simulation time 44551128131 ps
CPU time 11.02 seconds
Started Jul 01 12:35:54 PM PDT 24
Finished Jul 01 12:36:06 PM PDT 24
Peak memory 199996 kb
Host smart-2d214514-0ab3-4cf2-ad40-3770e70497fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966175538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1966175538
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.706078490
Short name T951
Test name
Test status
Simulation time 52879944907 ps
CPU time 87.67 seconds
Started Jul 01 12:35:54 PM PDT 24
Finished Jul 01 12:37:23 PM PDT 24
Peak memory 199940 kb
Host smart-7e58ad35-0035-45bb-8e3a-5395d050c2de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706078490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.706078490
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3397823131
Short name T424
Test name
Test status
Simulation time 64813036125 ps
CPU time 116.56 seconds
Started Jul 01 12:35:59 PM PDT 24
Finished Jul 01 12:37:56 PM PDT 24
Peak memory 199980 kb
Host smart-4304bee2-b62f-401a-b5f8-02575594981f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397823131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3397823131
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.304472921
Short name T917
Test name
Test status
Simulation time 7511277509 ps
CPU time 12.41 seconds
Started Jul 01 12:35:59 PM PDT 24
Finished Jul 01 12:36:12 PM PDT 24
Peak memory 199948 kb
Host smart-82583bb1-5281-4a03-ad97-531d7d31243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304472921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.304472921
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.76986516
Short name T414
Test name
Test status
Simulation time 28952093253 ps
CPU time 293.89 seconds
Started Jul 01 12:36:00 PM PDT 24
Finished Jul 01 12:40:55 PM PDT 24
Peak memory 199860 kb
Host smart-ea067e88-59b8-445a-a462-9006b7a3246f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76986516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.76986516
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1145722553
Short name T431
Test name
Test status
Simulation time 3358362101 ps
CPU time 16.3 seconds
Started Jul 01 12:35:54 PM PDT 24
Finished Jul 01 12:36:11 PM PDT 24
Peak memory 198996 kb
Host smart-d350d294-82f7-415b-851f-944f6acffe2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145722553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1145722553
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3320305088
Short name T638
Test name
Test status
Simulation time 104761959115 ps
CPU time 174.82 seconds
Started Jul 01 12:35:59 PM PDT 24
Finished Jul 01 12:38:55 PM PDT 24
Peak memory 199936 kb
Host smart-98c95f7b-14d0-4ccb-8d07-987db32e28ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320305088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3320305088
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.4015168961
Short name T671
Test name
Test status
Simulation time 39691869931 ps
CPU time 16.58 seconds
Started Jul 01 12:36:01 PM PDT 24
Finished Jul 01 12:36:18 PM PDT 24
Peak memory 196784 kb
Host smart-9385540e-9251-4bde-98b1-9c554efaf700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015168961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.4015168961
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2307199722
Short name T656
Test name
Test status
Simulation time 5990557711 ps
CPU time 23.52 seconds
Started Jul 01 12:35:58 PM PDT 24
Finished Jul 01 12:36:22 PM PDT 24
Peak memory 199432 kb
Host smart-41ee3504-5c62-480b-bd95-34a06c61b6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307199722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2307199722
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1925397324
Short name T950
Test name
Test status
Simulation time 238119805542 ps
CPU time 458.66 seconds
Started Jul 01 12:35:59 PM PDT 24
Finished Jul 01 12:43:39 PM PDT 24
Peak memory 199952 kb
Host smart-b1bfe1f5-d786-4349-af7d-989c57599c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925397324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1925397324
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.209564128
Short name T311
Test name
Test status
Simulation time 28580267434 ps
CPU time 683.73 seconds
Started Jul 01 12:35:59 PM PDT 24
Finished Jul 01 12:47:24 PM PDT 24
Peak memory 216576 kb
Host smart-912e80ab-5dda-4e0a-a775-41e96a0dd9a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209564128 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.209564128
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2682271607
Short name T451
Test name
Test status
Simulation time 4885352127 ps
CPU time 1.64 seconds
Started Jul 01 12:36:00 PM PDT 24
Finished Jul 01 12:36:02 PM PDT 24
Peak memory 199964 kb
Host smart-2197a9d1-86dd-4628-a5b0-c479d889ece9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682271607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2682271607
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3728336362
Short name T1047
Test name
Test status
Simulation time 2795672821 ps
CPU time 5 seconds
Started Jul 01 12:35:54 PM PDT 24
Finished Jul 01 12:35:59 PM PDT 24
Peak memory 199168 kb
Host smart-3ffc2c79-90a1-4ca7-9f0a-3dcfa78378b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728336362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3728336362
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.4112846740
Short name T241
Test name
Test status
Simulation time 216135528779 ps
CPU time 104.99 seconds
Started Jul 01 12:42:55 PM PDT 24
Finished Jul 01 12:44:41 PM PDT 24
Peak memory 199892 kb
Host smart-f5d9cb14-ac04-4cf3-9a61-08dd2c868402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112846740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4112846740
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.540944511
Short name T100
Test name
Test status
Simulation time 113315913727 ps
CPU time 367.29 seconds
Started Jul 01 12:42:55 PM PDT 24
Finished Jul 01 12:49:03 PM PDT 24
Peak memory 216484 kb
Host smart-dccbdd23-e579-4928-844b-e8c45b98adf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540944511 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.540944511
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2342970613
Short name T189
Test name
Test status
Simulation time 66963161258 ps
CPU time 127.8 seconds
Started Jul 01 12:42:56 PM PDT 24
Finished Jul 01 12:45:05 PM PDT 24
Peak memory 199864 kb
Host smart-59e3dac6-d824-47ad-a65d-a0322d1a1a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342970613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2342970613
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.87628485
Short name T582
Test name
Test status
Simulation time 214568174982 ps
CPU time 669.21 seconds
Started Jul 01 12:42:59 PM PDT 24
Finished Jul 01 12:54:09 PM PDT 24
Peak memory 225744 kb
Host smart-80c38089-d290-414e-9b4e-e2c72e60c9cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87628485 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.87628485
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1323031724
Short name T718
Test name
Test status
Simulation time 29337409540 ps
CPU time 62.48 seconds
Started Jul 01 12:43:00 PM PDT 24
Finished Jul 01 12:44:03 PM PDT 24
Peak memory 199908 kb
Host smart-6e93e38a-b8b9-4f5e-86e0-e6505d44d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323031724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1323031724
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2065529590
Short name T611
Test name
Test status
Simulation time 22016347832 ps
CPU time 34.33 seconds
Started Jul 01 12:42:59 PM PDT 24
Finished Jul 01 12:43:34 PM PDT 24
Peak memory 199928 kb
Host smart-9d64fcaa-7dd8-4252-868c-539175aaee6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065529590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2065529590
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1408843574
Short name T220
Test name
Test status
Simulation time 26551969741 ps
CPU time 46.18 seconds
Started Jul 01 12:43:03 PM PDT 24
Finished Jul 01 12:43:50 PM PDT 24
Peak memory 200108 kb
Host smart-c5b9ccef-c9be-4694-9e53-8889398dd4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408843574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1408843574
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2197706081
Short name T123
Test name
Test status
Simulation time 451752909938 ps
CPU time 546.41 seconds
Started Jul 01 12:43:06 PM PDT 24
Finished Jul 01 12:52:13 PM PDT 24
Peak memory 216496 kb
Host smart-ecc97b18-cd75-4fc9-9f45-9e44b10e13d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197706081 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2197706081
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.293814631
Short name T152
Test name
Test status
Simulation time 232265018246 ps
CPU time 73.03 seconds
Started Jul 01 12:43:05 PM PDT 24
Finished Jul 01 12:44:18 PM PDT 24
Peak memory 200008 kb
Host smart-24e34ed4-4609-46d4-ae14-7499d31a08bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293814631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.293814631
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2196998830
Short name T821
Test name
Test status
Simulation time 18438094462 ps
CPU time 18.26 seconds
Started Jul 01 12:43:04 PM PDT 24
Finished Jul 01 12:43:23 PM PDT 24
Peak memory 199948 kb
Host smart-e3cb73be-30cf-40f6-8cc4-305ae0bafdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196998830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2196998830
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.448656735
Short name T163
Test name
Test status
Simulation time 480092755635 ps
CPU time 870.33 seconds
Started Jul 01 12:43:06 PM PDT 24
Finished Jul 01 12:57:37 PM PDT 24
Peak memory 224916 kb
Host smart-7aa38bc2-8518-4de8-a487-fd70ba46912d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448656735 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.448656735
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.19348462
Short name T826
Test name
Test status
Simulation time 108512713586 ps
CPU time 72.92 seconds
Started Jul 01 12:43:05 PM PDT 24
Finished Jul 01 12:44:19 PM PDT 24
Peak memory 199992 kb
Host smart-5b43061a-1df2-4e85-8c45-a1204543b815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19348462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.19348462
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.4025056962
Short name T794
Test name
Test status
Simulation time 171150657474 ps
CPU time 119.41 seconds
Started Jul 01 12:43:09 PM PDT 24
Finished Jul 01 12:45:09 PM PDT 24
Peak memory 199824 kb
Host smart-cd632b68-029e-4cf4-94d3-6900bba43e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025056962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4025056962
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1834308056
Short name T159
Test name
Test status
Simulation time 73369896386 ps
CPU time 335.94 seconds
Started Jul 01 12:43:10 PM PDT 24
Finished Jul 01 12:48:47 PM PDT 24
Peak memory 216492 kb
Host smart-97c70ebc-f831-4ac2-b539-f59276e2d683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834308056 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1834308056
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1608186556
Short name T31
Test name
Test status
Simulation time 45275169 ps
CPU time 0.56 seconds
Started Jul 01 12:36:11 PM PDT 24
Finished Jul 01 12:36:12 PM PDT 24
Peak memory 195312 kb
Host smart-01feb030-2e24-4a88-9e70-b34219ef6632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608186556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1608186556
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2091355384
Short name T527
Test name
Test status
Simulation time 13476956028 ps
CPU time 21.04 seconds
Started Jul 01 12:36:05 PM PDT 24
Finished Jul 01 12:36:27 PM PDT 24
Peak memory 199980 kb
Host smart-7a0173f9-eafa-47e4-ae07-d64fa9e655aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091355384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2091355384
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2967439677
Short name T928
Test name
Test status
Simulation time 210906134926 ps
CPU time 86.73 seconds
Started Jul 01 12:36:07 PM PDT 24
Finished Jul 01 12:37:34 PM PDT 24
Peak memory 199936 kb
Host smart-30f35125-d97f-467f-a569-a4a30266d0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967439677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2967439677
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1815912798
Short name T121
Test name
Test status
Simulation time 30325447428 ps
CPU time 17.76 seconds
Started Jul 01 12:36:05 PM PDT 24
Finished Jul 01 12:36:23 PM PDT 24
Peak memory 199984 kb
Host smart-c494bd57-bb30-4b3d-ac2f-476216306358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815912798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1815912798
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3645708387
Short name T990
Test name
Test status
Simulation time 10803105923 ps
CPU time 6.91 seconds
Started Jul 01 12:36:06 PM PDT 24
Finished Jul 01 12:36:13 PM PDT 24
Peak memory 199980 kb
Host smart-2e20d143-ef2d-45af-9cf0-b2436d0fc20e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645708387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3645708387
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.4165591697
Short name T850
Test name
Test status
Simulation time 170403469733 ps
CPU time 328.1 seconds
Started Jul 01 12:36:05 PM PDT 24
Finished Jul 01 12:41:33 PM PDT 24
Peak memory 199964 kb
Host smart-dfeb5c26-221f-4846-b289-fc01d107d289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165591697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.4165591697
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2486504325
Short name T836
Test name
Test status
Simulation time 1271294207 ps
CPU time 1.72 seconds
Started Jul 01 12:36:05 PM PDT 24
Finished Jul 01 12:36:07 PM PDT 24
Peak memory 196932 kb
Host smart-d657f3dd-b7ec-4031-85db-a5ffa98c462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486504325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2486504325
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.3551835597
Short name T699
Test name
Test status
Simulation time 22222555986 ps
CPU time 240.84 seconds
Started Jul 01 12:36:05 PM PDT 24
Finished Jul 01 12:40:07 PM PDT 24
Peak memory 199964 kb
Host smart-b13b3b24-4957-4543-8a2f-fa9ba2a1a55a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551835597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3551835597
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1718744629
Short name T812
Test name
Test status
Simulation time 4571826769 ps
CPU time 20.68 seconds
Started Jul 01 12:36:07 PM PDT 24
Finished Jul 01 12:36:29 PM PDT 24
Peak memory 199220 kb
Host smart-84a8ba0a-e168-4276-96b7-022c53278460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1718744629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1718744629
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2992233543
Short name T509
Test name
Test status
Simulation time 89478115521 ps
CPU time 141.58 seconds
Started Jul 01 12:36:07 PM PDT 24
Finished Jul 01 12:38:29 PM PDT 24
Peak memory 199864 kb
Host smart-3e28c149-339e-41fa-be28-bedb21308e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992233543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2992233543
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1136785237
Short name T891
Test name
Test status
Simulation time 4530928261 ps
CPU time 2.36 seconds
Started Jul 01 12:36:07 PM PDT 24
Finished Jul 01 12:36:10 PM PDT 24
Peak memory 196020 kb
Host smart-035e68cf-6198-4a1b-8ab0-ece0acb772d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136785237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1136785237
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3558011303
Short name T903
Test name
Test status
Simulation time 272613909 ps
CPU time 1.34 seconds
Started Jul 01 12:36:00 PM PDT 24
Finished Jul 01 12:36:02 PM PDT 24
Peak memory 198136 kb
Host smart-35218288-a156-4cf5-af07-17eff45b3d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558011303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3558011303
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2626037040
Short name T900
Test name
Test status
Simulation time 87032340497 ps
CPU time 197.25 seconds
Started Jul 01 12:36:09 PM PDT 24
Finished Jul 01 12:39:27 PM PDT 24
Peak memory 199984 kb
Host smart-4ae98e7c-c3b1-4577-861f-4ede901f693e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626037040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2626037040
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.994813497
Short name T510
Test name
Test status
Simulation time 6378639911 ps
CPU time 29.58 seconds
Started Jul 01 12:36:06 PM PDT 24
Finished Jul 01 12:36:36 PM PDT 24
Peak memory 199700 kb
Host smart-739a5c74-ad96-4624-b3b9-a07cb5d9b1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994813497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.994813497
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1802164991
Short name T369
Test name
Test status
Simulation time 9592559489 ps
CPU time 8.08 seconds
Started Jul 01 12:36:05 PM PDT 24
Finished Jul 01 12:36:14 PM PDT 24
Peak memory 199972 kb
Host smart-0f977416-e245-4ae4-8343-aea1c79461c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802164991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1802164991
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1269072014
Short name T217
Test name
Test status
Simulation time 134950911136 ps
CPU time 58.64 seconds
Started Jul 01 12:43:10 PM PDT 24
Finished Jul 01 12:44:10 PM PDT 24
Peak memory 199892 kb
Host smart-bc273f92-68bb-4895-94c5-2fa7d0d30b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269072014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1269072014
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3769086936
Short name T889
Test name
Test status
Simulation time 35628159195 ps
CPU time 97.03 seconds
Started Jul 01 12:43:11 PM PDT 24
Finished Jul 01 12:44:48 PM PDT 24
Peak memory 215540 kb
Host smart-8022f838-7fe5-4429-bce5-c28c7c8f712c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769086936 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3769086936
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3383887481
Short name T758
Test name
Test status
Simulation time 101108749567 ps
CPU time 45.77 seconds
Started Jul 01 12:43:10 PM PDT 24
Finished Jul 01 12:43:56 PM PDT 24
Peak memory 199936 kb
Host smart-1fbffcc7-524a-4a92-b8a6-3a2f7d529dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383887481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3383887481
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.360666126
Short name T101
Test name
Test status
Simulation time 20547267412 ps
CPU time 180.16 seconds
Started Jul 01 12:43:10 PM PDT 24
Finished Jul 01 12:46:11 PM PDT 24
Peak memory 215580 kb
Host smart-571c200c-b428-4ca9-9efc-d041c4d172ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360666126 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.360666126
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2097667753
Short name T519
Test name
Test status
Simulation time 67778109335 ps
CPU time 31.87 seconds
Started Jul 01 12:43:13 PM PDT 24
Finished Jul 01 12:43:46 PM PDT 24
Peak memory 199992 kb
Host smart-04e4af2a-5099-40f3-be51-4e61c072b4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097667753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2097667753
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2538983906
Short name T1040
Test name
Test status
Simulation time 131661886626 ps
CPU time 66.48 seconds
Started Jul 01 12:43:18 PM PDT 24
Finished Jul 01 12:44:25 PM PDT 24
Peak memory 199900 kb
Host smart-e58c9e65-b55e-4f62-a6d8-41691fb54209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538983906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2538983906
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3869331866
Short name T197
Test name
Test status
Simulation time 22375854735 ps
CPU time 618.39 seconds
Started Jul 01 12:43:18 PM PDT 24
Finished Jul 01 12:53:37 PM PDT 24
Peak memory 216496 kb
Host smart-893e080d-0b78-4297-bdb3-d4ec6a0f6c21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869331866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3869331866
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.843816490
Short name T637
Test name
Test status
Simulation time 388427823554 ps
CPU time 1216.02 seconds
Started Jul 01 12:43:15 PM PDT 24
Finished Jul 01 01:03:32 PM PDT 24
Peak memory 224752 kb
Host smart-d2055801-0c19-43c7-a7b5-2da750d1c8dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843816490 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.843816490
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2587335598
Short name T144
Test name
Test status
Simulation time 38567893274 ps
CPU time 24.14 seconds
Started Jul 01 12:43:15 PM PDT 24
Finished Jul 01 12:43:40 PM PDT 24
Peak memory 199996 kb
Host smart-c44b07fd-4571-4470-a741-a26141176559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587335598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2587335598
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.4258724995
Short name T975
Test name
Test status
Simulation time 115561187591 ps
CPU time 777.02 seconds
Started Jul 01 12:43:16 PM PDT 24
Finished Jul 01 12:56:14 PM PDT 24
Peak memory 216512 kb
Host smart-d7eeb249-339c-4f15-8995-d6d83fd33fa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258724995 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.4258724995
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2731484784
Short name T598
Test name
Test status
Simulation time 103671387104 ps
CPU time 318.63 seconds
Started Jul 01 12:43:14 PM PDT 24
Finished Jul 01 12:48:33 PM PDT 24
Peak memory 200008 kb
Host smart-7928c499-1e5d-4119-ae6c-9d20e94577b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731484784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2731484784
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3191713840
Short name T153
Test name
Test status
Simulation time 23494738204 ps
CPU time 17.29 seconds
Started Jul 01 12:43:16 PM PDT 24
Finished Jul 01 12:43:34 PM PDT 24
Peak memory 199804 kb
Host smart-d774144d-4bca-4ea9-9a63-a44c23318aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191713840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3191713840
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1606657814
Short name T166
Test name
Test status
Simulation time 32651828184 ps
CPU time 47.98 seconds
Started Jul 01 12:43:16 PM PDT 24
Finished Jul 01 12:44:05 PM PDT 24
Peak memory 199912 kb
Host smart-b4baddaa-b5d4-41ba-89d5-b0da3020e88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606657814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1606657814
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.4010338794
Short name T59
Test name
Test status
Simulation time 92791005220 ps
CPU time 952.38 seconds
Started Jul 01 12:43:20 PM PDT 24
Finished Jul 01 12:59:13 PM PDT 24
Peak memory 224724 kb
Host smart-82be5490-759d-48dc-8865-6a1c59d4aa32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010338794 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.4010338794
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1708280437
Short name T604
Test name
Test status
Simulation time 14553754 ps
CPU time 0.58 seconds
Started Jul 01 12:36:16 PM PDT 24
Finished Jul 01 12:36:17 PM PDT 24
Peak memory 195492 kb
Host smart-8d788f81-a581-46a7-b92a-7c59b3278d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708280437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1708280437
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3392771449
Short name T1017
Test name
Test status
Simulation time 108499701920 ps
CPU time 89.69 seconds
Started Jul 01 12:36:09 PM PDT 24
Finished Jul 01 12:37:39 PM PDT 24
Peak memory 200000 kb
Host smart-e2808f2a-4b24-4902-a5ab-9d198ed348db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392771449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3392771449
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1437683352
Short name T1082
Test name
Test status
Simulation time 20396716576 ps
CPU time 33.23 seconds
Started Jul 01 12:36:10 PM PDT 24
Finished Jul 01 12:36:45 PM PDT 24
Peak memory 199820 kb
Host smart-9e296287-d043-4c2d-b6d9-6790f00fafbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437683352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1437683352
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.610289736
Short name T505
Test name
Test status
Simulation time 116216275000 ps
CPU time 201.05 seconds
Started Jul 01 12:36:11 PM PDT 24
Finished Jul 01 12:39:33 PM PDT 24
Peak memory 199888 kb
Host smart-2f97ec24-8a4b-4bd1-88f6-927d5c2b80ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610289736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.610289736
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.77342151
Short name T383
Test name
Test status
Simulation time 8321515514 ps
CPU time 1.98 seconds
Started Jul 01 12:36:11 PM PDT 24
Finished Jul 01 12:36:14 PM PDT 24
Peak memory 196672 kb
Host smart-b31f707a-5fd1-442c-a448-9e87eb3970b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77342151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.77342151
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2968576771
Short name T643
Test name
Test status
Simulation time 109754946125 ps
CPU time 816.81 seconds
Started Jul 01 12:36:14 PM PDT 24
Finished Jul 01 12:49:51 PM PDT 24
Peak memory 199984 kb
Host smart-f4f6b840-c205-4aa7-a6ca-cdcb3004f299
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968576771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2968576771
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1146759335
Short name T806
Test name
Test status
Simulation time 3340195365 ps
CPU time 6.52 seconds
Started Jul 01 12:36:14 PM PDT 24
Finished Jul 01 12:36:21 PM PDT 24
Peak memory 198656 kb
Host smart-318f6bde-9224-4eae-9355-71fa9e103911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146759335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1146759335
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.3773350334
Short name T399
Test name
Test status
Simulation time 5596513028 ps
CPU time 319.92 seconds
Started Jul 01 12:36:14 PM PDT 24
Finished Jul 01 12:41:34 PM PDT 24
Peak memory 199908 kb
Host smart-1b85a08b-f96f-4464-868b-ba7c0fbf982d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773350334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3773350334
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2250992121
Short name T380
Test name
Test status
Simulation time 3062672639 ps
CPU time 5.62 seconds
Started Jul 01 12:36:10 PM PDT 24
Finished Jul 01 12:36:16 PM PDT 24
Peak memory 199428 kb
Host smart-b29a5d0b-ea1d-45ca-9fa2-c6fbae6fd9df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2250992121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2250992121
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.793866314
Short name T1088
Test name
Test status
Simulation time 34998581202 ps
CPU time 68.46 seconds
Started Jul 01 12:36:11 PM PDT 24
Finished Jul 01 12:37:20 PM PDT 24
Peak memory 199852 kb
Host smart-7acda2ad-9b03-41e3-8193-d53e90d44154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793866314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.793866314
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2050656217
Short name T1006
Test name
Test status
Simulation time 1962147680 ps
CPU time 1.4 seconds
Started Jul 01 12:36:09 PM PDT 24
Finished Jul 01 12:36:11 PM PDT 24
Peak memory 195372 kb
Host smart-ab5be857-898a-4597-b47a-2603bc12d18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050656217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2050656217
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2605342256
Short name T905
Test name
Test status
Simulation time 832907883 ps
CPU time 2.02 seconds
Started Jul 01 12:36:11 PM PDT 24
Finished Jul 01 12:36:14 PM PDT 24
Peak memory 199472 kb
Host smart-908fc7df-52b4-48bd-ab8c-1d2063c1e274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605342256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2605342256
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1311852996
Short name T162
Test name
Test status
Simulation time 516202188886 ps
CPU time 503.98 seconds
Started Jul 01 12:36:13 PM PDT 24
Finished Jul 01 12:44:38 PM PDT 24
Peak memory 199880 kb
Host smart-49e7dcc7-6355-45d0-8c80-50dd5e1a5e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311852996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1311852996
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.146736088
Short name T107
Test name
Test status
Simulation time 113709793398 ps
CPU time 227.39 seconds
Started Jul 01 12:36:14 PM PDT 24
Finished Jul 01 12:40:02 PM PDT 24
Peak memory 216340 kb
Host smart-77ffbbc5-7052-4832-97c2-5b1173df31e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146736088 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.146736088
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1267323115
Short name T22
Test name
Test status
Simulation time 1036701608 ps
CPU time 3.07 seconds
Started Jul 01 12:36:15 PM PDT 24
Finished Jul 01 12:36:18 PM PDT 24
Peak memory 199380 kb
Host smart-199e97d2-bc02-440d-9764-288137c1a9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267323115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1267323115
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.374347605
Short name T516
Test name
Test status
Simulation time 82005856940 ps
CPU time 128.15 seconds
Started Jul 01 12:36:08 PM PDT 24
Finished Jul 01 12:38:17 PM PDT 24
Peak memory 199856 kb
Host smart-93a23e24-bcfb-4454-9895-0abee3a28e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374347605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.374347605
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2598005507
Short name T791
Test name
Test status
Simulation time 235403523782 ps
CPU time 55.77 seconds
Started Jul 01 12:43:19 PM PDT 24
Finished Jul 01 12:44:16 PM PDT 24
Peak memory 199892 kb
Host smart-36e6ce8f-ff14-4fce-907d-245d03f326f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598005507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2598005507
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.227400227
Short name T58
Test name
Test status
Simulation time 66133818608 ps
CPU time 1639.64 seconds
Started Jul 01 12:43:19 PM PDT 24
Finished Jul 01 01:10:40 PM PDT 24
Peak memory 216572 kb
Host smart-9e111de6-3210-4559-8a15-167c0a038adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227400227 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.227400227
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3033584369
Short name T373
Test name
Test status
Simulation time 77580914916 ps
CPU time 119.36 seconds
Started Jul 01 12:43:19 PM PDT 24
Finished Jul 01 12:45:19 PM PDT 24
Peak memory 199812 kb
Host smart-f335e051-2626-4fa8-890f-b426d35559bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033584369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3033584369
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.4228056362
Short name T579
Test name
Test status
Simulation time 26295262455 ps
CPU time 46.82 seconds
Started Jul 01 12:43:20 PM PDT 24
Finished Jul 01 12:44:08 PM PDT 24
Peak memory 200020 kb
Host smart-599835d6-e934-461d-a0ce-88ccdb6f8916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228056362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.4228056362
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.4072185336
Short name T271
Test name
Test status
Simulation time 24778833864 ps
CPU time 10.95 seconds
Started Jul 01 12:43:20 PM PDT 24
Finished Jul 01 12:43:32 PM PDT 24
Peak memory 199984 kb
Host smart-4f08976a-82d4-44f1-9925-621cc5dea4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072185336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.4072185336
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1307586165
Short name T501
Test name
Test status
Simulation time 60782902450 ps
CPU time 47.92 seconds
Started Jul 01 12:43:25 PM PDT 24
Finished Jul 01 12:44:14 PM PDT 24
Peak memory 199744 kb
Host smart-562f3918-31f1-4cb8-9583-2c20208e5dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307586165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1307586165
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3936486301
Short name T124
Test name
Test status
Simulation time 26706600945 ps
CPU time 195.45 seconds
Started Jul 01 12:43:25 PM PDT 24
Finished Jul 01 12:46:41 PM PDT 24
Peak memory 208320 kb
Host smart-3d20b5c2-1977-4863-a3f2-908385af0c2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936486301 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3936486301
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3893855720
Short name T326
Test name
Test status
Simulation time 78072242987 ps
CPU time 24.74 seconds
Started Jul 01 12:43:26 PM PDT 24
Finished Jul 01 12:43:52 PM PDT 24
Peak memory 199892 kb
Host smart-f2304c78-bbf9-4f68-af20-3c4bf29bd34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893855720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3893855720
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2244948418
Short name T315
Test name
Test status
Simulation time 21341140965 ps
CPU time 626.11 seconds
Started Jul 01 12:43:27 PM PDT 24
Finished Jul 01 12:53:54 PM PDT 24
Peak memory 208360 kb
Host smart-2b12185e-1f3f-4945-9be0-f65c429d4c9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244948418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2244948418
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.112713909
Short name T592
Test name
Test status
Simulation time 290648165281 ps
CPU time 196.5 seconds
Started Jul 01 12:43:25 PM PDT 24
Finished Jul 01 12:46:41 PM PDT 24
Peak memory 199912 kb
Host smart-6df87786-ef3a-457f-9a64-529bcecd1346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112713909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.112713909
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3899126715
Short name T105
Test name
Test status
Simulation time 76172150599 ps
CPU time 135.36 seconds
Started Jul 01 12:43:26 PM PDT 24
Finished Jul 01 12:45:42 PM PDT 24
Peak memory 216492 kb
Host smart-c6ed0d85-3379-4cc2-aaab-8d7a63e5e188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899126715 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3899126715
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1772041639
Short name T1036
Test name
Test status
Simulation time 112639450753 ps
CPU time 36.31 seconds
Started Jul 01 12:43:25 PM PDT 24
Finished Jul 01 12:44:02 PM PDT 24
Peak memory 199776 kb
Host smart-165ec39d-5bdc-4d95-9675-d323aef858cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772041639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1772041639
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1659454698
Short name T39
Test name
Test status
Simulation time 161411205487 ps
CPU time 742.34 seconds
Started Jul 01 12:43:25 PM PDT 24
Finished Jul 01 12:55:48 PM PDT 24
Peak memory 216412 kb
Host smart-724d0012-2d83-44d5-a4d8-5ba962692e94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659454698 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1659454698
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.466195206
Short name T202
Test name
Test status
Simulation time 54584500976 ps
CPU time 106.17 seconds
Started Jul 01 12:43:27 PM PDT 24
Finished Jul 01 12:45:13 PM PDT 24
Peak memory 199832 kb
Host smart-21fe9556-bd03-4331-9329-9b704c97cbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466195206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.466195206
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3407017362
Short name T1079
Test name
Test status
Simulation time 89262509075 ps
CPU time 269.68 seconds
Started Jul 01 12:43:27 PM PDT 24
Finished Jul 01 12:47:57 PM PDT 24
Peak memory 216444 kb
Host smart-26ced20b-9163-4954-83cc-761144f02362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407017362 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3407017362
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1438228014
Short name T919
Test name
Test status
Simulation time 121198397865 ps
CPU time 11.02 seconds
Started Jul 01 12:43:30 PM PDT 24
Finished Jul 01 12:43:42 PM PDT 24
Peak memory 199952 kb
Host smart-106c24b8-4b7d-48dd-9f53-3da1eda1adac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438228014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1438228014
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2009854102
Short name T106
Test name
Test status
Simulation time 23942452069 ps
CPU time 273.54 seconds
Started Jul 01 12:43:29 PM PDT 24
Finished Jul 01 12:48:03 PM PDT 24
Peak memory 216484 kb
Host smart-f5a21294-fd95-48db-b891-9bd314c21c7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009854102 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2009854102
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1045930632
Short name T336
Test name
Test status
Simulation time 19212174 ps
CPU time 0.58 seconds
Started Jul 01 12:36:25 PM PDT 24
Finished Jul 01 12:36:27 PM PDT 24
Peak memory 195216 kb
Host smart-4107a997-3b72-46b9-853d-b59ee1e49293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045930632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1045930632
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1392791861
Short name T275
Test name
Test status
Simulation time 25798424379 ps
CPU time 19.79 seconds
Started Jul 01 12:36:19 PM PDT 24
Finished Jul 01 12:36:40 PM PDT 24
Peak memory 199936 kb
Host smart-8633fb35-0769-48d7-9bea-9784b5a9d2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392791861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1392791861
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1592936639
Short name T249
Test name
Test status
Simulation time 196678308532 ps
CPU time 136.98 seconds
Started Jul 01 12:36:19 PM PDT 24
Finished Jul 01 12:38:38 PM PDT 24
Peak memory 199840 kb
Host smart-ea53de5a-e9d2-4d10-8ee7-b6dc548060dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592936639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1592936639
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3472149507
Short name T1018
Test name
Test status
Simulation time 94242593488 ps
CPU time 149.89 seconds
Started Jul 01 12:36:18 PM PDT 24
Finished Jul 01 12:38:49 PM PDT 24
Peak memory 199900 kb
Host smart-b6d50acd-17ab-4649-a58b-4ec0917d57d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472149507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3472149507
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2767756778
Short name T581
Test name
Test status
Simulation time 34407802193 ps
CPU time 15.1 seconds
Started Jul 01 12:36:19 PM PDT 24
Finished Jul 01 12:36:34 PM PDT 24
Peak memory 199748 kb
Host smart-e7fb5ea3-5498-4022-b204-d0ec6772a4b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767756778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2767756778
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3448675134
Short name T918
Test name
Test status
Simulation time 218381976426 ps
CPU time 241.03 seconds
Started Jul 01 12:36:24 PM PDT 24
Finished Jul 01 12:40:26 PM PDT 24
Peak memory 199904 kb
Host smart-da583eef-0fc2-4439-b884-f58521008d7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448675134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3448675134
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2577764031
Short name T863
Test name
Test status
Simulation time 7019510549 ps
CPU time 3.94 seconds
Started Jul 01 12:36:24 PM PDT 24
Finished Jul 01 12:36:29 PM PDT 24
Peak memory 197992 kb
Host smart-c72f4b68-fc69-4b36-b5ba-8d79e8921cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577764031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2577764031
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1680255717
Short name T1091
Test name
Test status
Simulation time 2271845687 ps
CPU time 1.47 seconds
Started Jul 01 12:36:18 PM PDT 24
Finished Jul 01 12:36:21 PM PDT 24
Peak memory 198684 kb
Host smart-a0df5e75-16ee-41da-8ee2-380816e461b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680255717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1680255717
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.47336637
Short name T942
Test name
Test status
Simulation time 22986476395 ps
CPU time 1283.33 seconds
Started Jul 01 12:36:25 PM PDT 24
Finished Jul 01 12:57:49 PM PDT 24
Peak memory 199920 kb
Host smart-b05ca71f-8779-45ba-8cbc-73c141e5305f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47336637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.47336637
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2116876473
Short name T945
Test name
Test status
Simulation time 5634921348 ps
CPU time 44.36 seconds
Started Jul 01 12:36:19 PM PDT 24
Finished Jul 01 12:37:05 PM PDT 24
Peak memory 198544 kb
Host smart-3d7f7336-e561-44b0-a6bd-1e97a5e929ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2116876473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2116876473
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1059301521
Short name T753
Test name
Test status
Simulation time 22698159468 ps
CPU time 15.25 seconds
Started Jul 01 12:36:17 PM PDT 24
Finished Jul 01 12:36:33 PM PDT 24
Peak memory 198284 kb
Host smart-a018938e-21fb-4045-ae19-5ff6a927d647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059301521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1059301521
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.992541709
Short name T548
Test name
Test status
Simulation time 1760696133 ps
CPU time 2.1 seconds
Started Jul 01 12:36:20 PM PDT 24
Finished Jul 01 12:36:23 PM PDT 24
Peak memory 195440 kb
Host smart-6968c871-b58f-4553-bdab-2ca38160104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992541709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.992541709
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1633489343
Short name T619
Test name
Test status
Simulation time 845258569 ps
CPU time 5.09 seconds
Started Jul 01 12:36:13 PM PDT 24
Finished Jul 01 12:36:19 PM PDT 24
Peak memory 198172 kb
Host smart-6091d28f-1d91-42e8-8166-4b4184d29b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633489343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1633489343
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3622341638
Short name T838
Test name
Test status
Simulation time 178247662608 ps
CPU time 185.37 seconds
Started Jul 01 12:36:23 PM PDT 24
Finished Jul 01 12:39:29 PM PDT 24
Peak memory 199900 kb
Host smart-fb009989-11e9-447a-bf9c-24c2e3c18fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622341638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3622341638
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2714652134
Short name T901
Test name
Test status
Simulation time 1032448966 ps
CPU time 3.35 seconds
Started Jul 01 12:36:23 PM PDT 24
Finished Jul 01 12:36:27 PM PDT 24
Peak memory 198420 kb
Host smart-3fd038c1-d12f-48d3-bcc6-852a45fcba81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714652134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2714652134
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2740813911
Short name T711
Test name
Test status
Simulation time 90681201399 ps
CPU time 13.82 seconds
Started Jul 01 12:36:20 PM PDT 24
Finished Jul 01 12:36:35 PM PDT 24
Peak memory 196684 kb
Host smart-3be3f72e-e058-4e54-9712-4d407dfba22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740813911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2740813911
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.4123362227
Short name T147
Test name
Test status
Simulation time 77116811858 ps
CPU time 114.03 seconds
Started Jul 01 12:43:30 PM PDT 24
Finished Jul 01 12:45:24 PM PDT 24
Peak memory 200116 kb
Host smart-85990da8-1b82-4b35-a45e-5a928bb7ee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123362227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4123362227
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.197241264
Short name T601
Test name
Test status
Simulation time 14338631020 ps
CPU time 12.12 seconds
Started Jul 01 12:43:30 PM PDT 24
Finished Jul 01 12:43:42 PM PDT 24
Peak memory 199928 kb
Host smart-636c6cb8-108c-44d7-bf05-99064707b569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197241264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.197241264
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1562851192
Short name T529
Test name
Test status
Simulation time 95882242580 ps
CPU time 382.55 seconds
Started Jul 01 12:43:30 PM PDT 24
Finished Jul 01 12:49:53 PM PDT 24
Peak memory 216436 kb
Host smart-661063ef-0277-432c-9362-6fc2bf7e8688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562851192 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1562851192
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3393188635
Short name T69
Test name
Test status
Simulation time 117331611024 ps
CPU time 194.02 seconds
Started Jul 01 12:43:31 PM PDT 24
Finished Jul 01 12:46:45 PM PDT 24
Peak memory 199936 kb
Host smart-1819c03d-3b31-4c20-84a5-18b5cab29b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393188635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3393188635
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3631272637
Short name T185
Test name
Test status
Simulation time 221665227584 ps
CPU time 153.35 seconds
Started Jul 01 12:43:30 PM PDT 24
Finished Jul 01 12:46:04 PM PDT 24
Peak memory 199952 kb
Host smart-3d811b62-d2f1-4fbd-812c-63dc78153075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631272637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3631272637
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.550148219
Short name T38
Test name
Test status
Simulation time 47227293172 ps
CPU time 569.09 seconds
Started Jul 01 12:43:30 PM PDT 24
Finished Jul 01 12:53:00 PM PDT 24
Peak memory 216580 kb
Host smart-20be14b5-903d-48c3-9141-0a99c0c31bcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550148219 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.550148219
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2956221195
Short name T262
Test name
Test status
Simulation time 86936402730 ps
CPU time 98.57 seconds
Started Jul 01 12:43:35 PM PDT 24
Finished Jul 01 12:45:15 PM PDT 24
Peak memory 199912 kb
Host smart-fd6aae20-b479-41a3-b925-3af9c18e15cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956221195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2956221195
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3828511867
Short name T314
Test name
Test status
Simulation time 37755731435 ps
CPU time 372.91 seconds
Started Jul 01 12:43:35 PM PDT 24
Finished Jul 01 12:49:49 PM PDT 24
Peak memory 216380 kb
Host smart-8408112c-ccaf-4a97-b081-a09333b43237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828511867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3828511867
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2131581050
Short name T333
Test name
Test status
Simulation time 73193714748 ps
CPU time 24.3 seconds
Started Jul 01 12:43:34 PM PDT 24
Finished Jul 01 12:43:59 PM PDT 24
Peak memory 199148 kb
Host smart-5fe74999-aaf6-42f8-a5b5-5945d7253473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131581050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2131581050
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.582877837
Short name T540
Test name
Test status
Simulation time 80365752451 ps
CPU time 807.58 seconds
Started Jul 01 12:43:35 PM PDT 24
Finished Jul 01 12:57:03 PM PDT 24
Peak memory 224732 kb
Host smart-c6c44cc6-cded-4553-83b7-08379ffd96d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582877837 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.582877837
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.224999026
Short name T738
Test name
Test status
Simulation time 51262034032 ps
CPU time 46.05 seconds
Started Jul 01 12:43:40 PM PDT 24
Finished Jul 01 12:44:27 PM PDT 24
Peak memory 199868 kb
Host smart-8d787821-a919-4c78-b634-64d26cd5ee22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224999026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.224999026
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2511476740
Short name T17
Test name
Test status
Simulation time 86048466821 ps
CPU time 213.47 seconds
Started Jul 01 12:43:40 PM PDT 24
Finished Jul 01 12:47:14 PM PDT 24
Peak memory 216220 kb
Host smart-dfbea17f-5619-4411-9adf-96e4d7975a90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511476740 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2511476740
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1497290657
Short name T299
Test name
Test status
Simulation time 138081321632 ps
CPU time 179.12 seconds
Started Jul 01 12:43:39 PM PDT 24
Finished Jul 01 12:46:39 PM PDT 24
Peak memory 199928 kb
Host smart-346fc927-1200-422c-98a1-a0d182767a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497290657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1497290657
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.575922862
Short name T148
Test name
Test status
Simulation time 42039972469 ps
CPU time 36 seconds
Started Jul 01 12:43:38 PM PDT 24
Finished Jul 01 12:44:15 PM PDT 24
Peak memory 199924 kb
Host smart-07ccb2ea-b647-499b-b286-2f418cd262f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575922862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.575922862
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2763769627
Short name T722
Test name
Test status
Simulation time 97405302261 ps
CPU time 283.75 seconds
Started Jul 01 12:43:38 PM PDT 24
Finished Jul 01 12:48:22 PM PDT 24
Peak memory 216476 kb
Host smart-9a5b274b-c167-4eed-b3df-117706e88347
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763769627 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2763769627
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.627640921
Short name T682
Test name
Test status
Simulation time 104120246260 ps
CPU time 308.35 seconds
Started Jul 01 12:43:38 PM PDT 24
Finished Jul 01 12:48:47 PM PDT 24
Peak memory 199860 kb
Host smart-810402a7-e7da-4a43-aa2a-0b91cf4a221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627640921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.627640921
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.682278280
Short name T1013
Test name
Test status
Simulation time 32198700635 ps
CPU time 736.14 seconds
Started Jul 01 12:43:46 PM PDT 24
Finished Jul 01 12:56:02 PM PDT 24
Peak memory 215708 kb
Host smart-84b76ef6-baa1-4dd4-8221-3e7d6ae2aebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682278280 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.682278280
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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