Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99722	1			T1	1		T2	7		T3	1
all_values[1]	99722	1			T1	1		T2	7		T3	1
all_values[2]	99722	1			T1	1		T2	7		T3	1
all_values[3]	99722	1			T1	1		T2	7		T3	1
all_values[4]	99722	1			T1	1		T2	7		T3	1
all_values[5]	99722	1			T1	1		T2	7		T3	1
all_values[6]	99722	1			T1	1		T2	7		T3	1
all_values[7]	99722	1			T1	1		T2	7		T3	1
all_values[8]	99722	1			T1	1		T2	7		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

443634

1

T1

3

T2

33

T3

5

auto[1]

453864

1

T1

6

T2

30

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

817491

1

T1

7

T2

48

T3

7

auto[1]

80007

1

T1

2

T2

15

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	30873	1			T5	3		T8	15		T10	19
all_values[0]	auto[0]	auto[1]	19301	1			T2	7		T3	1		T6	2
all_values[0]	auto[1]	auto[0]	29641	1			T5	29		T33	24		T14	8
all_values[0]	auto[1]	auto[1]	19907	1			T1	1		T4	4		T5	1
all_values[1]	auto[0]	auto[0]	47454	1			T3	1		T6	2		T8	27
all_values[1]	auto[0]	auto[1]	1464	1			T10	2		T11	16		T14	8
all_values[1]	auto[1]	auto[0]	49373	1			T1	1		T2	7		T4	4
all_values[1]	auto[1]	auto[1]	1431	1			T5	17		T10	13		T12	1
all_values[2]	auto[0]	auto[0]	47184	1			T5	30		T6	1		T8	3
all_values[2]	auto[0]	auto[1]	2227	1			T5	3		T6	1		T8	1
all_values[2]	auto[1]	auto[0]	48347	1			T1	1		T2	6		T3	1
all_values[2]	auto[1]	auto[1]	1964	1			T2	1		T4	1		T10	6
all_values[3]	auto[0]	auto[0]	50651	1			T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	219	1			T10	2		T11	1		T14	1
all_values[3]	auto[1]	auto[0]	48593	1			T2	5		T5	13		T7	1
all_values[3]	auto[1]	auto[1]	259	1			T5	1		T10	2		T14	5
all_values[4]	auto[0]	auto[0]	49433	1			T2	5		T5	4		T6	2
all_values[4]	auto[0]	auto[1]	272	1			T11	9		T14	5		T133	9
all_values[4]	auto[1]	auto[0]	49644	1			T1	1		T2	2		T3	1
all_values[4]	auto[1]	auto[1]	373	1			T10	10		T26	2		T249	10
all_values[5]	auto[0]	auto[0]	50178	1			T1	1		T2	2		T5	19
all_values[5]	auto[0]	auto[1]	142	1			T10	3		T14	2		T25	3
all_values[5]	auto[1]	auto[0]	49271	1			T2	5		T3	1		T4	4
all_values[5]	auto[1]	auto[1]	131	1			T10	4		T14	2		T25	1
all_values[6]	auto[0]	auto[0]	47183	1			T1	1		T2	5		T3	1
all_values[6]	auto[0]	auto[1]	139	1			T10	3		T14	2		T25	1
all_values[6]	auto[1]	auto[0]	52270	1			T2	2		T5	32		T8	17
all_values[6]	auto[1]	auto[1]	130	1			T10	1		T27	3		T124	6
all_values[7]	auto[0]	auto[0]	48994	1			T2	7		T3	1		T4	4
all_values[7]	auto[0]	auto[1]	280	1			T11	8		T14	2		T126	1
all_values[7]	auto[1]	auto[0]	50122	1			T1	1		T5	4		T8	40
all_values[7]	auto[1]	auto[1]	326	1			T14	3		T25	2		T126	2
all_values[8]	auto[0]	auto[0]	32935	1			T5	29		T8	37		T10	13
all_values[8]	auto[0]	auto[1]	14705	1			T2	5		T4	4		T5	1
all_values[8]	auto[1]	auto[0]	35345	1			T5	3		T10	20		T32	3
all_values[8]	auto[1]	auto[1]	16737	1			T1	1		T2	2		T3	1