Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2225

1

T1

1

T2

1

T3

1

auto[UartRx]

2225

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4058	1			T1	2		T2	2		T3	2
values[1]	30	1			T14	1		T25	1		T27	1
values[2]	30	1			T10	1		T27	1		T30	1
values[3]	29	1			T8	1		T25	1		T26	1
values[4]	36	1			T8	1		T10	1		T14	1
values[5]	39	1			T14	1		T25	4		T26	1
values[6]	45	1			T10	1		T26	1		T27	1
values[7]	37	1			T8	1		T25	1		T26	1
values[8]	44	1			T8	1		T14	2		T25	1
values[9]	44	1			T25	2		T26	1		T29	1
values[10]	42	1			T10	2		T25	1		T27	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2088	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	7	1			T27	1		T28	1		T337	1
auto[UartTx]	values[2]	9	1			T10	1		T337	1		T338	1
auto[UartTx]	values[3]	12	1			T8	1		T25	1		T26	1
auto[UartTx]	values[4]	14	1			T10	1		T121	2		T338	1
auto[UartTx]	values[5]	12	1			T14	1		T25	1		T50	1
auto[UartTx]	values[6]	15	1			T339	2		T340	1		T123	2
auto[UartTx]	values[7]	13	1			T26	1		T31	1		T121	1
auto[UartTx]	values[8]	17	1			T14	1		T26	1		T152	1
auto[UartTx]	values[9]	15	1			T25	1		T29	1		T31	1
auto[UartTx]	values[10]	17	1			T10	1		T27	1		T31	1
auto[UartRx]	values[0]	1970	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	23	1			T14	1		T25	1		T29	1
auto[UartRx]	values[2]	21	1			T27	1		T30	1		T337	1
auto[UartRx]	values[3]	17	1			T27	1		T28	1		T136	1
auto[UartRx]	values[4]	22	1			T8	1		T14	1		T29	1
auto[UartRx]	values[5]	27	1			T25	3		T26	1		T28	1
auto[UartRx]	values[6]	30	1			T10	1		T26	1		T27	1
auto[UartRx]	values[7]	24	1			T8	1		T25	1		T30	2
auto[UartRx]	values[8]	27	1			T8	1		T14	1		T25	1
auto[UartRx]	values[9]	29	1			T25	1		T26	1		T30	1
auto[UartRx]	values[10]	25	1			T10	1		T25	1		T27	1