Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1921	1			T1	5		T2	1		T3	9
auto[BaudRate115200]	1555	1			T4	1		T5	1		T6	1
auto[BaudRate230400]	1544	1			T2	2		T5	3		T8	2
auto[BaudRate128Kbps]	1556	1			T2	1		T8	2		T9	1
auto[BaudRate256Kbps]	1676	1			T2	1		T4	1		T5	2
auto[BaudRate1Mbps]	1427	1			T4	1		T5	2		T8	3
auto[BaudRate1p5Mbps]	1098	1			T4	2		T5	1		T8	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	808	1			T127	9		T341	10		T288	2
freqs[25]	1045	1			T8	12		T138	5		T274	2
freqs[48]	531	1			T7	8		T128	7		T194	10
freqs[50]	377	1			T17	27		T302	2		T298	2
freqs[100]	1099	1			T258	9		T37	9		T133	4

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	131	1			T127	2		T341	10		T269	1
auto[BaudRate9600]	freqs[25]	166	1			T274	1		T150	1		T342	6
auto[BaudRate9600]	freqs[48]	74	1			T7	8		T194	2		T31	4
auto[BaudRate9600]	freqs[50]	82	1			T17	6		T176	1		T343	5
auto[BaudRate9600]	freqs[100]	169	1			T144	1		T145	1		T142	1
auto[BaudRate115200]	freqs[24]	121	1			T127	1		T335	1		T268	1
auto[BaudRate115200]	freqs[25]	139	1			T8	1		T138	1		T274	1
auto[BaudRate115200]	freqs[48]	64	1			T264	1		T31	4		T184	1
auto[BaudRate115200]	freqs[50]	66	1			T17	6		T147	1		T344	1
auto[BaudRate115200]	freqs[100]	164	1			T133	1		T144	3		T145	1
auto[BaudRate230400]	freqs[24]	110	1			T127	1		T292	1		T153	2
auto[BaudRate230400]	freqs[25]	141	1			T8	2		T138	1		T150	1
auto[BaudRate230400]	freqs[48]	81	1			T194	2		T31	4		T184	1
auto[BaudRate230400]	freqs[50]	51	1			T17	6		T147	3		T176	4
auto[BaudRate230400]	freqs[100]	129	1			T37	4		T144	2		T141	1
auto[BaudRate128Kbps]	freqs[24]	135	1			T127	3		T335	1		T268	3
auto[BaudRate128Kbps]	freqs[25]	143	1			T8	2		T138	2		T27	9
auto[BaudRate128Kbps]	freqs[48]	95	1			T128	2		T194	4		T264	2
auto[BaudRate128Kbps]	freqs[50]	24	1			T65	3		T78	1		T345	1
auto[BaudRate128Kbps]	freqs[100]	162	1			T37	2		T133	3		T144	1
auto[BaudRate256Kbps]	freqs[24]	136	1			T127	1		T268	1		T292	1
auto[BaudRate256Kbps]	freqs[25]	177	1			T8	2		T138	1		T150	1
auto[BaudRate256Kbps]	freqs[48]	84	1			T128	3		T264	1		T31	3
auto[BaudRate256Kbps]	freqs[50]	44	1			T302	1		T147	2		T346	1
auto[BaudRate256Kbps]	freqs[100]	148	1			T258	4		T144	2		T145	1
auto[BaudRate1Mbps]	freqs[24]	113	1			T127	1		T269	1		T268	2
auto[BaudRate1Mbps]	freqs[25]	186	1			T8	3		T150	2		T342	6
auto[BaudRate1Mbps]	freqs[48]	59	1			T128	2		T194	1		T264	1
auto[BaudRate1Mbps]	freqs[50]	67	1			T17	6		T147	1		T346	2
auto[BaudRate1Mbps]	freqs[100]	150	1			T258	2		T37	2		T144	1
auto[BaudRate1p5Mbps]	freqs[25]	93	1			T8	2		T342	3		T27	2
auto[BaudRate1p5Mbps]	freqs[48]	74	1			T194	1		T31	3		T191	2
auto[BaudRate1p5Mbps]	freqs[50]	43	1			T17	3		T302	1		T298	2
auto[BaudRate1p5Mbps]	freqs[100]	177	1			T258	3		T37	1		T141	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded