Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32040036	1			T1	1		T2	17		T3	1
all_levels[1]	179273	1			T2	1		T5	2		T8	656
all_levels[2]	1872	1			T8	17		T25	5		T126	1
all_levels[3]	829	1			T10	1		T33	1		T25	1
all_levels[4]	570	1			T10	3		T34	1		T25	1
all_levels[5]	462	1			T4	1		T5	4		T10	2
all_levels[6]	335	1			T5	1		T10	1		T33	1
all_levels[7]	299	1			T4	1		T5	5		T10	1
all_levels[8]	269	1			T5	1		T32	2		T34	1
all_levels[9]	215	1			T5	1		T10	1		T33	1
all_levels[10]	202	1			T5	1		T10	1		T12	2
all_levels[11]	174	1			T10	2		T12	1		T33	1
all_levels[12]	111	1			T4	2		T10	3		T32	1
all_levels[13]	135	1			T14	1		T138	1		T126	2
all_levels[14]	124	1			T12	1		T14	1		T130	1
all_levels[15]	88	1			T4	5		T5	1		T10	1
all_levels[16]	110	1			T10	1		T36	2		T139	1
all_levels[17]	98	1			T25	1		T126	1		T140	3
all_levels[18]	82	1			T40	1		T141	1		T142	1
all_levels[19]	80	1			T5	1		T14	1		T130	1
all_levels[20]	66	1			T126	1		T143	1		T141	2
all_levels[21]	96	1			T33	1		T25	1		T35	1
all_levels[22]	58	1			T126	1		T139	1		T129	2
all_levels[23]	74	1			T12	2		T144	1		T145	1
all_levels[24]	60	1			T35	1		T127	1		T139	1
all_levels[25]	48	1			T142	1		T146	1		T147	2
all_levels[26]	41	1			T26	1		T145	1		T148	1
all_levels[27]	52	1			T130	1		T35	1		T145	1
all_levels[28]	29	1			T126	2		T145	3		T141	1
all_levels[29]	47	1			T138	2		T149	1		T40	1
all_levels[30]	41	1			T125	1		T126	1		T150	1
all_levels[31]	42	1			T130	1		T127	1		T141	2
all_levels[32]	32	1			T130	1		T150	1		T151	1
all_levels[33]	24	1			T33	2		T148	1		T152	1
all_levels[34]	23	1			T145	1		T142	1		T153	1
all_levels[35]	19	1			T149	1		T142	3		T135	1
all_levels[36]	33	1			T145	1		T142	1		T27	1
all_levels[37]	17	1			T154	1		T152	1		T155	2
all_levels[38]	18	1			T148	1		T142	1		T27	1
all_levels[39]	11	1			T156	1		T157	1		T158	1
all_levels[40]	15	1			T159	3		T160	2		T161	1
all_levels[41]	19	1			T127	1		T145	1		T162	1
all_levels[42]	11	1			T131	2		T163	1		T164	1
all_levels[43]	14	1			T12	1		T165	1		T156	1
all_levels[44]	25	1			T25	1		T148	1		T27	1
all_levels[45]	11	1			T27	1		T166	2		T62	1
all_levels[46]	16	1			T130	1		T27	1		T167	1
all_levels[47]	12	1			T168	1		T169	1		T170	3
all_levels[48]	5	1			T171	1		T172	1		T173	1
all_levels[49]	14	1			T145	1		T174	1		T175	4
all_levels[50]	16	1			T127	1		T152	1		T161	1
all_levels[51]	9	1			T27	1		T160	1		T152	1
all_levels[52]	16	1			T149	1		T37	2		T143	1
all_levels[53]	10	1			T176	3		T177	1		T178	1
all_levels[54]	2	1			T152	1		T179	1		-	-
all_levels[55]	7	1			T152	1		T157	1		T180	1
all_levels[56]	9	1			T5	1		T36	4		T181	1
all_levels[57]	7	1			T156	1		T180	1		T182	1
all_levels[58]	1	1			T183	1		-	-		-	-
all_levels[59]	11	1			T184	1		T164	1		T185	4
all_levels[60]	2	1			T186	1		T187	1		-	-
all_levels[61]	10	1			T188	4		T189	1		T190	1
all_levels[62]	3	1			T191	2		T192	1		-	-
all_levels[63]	5	1			T152	1		T193	1		T171	1
all_levels[64]	93	1			T125	1		T26	1		T143	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32222314

1

T2

18

T4

17

T5

19

auto[1]

4224

1

T1

1

T3

1

T4

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[54] , all_levels[55]]	[auto[1]]	--	--	2
[all_levels[57] , all_levels[58]]	[auto[1]]	--	--	2
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32036321	1			T2	17		T4	11		T5	6
all_levels[0]	auto[1]	3715	1			T1	1		T3	1		T4	2
all_levels[1]	auto[0]	179170	1			T2	1		T5	2		T8	656
all_levels[1]	auto[1]	103	1			T25	1		T194	1		T195	1
all_levels[2]	auto[0]	1849	1			T8	17		T25	5		T126	1
all_levels[2]	auto[1]	23	1			T144	2		T153	4		T174	1
all_levels[3]	auto[0]	813	1			T10	1		T33	1		T25	1
all_levels[3]	auto[1]	16	1			T196	1		T41	1		T81	1
all_levels[4]	auto[0]	553	1			T10	3		T34	1		T25	1
all_levels[4]	auto[1]	17	1			T194	1		T197	1		T198	1
all_levels[5]	auto[0]	437	1			T4	1		T5	2		T10	2
all_levels[5]	auto[1]	25	1			T5	2		T199	1		T128	1
all_levels[6]	auto[0]	322	1			T5	1		T10	1		T33	1
all_levels[6]	auto[1]	13	1			T144	1		T30	1		T120	1
all_levels[7]	auto[0]	278	1			T4	1		T5	2		T10	1
all_levels[7]	auto[1]	21	1			T5	3		T12	3		T32	2
all_levels[8]	auto[0]	248	1			T5	1		T32	1		T34	1
all_levels[8]	auto[1]	21	1			T32	1		T147	1		T200	4
all_levels[9]	auto[0]	201	1			T5	1		T10	1		T33	1
all_levels[9]	auto[1]	14	1			T25	1		T201	2		T202	2
all_levels[10]	auto[0]	190	1			T5	1		T10	1		T12	2
all_levels[10]	auto[1]	12	1			T25	1		T144	1		T191	1
all_levels[11]	auto[0]	168	1			T10	2		T12	1		T33	1
all_levels[11]	auto[1]	6	1			T75	1		T203	2		T204	1
all_levels[12]	auto[0]	106	1			T4	2		T10	3		T32	1
all_levels[12]	auto[1]	5	1			T144	1		T62	1		T205	1
all_levels[13]	auto[0]	126	1			T14	1		T138	1		T126	2
all_levels[13]	auto[1]	9	1			T169	1		T206	2		T207	2
all_levels[14]	auto[0]	106	1			T12	1		T14	1		T130	1
all_levels[14]	auto[1]	18	1			T128	2		T208	1		T120	1
all_levels[15]	auto[0]	83	1			T4	2		T5	1		T10	1
all_levels[15]	auto[1]	5	1			T4	3		T209	1		T210	1
all_levels[16]	auto[0]	103	1			T10	1		T36	2		T139	1
all_levels[16]	auto[1]	7	1			T142	1		T211	2		T212	1
all_levels[17]	auto[0]	90	1			T25	1		T126	1		T140	1
all_levels[17]	auto[1]	8	1			T140	2		T61	2		T80	2
all_levels[18]	auto[0]	80	1			T40	1		T141	1		T142	1
all_levels[18]	auto[1]	2	1			T188	2		-	-		-	-
all_levels[19]	auto[0]	69	1			T5	1		T14	1		T130	1
all_levels[19]	auto[1]	11	1			T213	1		T187	1		T214	3
all_levels[20]	auto[0]	59	1			T126	1		T143	1		T141	2
all_levels[20]	auto[1]	7	1			T215	3		T56	1		T216	1
all_levels[21]	auto[0]	82	1			T33	1		T25	1		T35	1
all_levels[21]	auto[1]	14	1			T157	3		T217	1		T218	2
all_levels[22]	auto[0]	50	1			T126	1		T139	1		T129	1
all_levels[22]	auto[1]	8	1			T129	1		T219	3		T220	1
all_levels[23]	auto[0]	61	1			T12	2		T144	1		T145	1
all_levels[23]	auto[1]	13	1			T28	1		T221	4		T203	3
all_levels[24]	auto[0]	51	1			T35	1		T127	1		T139	1
all_levels[24]	auto[1]	9	1			T222	2		T223	2		T224	1
all_levels[25]	auto[0]	46	1			T142	1		T146	1		T147	2
all_levels[25]	auto[1]	2	1			T218	1		T210	1		-	-
all_levels[26]	auto[0]	38	1			T26	1		T145	1		T148	1
all_levels[26]	auto[1]	3	1			T191	2		T225	1		-	-
all_levels[27]	auto[0]	44	1			T130	1		T35	1		T145	1
all_levels[27]	auto[1]	8	1			T226	1		T197	1		T209	1
all_levels[28]	auto[0]	27	1			T126	2		T145	3		T141	1
all_levels[28]	auto[1]	2	1			T201	1		T182	1		-	-
all_levels[29]	auto[0]	35	1			T138	1		T149	1		T40	1
all_levels[29]	auto[1]	12	1			T138	1		T223	4		T204	4
all_levels[30]	auto[0]	35	1			T125	1		T126	1		T150	1
all_levels[30]	auto[1]	6	1			T175	1		T119	3		T227	1
all_levels[31]	auto[0]	36	1			T130	1		T127	1		T141	2
all_levels[31]	auto[1]	6	1			T142	3		T160	1		T228	1
all_levels[32]	auto[0]	25	1			T130	1		T150	1		T151	1
all_levels[32]	auto[1]	7	1			T152	1		T229	1		T230	3
all_levels[33]	auto[0]	22	1			T33	1		T148	1		T152	1
all_levels[33]	auto[1]	2	1			T33	1		T231	1		-	-
all_levels[34]	auto[0]	21	1			T145	1		T142	1		T153	1
all_levels[34]	auto[1]	2	1			T112	1		T232	1		-	-
all_levels[35]	auto[0]	14	1			T149	1		T142	1		T135	1
all_levels[35]	auto[1]	5	1			T142	2		T233	2		T234	1
all_levels[36]	auto[0]	25	1			T145	1		T142	1		T27	1
all_levels[36]	auto[1]	8	1			T235	1		T236	4		T89	1
all_levels[37]	auto[0]	17	1			T154	1		T152	1		T155	2
all_levels[38]	auto[0]	17	1			T148	1		T142	1		T27	1
all_levels[38]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[39]	auto[0]	11	1			T156	1		T157	1		T158	1
all_levels[40]	auto[0]	12	1			T159	1		T160	1		T161	1
all_levels[40]	auto[1]	3	1			T159	2		T160	1		-	-
all_levels[41]	auto[0]	17	1			T127	1		T145	1		T162	1
all_levels[41]	auto[1]	2	1			T214	1		T238	1		-	-
all_levels[42]	auto[0]	8	1			T131	1		T163	1		T164	1
all_levels[42]	auto[1]	3	1			T131	1		T239	2		-	-
all_levels[43]	auto[0]	14	1			T12	1		T165	1		T156	1
all_levels[44]	auto[0]	22	1			T25	1		T148	1		T27	1
all_levels[44]	auto[1]	3	1			T240	2		T241	1		-	-
all_levels[45]	auto[0]	8	1			T27	1		T166	1		T62	1
all_levels[45]	auto[1]	3	1			T166	1		T242	1		T243	1
all_levels[46]	auto[0]	14	1			T130	1		T27	1		T167	1
all_levels[46]	auto[1]	2	1			T244	2		-	-		-	-
all_levels[47]	auto[0]	9	1			T168	1		T169	1		T170	1
all_levels[47]	auto[1]	3	1			T170	2		T245	1		-	-
all_levels[48]	auto[0]	5	1			T171	1		T172	1		T173	1
all_levels[49]	auto[0]	12	1			T145	1		T174	1		T175	2
all_levels[49]	auto[1]	2	1			T175	2		-	-		-	-
all_levels[50]	auto[0]	15	1			T127	1		T152	1		T161	1
all_levels[50]	auto[1]	1	1			T173	1		-	-		-	-
all_levels[51]	auto[0]	9	1			T27	1		T160	1		T152	1
all_levels[52]	auto[0]	15	1			T149	1		T37	2		T143	1
all_levels[52]	auto[1]	1	1			T246	1		-	-		-	-
all_levels[53]	auto[0]	8	1			T176	1		T177	1		T178	1
all_levels[53]	auto[1]	2	1			T176	2		-	-		-	-
all_levels[54]	auto[0]	2	1			T152	1		T179	1		-	-
all_levels[55]	auto[0]	7	1			T152	1		T157	1		T180	1
all_levels[56]	auto[0]	6	1			T5	1		T36	1		T181	1
all_levels[56]	auto[1]	3	1			T36	3		-	-		-	-
all_levels[57]	auto[0]	7	1			T156	1		T180	1		T182	1
all_levels[58]	auto[0]	1	1			T183	1		-	-		-	-
all_levels[59]	auto[0]	7	1			T184	1		T164	1		T185	1
all_levels[59]	auto[1]	4	1			T185	3		T247	1		-	-
all_levels[60]	auto[0]	2	1			T186	1		T187	1		-	-
all_levels[61]	auto[0]	5	1			T188	1		T189	1		T190	1
all_levels[61]	auto[1]	5	1			T188	3		T248	2		-	-
all_levels[62]	auto[0]	2	1			T191	1		T192	1		-	-
all_levels[62]	auto[1]	1	1			T191	1		-	-		-	-
all_levels[63]	auto[0]	5	1			T152	1		T193	1		T171	1
all_levels[64]	auto[0]	73	1			T125	1		T26	1		T143	1
all_levels[64]	auto[1]	20	1			T160	3		T197	1		T184	2