Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99722	1			T1	1		T2	7		T3	1
all_pins[1]	99722	1			T1	1		T2	7		T3	1
all_pins[2]	99722	1			T1	1		T2	7		T3	1
all_pins[3]	99722	1			T1	1		T2	7		T3	1
all_pins[4]	99722	1			T1	1		T2	7		T3	1
all_pins[5]	99722	1			T1	1		T2	7		T3	1
all_pins[6]	99722	1			T1	1		T2	7		T3	1
all_pins[7]	99722	1			T1	1		T2	7		T3	1
all_pins[8]	99722	1			T1	1		T2	7		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	855478	1			T1	7		T2	60		T3	8
values[0x1]	42020	1			T1	2		T2	3		T3	1
transitions[0x0=>0x1]	33396	1			T1	1		T2	3		T4	5
transitions[0x1=>0x0]	33199	1			T1	1		T2	3		T3	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	79765	1			T2	7		T3	1		T5	32
all_pins[0]	values[0x1]	19957	1			T1	1		T4	4		T5	1
all_pins[0]	transitions[0x0=>0x1]	19531	1			T1	1		T4	4		T5	1
all_pins[0]	transitions[0x1=>0x0]	996	1			T5	17		T10	11		T25	3
all_pins[1]	values[0x0]	98300	1			T1	1		T2	7		T3	1
all_pins[1]	values[0x1]	1422	1			T5	17		T10	13		T12	1
all_pins[1]	transitions[0x0=>0x1]	1326	1			T5	17		T10	11		T14	8
all_pins[1]	transitions[0x1=>0x0]	1912	1			T2	1		T4	1		T10	4
all_pins[2]	values[0x0]	97714	1			T1	1		T2	6		T3	1
all_pins[2]	values[0x1]	2008	1			T2	1		T4	1		T10	6
all_pins[2]	transitions[0x0=>0x1]	1946	1			T2	1		T4	1		T10	4
all_pins[2]	transitions[0x1=>0x0]	197	1			T5	1		T14	4		T26	1
all_pins[3]	values[0x0]	99463	1			T1	1		T2	7		T3	1
all_pins[3]	values[0x1]	259	1			T5	1		T10	2		T14	5
all_pins[3]	transitions[0x0=>0x1]	220	1			T5	1		T10	2		T14	5
all_pins[3]	transitions[0x1=>0x0]	334	1			T10	10		T26	2		T249	10
all_pins[4]	values[0x0]	99349	1			T1	1		T2	7		T3	1
all_pins[4]	values[0x1]	373	1			T10	10		T26	2		T249	10
all_pins[4]	transitions[0x0=>0x1]	337	1			T10	10		T26	1		T249	8
all_pins[4]	transitions[0x1=>0x0]	120	1			T10	4		T14	3		T25	1
all_pins[5]	values[0x0]	99566	1			T1	1		T2	7		T3	1
all_pins[5]	values[0x1]	156	1			T10	4		T14	3		T25	1
all_pins[5]	transitions[0x0=>0x1]	119	1			T10	3		T14	3		T25	1
all_pins[5]	transitions[0x1=>0x0]	693	1			T10	9		T25	1		T130	1
all_pins[6]	values[0x0]	98992	1			T1	1		T2	7		T3	1
all_pins[6]	values[0x1]	730	1			T10	10		T25	1		T130	1
all_pins[6]	transitions[0x0=>0x1]	694	1			T10	10		T25	1		T130	1
all_pins[6]	transitions[0x1=>0x0]	290	1			T14	3		T25	2		T126	2
all_pins[7]	values[0x0]	99396	1			T1	1		T2	7		T3	1
all_pins[7]	values[0x1]	326	1			T14	3		T25	2		T126	2
all_pins[7]	transitions[0x0=>0x1]	174	1			T14	2		T126	2		T37	1
all_pins[7]	transitions[0x1=>0x0]	16637	1			T1	1		T2	2		T3	1
all_pins[8]	values[0x0]	82933	1			T2	5		T4	4		T5	33
all_pins[8]	values[0x1]	16789	1			T1	1		T2	2		T3	1
all_pins[8]	transitions[0x0=>0x1]	9049	1			T2	2		T8	2		T10	11
all_pins[8]	transitions[0x1=>0x0]	12020	1			T4	3		T10	7		T33	1