Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8110259	1			T2	13		T3	1		T4	5
all_levels[1]	1479452	1			T8	16095		T11	1608		T12	1
all_levels[2]	301172	1			T8	7		T10	1		T14	2
all_levels[3]	524419	1			T8	6		T14	2		T34	5
all_levels[4]	444956	1			T8	7		T32	7		T14	5
all_levels[5]	213262	1			T8	11		T34	4		T25	270
all_levels[6]	257476	1			T8	7		T12	1		T14	2
all_levels[7]	267548	1			T8	7		T34	2		T25	340
all_levels[8]	839277	1			T4	2		T8	7		T32	3
all_levels[9]	211225	1			T8	9		T34	1		T25	171
all_levels[10]	284241	1			T8	9		T10	1		T14	1
all_levels[11]	411238	1			T8	10		T34	4		T25	161
all_levels[12]	242565	1			T4	1		T8	8		T34	2
all_levels[13]	201069	1			T8	9		T14	1		T34	5
all_levels[14]	204691	1			T8	7		T34	1		T25	326
all_levels[15]	454834	1			T8	10		T34	3		T25	345
all_levels[16]	215769	1			T8	9		T34	9		T25	341
all_levels[17]	213244	1			T4	1		T8	8		T10	1
all_levels[18]	210550	1			T8	6		T14	2		T34	13
all_levels[19]	194603	1			T8	7		T14	4		T34	3
all_levels[20]	307221	1			T8	6		T34	4		T25	339
all_levels[21]	189953	1			T8	10		T10	1		T14	39
all_levels[22]	439346	1			T8	8		T10	2		T34	1
all_levels[23]	208427	1			T8	6		T10	3		T34	6
all_levels[24]	185804	1			T8	6		T10	2		T14	3
all_levels[25]	168727	1			T2	2		T8	6		T10	7
all_levels[26]	167350	1			T5	12		T8	6		T10	17
all_levels[27]	174956	1			T8	7		T34	2		T25	306
all_levels[28]	232718	1			T2	1		T4	1		T8	6
all_levels[29]	182909	1			T5	3		T8	8		T34	2
all_levels[30]	221925	1			T8	11		T33	1		T34	7
all_levels[31]	509561	1			T4	1		T8	342		T14	113
all_levels[32]	13955498	1			T2	3		T4	9		T5	9

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32222314

1

T2

18

T4

17

T5

19

auto[1]

3931

1

T2

1

T3

1

T4

3

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8108033	1			T2	12		T4	4		T5	2
all_levels[0]	auto[1]	2226	1			T2	1		T3	1		T4	1
all_levels[1]	auto[0]	1479149	1			T8	16095		T11	1608		T12	1
all_levels[1]	auto[1]	303	1			T25	1		T138	1		T36	2
all_levels[2]	auto[0]	301136	1			T8	7		T10	1		T14	2
all_levels[2]	auto[1]	36	1			T148	1		T142	2		T175	2
all_levels[3]	auto[0]	524289	1			T8	6		T14	2		T34	5
all_levels[3]	auto[1]	130	1			T149	1		T133	18		T153	1
all_levels[4]	auto[0]	444924	1			T8	7		T32	2		T14	5
all_levels[4]	auto[1]	32	1			T32	5		T127	1		T268	1
all_levels[5]	auto[0]	213239	1			T8	9		T34	4		T25	270
all_levels[5]	auto[1]	23	1			T8	2		T143	2		T336	3
all_levels[6]	auto[0]	257452	1			T8	7		T12	1		T14	2
all_levels[6]	auto[1]	24	1			T174	1		T275	1		T157	1
all_levels[7]	auto[0]	267483	1			T8	7		T34	2		T25	340
all_levels[7]	auto[1]	65	1			T133	1		T134	5		T152	1
all_levels[8]	auto[0]	839257	1			T4	2		T8	7		T32	1
all_levels[8]	auto[1]	20	1			T32	2		T129	1		T144	1
all_levels[9]	auto[0]	211200	1			T8	9		T34	1		T25	171
all_levels[9]	auto[1]	25	1			T28	1		T208	3		T315	1
all_levels[10]	auto[0]	284216	1			T8	9		T10	1		T14	1
all_levels[10]	auto[1]	25	1			T197	1		T333	1		T347	2
all_levels[11]	auto[0]	411217	1			T8	10		T34	4		T25	160
all_levels[11]	auto[1]	21	1			T25	1		T299	1		T348	1
all_levels[12]	auto[0]	242547	1			T4	1		T8	8		T34	2
all_levels[12]	auto[1]	18	1			T128	1		T160	1		T277	1
all_levels[13]	auto[0]	201045	1			T8	9		T14	1		T34	5
all_levels[13]	auto[1]	24	1			T159	1		T197	1		T166	1
all_levels[14]	auto[0]	204672	1			T8	7		T34	1		T25	326
all_levels[14]	auto[1]	19	1			T175	1		T30	1		T300	1
all_levels[15]	auto[0]	454743	1			T8	10		T34	3		T25	345
all_levels[15]	auto[1]	91	1			T174	1		T251	1		T329	17
all_levels[16]	auto[0]	215745	1			T8	9		T34	9		T25	340
all_levels[16]	auto[1]	24	1			T25	1		T199	1		T174	1
all_levels[17]	auto[0]	213223	1			T4	1		T8	8		T10	1
all_levels[17]	auto[1]	21	1			T26	1		T153	1		T169	1
all_levels[18]	auto[0]	210521	1			T8	6		T14	2		T34	12
all_levels[18]	auto[1]	29	1			T34	1		T140	1		T142	4
all_levels[19]	auto[0]	194590	1			T8	7		T14	4		T34	3
all_levels[19]	auto[1]	13	1			T197	1		T30	1		T333	1
all_levels[20]	auto[0]	307206	1			T8	6		T34	4		T25	339
all_levels[20]	auto[1]	15	1			T128	1		T159	1		T226	2
all_levels[21]	auto[0]	189934	1			T8	10		T10	1		T14	39
all_levels[21]	auto[1]	19	1			T174	2		T304	2		T310	1
all_levels[22]	auto[0]	439313	1			T8	8		T10	2		T34	1
all_levels[22]	auto[1]	33	1			T226	1		T233	1		T349	1
all_levels[23]	auto[0]	208404	1			T8	6		T10	3		T34	6
all_levels[23]	auto[1]	23	1			T195	3		T312	2		T350	2
all_levels[24]	auto[0]	185791	1			T8	6		T10	2		T14	3
all_levels[24]	auto[1]	13	1			T254	1		T300	1		T332	2
all_levels[25]	auto[0]	168699	1			T2	2		T8	6		T10	7
all_levels[25]	auto[1]	28	1			T275	2		T226	1		T152	1
all_levels[26]	auto[0]	167323	1			T5	9		T8	6		T10	17
all_levels[26]	auto[1]	27	1			T5	3		T312	3		T162	1
all_levels[27]	auto[0]	174930	1			T8	7		T34	2		T25	306
all_levels[27]	auto[1]	26	1			T37	1		T152	2		T325	1
all_levels[28]	auto[0]	232712	1			T2	1		T4	1		T8	6
all_levels[28]	auto[1]	6	1			T25	1		T187	1		T351	1
all_levels[29]	auto[0]	182888	1			T5	2		T8	8		T34	2
all_levels[29]	auto[1]	21	1			T5	1		T138	1		T175	1
all_levels[30]	auto[0]	221904	1			T8	11		T33	1		T34	6
all_levels[30]	auto[1]	21	1			T34	1		T159	3		T276	1
all_levels[31]	auto[0]	509545	1			T4	1		T8	342		T14	113
all_levels[31]	auto[1]	16	1			T128	1		T194	1		T352	1
all_levels[32]	auto[0]	13954984	1			T2	3		T4	7		T5	6
all_levels[32]	auto[1]	514	1			T4	2		T5	3		T33	2