Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	586	1			T10	7		T14	7		T25	7
all_values[1]	586	1			T10	7		T14	7		T25	7
all_values[2]	586	1			T10	7		T14	7		T25	7
all_values[3]	586	1			T10	7		T14	7		T25	7
all_values[4]	586	1			T10	7		T14	7		T25	7
all_values[5]	586	1			T10	7		T14	7		T25	7
all_values[6]	586	1			T10	7		T14	7		T25	7
all_values[7]	586	1			T10	7		T14	7		T25	7
all_values[8]	586	1			T10	7		T14	7		T25	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2807

1

T10

30

T14

32

T25

19

auto[1]

2467

1

T10

33

T14

31

T25

44

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1740

1

T10

20

T14

23

T25

28

auto[1]

3534

1

T10

43

T14

40

T25

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3122

1

T10

39

T14

38

T25

42

auto[1]

2152

1

T10

24

T14

25

T25

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	159	1			T10	3		T25	1		T26	1
all_values[0]	auto[0]	auto[1]	auto[1]	185	1			T10	1		T14	4		T25	5
all_values[0]	auto[1]	auto[0]	auto[1]	116	1			T10	1		T14	1		T25	1
all_values[0]	auto[1]	auto[1]	auto[1]	126	1			T10	2		T14	2		T26	2
all_values[1]	auto[0]	auto[0]	auto[0]	205	1			T14	3		T25	2		T26	1
all_values[1]	auto[0]	auto[1]	auto[0]	137	1			T10	3		T14	1		T25	4
all_values[1]	auto[1]	auto[0]	auto[1]	147	1			T10	1		T14	2		T26	1
all_values[1]	auto[1]	auto[1]	auto[1]	97	1			T10	3		T14	1		T25	1
all_values[2]	auto[0]	auto[0]	auto[0]	128	1			T14	1		T25	2		T26	1
all_values[2]	auto[0]	auto[0]	auto[1]	62	1			T10	1		T25	1		T27	1
all_values[2]	auto[0]	auto[1]	auto[0]	103	1			T14	4		T25	1		T135	1
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T26	1		T29	1		T136	1
all_values[2]	auto[1]	auto[0]	auto[1]	123	1			T10	4		T25	2		T26	1
all_values[2]	auto[1]	auto[1]	auto[1]	109	1			T10	2		T14	2		T25	1
all_values[3]	auto[0]	auto[0]	auto[0]	111	1			T10	1		T14	1		T25	1
all_values[3]	auto[0]	auto[0]	auto[1]	47	1			T10	3		T25	1		T27	1
all_values[3]	auto[0]	auto[1]	auto[0]	117	1			T10	1		T25	4		T27	1
all_values[3]	auto[0]	auto[1]	auto[1]	60	1			T14	1		T26	1		T27	1
all_values[3]	auto[1]	auto[0]	auto[1]	134	1			T14	2		T27	2		T124	3
all_values[3]	auto[1]	auto[1]	auto[1]	117	1			T10	2		T14	3		T25	1
all_values[4]	auto[0]	auto[0]	auto[0]	129	1			T10	2		T14	4		T25	2
all_values[4]	auto[0]	auto[0]	auto[1]	58	1			T27	1		T124	2		T29	1
all_values[4]	auto[0]	auto[1]	auto[0]	111	1			T10	3		T25	4		T27	1
all_values[4]	auto[0]	auto[1]	auto[1]	51	1			T26	1		T135	1		T136	1
all_values[4]	auto[1]	auto[0]	auto[1]	116	1			T14	1		T27	3		T124	2
all_values[4]	auto[1]	auto[1]	auto[1]	121	1			T10	2		T14	2		T25	1
all_values[5]	auto[0]	auto[0]	auto[0]	126	1			T14	1		T26	1		T27	1
all_values[5]	auto[0]	auto[0]	auto[1]	53	1			T10	1		T14	1		T25	1
all_values[5]	auto[0]	auto[1]	auto[0]	99	1			T14	1		T25	2		T27	1
all_values[5]	auto[0]	auto[1]	auto[1]	63	1			T10	4		T26	1		T135	1
all_values[5]	auto[1]	auto[0]	auto[1]	134	1			T10	1		T14	2		T25	1
all_values[5]	auto[1]	auto[1]	auto[1]	111	1			T10	1		T14	2		T25	3
all_values[6]	auto[0]	auto[0]	auto[0]	134	1			T10	3		T14	3		T26	1
all_values[6]	auto[0]	auto[0]	auto[1]	62	1			T10	2		T14	1		T26	1
all_values[6]	auto[0]	auto[1]	auto[0]	104	1			T14	1		T25	3		T26	1
all_values[6]	auto[0]	auto[1]	auto[1]	58	1			T10	1		T27	1		T124	3
all_values[6]	auto[1]	auto[0]	auto[1]	130	1			T14	2		T25	2		T26	1
all_values[6]	auto[1]	auto[1]	auto[1]	98	1			T10	1		T25	2		T27	2
all_values[7]	auto[0]	auto[0]	auto[0]	125	1			T10	5		T25	2		T26	1
all_values[7]	auto[0]	auto[0]	auto[1]	59	1			T27	1		T135	2		T124	1
all_values[7]	auto[0]	auto[1]	auto[0]	111	1			T10	2		T14	3		T25	1
all_values[7]	auto[0]	auto[1]	auto[1]	51	1			T14	2		T25	1		T29	1
all_values[7]	auto[1]	auto[0]	auto[1]	122	1			T14	1		T27	2		T135	1
all_values[7]	auto[1]	auto[1]	auto[1]	118	1			T14	1		T25	3		T27	1
all_values[8]	auto[0]	auto[0]	auto[1]	190	1			T10	1		T14	5		T26	3
all_values[8]	auto[0]	auto[1]	auto[1]	163	1			T10	2		T14	1		T25	4
all_values[8]	auto[1]	auto[0]	auto[1]	137	1			T10	1		T14	1		T26	1
all_values[8]	auto[1]	auto[1]	auto[1]	96	1			T10	3		T25	3		T27	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal