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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1225
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T1030 /workspace/coverage/default/24.uart_rx_oversample.703477058 Jul 01 06:37:26 PM PDT 24 Jul 01 06:38:15 PM PDT 24 5391743295 ps
T1031 /workspace/coverage/default/9.uart_tx_ovrd.1845371725 Jul 01 06:35:27 PM PDT 24 Jul 01 06:35:32 PM PDT 24 2678299400 ps
T1032 /workspace/coverage/default/20.uart_loopback.2165450237 Jul 01 06:36:51 PM PDT 24 Jul 01 06:36:59 PM PDT 24 3710307938 ps
T1033 /workspace/coverage/default/10.uart_fifo_full.3911336890 Jul 01 06:35:36 PM PDT 24 Jul 01 06:36:21 PM PDT 24 109234260402 ps
T1034 /workspace/coverage/default/46.uart_intr.3588472684 Jul 01 06:40:14 PM PDT 24 Jul 01 06:44:26 PM PDT 24 202315442133 ps
T1035 /workspace/coverage/default/56.uart_fifo_reset.1118499273 Jul 01 06:40:52 PM PDT 24 Jul 01 06:42:56 PM PDT 24 76364543176 ps
T1036 /workspace/coverage/default/31.uart_rx_oversample.2895678173 Jul 01 06:38:13 PM PDT 24 Jul 01 06:38:37 PM PDT 24 3344393777 ps
T1037 /workspace/coverage/default/216.uart_fifo_reset.3448051758 Jul 01 06:42:33 PM PDT 24 Jul 01 06:43:01 PM PDT 24 48492243670 ps
T1038 /workspace/coverage/default/289.uart_fifo_reset.570722459 Jul 01 06:43:12 PM PDT 24 Jul 01 06:43:56 PM PDT 24 86034010588 ps
T1039 /workspace/coverage/default/264.uart_fifo_reset.1609704006 Jul 01 06:42:53 PM PDT 24 Jul 01 06:43:14 PM PDT 24 13682077064 ps
T1040 /workspace/coverage/default/46.uart_rx_start_bit_filter.698540026 Jul 01 06:40:13 PM PDT 24 Jul 01 06:40:20 PM PDT 24 4477079352 ps
T1041 /workspace/coverage/default/48.uart_smoke.2227065455 Jul 01 06:40:34 PM PDT 24 Jul 01 06:40:37 PM PDT 24 328212731 ps
T1042 /workspace/coverage/default/14.uart_fifo_reset.4059648738 Jul 01 06:36:12 PM PDT 24 Jul 01 06:36:41 PM PDT 24 142295785385 ps
T1043 /workspace/coverage/default/247.uart_fifo_reset.3279168387 Jul 01 06:42:40 PM PDT 24 Jul 01 06:42:59 PM PDT 24 39078916671 ps
T1044 /workspace/coverage/default/10.uart_smoke.1930220196 Jul 01 06:35:25 PM PDT 24 Jul 01 06:35:35 PM PDT 24 5551614645 ps
T1045 /workspace/coverage/default/47.uart_fifo_reset.3980675137 Jul 01 06:40:22 PM PDT 24 Jul 01 06:41:32 PM PDT 24 39347767358 ps
T1046 /workspace/coverage/default/234.uart_fifo_reset.1781495638 Jul 01 06:42:41 PM PDT 24 Jul 01 06:45:01 PM PDT 24 175563824957 ps
T1047 /workspace/coverage/default/0.uart_rx_start_bit_filter.42998209 Jul 01 06:34:26 PM PDT 24 Jul 01 06:34:34 PM PDT 24 5310337794 ps
T1048 /workspace/coverage/default/17.uart_long_xfer_wo_dly.3777231333 Jul 01 06:36:35 PM PDT 24 Jul 01 06:48:31 PM PDT 24 72549025188 ps
T1049 /workspace/coverage/default/14.uart_rx_start_bit_filter.3847901488 Jul 01 06:36:12 PM PDT 24 Jul 01 06:36:15 PM PDT 24 2409017081 ps
T1050 /workspace/coverage/default/14.uart_smoke.1678714054 Jul 01 06:36:06 PM PDT 24 Jul 01 06:36:08 PM PDT 24 861701800 ps
T1051 /workspace/coverage/default/29.uart_smoke.2013886554 Jul 01 06:37:57 PM PDT 24 Jul 01 06:37:59 PM PDT 24 140294529 ps
T1052 /workspace/coverage/default/12.uart_perf.3880108838 Jul 01 06:35:52 PM PDT 24 Jul 01 06:41:44 PM PDT 24 13167769780 ps
T1053 /workspace/coverage/default/32.uart_fifo_full.4017283686 Jul 01 06:38:23 PM PDT 24 Jul 01 06:40:25 PM PDT 24 66600245680 ps
T1054 /workspace/coverage/default/0.uart_stress_all.112702066 Jul 01 06:34:30 PM PDT 24 Jul 01 06:40:27 PM PDT 24 201944225129 ps
T1055 /workspace/coverage/default/61.uart_fifo_reset.1536449795 Jul 01 06:40:59 PM PDT 24 Jul 01 06:42:38 PM PDT 24 66624901699 ps
T1056 /workspace/coverage/default/14.uart_intr.3820896583 Jul 01 06:36:05 PM PDT 24 Jul 01 06:36:17 PM PDT 24 4889413589 ps
T1057 /workspace/coverage/default/8.uart_fifo_full.2968227666 Jul 01 06:35:14 PM PDT 24 Jul 01 06:35:50 PM PDT 24 189699748310 ps
T1058 /workspace/coverage/default/36.uart_loopback.252520080 Jul 01 06:38:57 PM PDT 24 Jul 01 06:39:15 PM PDT 24 8446519285 ps
T1059 /workspace/coverage/default/19.uart_fifo_full.3993427528 Jul 01 06:36:38 PM PDT 24 Jul 01 06:36:57 PM PDT 24 43888835045 ps
T1060 /workspace/coverage/default/29.uart_loopback.1421466624 Jul 01 06:38:05 PM PDT 24 Jul 01 06:38:09 PM PDT 24 1316398957 ps
T1061 /workspace/coverage/default/46.uart_loopback.2329894489 Jul 01 06:40:19 PM PDT 24 Jul 01 06:40:25 PM PDT 24 3924764347 ps
T1062 /workspace/coverage/default/27.uart_fifo_overflow.1719952568 Jul 01 06:37:38 PM PDT 24 Jul 01 06:38:01 PM PDT 24 27529639939 ps
T1063 /workspace/coverage/default/248.uart_fifo_reset.589370165 Jul 01 06:42:40 PM PDT 24 Jul 01 06:43:27 PM PDT 24 234388629308 ps
T1064 /workspace/coverage/default/146.uart_fifo_reset.1185753930 Jul 01 06:41:52 PM PDT 24 Jul 01 06:43:25 PM PDT 24 208760876064 ps
T1065 /workspace/coverage/default/12.uart_tx_ovrd.1461296984 Jul 01 06:35:52 PM PDT 24 Jul 01 06:35:58 PM PDT 24 920869500 ps
T1066 /workspace/coverage/default/20.uart_stress_all.40664894 Jul 01 06:37:01 PM PDT 24 Jul 01 06:38:52 PM PDT 24 72990900727 ps
T1067 /workspace/coverage/default/45.uart_fifo_full.3757185086 Jul 01 06:40:05 PM PDT 24 Jul 01 06:42:08 PM PDT 24 150254432503 ps
T1068 /workspace/coverage/default/45.uart_perf.2573933537 Jul 01 06:40:12 PM PDT 24 Jul 01 06:45:30 PM PDT 24 36429664459 ps
T1069 /workspace/coverage/default/3.uart_tx_rx.743499180 Jul 01 06:34:42 PM PDT 24 Jul 01 06:38:03 PM PDT 24 80783696313 ps
T1070 /workspace/coverage/default/190.uart_fifo_reset.3617014815 Jul 01 06:42:13 PM PDT 24 Jul 01 06:43:01 PM PDT 24 36782479767 ps
T1071 /workspace/coverage/default/42.uart_rx_start_bit_filter.1395211595 Jul 01 06:39:57 PM PDT 24 Jul 01 06:40:10 PM PDT 24 7066642116 ps
T1072 /workspace/coverage/default/39.uart_intr.1028080112 Jul 01 06:39:28 PM PDT 24 Jul 01 06:40:27 PM PDT 24 37354172074 ps
T1073 /workspace/coverage/default/44.uart_smoke.3748794736 Jul 01 06:40:07 PM PDT 24 Jul 01 06:40:22 PM PDT 24 883008599 ps
T1074 /workspace/coverage/default/134.uart_fifo_reset.1205685901 Jul 01 06:41:48 PM PDT 24 Jul 01 06:42:09 PM PDT 24 23094289975 ps
T1075 /workspace/coverage/default/34.uart_fifo_reset.3912933200 Jul 01 06:38:41 PM PDT 24 Jul 01 06:40:37 PM PDT 24 79108958112 ps
T1076 /workspace/coverage/default/31.uart_intr.3763842215 Jul 01 06:38:16 PM PDT 24 Jul 01 06:40:43 PM PDT 24 204708296413 ps
T1077 /workspace/coverage/default/21.uart_rx_start_bit_filter.2048717422 Jul 01 06:37:00 PM PDT 24 Jul 01 06:37:08 PM PDT 24 3776155853 ps
T1078 /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2389812300 Jul 01 06:36:12 PM PDT 24 Jul 01 06:40:10 PM PDT 24 19674589680 ps
T1079 /workspace/coverage/default/42.uart_tx_rx.576204163 Jul 01 06:39:44 PM PDT 24 Jul 01 06:40:09 PM PDT 24 24958267783 ps
T1080 /workspace/coverage/default/32.uart_perf.544449483 Jul 01 06:38:28 PM PDT 24 Jul 01 06:54:47 PM PDT 24 16823952170 ps
T1081 /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1477808524 Jul 01 06:40:59 PM PDT 24 Jul 01 06:52:49 PM PDT 24 39749037438 ps
T1082 /workspace/coverage/default/218.uart_fifo_reset.3908646406 Jul 01 06:42:31 PM PDT 24 Jul 01 06:43:36 PM PDT 24 167589316522 ps
T1083 /workspace/coverage/default/6.uart_fifo_full.914966117 Jul 01 06:35:08 PM PDT 24 Jul 01 06:38:08 PM PDT 24 409765356698 ps
T1084 /workspace/coverage/default/169.uart_fifo_reset.1136682909 Jul 01 06:42:07 PM PDT 24 Jul 01 06:42:50 PM PDT 24 109077064732 ps
T1085 /workspace/coverage/default/2.uart_stress_all.30489292 Jul 01 06:34:37 PM PDT 24 Jul 01 06:35:22 PM PDT 24 87086378117 ps
T1086 /workspace/coverage/default/79.uart_fifo_reset.575723931 Jul 01 06:41:11 PM PDT 24 Jul 01 06:41:28 PM PDT 24 9333199485 ps
T1087 /workspace/coverage/default/29.uart_fifo_full.896848240 Jul 01 06:38:00 PM PDT 24 Jul 01 06:43:13 PM PDT 24 153899074038 ps
T1088 /workspace/coverage/default/43.uart_fifo_reset.3788217267 Jul 01 06:39:54 PM PDT 24 Jul 01 06:41:26 PM PDT 24 51998416905 ps
T1089 /workspace/coverage/default/27.uart_intr.596752386 Jul 01 06:37:47 PM PDT 24 Jul 01 06:43:22 PM PDT 24 227017868299 ps
T1090 /workspace/coverage/cover_reg_top/14.uart_intr_test.3899718457 Jul 01 04:31:06 PM PDT 24 Jul 01 04:31:21 PM PDT 24 39350021 ps
T1091 /workspace/coverage/cover_reg_top/43.uart_intr_test.619540811 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:40 PM PDT 24 16580639 ps
T1092 /workspace/coverage/cover_reg_top/31.uart_intr_test.933850737 Jul 01 04:31:10 PM PDT 24 Jul 01 04:31:24 PM PDT 24 35111752 ps
T1093 /workspace/coverage/cover_reg_top/20.uart_intr_test.1175313764 Jul 01 04:31:11 PM PDT 24 Jul 01 04:31:24 PM PDT 24 84183764 ps
T92 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1340437172 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 18977430 ps
T1094 /workspace/coverage/cover_reg_top/36.uart_intr_test.4152550212 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:40 PM PDT 24 14324293 ps
T1095 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4266885250 Jul 01 04:31:14 PM PDT 24 Jul 01 04:31:27 PM PDT 24 97155518 ps
T93 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1679701612 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 16125066 ps
T1096 /workspace/coverage/cover_reg_top/9.uart_intr_test.660050599 Jul 01 04:31:08 PM PDT 24 Jul 01 04:31:22 PM PDT 24 14642921 ps
T1097 /workspace/coverage/cover_reg_top/10.uart_tl_errors.748979910 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:23 PM PDT 24 476892317 ps
T1098 /workspace/coverage/cover_reg_top/1.uart_tl_errors.486710094 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:11 PM PDT 24 307274332 ps
T1099 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1443110315 Jul 01 04:30:56 PM PDT 24 Jul 01 04:31:06 PM PDT 24 123936875 ps
T1100 /workspace/coverage/cover_reg_top/18.uart_intr_test.3104605009 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 51071373 ps
T1101 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1121605496 Jul 01 04:31:17 PM PDT 24 Jul 01 04:31:29 PM PDT 24 40512637 ps
T1102 /workspace/coverage/cover_reg_top/8.uart_intr_test.3478718449 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:15 PM PDT 24 14079623 ps
T1103 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1946324256 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:15 PM PDT 24 144606234 ps
T1104 /workspace/coverage/cover_reg_top/32.uart_intr_test.2893469603 Jul 01 04:31:14 PM PDT 24 Jul 01 04:31:26 PM PDT 24 20564819 ps
T94 /workspace/coverage/cover_reg_top/0.uart_csr_rw.644328495 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 57004426 ps
T1105 /workspace/coverage/cover_reg_top/34.uart_intr_test.727073618 Jul 01 04:31:19 PM PDT 24 Jul 01 04:31:31 PM PDT 24 41471161 ps
T1106 /workspace/coverage/cover_reg_top/24.uart_intr_test.2246693501 Jul 01 04:31:11 PM PDT 24 Jul 01 04:31:24 PM PDT 24 11776280 ps
T101 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3371071659 Jul 01 04:31:11 PM PDT 24 Jul 01 04:31:25 PM PDT 24 72115721 ps
T95 /workspace/coverage/cover_reg_top/2.uart_csr_rw.34096183 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 27674274 ps
T1107 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.305655181 Jul 01 04:31:08 PM PDT 24 Jul 01 04:31:23 PM PDT 24 93683112 ps
T96 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2210007136 Jul 01 04:31:26 PM PDT 24 Jul 01 04:31:37 PM PDT 24 13036591 ps
T1108 /workspace/coverage/cover_reg_top/21.uart_intr_test.1985210753 Jul 01 04:31:11 PM PDT 24 Jul 01 04:31:24 PM PDT 24 16577122 ps
T97 /workspace/coverage/cover_reg_top/18.uart_csr_rw.642853908 Jul 01 04:31:13 PM PDT 24 Jul 01 04:31:26 PM PDT 24 13051336 ps
T1109 /workspace/coverage/cover_reg_top/30.uart_intr_test.562152051 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 21940910 ps
T98 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2204292003 Jul 01 04:31:00 PM PDT 24 Jul 01 04:31:12 PM PDT 24 49153399 ps
T99 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2473747176 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:17 PM PDT 24 336223602 ps
T1110 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1449362191 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 265012367 ps
T67 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1225985202 Jul 01 04:31:00 PM PDT 24 Jul 01 04:31:12 PM PDT 24 49960093 ps
T100 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3373192554 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:13 PM PDT 24 50608378 ps
T1111 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1227713361 Jul 01 04:31:00 PM PDT 24 Jul 01 04:31:14 PM PDT 24 679133831 ps
T1112 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2208204687 Jul 01 04:31:07 PM PDT 24 Jul 01 04:31:22 PM PDT 24 120146354 ps
T1113 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2089801055 Jul 01 04:30:57 PM PDT 24 Jul 01 04:31:08 PM PDT 24 99990597 ps
T1114 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2616064826 Jul 01 04:31:23 PM PDT 24 Jul 01 04:31:35 PM PDT 24 35432370 ps
T1115 /workspace/coverage/cover_reg_top/47.uart_intr_test.233717296 Jul 01 04:31:29 PM PDT 24 Jul 01 04:31:40 PM PDT 24 35391323 ps
T102 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1596863378 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:26 PM PDT 24 83184742 ps
T1116 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1851036716 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 19112413 ps
T1117 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2462855341 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:19 PM PDT 24 131286367 ps
T1118 /workspace/coverage/cover_reg_top/45.uart_intr_test.1588955712 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:39 PM PDT 24 18615948 ps
T1119 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1974147910 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:13 PM PDT 24 43293638 ps
T103 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2185449709 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:18 PM PDT 24 55078943 ps
T1120 /workspace/coverage/cover_reg_top/28.uart_intr_test.3359585413 Jul 01 04:31:10 PM PDT 24 Jul 01 04:31:23 PM PDT 24 21068080 ps
T106 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1612594844 Jul 01 04:30:57 PM PDT 24 Jul 01 04:31:08 PM PDT 24 249780909 ps
T1121 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2975033008 Jul 01 04:31:07 PM PDT 24 Jul 01 04:31:22 PM PDT 24 64764560 ps
T1122 /workspace/coverage/cover_reg_top/15.uart_intr_test.2140020407 Jul 01 04:31:09 PM PDT 24 Jul 01 04:31:23 PM PDT 24 49017580 ps
T1123 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2841090693 Jul 01 04:31:22 PM PDT 24 Jul 01 04:31:34 PM PDT 24 45508769 ps
T1124 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1315054137 Jul 01 04:31:27 PM PDT 24 Jul 01 04:31:39 PM PDT 24 21869993 ps
T1125 /workspace/coverage/cover_reg_top/42.uart_intr_test.3874637575 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:36 PM PDT 24 42045167 ps
T1126 /workspace/coverage/cover_reg_top/3.uart_tl_errors.248903824 Jul 01 04:31:05 PM PDT 24 Jul 01 04:31:20 PM PDT 24 89566569 ps
T68 /workspace/coverage/cover_reg_top/13.uart_csr_rw.369838609 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:17 PM PDT 24 11863766 ps
T1127 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4091993745 Jul 01 04:31:17 PM PDT 24 Jul 01 04:31:29 PM PDT 24 49722570 ps
T1128 /workspace/coverage/cover_reg_top/12.uart_csr_rw.530085681 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 39399643 ps
T1129 /workspace/coverage/cover_reg_top/16.uart_intr_test.3970912335 Jul 01 04:31:09 PM PDT 24 Jul 01 04:31:23 PM PDT 24 160539345 ps
T104 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3045359745 Jul 01 04:31:07 PM PDT 24 Jul 01 04:31:22 PM PDT 24 136826030 ps
T105 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1476416240 Jul 01 04:31:01 PM PDT 24 Jul 01 04:31:13 PM PDT 24 54399970 ps
T1130 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2302366025 Jul 01 04:31:13 PM PDT 24 Jul 01 04:31:26 PM PDT 24 95510582 ps
T1131 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3233762704 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:18 PM PDT 24 84722441 ps
T1132 /workspace/coverage/cover_reg_top/38.uart_intr_test.1937112975 Jul 01 04:31:23 PM PDT 24 Jul 01 04:31:35 PM PDT 24 66041668 ps
T1133 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2333767572 Jul 01 04:31:16 PM PDT 24 Jul 01 04:31:30 PM PDT 24 540967405 ps
T1134 /workspace/coverage/cover_reg_top/12.uart_intr_test.1228229672 Jul 01 04:31:15 PM PDT 24 Jul 01 04:31:27 PM PDT 24 23873255 ps
T1135 /workspace/coverage/cover_reg_top/40.uart_intr_test.941004593 Jul 01 04:31:27 PM PDT 24 Jul 01 04:31:38 PM PDT 24 25582398 ps
T69 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2020434759 Jul 01 04:31:11 PM PDT 24 Jul 01 04:31:24 PM PDT 24 77585753 ps
T1136 /workspace/coverage/cover_reg_top/29.uart_intr_test.2379317550 Jul 01 04:31:09 PM PDT 24 Jul 01 04:31:23 PM PDT 24 50804770 ps
T1137 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2635871912 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 46105968 ps
T1138 /workspace/coverage/cover_reg_top/37.uart_intr_test.126166327 Jul 01 04:31:30 PM PDT 24 Jul 01 04:31:41 PM PDT 24 148942299 ps
T1139 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4011827433 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:14 PM PDT 24 26148780 ps
T1140 /workspace/coverage/cover_reg_top/41.uart_intr_test.2442956851 Jul 01 04:31:16 PM PDT 24 Jul 01 04:31:28 PM PDT 24 12256515 ps
T1141 /workspace/coverage/cover_reg_top/5.uart_csr_rw.465105308 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 26487239 ps
T1142 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.234638077 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 32640051 ps
T1143 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1361381801 Jul 01 04:31:01 PM PDT 24 Jul 01 04:31:13 PM PDT 24 55650358 ps
T1144 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1879881957 Jul 01 04:31:00 PM PDT 24 Jul 01 04:31:12 PM PDT 24 16272300 ps
T90 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.909620868 Jul 01 04:31:01 PM PDT 24 Jul 01 04:31:13 PM PDT 24 28587211 ps
T1145 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2320410417 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:09 PM PDT 24 87592723 ps
T1146 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3540109366 Jul 01 04:31:05 PM PDT 24 Jul 01 04:31:20 PM PDT 24 299885475 ps
T137 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4173824278 Jul 01 04:31:17 PM PDT 24 Jul 01 04:31:30 PM PDT 24 196143799 ps
T70 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3519922642 Jul 01 04:31:00 PM PDT 24 Jul 01 04:31:12 PM PDT 24 49429543 ps
T1147 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.653072582 Jul 01 04:31:01 PM PDT 24 Jul 01 04:31:13 PM PDT 24 166759205 ps
T1148 /workspace/coverage/cover_reg_top/14.uart_tl_errors.827333441 Jul 01 04:31:07 PM PDT 24 Jul 01 04:31:23 PM PDT 24 689093956 ps
T1149 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3409327483 Jul 01 04:31:14 PM PDT 24 Jul 01 04:31:28 PM PDT 24 90857872 ps
T1150 /workspace/coverage/cover_reg_top/8.uart_csr_rw.719130199 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:13 PM PDT 24 24518870 ps
T1151 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2865094102 Jul 01 04:31:11 PM PDT 24 Jul 01 04:31:25 PM PDT 24 91234532 ps
T1152 /workspace/coverage/cover_reg_top/46.uart_intr_test.969012347 Jul 01 04:31:32 PM PDT 24 Jul 01 04:31:44 PM PDT 24 48970690 ps
T1153 /workspace/coverage/cover_reg_top/15.uart_tl_errors.374896469 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:19 PM PDT 24 81509705 ps
T1154 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1830459797 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:17 PM PDT 24 379382681 ps
T1155 /workspace/coverage/cover_reg_top/27.uart_intr_test.1724751056 Jul 01 04:31:14 PM PDT 24 Jul 01 04:31:27 PM PDT 24 14203601 ps
T1156 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3169253026 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:18 PM PDT 24 31907514 ps
T1157 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3594889557 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:11 PM PDT 24 25523349 ps
T71 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.787887143 Jul 01 04:31:00 PM PDT 24 Jul 01 04:31:11 PM PDT 24 55006567 ps
T1158 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1349712998 Jul 01 04:30:58 PM PDT 24 Jul 01 04:31:09 PM PDT 24 23428852 ps
T1159 /workspace/coverage/cover_reg_top/10.uart_intr_test.3130089108 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:15 PM PDT 24 12202043 ps
T1160 /workspace/coverage/cover_reg_top/3.uart_intr_test.3318849852 Jul 01 04:30:56 PM PDT 24 Jul 01 04:31:05 PM PDT 24 49131097 ps
T1161 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3016384126 Jul 01 04:31:15 PM PDT 24 Jul 01 04:31:29 PM PDT 24 443306106 ps
T1162 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3433483145 Jul 01 04:31:14 PM PDT 24 Jul 01 04:31:27 PM PDT 24 20358506 ps
T1163 /workspace/coverage/cover_reg_top/48.uart_intr_test.3787744303 Jul 01 04:31:16 PM PDT 24 Jul 01 04:31:28 PM PDT 24 28486919 ps
T107 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.11595489 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:18 PM PDT 24 298779833 ps
T1164 /workspace/coverage/cover_reg_top/7.uart_intr_test.518110878 Jul 01 04:31:07 PM PDT 24 Jul 01 04:31:22 PM PDT 24 41294540 ps
T1165 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4121462134 Jul 01 04:31:10 PM PDT 24 Jul 01 04:31:24 PM PDT 24 34675497 ps
T1166 /workspace/coverage/cover_reg_top/39.uart_intr_test.2461228067 Jul 01 04:31:16 PM PDT 24 Jul 01 04:31:28 PM PDT 24 42341914 ps
T1167 /workspace/coverage/cover_reg_top/13.uart_intr_test.3343767370 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:15 PM PDT 24 14308398 ps
T1168 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2634524407 Jul 01 04:31:24 PM PDT 24 Jul 01 04:31:36 PM PDT 24 65753102 ps
T1169 /workspace/coverage/cover_reg_top/26.uart_intr_test.2986288392 Jul 01 04:31:17 PM PDT 24 Jul 01 04:31:29 PM PDT 24 13513343 ps
T1170 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1251282999 Jul 01 04:31:05 PM PDT 24 Jul 01 04:31:19 PM PDT 24 45123407 ps
T1171 /workspace/coverage/cover_reg_top/19.uart_intr_test.2684472914 Jul 01 04:31:15 PM PDT 24 Jul 01 04:31:28 PM PDT 24 16549658 ps
T1172 /workspace/coverage/cover_reg_top/4.uart_intr_test.4062595715 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:13 PM PDT 24 11554815 ps
T1173 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1353766515 Jul 01 04:31:13 PM PDT 24 Jul 01 04:31:26 PM PDT 24 41433402 ps
T1174 /workspace/coverage/cover_reg_top/4.uart_tl_errors.716960863 Jul 01 04:30:58 PM PDT 24 Jul 01 04:31:10 PM PDT 24 26406905 ps
T108 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2804388328 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 172275062 ps
T1175 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1293042889 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:16 PM PDT 24 211346749 ps
T1176 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2997325594 Jul 01 04:31:00 PM PDT 24 Jul 01 04:31:12 PM PDT 24 59587691 ps
T72 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2751574961 Jul 01 04:31:01 PM PDT 24 Jul 01 04:31:13 PM PDT 24 53460860 ps
T1177 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.824029076 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 111977211 ps
T1178 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.825823874 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:11 PM PDT 24 48462139 ps
T109 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.540259095 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:15 PM PDT 24 247271405 ps
T1179 /workspace/coverage/cover_reg_top/25.uart_intr_test.3682712796 Jul 01 04:31:24 PM PDT 24 Jul 01 04:31:36 PM PDT 24 25751700 ps
T1180 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4232382235 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 59761057 ps
T1181 /workspace/coverage/cover_reg_top/23.uart_intr_test.2983497839 Jul 01 04:31:10 PM PDT 24 Jul 01 04:31:23 PM PDT 24 26152388 ps
T1182 /workspace/coverage/cover_reg_top/5.uart_intr_test.858881442 Jul 01 04:30:58 PM PDT 24 Jul 01 04:31:09 PM PDT 24 11900783 ps
T1183 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1596053011 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 53576131 ps
T1184 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3006768266 Jul 01 04:31:01 PM PDT 24 Jul 01 04:31:13 PM PDT 24 136473091 ps
T1185 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2156074139 Jul 01 04:30:57 PM PDT 24 Jul 01 04:31:08 PM PDT 24 129879838 ps
T1186 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2244134553 Jul 01 04:30:58 PM PDT 24 Jul 01 04:31:09 PM PDT 24 33605018 ps
T1187 /workspace/coverage/cover_reg_top/16.uart_tl_errors.498984782 Jul 01 04:31:14 PM PDT 24 Jul 01 04:31:27 PM PDT 24 58073255 ps
T1188 /workspace/coverage/cover_reg_top/33.uart_intr_test.1312196036 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:40 PM PDT 24 11903732 ps
T1189 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2672774357 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:18 PM PDT 24 30140172 ps
T1190 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2182199497 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:16 PM PDT 24 376988479 ps
T1191 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.986817293 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:17 PM PDT 24 29114268 ps
T73 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3857713888 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:15 PM PDT 24 793977765 ps
T1192 /workspace/coverage/cover_reg_top/2.uart_intr_test.2692442403 Jul 01 04:30:56 PM PDT 24 Jul 01 04:31:06 PM PDT 24 22948876 ps
T1193 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.824906028 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 16913759 ps
T1194 /workspace/coverage/cover_reg_top/17.uart_intr_test.2089581361 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 35350991 ps
T1195 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1685554502 Jul 01 04:31:13 PM PDT 24 Jul 01 04:31:26 PM PDT 24 39006313 ps
T1196 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2943389851 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:15 PM PDT 24 16077256 ps
T1197 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3664883324 Jul 01 04:31:15 PM PDT 24 Jul 01 04:31:27 PM PDT 24 145833807 ps
T91 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1039550126 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:10 PM PDT 24 17013743 ps
T1198 /workspace/coverage/cover_reg_top/11.uart_intr_test.1448390465 Jul 01 04:31:08 PM PDT 24 Jul 01 04:31:22 PM PDT 24 27502058 ps
T1199 /workspace/coverage/cover_reg_top/18.uart_tl_errors.356036016 Jul 01 04:31:13 PM PDT 24 Jul 01 04:31:26 PM PDT 24 96767899 ps
T1200 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1075122194 Jul 01 04:30:58 PM PDT 24 Jul 01 04:31:09 PM PDT 24 27757287 ps
T1201 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3081371393 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:13 PM PDT 24 62773459 ps
T1202 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.753774201 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 24603510 ps
T1203 /workspace/coverage/cover_reg_top/22.uart_intr_test.1837975428 Jul 01 04:31:13 PM PDT 24 Jul 01 04:31:26 PM PDT 24 28926827 ps
T1204 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.293321928 Jul 01 04:31:10 PM PDT 24 Jul 01 04:31:24 PM PDT 24 100863531 ps
T1205 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1863944604 Jul 01 04:31:09 PM PDT 24 Jul 01 04:31:23 PM PDT 24 104732797 ps
T1206 /workspace/coverage/cover_reg_top/0.uart_tl_errors.310761338 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 95424168 ps
T1207 /workspace/coverage/cover_reg_top/0.uart_intr_test.2341521262 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:11 PM PDT 24 146798200 ps
T1208 /workspace/coverage/cover_reg_top/35.uart_intr_test.4048326783 Jul 01 04:31:15 PM PDT 24 Jul 01 04:31:28 PM PDT 24 41541629 ps
T1209 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2817388327 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:16 PM PDT 24 96319616 ps
T1210 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1793981764 Jul 01 04:30:57 PM PDT 24 Jul 01 04:31:07 PM PDT 24 17643461 ps
T1211 /workspace/coverage/cover_reg_top/1.uart_intr_test.1099022456 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:11 PM PDT 24 24640947 ps
T1212 /workspace/coverage/cover_reg_top/6.uart_tl_errors.4037590799 Jul 01 04:31:15 PM PDT 24 Jul 01 04:31:29 PM PDT 24 312632018 ps
T1213 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3870416677 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:11 PM PDT 24 728102138 ps
T1214 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2196889488 Jul 01 04:30:58 PM PDT 24 Jul 01 04:31:09 PM PDT 24 16542969 ps
T1215 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3573693514 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 11970247 ps
T74 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1899644267 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:15 PM PDT 24 17528202 ps
T1216 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3961603596 Jul 01 04:30:57 PM PDT 24 Jul 01 04:31:09 PM PDT 24 62479556 ps
T1217 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.398999543 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:13 PM PDT 24 18390067 ps
T1218 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3178201476 Jul 01 04:31:00 PM PDT 24 Jul 01 04:31:12 PM PDT 24 99870206 ps
T1219 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.47263532 Jul 01 04:31:03 PM PDT 24 Jul 01 04:31:15 PM PDT 24 23665637 ps
T1220 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1685255626 Jul 01 04:31:04 PM PDT 24 Jul 01 04:31:18 PM PDT 24 167338371 ps
T1221 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2214007887 Jul 01 04:31:12 PM PDT 24 Jul 01 04:31:25 PM PDT 24 79335016 ps
T1222 /workspace/coverage/cover_reg_top/6.uart_intr_test.1308773993 Jul 01 04:31:08 PM PDT 24 Jul 01 04:31:22 PM PDT 24 15064558 ps
T1223 /workspace/coverage/cover_reg_top/44.uart_intr_test.3507766170 Jul 01 04:31:15 PM PDT 24 Jul 01 04:31:28 PM PDT 24 27955871 ps
T1224 /workspace/coverage/cover_reg_top/49.uart_intr_test.1271364718 Jul 01 04:31:31 PM PDT 24 Jul 01 04:31:42 PM PDT 24 13789389 ps
T1225 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2262322102 Jul 01 04:31:02 PM PDT 24 Jul 01 04:31:15 PM PDT 24 52638943 ps

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.908536117
Short name T8
Test name
Test status
Simulation time 33853206138 ps
CPU time 184.13 seconds
Started Jul 01 06:40:08 PM PDT 24
Finished Jul 01 06:43:20 PM PDT 24
Peak memory 216188 kb
Host smart-30fce365-fe87-4224-b04c-255417b7055b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908536117 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.908536117
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1733619230
Short name T14
Test name
Test status
Simulation time 137720987801 ps
CPU time 470.36 seconds
Started Jul 01 06:40:58 PM PDT 24
Finished Jul 01 06:48:49 PM PDT 24
Peak memory 216632 kb
Host smart-850c2825-b0be-45e2-acee-6e16146bc700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733619230 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1733619230
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2529513750
Short name T26
Test name
Test status
Simulation time 155192715592 ps
CPU time 921.38 seconds
Started Jul 01 06:37:47 PM PDT 24
Finished Jul 01 06:53:10 PM PDT 24
Peak memory 216528 kb
Host smart-1ccdfd63-8dba-4dc9-a5af-5903c28b0b7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529513750 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2529513750
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.253289301
Short name T27
Test name
Test status
Simulation time 142632211973 ps
CPU time 425.66 seconds
Started Jul 01 06:41:12 PM PDT 24
Finished Jul 01 06:48:20 PM PDT 24
Peak memory 211772 kb
Host smart-c6325e1d-4b28-470d-956c-e63c04ce7449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253289301 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.253289301
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1299567190
Short name T152
Test name
Test status
Simulation time 250620364905 ps
CPU time 415.94 seconds
Started Jul 01 06:38:14 PM PDT 24
Finished Jul 01 06:45:13 PM PDT 24
Peak memory 216528 kb
Host smart-d9317394-b419-4c59-863a-72096e8fbe3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299567190 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1299567190
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.327655337
Short name T131
Test name
Test status
Simulation time 268578301401 ps
CPU time 1105.7 seconds
Started Jul 01 06:39:44 PM PDT 24
Finished Jul 01 06:58:17 PM PDT 24
Peak memory 199952 kb
Host smart-78c4e3c0-2f37-4d20-b4a9-8d4f353874ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327655337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.327655337
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all.2591881575
Short name T135
Test name
Test status
Simulation time 311917714569 ps
CPU time 853.22 seconds
Started Jul 01 06:38:06 PM PDT 24
Finished Jul 01 06:52:22 PM PDT 24
Peak memory 200040 kb
Host smart-252688a8-3314-4b57-bfa6-364a8a4c97f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591881575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2591881575
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3554808160
Short name T30
Test name
Test status
Simulation time 184034258891 ps
CPU time 791.64 seconds
Started Jul 01 06:41:23 PM PDT 24
Finished Jul 01 06:54:36 PM PDT 24
Peak memory 215616 kb
Host smart-83c0e696-8743-47cd-88f4-77581c8eb09b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554808160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3554808160
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3450476842
Short name T40
Test name
Test status
Simulation time 148691511976 ps
CPU time 76.52 seconds
Started Jul 01 06:37:19 PM PDT 24
Finished Jul 01 06:38:37 PM PDT 24
Peak memory 200056 kb
Host smart-6f6de8c3-7a1a-416d-8fb0-85f330df345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450476842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3450476842
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1596863378
Short name T102
Test name
Test status
Simulation time 83184742 ps
CPU time 1.26 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:26 PM PDT 24
Peak memory 199712 kb
Host smart-725948a6-3155-49b8-8bfc-bfe0b56aab35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596863378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1596863378
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.378776864
Short name T197
Test name
Test status
Simulation time 427650149231 ps
CPU time 58.56 seconds
Started Jul 01 06:40:58 PM PDT 24
Finished Jul 01 06:41:58 PM PDT 24
Peak memory 200032 kb
Host smart-4a37d6e7-221b-4b3d-9420-c872d44fcf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378776864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.378776864
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2842001749
Short name T20
Test name
Test status
Simulation time 13459497 ps
CPU time 0.56 seconds
Started Jul 01 06:36:07 PM PDT 24
Finished Jul 01 06:36:08 PM PDT 24
Peak memory 195312 kb
Host smart-b9f2b66e-caea-4393-a500-b11dd3649f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842001749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2842001749
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.601401955
Short name T5
Test name
Test status
Simulation time 18284044159 ps
CPU time 25.78 seconds
Started Jul 01 06:41:20 PM PDT 24
Finished Jul 01 06:41:48 PM PDT 24
Peak memory 200044 kb
Host smart-577ccf71-e7ad-46d0-8260-e721c1ef1d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601401955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.601401955
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.795856942
Short name T52
Test name
Test status
Simulation time 61509074240 ps
CPU time 506.76 seconds
Started Jul 01 06:41:29 PM PDT 24
Finished Jul 01 06:49:57 PM PDT 24
Peak memory 216524 kb
Host smart-7b2da6d3-081c-4953-90ba-6fe3e403952e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795856942 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.795856942
Directory /workspace/99.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2748875332
Short name T266
Test name
Test status
Simulation time 167838063013 ps
CPU time 607.88 seconds
Started Jul 01 06:36:14 PM PDT 24
Finished Jul 01 06:46:23 PM PDT 24
Peak memory 199948 kb
Host smart-ac5f3678-67fa-4fa7-bb82-00590f881969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748875332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2748875332
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3493194487
Short name T228
Test name
Test status
Simulation time 145225614219 ps
CPU time 424.44 seconds
Started Jul 01 06:43:25 PM PDT 24
Finished Jul 01 06:50:30 PM PDT 24
Peak memory 199572 kb
Host smart-fab1f6c0-4931-42d6-870e-554f9f70ced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493194487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3493194487
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.4059343795
Short name T159
Test name
Test status
Simulation time 207841904257 ps
CPU time 80.47 seconds
Started Jul 01 06:43:02 PM PDT 24
Finished Jul 01 06:44:25 PM PDT 24
Peak memory 200116 kb
Host smart-8112a360-0347-41e3-a4c7-2d221fa12d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059343795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.4059343795
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.1087151664
Short name T254
Test name
Test status
Simulation time 249442230921 ps
CPU time 86.61 seconds
Started Jul 01 06:40:22 PM PDT 24
Finished Jul 01 06:41:51 PM PDT 24
Peak memory 199624 kb
Host smart-cd583a40-023d-4cb0-afaa-5ff57db4e885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087151664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1087151664
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1498136762
Short name T111
Test name
Test status
Simulation time 119601857 ps
CPU time 0.76 seconds
Started Jul 01 06:34:27 PM PDT 24
Finished Jul 01 06:34:32 PM PDT 24
Peak memory 218352 kb
Host smart-c50332f4-6f88-43f0-af09-a21abe282302
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498136762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1498136762
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.475640887
Short name T29
Test name
Test status
Simulation time 271739815314 ps
CPU time 553.88 seconds
Started Jul 01 06:38:15 PM PDT 24
Finished Jul 01 06:47:32 PM PDT 24
Peak memory 216524 kb
Host smart-a4fb2fcc-3373-47a4-9ab6-78dec3018ed6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475640887 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.475640887
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3898425169
Short name T327
Test name
Test status
Simulation time 41585136473 ps
CPU time 28 seconds
Started Jul 01 06:38:42 PM PDT 24
Finished Jul 01 06:39:12 PM PDT 24
Peak memory 199948 kb
Host smart-ef88c2c0-0424-4b39-937a-b4c09934e45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898425169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3898425169
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1225985202
Short name T67
Test name
Test status
Simulation time 49960093 ps
CPU time 0.62 seconds
Started Jul 01 04:31:00 PM PDT 24
Finished Jul 01 04:31:12 PM PDT 24
Peak memory 196096 kb
Host smart-c6e5150f-7570-4e55-9c0e-fe6db0a29db3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225985202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1225985202
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1735516229
Short name T194
Test name
Test status
Simulation time 174018645023 ps
CPU time 344.83 seconds
Started Jul 01 06:42:21 PM PDT 24
Finished Jul 01 06:48:07 PM PDT 24
Peak memory 200096 kb
Host smart-d11f3e86-d1d9-4c21-8c5b-f9defc2f0167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735516229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1735516229
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all.29373645
Short name T46
Test name
Test status
Simulation time 149489977373 ps
CPU time 69.53 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:40:46 PM PDT 24
Peak memory 199980 kb
Host smart-5e3fe143-9745-44f3-9fee-8905a3e9878c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29373645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.29373645
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3966490129
Short name T34
Test name
Test status
Simulation time 98630849110 ps
CPU time 265.2 seconds
Started Jul 01 06:41:12 PM PDT 24
Finished Jul 01 06:45:39 PM PDT 24
Peak memory 199960 kb
Host smart-d562762c-4236-47df-9b11-6d7ae7812865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966490129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3966490129
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3752491873
Short name T267
Test name
Test status
Simulation time 129325875466 ps
CPU time 126.66 seconds
Started Jul 01 06:39:56 PM PDT 24
Finished Jul 01 06:42:06 PM PDT 24
Peak memory 199936 kb
Host smart-4edc942d-b817-4b65-8278-cb66313362d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752491873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3752491873
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_stress_all.2100923519
Short name T164
Test name
Test status
Simulation time 537804790464 ps
CPU time 714.81 seconds
Started Jul 01 06:36:43 PM PDT 24
Finished Jul 01 06:48:38 PM PDT 24
Peak memory 200104 kb
Host smart-cad218a0-3635-4305-bc14-62b1d7fc481d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100923519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2100923519
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2305927230
Short name T127
Test name
Test status
Simulation time 110797313043 ps
CPU time 42.8 seconds
Started Jul 01 06:40:50 PM PDT 24
Finished Jul 01 06:41:34 PM PDT 24
Peak memory 199996 kb
Host smart-c4f79299-c50b-49a7-a6ac-e9216a006282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305927230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2305927230
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.1473807376
Short name T390
Test name
Test status
Simulation time 108451092388 ps
CPU time 722.36 seconds
Started Jul 01 06:38:41 PM PDT 24
Finished Jul 01 06:50:45 PM PDT 24
Peak memory 199968 kb
Host smart-8b532d00-aebc-4b4a-b929-47dbaa62bbdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473807376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1473807376
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2119809309
Short name T156
Test name
Test status
Simulation time 99869194736 ps
CPU time 202.51 seconds
Started Jul 01 06:38:07 PM PDT 24
Finished Jul 01 06:41:32 PM PDT 24
Peak memory 199944 kb
Host smart-5806eb2e-3f65-4039-9010-96420a6033fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119809309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2119809309
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1192402931
Short name T175
Test name
Test status
Simulation time 18423644434 ps
CPU time 37.74 seconds
Started Jul 01 06:41:18 PM PDT 24
Finished Jul 01 06:41:57 PM PDT 24
Peak memory 199984 kb
Host smart-b649d120-82b5-4cbf-81fc-713f4c8e46d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192402931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1192402931
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1193186201
Short name T337
Test name
Test status
Simulation time 120441510023 ps
CPU time 962.21 seconds
Started Jul 01 06:41:00 PM PDT 24
Finished Jul 01 06:57:05 PM PDT 24
Peak memory 216508 kb
Host smart-d5f03b7a-5e47-41db-a4e8-a52cfa1b178f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193186201 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1193186201
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3660950523
Short name T25
Test name
Test status
Simulation time 81256964173 ps
CPU time 938.27 seconds
Started Jul 01 06:41:21 PM PDT 24
Finished Jul 01 06:57:01 PM PDT 24
Peak memory 216456 kb
Host smart-0f4d20bc-49eb-49de-a629-a693978459e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660950523 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3660950523
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3870416677
Short name T1213
Test name
Test status
Simulation time 728102138 ps
CPU time 1.24 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 199616 kb
Host smart-2db91e54-eea9-423c-85a0-93ba481c6749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870416677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3870416677
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2406124013
Short name T169
Test name
Test status
Simulation time 118322715410 ps
CPU time 185.17 seconds
Started Jul 01 06:42:55 PM PDT 24
Finished Jul 01 06:46:02 PM PDT 24
Peak memory 200004 kb
Host smart-34dbdea8-85fd-4868-a92c-5fb6eeb074bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406124013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2406124013
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4291312994
Short name T142
Test name
Test status
Simulation time 125532413831 ps
CPU time 188.43 seconds
Started Jul 01 06:42:19 PM PDT 24
Finished Jul 01 06:45:29 PM PDT 24
Peak memory 200000 kb
Host smart-c01ef238-b16f-47c1-aa8e-0169cab6fe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291312994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4291312994
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3213100747
Short name T167
Test name
Test status
Simulation time 119359806771 ps
CPU time 121.62 seconds
Started Jul 01 06:35:00 PM PDT 24
Finished Jul 01 06:37:04 PM PDT 24
Peak memory 199884 kb
Host smart-7ab11b21-2389-4aa1-b1f9-14e2f2c1e9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213100747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3213100747
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3414959962
Short name T191
Test name
Test status
Simulation time 19802245580 ps
CPU time 18.41 seconds
Started Jul 01 06:40:48 PM PDT 24
Finished Jul 01 06:41:08 PM PDT 24
Peak memory 200008 kb
Host smart-98f72bbd-2bae-4066-88c9-50129ba30c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414959962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3414959962
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.475691246
Short name T237
Test name
Test status
Simulation time 16269992179 ps
CPU time 23.87 seconds
Started Jul 01 06:41:46 PM PDT 24
Finished Jul 01 06:42:12 PM PDT 24
Peak memory 199888 kb
Host smart-b7b2d35f-29df-46a4-8e5a-939564a49858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475691246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.475691246
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2601319696
Short name T187
Test name
Test status
Simulation time 133038362826 ps
CPU time 223.28 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:45:52 PM PDT 24
Peak memory 199904 kb
Host smart-436c6525-1b76-433b-b094-dbd4eab7e5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601319696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2601319696
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.658621840
Short name T176
Test name
Test status
Simulation time 65606001332 ps
CPU time 52.44 seconds
Started Jul 01 06:40:48 PM PDT 24
Finished Jul 01 06:41:42 PM PDT 24
Peak memory 199932 kb
Host smart-cad21512-6c1f-4136-98b9-23fa648012d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658621840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.658621840
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1446368372
Short name T41
Test name
Test status
Simulation time 114646775673 ps
CPU time 981.91 seconds
Started Jul 01 06:41:00 PM PDT 24
Finished Jul 01 06:57:25 PM PDT 24
Peak memory 216564 kb
Host smart-f70a22ae-7225-4977-8f60-41077297a1bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446368372 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1446368372
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3487829905
Short name T188
Test name
Test status
Simulation time 27644463512 ps
CPU time 48.17 seconds
Started Jul 01 06:41:21 PM PDT 24
Finished Jul 01 06:42:11 PM PDT 24
Peak memory 200116 kb
Host smart-e831dbe8-ef23-4b80-9cda-17a72d68c9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487829905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3487829905
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3308377572
Short name T564
Test name
Test status
Simulation time 200539351702 ps
CPU time 1756.53 seconds
Started Jul 01 06:41:32 PM PDT 24
Finished Jul 01 07:10:50 PM PDT 24
Peak memory 224672 kb
Host smart-76727c95-0bdc-4b28-95cc-05e92d51e3d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308377572 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3308377572
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.114954427
Short name T508
Test name
Test status
Simulation time 115050245412 ps
CPU time 1509.52 seconds
Started Jul 01 06:36:59 PM PDT 24
Finished Jul 01 07:02:09 PM PDT 24
Peak memory 216508 kb
Host smart-1ea2486f-9d1e-46d5-94fd-ce20ed40836f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114954427 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.114954427
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2131582757
Short name T243
Test name
Test status
Simulation time 32628899151 ps
CPU time 51.85 seconds
Started Jul 01 06:38:14 PM PDT 24
Finished Jul 01 06:39:09 PM PDT 24
Peak memory 199952 kb
Host smart-703abd92-6cf6-4b5a-91bd-bdb71833778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131582757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2131582757
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1230141650
Short name T173
Test name
Test status
Simulation time 127112089919 ps
CPU time 26.55 seconds
Started Jul 01 06:40:58 PM PDT 24
Finished Jul 01 06:41:26 PM PDT 24
Peak memory 199948 kb
Host smart-4a96a7d1-233b-455c-bbac-183180b6751d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230141650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1230141650
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.325727844
Short name T349
Test name
Test status
Simulation time 39485213398 ps
CPU time 27.85 seconds
Started Jul 01 06:34:23 PM PDT 24
Finished Jul 01 06:34:57 PM PDT 24
Peak memory 200004 kb
Host smart-0732a293-1479-42fb-8c11-004cfcc9ffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325727844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.325727844
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2579071411
Short name T10
Test name
Test status
Simulation time 55704713736 ps
CPU time 528.6 seconds
Started Jul 01 06:35:46 PM PDT 24
Finished Jul 01 06:44:37 PM PDT 24
Peak memory 216496 kb
Host smart-4ae9193e-f600-4dcf-a150-756d2fab21a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579071411 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2579071411
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3825874208
Short name T420
Test name
Test status
Simulation time 106923623096 ps
CPU time 98.71 seconds
Started Jul 01 06:41:46 PM PDT 24
Finished Jul 01 06:43:26 PM PDT 24
Peak memory 200040 kb
Host smart-aaa16415-73cf-42eb-8e76-9362e585ee18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825874208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3825874208
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2572978655
Short name T214
Test name
Test status
Simulation time 51824451506 ps
CPU time 13.55 seconds
Started Jul 01 06:41:52 PM PDT 24
Finished Jul 01 06:42:08 PM PDT 24
Peak memory 200104 kb
Host smart-3a223817-129e-47a5-9126-59dd304afefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572978655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2572978655
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3425601483
Short name T128
Test name
Test status
Simulation time 21226231440 ps
CPU time 18.81 seconds
Started Jul 01 06:42:06 PM PDT 24
Finished Jul 01 06:42:26 PM PDT 24
Peak memory 200000 kb
Host smart-e68d9898-f695-4559-b2d5-cbb5fce9dbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425601483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3425601483
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2695455855
Short name T203
Test name
Test status
Simulation time 240833086449 ps
CPU time 27.43 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:43:02 PM PDT 24
Peak memory 200008 kb
Host smart-2c8f1b90-7005-495e-bc65-2adfe77c4fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695455855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2695455855
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.946305156
Short name T183
Test name
Test status
Simulation time 87253981424 ps
CPU time 35.31 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:43:10 PM PDT 24
Peak memory 200104 kb
Host smart-920abf09-17d1-4360-96b4-efc60544dca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946305156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.946305156
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1832828136
Short name T210
Test name
Test status
Simulation time 36655779549 ps
CPU time 15.99 seconds
Started Jul 01 06:42:31 PM PDT 24
Finished Jul 01 06:42:48 PM PDT 24
Peak memory 199984 kb
Host smart-2798d1df-6720-453b-9ade-9edab531774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832828136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1832828136
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1368915267
Short name T223
Test name
Test status
Simulation time 150081792974 ps
CPU time 33.36 seconds
Started Jul 01 06:42:47 PM PDT 24
Finished Jul 01 06:43:22 PM PDT 24
Peak memory 199952 kb
Host smart-41cd174a-db1a-48de-8e74-894cb6ef4bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368915267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1368915267
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_perf.1828466665
Short name T314
Test name
Test status
Simulation time 15146751541 ps
CPU time 139.04 seconds
Started Jul 01 06:35:08 PM PDT 24
Finished Jul 01 06:37:29 PM PDT 24
Peak memory 199908 kb
Host smart-7477b5ec-d24a-4ee8-ba65-ade44f10d71b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828466665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1828466665
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3441390850
Short name T244
Test name
Test status
Simulation time 58913513539 ps
CPU time 25.25 seconds
Started Jul 01 06:35:33 PM PDT 24
Finished Jul 01 06:35:59 PM PDT 24
Peak memory 199940 kb
Host smart-06ac889c-621d-4eb7-91ef-4e7a973182da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441390850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3441390850
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2227778453
Short name T33
Test name
Test status
Simulation time 69683245923 ps
CPU time 86.2 seconds
Started Jul 01 06:41:28 PM PDT 24
Finished Jul 01 06:42:56 PM PDT 24
Peak memory 199936 kb
Host smart-d7f33a52-8f75-413d-8815-bf7bea562043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227778453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2227778453
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1167479677
Short name T950
Test name
Test status
Simulation time 39232926292 ps
CPU time 16.83 seconds
Started Jul 01 06:41:30 PM PDT 24
Finished Jul 01 06:41:48 PM PDT 24
Peak memory 200068 kb
Host smart-c0a04169-cedf-4762-ade7-0f21f4404910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167479677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1167479677
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.881487436
Short name T247
Test name
Test status
Simulation time 36421035245 ps
CPU time 50.2 seconds
Started Jul 01 06:41:38 PM PDT 24
Finished Jul 01 06:42:30 PM PDT 24
Peak memory 199912 kb
Host smart-38ea95fd-32e0-49a9-b888-ceedbf784870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881487436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.881487436
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3700241562
Short name T80
Test name
Test status
Simulation time 14905231974 ps
CPU time 11.35 seconds
Started Jul 01 06:41:45 PM PDT 24
Finished Jul 01 06:41:58 PM PDT 24
Peak memory 199956 kb
Host smart-06a90b07-1ead-435b-8b19-981553403236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700241562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3700241562
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2650007699
Short name T999
Test name
Test status
Simulation time 86349553897 ps
CPU time 153.95 seconds
Started Jul 01 06:36:13 PM PDT 24
Finished Jul 01 06:38:49 PM PDT 24
Peak memory 199960 kb
Host smart-c0d5775e-8659-4f4f-aea6-574d859de419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650007699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2650007699
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3527716878
Short name T112
Test name
Test status
Simulation time 60454833900 ps
CPU time 25.9 seconds
Started Jul 01 06:42:19 PM PDT 24
Finished Jul 01 06:42:46 PM PDT 24
Peak memory 199940 kb
Host smart-7959285d-d7bc-405f-a5e2-996217dc08d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527716878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3527716878
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2150584061
Short name T235
Test name
Test status
Simulation time 29119067189 ps
CPU time 45.1 seconds
Started Jul 01 06:42:24 PM PDT 24
Finished Jul 01 06:43:11 PM PDT 24
Peak memory 200032 kb
Host smart-d7479027-f926-4e9c-987a-ad5e3f47ecc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150584061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2150584061
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1724998572
Short name T36
Test name
Test status
Simulation time 60494256871 ps
CPU time 83.93 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:43:59 PM PDT 24
Peak memory 200032 kb
Host smart-464fa78b-f417-4b78-9368-b61cf8e3b0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724998572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1724998572
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2729446543
Short name T182
Test name
Test status
Simulation time 109204271998 ps
CPU time 84.92 seconds
Started Jul 01 06:42:33 PM PDT 24
Finished Jul 01 06:44:00 PM PDT 24
Peak memory 199976 kb
Host smart-3e696c32-6787-4bb2-a7c3-12e84627ef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729446543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2729446543
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2032926749
Short name T170
Test name
Test status
Simulation time 129972347612 ps
CPU time 151.81 seconds
Started Jul 01 06:42:42 PM PDT 24
Finished Jul 01 06:45:15 PM PDT 24
Peak memory 200004 kb
Host smart-4727f93a-fa24-4f17-aa46-91a2f5911287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032926749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2032926749
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2191266359
Short name T246
Test name
Test status
Simulation time 53917787051 ps
CPU time 103.9 seconds
Started Jul 01 06:42:55 PM PDT 24
Finished Jul 01 06:44:40 PM PDT 24
Peak memory 199900 kb
Host smart-fcf7ad71-d988-48f3-bd33-e715bf8b78e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191266359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2191266359
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2644005877
Short name T241
Test name
Test status
Simulation time 59530519852 ps
CPU time 25.07 seconds
Started Jul 01 06:39:33 PM PDT 24
Finished Jul 01 06:39:59 PM PDT 24
Peak memory 200132 kb
Host smart-d6e13e2a-8d0a-493d-81e4-54e19ef18732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644005877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2644005877
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2089801055
Short name T1113
Test name
Test status
Simulation time 99990597 ps
CPU time 0.79 seconds
Started Jul 01 04:30:57 PM PDT 24
Finished Jul 01 04:31:08 PM PDT 24
Peak memory 196556 kb
Host smart-50f1fe60-b822-43e7-b642-b2aa848597c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089801055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2089801055
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2156074139
Short name T1185
Test name
Test status
Simulation time 129879838 ps
CPU time 1.44 seconds
Started Jul 01 04:30:57 PM PDT 24
Finished Jul 01 04:31:08 PM PDT 24
Peak memory 198428 kb
Host smart-bd6a9318-d55f-427d-873f-97a018ef8249
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156074139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2156074139
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.398999543
Short name T1217
Test name
Test status
Simulation time 18390067 ps
CPU time 0.67 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 195728 kb
Host smart-6210bb13-3314-46c7-a256-774d70c831fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398999543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.398999543
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.47263532
Short name T1219
Test name
Test status
Simulation time 23665637 ps
CPU time 1.12 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 200144 kb
Host smart-dfbb91ce-8782-4a4d-b7ef-f486a2136c83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47263532 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.47263532
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.644328495
Short name T94
Test name
Test status
Simulation time 57004426 ps
CPU time 0.58 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 195764 kb
Host smart-512e2970-56e3-4b3d-85c0-0a0842d14a8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644328495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.644328495
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2341521262
Short name T1207
Test name
Test status
Simulation time 146798200 ps
CPU time 0.57 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 194704 kb
Host smart-f0d4f17a-ab0e-4cf6-b436-33a85f7a810e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341521262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2341521262
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2473747176
Short name T99
Test name
Test status
Simulation time 336223602 ps
CPU time 0.72 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:17 PM PDT 24
Peak memory 197048 kb
Host smart-6bf65a24-8276-42b6-906a-b2d2782ab054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473747176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2473747176
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.310761338
Short name T1206
Test name
Test status
Simulation time 95424168 ps
CPU time 1.27 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 200360 kb
Host smart-91e8ec76-d084-4ab6-be7f-c5bf2318c52b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310761338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.310761338
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.653072582
Short name T1147
Test name
Test status
Simulation time 166759205 ps
CPU time 1.33 seconds
Started Jul 01 04:31:01 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 199632 kb
Host smart-65aa380c-0e2e-4a35-abe8-6113dad1d18d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653072582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.653072582
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2751574961
Short name T72
Test name
Test status
Simulation time 53460860 ps
CPU time 0.79 seconds
Started Jul 01 04:31:01 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 196700 kb
Host smart-71eff310-3192-4349-8c8e-5dac102c25c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751574961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2751574961
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3006768266
Short name T1184
Test name
Test status
Simulation time 136473091 ps
CPU time 1.55 seconds
Started Jul 01 04:31:01 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 198088 kb
Host smart-e359956f-0460-454e-ac63-6f860bf9f0da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006768266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3006768266
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2244134553
Short name T1186
Test name
Test status
Simulation time 33605018 ps
CPU time 0.57 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 195428 kb
Host smart-0565e088-19ad-45ff-9922-2392ddfa03da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244134553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2244134553
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1793981764
Short name T1210
Test name
Test status
Simulation time 17643461 ps
CPU time 0.66 seconds
Started Jul 01 04:30:57 PM PDT 24
Finished Jul 01 04:31:07 PM PDT 24
Peak memory 198060 kb
Host smart-e4f22fc2-8f87-44a8-b251-ed85b69c5e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793981764 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1793981764
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3519922642
Short name T70
Test name
Test status
Simulation time 49429543 ps
CPU time 0.58 seconds
Started Jul 01 04:31:00 PM PDT 24
Finished Jul 01 04:31:12 PM PDT 24
Peak memory 195712 kb
Host smart-1c0b7f8e-0924-48e7-9dc5-b81765952911
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519922642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3519922642
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1099022456
Short name T1211
Test name
Test status
Simulation time 24640947 ps
CPU time 0.61 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 194712 kb
Host smart-a8c0f2b9-49fc-44d7-a68d-ec0390354302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099022456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1099022456
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2204292003
Short name T98
Test name
Test status
Simulation time 49153399 ps
CPU time 0.62 seconds
Started Jul 01 04:31:00 PM PDT 24
Finished Jul 01 04:31:12 PM PDT 24
Peak memory 197116 kb
Host smart-9f59b347-cae7-4ae1-95d8-3c918897621d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204292003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2204292003
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.486710094
Short name T1098
Test name
Test status
Simulation time 307274332 ps
CPU time 1.63 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 200684 kb
Host smart-6f0413ef-7106-409f-9dad-6f562092260a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486710094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.486710094
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1612594844
Short name T106
Test name
Test status
Simulation time 249780909 ps
CPU time 1.25 seconds
Started Jul 01 04:30:57 PM PDT 24
Finished Jul 01 04:31:08 PM PDT 24
Peak memory 199628 kb
Host smart-fa5a0405-f7a5-4be7-8bf9-18d61ef76632
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612594844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1612594844
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3081371393
Short name T1201
Test name
Test status
Simulation time 62773459 ps
CPU time 0.86 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 200196 kb
Host smart-0e0ecbaf-8c0d-4e17-9cee-0652b9bef4ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081371393 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3081371393
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2943389851
Short name T1196
Test name
Test status
Simulation time 16077256 ps
CPU time 0.69 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 196344 kb
Host smart-a7817e6e-45ee-454a-92cc-4e669ab90d1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943389851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2943389851
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3130089108
Short name T1159
Test name
Test status
Simulation time 12202043 ps
CPU time 0.58 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 194696 kb
Host smart-75a0b5bc-967e-4fcb-8eac-b0da39d571c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130089108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3130089108
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.986817293
Short name T1191
Test name
Test status
Simulation time 29114268 ps
CPU time 0.75 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:17 PM PDT 24
Peak memory 197252 kb
Host smart-c57deb9d-e343-4732-b0eb-29d4a42d5f13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986817293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.986817293
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.748979910
Short name T1097
Test name
Test status
Simulation time 476892317 ps
CPU time 2.18 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:23 PM PDT 24
Peak memory 200468 kb
Host smart-61a72bc5-4246-4dff-a45d-24b7afdb405f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748979910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.748979910
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3233762704
Short name T1131
Test name
Test status
Simulation time 84722441 ps
CPU time 1.27 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:18 PM PDT 24
Peak memory 199548 kb
Host smart-e0d4b861-53cc-4a45-a0be-532ee7fd6054
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233762704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3233762704
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3178201476
Short name T1218
Test name
Test status
Simulation time 99870206 ps
CPU time 0.76 seconds
Started Jul 01 04:31:00 PM PDT 24
Finished Jul 01 04:31:12 PM PDT 24
Peak memory 199132 kb
Host smart-0303496f-6720-4e76-ad72-b0dc0a24146f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178201476 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3178201476
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2635871912
Short name T1137
Test name
Test status
Simulation time 46105968 ps
CPU time 0.64 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 195692 kb
Host smart-eb578e18-cecb-4eaf-a627-1107d9bedf5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635871912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2635871912
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1448390465
Short name T1198
Test name
Test status
Simulation time 27502058 ps
CPU time 0.58 seconds
Started Jul 01 04:31:08 PM PDT 24
Finished Jul 01 04:31:22 PM PDT 24
Peak memory 194856 kb
Host smart-3f129ef0-8903-4c4a-8538-12aa6e56a885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448390465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1448390465
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3169253026
Short name T1156
Test name
Test status
Simulation time 31907514 ps
CPU time 0.77 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:18 PM PDT 24
Peak memory 197260 kb
Host smart-77ae2ada-9acb-4691-94a9-3e65669dc3e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169253026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3169253026
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1293042889
Short name T1175
Test name
Test status
Simulation time 211346749 ps
CPU time 2.27 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 200616 kb
Host smart-570f86fe-0f27-4a8c-a12e-0a9a77b931b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293042889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1293042889
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.11595489
Short name T107
Test name
Test status
Simulation time 298779833 ps
CPU time 1.29 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:18 PM PDT 24
Peak memory 199632 kb
Host smart-f5e3eb1a-1580-4c66-855d-fd81a250208f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11595489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.11595489
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3664883324
Short name T1197
Test name
Test status
Simulation time 145833807 ps
CPU time 0.82 seconds
Started Jul 01 04:31:15 PM PDT 24
Finished Jul 01 04:31:27 PM PDT 24
Peak memory 200080 kb
Host smart-1f74ac04-c74c-438f-b7b5-644fdf4bf443
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664883324 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3664883324
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.530085681
Short name T1128
Test name
Test status
Simulation time 39399643 ps
CPU time 0.59 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 195796 kb
Host smart-fb3de65a-640a-49ab-832a-788aefd4e849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530085681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.530085681
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1228229672
Short name T1134
Test name
Test status
Simulation time 23873255 ps
CPU time 0.55 seconds
Started Jul 01 04:31:15 PM PDT 24
Finished Jul 01 04:31:27 PM PDT 24
Peak memory 194692 kb
Host smart-2cef5812-6176-4913-8f70-c0867f516e13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228229672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1228229672
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2616064826
Short name T1114
Test name
Test status
Simulation time 35432370 ps
CPU time 0.77 seconds
Started Jul 01 04:31:23 PM PDT 24
Finished Jul 01 04:31:35 PM PDT 24
Peak memory 197812 kb
Host smart-622848e0-854e-47a5-a8fd-548a5ed88988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616064826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2616064826
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1449362191
Short name T1110
Test name
Test status
Simulation time 265012367 ps
CPU time 1.02 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 200132 kb
Host smart-84343928-ab4b-41a6-8459-a16551bffa8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449362191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1449362191
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.293321928
Short name T1204
Test name
Test status
Simulation time 100863531 ps
CPU time 0.89 seconds
Started Jul 01 04:31:10 PM PDT 24
Finished Jul 01 04:31:24 PM PDT 24
Peak memory 199196 kb
Host smart-eddf5372-24bf-4b94-8e12-b8532a68f747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293321928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.293321928
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.824906028
Short name T1193
Test name
Test status
Simulation time 16913759 ps
CPU time 0.82 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 200160 kb
Host smart-57d89d46-f1eb-400e-aaa9-23fd8856e58c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824906028 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.824906028
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.369838609
Short name T68
Test name
Test status
Simulation time 11863766 ps
CPU time 0.6 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:17 PM PDT 24
Peak memory 195736 kb
Host smart-929d47e7-5234-4ffe-9f24-30eb9c7dda6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369838609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.369838609
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3343767370
Short name T1167
Test name
Test status
Simulation time 14308398 ps
CPU time 0.58 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 194612 kb
Host smart-01dfa475-fad2-4248-aa5e-a499f489e933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343767370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3343767370
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1340437172
Short name T92
Test name
Test status
Simulation time 18977430 ps
CPU time 0.77 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 197544 kb
Host smart-1a629a7f-419c-4301-be45-573a0265918b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340437172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1340437172
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1830459797
Short name T1154
Test name
Test status
Simulation time 379382681 ps
CPU time 1.98 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:17 PM PDT 24
Peak memory 200436 kb
Host smart-2d7ce435-1e50-43e4-a808-ac2eb484e6ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830459797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1830459797
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2182199497
Short name T1190
Test name
Test status
Simulation time 376988479 ps
CPU time 1.26 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 199704 kb
Host smart-b893354b-deed-45d6-a88d-4331aeaae21a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182199497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2182199497
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2208204687
Short name T1112
Test name
Test status
Simulation time 120146354 ps
CPU time 0.69 seconds
Started Jul 01 04:31:07 PM PDT 24
Finished Jul 01 04:31:22 PM PDT 24
Peak memory 198128 kb
Host smart-9fdb2272-c476-40d6-9ed7-825eb8d8e324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208204687 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2208204687
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2020434759
Short name T69
Test name
Test status
Simulation time 77585753 ps
CPU time 0.6 seconds
Started Jul 01 04:31:11 PM PDT 24
Finished Jul 01 04:31:24 PM PDT 24
Peak memory 195840 kb
Host smart-3a1eb499-e9f9-40ca-929f-0eaf0f46a6f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020434759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2020434759
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3899718457
Short name T1090
Test name
Test status
Simulation time 39350021 ps
CPU time 0.56 seconds
Started Jul 01 04:31:06 PM PDT 24
Finished Jul 01 04:31:21 PM PDT 24
Peak memory 194724 kb
Host smart-616fd072-9119-4e96-b5f6-31b5edc62061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899718457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3899718457
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1353766515
Short name T1173
Test name
Test status
Simulation time 41433402 ps
CPU time 0.7 seconds
Started Jul 01 04:31:13 PM PDT 24
Finished Jul 01 04:31:26 PM PDT 24
Peak memory 197232 kb
Host smart-1db3b482-9ba5-4cd9-a417-9df17a661fd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353766515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1353766515
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.827333441
Short name T1148
Test name
Test status
Simulation time 689093956 ps
CPU time 2.23 seconds
Started Jul 01 04:31:07 PM PDT 24
Finished Jul 01 04:31:23 PM PDT 24
Peak memory 200488 kb
Host smart-6eb374d9-a620-4519-ae4c-f442b725ef19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827333441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.827333441
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3371071659
Short name T101
Test name
Test status
Simulation time 72115721 ps
CPU time 1.18 seconds
Started Jul 01 04:31:11 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 199620 kb
Host smart-990c71d7-c675-43cf-bc31-811a986da079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371071659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3371071659
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3433483145
Short name T1162
Test name
Test status
Simulation time 20358506 ps
CPU time 1.01 seconds
Started Jul 01 04:31:14 PM PDT 24
Finished Jul 01 04:31:27 PM PDT 24
Peak memory 200104 kb
Host smart-e66181ac-02fb-48ad-9591-d242f391feff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433483145 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3433483145
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3573693514
Short name T1215
Test name
Test status
Simulation time 11970247 ps
CPU time 0.61 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 195796 kb
Host smart-2a17a595-5275-4352-a014-191db7f5e9c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573693514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3573693514
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2140020407
Short name T1122
Test name
Test status
Simulation time 49017580 ps
CPU time 0.57 seconds
Started Jul 01 04:31:09 PM PDT 24
Finished Jul 01 04:31:23 PM PDT 24
Peak memory 194668 kb
Host smart-3bafe6d1-41c2-4632-b03c-e91f35de31c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140020407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2140020407
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2634524407
Short name T1168
Test name
Test status
Simulation time 65753102 ps
CPU time 0.74 seconds
Started Jul 01 04:31:24 PM PDT 24
Finished Jul 01 04:31:36 PM PDT 24
Peak memory 196324 kb
Host smart-b082a50f-763c-4a6d-9c14-c35d80dd4715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634524407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2634524407
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.374896469
Short name T1153
Test name
Test status
Simulation time 81509705 ps
CPU time 1.99 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:19 PM PDT 24
Peak memory 200360 kb
Host smart-1a929e4a-9318-4c2f-a41d-38bcbe205ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374896469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.374896469
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1863944604
Short name T1205
Test name
Test status
Simulation time 104732797 ps
CPU time 0.86 seconds
Started Jul 01 04:31:09 PM PDT 24
Finished Jul 01 04:31:23 PM PDT 24
Peak memory 198944 kb
Host smart-e61fbfd9-e394-43a2-a1e1-0c1463eb6216
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863944604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1863944604
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1121605496
Short name T1101
Test name
Test status
Simulation time 40512637 ps
CPU time 0.74 seconds
Started Jul 01 04:31:17 PM PDT 24
Finished Jul 01 04:31:29 PM PDT 24
Peak memory 199384 kb
Host smart-8b452b03-634f-4e19-8604-4eb036dfe37f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121605496 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1121605496
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2210007136
Short name T96
Test name
Test status
Simulation time 13036591 ps
CPU time 0.64 seconds
Started Jul 01 04:31:26 PM PDT 24
Finished Jul 01 04:31:37 PM PDT 24
Peak memory 195880 kb
Host smart-b455a0ac-4209-4d6a-b327-ddb37f409e1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210007136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2210007136
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3970912335
Short name T1129
Test name
Test status
Simulation time 160539345 ps
CPU time 0.63 seconds
Started Jul 01 04:31:09 PM PDT 24
Finished Jul 01 04:31:23 PM PDT 24
Peak memory 194784 kb
Host smart-9611feb7-ae49-4cec-bc23-3597c984aa2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970912335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3970912335
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2841090693
Short name T1123
Test name
Test status
Simulation time 45508769 ps
CPU time 0.65 seconds
Started Jul 01 04:31:22 PM PDT 24
Finished Jul 01 04:31:34 PM PDT 24
Peak memory 196216 kb
Host smart-55370794-c42a-4060-a726-c2883f9a7942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841090693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2841090693
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.498984782
Short name T1187
Test name
Test status
Simulation time 58073255 ps
CPU time 1.4 seconds
Started Jul 01 04:31:14 PM PDT 24
Finished Jul 01 04:31:27 PM PDT 24
Peak memory 200368 kb
Host smart-4efe5bcd-9523-48f7-8844-79954fa6810b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498984782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.498984782
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2804388328
Short name T108
Test name
Test status
Simulation time 172275062 ps
CPU time 0.93 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 199464 kb
Host smart-031bd359-623a-401a-9c63-24b3da987005
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804388328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2804388328
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4266885250
Short name T1095
Test name
Test status
Simulation time 97155518 ps
CPU time 0.79 seconds
Started Jul 01 04:31:14 PM PDT 24
Finished Jul 01 04:31:27 PM PDT 24
Peak memory 198692 kb
Host smart-d2e95464-66b0-44d1-b8fe-a473c5e16b92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266885250 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4266885250
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1685554502
Short name T1195
Test name
Test status
Simulation time 39006313 ps
CPU time 0.59 seconds
Started Jul 01 04:31:13 PM PDT 24
Finished Jul 01 04:31:26 PM PDT 24
Peak memory 195804 kb
Host smart-ecf45e8f-eb45-4a89-a017-466bfb2ef980
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685554502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1685554502
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2089581361
Short name T1194
Test name
Test status
Simulation time 35350991 ps
CPU time 0.55 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 194704 kb
Host smart-8b3a382b-13fd-428d-8c99-a116292d1a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089581361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2089581361
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2302366025
Short name T1130
Test name
Test status
Simulation time 95510582 ps
CPU time 0.75 seconds
Started Jul 01 04:31:13 PM PDT 24
Finished Jul 01 04:31:26 PM PDT 24
Peak memory 197260 kb
Host smart-7451dd21-1bf1-4312-b9cb-447166b866d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302366025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2302366025
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3016384126
Short name T1161
Test name
Test status
Simulation time 443306106 ps
CPU time 1.41 seconds
Started Jul 01 04:31:15 PM PDT 24
Finished Jul 01 04:31:29 PM PDT 24
Peak memory 200032 kb
Host smart-39ed2861-710b-4020-a366-c78560de7086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016384126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3016384126
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4173824278
Short name T137
Test name
Test status
Simulation time 196143799 ps
CPU time 1.42 seconds
Started Jul 01 04:31:17 PM PDT 24
Finished Jul 01 04:31:30 PM PDT 24
Peak memory 199768 kb
Host smart-fbb44905-5575-465d-92e0-e9ab1a5a73f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173824278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4173824278
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4091993745
Short name T1127
Test name
Test status
Simulation time 49722570 ps
CPU time 0.8 seconds
Started Jul 01 04:31:17 PM PDT 24
Finished Jul 01 04:31:29 PM PDT 24
Peak memory 199948 kb
Host smart-5c516022-fd2f-4207-9f1e-16ea3cb2af0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091993745 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.4091993745
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.642853908
Short name T97
Test name
Test status
Simulation time 13051336 ps
CPU time 0.63 seconds
Started Jul 01 04:31:13 PM PDT 24
Finished Jul 01 04:31:26 PM PDT 24
Peak memory 195840 kb
Host smart-21c45a16-e674-4162-9d1c-7637a2aa10e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642853908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.642853908
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3104605009
Short name T1100
Test name
Test status
Simulation time 51071373 ps
CPU time 0.58 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 194648 kb
Host smart-fc6608ee-736f-4403-8b12-fc08b50403f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104605009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3104605009
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1596053011
Short name T1183
Test name
Test status
Simulation time 53576131 ps
CPU time 0.64 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 196224 kb
Host smart-261b0fe9-8041-41bb-931f-6cabeb2ca216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596053011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1596053011
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.356036016
Short name T1199
Test name
Test status
Simulation time 96767899 ps
CPU time 1.19 seconds
Started Jul 01 04:31:13 PM PDT 24
Finished Jul 01 04:31:26 PM PDT 24
Peak memory 200292 kb
Host smart-5682db38-83fc-4dea-a8f9-0443d63aebd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356036016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.356036016
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.753774201
Short name T1202
Test name
Test status
Simulation time 24603510 ps
CPU time 0.73 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 198600 kb
Host smart-aca7c19f-cb41-4a78-ab67-3dfa6769cc6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753774201 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.753774201
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1315054137
Short name T1124
Test name
Test status
Simulation time 21869993 ps
CPU time 0.64 seconds
Started Jul 01 04:31:27 PM PDT 24
Finished Jul 01 04:31:39 PM PDT 24
Peak memory 195908 kb
Host smart-141b15b1-7c31-4a97-82e6-ef1be52d7d4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315054137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1315054137
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2684472914
Short name T1171
Test name
Test status
Simulation time 16549658 ps
CPU time 0.61 seconds
Started Jul 01 04:31:15 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 194404 kb
Host smart-4cf57e48-cc09-47bc-a0e9-a6d072291c2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684472914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2684472914
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2214007887
Short name T1221
Test name
Test status
Simulation time 79335016 ps
CPU time 0.72 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 197356 kb
Host smart-a239f674-db75-47f5-80b9-aeebb9654077
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214007887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2214007887
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2333767572
Short name T1133
Test name
Test status
Simulation time 540967405 ps
CPU time 2.15 seconds
Started Jul 01 04:31:16 PM PDT 24
Finished Jul 01 04:31:30 PM PDT 24
Peak memory 200316 kb
Host smart-83cd40ec-86df-4526-9356-f57287e0156c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333767572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2333767572
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2865094102
Short name T1151
Test name
Test status
Simulation time 91234532 ps
CPU time 0.93 seconds
Started Jul 01 04:31:11 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 199312 kb
Host smart-e5f14247-3def-4ec3-bfd8-b31ef062487a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865094102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2865094102
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1899644267
Short name T74
Test name
Test status
Simulation time 17528202 ps
CPU time 0.78 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 197204 kb
Host smart-dfc4244a-729b-48bf-b802-6bb18e8f7257
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899644267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1899644267
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3857713888
Short name T73
Test name
Test status
Simulation time 793977765 ps
CPU time 2.51 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 197632 kb
Host smart-b35026d6-a84f-4653-bf12-c98d722acacb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857713888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3857713888
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.787887143
Short name T71
Test name
Test status
Simulation time 55006567 ps
CPU time 0.62 seconds
Started Jul 01 04:31:00 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 195900 kb
Host smart-0fe50929-b092-48d5-9a22-f8ba49c23b1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787887143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.787887143
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1443110315
Short name T1099
Test name
Test status
Simulation time 123936875 ps
CPU time 0.81 seconds
Started Jul 01 04:30:56 PM PDT 24
Finished Jul 01 04:31:06 PM PDT 24
Peak memory 200076 kb
Host smart-e66569db-23ab-4ca7-98f6-d1496eebb601
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443110315 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1443110315
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.34096183
Short name T95
Test name
Test status
Simulation time 27674274 ps
CPU time 0.58 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 195696 kb
Host smart-267d3ccf-8e4b-4e26-96ab-c51532358680
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34096183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.34096183
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2692442403
Short name T1192
Test name
Test status
Simulation time 22948876 ps
CPU time 0.55 seconds
Started Jul 01 04:30:56 PM PDT 24
Finished Jul 01 04:31:06 PM PDT 24
Peak memory 194696 kb
Host smart-0788019a-228f-4564-a8b6-40672ad08883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692442403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2692442403
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1251282999
Short name T1170
Test name
Test status
Simulation time 45123407 ps
CPU time 0.63 seconds
Started Jul 01 04:31:05 PM PDT 24
Finished Jul 01 04:31:19 PM PDT 24
Peak memory 196156 kb
Host smart-380b6139-71b6-4cd7-a9b7-acd949ff8849
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251282999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1251282999
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3540109366
Short name T1146
Test name
Test status
Simulation time 299885475 ps
CPU time 2.35 seconds
Started Jul 01 04:31:05 PM PDT 24
Finished Jul 01 04:31:20 PM PDT 24
Peak memory 200368 kb
Host smart-be123d05-38e5-42df-8c86-8f625df7ea8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540109366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3540109366
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.540259095
Short name T109
Test name
Test status
Simulation time 247271405 ps
CPU time 1.22 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 199548 kb
Host smart-0c3d357b-f0fd-44a4-ba40-55f323d1fe97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540259095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.540259095
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1175313764
Short name T1093
Test name
Test status
Simulation time 84183764 ps
CPU time 0.6 seconds
Started Jul 01 04:31:11 PM PDT 24
Finished Jul 01 04:31:24 PM PDT 24
Peak memory 194988 kb
Host smart-5890967b-e1af-4a65-bb15-dcdb74edd458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175313764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1175313764
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1985210753
Short name T1108
Test name
Test status
Simulation time 16577122 ps
CPU time 0.6 seconds
Started Jul 01 04:31:11 PM PDT 24
Finished Jul 01 04:31:24 PM PDT 24
Peak memory 194912 kb
Host smart-5d628894-2605-4ed8-b07f-b164f5171477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985210753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1985210753
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1837975428
Short name T1203
Test name
Test status
Simulation time 28926827 ps
CPU time 0.56 seconds
Started Jul 01 04:31:13 PM PDT 24
Finished Jul 01 04:31:26 PM PDT 24
Peak memory 194680 kb
Host smart-9841d0ba-be49-4e7d-bbc2-9b6f57d68c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837975428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1837975428
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2983497839
Short name T1181
Test name
Test status
Simulation time 26152388 ps
CPU time 0.59 seconds
Started Jul 01 04:31:10 PM PDT 24
Finished Jul 01 04:31:23 PM PDT 24
Peak memory 194712 kb
Host smart-b8182f57-64c6-4862-976f-64dd4917effe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983497839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2983497839
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2246693501
Short name T1106
Test name
Test status
Simulation time 11776280 ps
CPU time 0.61 seconds
Started Jul 01 04:31:11 PM PDT 24
Finished Jul 01 04:31:24 PM PDT 24
Peak memory 194704 kb
Host smart-8cb5eb29-f48e-483e-99ff-5e1a99465759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246693501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2246693501
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3682712796
Short name T1179
Test name
Test status
Simulation time 25751700 ps
CPU time 0.61 seconds
Started Jul 01 04:31:24 PM PDT 24
Finished Jul 01 04:31:36 PM PDT 24
Peak memory 194820 kb
Host smart-107c14a7-8c68-4c54-9225-017465d215b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682712796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3682712796
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2986288392
Short name T1169
Test name
Test status
Simulation time 13513343 ps
CPU time 0.58 seconds
Started Jul 01 04:31:17 PM PDT 24
Finished Jul 01 04:31:29 PM PDT 24
Peak memory 194712 kb
Host smart-02256b74-ba93-4f40-917b-4a6d95b6c93b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986288392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2986288392
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1724751056
Short name T1155
Test name
Test status
Simulation time 14203601 ps
CPU time 0.6 seconds
Started Jul 01 04:31:14 PM PDT 24
Finished Jul 01 04:31:27 PM PDT 24
Peak memory 194612 kb
Host smart-664620f1-8718-4314-b249-5f6ab71c5a11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724751056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1724751056
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3359585413
Short name T1120
Test name
Test status
Simulation time 21068080 ps
CPU time 0.6 seconds
Started Jul 01 04:31:10 PM PDT 24
Finished Jul 01 04:31:23 PM PDT 24
Peak memory 194680 kb
Host smart-3edff4f0-c256-49db-8269-651b14a113d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359585413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3359585413
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2379317550
Short name T1136
Test name
Test status
Simulation time 50804770 ps
CPU time 0.59 seconds
Started Jul 01 04:31:09 PM PDT 24
Finished Jul 01 04:31:23 PM PDT 24
Peak memory 194740 kb
Host smart-112fb1fb-2f09-4f26-90dc-8f5b6c2e9756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379317550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2379317550
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.909620868
Short name T90
Test name
Test status
Simulation time 28587211 ps
CPU time 0.78 seconds
Started Jul 01 04:31:01 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 196572 kb
Host smart-5b81d268-efa9-442b-9d0d-29a37bab6ab9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909620868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.909620868
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3961603596
Short name T1216
Test name
Test status
Simulation time 62479556 ps
CPU time 1.41 seconds
Started Jul 01 04:30:57 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 198092 kb
Host smart-c9385e98-d20e-4d5b-b274-71150f906800
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961603596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3961603596
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1879881957
Short name T1144
Test name
Test status
Simulation time 16272300 ps
CPU time 0.65 seconds
Started Jul 01 04:31:00 PM PDT 24
Finished Jul 01 04:31:12 PM PDT 24
Peak memory 195716 kb
Host smart-26d36ea6-07e2-41ad-b50f-1c1567ff586c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879881957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1879881957
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2320410417
Short name T1145
Test name
Test status
Simulation time 87592723 ps
CPU time 1.12 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 200392 kb
Host smart-2031bc88-2a51-4fd9-a670-a00d64884ff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320410417 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2320410417
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3318849852
Short name T1160
Test name
Test status
Simulation time 49131097 ps
CPU time 0.58 seconds
Started Jul 01 04:30:56 PM PDT 24
Finished Jul 01 04:31:05 PM PDT 24
Peak memory 194704 kb
Host smart-46831206-0ee1-484a-9f2b-55c1a875653c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318849852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3318849852
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2997325594
Short name T1176
Test name
Test status
Simulation time 59587691 ps
CPU time 0.74 seconds
Started Jul 01 04:31:00 PM PDT 24
Finished Jul 01 04:31:12 PM PDT 24
Peak memory 197392 kb
Host smart-f200f5b8-c19d-4fcb-bf16-7ecd2f1c94f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997325594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2997325594
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.248903824
Short name T1126
Test name
Test status
Simulation time 89566569 ps
CPU time 1.62 seconds
Started Jul 01 04:31:05 PM PDT 24
Finished Jul 01 04:31:20 PM PDT 24
Peak memory 200352 kb
Host smart-f038cc0b-a624-4348-a72a-dd8b425eb8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248903824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.248903824
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1476416240
Short name T105
Test name
Test status
Simulation time 54399970 ps
CPU time 0.96 seconds
Started Jul 01 04:31:01 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 199416 kb
Host smart-2d4cf192-2e04-4041-ad70-b105bafb44b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476416240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1476416240
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.562152051
Short name T1109
Test name
Test status
Simulation time 21940910 ps
CPU time 0.62 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 194776 kb
Host smart-cfabb2a6-9560-4b2b-9fde-8323b928a85b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562152051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.562152051
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.933850737
Short name T1092
Test name
Test status
Simulation time 35111752 ps
CPU time 0.61 seconds
Started Jul 01 04:31:10 PM PDT 24
Finished Jul 01 04:31:24 PM PDT 24
Peak memory 194876 kb
Host smart-d0f2c984-fde2-45f7-acf1-beb375351dcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933850737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.933850737
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2893469603
Short name T1104
Test name
Test status
Simulation time 20564819 ps
CPU time 0.57 seconds
Started Jul 01 04:31:14 PM PDT 24
Finished Jul 01 04:31:26 PM PDT 24
Peak memory 194680 kb
Host smart-d310f028-c617-4774-95a3-b14e4e950897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893469603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2893469603
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1312196036
Short name T1188
Test name
Test status
Simulation time 11903732 ps
CPU time 0.57 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:40 PM PDT 24
Peak memory 194632 kb
Host smart-dfa20adc-8ff1-4b18-a5ca-a4d424a19f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312196036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1312196036
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.727073618
Short name T1105
Test name
Test status
Simulation time 41471161 ps
CPU time 0.55 seconds
Started Jul 01 04:31:19 PM PDT 24
Finished Jul 01 04:31:31 PM PDT 24
Peak memory 194636 kb
Host smart-1d42ac0c-4766-46e1-aab0-bcff0d62c09e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727073618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.727073618
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.4048326783
Short name T1208
Test name
Test status
Simulation time 41541629 ps
CPU time 0.59 seconds
Started Jul 01 04:31:15 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 194692 kb
Host smart-0ffb27ce-f7d4-48cf-a908-579cfff5545b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048326783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4048326783
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.4152550212
Short name T1094
Test name
Test status
Simulation time 14324293 ps
CPU time 0.57 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:40 PM PDT 24
Peak memory 194784 kb
Host smart-c64593c2-03ae-4fcd-8e7f-caaa0a76b608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152550212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.4152550212
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.126166327
Short name T1138
Test name
Test status
Simulation time 148942299 ps
CPU time 0.57 seconds
Started Jul 01 04:31:30 PM PDT 24
Finished Jul 01 04:31:41 PM PDT 24
Peak memory 194684 kb
Host smart-2e612810-5274-41fb-9119-7ade3fa18795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126166327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.126166327
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1937112975
Short name T1132
Test name
Test status
Simulation time 66041668 ps
CPU time 0.61 seconds
Started Jul 01 04:31:23 PM PDT 24
Finished Jul 01 04:31:35 PM PDT 24
Peak memory 194828 kb
Host smart-fb3d0d01-5cad-4620-a124-283ecb1103cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937112975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1937112975
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2461228067
Short name T1166
Test name
Test status
Simulation time 42341914 ps
CPU time 0.6 seconds
Started Jul 01 04:31:16 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 194864 kb
Host smart-cb1cce88-fdc2-4e97-96d2-69e7410de06e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461228067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2461228067
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4011827433
Short name T1139
Test name
Test status
Simulation time 26148780 ps
CPU time 0.68 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:14 PM PDT 24
Peak memory 195708 kb
Host smart-86698b6a-3f0b-4e86-9a6a-661c8d76d493
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011827433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.4011827433
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1227713361
Short name T1111
Test name
Test status
Simulation time 679133831 ps
CPU time 2.61 seconds
Started Jul 01 04:31:00 PM PDT 24
Finished Jul 01 04:31:14 PM PDT 24
Peak memory 198532 kb
Host smart-61f4309b-0bbf-4cfc-9f1b-120e99aeed28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227713361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1227713361
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1075122194
Short name T1200
Test name
Test status
Simulation time 27757287 ps
CPU time 0.61 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 195700 kb
Host smart-4ef27b82-3929-4d2c-8c88-3df8867077e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075122194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1075122194
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1946324256
Short name T1103
Test name
Test status
Simulation time 144606234 ps
CPU time 0.83 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 200140 kb
Host smart-caf119e6-5d2d-48ef-9114-428eb982b046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946324256 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1946324256
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1039550126
Short name T91
Test name
Test status
Simulation time 17013743 ps
CPU time 0.63 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:10 PM PDT 24
Peak memory 195768 kb
Host smart-9fa13865-29c0-4bbe-886b-2f8d2457e124
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039550126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1039550126
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4062595715
Short name T1172
Test name
Test status
Simulation time 11554815 ps
CPU time 0.61 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 194720 kb
Host smart-05364f8d-fb39-44d7-90b1-2822ce96f631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062595715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4062595715
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1349712998
Short name T1158
Test name
Test status
Simulation time 23428852 ps
CPU time 0.77 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 197208 kb
Host smart-91e94f8c-69ba-4581-9424-4bfe8d504de9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349712998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1349712998
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.716960863
Short name T1174
Test name
Test status
Simulation time 26406905 ps
CPU time 1.33 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:10 PM PDT 24
Peak memory 200168 kb
Host smart-02b817e1-17bf-49a3-80be-33634363eaf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716960863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.716960863
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.941004593
Short name T1135
Test name
Test status
Simulation time 25582398 ps
CPU time 0.57 seconds
Started Jul 01 04:31:27 PM PDT 24
Finished Jul 01 04:31:38 PM PDT 24
Peak memory 194640 kb
Host smart-d279d5db-7f9b-433b-b1c2-2b33df2e5f33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941004593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.941004593
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2442956851
Short name T1140
Test name
Test status
Simulation time 12256515 ps
CPU time 0.57 seconds
Started Jul 01 04:31:16 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 194776 kb
Host smart-75252b3e-c329-4b67-84a8-50a24de3cb38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442956851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2442956851
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3874637575
Short name T1125
Test name
Test status
Simulation time 42045167 ps
CPU time 0.56 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:36 PM PDT 24
Peak memory 194704 kb
Host smart-50729a96-1697-416d-8b30-c862e1f0b816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874637575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3874637575
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.619540811
Short name T1091
Test name
Test status
Simulation time 16580639 ps
CPU time 0.58 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:40 PM PDT 24
Peak memory 194988 kb
Host smart-3e3bd316-14bf-4c67-a5fc-fa9896496706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619540811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.619540811
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3507766170
Short name T1223
Test name
Test status
Simulation time 27955871 ps
CPU time 0.61 seconds
Started Jul 01 04:31:15 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 194812 kb
Host smart-ba2dceb4-944b-4637-8995-cbe1144ad1bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507766170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3507766170
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1588955712
Short name T1118
Test name
Test status
Simulation time 18615948 ps
CPU time 0.57 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:39 PM PDT 24
Peak memory 194780 kb
Host smart-2316891d-a7e3-4244-b87d-b19880eeb3ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588955712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1588955712
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.969012347
Short name T1152
Test name
Test status
Simulation time 48970690 ps
CPU time 0.62 seconds
Started Jul 01 04:31:32 PM PDT 24
Finished Jul 01 04:31:44 PM PDT 24
Peak memory 194760 kb
Host smart-c1651793-26d6-4f2b-aa2d-4a187d94825e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969012347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.969012347
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.233717296
Short name T1115
Test name
Test status
Simulation time 35391323 ps
CPU time 0.57 seconds
Started Jul 01 04:31:29 PM PDT 24
Finished Jul 01 04:31:40 PM PDT 24
Peak memory 194684 kb
Host smart-e3ea2ff8-2163-4a7a-94ae-ce0271bd3f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233717296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.233717296
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3787744303
Short name T1163
Test name
Test status
Simulation time 28486919 ps
CPU time 0.59 seconds
Started Jul 01 04:31:16 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 194776 kb
Host smart-0451ceae-3e1c-424e-944d-ee9fe603010f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787744303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3787744303
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1271364718
Short name T1224
Test name
Test status
Simulation time 13789389 ps
CPU time 0.55 seconds
Started Jul 01 04:31:31 PM PDT 24
Finished Jul 01 04:31:42 PM PDT 24
Peak memory 194740 kb
Host smart-6ff8a246-d1ee-4e78-8c31-6f4740129b2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271364718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1271364718
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1851036716
Short name T1116
Test name
Test status
Simulation time 19112413 ps
CPU time 0.85 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 200168 kb
Host smart-adb28a29-65ed-4859-91cd-625e965cf694
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851036716 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1851036716
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.465105308
Short name T1141
Test name
Test status
Simulation time 26487239 ps
CPU time 0.59 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 195712 kb
Host smart-ee1fbaba-94fa-49b2-b055-7b6fb0c67369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465105308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.465105308
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.858881442
Short name T1182
Test name
Test status
Simulation time 11900783 ps
CPU time 0.57 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 194752 kb
Host smart-49cc5a00-ea77-45bd-ad53-c7ef07c93235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858881442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.858881442
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2196889488
Short name T1214
Test name
Test status
Simulation time 16542969 ps
CPU time 0.74 seconds
Started Jul 01 04:30:58 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 196904 kb
Host smart-d67af5fe-4814-49cf-af63-b73dbd7da316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196889488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2196889488
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3594889557
Short name T1157
Test name
Test status
Simulation time 25523349 ps
CPU time 1.33 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 200472 kb
Host smart-a9b0b636-c6b8-4a3c-9849-6ab00fae9d71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594889557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3594889557
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.825823874
Short name T1178
Test name
Test status
Simulation time 48462139 ps
CPU time 1 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:11 PM PDT 24
Peak memory 199444 kb
Host smart-761c3c4d-3409-47ca-a48c-a6f211688a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825823874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.825823874
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2672774357
Short name T1189
Test name
Test status
Simulation time 30140172 ps
CPU time 0.82 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:18 PM PDT 24
Peak memory 199984 kb
Host smart-2ea082f0-c358-4415-ae38-eb2a2998c49f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672774357 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2672774357
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1679701612
Short name T93
Test name
Test status
Simulation time 16125066 ps
CPU time 0.61 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 195796 kb
Host smart-eac63312-af3a-4f81-af4d-e35d64cd8215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679701612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1679701612
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1308773993
Short name T1222
Test name
Test status
Simulation time 15064558 ps
CPU time 0.57 seconds
Started Jul 01 04:31:08 PM PDT 24
Finished Jul 01 04:31:22 PM PDT 24
Peak memory 194840 kb
Host smart-1aa6afe7-38c3-45e1-ac9b-4245772953b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308773993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1308773993
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1974147910
Short name T1119
Test name
Test status
Simulation time 43293638 ps
CPU time 0.67 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 197024 kb
Host smart-3a5d37f8-ebf0-4f66-9ade-29556725a940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974147910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1974147910
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.4037590799
Short name T1212
Test name
Test status
Simulation time 312632018 ps
CPU time 2.52 seconds
Started Jul 01 04:31:15 PM PDT 24
Finished Jul 01 04:31:29 PM PDT 24
Peak memory 200324 kb
Host smart-e4173a97-476e-4e63-afc7-4fe64da64759
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037590799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.4037590799
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3409327483
Short name T1149
Test name
Test status
Simulation time 90857872 ps
CPU time 1.32 seconds
Started Jul 01 04:31:14 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 199712 kb
Host smart-8d228e60-cb4d-4b9c-9b79-13dfd86e5b65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409327483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3409327483
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.305655181
Short name T1107
Test name
Test status
Simulation time 93683112 ps
CPU time 1.11 seconds
Started Jul 01 04:31:08 PM PDT 24
Finished Jul 01 04:31:23 PM PDT 24
Peak memory 200104 kb
Host smart-1b2b5d21-8491-49f2-8851-0ce38f2a1007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305655181 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.305655181
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1361381801
Short name T1143
Test name
Test status
Simulation time 55650358 ps
CPU time 0.61 seconds
Started Jul 01 04:31:01 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 195904 kb
Host smart-c352333a-f922-4d73-b7bb-ae5c4a4b80d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361381801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1361381801
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.518110878
Short name T1164
Test name
Test status
Simulation time 41294540 ps
CPU time 0.55 seconds
Started Jul 01 04:31:07 PM PDT 24
Finished Jul 01 04:31:22 PM PDT 24
Peak memory 194644 kb
Host smart-5ffd72b9-1298-4da2-bcc5-561e6d3e7399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518110878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.518110878
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.234638077
Short name T1142
Test name
Test status
Simulation time 32640051 ps
CPU time 0.81 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 196512 kb
Host smart-e1dcf823-c01c-4b07-8874-2e37a0bfa969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234638077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.234638077
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2462855341
Short name T1117
Test name
Test status
Simulation time 131286367 ps
CPU time 1.94 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:19 PM PDT 24
Peak memory 200284 kb
Host smart-2e11df1d-d6fd-4be2-92db-6bce59327b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462855341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2462855341
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1685255626
Short name T1220
Test name
Test status
Simulation time 167338371 ps
CPU time 1.34 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:18 PM PDT 24
Peak memory 199456 kb
Host smart-95514f42-394d-4e44-8888-e1283a87725b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685255626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1685255626
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2975033008
Short name T1121
Test name
Test status
Simulation time 64764560 ps
CPU time 0.74 seconds
Started Jul 01 04:31:07 PM PDT 24
Finished Jul 01 04:31:22 PM PDT 24
Peak memory 198148 kb
Host smart-f2ede81f-bfda-4ee7-bc42-68cb4638eb32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975033008 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2975033008
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.719130199
Short name T1150
Test name
Test status
Simulation time 24518870 ps
CPU time 0.62 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 195968 kb
Host smart-36cf5db7-2981-4cfa-98ff-7dfa9351c546
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719130199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.719130199
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3478718449
Short name T1102
Test name
Test status
Simulation time 14079623 ps
CPU time 0.58 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 194640 kb
Host smart-71e13a82-1d3b-4f4b-93dc-c5df068019a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478718449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3478718449
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4232382235
Short name T1180
Test name
Test status
Simulation time 59761057 ps
CPU time 0.63 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 195864 kb
Host smart-f04600e4-95de-457e-8bc9-f7aa5833805b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232382235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.4232382235
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2817388327
Short name T1209
Test name
Test status
Simulation time 96319616 ps
CPU time 1.23 seconds
Started Jul 01 04:31:03 PM PDT 24
Finished Jul 01 04:31:16 PM PDT 24
Peak memory 200560 kb
Host smart-23d4217f-b78b-4259-8770-b6932f69444f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817388327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2817388327
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2185449709
Short name T103
Test name
Test status
Simulation time 55078943 ps
CPU time 0.98 seconds
Started Jul 01 04:31:04 PM PDT 24
Finished Jul 01 04:31:18 PM PDT 24
Peak memory 199276 kb
Host smart-ccbe663a-35f2-4954-8b78-6efccc22f5fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185449709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2185449709
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4121462134
Short name T1165
Test name
Test status
Simulation time 34675497 ps
CPU time 0.7 seconds
Started Jul 01 04:31:10 PM PDT 24
Finished Jul 01 04:31:24 PM PDT 24
Peak memory 198128 kb
Host smart-283217e9-77e3-4f72-8848-cfb1b442546e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121462134 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.4121462134
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3373192554
Short name T100
Test name
Test status
Simulation time 50608378 ps
CPU time 0.61 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 195884 kb
Host smart-c2b20f7d-1fd6-47d3-9c9c-3245f199cd03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373192554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3373192554
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.660050599
Short name T1096
Test name
Test status
Simulation time 14642921 ps
CPU time 0.6 seconds
Started Jul 01 04:31:08 PM PDT 24
Finished Jul 01 04:31:22 PM PDT 24
Peak memory 194840 kb
Host smart-9848d79c-3f1a-41ee-981d-180e9ab15b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660050599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.660050599
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.824029076
Short name T1177
Test name
Test status
Simulation time 111977211 ps
CPU time 0.74 seconds
Started Jul 01 04:31:12 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 197476 kb
Host smart-c486e684-b9ba-4b2d-9c48-fdb4f9f9cd95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824029076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.824029076
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2262322102
Short name T1225
Test name
Test status
Simulation time 52638943 ps
CPU time 1.38 seconds
Started Jul 01 04:31:02 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 200444 kb
Host smart-856b814e-b371-4c84-9f30-4d6d6c581a32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262322102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2262322102
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3045359745
Short name T104
Test name
Test status
Simulation time 136826030 ps
CPU time 1.28 seconds
Started Jul 01 04:31:07 PM PDT 24
Finished Jul 01 04:31:22 PM PDT 24
Peak memory 199596 kb
Host smart-f5c39ecf-fb31-4706-98cf-240a30f29c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045359745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3045359745
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3080441241
Short name T389
Test name
Test status
Simulation time 47437799 ps
CPU time 0.56 seconds
Started Jul 01 06:34:29 PM PDT 24
Finished Jul 01 06:34:33 PM PDT 24
Peak memory 194888 kb
Host smart-33f39add-3dba-46fc-b9e2-9ea054afad13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080441241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3080441241
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2176963443
Short name T958
Test name
Test status
Simulation time 55709137651 ps
CPU time 83.1 seconds
Started Jul 01 06:34:23 PM PDT 24
Finished Jul 01 06:35:52 PM PDT 24
Peak memory 200024 kb
Host smart-18743414-48b3-411c-b37f-6858516a76f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176963443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2176963443
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.852086371
Short name T413
Test name
Test status
Simulation time 229929614582 ps
CPU time 33.2 seconds
Started Jul 01 06:34:25 PM PDT 24
Finished Jul 01 06:35:04 PM PDT 24
Peak memory 199956 kb
Host smart-f24df520-15f0-4715-978e-8ca4cdbe12b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852086371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.852086371
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.2561190923
Short name T651
Test name
Test status
Simulation time 214937359831 ps
CPU time 195.54 seconds
Started Jul 01 06:34:25 PM PDT 24
Finished Jul 01 06:37:47 PM PDT 24
Peak memory 199772 kb
Host smart-dadfc5dc-302f-40ab-b662-1573c2797fcf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561190923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2561190923
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3399342319
Short name T399
Test name
Test status
Simulation time 136961218047 ps
CPU time 536.88 seconds
Started Jul 01 06:34:26 PM PDT 24
Finished Jul 01 06:43:28 PM PDT 24
Peak memory 199976 kb
Host smart-cc88bbec-880f-4525-a59c-e75e25241be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3399342319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3399342319
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3293452420
Short name T754
Test name
Test status
Simulation time 3157073646 ps
CPU time 6.01 seconds
Started Jul 01 06:34:28 PM PDT 24
Finished Jul 01 06:34:38 PM PDT 24
Peak memory 195968 kb
Host smart-7a9fb520-742e-448c-a1f5-0d2d5324cab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293452420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3293452420
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.4193455330
Short name T854
Test name
Test status
Simulation time 14927437982 ps
CPU time 338.15 seconds
Started Jul 01 06:34:27 PM PDT 24
Finished Jul 01 06:40:10 PM PDT 24
Peak memory 199808 kb
Host smart-ae0b66be-1ab6-4c59-b2c9-4c871745c887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193455330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4193455330
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3422719840
Short name T456
Test name
Test status
Simulation time 2117447095 ps
CPU time 12.4 seconds
Started Jul 01 06:34:23 PM PDT 24
Finished Jul 01 06:34:41 PM PDT 24
Peak memory 198000 kb
Host smart-a4ccbcd1-af2d-490d-a495-f4debdc5376d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3422719840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3422719840
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.714760168
Short name T710
Test name
Test status
Simulation time 31301394137 ps
CPU time 63.38 seconds
Started Jul 01 06:34:29 PM PDT 24
Finished Jul 01 06:35:36 PM PDT 24
Peak memory 199952 kb
Host smart-959e0974-a51a-45c0-9084-8016f1aeaf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714760168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.714760168
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.42998209
Short name T1047
Test name
Test status
Simulation time 5310337794 ps
CPU time 2.73 seconds
Started Jul 01 06:34:26 PM PDT 24
Finished Jul 01 06:34:34 PM PDT 24
Peak memory 196300 kb
Host smart-d83c5acb-9dbe-4b36-8d53-060bbb712cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42998209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.42998209
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.786000448
Short name T847
Test name
Test status
Simulation time 121115289 ps
CPU time 0.98 seconds
Started Jul 01 06:34:24 PM PDT 24
Finished Jul 01 06:34:31 PM PDT 24
Peak memory 197796 kb
Host smart-a8a1bafa-0551-4646-b6cb-6a02208b1937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786000448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.786000448
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.112702066
Short name T1054
Test name
Test status
Simulation time 201944225129 ps
CPU time 354.27 seconds
Started Jul 01 06:34:30 PM PDT 24
Finished Jul 01 06:40:27 PM PDT 24
Peak memory 200072 kb
Host smart-3afe9051-97e5-4ac1-8150-c0bc22e778c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112702066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.112702066
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2173367832
Short name T643
Test name
Test status
Simulation time 2337882506 ps
CPU time 2.25 seconds
Started Jul 01 06:34:22 PM PDT 24
Finished Jul 01 06:34:29 PM PDT 24
Peak memory 198516 kb
Host smart-a4b716c4-8683-4237-beaf-7c137abcc244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173367832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2173367832
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1918909066
Short name T788
Test name
Test status
Simulation time 3218436989 ps
CPU time 3.17 seconds
Started Jul 01 06:34:22 PM PDT 24
Finished Jul 01 06:34:31 PM PDT 24
Peak memory 197780 kb
Host smart-3d40c7c7-7370-4573-b6c9-9c2880b41e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918909066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1918909066
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.474347616
Short name T859
Test name
Test status
Simulation time 46445369 ps
CPU time 0.57 seconds
Started Jul 01 06:34:38 PM PDT 24
Finished Jul 01 06:34:41 PM PDT 24
Peak memory 195324 kb
Host smart-9ff6f251-7e39-4a2f-a627-54d57b6f962b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474347616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.474347616
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1138657566
Short name T619
Test name
Test status
Simulation time 77425149083 ps
CPU time 34.81 seconds
Started Jul 01 06:34:29 PM PDT 24
Finished Jul 01 06:35:07 PM PDT 24
Peak memory 200076 kb
Host smart-adb671a1-2f6c-49ce-8c4b-4de352006733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138657566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1138657566
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2873485780
Short name T318
Test name
Test status
Simulation time 48981526272 ps
CPU time 83.65 seconds
Started Jul 01 06:34:25 PM PDT 24
Finished Jul 01 06:35:55 PM PDT 24
Peak memory 199996 kb
Host smart-d55323f3-cd1a-4001-bc51-d13923a867b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873485780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2873485780
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1032626152
Short name T143
Test name
Test status
Simulation time 117698616901 ps
CPU time 158.79 seconds
Started Jul 01 06:34:27 PM PDT 24
Finished Jul 01 06:37:10 PM PDT 24
Peak memory 199988 kb
Host smart-325e09af-9155-43ac-b9f9-0a650961b31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032626152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1032626152
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2865311893
Short name T684
Test name
Test status
Simulation time 61616998471 ps
CPU time 138.64 seconds
Started Jul 01 06:34:28 PM PDT 24
Finished Jul 01 06:36:51 PM PDT 24
Peak memory 199908 kb
Host smart-6f450065-1648-4961-a105-62973c17306b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865311893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2865311893
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1052048773
Short name T388
Test name
Test status
Simulation time 62148119113 ps
CPU time 334.07 seconds
Started Jul 01 06:34:36 PM PDT 24
Finished Jul 01 06:40:13 PM PDT 24
Peak memory 199968 kb
Host smart-2dcb9b02-3d83-418d-97ed-5adf1e706371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052048773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1052048773
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2231711537
Short name T483
Test name
Test status
Simulation time 510305357 ps
CPU time 1 seconds
Started Jul 01 06:34:32 PM PDT 24
Finished Jul 01 06:34:35 PM PDT 24
Peak memory 198740 kb
Host smart-503d1ad1-5adc-41ab-b29d-bb09457febca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231711537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2231711537
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.4085975760
Short name T676
Test name
Test status
Simulation time 5248823512 ps
CPU time 151.28 seconds
Started Jul 01 06:34:35 PM PDT 24
Finished Jul 01 06:37:10 PM PDT 24
Peak memory 200152 kb
Host smart-8c7b0b3e-e8ad-47db-a9a5-fe7e7f3a2f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085975760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.4085975760
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.373652111
Short name T573
Test name
Test status
Simulation time 3710910815 ps
CPU time 7.65 seconds
Started Jul 01 06:34:29 PM PDT 24
Finished Jul 01 06:34:40 PM PDT 24
Peak memory 198056 kb
Host smart-5d9a9901-61b3-487f-9190-1cd30bc271d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373652111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.373652111
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1763529919
Short name T932
Test name
Test status
Simulation time 40719110225 ps
CPU time 26.04 seconds
Started Jul 01 06:34:33 PM PDT 24
Finished Jul 01 06:35:01 PM PDT 24
Peak memory 199944 kb
Host smart-6f731712-9fda-4b4e-aa3d-1ebe1313651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763529919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1763529919
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2966533926
Short name T457
Test name
Test status
Simulation time 6770108534 ps
CPU time 2.73 seconds
Started Jul 01 06:34:36 PM PDT 24
Finished Jul 01 06:34:42 PM PDT 24
Peak memory 196496 kb
Host smart-7d8b980a-93fd-44ac-82f9-e846ca0564c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966533926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2966533926
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.770969710
Short name T23
Test name
Test status
Simulation time 713583525 ps
CPU time 0.85 seconds
Started Jul 01 06:34:33 PM PDT 24
Finished Jul 01 06:34:37 PM PDT 24
Peak memory 218404 kb
Host smart-ef0b5663-dfb7-4bab-b895-11441a97d0d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770969710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.770969710
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3127465232
Short name T821
Test name
Test status
Simulation time 933283135 ps
CPU time 3.94 seconds
Started Jul 01 06:34:27 PM PDT 24
Finished Jul 01 06:34:36 PM PDT 24
Peak memory 199676 kb
Host smart-d5a9155e-74d5-40f6-a4e3-89d7f26b92ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127465232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3127465232
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.4038378279
Short name T697
Test name
Test status
Simulation time 31755933519 ps
CPU time 411.91 seconds
Started Jul 01 06:34:37 PM PDT 24
Finished Jul 01 06:41:31 PM PDT 24
Peak memory 215560 kb
Host smart-a4228519-8f8f-4036-affd-c313474dd950
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038378279 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.4038378279
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.237928807
Short name T766
Test name
Test status
Simulation time 1050342871 ps
CPU time 4.71 seconds
Started Jul 01 06:34:36 PM PDT 24
Finished Jul 01 06:34:43 PM PDT 24
Peak memory 198988 kb
Host smart-f951849a-b16e-4d5c-afd7-ff428e5d11f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237928807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.237928807
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1268958127
Short name T516
Test name
Test status
Simulation time 80001070137 ps
CPU time 59.46 seconds
Started Jul 01 06:34:27 PM PDT 24
Finished Jul 01 06:35:31 PM PDT 24
Peak memory 199936 kb
Host smart-640631a0-8667-426e-8401-1a82ce3531fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268958127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1268958127
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2908909811
Short name T496
Test name
Test status
Simulation time 54674264 ps
CPU time 0.58 seconds
Started Jul 01 06:35:38 PM PDT 24
Finished Jul 01 06:35:40 PM PDT 24
Peak memory 195376 kb
Host smart-467c584a-58a1-452f-b4af-a87f86297d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908909811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2908909811
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3911336890
Short name T1033
Test name
Test status
Simulation time 109234260402 ps
CPU time 43.98 seconds
Started Jul 01 06:35:36 PM PDT 24
Finished Jul 01 06:36:21 PM PDT 24
Peak memory 199996 kb
Host smart-d4e885d7-5ba6-4ed8-b5f4-f8e4ab49093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911336890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3911336890
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1985136110
Short name T47
Test name
Test status
Simulation time 77971670664 ps
CPU time 133.08 seconds
Started Jul 01 06:35:33 PM PDT 24
Finished Jul 01 06:37:47 PM PDT 24
Peak memory 199948 kb
Host smart-faa8d7f0-eaac-4164-ad60-0cd8f8f1edb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985136110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1985136110
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.4244866197
Short name T588
Test name
Test status
Simulation time 179163156953 ps
CPU time 257.89 seconds
Started Jul 01 06:35:36 PM PDT 24
Finished Jul 01 06:39:55 PM PDT 24
Peak memory 199980 kb
Host smart-537528ed-bcba-429a-8e7a-8ebc99161cbb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244866197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.4244866197
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1019960373
Short name T598
Test name
Test status
Simulation time 197725677636 ps
CPU time 339.06 seconds
Started Jul 01 06:35:38 PM PDT 24
Finished Jul 01 06:41:18 PM PDT 24
Peak memory 199976 kb
Host smart-2340eb41-f6e7-4af7-a859-4017c7e5743a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019960373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1019960373
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3083191040
Short name T922
Test name
Test status
Simulation time 3808242693 ps
CPU time 6.7 seconds
Started Jul 01 06:35:39 PM PDT 24
Finished Jul 01 06:35:47 PM PDT 24
Peak memory 198604 kb
Host smart-a6c21f45-882a-426e-b4df-6a7c4a5fa4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083191040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3083191040
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.2423360283
Short name T637
Test name
Test status
Simulation time 5606637078 ps
CPU time 294.13 seconds
Started Jul 01 06:35:42 PM PDT 24
Finished Jul 01 06:40:37 PM PDT 24
Peak memory 200064 kb
Host smart-e4c39803-fb09-4955-9d64-f8efdaa294c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423360283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2423360283
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.135537492
Short name T910
Test name
Test status
Simulation time 4935615130 ps
CPU time 3.49 seconds
Started Jul 01 06:35:34 PM PDT 24
Finished Jul 01 06:35:39 PM PDT 24
Peak memory 198864 kb
Host smart-ee6e609e-80e0-4dbf-bcc5-e9056c5c1aea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135537492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.135537492
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1892973173
Short name T37
Test name
Test status
Simulation time 14424597937 ps
CPU time 23.33 seconds
Started Jul 01 06:35:37 PM PDT 24
Finished Jul 01 06:36:02 PM PDT 24
Peak memory 199984 kb
Host smart-b592c5e1-d14a-4663-9e77-b84e6dadf9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892973173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1892973173
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3848722231
Short name T742
Test name
Test status
Simulation time 1762149714 ps
CPU time 3.5 seconds
Started Jul 01 06:35:34 PM PDT 24
Finished Jul 01 06:35:39 PM PDT 24
Peak memory 195600 kb
Host smart-c698ee68-c38b-411a-838d-af32cd9b93bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848722231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3848722231
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1930220196
Short name T1044
Test name
Test status
Simulation time 5551614645 ps
CPU time 8.46 seconds
Started Jul 01 06:35:25 PM PDT 24
Finished Jul 01 06:35:35 PM PDT 24
Peak memory 199976 kb
Host smart-eeb0a73b-b530-4335-af29-a20d464ca0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930220196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1930220196
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3891370362
Short name T704
Test name
Test status
Simulation time 7561305543 ps
CPU time 13.21 seconds
Started Jul 01 06:35:40 PM PDT 24
Finished Jul 01 06:35:55 PM PDT 24
Peak memory 199616 kb
Host smart-3dcce46e-b9a1-4a20-8f61-3b088682a7ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891370362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3891370362
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3620845798
Short name T668
Test name
Test status
Simulation time 59454129159 ps
CPU time 349.07 seconds
Started Jul 01 06:35:41 PM PDT 24
Finished Jul 01 06:41:32 PM PDT 24
Peak memory 216584 kb
Host smart-98bc8dd3-b7bf-4b58-bf73-d981c7e51ddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620845798 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3620845798
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1212421546
Short name T297
Test name
Test status
Simulation time 12891057768 ps
CPU time 4.9 seconds
Started Jul 01 06:35:33 PM PDT 24
Finished Jul 01 06:35:38 PM PDT 24
Peak memory 199800 kb
Host smart-083c2065-c2b2-4225-be5d-7782602f21f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212421546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1212421546
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.233777163
Short name T770
Test name
Test status
Simulation time 32767153490 ps
CPU time 49.41 seconds
Started Jul 01 06:35:32 PM PDT 24
Finished Jul 01 06:36:23 PM PDT 24
Peak memory 199988 kb
Host smart-80a479dd-1433-4d7f-9921-f64e28b70e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233777163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.233777163
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1013154128
Short name T517
Test name
Test status
Simulation time 70672072892 ps
CPU time 59.01 seconds
Started Jul 01 06:41:32 PM PDT 24
Finished Jul 01 06:42:32 PM PDT 24
Peak memory 199972 kb
Host smart-1f5dc2c4-7a4d-41d9-b5d5-55cc4bd47af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013154128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1013154128
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3503213585
Short name T114
Test name
Test status
Simulation time 168034677101 ps
CPU time 86.01 seconds
Started Jul 01 06:41:28 PM PDT 24
Finished Jul 01 06:42:55 PM PDT 24
Peak memory 199956 kb
Host smart-50c782b9-5599-4fe5-b58f-379ad3316a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503213585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3503213585
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.391974743
Short name T454
Test name
Test status
Simulation time 89869680342 ps
CPU time 67.31 seconds
Started Jul 01 06:41:28 PM PDT 24
Finished Jul 01 06:42:37 PM PDT 24
Peak memory 199948 kb
Host smart-739e5c0c-a9d2-4196-869a-24e4899ebad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391974743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.391974743
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.427808845
Short name T221
Test name
Test status
Simulation time 26131378616 ps
CPU time 20.88 seconds
Started Jul 01 06:41:29 PM PDT 24
Finished Jul 01 06:41:51 PM PDT 24
Peak memory 199932 kb
Host smart-e8176795-34dd-4771-93a8-0a80655b704f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427808845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.427808845
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.366815810
Short name T599
Test name
Test status
Simulation time 71395098201 ps
CPU time 32.48 seconds
Started Jul 01 06:41:28 PM PDT 24
Finished Jul 01 06:42:02 PM PDT 24
Peak memory 200008 kb
Host smart-f20dd199-659b-4818-8a8b-c6bbe40fefae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366815810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.366815810
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3358929532
Short name T857
Test name
Test status
Simulation time 13978848162 ps
CPU time 22.69 seconds
Started Jul 01 06:41:29 PM PDT 24
Finished Jul 01 06:41:53 PM PDT 24
Peak memory 199956 kb
Host smart-61497e5b-8f60-41b9-97c2-beedadfcb1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358929532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3358929532
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.713822730
Short name T469
Test name
Test status
Simulation time 94354739024 ps
CPU time 22.79 seconds
Started Jul 01 06:41:29 PM PDT 24
Finished Jul 01 06:41:53 PM PDT 24
Peak memory 199976 kb
Host smart-119a5a41-865a-4176-bcd3-7e18abad23ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713822730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.713822730
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2148864795
Short name T393
Test name
Test status
Simulation time 15673520626 ps
CPU time 6.59 seconds
Started Jul 01 06:41:32 PM PDT 24
Finished Jul 01 06:41:39 PM PDT 24
Peak memory 200028 kb
Host smart-d9542332-6a91-4f65-bb96-ab7844c42ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148864795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2148864795
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1390583084
Short name T679
Test name
Test status
Simulation time 132153043687 ps
CPU time 212.77 seconds
Started Jul 01 06:41:30 PM PDT 24
Finished Jul 01 06:45:04 PM PDT 24
Peak memory 199968 kb
Host smart-a404ec9e-9e48-41e1-9ecc-5c54b51a4782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390583084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1390583084
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4073273699
Short name T458
Test name
Test status
Simulation time 139993240 ps
CPU time 0.53 seconds
Started Jul 01 06:35:45 PM PDT 24
Finished Jul 01 06:35:48 PM PDT 24
Peak memory 195432 kb
Host smart-fae51a06-b8de-4881-9e39-e078fc5a7913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073273699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4073273699
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.77920344
Short name T838
Test name
Test status
Simulation time 24248844202 ps
CPU time 42.89 seconds
Started Jul 01 06:35:39 PM PDT 24
Finished Jul 01 06:36:23 PM PDT 24
Peak memory 199996 kb
Host smart-ca92a863-2934-4227-8464-7e860dc69886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77920344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.77920344
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1207636342
Short name T151
Test name
Test status
Simulation time 29343062949 ps
CPU time 26.14 seconds
Started Jul 01 06:35:40 PM PDT 24
Finished Jul 01 06:36:08 PM PDT 24
Peak memory 199936 kb
Host smart-4727f0b3-a8e3-420b-98ae-5e231ed4de04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207636342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1207636342
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1922540108
Short name T811
Test name
Test status
Simulation time 184424836897 ps
CPU time 175.37 seconds
Started Jul 01 06:35:39 PM PDT 24
Finished Jul 01 06:38:36 PM PDT 24
Peak memory 200004 kb
Host smart-b0e4cb74-62ef-46ce-b477-ade32da9cf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922540108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1922540108
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.481503620
Short name T249
Test name
Test status
Simulation time 287185455475 ps
CPU time 161.54 seconds
Started Jul 01 06:35:41 PM PDT 24
Finished Jul 01 06:38:24 PM PDT 24
Peak memory 199944 kb
Host smart-fa75b3fc-c201-41b0-ac47-06ffe1324f35
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481503620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.481503620
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1073313107
Short name T988
Test name
Test status
Simulation time 183540130217 ps
CPU time 329.62 seconds
Started Jul 01 06:35:47 PM PDT 24
Finished Jul 01 06:41:19 PM PDT 24
Peak memory 200000 kb
Host smart-0b45d941-c1ad-4bc1-9dfe-5d0663884687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073313107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1073313107
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.783512332
Short name T708
Test name
Test status
Simulation time 2180310588 ps
CPU time 1.71 seconds
Started Jul 01 06:35:45 PM PDT 24
Finished Jul 01 06:35:48 PM PDT 24
Peak memory 196184 kb
Host smart-6e1532eb-98f3-4238-b467-3aec4564c86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783512332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.783512332
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.924298901
Short name T268
Test name
Test status
Simulation time 10744704715 ps
CPU time 158.58 seconds
Started Jul 01 06:35:46 PM PDT 24
Finished Jul 01 06:38:27 PM PDT 24
Peak memory 199968 kb
Host smart-c5f99bc5-1e09-4a41-9399-5768b482d9ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924298901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.924298901
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2907311367
Short name T1
Test name
Test status
Simulation time 2407090705 ps
CPU time 1.96 seconds
Started Jul 01 06:35:39 PM PDT 24
Finished Jul 01 06:35:43 PM PDT 24
Peak memory 199084 kb
Host smart-d69f9e88-2ffd-4e6c-8c0b-9434eb959920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2907311367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2907311367
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3744077977
Short name T797
Test name
Test status
Simulation time 123720823774 ps
CPU time 214.8 seconds
Started Jul 01 06:35:39 PM PDT 24
Finished Jul 01 06:39:15 PM PDT 24
Peak memory 199984 kb
Host smart-11156716-ad67-4648-bd43-644188bb89ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744077977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3744077977
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2634773253
Short name T548
Test name
Test status
Simulation time 4978369448 ps
CPU time 8.68 seconds
Started Jul 01 06:35:39 PM PDT 24
Finished Jul 01 06:35:49 PM PDT 24
Peak memory 196092 kb
Host smart-6da69d29-1c98-4c5a-9216-8158285987b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634773253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2634773253
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2960118966
Short name T633
Test name
Test status
Simulation time 702624384 ps
CPU time 1.28 seconds
Started Jul 01 06:35:39 PM PDT 24
Finished Jul 01 06:35:42 PM PDT 24
Peak memory 198800 kb
Host smart-7f7ac168-5573-4b2a-87b3-dc2572dc9f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960118966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2960118966
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3836939433
Short name T628
Test name
Test status
Simulation time 518149084 ps
CPU time 1.18 seconds
Started Jul 01 06:35:45 PM PDT 24
Finished Jul 01 06:35:48 PM PDT 24
Peak memory 196972 kb
Host smart-ca8678d4-293c-4d3a-8fa2-8b664ecf08f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836939433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3836939433
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.506324401
Short name T307
Test name
Test status
Simulation time 18501488102 ps
CPU time 31.08 seconds
Started Jul 01 06:35:42 PM PDT 24
Finished Jul 01 06:36:14 PM PDT 24
Peak memory 199700 kb
Host smart-debe4bac-859e-4ce9-a2b8-9b35452ded55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506324401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.506324401
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2399449089
Short name T987
Test name
Test status
Simulation time 22952744668 ps
CPU time 35.42 seconds
Started Jul 01 06:41:29 PM PDT 24
Finished Jul 01 06:42:06 PM PDT 24
Peak memory 199976 kb
Host smart-e7a9e8f5-aa20-4fc4-be82-6d25dbbd4a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399449089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2399449089
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3394921203
Short name T462
Test name
Test status
Simulation time 56995774082 ps
CPU time 21.8 seconds
Started Jul 01 06:41:47 PM PDT 24
Finished Jul 01 06:42:10 PM PDT 24
Peak memory 198596 kb
Host smart-424d0bd8-5336-4c1b-958a-e6a8a669784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394921203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3394921203
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.372328133
Short name T162
Test name
Test status
Simulation time 134534957304 ps
CPU time 16.47 seconds
Started Jul 01 06:41:36 PM PDT 24
Finished Jul 01 06:41:54 PM PDT 24
Peak memory 200036 kb
Host smart-b73bbc47-7c18-458a-a2ef-10301cdf287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372328133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.372328133
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1730689754
Short name T461
Test name
Test status
Simulation time 10867513421 ps
CPU time 17.81 seconds
Started Jul 01 06:41:36 PM PDT 24
Finished Jul 01 06:41:55 PM PDT 24
Peak memory 198156 kb
Host smart-0e7900c9-2de6-4a3c-906f-13bac8ffa893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730689754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1730689754
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.579771913
Short name T762
Test name
Test status
Simulation time 9364469403 ps
CPU time 14.12 seconds
Started Jul 01 06:41:36 PM PDT 24
Finished Jul 01 06:41:51 PM PDT 24
Peak memory 199652 kb
Host smart-a4b3765c-2078-4297-8304-75ddb817f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579771913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.579771913
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.604979837
Short name T919
Test name
Test status
Simulation time 165267848915 ps
CPU time 56.45 seconds
Started Jul 01 06:41:38 PM PDT 24
Finished Jul 01 06:42:36 PM PDT 24
Peak memory 200000 kb
Host smart-9a4d05b1-e2fb-4c72-9fa2-1cd7afdeac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604979837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.604979837
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2867987674
Short name T406
Test name
Test status
Simulation time 35704575325 ps
CPU time 11.42 seconds
Started Jul 01 06:41:36 PM PDT 24
Finished Jul 01 06:41:48 PM PDT 24
Peak memory 199940 kb
Host smart-df7c4299-4a69-46a8-af52-ac686e4a9b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867987674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2867987674
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.4190621359
Short name T775
Test name
Test status
Simulation time 146606887289 ps
CPU time 37.44 seconds
Started Jul 01 06:41:37 PM PDT 24
Finished Jul 01 06:42:16 PM PDT 24
Peak memory 200076 kb
Host smart-a04c963f-01bf-4281-894f-53d0cbfa341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190621359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4190621359
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.338909245
Short name T85
Test name
Test status
Simulation time 41184070 ps
CPU time 0.56 seconds
Started Jul 01 06:35:52 PM PDT 24
Finished Jul 01 06:35:56 PM PDT 24
Peak memory 195312 kb
Host smart-ee0dc819-537b-4c63-ae83-41b3db3fd1ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338909245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.338909245
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2008745612
Short name T352
Test name
Test status
Simulation time 144425338238 ps
CPU time 36.65 seconds
Started Jul 01 06:35:45 PM PDT 24
Finished Jul 01 06:36:25 PM PDT 24
Peak memory 200004 kb
Host smart-e3e91592-fd89-4f49-9327-8dd9ff467453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008745612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2008745612
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2713910439
Short name T282
Test name
Test status
Simulation time 55913968316 ps
CPU time 27.86 seconds
Started Jul 01 06:35:48 PM PDT 24
Finished Jul 01 06:36:18 PM PDT 24
Peak memory 200012 kb
Host smart-1822797f-57ba-4717-9356-16dd0d95e476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713910439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2713910439
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2510605698
Short name T771
Test name
Test status
Simulation time 13753998798 ps
CPU time 15.03 seconds
Started Jul 01 06:35:46 PM PDT 24
Finished Jul 01 06:36:04 PM PDT 24
Peak memory 199980 kb
Host smart-277292de-990a-41d8-9c9b-5c575904f83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510605698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2510605698
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2184005667
Short name T486
Test name
Test status
Simulation time 29166292085 ps
CPU time 48.41 seconds
Started Jul 01 06:35:47 PM PDT 24
Finished Jul 01 06:36:38 PM PDT 24
Peak memory 199560 kb
Host smart-c21ec795-ac0f-4b22-a372-505543c01da8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184005667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2184005667
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.469975564
Short name T258
Test name
Test status
Simulation time 122572336831 ps
CPU time 819.1 seconds
Started Jul 01 06:35:52 PM PDT 24
Finished Jul 01 06:49:33 PM PDT 24
Peak memory 199916 kb
Host smart-321ea403-66f0-4b83-80e4-58b300d37b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469975564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.469975564
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1863219536
Short name T363
Test name
Test status
Simulation time 1116675928 ps
CPU time 3.78 seconds
Started Jul 01 06:35:53 PM PDT 24
Finished Jul 01 06:36:01 PM PDT 24
Peak memory 198456 kb
Host smart-888d1ffc-b109-4e4c-810b-9bfe43ea995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863219536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1863219536
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.3880108838
Short name T1052
Test name
Test status
Simulation time 13167769780 ps
CPU time 349.05 seconds
Started Jul 01 06:35:52 PM PDT 24
Finished Jul 01 06:41:44 PM PDT 24
Peak memory 199980 kb
Host smart-1219d1d7-8b39-47f5-a99f-82aa16ea2ab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880108838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3880108838
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.872072158
Short name T404
Test name
Test status
Simulation time 6084844843 ps
CPU time 13.63 seconds
Started Jul 01 06:35:47 PM PDT 24
Finished Jul 01 06:36:04 PM PDT 24
Peak memory 199252 kb
Host smart-7802c4ad-8a7d-40d2-a87d-8e1bc51e6552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872072158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.872072158
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2525192801
Short name T641
Test name
Test status
Simulation time 59323461074 ps
CPU time 26.16 seconds
Started Jul 01 06:35:52 PM PDT 24
Finished Jul 01 06:36:21 PM PDT 24
Peak memory 199924 kb
Host smart-b394e2c4-b020-4148-8987-d3bfdda027f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525192801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2525192801
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2136437880
Short name T615
Test name
Test status
Simulation time 38554081499 ps
CPU time 50.06 seconds
Started Jul 01 06:35:45 PM PDT 24
Finished Jul 01 06:36:38 PM PDT 24
Peak memory 196320 kb
Host smart-a2460408-f1dc-4ce9-8295-aca0e4c4e20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136437880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2136437880
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3067420611
Short name T743
Test name
Test status
Simulation time 689659210 ps
CPU time 3.69 seconds
Started Jul 01 06:35:46 PM PDT 24
Finished Jul 01 06:35:52 PM PDT 24
Peak memory 199952 kb
Host smart-a96f4786-8c00-4b70-be06-0ca51ed726c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067420611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3067420611
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1461296984
Short name T1065
Test name
Test status
Simulation time 920869500 ps
CPU time 2.35 seconds
Started Jul 01 06:35:52 PM PDT 24
Finished Jul 01 06:35:58 PM PDT 24
Peak memory 198932 kb
Host smart-97fc06d5-c8a6-43be-9a9f-97ed22e124cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461296984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1461296984
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.865536415
Short name T391
Test name
Test status
Simulation time 46865896668 ps
CPU time 67.85 seconds
Started Jul 01 06:35:48 PM PDT 24
Finished Jul 01 06:36:58 PM PDT 24
Peak memory 199936 kb
Host smart-68f1b0b4-d1d6-49b8-90da-108ab60c899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865536415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.865536415
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2043608189
Short name T348
Test name
Test status
Simulation time 13069788157 ps
CPU time 24.59 seconds
Started Jul 01 06:41:37 PM PDT 24
Finished Jul 01 06:42:03 PM PDT 24
Peak memory 200104 kb
Host smart-d2027709-aef8-46a2-a481-0813989229d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043608189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2043608189
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.619669805
Short name T502
Test name
Test status
Simulation time 76459211011 ps
CPU time 67.39 seconds
Started Jul 01 06:41:37 PM PDT 24
Finished Jul 01 06:42:46 PM PDT 24
Peak memory 199936 kb
Host smart-37875aeb-60e7-41f1-8758-138cdde1c1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619669805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.619669805
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1428834870
Short name T138
Test name
Test status
Simulation time 29733810442 ps
CPU time 12.83 seconds
Started Jul 01 06:41:40 PM PDT 24
Finished Jul 01 06:41:54 PM PDT 24
Peak memory 200048 kb
Host smart-74171a05-2072-4296-b226-44ef2ad7cb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428834870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1428834870
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1623196134
Short name T597
Test name
Test status
Simulation time 37028014808 ps
CPU time 17.84 seconds
Started Jul 01 06:41:46 PM PDT 24
Finished Jul 01 06:42:05 PM PDT 24
Peak memory 200068 kb
Host smart-04e4b46e-bf27-4cea-b044-317565936cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623196134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1623196134
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3674411584
Short name T212
Test name
Test status
Simulation time 78652709658 ps
CPU time 66.38 seconds
Started Jul 01 06:41:35 PM PDT 24
Finished Jul 01 06:42:42 PM PDT 24
Peak memory 200004 kb
Host smart-264a6a80-c552-4cb4-b3b6-4446c72617c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674411584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3674411584
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2197572987
Short name T855
Test name
Test status
Simulation time 46436093981 ps
CPU time 11.04 seconds
Started Jul 01 06:41:36 PM PDT 24
Finished Jul 01 06:41:47 PM PDT 24
Peak memory 200012 kb
Host smart-a4ded58e-3410-4b19-8c42-aa534dd02b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197572987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2197572987
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2054754847
Short name T985
Test name
Test status
Simulation time 210208626736 ps
CPU time 153.09 seconds
Started Jul 01 06:41:48 PM PDT 24
Finished Jul 01 06:44:22 PM PDT 24
Peak memory 200032 kb
Host smart-5d2642ef-cdb2-40e4-8de4-49e63192de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054754847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2054754847
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3835647327
Short name T275
Test name
Test status
Simulation time 74370852637 ps
CPU time 60.29 seconds
Started Jul 01 06:41:45 PM PDT 24
Finished Jul 01 06:42:47 PM PDT 24
Peak memory 199956 kb
Host smart-732b7428-852b-46c8-b9b7-39973355c70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835647327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3835647327
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3484122856
Short name T117
Test name
Test status
Simulation time 366106279978 ps
CPU time 46.26 seconds
Started Jul 01 06:41:47 PM PDT 24
Finished Jul 01 06:42:35 PM PDT 24
Peak memory 200004 kb
Host smart-2b1bf8e3-e63c-4ebe-b97b-6cec08c40960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484122856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3484122856
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2802051390
Short name T523
Test name
Test status
Simulation time 52666826 ps
CPU time 0.55 seconds
Started Jul 01 06:35:59 PM PDT 24
Finished Jul 01 06:36:01 PM PDT 24
Peak memory 194292 kb
Host smart-5f60bded-7f53-4877-89d6-128efcb3e1c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802051390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2802051390
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2980469185
Short name T735
Test name
Test status
Simulation time 63109651643 ps
CPU time 44.25 seconds
Started Jul 01 06:35:55 PM PDT 24
Finished Jul 01 06:36:42 PM PDT 24
Peak memory 199900 kb
Host smart-88080d91-af3f-41b0-87a8-b5ef6d22c111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980469185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2980469185
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2339307760
Short name T425
Test name
Test status
Simulation time 56969622877 ps
CPU time 29.7 seconds
Started Jul 01 06:35:52 PM PDT 24
Finished Jul 01 06:36:26 PM PDT 24
Peak memory 200076 kb
Host smart-9fd78de7-ac0e-4585-8806-32d7919d656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339307760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2339307760
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1393152366
Short name T401
Test name
Test status
Simulation time 35177879228 ps
CPU time 13.5 seconds
Started Jul 01 06:35:50 PM PDT 24
Finished Jul 01 06:36:06 PM PDT 24
Peak memory 199964 kb
Host smart-56e2c6de-54ea-4da9-8d9e-585f01105673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393152366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1393152366
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.716731451
Short name T335
Test name
Test status
Simulation time 18399901155 ps
CPU time 7.22 seconds
Started Jul 01 06:35:59 PM PDT 24
Finished Jul 01 06:36:08 PM PDT 24
Peak memory 197048 kb
Host smart-1a5664bb-cd1c-4c39-982a-b377a7fc1055
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716731451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.716731451
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3408441061
Short name T979
Test name
Test status
Simulation time 89129374039 ps
CPU time 157.43 seconds
Started Jul 01 06:35:58 PM PDT 24
Finished Jul 01 06:38:37 PM PDT 24
Peak memory 199920 kb
Host smart-7773a814-f98a-402c-a4bf-98e2eb55d924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408441061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3408441061
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1868259740
Short name T17
Test name
Test status
Simulation time 5820624639 ps
CPU time 7.95 seconds
Started Jul 01 06:35:58 PM PDT 24
Finished Jul 01 06:36:08 PM PDT 24
Peak memory 199932 kb
Host smart-842ff531-11c2-4311-90af-ea8378b0d2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868259740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1868259740
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.1697275242
Short name T271
Test name
Test status
Simulation time 23757654290 ps
CPU time 614.38 seconds
Started Jul 01 06:36:00 PM PDT 24
Finished Jul 01 06:46:16 PM PDT 24
Peak memory 199940 kb
Host smart-5cf7d414-e7b9-40c4-9d99-74531c94f1a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1697275242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1697275242
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.839538309
Short name T524
Test name
Test status
Simulation time 5248034447 ps
CPU time 44.01 seconds
Started Jul 01 06:35:59 PM PDT 24
Finished Jul 01 06:36:45 PM PDT 24
Peak memory 199508 kb
Host smart-1bfdec3c-e68b-4799-9c96-0a6231ddd9ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839538309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.839538309
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2924900119
Short name T800
Test name
Test status
Simulation time 229095188775 ps
CPU time 26.27 seconds
Started Jul 01 06:35:59 PM PDT 24
Finished Jul 01 06:36:27 PM PDT 24
Peak memory 199988 kb
Host smart-48ab598e-a0e1-4b58-ab08-47af82a2404f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924900119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2924900119
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3386647268
Short name T460
Test name
Test status
Simulation time 6627902308 ps
CPU time 5.63 seconds
Started Jul 01 06:35:57 PM PDT 24
Finished Jul 01 06:36:04 PM PDT 24
Peak memory 196284 kb
Host smart-1ef269e6-f284-4e2a-8150-2a5ba68dd865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386647268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3386647268
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3760043659
Short name T44
Test name
Test status
Simulation time 5751152143 ps
CPU time 11.16 seconds
Started Jul 01 06:35:51 PM PDT 24
Finished Jul 01 06:36:05 PM PDT 24
Peak memory 199944 kb
Host smart-7c1965a6-f87e-4f49-b593-5943fa7744f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760043659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3760043659
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3784389703
Short name T675
Test name
Test status
Simulation time 295577768357 ps
CPU time 1027.07 seconds
Started Jul 01 06:35:59 PM PDT 24
Finished Jul 01 06:53:08 PM PDT 24
Peak memory 199968 kb
Host smart-c8f78ebb-20a9-49c1-83ac-644951aa7742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784389703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3784389703
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2833350655
Short name T501
Test name
Test status
Simulation time 114024737233 ps
CPU time 732.15 seconds
Started Jul 01 06:36:00 PM PDT 24
Finished Jul 01 06:48:14 PM PDT 24
Peak memory 216616 kb
Host smart-508eaca0-cf84-4874-b465-fd41bfe1e255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833350655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2833350655
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.224655818
Short name T515
Test name
Test status
Simulation time 608053000 ps
CPU time 2.03 seconds
Started Jul 01 06:35:58 PM PDT 24
Finished Jul 01 06:36:02 PM PDT 24
Peak memory 198904 kb
Host smart-870855ce-5de5-4588-97e7-797593222578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224655818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.224655818
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2284356005
Short name T270
Test name
Test status
Simulation time 159661975001 ps
CPU time 68.56 seconds
Started Jul 01 06:35:50 PM PDT 24
Finished Jul 01 06:37:01 PM PDT 24
Peak memory 200012 kb
Host smart-b6e05b10-3080-492e-93dd-957a0c82a4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284356005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2284356005
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2337489177
Short name T4
Test name
Test status
Simulation time 23463353300 ps
CPU time 20.85 seconds
Started Jul 01 06:41:48 PM PDT 24
Finished Jul 01 06:42:10 PM PDT 24
Peak memory 199936 kb
Host smart-a1ad4393-738d-4254-a1fa-7e17d526ae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337489177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2337489177
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.4160296242
Short name T664
Test name
Test status
Simulation time 130662283099 ps
CPU time 183.45 seconds
Started Jul 01 06:41:45 PM PDT 24
Finished Jul 01 06:44:50 PM PDT 24
Peak memory 200068 kb
Host smart-a5e8bdcc-5d60-4a96-8f0e-29c7d3e1d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160296242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.4160296242
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.992521250
Short name T649
Test name
Test status
Simulation time 20077772924 ps
CPU time 32.86 seconds
Started Jul 01 06:41:45 PM PDT 24
Finished Jul 01 06:42:19 PM PDT 24
Peak memory 200064 kb
Host smart-65db591a-b02b-4f35-bc4f-027e09441f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992521250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.992521250
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1205685901
Short name T1074
Test name
Test status
Simulation time 23094289975 ps
CPU time 19.95 seconds
Started Jul 01 06:41:48 PM PDT 24
Finished Jul 01 06:42:09 PM PDT 24
Peak memory 200064 kb
Host smart-3f2a0dd7-4742-4b8c-96f9-b62939ce6028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205685901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1205685901
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3872660484
Short name T513
Test name
Test status
Simulation time 279350978829 ps
CPU time 111.99 seconds
Started Jul 01 06:41:45 PM PDT 24
Finished Jul 01 06:43:39 PM PDT 24
Peak memory 200000 kb
Host smart-82ef3ea5-24c2-4ead-98be-c7e6cc4313c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872660484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3872660484
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3254044614
Short name T299
Test name
Test status
Simulation time 104656349251 ps
CPU time 148.95 seconds
Started Jul 01 06:41:48 PM PDT 24
Finished Jul 01 06:44:18 PM PDT 24
Peak memory 199916 kb
Host smart-3ad00f1d-d660-409b-8a09-65d64001b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254044614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3254044614
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1831318406
Short name T840
Test name
Test status
Simulation time 145360340938 ps
CPU time 219.39 seconds
Started Jul 01 06:41:49 PM PDT 24
Finished Jul 01 06:45:29 PM PDT 24
Peak memory 200092 kb
Host smart-8eff6529-d66e-460f-8219-9f85a0ceeb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831318406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1831318406
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4166482639
Short name T698
Test name
Test status
Simulation time 135993303016 ps
CPU time 101.62 seconds
Started Jul 01 06:41:44 PM PDT 24
Finished Jul 01 06:43:27 PM PDT 24
Peak memory 199964 kb
Host smart-428e5422-f25d-4769-ac31-2eae076e28ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166482639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4166482639
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1144193058
Short name T913
Test name
Test status
Simulation time 153094985985 ps
CPU time 15.47 seconds
Started Jul 01 06:36:05 PM PDT 24
Finished Jul 01 06:36:21 PM PDT 24
Peak memory 199952 kb
Host smart-122e0f2f-265a-456c-9a29-117ec61bf844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144193058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1144193058
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.879009807
Short name T35
Test name
Test status
Simulation time 9598715338 ps
CPU time 15.49 seconds
Started Jul 01 06:36:05 PM PDT 24
Finished Jul 01 06:36:21 PM PDT 24
Peak memory 199960 kb
Host smart-cf275aac-e65c-4bba-b44a-cad759e66f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879009807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.879009807
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4059648738
Short name T1042
Test name
Test status
Simulation time 142295785385 ps
CPU time 28.03 seconds
Started Jul 01 06:36:12 PM PDT 24
Finished Jul 01 06:36:41 PM PDT 24
Peak memory 200036 kb
Host smart-54092df1-1567-4c1e-8ef8-1596a0f626a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059648738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4059648738
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3820896583
Short name T1056
Test name
Test status
Simulation time 4889413589 ps
CPU time 11.28 seconds
Started Jul 01 06:36:05 PM PDT 24
Finished Jul 01 06:36:17 PM PDT 24
Peak memory 199984 kb
Host smart-4a86c98a-325f-43b0-87ae-bb31ac7d65df
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820896583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3820896583
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3591326794
Short name T468
Test name
Test status
Simulation time 78770995094 ps
CPU time 140.79 seconds
Started Jul 01 06:36:06 PM PDT 24
Finished Jul 01 06:38:28 PM PDT 24
Peak memory 200000 kb
Host smart-3b8bce74-64c1-4c63-a643-206eb8d4273c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591326794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3591326794
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2095000217
Short name T787
Test name
Test status
Simulation time 7249278587 ps
CPU time 13.7 seconds
Started Jul 01 06:36:05 PM PDT 24
Finished Jul 01 06:36:19 PM PDT 24
Peak memory 199128 kb
Host smart-ec75a875-c86e-426c-aec9-bb8f2d4c834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095000217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2095000217
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.3315670456
Short name T876
Test name
Test status
Simulation time 12763074882 ps
CPU time 349.41 seconds
Started Jul 01 06:36:04 PM PDT 24
Finished Jul 01 06:41:54 PM PDT 24
Peak memory 199968 kb
Host smart-dd4fe570-8730-4b0d-9e72-a3708c11142a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3315670456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3315670456
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1279525447
Short name T381
Test name
Test status
Simulation time 7690066495 ps
CPU time 35.22 seconds
Started Jul 01 06:36:06 PM PDT 24
Finished Jul 01 06:36:42 PM PDT 24
Peak memory 198244 kb
Host smart-f85e63c3-25ac-408d-bd68-439ceb54d269
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279525447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1279525447
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2633857611
Short name T904
Test name
Test status
Simulation time 199378464589 ps
CPU time 40.76 seconds
Started Jul 01 06:36:06 PM PDT 24
Finished Jul 01 06:36:47 PM PDT 24
Peak memory 200012 kb
Host smart-2ffc9d4c-2b57-49dd-9d4b-990004c732a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633857611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2633857611
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3847901488
Short name T1049
Test name
Test status
Simulation time 2409017081 ps
CPU time 1.51 seconds
Started Jul 01 06:36:12 PM PDT 24
Finished Jul 01 06:36:15 PM PDT 24
Peak memory 196304 kb
Host smart-e935dd37-2a54-49f8-9330-dda3f6feb15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847901488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3847901488
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1678714054
Short name T1050
Test name
Test status
Simulation time 861701800 ps
CPU time 1.64 seconds
Started Jul 01 06:36:06 PM PDT 24
Finished Jul 01 06:36:08 PM PDT 24
Peak memory 199704 kb
Host smart-626470d2-50f3-4774-956c-95bfa710e501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678714054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1678714054
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2636953625
Short name T638
Test name
Test status
Simulation time 27281024404 ps
CPU time 62.19 seconds
Started Jul 01 06:36:05 PM PDT 24
Finished Jul 01 06:37:08 PM PDT 24
Peak memory 199848 kb
Host smart-ffeac853-c468-4b2b-a18f-b0f370c7f062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636953625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2636953625
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2935817126
Short name T50
Test name
Test status
Simulation time 89884866021 ps
CPU time 256.36 seconds
Started Jul 01 06:36:06 PM PDT 24
Finished Jul 01 06:40:24 PM PDT 24
Peak memory 208428 kb
Host smart-1d6db7d4-f8b0-4b1a-b062-2f8ddcde07bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935817126 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2935817126
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2576085179
Short name T13
Test name
Test status
Simulation time 1280059597 ps
CPU time 3.61 seconds
Started Jul 01 06:36:06 PM PDT 24
Finished Jul 01 06:36:10 PM PDT 24
Peak memory 198892 kb
Host smart-e9c7b80c-e9f3-42ae-8b63-c657fa2fdb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576085179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2576085179
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.4264828709
Short name T287
Test name
Test status
Simulation time 62403800518 ps
CPU time 24.79 seconds
Started Jul 01 06:36:12 PM PDT 24
Finished Jul 01 06:36:38 PM PDT 24
Peak memory 200020 kb
Host smart-876e5577-6746-4392-b1a8-27eff147e3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264828709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.4264828709
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1755974086
Short name T213
Test name
Test status
Simulation time 14869239846 ps
CPU time 24.86 seconds
Started Jul 01 06:41:51 PM PDT 24
Finished Jul 01 06:42:17 PM PDT 24
Peak memory 199940 kb
Host smart-4f4d02e2-a074-460c-8b3a-4d869bcf4ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755974086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1755974086
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1983953979
Short name T757
Test name
Test status
Simulation time 432419804421 ps
CPU time 95.14 seconds
Started Jul 01 06:41:53 PM PDT 24
Finished Jul 01 06:43:31 PM PDT 24
Peak memory 199992 kb
Host smart-2ff1ea8d-d414-42ee-8f0b-e8e6747f8826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983953979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1983953979
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2705195043
Short name T300
Test name
Test status
Simulation time 66957751519 ps
CPU time 56.26 seconds
Started Jul 01 06:41:53 PM PDT 24
Finished Jul 01 06:42:52 PM PDT 24
Peak memory 199940 kb
Host smart-abd2a463-3530-4425-949e-a1adfe70b02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705195043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2705195043
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3036802929
Short name T891
Test name
Test status
Simulation time 74732630107 ps
CPU time 37.71 seconds
Started Jul 01 06:41:52 PM PDT 24
Finished Jul 01 06:42:33 PM PDT 24
Peak memory 199960 kb
Host smart-c42391c5-bc1c-4972-a7e3-f649ff1ee2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036802929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3036802929
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3358041948
Short name T877
Test name
Test status
Simulation time 11366274826 ps
CPU time 16.6 seconds
Started Jul 01 06:41:53 PM PDT 24
Finished Jul 01 06:42:12 PM PDT 24
Peak memory 200148 kb
Host smart-4573793c-219f-4473-8797-ab6e94f59bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358041948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3358041948
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3891274088
Short name T511
Test name
Test status
Simulation time 175256108792 ps
CPU time 42.09 seconds
Started Jul 01 06:41:52 PM PDT 24
Finished Jul 01 06:42:37 PM PDT 24
Peak memory 199980 kb
Host smart-51247263-6d87-4acb-99ed-a2422b6b4d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891274088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3891274088
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1185753930
Short name T1064
Test name
Test status
Simulation time 208760876064 ps
CPU time 90.05 seconds
Started Jul 01 06:41:52 PM PDT 24
Finished Jul 01 06:43:25 PM PDT 24
Peak memory 199876 kb
Host smart-667df30c-2c48-4fcd-8b99-a9033444d4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185753930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1185753930
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3344584869
Short name T238
Test name
Test status
Simulation time 95235971168 ps
CPU time 196.36 seconds
Started Jul 01 06:41:51 PM PDT 24
Finished Jul 01 06:45:11 PM PDT 24
Peak memory 200020 kb
Host smart-2c5e6a7b-178e-4834-b044-f46102f71ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344584869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3344584869
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2516793845
Short name T927
Test name
Test status
Simulation time 20481390380 ps
CPU time 29.43 seconds
Started Jul 01 06:41:51 PM PDT 24
Finished Jul 01 06:42:24 PM PDT 24
Peak memory 199992 kb
Host smart-3c8f2a99-4e52-45c6-8145-ef7d970b93bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516793845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2516793845
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2577464167
Short name T931
Test name
Test status
Simulation time 28756107 ps
CPU time 0.54 seconds
Started Jul 01 06:36:18 PM PDT 24
Finished Jul 01 06:36:20 PM PDT 24
Peak memory 195376 kb
Host smart-91a243bf-31b6-43fc-a886-a7e24acbfa11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577464167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2577464167
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2950187919
Short name T636
Test name
Test status
Simulation time 78465707217 ps
CPU time 138.42 seconds
Started Jul 01 06:36:12 PM PDT 24
Finished Jul 01 06:38:32 PM PDT 24
Peak memory 199948 kb
Host smart-6a61e3dd-c85e-4a4c-8d8f-59d11d9cfa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950187919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2950187919
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.1967292437
Short name T960
Test name
Test status
Simulation time 43882589356 ps
CPU time 77.18 seconds
Started Jul 01 06:36:12 PM PDT 24
Finished Jul 01 06:37:31 PM PDT 24
Peak memory 199932 kb
Host smart-9d22776b-a71c-4bcf-aeb5-e8d6212115ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967292437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1967292437
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1465476835
Short name T411
Test name
Test status
Simulation time 208353564324 ps
CPU time 160.96 seconds
Started Jul 01 06:36:11 PM PDT 24
Finished Jul 01 06:38:54 PM PDT 24
Peak memory 200064 kb
Host smart-75231a5d-d88c-4b42-a911-ee788925f8b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1465476835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1465476835
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.4256412561
Short name T677
Test name
Test status
Simulation time 13572040301 ps
CPU time 56.31 seconds
Started Jul 01 06:36:14 PM PDT 24
Finished Jul 01 06:37:11 PM PDT 24
Peak memory 198728 kb
Host smart-41ddf342-5ac5-4ffd-b8de-eac7c492f01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256412561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4256412561
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.2729726665
Short name T924
Test name
Test status
Simulation time 15181597114 ps
CPU time 449.41 seconds
Started Jul 01 06:36:13 PM PDT 24
Finished Jul 01 06:43:44 PM PDT 24
Peak memory 199984 kb
Host smart-e6eed699-ebcf-408a-9e99-faa808d80a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729726665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2729726665
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.601016059
Short name T400
Test name
Test status
Simulation time 7283804989 ps
CPU time 32.24 seconds
Started Jul 01 06:36:12 PM PDT 24
Finished Jul 01 06:36:46 PM PDT 24
Peak memory 199132 kb
Host smart-505680c9-abbc-44e2-b056-02261a2cf266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601016059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.601016059
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2390055240
Short name T193
Test name
Test status
Simulation time 127692168207 ps
CPU time 399.78 seconds
Started Jul 01 06:36:14 PM PDT 24
Finished Jul 01 06:42:55 PM PDT 24
Peak memory 199912 kb
Host smart-c272c62c-155d-41aa-8f04-2078baf9c85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390055240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2390055240
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2051432312
Short name T705
Test name
Test status
Simulation time 2328932049 ps
CPU time 4.62 seconds
Started Jul 01 06:36:12 PM PDT 24
Finished Jul 01 06:36:18 PM PDT 24
Peak memory 196512 kb
Host smart-67e15654-3340-4ca8-a8dd-11f3f0953a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051432312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2051432312
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.736322034
Short name T683
Test name
Test status
Simulation time 6317280965 ps
CPU time 12.56 seconds
Started Jul 01 06:36:12 PM PDT 24
Finished Jul 01 06:36:26 PM PDT 24
Peak memory 199836 kb
Host smart-12b8fbe9-a757-4b9c-bb1d-b282e2d79820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736322034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.736322034
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.496870315
Short name T911
Test name
Test status
Simulation time 396033743879 ps
CPU time 497.36 seconds
Started Jul 01 06:36:19 PM PDT 24
Finished Jul 01 06:44:37 PM PDT 24
Peak memory 199984 kb
Host smart-b7421aae-2739-4486-9c57-eb741a9000ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496870315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.496870315
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2389812300
Short name T1078
Test name
Test status
Simulation time 19674589680 ps
CPU time 236.52 seconds
Started Jul 01 06:36:12 PM PDT 24
Finished Jul 01 06:40:10 PM PDT 24
Peak memory 215824 kb
Host smart-0e605e5e-5392-4f86-ae50-b7232b36d9be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389812300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2389812300
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2386063621
Short name T436
Test name
Test status
Simulation time 2448787150 ps
CPU time 2.41 seconds
Started Jul 01 06:36:13 PM PDT 24
Finished Jul 01 06:36:17 PM PDT 24
Peak memory 199988 kb
Host smart-714c7b44-7d4e-4f7c-b87b-b2132bdbca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386063621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2386063621
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.612415915
Short name T972
Test name
Test status
Simulation time 23934756489 ps
CPU time 36.82 seconds
Started Jul 01 06:36:11 PM PDT 24
Finished Jul 01 06:36:48 PM PDT 24
Peak memory 199884 kb
Host smart-ac993802-c553-4614-a6f9-93b5d9ca1b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612415915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.612415915
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3913400339
Short name T578
Test name
Test status
Simulation time 14695742783 ps
CPU time 22.54 seconds
Started Jul 01 06:41:53 PM PDT 24
Finished Jul 01 06:42:18 PM PDT 24
Peak memory 199768 kb
Host smart-5f8249c9-ad2b-41df-9697-ced0db8efd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913400339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3913400339
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.361061150
Short name T1011
Test name
Test status
Simulation time 67789159930 ps
CPU time 49.19 seconds
Started Jul 01 06:41:52 PM PDT 24
Finished Jul 01 06:42:44 PM PDT 24
Peak memory 200080 kb
Host smart-d43e7adc-eec7-49eb-9302-b87687d10068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361061150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.361061150
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3216503654
Short name T81
Test name
Test status
Simulation time 87684546787 ps
CPU time 71.44 seconds
Started Jul 01 06:41:52 PM PDT 24
Finished Jul 01 06:43:06 PM PDT 24
Peak memory 199940 kb
Host smart-e079742d-9738-4ea9-aaca-06354a77e94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216503654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3216503654
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3527931701
Short name T180
Test name
Test status
Simulation time 124316913311 ps
CPU time 65.47 seconds
Started Jul 01 06:41:52 PM PDT 24
Finished Jul 01 06:43:00 PM PDT 24
Peak memory 200024 kb
Host smart-f504d535-8108-437b-85f8-fe4ed13d63e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527931701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3527931701
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3324069509
Short name T198
Test name
Test status
Simulation time 51782384733 ps
CPU time 73.98 seconds
Started Jul 01 06:41:59 PM PDT 24
Finished Jul 01 06:43:14 PM PDT 24
Peak memory 199952 kb
Host smart-c46d386d-80ed-4398-8737-50c4de1986d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324069509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3324069509
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1925498005
Short name T825
Test name
Test status
Simulation time 81461194541 ps
CPU time 89.71 seconds
Started Jul 01 06:42:00 PM PDT 24
Finished Jul 01 06:43:30 PM PDT 24
Peak memory 199904 kb
Host smart-a5b1532a-b6e3-44c3-9c2d-a4c0ca9d85c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925498005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1925498005
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1561229979
Short name T192
Test name
Test status
Simulation time 26411244686 ps
CPU time 49.2 seconds
Started Jul 01 06:41:58 PM PDT 24
Finished Jul 01 06:42:48 PM PDT 24
Peak memory 200080 kb
Host smart-92809093-fc7b-4c9b-baa2-bd7a060cb598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561229979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1561229979
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.537573356
Short name T916
Test name
Test status
Simulation time 83158977799 ps
CPU time 83.68 seconds
Started Jul 01 06:41:58 PM PDT 24
Finished Jul 01 06:43:23 PM PDT 24
Peak memory 199980 kb
Host smart-e1174d82-6c68-43c3-919d-4282e45ab423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537573356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.537573356
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.889808254
Short name T540
Test name
Test status
Simulation time 33787276971 ps
CPU time 17.14 seconds
Started Jul 01 06:41:58 PM PDT 24
Finished Jul 01 06:42:16 PM PDT 24
Peak memory 200000 kb
Host smart-552351ea-11d8-44ff-8723-3f19dbe48ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889808254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.889808254
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2012260528
Short name T737
Test name
Test status
Simulation time 208473934085 ps
CPU time 344.04 seconds
Started Jul 01 06:41:59 PM PDT 24
Finished Jul 01 06:47:44 PM PDT 24
Peak memory 199940 kb
Host smart-2a51489c-20b8-4a46-aea1-555e5aa65ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012260528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2012260528
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2545633220
Short name T856
Test name
Test status
Simulation time 42156888 ps
CPU time 0.57 seconds
Started Jul 01 06:36:24 PM PDT 24
Finished Jul 01 06:36:25 PM PDT 24
Peak memory 195320 kb
Host smart-f4e8d194-9aae-4937-948c-aaaa1007d393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545633220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2545633220
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.190348634
Short name T155
Test name
Test status
Simulation time 193849230803 ps
CPU time 304.31 seconds
Started Jul 01 06:36:22 PM PDT 24
Finished Jul 01 06:41:28 PM PDT 24
Peak memory 200000 kb
Host smart-b579c517-f451-4d7f-9ef3-1ea2282f4073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190348634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.190348634
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1165569764
Short name T290
Test name
Test status
Simulation time 178328952290 ps
CPU time 72.16 seconds
Started Jul 01 06:36:22 PM PDT 24
Finished Jul 01 06:37:36 PM PDT 24
Peak memory 199960 kb
Host smart-23d73523-4696-4e4d-82a2-def57bb3323d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165569764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1165569764
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.570852236
Short name T200
Test name
Test status
Simulation time 26457057947 ps
CPU time 52.16 seconds
Started Jul 01 06:36:18 PM PDT 24
Finished Jul 01 06:37:12 PM PDT 24
Peak memory 199992 kb
Host smart-178609ef-c2a4-4be5-95d1-0119b17ea3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570852236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.570852236
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.311545745
Short name T377
Test name
Test status
Simulation time 85294350389 ps
CPU time 285.92 seconds
Started Jul 01 06:36:25 PM PDT 24
Finished Jul 01 06:41:12 PM PDT 24
Peak memory 200000 kb
Host smart-5bfa42a6-e462-4325-84f8-89306a7eb59b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311545745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.311545745
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2482765760
Short name T610
Test name
Test status
Simulation time 2190646952 ps
CPU time 3.86 seconds
Started Jul 01 06:36:25 PM PDT 24
Finished Jul 01 06:36:30 PM PDT 24
Peak memory 197268 kb
Host smart-7b88e890-a649-4722-86a5-f04dcab2b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482765760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2482765760
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.2762820372
Short name T331
Test name
Test status
Simulation time 7606290075 ps
CPU time 88.61 seconds
Started Jul 01 06:36:25 PM PDT 24
Finished Jul 01 06:37:55 PM PDT 24
Peak memory 199984 kb
Host smart-4eee1266-3dea-43bc-ad9c-23e717bf39e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2762820372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2762820372
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1317606731
Short name T364
Test name
Test status
Simulation time 6673882754 ps
CPU time 55.67 seconds
Started Jul 01 06:36:20 PM PDT 24
Finished Jul 01 06:37:17 PM PDT 24
Peak memory 199168 kb
Host smart-25cac88b-554d-4675-8a58-e6107aae1841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317606731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1317606731
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2836058358
Short name T168
Test name
Test status
Simulation time 95560423450 ps
CPU time 150.84 seconds
Started Jul 01 06:36:18 PM PDT 24
Finished Jul 01 06:38:49 PM PDT 24
Peak memory 200084 kb
Host smart-981139a7-ca79-46b0-a552-535b45180606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836058358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2836058358
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.781395136
Short name T816
Test name
Test status
Simulation time 34723370358 ps
CPU time 14.24 seconds
Started Jul 01 06:36:19 PM PDT 24
Finished Jul 01 06:36:35 PM PDT 24
Peak memory 195696 kb
Host smart-80721e4f-6625-4819-a50a-d5d04142e054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781395136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.781395136
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2631480081
Short name T734
Test name
Test status
Simulation time 305858557 ps
CPU time 1.63 seconds
Started Jul 01 06:36:19 PM PDT 24
Finished Jul 01 06:36:22 PM PDT 24
Peak memory 198432 kb
Host smart-536de0e1-d8c0-4c42-8120-4a6a8cb964d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631480081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2631480081
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2529600409
Short name T58
Test name
Test status
Simulation time 67680304872 ps
CPU time 565.2 seconds
Started Jul 01 06:36:25 PM PDT 24
Finished Jul 01 06:45:52 PM PDT 24
Peak memory 212848 kb
Host smart-8c18e04f-b34c-44f9-bd05-572047113c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529600409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2529600409
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.654450795
Short name T9
Test name
Test status
Simulation time 3170998135 ps
CPU time 2.99 seconds
Started Jul 01 06:36:18 PM PDT 24
Finished Jul 01 06:36:23 PM PDT 24
Peak memory 198692 kb
Host smart-04c674c8-a1c7-4d8c-9797-e59bc8c7e02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654450795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.654450795
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.283147880
Short name T527
Test name
Test status
Simulation time 63379537792 ps
CPU time 34.78 seconds
Started Jul 01 06:36:19 PM PDT 24
Finished Jul 01 06:36:55 PM PDT 24
Peak memory 199980 kb
Host smart-d8cc3b31-ba4e-4f4d-92c1-8431fdf4f65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283147880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.283147880
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1896442572
Short name T217
Test name
Test status
Simulation time 17102459392 ps
CPU time 26.26 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:42:34 PM PDT 24
Peak memory 200064 kb
Host smart-e3df3768-c1ec-4da2-b3fc-d89629b39489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896442572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1896442572
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2063908223
Short name T405
Test name
Test status
Simulation time 34053157677 ps
CPU time 19.6 seconds
Started Jul 01 06:42:08 PM PDT 24
Finished Jul 01 06:42:29 PM PDT 24
Peak memory 197316 kb
Host smart-ddccd77d-7640-49ea-9259-1d301d3a5fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063908223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2063908223
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2251519322
Short name T62
Test name
Test status
Simulation time 115618767057 ps
CPU time 95.9 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:43:44 PM PDT 24
Peak memory 199928 kb
Host smart-2f9a73b1-fb29-4221-b368-effe56567016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251519322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2251519322
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1026749804
Short name T464
Test name
Test status
Simulation time 50893411873 ps
CPU time 35.23 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:42:44 PM PDT 24
Peak memory 200000 kb
Host smart-6081ddf4-efe0-4964-9bcc-dfdc8fc0b960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026749804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1026749804
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.4156949882
Short name T729
Test name
Test status
Simulation time 20600424753 ps
CPU time 16.73 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:42:25 PM PDT 24
Peak memory 200076 kb
Host smart-95ce7f36-e92b-4b75-8680-f0772ecbc1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156949882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.4156949882
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.4057270217
Short name T1009
Test name
Test status
Simulation time 104399670412 ps
CPU time 108.78 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:43:58 PM PDT 24
Peak memory 200000 kb
Host smart-097ab270-4c2c-4711-9d3f-c8da52e4f1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057270217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.4057270217
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3355189193
Short name T898
Test name
Test status
Simulation time 41833264150 ps
CPU time 36.1 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:42:44 PM PDT 24
Peak memory 199956 kb
Host smart-6f27c91a-2e0d-483f-9b49-775a5ad0433f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355189193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3355189193
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.4109619044
Short name T129
Test name
Test status
Simulation time 24268190028 ps
CPU time 21.89 seconds
Started Jul 01 06:42:09 PM PDT 24
Finished Jul 01 06:42:32 PM PDT 24
Peak memory 199948 kb
Host smart-da07dc8b-0d6e-4140-8abb-c998851d0205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109619044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.4109619044
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1136682909
Short name T1084
Test name
Test status
Simulation time 109077064732 ps
CPU time 41.16 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:42:50 PM PDT 24
Peak memory 200000 kb
Host smart-9d6f9f3c-4a97-4c3c-9379-24a19b59f8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136682909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1136682909
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.860531358
Short name T534
Test name
Test status
Simulation time 32915974 ps
CPU time 0.55 seconds
Started Jul 01 06:36:32 PM PDT 24
Finished Jul 01 06:36:33 PM PDT 24
Peak memory 195344 kb
Host smart-bae0436c-6867-4a83-b56c-d2004149481c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860531358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.860531358
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1653684505
Short name T642
Test name
Test status
Simulation time 68037132539 ps
CPU time 28.16 seconds
Started Jul 01 06:36:28 PM PDT 24
Finished Jul 01 06:36:57 PM PDT 24
Peak memory 199920 kb
Host smart-aafeffce-a5c1-40f5-b03c-e47bee73bc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653684505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1653684505
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3782523822
Short name T384
Test name
Test status
Simulation time 41968089387 ps
CPU time 70.86 seconds
Started Jul 01 06:36:25 PM PDT 24
Finished Jul 01 06:37:37 PM PDT 24
Peak memory 200004 kb
Host smart-c2a7374c-5bfc-4071-9b15-d3b11642dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782523822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3782523822
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3729553242
Short name T1019
Test name
Test status
Simulation time 99213512719 ps
CPU time 13.52 seconds
Started Jul 01 06:36:27 PM PDT 24
Finished Jul 01 06:36:41 PM PDT 24
Peak memory 199836 kb
Host smart-ede76191-58e3-4a47-96ba-c82e1131f926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729553242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3729553242
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3919596700
Short name T285
Test name
Test status
Simulation time 44341965695 ps
CPU time 61.11 seconds
Started Jul 01 06:36:26 PM PDT 24
Finished Jul 01 06:37:28 PM PDT 24
Peak memory 199948 kb
Host smart-48b26eae-9386-4bbc-a4b0-a9db48faec3b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919596700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3919596700
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3777231333
Short name T1048
Test name
Test status
Simulation time 72549025188 ps
CPU time 715.07 seconds
Started Jul 01 06:36:35 PM PDT 24
Finished Jul 01 06:48:31 PM PDT 24
Peak memory 199932 kb
Host smart-8f6dde89-8c70-4421-8164-628a344ca975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777231333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3777231333
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1239146672
Short name T360
Test name
Test status
Simulation time 6083781120 ps
CPU time 14.52 seconds
Started Jul 01 06:36:34 PM PDT 24
Finished Jul 01 06:36:50 PM PDT 24
Peak memory 199828 kb
Host smart-e3f9dfa1-2bb6-4dae-b246-75141d4f8206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239146672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1239146672
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.716005117
Short name T947
Test name
Test status
Simulation time 18775090864 ps
CPU time 227.56 seconds
Started Jul 01 06:36:34 PM PDT 24
Finished Jul 01 06:40:23 PM PDT 24
Peak memory 199964 kb
Host smart-f66cd7e0-006a-438d-abcb-3a4932fa4245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716005117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.716005117
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1919030489
Short name T721
Test name
Test status
Simulation time 3412451014 ps
CPU time 22.76 seconds
Started Jul 01 06:36:24 PM PDT 24
Finished Jul 01 06:36:48 PM PDT 24
Peak memory 198948 kb
Host smart-2a60b90b-3bde-49bf-95fd-225f1cb9e8fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919030489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1919030489
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.627997087
Short name T976
Test name
Test status
Simulation time 114756831335 ps
CPU time 281.9 seconds
Started Jul 01 06:36:32 PM PDT 24
Finished Jul 01 06:41:15 PM PDT 24
Peak memory 200044 kb
Host smart-9272ab16-cc6d-4ff6-b9b2-26b0a77b39bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627997087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.627997087
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.775142289
Short name T418
Test name
Test status
Simulation time 4366636587 ps
CPU time 2.25 seconds
Started Jul 01 06:36:32 PM PDT 24
Finished Jul 01 06:36:35 PM PDT 24
Peak memory 196360 kb
Host smart-175f8fb6-5e04-466f-b575-216433ddd01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775142289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.775142289
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.715250013
Short name T558
Test name
Test status
Simulation time 648366405 ps
CPU time 2.36 seconds
Started Jul 01 06:36:26 PM PDT 24
Finished Jul 01 06:36:30 PM PDT 24
Peak memory 198728 kb
Host smart-63393c04-32f6-47f6-b7df-7332f8096144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715250013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.715250013
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.4253676842
Short name T431
Test name
Test status
Simulation time 7853998909 ps
CPU time 10.52 seconds
Started Jul 01 06:36:32 PM PDT 24
Finished Jul 01 06:36:44 PM PDT 24
Peak memory 199912 kb
Host smart-788a3aac-734f-42b1-aa62-db768f4b081d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253676842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.4253676842
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1220096444
Short name T946
Test name
Test status
Simulation time 8932108242 ps
CPU time 14.31 seconds
Started Jul 01 06:36:24 PM PDT 24
Finished Jul 01 06:36:39 PM PDT 24
Peak memory 199748 kb
Host smart-d82525d6-4abd-429a-b1a8-47685f7e823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220096444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1220096444
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2006700900
Short name T1024
Test name
Test status
Simulation time 69838856234 ps
CPU time 58.78 seconds
Started Jul 01 06:42:06 PM PDT 24
Finished Jul 01 06:43:06 PM PDT 24
Peak memory 200092 kb
Host smart-296b2b60-96d9-499f-9f2d-ba8857b532d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006700900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2006700900
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2373610367
Short name T611
Test name
Test status
Simulation time 87213481914 ps
CPU time 279.34 seconds
Started Jul 01 06:42:06 PM PDT 24
Finished Jul 01 06:46:46 PM PDT 24
Peak memory 200024 kb
Host smart-8ead271b-fa47-4f7e-9fef-1503fab04291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373610367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2373610367
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2744301277
Short name T835
Test name
Test status
Simulation time 213445196640 ps
CPU time 441.1 seconds
Started Jul 01 06:42:08 PM PDT 24
Finished Jul 01 06:49:31 PM PDT 24
Peak memory 200040 kb
Host smart-0b4e72fb-a778-46e3-b732-52659e9ed08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744301277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2744301277
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1792996548
Short name T618
Test name
Test status
Simulation time 117514775308 ps
CPU time 166.07 seconds
Started Jul 01 06:42:08 PM PDT 24
Finished Jul 01 06:44:55 PM PDT 24
Peak memory 199948 kb
Host smart-6da7b826-32da-489e-afb8-bb6f295dc653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792996548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1792996548
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2878473141
Short name T820
Test name
Test status
Simulation time 165486248676 ps
CPU time 30.82 seconds
Started Jul 01 06:42:08 PM PDT 24
Finished Jul 01 06:42:40 PM PDT 24
Peak memory 200068 kb
Host smart-24dad6f4-37a7-4125-b8e9-a0877035aad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878473141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2878473141
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1757678877
Short name T403
Test name
Test status
Simulation time 32182175960 ps
CPU time 20.64 seconds
Started Jul 01 06:42:08 PM PDT 24
Finished Jul 01 06:42:30 PM PDT 24
Peak memory 200128 kb
Host smart-b72f1c02-388f-40b5-a9f4-bdff7e22adf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757678877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1757678877
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1025552454
Short name T929
Test name
Test status
Simulation time 26880187729 ps
CPU time 57.72 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:43:06 PM PDT 24
Peak memory 200060 kb
Host smart-798905a8-8d4b-4c5b-9f6a-6f7aebbd7fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025552454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1025552454
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3971984945
Short name T749
Test name
Test status
Simulation time 176514578302 ps
CPU time 144.3 seconds
Started Jul 01 06:42:12 PM PDT 24
Finished Jul 01 06:44:37 PM PDT 24
Peak memory 199920 kb
Host smart-25cbaee5-2d0c-4af0-92cf-0a8e745cb034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971984945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3971984945
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3176887649
Short name T61
Test name
Test status
Simulation time 29569148103 ps
CPU time 43.73 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:42:52 PM PDT 24
Peak memory 200124 kb
Host smart-20a4eb5a-5f95-41fd-8462-493e42eb1afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176887649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3176887649
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1556325295
Short name T498
Test name
Test status
Simulation time 16780514 ps
CPU time 0.53 seconds
Started Jul 01 06:36:43 PM PDT 24
Finished Jul 01 06:36:44 PM PDT 24
Peak memory 194336 kb
Host smart-fec58248-6b67-4f38-8e30-b70dd813c271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556325295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1556325295
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2602689385
Short name T915
Test name
Test status
Simulation time 113836454879 ps
CPU time 59.15 seconds
Started Jul 01 06:36:33 PM PDT 24
Finished Jul 01 06:37:33 PM PDT 24
Peak memory 199996 kb
Host smart-e67f47a4-2a5d-4f77-8151-496830055d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602689385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2602689385
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.4135111486
Short name T600
Test name
Test status
Simulation time 19992416639 ps
CPU time 35.14 seconds
Started Jul 01 06:36:40 PM PDT 24
Finished Jul 01 06:37:16 PM PDT 24
Peak memory 200124 kb
Host smart-96a8d85f-9882-4d2f-8c2a-5c7ad752c261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135111486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.4135111486
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.4262096876
Short name T196
Test name
Test status
Simulation time 29696599231 ps
CPU time 48.9 seconds
Started Jul 01 06:36:43 PM PDT 24
Finished Jul 01 06:37:33 PM PDT 24
Peak memory 200020 kb
Host smart-25c498da-e4eb-4be2-a81f-fc74e350c81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262096876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.4262096876
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.689141228
Short name T133
Test name
Test status
Simulation time 73594092887 ps
CPU time 142.8 seconds
Started Jul 01 06:36:39 PM PDT 24
Finished Jul 01 06:39:03 PM PDT 24
Peak memory 199980 kb
Host smart-1e59986e-f1c3-49f0-96e9-9528651a8dc9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689141228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.689141228
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3951876498
Short name T647
Test name
Test status
Simulation time 90395917839 ps
CPU time 139.24 seconds
Started Jul 01 06:36:39 PM PDT 24
Finished Jul 01 06:38:59 PM PDT 24
Peak memory 199980 kb
Host smart-fda24c35-5463-43ee-a530-f14ad9c6c0de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951876498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3951876498
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3913810254
Short name T417
Test name
Test status
Simulation time 4003762950 ps
CPU time 3.78 seconds
Started Jul 01 06:36:38 PM PDT 24
Finished Jul 01 06:36:43 PM PDT 24
Peak memory 195848 kb
Host smart-74547cc0-e284-41c3-ab44-6d987028a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913810254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3913810254
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.1178015869
Short name T659
Test name
Test status
Simulation time 8655873782 ps
CPU time 81.18 seconds
Started Jul 01 06:36:43 PM PDT 24
Finished Jul 01 06:38:05 PM PDT 24
Peak memory 199936 kb
Host smart-fb90cc4c-7034-41a7-a1fe-447cbeca2f90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178015869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1178015869
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1832035545
Short name T921
Test name
Test status
Simulation time 1707422500 ps
CPU time 4.66 seconds
Started Jul 01 06:36:38 PM PDT 24
Finished Jul 01 06:36:43 PM PDT 24
Peak memory 198988 kb
Host smart-2aa9e746-331e-4968-bef8-f9ddb3715e69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832035545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1832035545
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3951913747
Short name T1008
Test name
Test status
Simulation time 17607075509 ps
CPU time 7.94 seconds
Started Jul 01 06:36:39 PM PDT 24
Finished Jul 01 06:36:48 PM PDT 24
Peak memory 199740 kb
Host smart-87aaa665-d840-48ba-928b-ac87b269df09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951913747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3951913747
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1221510905
Short name T531
Test name
Test status
Simulation time 37195382055 ps
CPU time 15.81 seconds
Started Jul 01 06:36:38 PM PDT 24
Finished Jul 01 06:36:55 PM PDT 24
Peak memory 195944 kb
Host smart-600025c7-6387-4205-9d76-23fe65b1678c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221510905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1221510905
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2703570232
Short name T382
Test name
Test status
Simulation time 559748819 ps
CPU time 1.01 seconds
Started Jul 01 06:36:32 PM PDT 24
Finished Jul 01 06:36:34 PM PDT 24
Peak memory 198444 kb
Host smart-11c754b1-4215-4119-addc-b2ef5c8d0e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703570232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2703570232
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3426375140
Short name T741
Test name
Test status
Simulation time 12513794510 ps
CPU time 158.71 seconds
Started Jul 01 06:36:43 PM PDT 24
Finished Jul 01 06:39:23 PM PDT 24
Peak memory 216544 kb
Host smart-39a9789d-8d06-4638-83b3-bd579986624b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426375140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3426375140
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3765378354
Short name T829
Test name
Test status
Simulation time 842017866 ps
CPU time 2.04 seconds
Started Jul 01 06:36:39 PM PDT 24
Finished Jul 01 06:36:42 PM PDT 24
Peak memory 198816 kb
Host smart-d0e602a9-ceea-4489-809a-a5b6691dc92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765378354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3765378354
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3989976810
Short name T330
Test name
Test status
Simulation time 254934236996 ps
CPU time 38.39 seconds
Started Jul 01 06:36:33 PM PDT 24
Finished Jul 01 06:37:12 PM PDT 24
Peak memory 200108 kb
Host smart-079dd1ae-2be6-4d4e-9391-00e38a853ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989976810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3989976810
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.610574602
Short name T1028
Test name
Test status
Simulation time 86418272224 ps
CPU time 145.43 seconds
Started Jul 01 06:42:07 PM PDT 24
Finished Jul 01 06:44:34 PM PDT 24
Peak memory 200012 kb
Host smart-97a82e04-cad6-4277-baa4-c88fd7a166fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610574602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.610574602
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1708769911
Short name T230
Test name
Test status
Simulation time 34548723852 ps
CPU time 33.3 seconds
Started Jul 01 06:42:21 PM PDT 24
Finished Jul 01 06:42:56 PM PDT 24
Peak memory 200004 kb
Host smart-63061588-aef3-479d-9cc2-9d2fcf6a10e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708769911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1708769911
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3344566582
Short name T510
Test name
Test status
Simulation time 108042802901 ps
CPU time 40.61 seconds
Started Jul 01 06:42:19 PM PDT 24
Finished Jul 01 06:43:01 PM PDT 24
Peak memory 200004 kb
Host smart-b26e2615-27ad-43d3-9038-a331d762dc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344566582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3344566582
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.551383752
Short name T12
Test name
Test status
Simulation time 35436712702 ps
CPU time 16.54 seconds
Started Jul 01 06:42:20 PM PDT 24
Finished Jul 01 06:42:37 PM PDT 24
Peak memory 199772 kb
Host smart-6e11cc96-0ec9-455d-8cd4-155843822400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551383752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.551383752
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2113726595
Short name T147
Test name
Test status
Simulation time 27885306818 ps
CPU time 30.43 seconds
Started Jul 01 06:42:19 PM PDT 24
Finished Jul 01 06:42:50 PM PDT 24
Peak memory 199932 kb
Host smart-2d74b284-53cc-4929-9324-ea6565781ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113726595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2113726595
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3695884207
Short name T443
Test name
Test status
Simulation time 72155931903 ps
CPU time 58.41 seconds
Started Jul 01 06:42:21 PM PDT 24
Finished Jul 01 06:43:20 PM PDT 24
Peak memory 200076 kb
Host smart-3fc4f09f-8b56-446d-bd1a-114483ab05eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695884207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3695884207
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.455439536
Short name T140
Test name
Test status
Simulation time 179031902490 ps
CPU time 261.46 seconds
Started Jul 01 06:42:19 PM PDT 24
Finished Jul 01 06:46:42 PM PDT 24
Peak memory 200080 kb
Host smart-eb95d56d-cd5a-42bc-bc39-9b0d099aab75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455439536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.455439536
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1874831964
Short name T982
Test name
Test status
Simulation time 222434738565 ps
CPU time 24.39 seconds
Started Jul 01 06:42:21 PM PDT 24
Finished Jul 01 06:42:47 PM PDT 24
Peak memory 200040 kb
Host smart-67eb2530-9db6-4490-a480-5e1e8954d925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874831964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1874831964
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3673502240
Short name T359
Test name
Test status
Simulation time 23461903 ps
CPU time 0.58 seconds
Started Jul 01 06:36:45 PM PDT 24
Finished Jul 01 06:36:47 PM PDT 24
Peak memory 195604 kb
Host smart-229928bc-266d-4435-aa10-400de4cfe26e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673502240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3673502240
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3993427528
Short name T1059
Test name
Test status
Simulation time 43888835045 ps
CPU time 17.63 seconds
Started Jul 01 06:36:38 PM PDT 24
Finished Jul 01 06:36:57 PM PDT 24
Peak memory 199960 kb
Host smart-0181f0cb-9a59-4554-907c-79a9e0bcea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993427528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3993427528
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1235862889
Short name T1017
Test name
Test status
Simulation time 17151038171 ps
CPU time 7.68 seconds
Started Jul 01 06:36:44 PM PDT 24
Finished Jul 01 06:36:53 PM PDT 24
Peak memory 199188 kb
Host smart-0e9c385b-6f6d-47a2-9908-96f6f16fbfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235862889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1235862889
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3640367974
Short name T350
Test name
Test status
Simulation time 43436670453 ps
CPU time 33.37 seconds
Started Jul 01 06:36:43 PM PDT 24
Finished Jul 01 06:37:17 PM PDT 24
Peak memory 199952 kb
Host smart-2fa61754-3eee-46fc-9578-2f15e4ad8941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640367974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3640367974
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.4246949721
Short name T374
Test name
Test status
Simulation time 3927044530 ps
CPU time 12.22 seconds
Started Jul 01 06:36:47 PM PDT 24
Finished Jul 01 06:37:00 PM PDT 24
Peak memory 199800 kb
Host smart-1c399985-f840-4567-bf07-ffa5329ced58
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246949721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4246949721
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1977572135
Short name T376
Test name
Test status
Simulation time 89856794106 ps
CPU time 565.96 seconds
Started Jul 01 06:36:44 PM PDT 24
Finished Jul 01 06:46:11 PM PDT 24
Peak memory 199992 kb
Host smart-adc87b66-aad1-4227-92d6-fab7fb090c85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1977572135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1977572135
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2253166808
Short name T794
Test name
Test status
Simulation time 5110120289 ps
CPU time 7.75 seconds
Started Jul 01 06:36:44 PM PDT 24
Finished Jul 01 06:36:53 PM PDT 24
Peak memory 198908 kb
Host smart-6defc83f-b561-410f-ae27-ff31b368f7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253166808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2253166808
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.3896718182
Short name T765
Test name
Test status
Simulation time 26275082865 ps
CPU time 713.83 seconds
Started Jul 01 06:36:47 PM PDT 24
Finished Jul 01 06:48:42 PM PDT 24
Peak memory 199956 kb
Host smart-5756a89b-d169-4f88-a7c9-d78598dfe573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896718182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3896718182
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3513124019
Short name T463
Test name
Test status
Simulation time 6266174778 ps
CPU time 11.55 seconds
Started Jul 01 06:36:44 PM PDT 24
Finished Jul 01 06:36:57 PM PDT 24
Peak memory 199252 kb
Host smart-0a635c36-cac1-42ba-a70e-c395b8189aad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513124019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3513124019
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1326350926
Short name T662
Test name
Test status
Simulation time 18237372340 ps
CPU time 6.87 seconds
Started Jul 01 06:36:44 PM PDT 24
Finished Jul 01 06:36:52 PM PDT 24
Peak memory 198680 kb
Host smart-f7a79375-b541-4161-a7d0-667a886cc980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326350926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1326350926
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1974549609
Short name T810
Test name
Test status
Simulation time 2741828191 ps
CPU time 4.4 seconds
Started Jul 01 06:36:44 PM PDT 24
Finished Jul 01 06:36:49 PM PDT 24
Peak memory 196424 kb
Host smart-dfef6aa1-093e-4d69-a078-c23b577195be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974549609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1974549609
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1026959463
Short name T521
Test name
Test status
Simulation time 695518648 ps
CPU time 3.13 seconds
Started Jul 01 06:36:39 PM PDT 24
Finished Jul 01 06:36:43 PM PDT 24
Peak memory 198752 kb
Host smart-df373d3c-8276-4425-892b-b6a0c6f918e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026959463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1026959463
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4127607174
Short name T53
Test name
Test status
Simulation time 74489927948 ps
CPU time 558.63 seconds
Started Jul 01 06:36:45 PM PDT 24
Finished Jul 01 06:46:05 PM PDT 24
Peak memory 216588 kb
Host smart-7cf37142-bf7e-4666-b54d-b5cacd1afa54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127607174 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4127607174
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.640727205
Short name T430
Test name
Test status
Simulation time 6941618946 ps
CPU time 17.83 seconds
Started Jul 01 06:36:46 PM PDT 24
Finished Jul 01 06:37:05 PM PDT 24
Peak memory 199828 kb
Host smart-43f1f1bf-5cbe-43a6-91fe-a02923d73af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640727205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.640727205
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1558850128
Short name T780
Test name
Test status
Simulation time 82384351408 ps
CPU time 269.91 seconds
Started Jul 01 06:36:39 PM PDT 24
Finished Jul 01 06:41:10 PM PDT 24
Peak memory 199984 kb
Host smart-188dfb52-c6dd-4b42-a23c-84410ae98b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558850128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1558850128
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3617014815
Short name T1070
Test name
Test status
Simulation time 36782479767 ps
CPU time 46.65 seconds
Started Jul 01 06:42:13 PM PDT 24
Finished Jul 01 06:43:01 PM PDT 24
Peak memory 199940 kb
Host smart-ef26c7d3-b3a8-4d48-adf6-77b50f9a5bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617014815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3617014815
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3893184759
Short name T232
Test name
Test status
Simulation time 66631877150 ps
CPU time 125.56 seconds
Started Jul 01 06:42:20 PM PDT 24
Finished Jul 01 06:44:27 PM PDT 24
Peak memory 199980 kb
Host smart-4b788263-9b40-438d-805f-2817b5e5ffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893184759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3893184759
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4061133579
Short name T383
Test name
Test status
Simulation time 16105588427 ps
CPU time 14.88 seconds
Started Jul 01 06:42:19 PM PDT 24
Finished Jul 01 06:42:35 PM PDT 24
Peak memory 200040 kb
Host smart-cdc65d0e-75e8-4075-82d0-6b5d7e2dca1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061133579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4061133579
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.582898010
Short name T918
Test name
Test status
Simulation time 96103503789 ps
CPU time 180.25 seconds
Started Jul 01 06:42:22 PM PDT 24
Finished Jul 01 06:45:23 PM PDT 24
Peak memory 199944 kb
Host smart-685bc950-e58b-4217-99ec-8ab69de22086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582898010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.582898010
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1435639255
Short name T769
Test name
Test status
Simulation time 43277111922 ps
CPU time 67.97 seconds
Started Jul 01 06:42:19 PM PDT 24
Finished Jul 01 06:43:28 PM PDT 24
Peak memory 200000 kb
Host smart-955fa0b1-17e3-4751-b51b-e3faf6435eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435639255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1435639255
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3809922599
Short name T38
Test name
Test status
Simulation time 138855988759 ps
CPU time 87.93 seconds
Started Jul 01 06:42:20 PM PDT 24
Finished Jul 01 06:43:49 PM PDT 24
Peak memory 199936 kb
Host smart-a13e575c-45f0-43b4-8db0-43b819086d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809922599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3809922599
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3276551455
Short name T731
Test name
Test status
Simulation time 126617841420 ps
CPU time 181.12 seconds
Started Jul 01 06:42:20 PM PDT 24
Finished Jul 01 06:45:22 PM PDT 24
Peak memory 199976 kb
Host smart-0f1b61ae-8edd-40a6-846d-3f337328ed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276551455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3276551455
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1600668485
Short name T837
Test name
Test status
Simulation time 64468440218 ps
CPU time 41.14 seconds
Started Jul 01 06:42:20 PM PDT 24
Finished Jul 01 06:43:03 PM PDT 24
Peak memory 200068 kb
Host smart-820f50fb-b4a3-4fce-9884-fbe4c7e76288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600668485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1600668485
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.908302037
Short name T956
Test name
Test status
Simulation time 88463326152 ps
CPU time 121.39 seconds
Started Jul 01 06:42:20 PM PDT 24
Finished Jul 01 06:44:22 PM PDT 24
Peak memory 200060 kb
Host smart-b9601fbd-c7ed-475d-b7e8-bee71a3a5cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908302037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.908302037
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.566279448
Short name T356
Test name
Test status
Simulation time 15861766 ps
CPU time 0.58 seconds
Started Jul 01 06:34:38 PM PDT 24
Finished Jul 01 06:34:42 PM PDT 24
Peak memory 195596 kb
Host smart-1544fe78-020f-4c5e-987f-dc9cd7feca2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566279448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.566279448
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2959979491
Short name T419
Test name
Test status
Simulation time 25640763388 ps
CPU time 45.85 seconds
Started Jul 01 06:34:32 PM PDT 24
Finished Jul 01 06:35:21 PM PDT 24
Peak memory 199988 kb
Host smart-04055871-1053-404a-b47e-cce0aee9f76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959979491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2959979491
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1246802893
Short name T1014
Test name
Test status
Simulation time 93986347346 ps
CPU time 32.2 seconds
Started Jul 01 06:34:40 PM PDT 24
Finished Jul 01 06:35:16 PM PDT 24
Peak memory 199180 kb
Host smart-22ea3677-5cb7-404d-ba6b-9bd880b836e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246802893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1246802893
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3242563281
Short name T889
Test name
Test status
Simulation time 55107691419 ps
CPU time 123.89 seconds
Started Jul 01 06:34:40 PM PDT 24
Finished Jul 01 06:36:48 PM PDT 24
Peak memory 200084 kb
Host smart-10a8c461-214e-4628-a042-5ec9587fa88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242563281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3242563281
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2405649324
Short name T650
Test name
Test status
Simulation time 56539891839 ps
CPU time 23.85 seconds
Started Jul 01 06:34:42 PM PDT 24
Finished Jul 01 06:35:10 PM PDT 24
Peak memory 199696 kb
Host smart-19c53b9d-0402-4b13-a5d8-381e6fac7be0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405649324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2405649324
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2682080817
Short name T441
Test name
Test status
Simulation time 236904598848 ps
CPU time 272.71 seconds
Started Jul 01 06:34:38 PM PDT 24
Finished Jul 01 06:39:13 PM PDT 24
Peak memory 199984 kb
Host smart-8a644da6-c3ee-451c-8ece-95f4c2fea650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682080817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2682080817
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2639941646
Short name T789
Test name
Test status
Simulation time 472994659 ps
CPU time 0.97 seconds
Started Jul 01 06:34:37 PM PDT 24
Finished Jul 01 06:34:41 PM PDT 24
Peak memory 195472 kb
Host smart-462e3b9f-1241-4255-a173-bb8ac2b2d7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639941646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2639941646
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.464931712
Short name T693
Test name
Test status
Simulation time 10072546497 ps
CPU time 123.84 seconds
Started Jul 01 06:34:41 PM PDT 24
Finished Jul 01 06:36:48 PM PDT 24
Peak memory 199868 kb
Host smart-18148421-634c-4289-9e06-5a051d68bd77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464931712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.464931712
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1098849765
Short name T805
Test name
Test status
Simulation time 5087487390 ps
CPU time 2.78 seconds
Started Jul 01 06:34:39 PM PDT 24
Finished Jul 01 06:34:45 PM PDT 24
Peak memory 199116 kb
Host smart-a3f00d3f-cfa1-455b-843f-41a13af26e7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098849765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1098849765
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1836608355
Short name T589
Test name
Test status
Simulation time 64533196196 ps
CPU time 27.14 seconds
Started Jul 01 06:34:44 PM PDT 24
Finished Jul 01 06:35:15 PM PDT 24
Peak memory 199896 kb
Host smart-6748c2c2-cf5a-403a-b589-7b9c25fa513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836608355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1836608355
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2104238104
Short name T767
Test name
Test status
Simulation time 652455318 ps
CPU time 1.64 seconds
Started Jul 01 06:34:40 PM PDT 24
Finished Jul 01 06:34:46 PM PDT 24
Peak memory 195324 kb
Host smart-265af264-b517-4a24-97ae-c87f1bc6c550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104238104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2104238104
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.4103604957
Short name T110
Test name
Test status
Simulation time 114873935 ps
CPU time 0.88 seconds
Started Jul 01 06:34:41 PM PDT 24
Finished Jul 01 06:34:46 PM PDT 24
Peak memory 218280 kb
Host smart-4ae25e98-030b-4e26-a94b-f0e277e9e933
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103604957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4103604957
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1404252628
Short name T751
Test name
Test status
Simulation time 633678899 ps
CPU time 2.07 seconds
Started Jul 01 06:34:34 PM PDT 24
Finished Jul 01 06:34:39 PM PDT 24
Peak memory 198676 kb
Host smart-30d47d14-7428-4f95-a74a-f179b88e3f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404252628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1404252628
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.30489292
Short name T1085
Test name
Test status
Simulation time 87086378117 ps
CPU time 42.24 seconds
Started Jul 01 06:34:37 PM PDT 24
Finished Jul 01 06:35:22 PM PDT 24
Peak memory 200052 kb
Host smart-c51a2717-93d8-4945-9cd0-906c9fc82a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30489292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.30489292
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1267943956
Short name T272
Test name
Test status
Simulation time 7745662490 ps
CPU time 15.41 seconds
Started Jul 01 06:34:39 PM PDT 24
Finished Jul 01 06:34:57 PM PDT 24
Peak memory 199988 kb
Host smart-c2ef2edf-ecf3-4c13-b6a9-652b725a5fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267943956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1267943956
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3774030369
Short name T1021
Test name
Test status
Simulation time 42229089550 ps
CPU time 395.95 seconds
Started Jul 01 06:34:37 PM PDT 24
Finished Jul 01 06:41:15 PM PDT 24
Peak memory 199920 kb
Host smart-7592fa56-acb3-43d7-ba45-3bae870ec818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774030369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3774030369
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.123339030
Short name T478
Test name
Test status
Simulation time 17216992 ps
CPU time 0.55 seconds
Started Jul 01 06:37:00 PM PDT 24
Finished Jul 01 06:37:02 PM PDT 24
Peak memory 194572 kb
Host smart-ce14134a-d4b5-48b7-813a-b376641373d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123339030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.123339030
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1244767065
Short name T43
Test name
Test status
Simulation time 25847500558 ps
CPU time 35.7 seconds
Started Jul 01 06:36:52 PM PDT 24
Finished Jul 01 06:37:29 PM PDT 24
Peak memory 200004 kb
Host smart-4ee50e1a-5726-437c-bea2-2d58933bafd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244767065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1244767065
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2462700053
Short name T836
Test name
Test status
Simulation time 34787471783 ps
CPU time 48.73 seconds
Started Jul 01 06:36:53 PM PDT 24
Finished Jul 01 06:37:43 PM PDT 24
Peak memory 199956 kb
Host smart-93ddd8d4-ab7b-4b47-82fb-2d12e1e483e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462700053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2462700053
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2396523772
Short name T709
Test name
Test status
Simulation time 164742269644 ps
CPU time 93.22 seconds
Started Jul 01 06:36:51 PM PDT 24
Finished Jul 01 06:38:25 PM PDT 24
Peak memory 199996 kb
Host smart-28f57d0b-f9e1-4b3c-8bca-dc349332ad1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396523772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2396523772
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.722838127
Short name T535
Test name
Test status
Simulation time 309166371417 ps
CPU time 282.24 seconds
Started Jul 01 06:36:51 PM PDT 24
Finished Jul 01 06:41:35 PM PDT 24
Peak memory 199916 kb
Host smart-25d36f1e-52cf-4a8d-be58-a6ba9fdf0557
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722838127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.722838127
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1630731526
Short name T587
Test name
Test status
Simulation time 100942160124 ps
CPU time 147.27 seconds
Started Jul 01 06:36:58 PM PDT 24
Finished Jul 01 06:39:26 PM PDT 24
Peak memory 199964 kb
Host smart-c4a3c0b9-28b8-4c1d-8654-d274d3a12942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630731526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1630731526
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2165450237
Short name T1032
Test name
Test status
Simulation time 3710307938 ps
CPU time 6.47 seconds
Started Jul 01 06:36:51 PM PDT 24
Finished Jul 01 06:36:59 PM PDT 24
Peak memory 199540 kb
Host smart-c6f7ba47-ed24-4077-8ffb-493b11568904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165450237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2165450237
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.1570224638
Short name T533
Test name
Test status
Simulation time 13868522951 ps
CPU time 127.58 seconds
Started Jul 01 06:36:51 PM PDT 24
Finished Jul 01 06:39:00 PM PDT 24
Peak memory 199992 kb
Host smart-6a804be8-bd98-4d96-9ec7-f837353df0d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570224638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1570224638
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2880760239
Short name T920
Test name
Test status
Simulation time 4201816820 ps
CPU time 8.15 seconds
Started Jul 01 06:36:51 PM PDT 24
Finished Jul 01 06:37:00 PM PDT 24
Peak memory 198164 kb
Host smart-45027ab1-0a4b-466c-9aa0-591f2bda3ef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880760239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2880760239
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1671493270
Short name T293
Test name
Test status
Simulation time 122259733919 ps
CPU time 63.38 seconds
Started Jul 01 06:36:53 PM PDT 24
Finished Jul 01 06:37:57 PM PDT 24
Peak memory 200072 kb
Host smart-4b4aa632-861e-4e15-8baa-7aa9fed2e8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671493270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1671493270
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1733441850
Short name T525
Test name
Test status
Simulation time 36821657537 ps
CPU time 13.37 seconds
Started Jul 01 06:36:52 PM PDT 24
Finished Jul 01 06:37:06 PM PDT 24
Peak memory 195912 kb
Host smart-fe56171d-6b06-4ccd-b18b-79c56ef57e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733441850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1733441850
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.125821230
Short name T536
Test name
Test status
Simulation time 5372807392 ps
CPU time 11.42 seconds
Started Jul 01 06:36:45 PM PDT 24
Finished Jul 01 06:36:58 PM PDT 24
Peak memory 199836 kb
Host smart-35fedc4a-bcb0-4d61-bb34-d9558e0cf08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125821230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.125821230
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.40664894
Short name T1066
Test name
Test status
Simulation time 72990900727 ps
CPU time 110.04 seconds
Started Jul 01 06:37:01 PM PDT 24
Finished Jul 01 06:38:52 PM PDT 24
Peak memory 199964 kb
Host smart-7cba230e-f49f-49f3-8d6f-f4d635dc7872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.40664894
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1349283289
Short name T288
Test name
Test status
Simulation time 1298728463 ps
CPU time 1.2 seconds
Started Jul 01 06:36:54 PM PDT 24
Finished Jul 01 06:36:56 PM PDT 24
Peak memory 196892 kb
Host smart-df137504-aa9b-4d3f-8922-e227a266ada9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349283289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1349283289
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.4069389517
Short name T260
Test name
Test status
Simulation time 117871323650 ps
CPU time 24.96 seconds
Started Jul 01 06:36:44 PM PDT 24
Finished Jul 01 06:37:10 PM PDT 24
Peak memory 199932 kb
Host smart-9a6b21d8-0efe-45df-98d4-84cc40c3cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069389517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.4069389517
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1501007296
Short name T32
Test name
Test status
Simulation time 31592041257 ps
CPU time 16.61 seconds
Started Jul 01 06:42:24 PM PDT 24
Finished Jul 01 06:42:42 PM PDT 24
Peak memory 200072 kb
Host smart-dfd370c7-41a9-4573-8714-fa94a7e45678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501007296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1501007296
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2982181196
Short name T670
Test name
Test status
Simulation time 40715569922 ps
CPU time 67.72 seconds
Started Jul 01 06:42:25 PM PDT 24
Finished Jul 01 06:43:34 PM PDT 24
Peak memory 200016 kb
Host smart-5d86395c-1f81-44c6-83ae-8dedf42bf540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982181196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2982181196
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2017040185
Short name T624
Test name
Test status
Simulation time 68634293128 ps
CPU time 37.79 seconds
Started Jul 01 06:42:24 PM PDT 24
Finished Jul 01 06:43:04 PM PDT 24
Peak memory 200072 kb
Host smart-3cf4e1b4-2c94-4437-b019-f9a9c24b66d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017040185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2017040185
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.813411799
Short name T706
Test name
Test status
Simulation time 8471081416 ps
CPU time 7.52 seconds
Started Jul 01 06:42:24 PM PDT 24
Finished Jul 01 06:42:33 PM PDT 24
Peak memory 199800 kb
Host smart-eac43578-ac09-4eed-8879-96ca5edbfd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813411799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.813411799
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1908979350
Short name T218
Test name
Test status
Simulation time 108743850446 ps
CPU time 50.51 seconds
Started Jul 01 06:42:23 PM PDT 24
Finished Jul 01 06:43:15 PM PDT 24
Peak memory 200104 kb
Host smart-fc96ea98-ff61-48cf-8a84-061482b036d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908979350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1908979350
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3461183033
Short name T475
Test name
Test status
Simulation time 130153739590 ps
CPU time 99.72 seconds
Started Jul 01 06:42:27 PM PDT 24
Finished Jul 01 06:44:08 PM PDT 24
Peak memory 199960 kb
Host smart-49079f3b-8daf-4c4b-bcb5-077ac9c89083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461183033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3461183033
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1786138830
Short name T717
Test name
Test status
Simulation time 241185897910 ps
CPU time 97.63 seconds
Started Jul 01 06:42:24 PM PDT 24
Finished Jul 01 06:44:03 PM PDT 24
Peak memory 200056 kb
Host smart-da698c57-447c-42e1-85bf-33b8e76df79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786138830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1786138830
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1710511411
Short name T321
Test name
Test status
Simulation time 10198690363 ps
CPU time 16.2 seconds
Started Jul 01 06:42:24 PM PDT 24
Finished Jul 01 06:42:42 PM PDT 24
Peak memory 198828 kb
Host smart-5fc1c2b3-de27-4772-a34f-307472a9bbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710511411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1710511411
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1466422899
Short name T153
Test name
Test status
Simulation time 51829480044 ps
CPU time 29.99 seconds
Started Jul 01 06:42:23 PM PDT 24
Finished Jul 01 06:42:54 PM PDT 24
Peak memory 200000 kb
Host smart-53165575-6717-47f5-8b1f-e89f9d880b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466422899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1466422899
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2462683056
Short name T727
Test name
Test status
Simulation time 19363378 ps
CPU time 0.61 seconds
Started Jul 01 06:37:07 PM PDT 24
Finished Jul 01 06:37:09 PM PDT 24
Peak memory 195368 kb
Host smart-7810e793-5faa-4ff1-95bb-9462ada87395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462683056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2462683056
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2767781208
Short name T809
Test name
Test status
Simulation time 25522907147 ps
CPU time 19.84 seconds
Started Jul 01 06:37:00 PM PDT 24
Finished Jul 01 06:37:21 PM PDT 24
Peak memory 198756 kb
Host smart-090fdaa8-3d94-4f6f-9528-1bdcb65a13a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767781208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2767781208
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2824238023
Short name T977
Test name
Test status
Simulation time 75606512175 ps
CPU time 28.26 seconds
Started Jul 01 06:37:02 PM PDT 24
Finished Jul 01 06:37:31 PM PDT 24
Peak memory 199708 kb
Host smart-b472777b-e3b9-49ab-8d4b-3dd90a7d291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824238023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2824238023
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3709625440
Short name T686
Test name
Test status
Simulation time 136835687082 ps
CPU time 28.71 seconds
Started Jul 01 06:36:59 PM PDT 24
Finished Jul 01 06:37:28 PM PDT 24
Peak memory 199932 kb
Host smart-4b6204db-a31a-4dc3-b0f4-83e13ed723a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709625440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3709625440
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2365148221
Short name T594
Test name
Test status
Simulation time 22716906667 ps
CPU time 18.71 seconds
Started Jul 01 06:37:00 PM PDT 24
Finished Jul 01 06:37:20 PM PDT 24
Peak memory 198560 kb
Host smart-ae02b01f-41e8-4b61-a18e-a5585df042da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365148221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2365148221
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2621931957
Short name T421
Test name
Test status
Simulation time 91317005531 ps
CPU time 305.23 seconds
Started Jul 01 06:37:02 PM PDT 24
Finished Jul 01 06:42:08 PM PDT 24
Peak memory 199696 kb
Host smart-1241ecf4-9d9f-438d-bbe0-e0580d5fb518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621931957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2621931957
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3506776013
Short name T532
Test name
Test status
Simulation time 1907051524 ps
CPU time 1.78 seconds
Started Jul 01 06:37:00 PM PDT 24
Finished Jul 01 06:37:03 PM PDT 24
Peak memory 198000 kb
Host smart-273ef56f-e119-4f90-8323-d0cde4f47f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506776013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3506776013
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3571470174
Short name T634
Test name
Test status
Simulation time 28717172028 ps
CPU time 21.46 seconds
Started Jul 01 06:37:01 PM PDT 24
Finished Jul 01 06:37:24 PM PDT 24
Peak memory 199664 kb
Host smart-2a966ff8-057b-46a8-943c-3c7894fc6d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571470174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3571470174
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1286251573
Short name T983
Test name
Test status
Simulation time 21563929558 ps
CPU time 874.98 seconds
Started Jul 01 06:36:59 PM PDT 24
Finished Jul 01 06:51:36 PM PDT 24
Peak memory 199948 kb
Host smart-55b0a7bf-3305-468c-a26a-b2ab958c3d33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1286251573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1286251573
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2218348468
Short name T732
Test name
Test status
Simulation time 7211721184 ps
CPU time 16.45 seconds
Started Jul 01 06:37:00 PM PDT 24
Finished Jul 01 06:37:18 PM PDT 24
Peak memory 198180 kb
Host smart-782afbb6-e538-4607-87cc-7c40c3f72c36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2218348468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2218348468
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1800456082
Short name T547
Test name
Test status
Simulation time 44712136803 ps
CPU time 29.16 seconds
Started Jul 01 06:37:00 PM PDT 24
Finished Jul 01 06:37:31 PM PDT 24
Peak memory 198828 kb
Host smart-d0c11a95-486e-4af4-8a6b-e6b5953e61b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800456082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1800456082
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2048717422
Short name T1077
Test name
Test status
Simulation time 3776155853 ps
CPU time 6.14 seconds
Started Jul 01 06:37:00 PM PDT 24
Finished Jul 01 06:37:08 PM PDT 24
Peak memory 196424 kb
Host smart-f27b270b-5afd-4dd4-859c-be18b105a690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048717422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2048717422
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.237781012
Short name T880
Test name
Test status
Simulation time 436630602 ps
CPU time 1.64 seconds
Started Jul 01 06:37:01 PM PDT 24
Finished Jul 01 06:37:04 PM PDT 24
Peak memory 199588 kb
Host smart-cf289036-5587-4143-a305-ea1b61df61ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237781012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.237781012
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.620935182
Short name T334
Test name
Test status
Simulation time 241509706091 ps
CPU time 364.01 seconds
Started Jul 01 06:37:08 PM PDT 24
Finished Jul 01 06:43:13 PM PDT 24
Peak memory 199944 kb
Host smart-3692fd3c-8957-45e6-bc9a-b6f5a181c44d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620935182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.620935182
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1801807508
Short name T871
Test name
Test status
Simulation time 7028930242 ps
CPU time 20.67 seconds
Started Jul 01 06:37:00 PM PDT 24
Finished Jul 01 06:37:22 PM PDT 24
Peak memory 199560 kb
Host smart-834dd0f4-1cfc-4208-8b80-5129c2f2ffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801807508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1801807508
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.734713102
Short name T530
Test name
Test status
Simulation time 28710542532 ps
CPU time 70.58 seconds
Started Jul 01 06:36:59 PM PDT 24
Finished Jul 01 06:38:11 PM PDT 24
Peak memory 199996 kb
Host smart-9d55d4e7-d0e2-42f7-9c4c-e8bb6bececb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734713102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.734713102
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2445338869
Short name T781
Test name
Test status
Simulation time 44537867658 ps
CPU time 13.5 seconds
Started Jul 01 06:42:23 PM PDT 24
Finished Jul 01 06:42:38 PM PDT 24
Peak memory 199968 kb
Host smart-b70b0e6c-b5ea-443b-b0d6-394bf145cdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445338869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2445338869
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2012890303
Short name T325
Test name
Test status
Simulation time 27362020906 ps
CPU time 42.5 seconds
Started Jul 01 06:42:35 PM PDT 24
Finished Jul 01 06:43:19 PM PDT 24
Peak memory 199896 kb
Host smart-6b98c0bc-4077-46a4-90ff-8e01058e0cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012890303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2012890303
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.845742829
Short name T184
Test name
Test status
Simulation time 90876187988 ps
CPU time 62.06 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:43:37 PM PDT 24
Peak memory 200024 kb
Host smart-8e952520-abc2-4423-8333-d1faff967cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845742829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.845742829
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3574028042
Short name T89
Test name
Test status
Simulation time 136420686388 ps
CPU time 223.93 seconds
Started Jul 01 06:42:31 PM PDT 24
Finished Jul 01 06:46:16 PM PDT 24
Peak memory 200124 kb
Host smart-17baeda7-9a33-4d00-9761-084ea77dc610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574028042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3574028042
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.970427542
Short name T1016
Test name
Test status
Simulation time 18680490628 ps
CPU time 26.23 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:43:01 PM PDT 24
Peak memory 200008 kb
Host smart-5d147216-7de9-4e07-8247-a1ebad7eaf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970427542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.970427542
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3448051758
Short name T1037
Test name
Test status
Simulation time 48492243670 ps
CPU time 26.23 seconds
Started Jul 01 06:42:33 PM PDT 24
Finished Jul 01 06:43:01 PM PDT 24
Peak memory 199940 kb
Host smart-f240921d-da19-40f0-af57-646459a910da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448051758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3448051758
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.250143821
Short name T509
Test name
Test status
Simulation time 98797737783 ps
CPU time 37.91 seconds
Started Jul 01 06:42:33 PM PDT 24
Finished Jul 01 06:43:13 PM PDT 24
Peak memory 200024 kb
Host smart-cc6e586e-bb40-4a0a-8de0-25b539486167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250143821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.250143821
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3908646406
Short name T1082
Test name
Test status
Simulation time 167589316522 ps
CPU time 62.34 seconds
Started Jul 01 06:42:31 PM PDT 24
Finished Jul 01 06:43:36 PM PDT 24
Peak memory 199948 kb
Host smart-cd1724ad-ea97-4647-9fd8-ddc63c52a2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908646406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3908646406
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.4166529427
Short name T962
Test name
Test status
Simulation time 43611972 ps
CPU time 0.54 seconds
Started Jul 01 06:37:18 PM PDT 24
Finished Jul 01 06:37:19 PM PDT 24
Peak memory 194904 kb
Host smart-261eff92-9959-4825-9b13-3f2f9fde0642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166529427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4166529427
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1017908113
Short name T867
Test name
Test status
Simulation time 33539858235 ps
CPU time 25.42 seconds
Started Jul 01 06:37:09 PM PDT 24
Finished Jul 01 06:37:36 PM PDT 24
Peak memory 200040 kb
Host smart-514feb51-0c85-4366-8ebe-89674a725674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017908113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1017908113
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3250931556
Short name T606
Test name
Test status
Simulation time 96359182717 ps
CPU time 57.38 seconds
Started Jul 01 06:37:07 PM PDT 24
Finished Jul 01 06:38:06 PM PDT 24
Peak memory 199688 kb
Host smart-4f07b9f4-ccb9-4e6e-a021-834f6c140a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250931556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3250931556
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3760194806
Short name T839
Test name
Test status
Simulation time 129890848730 ps
CPU time 188.39 seconds
Started Jul 01 06:37:07 PM PDT 24
Finished Jul 01 06:40:17 PM PDT 24
Peak memory 199960 kb
Host smart-d735b89f-7fb8-4d8f-a4de-e5541df1c378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760194806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3760194806
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.4128452776
Short name T1018
Test name
Test status
Simulation time 4799308700 ps
CPU time 1.55 seconds
Started Jul 01 06:37:06 PM PDT 24
Finished Jul 01 06:37:08 PM PDT 24
Peak memory 198852 kb
Host smart-b697d8ef-66f3-4644-972d-8a1280837d95
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128452776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4128452776
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2933511398
Short name T518
Test name
Test status
Simulation time 85044244445 ps
CPU time 622.08 seconds
Started Jul 01 06:37:18 PM PDT 24
Finished Jul 01 06:47:41 PM PDT 24
Peak memory 199948 kb
Host smart-1069141e-f836-466c-b8f5-d08e0158e4a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933511398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2933511398
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2001090462
Short name T755
Test name
Test status
Simulation time 6135706821 ps
CPU time 6.09 seconds
Started Jul 01 06:37:10 PM PDT 24
Finished Jul 01 06:37:17 PM PDT 24
Peak memory 199732 kb
Host smart-c61545e3-2a9f-4a61-b4ab-669899f8b7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001090462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2001090462
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3157809193
Short name T251
Test name
Test status
Simulation time 22349250809 ps
CPU time 34.17 seconds
Started Jul 01 06:37:07 PM PDT 24
Finished Jul 01 06:37:43 PM PDT 24
Peak memory 200000 kb
Host smart-863d2e87-46b3-4dcb-b0aa-0871ac2e94c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157809193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3157809193
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1062933400
Short name T997
Test name
Test status
Simulation time 11337714238 ps
CPU time 672.92 seconds
Started Jul 01 06:37:09 PM PDT 24
Finished Jul 01 06:48:23 PM PDT 24
Peak memory 200020 kb
Host smart-724a621a-6a64-4fb3-bb6a-79c943a1cb03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062933400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1062933400
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.4257449597
Short name T529
Test name
Test status
Simulation time 2052807280 ps
CPU time 2.53 seconds
Started Jul 01 06:37:06 PM PDT 24
Finished Jul 01 06:37:10 PM PDT 24
Peak memory 198180 kb
Host smart-66b68464-6502-4054-95f4-ed7b87e7f666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257449597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.4257449597
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.88910154
Short name T186
Test name
Test status
Simulation time 66745773846 ps
CPU time 26.61 seconds
Started Jul 01 06:37:10 PM PDT 24
Finished Jul 01 06:37:37 PM PDT 24
Peak memory 200012 kb
Host smart-c3589883-ca6d-4bc4-b437-89523b9fa9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88910154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.88910154
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4259556988
Short name T373
Test name
Test status
Simulation time 503303653 ps
CPU time 1.44 seconds
Started Jul 01 06:37:05 PM PDT 24
Finished Jul 01 06:37:07 PM PDT 24
Peak memory 195544 kb
Host smart-cfbbc57f-fbcf-483b-8848-7d448217f89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259556988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4259556988
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3973492307
Short name T899
Test name
Test status
Simulation time 805910400 ps
CPU time 2.75 seconds
Started Jul 01 06:37:08 PM PDT 24
Finished Jul 01 06:37:12 PM PDT 24
Peak memory 199088 kb
Host smart-adf68b7e-e900-4d76-999e-9f0ecad71560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973492307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3973492307
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3976583976
Short name T250
Test name
Test status
Simulation time 160156030139 ps
CPU time 2172.59 seconds
Started Jul 01 06:37:19 PM PDT 24
Finished Jul 01 07:13:33 PM PDT 24
Peak memory 199976 kb
Host smart-f05d0cbd-4bb8-4316-a9ef-108641cd68d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976583976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3976583976
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2995086739
Short name T991
Test name
Test status
Simulation time 6867871061 ps
CPU time 9.2 seconds
Started Jul 01 06:37:08 PM PDT 24
Finished Jul 01 06:37:18 PM PDT 24
Peak memory 199316 kb
Host smart-bc5ae73a-02e0-49bd-82b1-95bf46f271c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995086739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2995086739
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1475874945
Short name T397
Test name
Test status
Simulation time 114047155093 ps
CPU time 117.07 seconds
Started Jul 01 06:37:07 PM PDT 24
Finished Jul 01 06:39:06 PM PDT 24
Peak memory 200036 kb
Host smart-fc45aace-d9a8-4e16-95bf-ee300040113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475874945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1475874945
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.568519088
Short name T978
Test name
Test status
Simulation time 111729001733 ps
CPU time 65.34 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:43:40 PM PDT 24
Peak memory 199956 kb
Host smart-bfb27856-a88e-473b-a3ea-2d4750067cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568519088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.568519088
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1896258317
Short name T242
Test name
Test status
Simulation time 451299703076 ps
CPU time 39.26 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:43:14 PM PDT 24
Peak memory 199952 kb
Host smart-1461183b-3a5a-464c-a1f9-d17f6ae0257e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896258317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1896258317
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3417809805
Short name T1001
Test name
Test status
Simulation time 85777868988 ps
CPU time 41.55 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:43:16 PM PDT 24
Peak memory 200020 kb
Host smart-191afe0d-487b-4f41-b777-bcffcca619a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417809805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3417809805
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3946871925
Short name T473
Test name
Test status
Simulation time 72634193419 ps
CPU time 26.59 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:43:02 PM PDT 24
Peak memory 199916 kb
Host smart-4e7dfa22-0721-4add-8024-0175d58720c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946871925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3946871925
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3521302225
Short name T849
Test name
Test status
Simulation time 143142114256 ps
CPU time 222.76 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:46:17 PM PDT 24
Peak memory 199936 kb
Host smart-a196ac12-588f-4bf0-9a3b-97a23a3addca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521302225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3521302225
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1805108592
Short name T870
Test name
Test status
Simulation time 9791969107 ps
CPU time 10.92 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:42:45 PM PDT 24
Peak memory 199964 kb
Host smart-2145f087-0bd6-4f1e-a2d8-6d3ec096644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805108592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1805108592
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2383184861
Short name T1007
Test name
Test status
Simulation time 167740149104 ps
CPU time 33.33 seconds
Started Jul 01 06:42:31 PM PDT 24
Finished Jul 01 06:43:07 PM PDT 24
Peak memory 200064 kb
Host smart-8d441bd2-c7b8-4128-a4fb-8e1207b6ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383184861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2383184861
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.400282816
Short name T21
Test name
Test status
Simulation time 53274190 ps
CPU time 0.57 seconds
Started Jul 01 06:37:24 PM PDT 24
Finished Jul 01 06:37:25 PM PDT 24
Peak memory 195276 kb
Host smart-3bde59be-b4c9-4b66-aab3-472aef5701c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400282816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.400282816
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1190847061
Short name T712
Test name
Test status
Simulation time 43923705357 ps
CPU time 19.04 seconds
Started Jul 01 06:37:18 PM PDT 24
Finished Jul 01 06:37:38 PM PDT 24
Peak memory 200040 kb
Host smart-ab824612-4505-451b-b801-84219247c8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190847061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1190847061
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2925769031
Short name T520
Test name
Test status
Simulation time 234439079467 ps
CPU time 75.23 seconds
Started Jul 01 06:37:17 PM PDT 24
Finished Jul 01 06:38:32 PM PDT 24
Peak memory 200008 kb
Host smart-1cf7e486-f6e0-4075-a501-a438cb560231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925769031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2925769031
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2744498282
Short name T451
Test name
Test status
Simulation time 17584174511 ps
CPU time 24.85 seconds
Started Jul 01 06:37:20 PM PDT 24
Finished Jul 01 06:37:46 PM PDT 24
Peak memory 196980 kb
Host smart-99351b85-8c11-431c-a0d8-a09ebd555b5b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744498282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2744498282
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.909506583
Short name T761
Test name
Test status
Simulation time 65010435434 ps
CPU time 85.92 seconds
Started Jul 01 06:37:18 PM PDT 24
Finished Jul 01 06:38:45 PM PDT 24
Peak memory 200048 kb
Host smart-7665d991-282e-429d-a681-fbc8fb34086d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909506583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.909506583
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.172553194
Short name T938
Test name
Test status
Simulation time 5587096285 ps
CPU time 6.57 seconds
Started Jul 01 06:37:21 PM PDT 24
Finished Jul 01 06:37:29 PM PDT 24
Peak memory 199760 kb
Host smart-f14f6fe0-1636-4c09-9576-2e3cd3e9f266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172553194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.172553194
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.2880781844
Short name T261
Test name
Test status
Simulation time 28714140706 ps
CPU time 181.31 seconds
Started Jul 01 06:37:19 PM PDT 24
Finished Jul 01 06:40:21 PM PDT 24
Peak memory 199944 kb
Host smart-ba5a4f65-0109-4c2c-8e31-3005354cbe65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880781844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2880781844
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3926171544
Short name T785
Test name
Test status
Simulation time 5824487636 ps
CPU time 23.79 seconds
Started Jul 01 06:37:21 PM PDT 24
Finished Jul 01 06:37:46 PM PDT 24
Peak memory 198324 kb
Host smart-30542d43-2533-41ac-abd3-5a4b2a97995e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926171544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3926171544
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.668872090
Short name T259
Test name
Test status
Simulation time 40215130532 ps
CPU time 11.05 seconds
Started Jul 01 06:37:20 PM PDT 24
Finished Jul 01 06:37:33 PM PDT 24
Peak memory 199728 kb
Host smart-b6abb2a0-521f-4e16-b6f6-e5a25e44d40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668872090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.668872090
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3099197723
Short name T951
Test name
Test status
Simulation time 4510761885 ps
CPU time 7.29 seconds
Started Jul 01 06:37:20 PM PDT 24
Finished Jul 01 06:37:29 PM PDT 24
Peak memory 196376 kb
Host smart-91eec6ad-303d-456b-92c4-c4ade3a138c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099197723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3099197723
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4096445264
Short name T758
Test name
Test status
Simulation time 575384708 ps
CPU time 0.88 seconds
Started Jul 01 06:37:19 PM PDT 24
Finished Jul 01 06:37:21 PM PDT 24
Peak memory 198844 kb
Host smart-aba54fcb-1f32-431f-9611-00bd279599b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096445264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4096445264
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3769573537
Short name T209
Test name
Test status
Simulation time 474279174119 ps
CPU time 180.69 seconds
Started Jul 01 06:37:21 PM PDT 24
Finished Jul 01 06:40:23 PM PDT 24
Peak memory 200012 kb
Host smart-ec68d669-16f2-4f78-8a80-e2bd2fcd8525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769573537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3769573537
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.4061764793
Short name T465
Test name
Test status
Simulation time 45544186381 ps
CPU time 527.04 seconds
Started Jul 01 06:37:21 PM PDT 24
Finished Jul 01 06:46:10 PM PDT 24
Peak memory 216660 kb
Host smart-6c588fb3-29c7-4faa-8523-dedf45ac1f30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061764793 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.4061764793
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1419531820
Short name T368
Test name
Test status
Simulation time 1178061141 ps
CPU time 1.85 seconds
Started Jul 01 06:37:21 PM PDT 24
Finished Jul 01 06:37:24 PM PDT 24
Peak memory 198712 kb
Host smart-1d2a224f-62f0-449e-820d-036fc2278f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419531820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1419531820
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2510278226
Short name T566
Test name
Test status
Simulation time 154919140713 ps
CPU time 220.52 seconds
Started Jul 01 06:37:20 PM PDT 24
Finished Jul 01 06:41:02 PM PDT 24
Peak memory 200004 kb
Host smart-32689f09-a0b4-40e3-9dc8-702bbc61408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510278226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2510278226
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2503916511
Short name T748
Test name
Test status
Simulation time 21514555312 ps
CPU time 41.55 seconds
Started Jul 01 06:42:32 PM PDT 24
Finished Jul 01 06:43:17 PM PDT 24
Peak memory 199956 kb
Host smart-615ee1ce-6a9d-40a0-8d3c-75ba8265cd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503916511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2503916511
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2822656877
Short name T760
Test name
Test status
Simulation time 53439759364 ps
CPU time 71.84 seconds
Started Jul 01 06:42:31 PM PDT 24
Finished Jul 01 06:43:45 PM PDT 24
Peak memory 200020 kb
Host smart-f5121336-7476-4c6b-9202-3c61d9e6dbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822656877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2822656877
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.503889624
Short name T202
Test name
Test status
Simulation time 106482214759 ps
CPU time 20.7 seconds
Started Jul 01 06:42:40 PM PDT 24
Finished Jul 01 06:43:02 PM PDT 24
Peak memory 200072 kb
Host smart-e3f71a4a-c413-4214-815b-55bdf447b763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503889624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.503889624
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2748584231
Short name T344
Test name
Test status
Simulation time 66309155446 ps
CPU time 53.03 seconds
Started Jul 01 06:42:40 PM PDT 24
Finished Jul 01 06:43:34 PM PDT 24
Peak memory 199944 kb
Host smart-b013ec66-d71f-4ac4-8d74-9455874ceb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748584231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2748584231
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1781495638
Short name T1046
Test name
Test status
Simulation time 175563824957 ps
CPU time 138.35 seconds
Started Jul 01 06:42:41 PM PDT 24
Finished Jul 01 06:45:01 PM PDT 24
Peak memory 200032 kb
Host smart-42fa2c4e-8cc3-40b4-bc4e-5935bca82db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781495638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1781495638
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1471110691
Short name T234
Test name
Test status
Simulation time 47179655072 ps
CPU time 35.08 seconds
Started Jul 01 06:42:42 PM PDT 24
Finished Jul 01 06:43:19 PM PDT 24
Peak memory 200068 kb
Host smart-03653ce1-abf6-4fcd-9b60-e898be5dda15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471110691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1471110691
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1711255314
Short name T248
Test name
Test status
Simulation time 27365363420 ps
CPU time 17.49 seconds
Started Jul 01 06:42:40 PM PDT 24
Finished Jul 01 06:42:58 PM PDT 24
Peak memory 199960 kb
Host smart-27587682-0618-4977-8d4c-fe0724e50f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711255314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1711255314
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1744715366
Short name T866
Test name
Test status
Simulation time 38958698553 ps
CPU time 56.85 seconds
Started Jul 01 06:42:41 PM PDT 24
Finished Jul 01 06:43:40 PM PDT 24
Peak memory 200044 kb
Host smart-53483a4d-5e71-4def-a27d-e3387be29db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744715366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1744715366
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1308896862
Short name T195
Test name
Test status
Simulation time 143679739635 ps
CPU time 22.73 seconds
Started Jul 01 06:42:42 PM PDT 24
Finished Jul 01 06:43:06 PM PDT 24
Peak memory 200092 kb
Host smart-c2c33069-dc0e-414a-a27b-e58b845923e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308896862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1308896862
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3872904517
Short name T942
Test name
Test status
Simulation time 59131879338 ps
CPU time 71.68 seconds
Started Jul 01 06:42:40 PM PDT 24
Finished Jul 01 06:43:52 PM PDT 24
Peak memory 200040 kb
Host smart-8a76c9b3-8fc8-42b2-8172-9db628759e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872904517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3872904517
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3281379700
Short name T852
Test name
Test status
Simulation time 45006426 ps
CPU time 0.55 seconds
Started Jul 01 06:37:27 PM PDT 24
Finished Jul 01 06:37:30 PM PDT 24
Peak memory 195296 kb
Host smart-c57a39ac-9abe-402a-8104-41e281fc15a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281379700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3281379700
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2144741801
Short name T189
Test name
Test status
Simulation time 90322157553 ps
CPU time 24.84 seconds
Started Jul 01 06:37:21 PM PDT 24
Finished Jul 01 06:37:47 PM PDT 24
Peak memory 199976 kb
Host smart-2da61421-1b50-42e4-b332-4ab3a8a7d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144741801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2144741801
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1481704784
Short name T879
Test name
Test status
Simulation time 100879013308 ps
CPU time 18.16 seconds
Started Jul 01 06:37:25 PM PDT 24
Finished Jul 01 06:37:44 PM PDT 24
Peak memory 199936 kb
Host smart-f8b3fa17-7b68-4b91-80e5-2c88fe81d402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481704784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1481704784
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1139365505
Short name T874
Test name
Test status
Simulation time 105223554102 ps
CPU time 88.55 seconds
Started Jul 01 06:37:29 PM PDT 24
Finished Jul 01 06:38:59 PM PDT 24
Peak memory 200032 kb
Host smart-00ef9e65-cf8e-4db6-a082-50d482d6219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139365505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1139365505
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3865129917
Short name T11
Test name
Test status
Simulation time 31179923584 ps
CPU time 50.63 seconds
Started Jul 01 06:37:27 PM PDT 24
Finished Jul 01 06:38:19 PM PDT 24
Peak memory 199744 kb
Host smart-aa4d36d9-1855-43a2-8165-3889d5ecd2b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865129917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3865129917
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1957455705
Short name T346
Test name
Test status
Simulation time 72534819778 ps
CPU time 237.34 seconds
Started Jul 01 06:37:28 PM PDT 24
Finished Jul 01 06:41:27 PM PDT 24
Peak memory 199908 kb
Host smart-bdbfa336-5eb6-4759-8f98-d2e70238c1fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957455705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1957455705
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2702316784
Short name T482
Test name
Test status
Simulation time 13963973751 ps
CPU time 29.03 seconds
Started Jul 01 06:37:29 PM PDT 24
Finished Jul 01 06:37:59 PM PDT 24
Peak memory 199668 kb
Host smart-4168e5cd-37f5-48da-827b-1b5b5e824611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702316784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2702316784
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3775196659
Short name T512
Test name
Test status
Simulation time 51576215543 ps
CPU time 124.69 seconds
Started Jul 01 06:37:27 PM PDT 24
Finished Jul 01 06:39:33 PM PDT 24
Peak memory 199972 kb
Host smart-fd028c58-c5b5-4704-af07-fdb5328b4766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775196659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3775196659
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3143127149
Short name T714
Test name
Test status
Simulation time 12739475701 ps
CPU time 531.12 seconds
Started Jul 01 06:37:25 PM PDT 24
Finished Jul 01 06:46:17 PM PDT 24
Peak memory 199972 kb
Host smart-036c33da-efb5-400b-be58-7475b041c048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143127149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3143127149
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.703477058
Short name T1030
Test name
Test status
Simulation time 5391743295 ps
CPU time 46.68 seconds
Started Jul 01 06:37:26 PM PDT 24
Finished Jul 01 06:38:15 PM PDT 24
Peak memory 198752 kb
Host smart-1e87e4cc-4427-42d8-babd-466936d01edb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=703477058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.703477058
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1491313878
Short name T190
Test name
Test status
Simulation time 27186634284 ps
CPU time 12.83 seconds
Started Jul 01 06:37:29 PM PDT 24
Finished Jul 01 06:37:43 PM PDT 24
Peak memory 200104 kb
Host smart-3d20c89c-27ba-4884-8ee9-4de1e9057a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491313878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1491313878
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.713193928
Short name T292
Test name
Test status
Simulation time 2847412143 ps
CPU time 1.74 seconds
Started Jul 01 06:37:25 PM PDT 24
Finished Jul 01 06:37:28 PM PDT 24
Peak memory 195948 kb
Host smart-fdb581d1-aa68-4239-9761-3b8941d284fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713193928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.713193928
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1546864589
Short name T563
Test name
Test status
Simulation time 5899100916 ps
CPU time 11.41 seconds
Started Jul 01 06:37:20 PM PDT 24
Finished Jul 01 06:37:33 PM PDT 24
Peak memory 199888 kb
Host smart-df6f19f8-f316-46db-b96c-e44a5e0f3250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546864589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1546864589
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.558315916
Short name T750
Test name
Test status
Simulation time 1999550710 ps
CPU time 3.87 seconds
Started Jul 01 06:37:29 PM PDT 24
Finished Jul 01 06:37:34 PM PDT 24
Peak memory 199968 kb
Host smart-5c1a161d-44bb-4a84-abca-3a8ae801535e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558315916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.558315916
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.717919552
Short name T607
Test name
Test status
Simulation time 211775483032 ps
CPU time 584.34 seconds
Started Jul 01 06:37:26 PM PDT 24
Finished Jul 01 06:47:12 PM PDT 24
Peak memory 213904 kb
Host smart-768b80e2-09f6-4a73-9d96-0baf16322a53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717919552 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.717919552
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3593013543
Short name T320
Test name
Test status
Simulation time 4989559203 ps
CPU time 1.44 seconds
Started Jul 01 06:37:27 PM PDT 24
Finished Jul 01 06:37:30 PM PDT 24
Peak memory 199820 kb
Host smart-0eef6c41-9711-4865-a5b5-bd40c33332cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593013543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3593013543
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2701864775
Short name T994
Test name
Test status
Simulation time 7885060184 ps
CPU time 11.7 seconds
Started Jul 01 06:37:23 PM PDT 24
Finished Jul 01 06:37:35 PM PDT 24
Peak memory 199984 kb
Host smart-d9aa7001-91e5-4e71-85e2-027e601d7f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701864775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2701864775
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.567579202
Short name T553
Test name
Test status
Simulation time 53276865400 ps
CPU time 19.2 seconds
Started Jul 01 06:42:40 PM PDT 24
Finished Jul 01 06:43:00 PM PDT 24
Peak memory 200104 kb
Host smart-c89b4c6f-67aa-4661-b912-7a699881b78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567579202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.567579202
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.562905699
Short name T1010
Test name
Test status
Simulation time 104449956934 ps
CPU time 134.93 seconds
Started Jul 01 06:42:40 PM PDT 24
Finished Jul 01 06:44:57 PM PDT 24
Peak memory 200004 kb
Host smart-6e27fda2-3c50-4c93-89dd-1cea0d40b68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562905699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.562905699
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2684677506
Short name T75
Test name
Test status
Simulation time 23881787273 ps
CPU time 43.64 seconds
Started Jul 01 06:42:41 PM PDT 24
Finished Jul 01 06:43:27 PM PDT 24
Peak memory 199980 kb
Host smart-03c11ea5-76e7-42f5-a5d0-add727c3a98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684677506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2684677506
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1326388261
Short name T262
Test name
Test status
Simulation time 39156227041 ps
CPU time 17.98 seconds
Started Jul 01 06:42:41 PM PDT 24
Finished Jul 01 06:43:01 PM PDT 24
Peak memory 200012 kb
Host smart-750beca8-d8fc-4dd9-9b6c-188d339e7216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326388261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1326388261
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3265060543
Short name T166
Test name
Test status
Simulation time 8086405206 ps
CPU time 17.67 seconds
Started Jul 01 06:42:40 PM PDT 24
Finished Jul 01 06:42:59 PM PDT 24
Peak memory 199944 kb
Host smart-6c5cffe8-1995-4441-b1a4-c4f0a259e013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265060543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3265060543
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.902694242
Short name T933
Test name
Test status
Simulation time 83464647576 ps
CPU time 32.28 seconds
Started Jul 01 06:42:40 PM PDT 24
Finished Jul 01 06:43:14 PM PDT 24
Peak memory 200068 kb
Host smart-b64c25e6-9c1d-43e5-9cea-48582c1c457a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902694242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.902694242
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3279168387
Short name T1043
Test name
Test status
Simulation time 39078916671 ps
CPU time 18.17 seconds
Started Jul 01 06:42:40 PM PDT 24
Finished Jul 01 06:42:59 PM PDT 24
Peak memory 199924 kb
Host smart-af6b5d8d-469b-49a7-a1b3-a5493aa7b525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279168387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3279168387
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.589370165
Short name T1063
Test name
Test status
Simulation time 234388629308 ps
CPU time 45.24 seconds
Started Jul 01 06:42:40 PM PDT 24
Finished Jul 01 06:43:27 PM PDT 24
Peak memory 200136 kb
Host smart-5454a573-2050-4462-8f9e-f865ff1d864b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589370165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.589370165
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1040429726
Short name T396
Test name
Test status
Simulation time 13343048205 ps
CPU time 23.39 seconds
Started Jul 01 06:42:47 PM PDT 24
Finished Jul 01 06:43:12 PM PDT 24
Peak memory 199984 kb
Host smart-b99fcda9-5c17-4f15-9d5f-a5429d15922d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040429726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1040429726
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4157335841
Short name T353
Test name
Test status
Simulation time 34544936 ps
CPU time 0.56 seconds
Started Jul 01 06:37:31 PM PDT 24
Finished Jul 01 06:37:33 PM PDT 24
Peak memory 194888 kb
Host smart-4ff8b8be-23f5-4851-8eab-fc1f7fa4c11b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157335841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4157335841
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2047072685
Short name T291
Test name
Test status
Simulation time 78325634005 ps
CPU time 168.76 seconds
Started Jul 01 06:37:25 PM PDT 24
Finished Jul 01 06:40:15 PM PDT 24
Peak memory 200140 kb
Host smart-fad73858-0d4d-4a12-9b8a-e522f6137e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047072685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2047072685
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.326880217
Short name T295
Test name
Test status
Simulation time 15062432061 ps
CPU time 31.26 seconds
Started Jul 01 06:37:26 PM PDT 24
Finished Jul 01 06:37:59 PM PDT 24
Peak memory 199944 kb
Host smart-820c8c80-6d41-453e-a930-1cc1a9b938ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326880217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.326880217
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1389064936
Short name T308
Test name
Test status
Simulation time 99979317424 ps
CPU time 26.18 seconds
Started Jul 01 06:37:26 PM PDT 24
Finished Jul 01 06:37:54 PM PDT 24
Peak memory 199916 kb
Host smart-e2e44fa7-d606-4553-bc4e-0a8652445b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389064936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1389064936
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3949101624
Short name T329
Test name
Test status
Simulation time 23366237281 ps
CPU time 25.72 seconds
Started Jul 01 06:37:26 PM PDT 24
Finished Jul 01 06:37:53 PM PDT 24
Peak memory 199932 kb
Host smart-4d6c0ec7-04bc-4971-89dd-1428a6da0410
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949101624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3949101624
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2109774578
Short name T522
Test name
Test status
Simulation time 123196532774 ps
CPU time 1066.49 seconds
Started Jul 01 06:37:34 PM PDT 24
Finished Jul 01 06:55:21 PM PDT 24
Peak memory 199956 kb
Host smart-2fa811c0-9e2b-4ef6-b5b5-14ff12af853a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2109774578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2109774578
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1431310158
Short name T1003
Test name
Test status
Simulation time 3982750824 ps
CPU time 5.33 seconds
Started Jul 01 06:37:27 PM PDT 24
Finished Jul 01 06:37:34 PM PDT 24
Peak memory 199420 kb
Host smart-c0261696-d3d9-4465-a1ba-f4c1cadfdfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431310158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1431310158
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.3157775778
Short name T984
Test name
Test status
Simulation time 9735829527 ps
CPU time 127.09 seconds
Started Jul 01 06:37:31 PM PDT 24
Finished Jul 01 06:39:39 PM PDT 24
Peak memory 199968 kb
Host smart-a0899181-55e0-41ba-b07c-b1f54dbf315d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157775778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3157775778
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.4092318050
Short name T472
Test name
Test status
Simulation time 3924894521 ps
CPU time 34.1 seconds
Started Jul 01 06:37:26 PM PDT 24
Finished Jul 01 06:38:02 PM PDT 24
Peak memory 198300 kb
Host smart-e54e9d00-c0fb-4ffc-ab51-9baf014cc82d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092318050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.4092318050
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2352302630
Short name T326
Test name
Test status
Simulation time 145695085164 ps
CPU time 233.51 seconds
Started Jul 01 06:37:25 PM PDT 24
Finished Jul 01 06:41:20 PM PDT 24
Peak memory 199944 kb
Host smart-80abffa4-07a2-4932-a95a-9d5607686867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352302630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2352302630
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.132081803
Short name T882
Test name
Test status
Simulation time 3563225120 ps
CPU time 2.05 seconds
Started Jul 01 06:37:25 PM PDT 24
Finished Jul 01 06:37:29 PM PDT 24
Peak memory 196516 kb
Host smart-35c8fd6e-0fcc-4c7c-8c2a-9dfa22a9a395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132081803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.132081803
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2529077716
Short name T394
Test name
Test status
Simulation time 274650258 ps
CPU time 1.01 seconds
Started Jul 01 06:37:27 PM PDT 24
Finished Jul 01 06:37:30 PM PDT 24
Peak memory 198588 kb
Host smart-cdaac275-0fc1-4423-a01d-4cb245921812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529077716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2529077716
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1998665512
Short name T601
Test name
Test status
Simulation time 1504220420 ps
CPU time 1.53 seconds
Started Jul 01 06:37:26 PM PDT 24
Finished Jul 01 06:37:30 PM PDT 24
Peak memory 199864 kb
Host smart-bcafd55e-c021-4106-aef8-aa832fee75ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998665512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1998665512
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3250747483
Short name T505
Test name
Test status
Simulation time 76434587906 ps
CPU time 79.73 seconds
Started Jul 01 06:37:26 PM PDT 24
Finished Jul 01 06:38:47 PM PDT 24
Peak memory 199944 kb
Host smart-a68a0b62-1b0e-4ddc-ae3e-4c98f0eb7f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250747483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3250747483
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2916862541
Short name T215
Test name
Test status
Simulation time 44858355416 ps
CPU time 19.83 seconds
Started Jul 01 06:42:46 PM PDT 24
Finished Jul 01 06:43:07 PM PDT 24
Peak memory 200048 kb
Host smart-2e68f11b-eaee-41ff-bb89-0baa93688119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916862541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2916862541
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4253585117
Short name T224
Test name
Test status
Simulation time 127017011497 ps
CPU time 303.67 seconds
Started Jul 01 06:42:45 PM PDT 24
Finished Jul 01 06:47:50 PM PDT 24
Peak memory 200016 kb
Host smart-448f7f28-08ce-477e-9aed-81cfc46cc196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253585117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4253585117
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1467849863
Short name T733
Test name
Test status
Simulation time 108487519046 ps
CPU time 53.77 seconds
Started Jul 01 06:42:46 PM PDT 24
Finished Jul 01 06:43:41 PM PDT 24
Peak memory 200124 kb
Host smart-8841c1ff-d7c4-49a1-bb80-ea398d6cfd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467849863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1467849863
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.169783540
Short name T154
Test name
Test status
Simulation time 118815260015 ps
CPU time 176.11 seconds
Started Jul 01 06:42:47 PM PDT 24
Finished Jul 01 06:45:45 PM PDT 24
Peak memory 199940 kb
Host smart-ce42e6df-f77d-4f3f-8139-a3c8179fd02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169783540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.169783540
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3973965632
Short name T753
Test name
Test status
Simulation time 32419961292 ps
CPU time 9.64 seconds
Started Jul 01 06:42:48 PM PDT 24
Finished Jul 01 06:42:59 PM PDT 24
Peak memory 199104 kb
Host smart-b61d5639-7b7e-4b4a-909e-8e550d78240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973965632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3973965632
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.996336646
Short name T803
Test name
Test status
Simulation time 26087136070 ps
CPU time 9.46 seconds
Started Jul 01 06:42:47 PM PDT 24
Finished Jul 01 06:42:58 PM PDT 24
Peak memory 199668 kb
Host smart-16170a86-0ac7-494f-bfba-422078657ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996336646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.996336646
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.275910901
Short name T736
Test name
Test status
Simulation time 95915608434 ps
CPU time 140.59 seconds
Started Jul 01 06:42:44 PM PDT 24
Finished Jul 01 06:45:06 PM PDT 24
Peak memory 200008 kb
Host smart-9d2d115b-b8bb-4896-8e26-93f9b3fd6696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275910901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.275910901
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2733030049
Short name T580
Test name
Test status
Simulation time 107055083233 ps
CPU time 36.93 seconds
Started Jul 01 06:42:48 PM PDT 24
Finished Jul 01 06:43:26 PM PDT 24
Peak memory 199888 kb
Host smart-976a2394-dd04-40d9-a2a8-cd9a3c00b169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733030049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2733030049
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.4168616384
Short name T577
Test name
Test status
Simulation time 235680019307 ps
CPU time 18.93 seconds
Started Jul 01 06:42:46 PM PDT 24
Finished Jul 01 06:43:06 PM PDT 24
Peak memory 199040 kb
Host smart-813c95a5-582d-4388-9250-ed0d88b17a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168616384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.4168616384
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.471900404
Short name T552
Test name
Test status
Simulation time 13612238 ps
CPU time 0.57 seconds
Started Jul 01 06:37:38 PM PDT 24
Finished Jul 01 06:37:40 PM PDT 24
Peak memory 195612 kb
Host smart-9627e772-2b13-4a7b-aadf-86ed16edf8b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471900404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.471900404
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1991483127
Short name T88
Test name
Test status
Simulation time 73939021529 ps
CPU time 65.59 seconds
Started Jul 01 06:37:32 PM PDT 24
Finished Jul 01 06:38:39 PM PDT 24
Peak memory 199980 kb
Host smart-f896db40-f57c-4962-a6b8-d6bb5162c0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991483127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1991483127
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.910426663
Short name T745
Test name
Test status
Simulation time 45132339575 ps
CPU time 25.66 seconds
Started Jul 01 06:37:32 PM PDT 24
Finished Jul 01 06:37:59 PM PDT 24
Peak memory 199944 kb
Host smart-eebe361c-e1b5-4a4a-bb02-1ad8057a1b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910426663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.910426663
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2368240624
Short name T711
Test name
Test status
Simulation time 146413470816 ps
CPU time 221.15 seconds
Started Jul 01 06:37:34 PM PDT 24
Finished Jul 01 06:41:16 PM PDT 24
Peak memory 200008 kb
Host smart-21b77aac-dd66-46f5-8fa6-7834c93557c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368240624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2368240624
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1099085921
Short name T653
Test name
Test status
Simulation time 25532182151 ps
CPU time 40.27 seconds
Started Jul 01 06:37:32 PM PDT 24
Finished Jul 01 06:38:13 PM PDT 24
Peak memory 197964 kb
Host smart-2e1fdf2a-90fe-4986-a950-155789a8b611
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099085921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1099085921
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3817782620
Short name T432
Test name
Test status
Simulation time 71053172948 ps
CPU time 127.42 seconds
Started Jul 01 06:37:39 PM PDT 24
Finished Jul 01 06:39:47 PM PDT 24
Peak memory 199984 kb
Host smart-e027a1dd-9463-47ef-bc42-ed3175f61266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817782620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3817782620
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3128613679
Short name T15
Test name
Test status
Simulation time 5366144311 ps
CPU time 9.47 seconds
Started Jul 01 06:37:39 PM PDT 24
Finished Jul 01 06:37:49 PM PDT 24
Peak memory 199192 kb
Host smart-b854be0b-595c-43ee-b916-51d981835960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128613679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3128613679
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.2075052561
Short name T488
Test name
Test status
Simulation time 21995366945 ps
CPU time 303.35 seconds
Started Jul 01 06:37:42 PM PDT 24
Finished Jul 01 06:42:46 PM PDT 24
Peak memory 199888 kb
Host smart-d251eb28-d58a-4db3-ac78-27c7e1c7b378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075052561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2075052561
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1569367274
Short name T799
Test name
Test status
Simulation time 3965320509 ps
CPU time 8.09 seconds
Started Jul 01 06:37:31 PM PDT 24
Finished Jul 01 06:37:41 PM PDT 24
Peak memory 198556 kb
Host smart-044d0cbf-9f6b-4d86-b9a1-62939f052fea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1569367274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1569367274
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1924702892
Short name T584
Test name
Test status
Simulation time 21306797827 ps
CPU time 16.89 seconds
Started Jul 01 06:37:40 PM PDT 24
Finished Jul 01 06:37:57 PM PDT 24
Peak memory 197368 kb
Host smart-b9b1b617-b46f-447f-b3d5-47273d9a02a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924702892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1924702892
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1578372533
Short name T881
Test name
Test status
Simulation time 2444213817 ps
CPU time 4.09 seconds
Started Jul 01 06:37:32 PM PDT 24
Finished Jul 01 06:37:38 PM PDT 24
Peak memory 196424 kb
Host smart-b2ab1213-725e-4bc1-8bf5-c53dff9b9095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578372533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1578372533
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3042352420
Short name T756
Test name
Test status
Simulation time 933026872 ps
CPU time 4.64 seconds
Started Jul 01 06:37:32 PM PDT 24
Finished Jul 01 06:37:38 PM PDT 24
Peak memory 199692 kb
Host smart-ca581aa5-0878-4fe2-8ac7-5145df8779d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042352420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3042352420
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.676035330
Short name T120
Test name
Test status
Simulation time 116522057614 ps
CPU time 439.24 seconds
Started Jul 01 06:37:38 PM PDT 24
Finished Jul 01 06:44:59 PM PDT 24
Peak memory 216544 kb
Host smart-30d261c7-efb1-48f0-a9a8-8f0ff23cffd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676035330 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.676035330
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3946066166
Short name T63
Test name
Test status
Simulation time 978249035 ps
CPU time 3.35 seconds
Started Jul 01 06:37:39 PM PDT 24
Finished Jul 01 06:37:43 PM PDT 24
Peak memory 198812 kb
Host smart-afda333e-77fc-4241-9871-c87328b6d1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946066166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3946066166
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1976370798
Short name T595
Test name
Test status
Simulation time 96202911623 ps
CPU time 103.19 seconds
Started Jul 01 06:37:32 PM PDT 24
Finished Jul 01 06:39:16 PM PDT 24
Peak memory 200008 kb
Host smart-a6a1b42b-7c90-4fc9-b7af-9431c9ee6bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976370798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1976370798
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1368449200
Short name T239
Test name
Test status
Simulation time 10910150515 ps
CPU time 10.36 seconds
Started Jul 01 06:42:47 PM PDT 24
Finished Jul 01 06:42:59 PM PDT 24
Peak memory 199944 kb
Host smart-d6ac4fb7-1178-4473-a36e-c081f139f15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368449200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1368449200
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1180395308
Short name T596
Test name
Test status
Simulation time 110101436275 ps
CPU time 47.78 seconds
Started Jul 01 06:42:47 PM PDT 24
Finished Jul 01 06:43:37 PM PDT 24
Peak memory 200020 kb
Host smart-90869529-66dd-4b2a-bbda-a7f6c7d48fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180395308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1180395308
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1536355294
Short name T689
Test name
Test status
Simulation time 55118621499 ps
CPU time 23.96 seconds
Started Jul 01 06:42:56 PM PDT 24
Finished Jul 01 06:43:21 PM PDT 24
Peak memory 200124 kb
Host smart-a5147a3e-245d-4e8e-a296-f523be65c975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536355294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1536355294
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3077484681
Short name T519
Test name
Test status
Simulation time 159568406703 ps
CPU time 111.05 seconds
Started Jul 01 06:42:54 PM PDT 24
Finished Jul 01 06:44:46 PM PDT 24
Peak memory 200044 kb
Host smart-62ab2e92-f5a8-4176-b20c-1e4a384a66b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077484681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3077484681
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1609704006
Short name T1039
Test name
Test status
Simulation time 13682077064 ps
CPU time 20.11 seconds
Started Jul 01 06:42:53 PM PDT 24
Finished Jul 01 06:43:14 PM PDT 24
Peak memory 199844 kb
Host smart-d673753c-e639-4127-af64-a7f5c6833264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609704006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1609704006
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3465972688
Short name T174
Test name
Test status
Simulation time 137515089116 ps
CPU time 178.07 seconds
Started Jul 01 06:42:54 PM PDT 24
Finished Jul 01 06:45:53 PM PDT 24
Peak memory 200000 kb
Host smart-767a10b3-df21-4f43-8b1b-121f311f1a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465972688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3465972688
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.412510350
Short name T499
Test name
Test status
Simulation time 17793270498 ps
CPU time 16.8 seconds
Started Jul 01 06:42:53 PM PDT 24
Finished Jul 01 06:43:11 PM PDT 24
Peak memory 199960 kb
Host smart-6c6ec910-ece5-4431-ab8e-510aa7309b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412510350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.412510350
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1349246621
Short name T160
Test name
Test status
Simulation time 44133197746 ps
CPU time 22.35 seconds
Started Jul 01 06:42:54 PM PDT 24
Finished Jul 01 06:43:19 PM PDT 24
Peak memory 200048 kb
Host smart-02027989-42cb-4a29-bb83-c07fa35031d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349246621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1349246621
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3945004434
Short name T930
Test name
Test status
Simulation time 41142823813 ps
CPU time 34.62 seconds
Started Jul 01 06:42:53 PM PDT 24
Finished Jul 01 06:43:29 PM PDT 24
Peak memory 200044 kb
Host smart-49088104-c349-4b49-b84e-d496a082a253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945004434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3945004434
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.920899344
Short name T492
Test name
Test status
Simulation time 40209980 ps
CPU time 0.56 seconds
Started Jul 01 06:37:45 PM PDT 24
Finished Jul 01 06:37:46 PM PDT 24
Peak memory 195392 kb
Host smart-1c64ccd3-685b-4211-99f3-360879d3aace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920899344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.920899344
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1437111109
Short name T869
Test name
Test status
Simulation time 150990934094 ps
CPU time 43.28 seconds
Started Jul 01 06:37:41 PM PDT 24
Finished Jul 01 06:38:25 PM PDT 24
Peak memory 199964 kb
Host smart-630c2e9e-7b84-4cb5-a3d6-71a9250bf083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437111109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1437111109
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1719952568
Short name T1062
Test name
Test status
Simulation time 27529639939 ps
CPU time 21.97 seconds
Started Jul 01 06:37:38 PM PDT 24
Finished Jul 01 06:38:01 PM PDT 24
Peak memory 199956 kb
Host smart-5c4ed4aa-2fa4-430d-b271-dcfe679bd1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719952568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1719952568
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1816211306
Short name T333
Test name
Test status
Simulation time 16057632822 ps
CPU time 24.95 seconds
Started Jul 01 06:37:46 PM PDT 24
Finished Jul 01 06:38:13 PM PDT 24
Peak memory 199940 kb
Host smart-043f5fb3-8078-4dbe-a4ed-091efe4bba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816211306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1816211306
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.596752386
Short name T1089
Test name
Test status
Simulation time 227017868299 ps
CPU time 332.94 seconds
Started Jul 01 06:37:47 PM PDT 24
Finished Jul 01 06:43:22 PM PDT 24
Peak memory 199824 kb
Host smart-4e9bbb93-13d0-4fee-a635-0797ed00bff3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596752386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.596752386
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2902763969
Short name T414
Test name
Test status
Simulation time 178863322972 ps
CPU time 785.8 seconds
Started Jul 01 06:37:46 PM PDT 24
Finished Jul 01 06:50:53 PM PDT 24
Peak memory 199992 kb
Host smart-89028142-10ba-4caf-a092-72fe6cb3d838
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902763969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2902763969
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1555035451
Short name T385
Test name
Test status
Simulation time 6910969674 ps
CPU time 4.93 seconds
Started Jul 01 06:37:47 PM PDT 24
Finished Jul 01 06:37:54 PM PDT 24
Peak memory 199036 kb
Host smart-7db20b61-222a-4cec-bf5a-b10b369c1c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555035451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1555035451
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.2493882688
Short name T116
Test name
Test status
Simulation time 6110267869 ps
CPU time 240.8 seconds
Started Jul 01 06:37:46 PM PDT 24
Finished Jul 01 06:41:49 PM PDT 24
Peak memory 199976 kb
Host smart-2c6ef7f8-60c0-40be-b714-b12f996ae8dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493882688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2493882688
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1423255661
Short name T487
Test name
Test status
Simulation time 7673670029 ps
CPU time 72.52 seconds
Started Jul 01 06:37:45 PM PDT 24
Finished Jul 01 06:38:59 PM PDT 24
Peak memory 198272 kb
Host smart-da208c58-5fa9-40c7-bb5b-a23fc407eb6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423255661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1423255661
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2046473127
Short name T141
Test name
Test status
Simulation time 19166891894 ps
CPU time 32.5 seconds
Started Jul 01 06:37:47 PM PDT 24
Finished Jul 01 06:38:21 PM PDT 24
Peak memory 199944 kb
Host smart-d9cddc84-e4b8-439d-97eb-d856d61bb124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046473127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2046473127
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.834364571
Short name T990
Test name
Test status
Simulation time 47654536234 ps
CPU time 33.65 seconds
Started Jul 01 06:37:46 PM PDT 24
Finished Jul 01 06:38:22 PM PDT 24
Peak memory 195840 kb
Host smart-1599d150-48da-4ba1-817c-5f09552e06d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834364571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.834364571
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3945210671
Short name T895
Test name
Test status
Simulation time 580541933 ps
CPU time 1.5 seconds
Started Jul 01 06:37:40 PM PDT 24
Finished Jul 01 06:37:42 PM PDT 24
Peak memory 199036 kb
Host smart-579cb721-5af8-482a-984c-a6e9db9216be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945210671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3945210671
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3662244019
Short name T621
Test name
Test status
Simulation time 118500036674 ps
CPU time 219.21 seconds
Started Jul 01 06:37:44 PM PDT 24
Finished Jul 01 06:41:23 PM PDT 24
Peak memory 199908 kb
Host smart-6950b95c-e436-496c-b8f4-49e0c4cb9896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662244019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3662244019
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3344372400
Short name T591
Test name
Test status
Simulation time 207618556 ps
CPU time 1.09 seconds
Started Jul 01 06:37:48 PM PDT 24
Finished Jul 01 06:37:50 PM PDT 24
Peak memory 197852 kb
Host smart-5748fa80-17e5-4341-a3d7-0ac81f3367a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344372400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3344372400
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4205767680
Short name T253
Test name
Test status
Simulation time 29589747166 ps
CPU time 21.71 seconds
Started Jul 01 06:37:40 PM PDT 24
Finished Jul 01 06:38:02 PM PDT 24
Peak memory 200000 kb
Host smart-dce899f1-6afd-45c5-b72a-acb9cbf86525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205767680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4205767680
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.796996392
Short name T719
Test name
Test status
Simulation time 35947102660 ps
CPU time 50.85 seconds
Started Jul 01 06:42:54 PM PDT 24
Finished Jul 01 06:43:46 PM PDT 24
Peak memory 200124 kb
Host smart-0f60245b-83df-4e0e-a455-96563bdf1278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796996392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.796996392
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2266824995
Short name T477
Test name
Test status
Simulation time 55617907084 ps
CPU time 12.21 seconds
Started Jul 01 06:43:01 PM PDT 24
Finished Jul 01 06:43:16 PM PDT 24
Peak memory 199964 kb
Host smart-dca963f2-a91d-461d-8bf5-85604410febd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266824995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2266824995
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3636001941
Short name T204
Test name
Test status
Simulation time 148103530394 ps
CPU time 36.55 seconds
Started Jul 01 06:43:01 PM PDT 24
Finished Jul 01 06:43:40 PM PDT 24
Peak memory 200072 kb
Host smart-1380572c-2641-49f3-8e1f-674d38bfb3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636001941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3636001941
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2378602393
Short name T144
Test name
Test status
Simulation time 87486306519 ps
CPU time 139.45 seconds
Started Jul 01 06:43:02 PM PDT 24
Finished Jul 01 06:45:24 PM PDT 24
Peak memory 199916 kb
Host smart-4fb58aac-99ef-4194-a91b-4400f1c0400b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378602393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2378602393
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2640255144
Short name T581
Test name
Test status
Simulation time 36660468101 ps
CPU time 29.1 seconds
Started Jul 01 06:43:03 PM PDT 24
Finished Jul 01 06:43:35 PM PDT 24
Peak memory 200020 kb
Host smart-16257f8f-ced9-4e67-a5a7-154928502430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640255144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2640255144
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2134401085
Short name T347
Test name
Test status
Simulation time 81495776706 ps
CPU time 38.38 seconds
Started Jul 01 06:43:04 PM PDT 24
Finished Jul 01 06:43:44 PM PDT 24
Peak memory 200020 kb
Host smart-f0348bd4-eccb-4d81-ba79-2929d54b1924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134401085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2134401085
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2915936273
Short name T317
Test name
Test status
Simulation time 95124672387 ps
CPU time 195.35 seconds
Started Jul 01 06:43:02 PM PDT 24
Finished Jul 01 06:46:19 PM PDT 24
Peak memory 199916 kb
Host smart-06e70ce0-c50d-45a8-9eef-6837084fc45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915936273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2915936273
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2546073387
Short name T1004
Test name
Test status
Simulation time 153045156074 ps
CPU time 67.63 seconds
Started Jul 01 06:43:02 PM PDT 24
Finished Jul 01 06:44:12 PM PDT 24
Peak memory 200000 kb
Host smart-4baedb78-3e18-47ca-8f20-c6c0f29d0ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546073387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2546073387
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3697977967
Short name T892
Test name
Test status
Simulation time 10854887 ps
CPU time 0.56 seconds
Started Jul 01 06:38:01 PM PDT 24
Finished Jul 01 06:38:04 PM PDT 24
Peak memory 194352 kb
Host smart-2737a947-f680-4019-ba87-9dad3a1b2809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697977967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3697977967
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3831778535
Short name T149
Test name
Test status
Simulation time 80718341260 ps
CPU time 25.33 seconds
Started Jul 01 06:37:47 PM PDT 24
Finished Jul 01 06:38:14 PM PDT 24
Peak memory 199932 kb
Host smart-aacaca95-f509-494f-8a26-07cf290f482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831778535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3831778535
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1167634643
Short name T148
Test name
Test status
Simulation time 228754978786 ps
CPU time 144.19 seconds
Started Jul 01 06:37:45 PM PDT 24
Finished Jul 01 06:40:10 PM PDT 24
Peak memory 200004 kb
Host smart-4de5640e-673c-4f32-884c-8e981114e58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167634643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1167634643
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2975481344
Short name T989
Test name
Test status
Simulation time 105840117361 ps
CPU time 108.56 seconds
Started Jul 01 06:37:47 PM PDT 24
Finished Jul 01 06:39:37 PM PDT 24
Peak memory 200056 kb
Host smart-ef17658b-c907-460c-8e7b-1a3f6a04247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975481344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2975481344
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1934697088
Short name T648
Test name
Test status
Simulation time 4597278037 ps
CPU time 4.01 seconds
Started Jul 01 06:37:51 PM PDT 24
Finished Jul 01 06:37:56 PM PDT 24
Peak memory 196776 kb
Host smart-4300ac95-114d-45d4-a57a-efa79399dcee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934697088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1934697088
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.117889903
Short name T833
Test name
Test status
Simulation time 294664600375 ps
CPU time 218.59 seconds
Started Jul 01 06:37:53 PM PDT 24
Finished Jul 01 06:41:33 PM PDT 24
Peak memory 200044 kb
Host smart-6c028309-1d06-4026-910d-2270f8cc41c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117889903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.117889903
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2479712225
Short name T16
Test name
Test status
Simulation time 2949668182 ps
CPU time 6.62 seconds
Started Jul 01 06:37:55 PM PDT 24
Finished Jul 01 06:38:02 PM PDT 24
Peak memory 198936 kb
Host smart-146cf363-174e-4d4d-88da-80710c742356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479712225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2479712225
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1355074381
Short name T256
Test name
Test status
Simulation time 38287383895 ps
CPU time 17.44 seconds
Started Jul 01 06:37:52 PM PDT 24
Finished Jul 01 06:38:11 PM PDT 24
Peak memory 200048 kb
Host smart-0dfa922f-17ab-4ad5-8bea-ea8568d4883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355074381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1355074381
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2503867570
Short name T784
Test name
Test status
Simulation time 5663406456 ps
CPU time 76.52 seconds
Started Jul 01 06:37:51 PM PDT 24
Finished Jul 01 06:39:09 PM PDT 24
Peak memory 199976 kb
Host smart-7a6131c3-30fa-4bf7-93b8-ba82865493d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2503867570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2503867570
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3943116283
Short name T782
Test name
Test status
Simulation time 1380136292 ps
CPU time 1.51 seconds
Started Jul 01 06:37:44 PM PDT 24
Finished Jul 01 06:37:46 PM PDT 24
Peak memory 196256 kb
Host smart-e5f7c8c9-b7b5-45be-81c1-9748bea577a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3943116283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3943116283
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4190505347
Short name T858
Test name
Test status
Simulation time 66565067284 ps
CPU time 104.65 seconds
Started Jul 01 06:37:53 PM PDT 24
Finished Jul 01 06:39:39 PM PDT 24
Peak memory 199988 kb
Host smart-82dc12e0-01ac-465d-8388-3b048974111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190505347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4190505347
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.515994984
Short name T923
Test name
Test status
Simulation time 5173270625 ps
CPU time 7.57 seconds
Started Jul 01 06:37:52 PM PDT 24
Finished Jul 01 06:38:00 PM PDT 24
Peak memory 196428 kb
Host smart-e20949df-70b0-42e9-91f7-f1420f7fda76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515994984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.515994984
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1562944174
Short name T620
Test name
Test status
Simulation time 663570985 ps
CPU time 2.02 seconds
Started Jul 01 06:37:47 PM PDT 24
Finished Jul 01 06:37:51 PM PDT 24
Peak memory 198248 kb
Host smart-4745d938-eb2d-4a02-8347-eb7467a1474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562944174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1562944174
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2850641296
Short name T130
Test name
Test status
Simulation time 119252593592 ps
CPU time 33.61 seconds
Started Jul 01 06:37:53 PM PDT 24
Finished Jul 01 06:38:28 PM PDT 24
Peak memory 200036 kb
Host smart-a7499005-d3fe-455b-b8d9-00938afccc5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850641296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2850641296
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1310770093
Short name T371
Test name
Test status
Simulation time 1289163475 ps
CPU time 6.15 seconds
Started Jul 01 06:37:54 PM PDT 24
Finished Jul 01 06:38:01 PM PDT 24
Peak memory 199824 kb
Host smart-3a8dad62-7a4e-47b5-beb4-4f2b26c3d369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310770093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1310770093
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3197705490
Short name T310
Test name
Test status
Simulation time 87115782540 ps
CPU time 183.16 seconds
Started Jul 01 06:37:46 PM PDT 24
Finished Jul 01 06:40:51 PM PDT 24
Peak memory 200016 kb
Host smart-11d70720-0f13-4dbe-b7b6-c6ef76ce8167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197705490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3197705490
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.787608301
Short name T157
Test name
Test status
Simulation time 78835804065 ps
CPU time 247.05 seconds
Started Jul 01 06:43:01 PM PDT 24
Finished Jul 01 06:47:11 PM PDT 24
Peak memory 199940 kb
Host smart-9528cea1-53d0-481b-b70d-76b2c090a868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787608301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.787608301
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1483789040
Short name T491
Test name
Test status
Simulation time 127281201335 ps
CPU time 59.1 seconds
Started Jul 01 06:43:02 PM PDT 24
Finished Jul 01 06:44:04 PM PDT 24
Peak memory 200008 kb
Host smart-6db94ed7-2e81-4c67-9acb-11d28dcb68c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483789040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1483789040
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1312775960
Short name T199
Test name
Test status
Simulation time 61322238109 ps
CPU time 23.32 seconds
Started Jul 01 06:43:04 PM PDT 24
Finished Jul 01 06:43:29 PM PDT 24
Peak memory 200108 kb
Host smart-b0b2fde0-0923-4b9b-8bd9-9dcebb8f8e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312775960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1312775960
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.633491916
Short name T87
Test name
Test status
Simulation time 21859412104 ps
CPU time 16.67 seconds
Started Jul 01 06:43:13 PM PDT 24
Finished Jul 01 06:43:31 PM PDT 24
Peak memory 199516 kb
Host smart-5485c6c6-2476-4c21-ade3-c7837fefd5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633491916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.633491916
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1147981241
Short name T206
Test name
Test status
Simulation time 121156653034 ps
CPU time 81.6 seconds
Started Jul 01 06:43:13 PM PDT 24
Finished Jul 01 06:44:35 PM PDT 24
Peak memory 200140 kb
Host smart-a9e53fb8-0d1f-49f9-b3b5-5b22f648430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147981241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1147981241
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2985714047
Short name T231
Test name
Test status
Simulation time 157147643936 ps
CPU time 314.35 seconds
Started Jul 01 06:43:14 PM PDT 24
Finished Jul 01 06:48:29 PM PDT 24
Peak memory 200008 kb
Host smart-f2472609-0070-40b2-a699-ef179018b527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985714047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2985714047
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.272013505
Short name T806
Test name
Test status
Simulation time 46315944718 ps
CPU time 19.25 seconds
Started Jul 01 06:43:12 PM PDT 24
Finished Jul 01 06:43:32 PM PDT 24
Peak memory 199924 kb
Host smart-90c92c68-f561-4a5b-aac3-579bbd316308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272013505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.272013505
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3937469997
Short name T902
Test name
Test status
Simulation time 208296428711 ps
CPU time 70.42 seconds
Started Jul 01 06:43:13 PM PDT 24
Finished Jul 01 06:44:25 PM PDT 24
Peak memory 199988 kb
Host smart-fbca8b9f-39c8-42fb-951b-4d63fb3bda9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937469997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3937469997
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2874931525
Short name T724
Test name
Test status
Simulation time 110414639842 ps
CPU time 173.09 seconds
Started Jul 01 06:43:13 PM PDT 24
Finished Jul 01 06:46:07 PM PDT 24
Peak memory 200088 kb
Host smart-601ce619-de68-4fdc-af68-f723af08ca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874931525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2874931525
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.570722459
Short name T1038
Test name
Test status
Simulation time 86034010588 ps
CPU time 43.23 seconds
Started Jul 01 06:43:12 PM PDT 24
Finished Jul 01 06:43:56 PM PDT 24
Peak memory 199972 kb
Host smart-fd15cc56-6b5e-487a-83e3-8a6aeca6853c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570722459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.570722459
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3399218437
Short name T507
Test name
Test status
Simulation time 33615431 ps
CPU time 0.55 seconds
Started Jul 01 06:38:06 PM PDT 24
Finished Jul 01 06:38:10 PM PDT 24
Peak memory 195316 kb
Host smart-a491b8c1-447c-4741-aa1b-0f5486c6839d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399218437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3399218437
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.896848240
Short name T1087
Test name
Test status
Simulation time 153899074038 ps
CPU time 311.86 seconds
Started Jul 01 06:38:00 PM PDT 24
Finished Jul 01 06:43:13 PM PDT 24
Peak memory 199972 kb
Host smart-d11db818-7ab8-4dfb-aada-0fa43edeab7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896848240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.896848240
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2118301339
Short name T158
Test name
Test status
Simulation time 83561548012 ps
CPU time 64.83 seconds
Started Jul 01 06:37:59 PM PDT 24
Finished Jul 01 06:39:05 PM PDT 24
Peak memory 199992 kb
Host smart-99183864-054a-4327-b65b-cb55ad639940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118301339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2118301339
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3332929886
Short name T495
Test name
Test status
Simulation time 67435797350 ps
CPU time 28.3 seconds
Started Jul 01 06:37:59 PM PDT 24
Finished Jul 01 06:38:28 PM PDT 24
Peak memory 199996 kb
Host smart-2379c73b-8e78-466b-a011-6ee3b72c108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332929886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3332929886
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2170483408
Short name T416
Test name
Test status
Simulation time 34969712585 ps
CPU time 30.63 seconds
Started Jul 01 06:37:59 PM PDT 24
Finished Jul 01 06:38:30 PM PDT 24
Peak memory 199908 kb
Host smart-11755726-49b2-4211-b30a-4357e6f550d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170483408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2170483408
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2662608456
Short name T296
Test name
Test status
Simulation time 108314246558 ps
CPU time 617.25 seconds
Started Jul 01 06:38:06 PM PDT 24
Finished Jul 01 06:48:26 PM PDT 24
Peak memory 199920 kb
Host smart-3cb424ab-22c8-495c-9d70-b7e9fa8f53b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662608456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2662608456
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1421466624
Short name T1060
Test name
Test status
Simulation time 1316398957 ps
CPU time 1.16 seconds
Started Jul 01 06:38:05 PM PDT 24
Finished Jul 01 06:38:09 PM PDT 24
Peak memory 197288 kb
Host smart-f2d0159d-cf07-4f3b-a40d-0da815531cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421466624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1421466624
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.434905308
Short name T629
Test name
Test status
Simulation time 12098970727 ps
CPU time 361.59 seconds
Started Jul 01 06:38:05 PM PDT 24
Finished Jul 01 06:44:10 PM PDT 24
Peak memory 199932 kb
Host smart-23425e77-49be-42fd-a712-5d50856528f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434905308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.434905308
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2981948722
Short name T622
Test name
Test status
Simulation time 4803870925 ps
CPU time 13.74 seconds
Started Jul 01 06:38:03 PM PDT 24
Finished Jul 01 06:38:20 PM PDT 24
Peak memory 199416 kb
Host smart-eece23eb-ceb9-46b0-88e8-a0208ddecc07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981948722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2981948722
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2879148690
Short name T551
Test name
Test status
Simulation time 116225017251 ps
CPU time 62.89 seconds
Started Jul 01 06:38:02 PM PDT 24
Finished Jul 01 06:39:08 PM PDT 24
Peak memory 200028 kb
Host smart-cd55cee5-3593-4dfb-9961-afda343f82f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879148690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2879148690
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4092775339
Short name T1006
Test name
Test status
Simulation time 24370384057 ps
CPU time 36.32 seconds
Started Jul 01 06:38:01 PM PDT 24
Finished Jul 01 06:38:40 PM PDT 24
Peak memory 195876 kb
Host smart-8d08bb72-3b66-4574-bdb5-5717d17f0856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092775339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4092775339
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2013886554
Short name T1051
Test name
Test status
Simulation time 140294529 ps
CPU time 0.84 seconds
Started Jul 01 06:37:57 PM PDT 24
Finished Jul 01 06:37:59 PM PDT 24
Peak memory 197164 kb
Host smart-d2fd8ea8-534a-4c18-9429-7b7799ed2874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013886554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2013886554
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3325385076
Short name T644
Test name
Test status
Simulation time 7813247540 ps
CPU time 10.2 seconds
Started Jul 01 06:38:01 PM PDT 24
Finished Jul 01 06:38:12 PM PDT 24
Peak memory 199956 kb
Host smart-d5c77aec-ab4b-49cb-8a0c-6574dd2d9954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325385076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3325385076
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2545846369
Short name T265
Test name
Test status
Simulation time 59099469373 ps
CPU time 36.52 seconds
Started Jul 01 06:38:00 PM PDT 24
Finished Jul 01 06:38:38 PM PDT 24
Peak memory 200004 kb
Host smart-c15e2cbe-0fdd-4a69-8563-fedc500adc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545846369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2545846369
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2202134964
Short name T48
Test name
Test status
Simulation time 22165509213 ps
CPU time 10.61 seconds
Started Jul 01 06:43:13 PM PDT 24
Finished Jul 01 06:43:24 PM PDT 24
Peak memory 199936 kb
Host smart-d2dec638-c164-4d95-8072-3ead02309bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202134964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2202134964
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.4290360035
Short name T336
Test name
Test status
Simulation time 70478047709 ps
CPU time 16.12 seconds
Started Jul 01 06:43:12 PM PDT 24
Finished Jul 01 06:43:29 PM PDT 24
Peak memory 199936 kb
Host smart-fe4bfa6a-c786-443d-a5a2-ecc33ebecec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290360035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.4290360035
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.176070134
Short name T312
Test name
Test status
Simulation time 88865961111 ps
CPU time 11.96 seconds
Started Jul 01 06:43:13 PM PDT 24
Finished Jul 01 06:43:25 PM PDT 24
Peak memory 200008 kb
Host smart-692963b6-eaec-4369-98da-c0a16ebb01e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176070134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.176070134
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1438719563
Short name T969
Test name
Test status
Simulation time 30689647099 ps
CPU time 16 seconds
Started Jul 01 06:43:14 PM PDT 24
Finished Jul 01 06:43:31 PM PDT 24
Peak memory 200000 kb
Host smart-2c38df2f-cb8c-452e-8b79-365ca38e9479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438719563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1438719563
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2616149661
Short name T225
Test name
Test status
Simulation time 79242275634 ps
CPU time 18.22 seconds
Started Jul 01 06:43:13 PM PDT 24
Finished Jul 01 06:43:33 PM PDT 24
Peak memory 200008 kb
Host smart-94482fd1-a85c-48c6-9a43-4bacd7e4b847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616149661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2616149661
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.4051140866
Short name T945
Test name
Test status
Simulation time 85957388079 ps
CPU time 33.58 seconds
Started Jul 01 06:43:14 PM PDT 24
Finished Jul 01 06:43:48 PM PDT 24
Peak memory 199996 kb
Host smart-18304bb1-e0e6-4597-816d-32089bd0ebb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051140866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.4051140866
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1115973741
Short name T435
Test name
Test status
Simulation time 117218713219 ps
CPU time 50.57 seconds
Started Jul 01 06:43:19 PM PDT 24
Finished Jul 01 06:44:11 PM PDT 24
Peak memory 200040 kb
Host smart-fe24cad7-e725-4cf5-9c37-8ffcb870a0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115973741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1115973741
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3545646882
Short name T851
Test name
Test status
Simulation time 18148606191 ps
CPU time 25.99 seconds
Started Jul 01 06:43:21 PM PDT 24
Finished Jul 01 06:43:49 PM PDT 24
Peak memory 199836 kb
Host smart-42302265-4502-4629-8955-bfb17394b420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545646882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3545646882
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2167424324
Short name T909
Test name
Test status
Simulation time 125807656830 ps
CPU time 67.6 seconds
Started Jul 01 06:43:25 PM PDT 24
Finished Jul 01 06:44:34 PM PDT 24
Peak memory 199576 kb
Host smart-e414f19a-8a9f-475b-95de-f306eaa08285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167424324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2167424324
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.305375354
Short name T19
Test name
Test status
Simulation time 12943153 ps
CPU time 0.56 seconds
Started Jul 01 06:34:56 PM PDT 24
Finished Jul 01 06:34:58 PM PDT 24
Peak memory 195380 kb
Host smart-929d9ff2-0211-430f-97b8-2745d3763182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305375354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.305375354
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3069915164
Short name T602
Test name
Test status
Simulation time 65924253268 ps
CPU time 24.9 seconds
Started Jul 01 06:34:45 PM PDT 24
Finished Jul 01 06:35:14 PM PDT 24
Peak memory 199948 kb
Host smart-7aedb67c-5a7a-46da-98ca-a2b7145c93a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069915164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3069915164
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2892840517
Short name T165
Test name
Test status
Simulation time 26447766644 ps
CPU time 57.88 seconds
Started Jul 01 06:34:46 PM PDT 24
Finished Jul 01 06:35:47 PM PDT 24
Peak memory 199996 kb
Host smart-4f1c7743-836f-4eef-95e8-120e8a9f0b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892840517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2892840517
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.835716137
Short name T328
Test name
Test status
Simulation time 7946810904 ps
CPU time 10.06 seconds
Started Jul 01 06:34:46 PM PDT 24
Finished Jul 01 06:34:59 PM PDT 24
Peak memory 199988 kb
Host smart-c90b69cd-7751-49c5-8838-8883f79ce069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835716137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.835716137
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4268571739
Short name T572
Test name
Test status
Simulation time 41799655043 ps
CPU time 67.11 seconds
Started Jul 01 06:34:47 PM PDT 24
Finished Jul 01 06:35:57 PM PDT 24
Peak memory 199984 kb
Host smart-f46f577c-e274-46f5-883a-fe47a6f119a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268571739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4268571739
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3643041637
Short name T372
Test name
Test status
Simulation time 64789672819 ps
CPU time 289.76 seconds
Started Jul 01 06:34:50 PM PDT 24
Finished Jul 01 06:39:41 PM PDT 24
Peak memory 199960 kb
Host smart-64083e34-6cf7-4fa6-84d4-c78b690c33e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643041637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3643041637
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1114666888
Short name T682
Test name
Test status
Simulation time 3065445746 ps
CPU time 7.23 seconds
Started Jul 01 06:34:46 PM PDT 24
Finished Jul 01 06:34:56 PM PDT 24
Peak memory 199528 kb
Host smart-f6f9a10e-ba41-4866-a1b5-870ab69db053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114666888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1114666888
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.1815069405
Short name T778
Test name
Test status
Simulation time 25880820459 ps
CPU time 138.11 seconds
Started Jul 01 06:34:45 PM PDT 24
Finished Jul 01 06:37:07 PM PDT 24
Peak memory 199992 kb
Host smart-d6071a68-f08f-4a80-813e-9364aa2253a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815069405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1815069405
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2347031439
Short name T66
Test name
Test status
Simulation time 6891969060 ps
CPU time 67.29 seconds
Started Jul 01 06:34:45 PM PDT 24
Finished Jul 01 06:35:56 PM PDT 24
Peak memory 198192 kb
Host smart-52009549-7007-4733-83bf-d1e633a9ab42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347031439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2347031439
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2485068121
Short name T614
Test name
Test status
Simulation time 150070872726 ps
CPU time 207.29 seconds
Started Jul 01 06:34:46 PM PDT 24
Finished Jul 01 06:38:16 PM PDT 24
Peak memory 199912 kb
Host smart-fdbdea3a-14c6-4125-aeb7-94e113609e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485068121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2485068121
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2261196650
Short name T786
Test name
Test status
Simulation time 38365790347 ps
CPU time 64.28 seconds
Started Jul 01 06:34:49 PM PDT 24
Finished Jul 01 06:35:55 PM PDT 24
Peak memory 196464 kb
Host smart-dd4e527d-7c01-4660-b384-e1d9f1ba5793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261196650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2261196650
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.144651160
Short name T24
Test name
Test status
Simulation time 60881883 ps
CPU time 0.85 seconds
Started Jul 01 06:34:46 PM PDT 24
Finished Jul 01 06:34:50 PM PDT 24
Peak memory 218340 kb
Host smart-17a1c332-aa0d-4641-b99c-8146c35c9131
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144651160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.144651160
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1421208375
Short name T890
Test name
Test status
Simulation time 6206878246 ps
CPU time 12.06 seconds
Started Jul 01 06:34:37 PM PDT 24
Finished Jul 01 06:34:52 PM PDT 24
Peak memory 199320 kb
Host smart-1dcf909b-b012-4006-b845-5e50c6add7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421208375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1421208375
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3379806440
Short name T773
Test name
Test status
Simulation time 33457647080 ps
CPU time 1446.36 seconds
Started Jul 01 06:34:47 PM PDT 24
Finished Jul 01 06:58:56 PM PDT 24
Peak memory 199976 kb
Host smart-ec23dfda-9047-47d4-8c7f-bace97c236c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379806440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3379806440
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.491680973
Short name T700
Test name
Test status
Simulation time 1424359860 ps
CPU time 2.9 seconds
Started Jul 01 06:34:46 PM PDT 24
Finished Jul 01 06:34:52 PM PDT 24
Peak memory 199252 kb
Host smart-8f935d09-ada7-440a-a566-fda8ce2a8166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491680973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.491680973
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.743499180
Short name T1069
Test name
Test status
Simulation time 80783696313 ps
CPU time 196.03 seconds
Started Jul 01 06:34:42 PM PDT 24
Finished Jul 01 06:38:03 PM PDT 24
Peak memory 199916 kb
Host smart-5ed1965c-6337-412c-bf1e-152de8efeeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743499180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.743499180
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.893372509
Short name T878
Test name
Test status
Simulation time 12761403 ps
CPU time 0.53 seconds
Started Jul 01 06:38:13 PM PDT 24
Finished Jul 01 06:38:17 PM PDT 24
Peak memory 195312 kb
Host smart-8c0e8e7e-aec6-40c3-8ca3-d6d9bd29d65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893372509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.893372509
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2498493984
Short name T603
Test name
Test status
Simulation time 86957720633 ps
CPU time 176.62 seconds
Started Jul 01 06:38:06 PM PDT 24
Finished Jul 01 06:41:06 PM PDT 24
Peak memory 199936 kb
Host smart-0bfe0b96-2d13-4203-8020-2187e4f61dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498493984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2498493984
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1196909803
Short name T612
Test name
Test status
Simulation time 175336614506 ps
CPU time 63.2 seconds
Started Jul 01 06:38:05 PM PDT 24
Finished Jul 01 06:39:11 PM PDT 24
Peak memory 199964 kb
Host smart-c395f9c9-6523-46fa-ad1b-d827fecd147b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196909803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1196909803
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.677401797
Short name T179
Test name
Test status
Simulation time 75784834240 ps
CPU time 32.55 seconds
Started Jul 01 06:38:06 PM PDT 24
Finished Jul 01 06:38:42 PM PDT 24
Peak memory 200052 kb
Host smart-b33a116a-1d6a-4171-9bcc-110d700371bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677401797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.677401797
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4123923901
Short name T842
Test name
Test status
Simulation time 48467070148 ps
CPU time 47.7 seconds
Started Jul 01 06:38:09 PM PDT 24
Finished Jul 01 06:38:59 PM PDT 24
Peak memory 199948 kb
Host smart-81621451-ba20-46f2-90f8-674ea4477fde
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123923901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4123923901
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.364148521
Short name T433
Test name
Test status
Simulation time 129903689881 ps
CPU time 659.8 seconds
Started Jul 01 06:38:15 PM PDT 24
Finished Jul 01 06:49:18 PM PDT 24
Peak memory 199904 kb
Host smart-eb2ca239-5a46-49bd-b1f6-2c4b2b7202d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364148521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.364148521
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1751582281
Short name T342
Test name
Test status
Simulation time 3977600681 ps
CPU time 3.97 seconds
Started Jul 01 06:38:05 PM PDT 24
Finished Jul 01 06:38:12 PM PDT 24
Peak memory 198868 kb
Host smart-2057fe33-56ac-469a-8c6f-607d246bcd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751582281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1751582281
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.2941951268
Short name T968
Test name
Test status
Simulation time 35041605255 ps
CPU time 208.55 seconds
Started Jul 01 06:38:12 PM PDT 24
Finished Jul 01 06:41:44 PM PDT 24
Peak memory 199968 kb
Host smart-5cc94a0d-1e31-4bc3-8ea1-2f1d99ee9952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2941951268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2941951268
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2784523001
Short name T361
Test name
Test status
Simulation time 6971812939 ps
CPU time 31.13 seconds
Started Jul 01 06:38:04 PM PDT 24
Finished Jul 01 06:38:38 PM PDT 24
Peak memory 199288 kb
Host smart-f86024b2-1c06-469e-a056-94cbad513507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784523001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2784523001
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.651990315
Short name T738
Test name
Test status
Simulation time 30146105343 ps
CPU time 23.27 seconds
Started Jul 01 06:38:06 PM PDT 24
Finished Jul 01 06:38:32 PM PDT 24
Peak memory 195736 kb
Host smart-13a1c5ef-1234-4096-be61-471e8d0e3693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651990315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.651990315
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.955362536
Short name T294
Test name
Test status
Simulation time 5859992438 ps
CPU time 7.02 seconds
Started Jul 01 06:38:05 PM PDT 24
Finished Jul 01 06:38:15 PM PDT 24
Peak memory 199740 kb
Host smart-64828187-d436-456d-aece-8a96362ca202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955362536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.955362536
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3954961141
Short name T227
Test name
Test status
Simulation time 237307929983 ps
CPU time 77.43 seconds
Started Jul 01 06:38:13 PM PDT 24
Finished Jul 01 06:39:34 PM PDT 24
Peak memory 200016 kb
Host smart-fc91d692-e643-4e57-bec4-52f42b59b251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954961141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3954961141
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2359607135
Short name T6
Test name
Test status
Simulation time 6743798019 ps
CPU time 12.59 seconds
Started Jul 01 06:38:05 PM PDT 24
Finished Jul 01 06:38:20 PM PDT 24
Peak memory 199912 kb
Host smart-771b6ece-7b2a-415e-9ed5-57763de42b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359607135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2359607135
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.110677087
Short name T815
Test name
Test status
Simulation time 27840119196 ps
CPU time 34.35 seconds
Started Jul 01 06:38:06 PM PDT 24
Finished Jul 01 06:38:44 PM PDT 24
Peak memory 199912 kb
Host smart-b30faf8b-4155-4c38-8d32-05d4efda2974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110677087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.110677087
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1231333226
Short name T937
Test name
Test status
Simulation time 32858559 ps
CPU time 0.62 seconds
Started Jul 01 06:38:14 PM PDT 24
Finished Jul 01 06:38:18 PM PDT 24
Peak memory 195316 kb
Host smart-0b42abf8-2e5c-4f70-8b11-34ac661df83c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231333226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1231333226
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.94716281
Short name T277
Test name
Test status
Simulation time 86069993290 ps
CPU time 125.24 seconds
Started Jul 01 06:38:14 PM PDT 24
Finished Jul 01 06:40:22 PM PDT 24
Peak memory 199964 kb
Host smart-61ffaf1d-3c1e-41f5-8f0c-310611e87d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94716281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.94716281
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.4072357060
Short name T841
Test name
Test status
Simulation time 59595128282 ps
CPU time 21.06 seconds
Started Jul 01 06:38:14 PM PDT 24
Finished Jul 01 06:38:38 PM PDT 24
Peak memory 199996 kb
Host smart-186dd063-8343-496f-93b1-a271b4d74da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072357060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.4072357060
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_intr.3763842215
Short name T1076
Test name
Test status
Simulation time 204708296413 ps
CPU time 144.64 seconds
Started Jul 01 06:38:16 PM PDT 24
Finished Jul 01 06:40:43 PM PDT 24
Peak memory 197676 kb
Host smart-e67a9343-1d80-4c35-a9e0-c4a8768c8ae9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763842215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3763842215
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1585268645
Short name T660
Test name
Test status
Simulation time 80105714041 ps
CPU time 417.46 seconds
Started Jul 01 06:38:11 PM PDT 24
Finished Jul 01 06:45:12 PM PDT 24
Peak memory 199980 kb
Host smart-3be90632-f829-4638-8c6b-5c77288c62dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585268645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1585268645
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1469164059
Short name T1027
Test name
Test status
Simulation time 4147892870 ps
CPU time 15.27 seconds
Started Jul 01 06:38:13 PM PDT 24
Finished Jul 01 06:38:32 PM PDT 24
Peak memory 198772 kb
Host smart-70ba7c34-4908-4feb-9535-1031874292c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469164059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1469164059
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3654483328
Short name T681
Test name
Test status
Simulation time 22711270636 ps
CPU time 41.9 seconds
Started Jul 01 06:38:13 PM PDT 24
Finished Jul 01 06:38:59 PM PDT 24
Peak memory 200040 kb
Host smart-7e9802bb-eb22-4ad3-9b88-ab160a640eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654483328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3654483328
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3619505498
Short name T255
Test name
Test status
Simulation time 17111642370 ps
CPU time 320.76 seconds
Started Jul 01 06:38:13 PM PDT 24
Finished Jul 01 06:43:36 PM PDT 24
Peak memory 200132 kb
Host smart-f53de1c4-674b-4964-a491-cc53b448ef2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619505498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3619505498
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2895678173
Short name T1036
Test name
Test status
Simulation time 3344393777 ps
CPU time 21.04 seconds
Started Jul 01 06:38:13 PM PDT 24
Finished Jul 01 06:38:37 PM PDT 24
Peak memory 198408 kb
Host smart-7ed2d49d-4d52-43d2-8b00-12c9294a57fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2895678173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2895678173
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1920852806
Short name T409
Test name
Test status
Simulation time 173709964967 ps
CPU time 101.88 seconds
Started Jul 01 06:38:13 PM PDT 24
Finished Jul 01 06:39:58 PM PDT 24
Peak memory 200028 kb
Host smart-95eee854-7903-457e-9ec0-4c2e12e314ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920852806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1920852806
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3550091524
Short name T452
Test name
Test status
Simulation time 31323018958 ps
CPU time 49.27 seconds
Started Jul 01 06:38:15 PM PDT 24
Finished Jul 01 06:39:08 PM PDT 24
Peak memory 196044 kb
Host smart-332fb558-da1a-4149-81a4-643d7dfedb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550091524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3550091524
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2159414461
Short name T86
Test name
Test status
Simulation time 10585417149 ps
CPU time 37.92 seconds
Started Jul 01 06:38:15 PM PDT 24
Finished Jul 01 06:38:56 PM PDT 24
Peak memory 199952 kb
Host smart-bcf773ff-2262-4e33-baa9-849395d61f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159414461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2159414461
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1342205670
Short name T245
Test name
Test status
Simulation time 61114830980 ps
CPU time 99.96 seconds
Started Jul 01 06:38:16 PM PDT 24
Finished Jul 01 06:39:58 PM PDT 24
Peak memory 200064 kb
Host smart-9d61bccb-a307-45ff-a368-704738159d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342205670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1342205670
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2426274588
Short name T257
Test name
Test status
Simulation time 376828539 ps
CPU time 1.47 seconds
Started Jul 01 06:38:13 PM PDT 24
Finished Jul 01 06:38:17 PM PDT 24
Peak memory 198500 kb
Host smart-46762b79-5c09-48f1-9430-731dec18fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426274588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2426274588
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3276411669
Short name T303
Test name
Test status
Simulation time 160384651532 ps
CPU time 31 seconds
Started Jul 01 06:38:14 PM PDT 24
Finished Jul 01 06:38:48 PM PDT 24
Peak memory 200004 kb
Host smart-f9878466-1026-4282-bb97-23950fc86004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276411669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3276411669
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1673898822
Short name T853
Test name
Test status
Simulation time 19022189 ps
CPU time 0.56 seconds
Started Jul 01 06:38:32 PM PDT 24
Finished Jul 01 06:38:36 PM PDT 24
Peak memory 195416 kb
Host smart-44956a2f-d814-4c3b-8080-bf771ebcec93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673898822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1673898822
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.4017283686
Short name T1053
Test name
Test status
Simulation time 66600245680 ps
CPU time 120.74 seconds
Started Jul 01 06:38:23 PM PDT 24
Finished Jul 01 06:40:25 PM PDT 24
Peak memory 199976 kb
Host smart-9dee3c18-7f61-4410-82e0-8da8137abcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017283686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.4017283686
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2915468919
Short name T554
Test name
Test status
Simulation time 4967029587 ps
CPU time 7.36 seconds
Started Jul 01 06:38:20 PM PDT 24
Finished Jul 01 06:38:29 PM PDT 24
Peak memory 199704 kb
Host smart-0dba4f91-ffdc-4041-9835-3675b9f1b239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915468919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2915468919
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.4155714088
Short name T201
Test name
Test status
Simulation time 171218316695 ps
CPU time 44.51 seconds
Started Jul 01 06:38:22 PM PDT 24
Finished Jul 01 06:39:08 PM PDT 24
Peak memory 199996 kb
Host smart-94946e2b-cd24-42dd-8133-ad4b738cb854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155714088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.4155714088
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1827959044
Short name T691
Test name
Test status
Simulation time 272178688628 ps
CPU time 198.78 seconds
Started Jul 01 06:38:20 PM PDT 24
Finished Jul 01 06:41:40 PM PDT 24
Peak memory 198920 kb
Host smart-402e3bbb-65a2-4f3c-95ef-698e16995dc3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827959044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1827959044
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3438016970
Short name T493
Test name
Test status
Simulation time 108849465664 ps
CPU time 398.69 seconds
Started Jul 01 06:38:31 PM PDT 24
Finished Jul 01 06:45:13 PM PDT 24
Peak memory 199948 kb
Host smart-a86a64de-4d65-4176-958a-54bcb96e4007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438016970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3438016970
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.714651839
Short name T593
Test name
Test status
Simulation time 1202442436 ps
CPU time 3.28 seconds
Started Jul 01 06:38:21 PM PDT 24
Finished Jul 01 06:38:26 PM PDT 24
Peak memory 198744 kb
Host smart-7f178127-a705-43e6-90dd-05d70a5c04a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714651839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.714651839
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2623939579
Short name T900
Test name
Test status
Simulation time 9664548241 ps
CPU time 15.1 seconds
Started Jul 01 06:38:24 PM PDT 24
Finished Jul 01 06:38:42 PM PDT 24
Peak memory 198140 kb
Host smart-2b88a84e-1631-4736-a2a7-d1f0bb1fbf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623939579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2623939579
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.544449483
Short name T1080
Test name
Test status
Simulation time 16823952170 ps
CPU time 975.51 seconds
Started Jul 01 06:38:28 PM PDT 24
Finished Jul 01 06:54:47 PM PDT 24
Peak memory 199984 kb
Host smart-37330b9a-83a5-4415-94a4-9953387dc4a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544449483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.544449483
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1992507939
Short name T7
Test name
Test status
Simulation time 3456863092 ps
CPU time 11.99 seconds
Started Jul 01 06:38:22 PM PDT 24
Finished Jul 01 06:38:35 PM PDT 24
Peak memory 198412 kb
Host smart-99af8b66-cae4-466d-aed8-ae09c440fd2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992507939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1992507939
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1431222311
Short name T306
Test name
Test status
Simulation time 81520983531 ps
CPU time 180.02 seconds
Started Jul 01 06:38:23 PM PDT 24
Finished Jul 01 06:41:24 PM PDT 24
Peak memory 199996 kb
Host smart-72e47e60-2a54-454c-9b68-c3404edc7083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431222311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1431222311
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1347126240
Short name T357
Test name
Test status
Simulation time 1990836514 ps
CPU time 3.67 seconds
Started Jul 01 06:38:21 PM PDT 24
Finished Jul 01 06:38:26 PM PDT 24
Peak memory 195476 kb
Host smart-d15f8a68-2c94-408d-b81e-1efe044f0f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347126240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1347126240
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.273382788
Short name T274
Test name
Test status
Simulation time 6248312113 ps
CPU time 10.79 seconds
Started Jul 01 06:38:23 PM PDT 24
Finished Jul 01 06:38:35 PM PDT 24
Peak memory 199796 kb
Host smart-7a920f30-e5d0-458c-b06c-cb47d7b43d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273382788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.273382788
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2249084902
Short name T278
Test name
Test status
Simulation time 146478822382 ps
CPU time 210.62 seconds
Started Jul 01 06:38:28 PM PDT 24
Finished Jul 01 06:42:02 PM PDT 24
Peak memory 199996 kb
Host smart-548e0d8b-cceb-4500-b0e3-d59be90e1e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249084902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2249084902
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1264788219
Short name T136
Test name
Test status
Simulation time 224471719295 ps
CPU time 281.3 seconds
Started Jul 01 06:38:28 PM PDT 24
Finished Jul 01 06:43:12 PM PDT 24
Peak memory 212984 kb
Host smart-a53eaaae-1024-4ed3-afd2-a2485cf55295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264788219 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1264788219
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3372561796
Short name T669
Test name
Test status
Simulation time 877050344 ps
CPU time 2.42 seconds
Started Jul 01 06:38:21 PM PDT 24
Finished Jul 01 06:38:24 PM PDT 24
Peak memory 198820 kb
Host smart-e6855a24-491b-4c73-984d-90050d303f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372561796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3372561796
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1766922180
Short name T952
Test name
Test status
Simulation time 99756159616 ps
CPU time 85.2 seconds
Started Jul 01 06:38:24 PM PDT 24
Finished Jul 01 06:39:52 PM PDT 24
Peak memory 199908 kb
Host smart-d5b13b78-be36-49f3-920c-3847824ed05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766922180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1766922180
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.4093514663
Short name T1026
Test name
Test status
Simulation time 23018499 ps
CPU time 0.56 seconds
Started Jul 01 06:38:37 PM PDT 24
Finished Jul 01 06:38:39 PM PDT 24
Peak memory 195312 kb
Host smart-42f31489-3542-4744-bf17-769515e17e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093514663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.4093514663
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2582015905
Short name T437
Test name
Test status
Simulation time 38434874518 ps
CPU time 60.44 seconds
Started Jul 01 06:38:27 PM PDT 24
Finished Jul 01 06:39:31 PM PDT 24
Peak memory 200008 kb
Host smart-7ec9b5f2-eb2b-4f29-ba40-e01c551df736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582015905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2582015905
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3584044019
Short name T423
Test name
Test status
Simulation time 145795444752 ps
CPU time 16.99 seconds
Started Jul 01 06:38:28 PM PDT 24
Finished Jul 01 06:38:49 PM PDT 24
Peak memory 199936 kb
Host smart-65905970-a470-401f-aa48-4e33514070fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584044019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3584044019
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3778024570
Short name T226
Test name
Test status
Simulation time 19205873871 ps
CPU time 32.47 seconds
Started Jul 01 06:38:29 PM PDT 24
Finished Jul 01 06:39:05 PM PDT 24
Peak memory 199976 kb
Host smart-d8b5e68b-bba8-4a19-bbbe-50d55438b0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778024570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3778024570
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.742690854
Short name T896
Test name
Test status
Simulation time 356849332373 ps
CPU time 138.07 seconds
Started Jul 01 06:38:32 PM PDT 24
Finished Jul 01 06:40:53 PM PDT 24
Peak memory 198376 kb
Host smart-ffaf4b34-0a0f-463c-b5be-7dec50deaa26
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742690854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.742690854
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1379195437
Short name T571
Test name
Test status
Simulation time 156407178657 ps
CPU time 387.13 seconds
Started Jul 01 06:38:39 PM PDT 24
Finished Jul 01 06:45:08 PM PDT 24
Peak memory 199908 kb
Host smart-d53ccbfe-8ea5-4331-b822-e3e6c1557807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379195437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1379195437
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2065651155
Short name T865
Test name
Test status
Simulation time 11088449242 ps
CPU time 16.45 seconds
Started Jul 01 06:38:34 PM PDT 24
Finished Jul 01 06:38:53 PM PDT 24
Peak memory 198196 kb
Host smart-a4a3cbbe-a581-4f7a-a7c0-ad128cc18b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065651155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2065651155
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3932827687
Short name T864
Test name
Test status
Simulation time 55596343735 ps
CPU time 25.86 seconds
Started Jul 01 06:38:29 PM PDT 24
Finished Jul 01 06:38:59 PM PDT 24
Peak memory 199828 kb
Host smart-43344456-4339-4f30-81d4-d783e7495b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932827687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3932827687
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3988932407
Short name T481
Test name
Test status
Simulation time 38319700123 ps
CPU time 2350.3 seconds
Started Jul 01 06:38:31 PM PDT 24
Finished Jul 01 07:17:45 PM PDT 24
Peak memory 199976 kb
Host smart-47f75394-b7f4-49e6-874e-d687c5c55677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988932407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3988932407
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2438226613
Short name T678
Test name
Test status
Simulation time 1794438557 ps
CPU time 3.78 seconds
Started Jul 01 06:38:28 PM PDT 24
Finished Jul 01 06:38:36 PM PDT 24
Peak memory 197968 kb
Host smart-ec7936d9-56bc-413c-84e7-94089be0b4ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438226613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2438226613
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2722891802
Short name T550
Test name
Test status
Simulation time 35634527896 ps
CPU time 55.38 seconds
Started Jul 01 06:38:28 PM PDT 24
Finished Jul 01 06:39:27 PM PDT 24
Peak memory 199980 kb
Host smart-b27207be-ddf3-4b69-9141-d0072f869448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722891802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2722891802
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.458738496
Short name T402
Test name
Test status
Simulation time 4210563113 ps
CPU time 6.14 seconds
Started Jul 01 06:38:34 PM PDT 24
Finished Jul 01 06:38:43 PM PDT 24
Peak memory 196000 kb
Host smart-1cb5d99d-5281-4d23-bd53-c285a74fbc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458738496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.458738496
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2339846836
Short name T556
Test name
Test status
Simulation time 523403993 ps
CPU time 1.68 seconds
Started Jul 01 06:38:29 PM PDT 24
Finished Jul 01 06:38:35 PM PDT 24
Peak memory 199748 kb
Host smart-ca2bd638-2505-4155-81ba-553e0ac7b62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339846836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2339846836
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1272995534
Short name T658
Test name
Test status
Simulation time 2846363655 ps
CPU time 2.08 seconds
Started Jul 01 06:38:31 PM PDT 24
Finished Jul 01 06:38:36 PM PDT 24
Peak memory 198480 kb
Host smart-ee6593a7-dc62-4c23-9f7c-91aa198d6e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272995534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1272995534
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1367134786
Short name T718
Test name
Test status
Simulation time 174199417348 ps
CPU time 139.51 seconds
Started Jul 01 06:38:28 PM PDT 24
Finished Jul 01 06:40:51 PM PDT 24
Peak memory 200112 kb
Host smart-23ef5cd2-da9b-4e4b-87d1-a96dc2d5de50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367134786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1367134786
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2646908150
Short name T818
Test name
Test status
Simulation time 40749730 ps
CPU time 0.55 seconds
Started Jul 01 06:38:41 PM PDT 24
Finished Jul 01 06:38:43 PM PDT 24
Peak memory 195360 kb
Host smart-68c62e01-40bf-4732-b835-fbdf256d75be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646908150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2646908150
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1580461296
Short name T150
Test name
Test status
Simulation time 135834762993 ps
CPU time 98.87 seconds
Started Jul 01 06:38:36 PM PDT 24
Finished Jul 01 06:40:17 PM PDT 24
Peak memory 200048 kb
Host smart-0545e03f-fd1d-4f94-ac08-9721fdadb8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580461296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1580461296
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2902066352
Short name T822
Test name
Test status
Simulation time 53462170540 ps
CPU time 45.81 seconds
Started Jul 01 06:38:39 PM PDT 24
Finished Jul 01 06:39:26 PM PDT 24
Peak memory 199936 kb
Host smart-18179644-712f-47df-8944-56f0e4aa53b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902066352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2902066352
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3912933200
Short name T1075
Test name
Test status
Simulation time 79108958112 ps
CPU time 115.52 seconds
Started Jul 01 06:38:41 PM PDT 24
Finished Jul 01 06:40:37 PM PDT 24
Peak memory 199912 kb
Host smart-69c2fa1a-1303-4f63-a554-a7ea22ea0b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912933200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3912933200
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3604049585
Short name T470
Test name
Test status
Simulation time 11020969177 ps
CPU time 17.75 seconds
Started Jul 01 06:38:36 PM PDT 24
Finished Jul 01 06:38:56 PM PDT 24
Peak memory 199612 kb
Host smart-c0f0f406-1ec4-47a8-8948-abf51c9aafbb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604049585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3604049585
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2178919262
Short name T427
Test name
Test status
Simulation time 54195306699 ps
CPU time 177.64 seconds
Started Jul 01 06:38:44 PM PDT 24
Finished Jul 01 06:41:42 PM PDT 24
Peak memory 199948 kb
Host smart-835fd6cb-399f-4043-90f1-7be0181b3f13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178919262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2178919262
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1850230132
Short name T625
Test name
Test status
Simulation time 7030061783 ps
CPU time 13.01 seconds
Started Jul 01 06:38:38 PM PDT 24
Finished Jul 01 06:38:52 PM PDT 24
Peak memory 198504 kb
Host smart-4aa85130-d919-4e74-b77a-46385645d9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850230132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1850230132
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.4008520927
Short name T281
Test name
Test status
Simulation time 21229760786 ps
CPU time 1109.35 seconds
Started Jul 01 06:38:42 PM PDT 24
Finished Jul 01 06:57:13 PM PDT 24
Peak memory 199876 kb
Host smart-47f903af-f458-4590-aecc-b8102fb5718f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4008520927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4008520927
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1607708324
Short name T392
Test name
Test status
Simulation time 1812863177 ps
CPU time 2.47 seconds
Started Jul 01 06:38:36 PM PDT 24
Finished Jul 01 06:38:40 PM PDT 24
Peak memory 199204 kb
Host smart-97e98af8-19d1-4e46-b7a2-dc0c1969567f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1607708324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1607708324
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4228687628
Short name T562
Test name
Test status
Simulation time 144183136833 ps
CPU time 73.57 seconds
Started Jul 01 06:38:36 PM PDT 24
Finished Jul 01 06:39:51 PM PDT 24
Peak memory 200020 kb
Host smart-a0c5ddbd-612a-4471-8b99-7d3f17bcd8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228687628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4228687628
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.4225156854
Short name T410
Test name
Test status
Simulation time 31785753192 ps
CPU time 44.37 seconds
Started Jul 01 06:38:39 PM PDT 24
Finished Jul 01 06:39:24 PM PDT 24
Peak memory 196844 kb
Host smart-d31aa435-f29c-4122-b3f8-fcb51778b117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225156854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4225156854
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3472014042
Short name T966
Test name
Test status
Simulation time 448416893 ps
CPU time 2.23 seconds
Started Jul 01 06:38:37 PM PDT 24
Finished Jul 01 06:38:41 PM PDT 24
Peak memory 199020 kb
Host smart-b0e4668a-09c0-4122-9f36-969e92428973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472014042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3472014042
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3101575097
Short name T319
Test name
Test status
Simulation time 1649355014 ps
CPU time 1.79 seconds
Started Jul 01 06:38:40 PM PDT 24
Finished Jul 01 06:38:42 PM PDT 24
Peak memory 199148 kb
Host smart-57b3fa53-73b5-4649-b09e-e0101adf5b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101575097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3101575097
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2068271976
Short name T893
Test name
Test status
Simulation time 41012947918 ps
CPU time 42.61 seconds
Started Jul 01 06:38:38 PM PDT 24
Finished Jul 01 06:39:22 PM PDT 24
Peak memory 200108 kb
Host smart-4c8470e9-9b96-483d-b792-0cb32f8898e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068271976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2068271976
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1839834519
Short name T666
Test name
Test status
Simulation time 36251302 ps
CPU time 0.54 seconds
Started Jul 01 06:38:54 PM PDT 24
Finished Jul 01 06:38:56 PM PDT 24
Peak memory 195652 kb
Host smart-fb1cc00e-0cb0-456d-a877-ba8d909d120d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839834519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1839834519
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2234080042
Short name T792
Test name
Test status
Simulation time 37515595678 ps
CPU time 19.07 seconds
Started Jul 01 06:38:40 PM PDT 24
Finished Jul 01 06:39:00 PM PDT 24
Peak memory 199948 kb
Host smart-a13a7c27-9641-495f-bcb5-dd72900a67ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234080042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2234080042
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.459803711
Short name T759
Test name
Test status
Simulation time 47546539291 ps
CPU time 48.44 seconds
Started Jul 01 06:38:42 PM PDT 24
Finished Jul 01 06:39:32 PM PDT 24
Peak memory 200028 kb
Host smart-8be141bd-e4d1-47ba-afd1-d1b1e00ebfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459803711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.459803711
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.312117149
Short name T605
Test name
Test status
Simulation time 33396137794 ps
CPU time 19.39 seconds
Started Jul 01 06:38:39 PM PDT 24
Finished Jul 01 06:39:00 PM PDT 24
Peak memory 199820 kb
Host smart-662f7291-e542-4d47-912a-d681416fc26c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312117149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.312117149
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.654633814
Short name T474
Test name
Test status
Simulation time 74686823658 ps
CPU time 455.53 seconds
Started Jul 01 06:38:53 PM PDT 24
Finished Jul 01 06:46:30 PM PDT 24
Peak memory 200020 kb
Host smart-0d0aac80-2405-4565-898f-b8fcd0e21f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654633814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.654633814
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3218245830
Short name T1013
Test name
Test status
Simulation time 11362010446 ps
CPU time 6.13 seconds
Started Jul 01 06:38:55 PM PDT 24
Finished Jul 01 06:39:03 PM PDT 24
Peak memory 198932 kb
Host smart-820406d0-8c2c-4637-9fee-d8f1bb886aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218245830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3218245830
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.1933655043
Short name T407
Test name
Test status
Simulation time 6734951986 ps
CPU time 397.4 seconds
Started Jul 01 06:38:52 PM PDT 24
Finished Jul 01 06:45:31 PM PDT 24
Peak memory 200008 kb
Host smart-72d5ae3b-1f6b-4645-b183-a399d48c6886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933655043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1933655043
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3097651068
Short name T887
Test name
Test status
Simulation time 7077740761 ps
CPU time 64.56 seconds
Started Jul 01 06:38:42 PM PDT 24
Finished Jul 01 06:39:48 PM PDT 24
Peak memory 198388 kb
Host smart-325bdc4f-070c-4ae2-b0c0-ca469f71dc3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097651068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3097651068
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.958307039
Short name T936
Test name
Test status
Simulation time 10647829801 ps
CPU time 18.48 seconds
Started Jul 01 06:38:54 PM PDT 24
Finished Jul 01 06:39:14 PM PDT 24
Peak memory 199940 kb
Host smart-9f64c032-ceaa-47c5-a769-6365ebf8dff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958307039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.958307039
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1168512311
Short name T701
Test name
Test status
Simulation time 1586915226 ps
CPU time 1.15 seconds
Started Jul 01 06:38:52 PM PDT 24
Finished Jul 01 06:38:54 PM PDT 24
Peak memory 195420 kb
Host smart-9df6356b-c0b4-48c2-a429-e63d6c9d15f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168512311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1168512311
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.942526710
Short name T886
Test name
Test status
Simulation time 543941293 ps
CPU time 0.98 seconds
Started Jul 01 06:38:42 PM PDT 24
Finished Jul 01 06:38:44 PM PDT 24
Peak memory 198336 kb
Host smart-9176dcea-8cda-40da-8725-762f73ad24b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942526710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.942526710
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1163168970
Short name T466
Test name
Test status
Simulation time 249648895859 ps
CPU time 888.62 seconds
Started Jul 01 06:38:53 PM PDT 24
Finished Jul 01 06:53:43 PM PDT 24
Peak memory 199848 kb
Host smart-bae477e5-e3bb-47fd-baea-d54977677c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163168970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1163168970
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2946045334
Short name T908
Test name
Test status
Simulation time 62972106245 ps
CPU time 423.05 seconds
Started Jul 01 06:38:52 PM PDT 24
Finished Jul 01 06:45:56 PM PDT 24
Peak memory 216568 kb
Host smart-8c7c3fc0-4ef2-4220-8480-05f6095be0d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946045334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2946045334
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2474655315
Short name T302
Test name
Test status
Simulation time 521440709 ps
CPU time 1.43 seconds
Started Jul 01 06:38:52 PM PDT 24
Finished Jul 01 06:38:55 PM PDT 24
Peak memory 198384 kb
Host smart-26be5fff-6332-40c8-b9f6-7d93dc829c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474655315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2474655315
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.838560265
Short name T609
Test name
Test status
Simulation time 37041229950 ps
CPU time 66.6 seconds
Started Jul 01 06:38:42 PM PDT 24
Finished Jul 01 06:39:50 PM PDT 24
Peak memory 199948 kb
Host smart-b8976a8e-ccf4-4c9b-9f81-5e7fb0ff6c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838560265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.838560265
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1749911890
Short name T617
Test name
Test status
Simulation time 11563466 ps
CPU time 0.55 seconds
Started Jul 01 06:38:55 PM PDT 24
Finished Jul 01 06:38:57 PM PDT 24
Peak memory 195316 kb
Host smart-254d5934-411d-4868-83f9-acecbb9ee2ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749911890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1749911890
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2563637401
Short name T687
Test name
Test status
Simulation time 37476161497 ps
CPU time 30.94 seconds
Started Jul 01 06:38:54 PM PDT 24
Finished Jul 01 06:39:26 PM PDT 24
Peak memory 199812 kb
Host smart-c6d3f697-88fc-4380-835c-d872f6f06ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563637401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2563637401
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2073942247
Short name T998
Test name
Test status
Simulation time 24033966575 ps
CPU time 14.06 seconds
Started Jul 01 06:38:53 PM PDT 24
Finished Jul 01 06:39:08 PM PDT 24
Peak memory 200092 kb
Host smart-386657e1-2868-466a-b33c-5cfb03daba20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073942247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2073942247
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2152269391
Short name T408
Test name
Test status
Simulation time 135633155282 ps
CPU time 168.1 seconds
Started Jul 01 06:38:53 PM PDT 24
Finished Jul 01 06:41:43 PM PDT 24
Peak memory 200036 kb
Host smart-7f32c70a-0ad3-417c-a5c2-e302a56cc708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152269391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2152269391
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.523805681
Short name T561
Test name
Test status
Simulation time 46418263574 ps
CPU time 68.11 seconds
Started Jul 01 06:39:03 PM PDT 24
Finished Jul 01 06:40:13 PM PDT 24
Peak memory 198972 kb
Host smart-d40eeb88-aef0-4d11-b274-3610c316fa00
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523805681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.523805681
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.242058576
Short name T948
Test name
Test status
Simulation time 93322397806 ps
CPU time 271.8 seconds
Started Jul 01 06:38:57 PM PDT 24
Finished Jul 01 06:43:30 PM PDT 24
Peak memory 199844 kb
Host smart-dfd13f50-c4b9-4c6d-96eb-729f929900d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=242058576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.242058576
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.252520080
Short name T1058
Test name
Test status
Simulation time 8446519285 ps
CPU time 17.64 seconds
Started Jul 01 06:38:57 PM PDT 24
Finished Jul 01 06:39:15 PM PDT 24
Peak memory 199800 kb
Host smart-3af0951e-ebe8-4068-85e9-37cab990cd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252520080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.252520080
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3306041288
Short name T301
Test name
Test status
Simulation time 16604593124 ps
CPU time 24.99 seconds
Started Jul 01 06:38:58 PM PDT 24
Finished Jul 01 06:39:24 PM PDT 24
Peak memory 198088 kb
Host smart-0df3da61-e4d3-4f6a-aa60-cc055b229ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306041288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3306041288
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3707331149
Short name T455
Test name
Test status
Simulation time 18290386749 ps
CPU time 254.66 seconds
Started Jul 01 06:39:04 PM PDT 24
Finished Jul 01 06:43:20 PM PDT 24
Peak memory 199940 kb
Host smart-dd8427c4-21ee-48ef-9ca7-b8f7ec4e87e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3707331149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3707331149
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3317451091
Short name T490
Test name
Test status
Simulation time 2629761417 ps
CPU time 4.98 seconds
Started Jul 01 06:38:52 PM PDT 24
Finished Jul 01 06:38:59 PM PDT 24
Peak memory 198048 kb
Host smart-f207bfb7-7c2e-46e2-ad11-fa34dd3a3621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3317451091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3317451091
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2937407486
Short name T917
Test name
Test status
Simulation time 15157666592 ps
CPU time 11.1 seconds
Started Jul 01 06:38:55 PM PDT 24
Finished Jul 01 06:39:08 PM PDT 24
Peak memory 199912 kb
Host smart-5b9b5ae4-cf55-4b5e-8f3d-e5a8f6af46e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937407486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2937407486
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.4233634266
Short name T538
Test name
Test status
Simulation time 2070242675 ps
CPU time 1.42 seconds
Started Jul 01 06:38:55 PM PDT 24
Finished Jul 01 06:38:58 PM PDT 24
Peak memory 195404 kb
Host smart-6c2b4a4c-dd1d-40e6-9d52-c486f9786ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233634266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.4233634266
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3530487876
Short name T646
Test name
Test status
Simulation time 89277448 ps
CPU time 0.94 seconds
Started Jul 01 06:38:52 PM PDT 24
Finished Jul 01 06:38:54 PM PDT 24
Peak memory 198152 kb
Host smart-6ae8cef8-89c6-4326-9162-0d594fadb3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530487876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3530487876
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2154621808
Short name T121
Test name
Test status
Simulation time 5577439644 ps
CPU time 35.88 seconds
Started Jul 01 06:39:03 PM PDT 24
Finished Jul 01 06:39:40 PM PDT 24
Peak memory 216136 kb
Host smart-034cc855-ec45-4fec-ad2d-094688168387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154621808 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2154621808
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1742355034
Short name T77
Test name
Test status
Simulation time 895793917 ps
CPU time 1.35 seconds
Started Jul 01 06:38:54 PM PDT 24
Finished Jul 01 06:38:57 PM PDT 24
Peak memory 197180 kb
Host smart-2d388a95-72d9-488f-9f91-54a1e14c6358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742355034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1742355034
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3708552522
Short name T845
Test name
Test status
Simulation time 19766608345 ps
CPU time 15.75 seconds
Started Jul 01 06:38:52 PM PDT 24
Finished Jul 01 06:39:09 PM PDT 24
Peak memory 199684 kb
Host smart-9610bc05-2555-4d08-b183-9a0d86e1236a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708552522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3708552522
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1491472289
Short name T949
Test name
Test status
Simulation time 34368423 ps
CPU time 0.56 seconds
Started Jul 01 06:39:04 PM PDT 24
Finished Jul 01 06:39:07 PM PDT 24
Peak memory 195312 kb
Host smart-ca8c7a48-ce6c-4b63-a96f-7d72399e72dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491472289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1491472289
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.821098446
Short name T635
Test name
Test status
Simulation time 27130491996 ps
CPU time 54.15 seconds
Started Jul 01 06:38:57 PM PDT 24
Finished Jul 01 06:39:52 PM PDT 24
Peak memory 200012 kb
Host smart-8fcb84df-21bb-4137-afbc-e491a919b087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821098446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.821098446
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1490564210
Short name T497
Test name
Test status
Simulation time 33732731499 ps
CPU time 54.13 seconds
Started Jul 01 06:38:54 PM PDT 24
Finished Jul 01 06:39:50 PM PDT 24
Peak memory 199976 kb
Host smart-bcc486d7-7686-46d7-bd5a-255aaff9a8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490564210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1490564210
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1031684255
Short name T216
Test name
Test status
Simulation time 73376758211 ps
CPU time 16.23 seconds
Started Jul 01 06:39:08 PM PDT 24
Finished Jul 01 06:39:26 PM PDT 24
Peak memory 199936 kb
Host smart-b0be4f6a-9b67-44fd-8b91-50a33e22551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031684255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1031684255
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.4215512471
Short name T345
Test name
Test status
Simulation time 26269534596 ps
CPU time 24.03 seconds
Started Jul 01 06:39:06 PM PDT 24
Finished Jul 01 06:39:32 PM PDT 24
Peak memory 199924 kb
Host smart-80a98cbd-81ca-4866-98b8-908482524678
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215512471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4215512471
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1061997645
Short name T252
Test name
Test status
Simulation time 61467170569 ps
CPU time 399.59 seconds
Started Jul 01 06:39:04 PM PDT 24
Finished Jul 01 06:45:45 PM PDT 24
Peak memory 199968 kb
Host smart-dbc59dab-059f-4067-95d7-c8df38472984
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1061997645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1061997645
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.494680765
Short name T542
Test name
Test status
Simulation time 4256428418 ps
CPU time 4.75 seconds
Started Jul 01 06:39:04 PM PDT 24
Finished Jul 01 06:39:10 PM PDT 24
Peak memory 196384 kb
Host smart-4aa755a6-b09f-4834-ba10-fd85faac7a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494680765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.494680765
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.2077348027
Short name T728
Test name
Test status
Simulation time 21011978898 ps
CPU time 1168.85 seconds
Started Jul 01 06:39:04 PM PDT 24
Finished Jul 01 06:58:35 PM PDT 24
Peak memory 200052 kb
Host smart-0a3893b5-c9cd-4602-8803-47d95fff186e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077348027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2077348027
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.746240305
Short name T82
Test name
Test status
Simulation time 7451351983 ps
CPU time 55.53 seconds
Started Jul 01 06:39:03 PM PDT 24
Finished Jul 01 06:40:00 PM PDT 24
Peak memory 198168 kb
Host smart-b3f25ce4-95ac-4269-98e5-a415b985aa46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746240305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.746240305
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1176793927
Short name T126
Test name
Test status
Simulation time 83789064705 ps
CPU time 45.08 seconds
Started Jul 01 06:39:03 PM PDT 24
Finished Jul 01 06:39:50 PM PDT 24
Peak memory 199992 kb
Host smart-5bafae05-6912-45e3-830c-fe9099143678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176793927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1176793927
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.769649243
Short name T796
Test name
Test status
Simulation time 48598631476 ps
CPU time 73.9 seconds
Started Jul 01 06:39:07 PM PDT 24
Finished Jul 01 06:40:22 PM PDT 24
Peak memory 196716 kb
Host smart-7d70685a-99e4-4164-ac55-6f49e6f2d517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769649243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.769649243
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3815959742
Short name T906
Test name
Test status
Simulation time 469034213 ps
CPU time 1.49 seconds
Started Jul 01 06:39:04 PM PDT 24
Finished Jul 01 06:39:08 PM PDT 24
Peak memory 198736 kb
Host smart-0d4f77af-2d67-418f-87fa-566c3879183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815959742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3815959742
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3704092741
Short name T828
Test name
Test status
Simulation time 166828368225 ps
CPU time 403.86 seconds
Started Jul 01 06:39:05 PM PDT 24
Finished Jul 01 06:45:51 PM PDT 24
Peak memory 199880 kb
Host smart-789006a7-6ed0-4ef7-891e-d2522a970260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704092741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3704092741
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.4253336983
Short name T801
Test name
Test status
Simulation time 29776792925 ps
CPU time 222.41 seconds
Started Jul 01 06:39:04 PM PDT 24
Finished Jul 01 06:42:49 PM PDT 24
Peak memory 216564 kb
Host smart-4a96dc7d-2ab4-42b1-a047-69c1a393ef26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253336983 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.4253336983
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1709813843
Short name T992
Test name
Test status
Simulation time 1200582094 ps
CPU time 1.79 seconds
Started Jul 01 06:39:03 PM PDT 24
Finished Jul 01 06:39:07 PM PDT 24
Peak memory 198756 kb
Host smart-bd583740-a9e8-4446-b6af-e022f83a78ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709813843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1709813843
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3937673270
Short name T42
Test name
Test status
Simulation time 43466950003 ps
CPU time 33.69 seconds
Started Jul 01 06:39:03 PM PDT 24
Finished Jul 01 06:39:39 PM PDT 24
Peak memory 199988 kb
Host smart-3026f754-8fcf-4f0b-b2bd-17ac438fa4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937673270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3937673270
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3716795509
Short name T1005
Test name
Test status
Simulation time 13776723 ps
CPU time 0.58 seconds
Started Jul 01 06:39:15 PM PDT 24
Finished Jul 01 06:39:17 PM PDT 24
Peak memory 195312 kb
Host smart-8c41fea8-854d-4da8-a917-1de08250db82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716795509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3716795509
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2190852249
Short name T163
Test name
Test status
Simulation time 52929932605 ps
CPU time 22.45 seconds
Started Jul 01 06:39:03 PM PDT 24
Finished Jul 01 06:39:27 PM PDT 24
Peak memory 199936 kb
Host smart-f10c80aa-250c-4020-9f1c-f7202c4867c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190852249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2190852249
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.27425623
Short name T995
Test name
Test status
Simulation time 45740325518 ps
CPU time 63.86 seconds
Started Jul 01 06:39:04 PM PDT 24
Finished Jul 01 06:40:09 PM PDT 24
Peak memory 199976 kb
Host smart-f1f6f108-5f7d-43ef-8b91-0981b166776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27425623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.27425623
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.696854364
Short name T220
Test name
Test status
Simulation time 89800951994 ps
CPU time 36.85 seconds
Started Jul 01 06:39:04 PM PDT 24
Finished Jul 01 06:39:43 PM PDT 24
Peak memory 199952 kb
Host smart-a46d2dad-3512-4f98-88c0-a8ece7e05631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696854364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.696854364
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.707546113
Short name T134
Test name
Test status
Simulation time 49210056600 ps
CPU time 22.68 seconds
Started Jul 01 06:39:16 PM PDT 24
Finished Jul 01 06:39:40 PM PDT 24
Peak memory 199408 kb
Host smart-89f9a7ba-c4f5-4fb2-b958-475a10f7c7e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707546113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.707546113
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1828780968
Short name T263
Test name
Test status
Simulation time 72528543182 ps
CPU time 600.06 seconds
Started Jul 01 06:39:17 PM PDT 24
Finished Jul 01 06:49:18 PM PDT 24
Peak memory 199992 kb
Host smart-631ddde2-2890-43b3-b615-baaacc2a3d7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828780968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1828780968
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1957392050
Short name T763
Test name
Test status
Simulation time 4502540482 ps
CPU time 7.8 seconds
Started Jul 01 06:39:15 PM PDT 24
Finished Jul 01 06:39:24 PM PDT 24
Peak memory 199816 kb
Host smart-8efd48ce-d94e-41d5-a233-b03806f8a472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957392050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1957392050
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.499576990
Short name T528
Test name
Test status
Simulation time 8860586644 ps
CPU time 539.01 seconds
Started Jul 01 06:39:13 PM PDT 24
Finished Jul 01 06:48:14 PM PDT 24
Peak memory 200020 kb
Host smart-a4520369-93df-4839-a89d-38087d29230c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499576990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.499576990
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1305442416
Short name T702
Test name
Test status
Simulation time 1598585530 ps
CPU time 1.76 seconds
Started Jul 01 06:39:08 PM PDT 24
Finished Jul 01 06:39:11 PM PDT 24
Peak memory 196816 kb
Host smart-7cdc7fa9-7fe2-4ba0-a108-ad586bf5639b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305442416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1305442416
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3229739442
Short name T957
Test name
Test status
Simulation time 95627560466 ps
CPU time 58.29 seconds
Started Jul 01 06:39:16 PM PDT 24
Finished Jul 01 06:40:16 PM PDT 24
Peak memory 199880 kb
Host smart-42ad6918-9a90-4aee-b047-efa4661b84e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229739442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3229739442
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1208236389
Short name T640
Test name
Test status
Simulation time 43642649038 ps
CPU time 30.59 seconds
Started Jul 01 06:39:13 PM PDT 24
Finished Jul 01 06:39:45 PM PDT 24
Peak memory 195852 kb
Host smart-19a1bc33-7f6a-4545-b9a0-2be64fb712fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208236389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1208236389
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3263885728
Short name T269
Test name
Test status
Simulation time 5298457208 ps
CPU time 10.94 seconds
Started Jul 01 06:39:04 PM PDT 24
Finished Jul 01 06:39:17 PM PDT 24
Peak memory 199388 kb
Host smart-7bf8dc3b-ecbd-48d4-a9e9-31a087372e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263885728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3263885728
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2900618318
Short name T123
Test name
Test status
Simulation time 80090883003 ps
CPU time 483.85 seconds
Started Jul 01 06:39:13 PM PDT 24
Finished Jul 01 06:47:18 PM PDT 24
Peak memory 216444 kb
Host smart-86dbd62c-458a-4383-96d9-6e7034571eba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900618318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2900618318
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2850747357
Short name T901
Test name
Test status
Simulation time 7419216087 ps
CPU time 9 seconds
Started Jul 01 06:39:13 PM PDT 24
Finished Jul 01 06:39:23 PM PDT 24
Peak memory 199848 kb
Host smart-e38d4143-e78e-4d18-8552-d02871933f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850747357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2850747357
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3049780525
Short name T834
Test name
Test status
Simulation time 23394012166 ps
CPU time 10.89 seconds
Started Jul 01 06:39:05 PM PDT 24
Finished Jul 01 06:39:17 PM PDT 24
Peak memory 200140 kb
Host smart-b63dd9fc-9ed1-431c-8140-e95a56a64ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049780525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3049780525
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1003886392
Short name T817
Test name
Test status
Simulation time 154319337 ps
CPU time 0.55 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:39:37 PM PDT 24
Peak memory 195200 kb
Host smart-3fe1a253-33ee-40eb-8d7c-871301f2880c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003886392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1003886392
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.428867758
Short name T613
Test name
Test status
Simulation time 102389576014 ps
CPU time 143.49 seconds
Started Jul 01 06:39:13 PM PDT 24
Finished Jul 01 06:41:38 PM PDT 24
Peak memory 200020 kb
Host smart-be536ec7-62f3-43dd-aa5a-dbcff4f2b8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428867758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.428867758
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2691664449
Short name T424
Test name
Test status
Simulation time 102856004553 ps
CPU time 234.26 seconds
Started Jul 01 06:39:27 PM PDT 24
Finished Jul 01 06:43:22 PM PDT 24
Peak memory 199808 kb
Host smart-fbe4b037-ab50-411e-af75-aca5bf2680c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691664449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2691664449
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2746615435
Short name T747
Test name
Test status
Simulation time 46934422144 ps
CPU time 74.41 seconds
Started Jul 01 06:39:19 PM PDT 24
Finished Jul 01 06:40:34 PM PDT 24
Peak memory 199992 kb
Host smart-45e8f3b9-1502-4e95-a65c-72d988ddd141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746615435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2746615435
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1028080112
Short name T1072
Test name
Test status
Simulation time 37354172074 ps
CPU time 58.25 seconds
Started Jul 01 06:39:28 PM PDT 24
Finished Jul 01 06:40:27 PM PDT 24
Peak memory 199992 kb
Host smart-a5792996-699f-4d33-91da-f0d4e5ad5df7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028080112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1028080112
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2326396457
Short name T526
Test name
Test status
Simulation time 132768221801 ps
CPU time 1363.71 seconds
Started Jul 01 06:39:28 PM PDT 24
Finished Jul 01 07:02:13 PM PDT 24
Peak memory 199892 kb
Host smart-4e5d7b06-50cd-485f-a69e-1fad42749c13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2326396457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2326396457
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2331556497
Short name T354
Test name
Test status
Simulation time 8773041066 ps
CPU time 9.35 seconds
Started Jul 01 06:39:27 PM PDT 24
Finished Jul 01 06:39:38 PM PDT 24
Peak memory 199448 kb
Host smart-c3efcec5-265f-463a-ac75-7e993cba24c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331556497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2331556497
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.2545236342
Short name T485
Test name
Test status
Simulation time 9149286790 ps
CPU time 498.62 seconds
Started Jul 01 06:39:30 PM PDT 24
Finished Jul 01 06:47:49 PM PDT 24
Peak memory 199948 kb
Host smart-1ee8a490-59a3-4ac3-b1fe-5dfa7bb01d8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545236342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2545236342
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1188214553
Short name T793
Test name
Test status
Simulation time 6316185331 ps
CPU time 14.74 seconds
Started Jul 01 06:39:27 PM PDT 24
Finished Jul 01 06:39:43 PM PDT 24
Peak memory 199004 kb
Host smart-453a30a5-5a06-46c6-8e70-98463bd20ba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188214553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1188214553
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3122207064
Short name T283
Test name
Test status
Simulation time 30867733635 ps
CPU time 27.05 seconds
Started Jul 01 06:39:29 PM PDT 24
Finished Jul 01 06:39:57 PM PDT 24
Peak memory 200080 kb
Host smart-c136bbf0-b57a-4872-94b6-8ae7a745cf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122207064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3122207064
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.4193795782
Short name T286
Test name
Test status
Simulation time 5020124457 ps
CPU time 1.81 seconds
Started Jul 01 06:39:27 PM PDT 24
Finished Jul 01 06:39:30 PM PDT 24
Peak memory 196232 kb
Host smart-6a414531-19f7-456e-aef0-47e2510b95b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193795782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.4193795782
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2447559637
Short name T298
Test name
Test status
Simulation time 97067612 ps
CPU time 0.89 seconds
Started Jul 01 06:39:15 PM PDT 24
Finished Jul 01 06:39:17 PM PDT 24
Peak memory 198364 kb
Host smart-0fba0f61-f8cf-4224-b3e5-f2140c650106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447559637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2447559637
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.106913430
Short name T798
Test name
Test status
Simulation time 368786760723 ps
CPU time 204.84 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:43:01 PM PDT 24
Peak memory 199948 kb
Host smart-1ef9383a-7f01-472d-afbc-61eebae7d465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106913430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.106913430
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1073248891
Short name T685
Test name
Test status
Simulation time 65338512987 ps
CPU time 297.91 seconds
Started Jul 01 06:39:29 PM PDT 24
Finished Jul 01 06:44:28 PM PDT 24
Peak memory 216444 kb
Host smart-a167a6f2-d237-4539-b69f-0254c0c56197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073248891 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1073248891
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1600309861
Short name T975
Test name
Test status
Simulation time 7356004247 ps
CPU time 10.78 seconds
Started Jul 01 06:39:27 PM PDT 24
Finished Jul 01 06:39:39 PM PDT 24
Peak memory 199960 kb
Host smart-c43a8c5f-c790-4753-92b7-5142c220827d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600309861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1600309861
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2483502150
Short name T545
Test name
Test status
Simulation time 46228325308 ps
CPU time 19.52 seconds
Started Jul 01 06:39:14 PM PDT 24
Finished Jul 01 06:39:35 PM PDT 24
Peak memory 200072 kb
Host smart-e238992e-b83b-480e-86ec-cf2de011b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483502150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2483502150
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3263517220
Short name T449
Test name
Test status
Simulation time 36804818 ps
CPU time 0.57 seconds
Started Jul 01 06:35:01 PM PDT 24
Finished Jul 01 06:35:05 PM PDT 24
Peak memory 195320 kb
Host smart-eed1093a-3396-45e8-84c7-5caff325bb00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263517220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3263517220
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.131472652
Short name T506
Test name
Test status
Simulation time 19375383497 ps
CPU time 33.07 seconds
Started Jul 01 06:34:59 PM PDT 24
Finished Jul 01 06:35:35 PM PDT 24
Peak memory 199924 kb
Host smart-ba099393-c6d9-4574-a402-1ec9760438f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131472652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.131472652
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1510747971
Short name T1029
Test name
Test status
Simulation time 242412884547 ps
CPU time 57.14 seconds
Started Jul 01 06:34:54 PM PDT 24
Finished Jul 01 06:35:53 PM PDT 24
Peak memory 199956 kb
Host smart-3f246f05-6eff-4949-8411-36b50c767e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510747971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1510747971
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1845251543
Short name T694
Test name
Test status
Simulation time 61310237974 ps
CPU time 32.44 seconds
Started Jul 01 06:34:54 PM PDT 24
Finished Jul 01 06:35:28 PM PDT 24
Peak memory 199952 kb
Host smart-b808c05c-efa4-4dcf-926a-336ab7c3ad67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845251543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1845251543
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2506973406
Short name T415
Test name
Test status
Simulation time 35112560595 ps
CPU time 54.14 seconds
Started Jul 01 06:34:52 PM PDT 24
Finished Jul 01 06:35:49 PM PDT 24
Peak memory 199888 kb
Host smart-f72f805a-ace3-47d3-89db-30d852bbd28e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506973406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2506973406
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1781968021
Short name T570
Test name
Test status
Simulation time 99922428549 ps
CPU time 528.76 seconds
Started Jul 01 06:34:53 PM PDT 24
Finished Jul 01 06:43:44 PM PDT 24
Peak memory 199996 kb
Host smart-41de13ed-e316-4b90-bea6-e68150b1b178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781968021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1781968021
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3008803107
Short name T626
Test name
Test status
Simulation time 10155487232 ps
CPU time 24.95 seconds
Started Jul 01 06:34:52 PM PDT 24
Finished Jul 01 06:35:19 PM PDT 24
Peak memory 199780 kb
Host smart-e85e92b6-1012-471f-95e4-7fd8db00190a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008803107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3008803107
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.720045636
Short name T544
Test name
Test status
Simulation time 140827495372 ps
CPU time 51.94 seconds
Started Jul 01 06:34:57 PM PDT 24
Finished Jul 01 06:35:50 PM PDT 24
Peak memory 200020 kb
Host smart-e7d991aa-38cb-4ffc-bd70-6b584614be4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720045636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.720045636
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.378621760
Short name T65
Test name
Test status
Simulation time 15462861829 ps
CPU time 323.5 seconds
Started Jul 01 06:34:53 PM PDT 24
Finished Jul 01 06:40:19 PM PDT 24
Peak memory 200056 kb
Host smart-d344e20d-1aeb-48cb-b064-02568c44e64a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378621760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.378621760
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2706603718
Short name T872
Test name
Test status
Simulation time 4298046947 ps
CPU time 6.16 seconds
Started Jul 01 06:34:54 PM PDT 24
Finished Jul 01 06:35:02 PM PDT 24
Peak memory 199448 kb
Host smart-df066331-7c62-42b4-9f5e-29cd679f04c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706603718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2706603718
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.4069420722
Short name T776
Test name
Test status
Simulation time 142677354734 ps
CPU time 212.99 seconds
Started Jul 01 06:34:55 PM PDT 24
Finished Jul 01 06:38:30 PM PDT 24
Peak memory 199996 kb
Host smart-3c228c1e-291d-4f6a-90e4-4d34b2e9f52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069420722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.4069420722
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2820240305
Short name T273
Test name
Test status
Simulation time 39898555425 ps
CPU time 54.31 seconds
Started Jul 01 06:34:54 PM PDT 24
Finished Jul 01 06:35:50 PM PDT 24
Peak memory 196100 kb
Host smart-b091b136-5ff3-47d0-8f07-88830789b5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820240305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2820240305
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3427602743
Short name T22
Test name
Test status
Simulation time 254045172 ps
CPU time 0.75 seconds
Started Jul 01 06:35:01 PM PDT 24
Finished Jul 01 06:35:05 PM PDT 24
Peak memory 218408 kb
Host smart-ce1331ac-aa1c-48d3-a1e6-2de41b8acff9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427602743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3427602743
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2619219906
Short name T555
Test name
Test status
Simulation time 662321828 ps
CPU time 1.69 seconds
Started Jul 01 06:34:53 PM PDT 24
Finished Jul 01 06:34:57 PM PDT 24
Peak memory 199628 kb
Host smart-b52fb020-0b54-4b31-b036-3723ae3862c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619219906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2619219906
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3811560471
Short name T489
Test name
Test status
Simulation time 23321750995 ps
CPU time 258.5 seconds
Started Jul 01 06:34:59 PM PDT 24
Finished Jul 01 06:39:21 PM PDT 24
Peak memory 199952 kb
Host smart-190a9b3f-934b-48da-a22f-3301e98c179e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811560471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3811560471
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3295923859
Short name T961
Test name
Test status
Simulation time 20976096486 ps
CPU time 135.44 seconds
Started Jul 01 06:34:55 PM PDT 24
Finished Jul 01 06:37:12 PM PDT 24
Peak memory 216556 kb
Host smart-353e89bf-b400-4476-acc0-ee638b0bf00b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295923859 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3295923859
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3800744219
Short name T358
Test name
Test status
Simulation time 630296831 ps
CPU time 2.21 seconds
Started Jul 01 06:34:52 PM PDT 24
Finished Jul 01 06:34:57 PM PDT 24
Peak memory 198396 kb
Host smart-cf67389c-5c68-4138-bf58-896528a4b2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800744219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3800744219
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3012602117
Short name T549
Test name
Test status
Simulation time 49341552827 ps
CPU time 74.7 seconds
Started Jul 01 06:34:55 PM PDT 24
Finished Jul 01 06:36:12 PM PDT 24
Peak memory 200052 kb
Host smart-40dee955-2c0d-45c9-a507-8be9804bbbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012602117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3012602117
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3873028477
Short name T118
Test name
Test status
Simulation time 11963160 ps
CPU time 0.54 seconds
Started Jul 01 06:39:33 PM PDT 24
Finished Jul 01 06:39:34 PM PDT 24
Peak memory 194300 kb
Host smart-3901202c-479b-43a5-a48b-6c7b84ee6259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873028477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3873028477
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1468813891
Short name T45
Test name
Test status
Simulation time 42066020913 ps
CPU time 28.28 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:40:05 PM PDT 24
Peak memory 199960 kb
Host smart-d93c37d2-e5c3-4994-86cf-68a8566c8be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468813891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1468813891
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1151545664
Short name T2
Test name
Test status
Simulation time 35286469199 ps
CPU time 11.69 seconds
Started Jul 01 06:39:34 PM PDT 24
Finished Jul 01 06:39:47 PM PDT 24
Peak memory 197924 kb
Host smart-5e6188f8-bf42-4109-8e8b-5b3906848517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151545664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1151545664
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.64773111
Short name T1002
Test name
Test status
Simulation time 170542492290 ps
CPU time 72.4 seconds
Started Jul 01 06:39:34 PM PDT 24
Finished Jul 01 06:40:48 PM PDT 24
Peak memory 199904 kb
Host smart-5a6fbf92-1b6a-4b38-b599-9412545641b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64773111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.64773111
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.641252307
Short name T804
Test name
Test status
Simulation time 70461133567 ps
CPU time 542.38 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:48:39 PM PDT 24
Peak memory 200032 kb
Host smart-023a151c-4c91-4f91-a64c-f207ef97319c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641252307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.641252307
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.830036134
Short name T386
Test name
Test status
Simulation time 2954582724 ps
CPU time 4.99 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:39:41 PM PDT 24
Peak memory 195852 kb
Host smart-46490708-3d32-4d80-a04a-8c2d2c89e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830036134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.830036134
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.692662323
Short name T863
Test name
Test status
Simulation time 22827734922 ps
CPU time 1155.83 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:58:52 PM PDT 24
Peak memory 199988 kb
Host smart-50bca368-bebe-4cf6-9a4e-7c9c8680b6af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692662323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.692662323
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.814703780
Short name T954
Test name
Test status
Simulation time 1584595464 ps
CPU time 5.86 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:39:43 PM PDT 24
Peak memory 197552 kb
Host smart-13359d37-b471-432d-9de0-4f7380632be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814703780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.814703780
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1668757700
Short name T655
Test name
Test status
Simulation time 57914996655 ps
CPU time 44.73 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:40:21 PM PDT 24
Peak memory 199824 kb
Host smart-28c4f696-611f-4fa5-815a-dc43cb779e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668757700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1668757700
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1695059209
Short name T716
Test name
Test status
Simulation time 5170142203 ps
CPU time 2.73 seconds
Started Jul 01 06:39:36 PM PDT 24
Finished Jul 01 06:39:40 PM PDT 24
Peak memory 196428 kb
Host smart-0ccbdf56-4e73-4949-b7c4-893ba6fa8887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695059209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1695059209
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.784094383
Short name T370
Test name
Test status
Simulation time 431830407 ps
CPU time 1.14 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:39:38 PM PDT 24
Peak memory 197608 kb
Host smart-1cf7c69f-80cb-4c71-8585-85b44f1890ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784094383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.784094383
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2721518202
Short name T484
Test name
Test status
Simulation time 43475043884 ps
CPU time 527.7 seconds
Started Jul 01 06:39:34 PM PDT 24
Finished Jul 01 06:48:23 PM PDT 24
Peak memory 216096 kb
Host smart-7e701e84-b610-4594-bef4-164c3e023ce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721518202 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2721518202
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.850239078
Short name T83
Test name
Test status
Simulation time 1212236983 ps
CPU time 1.39 seconds
Started Jul 01 06:39:34 PM PDT 24
Finished Jul 01 06:39:36 PM PDT 24
Peak memory 198544 kb
Host smart-8290a7ac-4d25-4515-a80f-2c5fd640bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850239078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.850239078
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3581493200
Short name T279
Test name
Test status
Simulation time 78488108908 ps
CPU time 108.76 seconds
Started Jul 01 06:39:40 PM PDT 24
Finished Jul 01 06:41:30 PM PDT 24
Peak memory 200048 kb
Host smart-c326b6d9-2377-4da1-abfc-c1f359165d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581493200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3581493200
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.824611646
Short name T959
Test name
Test status
Simulation time 68303496 ps
CPU time 0.56 seconds
Started Jul 01 06:39:45 PM PDT 24
Finished Jul 01 06:39:52 PM PDT 24
Peak memory 195596 kb
Host smart-b4818485-dda2-4216-a9e7-a15cf9f4d291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824611646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.824611646
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1796916603
Short name T145
Test name
Test status
Simulation time 38924534550 ps
CPU time 65.19 seconds
Started Jul 01 06:39:34 PM PDT 24
Finished Jul 01 06:40:41 PM PDT 24
Peak memory 200104 kb
Host smart-3bf75927-e982-4a5c-9ea2-4a32bc99f44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796916603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1796916603
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.4179911396
Short name T438
Test name
Test status
Simulation time 23253238642 ps
CPU time 9.21 seconds
Started Jul 01 06:39:40 PM PDT 24
Finished Jul 01 06:39:51 PM PDT 24
Peak memory 200056 kb
Host smart-ee380a66-15fb-47a9-8912-815330dfe119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179911396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.4179911396
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3637505373
Short name T850
Test name
Test status
Simulation time 95125790392 ps
CPU time 41.68 seconds
Started Jul 01 06:39:33 PM PDT 24
Finished Jul 01 06:40:16 PM PDT 24
Peak memory 200076 kb
Host smart-e12be11d-37d6-4adb-be33-50757ea732ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637505373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3637505373
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3172418113
Short name T790
Test name
Test status
Simulation time 130389385037 ps
CPU time 88.53 seconds
Started Jul 01 06:39:33 PM PDT 24
Finished Jul 01 06:41:03 PM PDT 24
Peak memory 200048 kb
Host smart-6c055215-7b5b-4bdd-aba7-4e52602a62fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172418113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3172418113
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4050604823
Short name T64
Test name
Test status
Simulation time 93104621135 ps
CPU time 420.63 seconds
Started Jul 01 06:39:44 PM PDT 24
Finished Jul 01 06:46:52 PM PDT 24
Peak memory 200044 kb
Host smart-64cfe5bd-4748-4afa-961f-afcbd38cf05c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050604823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4050604823
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1310632935
Short name T1022
Test name
Test status
Simulation time 1593386651 ps
CPU time 1.47 seconds
Started Jul 01 06:39:45 PM PDT 24
Finished Jul 01 06:39:55 PM PDT 24
Peak memory 197412 kb
Host smart-fc61a1e0-cb57-4305-8fc6-b639ead4ca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310632935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1310632935
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.1582315860
Short name T779
Test name
Test status
Simulation time 8225661639 ps
CPU time 94.23 seconds
Started Jul 01 06:39:45 PM PDT 24
Finished Jul 01 06:41:27 PM PDT 24
Peak memory 200052 kb
Host smart-cf9f820d-3e35-4bf6-a4bb-a55baddd49dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582315860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1582315860
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3916684050
Short name T18
Test name
Test status
Simulation time 5089903829 ps
CPU time 49.36 seconds
Started Jul 01 06:39:38 PM PDT 24
Finished Jul 01 06:40:28 PM PDT 24
Peak memory 199196 kb
Host smart-8ce5bf4e-f12c-4321-b007-dd7d70668af9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916684050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3916684050
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.873795395
Short name T316
Test name
Test status
Simulation time 26762352002 ps
CPU time 48.62 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:40:25 PM PDT 24
Peak memory 199860 kb
Host smart-cb73475d-93ab-4a58-8340-311f9520df0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873795395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.873795395
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3997375650
Short name T986
Test name
Test status
Simulation time 4427707638 ps
CPU time 7.53 seconds
Started Jul 01 06:39:36 PM PDT 24
Finished Jul 01 06:39:45 PM PDT 24
Peak memory 196236 kb
Host smart-e91bc4c8-b785-4f38-8d86-09480bfcd376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997375650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3997375650
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2771148560
Short name T971
Test name
Test status
Simulation time 271767253 ps
CPU time 1.93 seconds
Started Jul 01 06:39:36 PM PDT 24
Finished Jul 01 06:39:39 PM PDT 24
Peak memory 198944 kb
Host smart-f5bf5589-7bcd-405e-a441-6b827dd0cdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771148560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2771148560
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3032946475
Short name T398
Test name
Test status
Simulation time 1083042267 ps
CPU time 1.24 seconds
Started Jul 01 06:39:45 PM PDT 24
Finished Jul 01 06:39:54 PM PDT 24
Peak memory 197004 kb
Host smart-b738f3ce-56b0-4e99-ba16-2159f9f8be1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032946475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3032946475
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.769523980
Short name T313
Test name
Test status
Simulation time 56110284018 ps
CPU time 61.06 seconds
Started Jul 01 06:39:35 PM PDT 24
Finished Jul 01 06:40:37 PM PDT 24
Peak memory 199992 kb
Host smart-4c4728a5-ce3c-4ee2-b416-e177ae0bacfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769523980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.769523980
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1467543442
Short name T365
Test name
Test status
Simulation time 23795736 ps
CPU time 0.55 seconds
Started Jul 01 06:39:57 PM PDT 24
Finished Jul 01 06:40:02 PM PDT 24
Peak memory 195596 kb
Host smart-7b095e09-1288-4253-b344-91f4fdd41d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467543442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1467543442
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2932169179
Short name T311
Test name
Test status
Simulation time 103034195067 ps
CPU time 20.36 seconds
Started Jul 01 06:39:44 PM PDT 24
Finished Jul 01 06:40:12 PM PDT 24
Peak memory 200056 kb
Host smart-6a6a9c6a-292a-4102-8695-8bd60900845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932169179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2932169179
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3279493892
Short name T447
Test name
Test status
Simulation time 22960721891 ps
CPU time 38.68 seconds
Started Jul 01 06:39:44 PM PDT 24
Finished Jul 01 06:40:30 PM PDT 24
Peak memory 199940 kb
Host smart-25c24acb-9f6f-4acd-a96b-2a60b163a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279493892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3279493892
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.4183537926
Short name T211
Test name
Test status
Simulation time 101927229568 ps
CPU time 36.21 seconds
Started Jul 01 06:39:43 PM PDT 24
Finished Jul 01 06:40:26 PM PDT 24
Peak memory 199996 kb
Host smart-6ab50847-023e-47b4-86a5-3171fadccd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183537926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.4183537926
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.382192292
Short name T826
Test name
Test status
Simulation time 38853854830 ps
CPU time 58.67 seconds
Started Jul 01 06:39:43 PM PDT 24
Finished Jul 01 06:40:49 PM PDT 24
Peak memory 199332 kb
Host smart-8631a259-9ce3-4cfd-b74c-04bd084c0dfd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382192292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.382192292
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1080670042
Short name T690
Test name
Test status
Simulation time 66766267999 ps
CPU time 58.37 seconds
Started Jul 01 06:39:57 PM PDT 24
Finished Jul 01 06:40:59 PM PDT 24
Peak memory 200000 kb
Host smart-82c2c694-062f-4b00-89ae-a26bb3018531
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1080670042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1080670042
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.508190111
Short name T725
Test name
Test status
Simulation time 4438748357 ps
CPU time 7.81 seconds
Started Jul 01 06:39:55 PM PDT 24
Finished Jul 01 06:40:07 PM PDT 24
Peak memory 199008 kb
Host smart-7c00a6ce-8fc7-4e5c-b519-82e9bf18d104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508190111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.508190111
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.3130494915
Short name T567
Test name
Test status
Simulation time 8422725583 ps
CPU time 320 seconds
Started Jul 01 06:39:57 PM PDT 24
Finished Jul 01 06:45:21 PM PDT 24
Peak memory 199980 kb
Host smart-f319be6d-9865-45be-9544-9cc64a70ede4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3130494915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3130494915
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.433607706
Short name T3
Test name
Test status
Simulation time 3267802639 ps
CPU time 27.58 seconds
Started Jul 01 06:39:44 PM PDT 24
Finished Jul 01 06:40:19 PM PDT 24
Peak memory 198032 kb
Host smart-11bc4e9d-19dc-403f-9c94-7abd9b9477d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433607706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.433607706
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1635923509
Short name T723
Test name
Test status
Simulation time 11240154115 ps
CPU time 14.04 seconds
Started Jul 01 06:39:57 PM PDT 24
Finished Jul 01 06:40:15 PM PDT 24
Peak memory 200176 kb
Host smart-e459d201-9ef8-4a44-bd69-9429445eb0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635923509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1635923509
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1395211595
Short name T1071
Test name
Test status
Simulation time 7066642116 ps
CPU time 9.3 seconds
Started Jul 01 06:39:57 PM PDT 24
Finished Jul 01 06:40:10 PM PDT 24
Peak memory 196204 kb
Host smart-fd35ae3e-950f-41df-8c6b-26bf2aa3fe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395211595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1395211595
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3557404881
Short name T322
Test name
Test status
Simulation time 929420880 ps
CPU time 3.95 seconds
Started Jul 01 06:39:44 PM PDT 24
Finished Jul 01 06:39:55 PM PDT 24
Peak memory 199912 kb
Host smart-bd1571cd-bb8f-4722-9170-fa70f0d9c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557404881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3557404881
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2311499905
Short name T894
Test name
Test status
Simulation time 465717046837 ps
CPU time 464.55 seconds
Started Jul 01 06:39:58 PM PDT 24
Finished Jul 01 06:47:48 PM PDT 24
Peak memory 200016 kb
Host smart-f9e585ff-4b91-471e-8e64-e710f75685b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311499905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2311499905
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2976706831
Short name T56
Test name
Test status
Simulation time 66121434461 ps
CPU time 1740.86 seconds
Started Jul 01 06:39:55 PM PDT 24
Finished Jul 01 07:09:00 PM PDT 24
Peak memory 216728 kb
Host smart-bb1c5cc2-8cfb-4f05-8178-a381bc04ccae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976706831 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2976706831
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1967392982
Short name T844
Test name
Test status
Simulation time 817653371 ps
CPU time 4.4 seconds
Started Jul 01 06:39:58 PM PDT 24
Finished Jul 01 06:40:08 PM PDT 24
Peak memory 199520 kb
Host smart-7326724d-331c-41a1-ad2a-141bea47adae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967392982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1967392982
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.576204163
Short name T1079
Test name
Test status
Simulation time 24958267783 ps
CPU time 17.93 seconds
Started Jul 01 06:39:44 PM PDT 24
Finished Jul 01 06:40:09 PM PDT 24
Peak memory 198876 kb
Host smart-66410baa-ec6b-41ca-ad51-0f877a2dc0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576204163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.576204163
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3077405524
Short name T355
Test name
Test status
Simulation time 34608484 ps
CPU time 0.58 seconds
Started Jul 01 06:40:08 PM PDT 24
Finished Jul 01 06:40:16 PM PDT 24
Peak memory 195388 kb
Host smart-24dafb4e-ad28-48d9-b557-8ca3e347ec5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077405524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3077405524
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1449540726
Short name T125
Test name
Test status
Simulation time 186282356498 ps
CPU time 88.25 seconds
Started Jul 01 06:39:57 PM PDT 24
Finished Jul 01 06:41:29 PM PDT 24
Peak memory 199996 kb
Host smart-bf78d12b-3650-4c7e-9f0f-9b6712ae1176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449540726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1449540726
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2593012972
Short name T627
Test name
Test status
Simulation time 98323438976 ps
CPU time 136.97 seconds
Started Jul 01 06:39:57 PM PDT 24
Finished Jul 01 06:42:17 PM PDT 24
Peak memory 199932 kb
Host smart-3a311270-4e26-4634-ba0f-c9a47f8bb129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593012972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2593012972
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3788217267
Short name T1088
Test name
Test status
Simulation time 51998416905 ps
CPU time 88.76 seconds
Started Jul 01 06:39:54 PM PDT 24
Finished Jul 01 06:41:26 PM PDT 24
Peak memory 200008 kb
Host smart-7ce2f2d9-a403-4c08-ba93-4614e8c79b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788217267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3788217267
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2301085049
Short name T576
Test name
Test status
Simulation time 29073397845 ps
CPU time 39.54 seconds
Started Jul 01 06:39:56 PM PDT 24
Finished Jul 01 06:40:40 PM PDT 24
Peak memory 197852 kb
Host smart-500c324b-fb60-4aa2-8b56-fbc18b256778
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301085049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2301085049
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.4107575923
Short name T692
Test name
Test status
Simulation time 93431596519 ps
CPU time 461.91 seconds
Started Jul 01 06:40:08 PM PDT 24
Finished Jul 01 06:47:57 PM PDT 24
Peak memory 199984 kb
Host smart-c3e3b28f-22af-4268-9ce9-712cf560078a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107575923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4107575923
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.276827709
Short name T378
Test name
Test status
Simulation time 8628266205 ps
CPU time 18.56 seconds
Started Jul 01 06:40:11 PM PDT 24
Finished Jul 01 06:40:36 PM PDT 24
Peak memory 199712 kb
Host smart-1134cd81-08a0-4209-95ff-ac0b6f9e32d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276827709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.276827709
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.2168427549
Short name T324
Test name
Test status
Simulation time 21689562890 ps
CPU time 213.25 seconds
Started Jul 01 06:40:09 PM PDT 24
Finished Jul 01 06:43:50 PM PDT 24
Peak memory 199964 kb
Host smart-db2a56c1-c518-4dcb-b6d5-f77ed87b4799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168427549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2168427549
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.607631152
Short name T883
Test name
Test status
Simulation time 1794848286 ps
CPU time 5.98 seconds
Started Jul 01 06:39:56 PM PDT 24
Finished Jul 01 06:40:06 PM PDT 24
Peak memory 198008 kb
Host smart-bb9beed7-b38f-48c7-b80d-9c160a1f09eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607631152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.607631152
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1604196094
Short name T843
Test name
Test status
Simulation time 2553623836 ps
CPU time 2.41 seconds
Started Jul 01 06:39:55 PM PDT 24
Finished Jul 01 06:40:01 PM PDT 24
Peak memory 195796 kb
Host smart-11a7b7d2-a253-4bec-a32e-23fdffdf2cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604196094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1604196094
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.933251304
Short name T569
Test name
Test status
Simulation time 437484265 ps
CPU time 1.82 seconds
Started Jul 01 06:39:57 PM PDT 24
Finished Jul 01 06:40:03 PM PDT 24
Peak memory 198208 kb
Host smart-51b46818-64f0-4abe-a311-95f72a84ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933251304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.933251304
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1170039336
Short name T315
Test name
Test status
Simulation time 215787651947 ps
CPU time 1072.19 seconds
Started Jul 01 06:40:08 PM PDT 24
Finished Jul 01 06:58:08 PM PDT 24
Peak memory 200036 kb
Host smart-f67a0deb-5ce0-4b52-9476-e1a540c43f6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170039336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1170039336
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1198318700
Short name T695
Test name
Test status
Simulation time 170463495363 ps
CPU time 1760.36 seconds
Started Jul 01 06:40:08 PM PDT 24
Finished Jul 01 07:09:36 PM PDT 24
Peak memory 227492 kb
Host smart-6e2467b2-4775-491a-b365-26816c900299
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198318700 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1198318700
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3016974937
Short name T323
Test name
Test status
Simulation time 6927736806 ps
CPU time 11.59 seconds
Started Jul 01 06:40:08 PM PDT 24
Finished Jul 01 06:40:27 PM PDT 24
Peak memory 199468 kb
Host smart-7738acc7-c895-4e47-8055-8d438116a631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016974937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3016974937
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3958387955
Short name T583
Test name
Test status
Simulation time 98302162882 ps
CPU time 36.52 seconds
Started Jul 01 06:39:56 PM PDT 24
Finished Jul 01 06:40:36 PM PDT 24
Peak memory 200096 kb
Host smart-60882807-29cf-44af-a431-323a599adcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958387955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3958387955
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2133068349
Short name T369
Test name
Test status
Simulation time 26293935 ps
CPU time 0.56 seconds
Started Jul 01 06:40:08 PM PDT 24
Finished Jul 01 06:40:16 PM PDT 24
Peak memory 195344 kb
Host smart-588f4a11-970a-4124-b1ef-3afe482192c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133068349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2133068349
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2740485333
Short name T604
Test name
Test status
Simulation time 115044814080 ps
CPU time 57.81 seconds
Started Jul 01 06:40:07 PM PDT 24
Finished Jul 01 06:41:13 PM PDT 24
Peak memory 200120 kb
Host smart-987dbf51-aeea-4507-9765-e7e98f796208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740485333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2740485333
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2856479319
Short name T656
Test name
Test status
Simulation time 46913639109 ps
CPU time 20.08 seconds
Started Jul 01 06:40:08 PM PDT 24
Finished Jul 01 06:40:35 PM PDT 24
Peak memory 199892 kb
Host smart-a0490d26-afce-44bf-b3fd-18808d75f241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856479319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2856479319
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1070222555
Short name T229
Test name
Test status
Simulation time 42809151675 ps
CPU time 13.11 seconds
Started Jul 01 06:40:07 PM PDT 24
Finished Jul 01 06:40:28 PM PDT 24
Peak memory 200096 kb
Host smart-7afdf7bf-8362-4dcc-8808-eae40f4245b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070222555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1070222555
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2423066622
Short name T309
Test name
Test status
Simulation time 23716405227 ps
CPU time 38.45 seconds
Started Jul 01 06:40:06 PM PDT 24
Finished Jul 01 06:40:53 PM PDT 24
Peak memory 199868 kb
Host smart-a5408d06-ec9b-48bb-a5be-0ee1f1100c3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423066622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2423066622
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2861848114
Short name T630
Test name
Test status
Simulation time 65010645807 ps
CPU time 229.48 seconds
Started Jul 01 06:40:09 PM PDT 24
Finished Jul 01 06:44:06 PM PDT 24
Peak memory 200000 kb
Host smart-6da3b7bd-5401-428e-8d21-45d8d825ee66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861848114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2861848114
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.194990294
Short name T59
Test name
Test status
Simulation time 4608309530 ps
CPU time 1.89 seconds
Started Jul 01 06:40:07 PM PDT 24
Finished Jul 01 06:40:17 PM PDT 24
Peak memory 197576 kb
Host smart-d0c388ee-b6a9-4ec5-8baf-ece2351f9e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194990294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.194990294
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.255644476
Short name T802
Test name
Test status
Simulation time 34060142423 ps
CPU time 96.82 seconds
Started Jul 01 06:40:09 PM PDT 24
Finished Jul 01 06:41:53 PM PDT 24
Peak memory 199972 kb
Host smart-acf90917-a95e-42ff-b023-419e50387e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255644476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.255644476
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3101766095
Short name T341
Test name
Test status
Simulation time 4432398802 ps
CPU time 9.62 seconds
Started Jul 01 06:40:07 PM PDT 24
Finished Jul 01 06:40:24 PM PDT 24
Peak memory 198132 kb
Host smart-2036db95-7c6b-4b00-846e-d1491e1a7d22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101766095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3101766095
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2297896807
Short name T965
Test name
Test status
Simulation time 35930897364 ps
CPU time 47.52 seconds
Started Jul 01 06:40:09 PM PDT 24
Finished Jul 01 06:41:04 PM PDT 24
Peak memory 200000 kb
Host smart-e4a2e9f2-1882-40f2-b2b8-5e6be1b4cb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297896807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2297896807
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3451210790
Short name T1020
Test name
Test status
Simulation time 7780766540 ps
CPU time 3.7 seconds
Started Jul 01 06:40:06 PM PDT 24
Finished Jul 01 06:40:18 PM PDT 24
Peak memory 196048 kb
Host smart-53115ac9-c8ea-465d-bd5f-97440dabbc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451210790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3451210790
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3748794736
Short name T1073
Test name
Test status
Simulation time 883008599 ps
CPU time 6.48 seconds
Started Jul 01 06:40:07 PM PDT 24
Finished Jul 01 06:40:22 PM PDT 24
Peak memory 199748 kb
Host smart-cdb0db52-035c-421e-88ac-36129627c52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748794736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3748794736
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1740644251
Short name T903
Test name
Test status
Simulation time 8096958342 ps
CPU time 15.75 seconds
Started Jul 01 06:40:04 PM PDT 24
Finished Jul 01 06:40:30 PM PDT 24
Peak memory 199800 kb
Host smart-5e920eaf-b973-41bb-8b32-3bd7d467c08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740644251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1740644251
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3093788111
Short name T967
Test name
Test status
Simulation time 63074748005 ps
CPU time 31.23 seconds
Started Jul 01 06:40:05 PM PDT 24
Finished Jul 01 06:40:46 PM PDT 24
Peak memory 199956 kb
Host smart-12f5b20a-f6ee-464f-80e0-2be1bd736c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093788111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3093788111
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3655571569
Short name T996
Test name
Test status
Simulation time 13627989 ps
CPU time 0.57 seconds
Started Jul 01 06:40:16 PM PDT 24
Finished Jul 01 06:40:20 PM PDT 24
Peak memory 195708 kb
Host smart-b9c4dc5c-3227-4000-b425-95a3d7a5513d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655571569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3655571569
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3757185086
Short name T1067
Test name
Test status
Simulation time 150254432503 ps
CPU time 113.49 seconds
Started Jul 01 06:40:05 PM PDT 24
Finished Jul 01 06:42:08 PM PDT 24
Peak memory 200064 kb
Host smart-31ceb1d7-143f-42c6-b7cb-eaa9ac0ec01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757185086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3757185086
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3991014400
Short name T772
Test name
Test status
Simulation time 78259036376 ps
CPU time 29.92 seconds
Started Jul 01 06:40:05 PM PDT 24
Finished Jul 01 06:40:44 PM PDT 24
Peak memory 199980 kb
Host smart-430e8e43-95fb-43cc-a3e7-53e0edcf256d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991014400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3991014400
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.751432287
Short name T539
Test name
Test status
Simulation time 26438956551 ps
CPU time 53.87 seconds
Started Jul 01 06:40:09 PM PDT 24
Finished Jul 01 06:41:10 PM PDT 24
Peak memory 200024 kb
Host smart-b17e78ed-2d7d-4bf9-8f5e-edcfe923b7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751432287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.751432287
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1801980957
Short name T940
Test name
Test status
Simulation time 91480284628 ps
CPU time 443.15 seconds
Started Jul 01 06:40:17 PM PDT 24
Finished Jul 01 06:47:44 PM PDT 24
Peak memory 200052 kb
Host smart-a83d53d5-ef6d-422f-be43-188d2864817b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1801980957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1801980957
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.4067101780
Short name T707
Test name
Test status
Simulation time 10798097451 ps
CPU time 4.9 seconds
Started Jul 01 06:40:17 PM PDT 24
Finished Jul 01 06:40:26 PM PDT 24
Peak memory 198696 kb
Host smart-8a2bafc5-b21d-43af-8f08-6798e5f4c455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067101780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.4067101780
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.443002300
Short name T284
Test name
Test status
Simulation time 14085578072 ps
CPU time 5.52 seconds
Started Jul 01 06:40:08 PM PDT 24
Finished Jul 01 06:40:21 PM PDT 24
Peak memory 198964 kb
Host smart-b820a56e-a9ec-46eb-94f1-ac48c53b51f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443002300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.443002300
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2573933537
Short name T1068
Test name
Test status
Simulation time 36429664459 ps
CPU time 312 seconds
Started Jul 01 06:40:12 PM PDT 24
Finished Jul 01 06:45:30 PM PDT 24
Peak memory 200080 kb
Host smart-f88c034c-75a4-40c8-b082-adf654162417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573933537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2573933537
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1980958815
Short name T504
Test name
Test status
Simulation time 7444101040 ps
CPU time 31.71 seconds
Started Jul 01 06:40:08 PM PDT 24
Finished Jul 01 06:40:47 PM PDT 24
Peak memory 198948 kb
Host smart-9e8cae18-c8a2-4cf2-ba7a-a632a35cb00c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980958815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1980958815
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.10791780
Short name T1000
Test name
Test status
Simulation time 116811609582 ps
CPU time 48.43 seconds
Started Jul 01 06:40:13 PM PDT 24
Finished Jul 01 06:41:07 PM PDT 24
Peak memory 199796 kb
Host smart-1e89255d-9a5e-451d-96f8-bd6aefecc794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10791780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.10791780
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3369986433
Short name T699
Test name
Test status
Simulation time 27037015266 ps
CPU time 38.28 seconds
Started Jul 01 06:40:13 PM PDT 24
Finished Jul 01 06:40:56 PM PDT 24
Peak memory 196052 kb
Host smart-151aa0de-4ff4-4033-a5ce-b2dffd8d6ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369986433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3369986433
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3172253342
Short name T616
Test name
Test status
Simulation time 298108607 ps
CPU time 1.09 seconds
Started Jul 01 06:40:06 PM PDT 24
Finished Jul 01 06:40:16 PM PDT 24
Peak memory 198532 kb
Host smart-ecf62eeb-db89-4523-8275-2b4bd3596907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172253342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3172253342
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3749847086
Short name T623
Test name
Test status
Simulation time 534556110 ps
CPU time 1.82 seconds
Started Jul 01 06:40:17 PM PDT 24
Finished Jul 01 06:40:22 PM PDT 24
Peak memory 198552 kb
Host smart-1f695dd2-cb74-43e0-a5ea-93b40e6edb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749847086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3749847086
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.407249419
Short name T514
Test name
Test status
Simulation time 145335926930 ps
CPU time 102.5 seconds
Started Jul 01 06:40:06 PM PDT 24
Finished Jul 01 06:41:57 PM PDT 24
Peak memory 200004 kb
Host smart-407f0d1e-a29c-44c8-b236-f3ea2e51d722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407249419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.407249419
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2709691655
Short name T783
Test name
Test status
Simulation time 14804083 ps
CPU time 0.57 seconds
Started Jul 01 06:40:19 PM PDT 24
Finished Jul 01 06:40:23 PM PDT 24
Peak memory 195392 kb
Host smart-b8a9c415-f22b-4bc1-b6fa-e4fe41780271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709691655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2709691655
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2091642393
Short name T171
Test name
Test status
Simulation time 172148831088 ps
CPU time 60.31 seconds
Started Jul 01 06:40:12 PM PDT 24
Finished Jul 01 06:41:18 PM PDT 24
Peak memory 200008 kb
Host smart-9fee3378-4d02-489a-89fe-83a806acd8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091642393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2091642393
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3425504238
Short name T672
Test name
Test status
Simulation time 28491176187 ps
CPU time 26.67 seconds
Started Jul 01 06:40:12 PM PDT 24
Finished Jul 01 06:40:45 PM PDT 24
Peak memory 199480 kb
Host smart-2c9813e9-31e5-4007-8dd1-54d3c816e296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425504238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3425504238
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1067946267
Short name T236
Test name
Test status
Simulation time 127887048220 ps
CPU time 49.01 seconds
Started Jul 01 06:40:19 PM PDT 24
Finished Jul 01 06:41:11 PM PDT 24
Peak memory 199952 kb
Host smart-965e69cd-f170-48e0-bb2e-995982d377d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067946267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1067946267
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3588472684
Short name T1034
Test name
Test status
Simulation time 202315442133 ps
CPU time 247.2 seconds
Started Jul 01 06:40:14 PM PDT 24
Finished Jul 01 06:44:26 PM PDT 24
Peak memory 199668 kb
Host smart-96406f6f-0074-460d-8266-c133dc17e36e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588472684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3588472684
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2837000076
Short name T963
Test name
Test status
Simulation time 73805989396 ps
CPU time 113.25 seconds
Started Jul 01 06:40:16 PM PDT 24
Finished Jul 01 06:42:13 PM PDT 24
Peak memory 199984 kb
Host smart-870ce971-93e4-4f62-ad0e-2260c723c604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837000076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2837000076
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2329894489
Short name T1061
Test name
Test status
Simulation time 3924764347 ps
CPU time 3.17 seconds
Started Jul 01 06:40:19 PM PDT 24
Finished Jul 01 06:40:25 PM PDT 24
Peak memory 199896 kb
Host smart-638c264f-ed8f-4378-a472-7826c04f04d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329894489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2329894489
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.1996743843
Short name T471
Test name
Test status
Simulation time 11279806646 ps
CPU time 148.67 seconds
Started Jul 01 06:40:19 PM PDT 24
Finished Jul 01 06:42:51 PM PDT 24
Peak memory 200088 kb
Host smart-8aae2689-fe51-4d5e-bf5c-ff3993bbbfa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996743843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1996743843
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1274948820
Short name T663
Test name
Test status
Simulation time 3683130819 ps
CPU time 30.53 seconds
Started Jul 01 06:40:21 PM PDT 24
Finished Jul 01 06:40:54 PM PDT 24
Peak memory 198068 kb
Host smart-cb63fd46-edb4-4b8b-946a-3a0ca1ede332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1274948820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1274948820
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.285338151
Short name T848
Test name
Test status
Simulation time 184868846157 ps
CPU time 109.87 seconds
Started Jul 01 06:40:21 PM PDT 24
Finished Jul 01 06:42:14 PM PDT 24
Peak memory 199892 kb
Host smart-f89947fd-cf7f-43d7-a149-02fa35a52ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285338151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.285338151
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.698540026
Short name T1040
Test name
Test status
Simulation time 4477079352 ps
CPU time 1.55 seconds
Started Jul 01 06:40:13 PM PDT 24
Finished Jul 01 06:40:20 PM PDT 24
Peak memory 196496 kb
Host smart-10740d4b-7ee8-454f-8f93-fe84debc6c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698540026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.698540026
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2381470802
Short name T586
Test name
Test status
Simulation time 850343638 ps
CPU time 2.2 seconds
Started Jul 01 06:40:11 PM PDT 24
Finished Jul 01 06:40:20 PM PDT 24
Peak memory 198436 kb
Host smart-071ec8f4-64b3-4ff9-9182-b3dab2d0e0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381470802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2381470802
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2117599628
Short name T807
Test name
Test status
Simulation time 995190979 ps
CPU time 3.16 seconds
Started Jul 01 06:40:17 PM PDT 24
Finished Jul 01 06:40:24 PM PDT 24
Peak memory 199064 kb
Host smart-bf12ff1b-2ca3-4e58-a3ae-16ae44729ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117599628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2117599628
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3118122243
Short name T814
Test name
Test status
Simulation time 78160891180 ps
CPU time 25.86 seconds
Started Jul 01 06:40:13 PM PDT 24
Finished Jul 01 06:40:44 PM PDT 24
Peak memory 200112 kb
Host smart-f3d685ea-6d75-408f-9c90-5a77fbd2ad07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118122243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3118122243
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2973254608
Short name T720
Test name
Test status
Simulation time 28781402 ps
CPU time 0.61 seconds
Started Jul 01 06:40:27 PM PDT 24
Finished Jul 01 06:40:29 PM PDT 24
Peak memory 195304 kb
Host smart-5e31b3ef-08dd-4ccb-bf25-3ec6a3237cde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973254608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2973254608
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3207982378
Short name T448
Test name
Test status
Simulation time 85629152849 ps
CPU time 150.66 seconds
Started Jul 01 06:40:20 PM PDT 24
Finished Jul 01 06:42:53 PM PDT 24
Peak memory 200000 kb
Host smart-c6ba4c34-a34b-4819-b1c0-e6ee1d62cd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207982378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3207982378
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3677178435
Short name T1012
Test name
Test status
Simulation time 14791723814 ps
CPU time 35.94 seconds
Started Jul 01 06:40:18 PM PDT 24
Finished Jul 01 06:40:57 PM PDT 24
Peak memory 200032 kb
Host smart-2eb5643e-26ae-4c94-9984-35046ae778a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677178435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3677178435
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3980675137
Short name T1045
Test name
Test status
Simulation time 39347767358 ps
CPU time 67.81 seconds
Started Jul 01 06:40:22 PM PDT 24
Finished Jul 01 06:41:32 PM PDT 24
Peak memory 199292 kb
Host smart-3be9547b-48bc-4942-8d78-9678747e7260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980675137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3980675137
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1477492215
Short name T791
Test name
Test status
Simulation time 17940103079 ps
CPU time 15.72 seconds
Started Jul 01 06:40:19 PM PDT 24
Finished Jul 01 06:40:38 PM PDT 24
Peak memory 199924 kb
Host smart-7d7caec5-a8ab-4423-a47c-fc8e2c882bc5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477492215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1477492215
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1901638687
Short name T665
Test name
Test status
Simulation time 70320920295 ps
CPU time 269.08 seconds
Started Jul 01 06:40:19 PM PDT 24
Finished Jul 01 06:44:50 PM PDT 24
Peak memory 199968 kb
Host smart-bef672cb-6d7d-4ee2-8edc-13c2e49d2eb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901638687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1901638687
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3929539399
Short name T480
Test name
Test status
Simulation time 1287013799 ps
CPU time 1.2 seconds
Started Jul 01 06:40:20 PM PDT 24
Finished Jul 01 06:40:24 PM PDT 24
Peak memory 196044 kb
Host smart-81cf02ee-b1ae-45ea-9353-45e73a4ca10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929539399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3929539399
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2476544124
Short name T631
Test name
Test status
Simulation time 19714844935 ps
CPU time 15.13 seconds
Started Jul 01 06:40:21 PM PDT 24
Finished Jul 01 06:40:39 PM PDT 24
Peak memory 199852 kb
Host smart-46386e43-9d27-4081-a9d3-00dd572a8776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476544124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2476544124
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2534827971
Short name T39
Test name
Test status
Simulation time 15752200959 ps
CPU time 293.31 seconds
Started Jul 01 06:40:18 PM PDT 24
Finished Jul 01 06:45:15 PM PDT 24
Peak memory 199968 kb
Host smart-084c125e-1132-4a87-bc69-ba80b9e3e582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534827971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2534827971
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3614673331
Short name T973
Test name
Test status
Simulation time 1480675832 ps
CPU time 5.89 seconds
Started Jul 01 06:40:22 PM PDT 24
Finished Jul 01 06:40:30 PM PDT 24
Peak memory 197612 kb
Host smart-3e93b6bb-8057-4fed-bc50-bb34456a1607
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614673331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3614673331
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2300426244
Short name T830
Test name
Test status
Simulation time 67513418132 ps
CPU time 38.91 seconds
Started Jul 01 06:40:20 PM PDT 24
Finished Jul 01 06:41:01 PM PDT 24
Peak memory 199996 kb
Host smart-e10d22be-7064-4600-9c28-035ecfc7592f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300426244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2300426244
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4284304071
Short name T808
Test name
Test status
Simulation time 3080473655 ps
CPU time 1.78 seconds
Started Jul 01 06:40:20 PM PDT 24
Finished Jul 01 06:40:25 PM PDT 24
Peak memory 196844 kb
Host smart-cec43f25-df89-460d-b355-a21e48c582ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284304071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4284304071
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3392353069
Short name T387
Test name
Test status
Simulation time 5881061551 ps
CPU time 13.53 seconds
Started Jul 01 06:40:22 PM PDT 24
Finished Jul 01 06:40:38 PM PDT 24
Peak memory 198504 kb
Host smart-1edc1068-680d-45b2-8fe4-793221e58f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392353069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3392353069
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.305480627
Short name T124
Test name
Test status
Simulation time 153737135792 ps
CPU time 274.28 seconds
Started Jul 01 06:40:26 PM PDT 24
Finished Jul 01 06:45:01 PM PDT 24
Peak memory 200024 kb
Host smart-777c5312-5f7d-43f9-9709-ec331a8ab4a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305480627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.305480627
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1431797530
Short name T934
Test name
Test status
Simulation time 841418837 ps
CPU time 3.19 seconds
Started Jul 01 06:40:22 PM PDT 24
Finished Jul 01 06:40:27 PM PDT 24
Peak memory 198892 kb
Host smart-6bd63cda-f77d-4b87-a569-64fcd28b3cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431797530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1431797530
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3409628645
Short name T777
Test name
Test status
Simulation time 33720627323 ps
CPU time 39.22 seconds
Started Jul 01 06:40:18 PM PDT 24
Finished Jul 01 06:41:00 PM PDT 24
Peak memory 200072 kb
Host smart-a939ce15-e7af-47aa-93b6-6008f6dc56c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409628645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3409628645
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3320585454
Short name T379
Test name
Test status
Simulation time 37329911 ps
CPU time 0.54 seconds
Started Jul 01 06:40:36 PM PDT 24
Finished Jul 01 06:40:38 PM PDT 24
Peak memory 195324 kb
Host smart-fde77664-81b2-429c-9774-9972d5a55729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320585454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3320585454
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3847139215
Short name T78
Test name
Test status
Simulation time 59418650811 ps
CPU time 56.9 seconds
Started Jul 01 06:40:29 PM PDT 24
Finished Jul 01 06:41:26 PM PDT 24
Peak memory 200024 kb
Host smart-17f1de44-4e97-4ef0-86d0-9d28be01ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847139215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3847139215
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2509128440
Short name T367
Test name
Test status
Simulation time 15910333835 ps
CPU time 26.04 seconds
Started Jul 01 06:40:34 PM PDT 24
Finished Jul 01 06:41:02 PM PDT 24
Peak memory 199484 kb
Host smart-8d0dadca-69f2-4cdd-bb38-b7103b2bf5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509128440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2509128440
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1114186097
Short name T585
Test name
Test status
Simulation time 92344547319 ps
CPU time 35.99 seconds
Started Jul 01 06:40:28 PM PDT 24
Finished Jul 01 06:41:05 PM PDT 24
Peak memory 199916 kb
Host smart-d71edde0-44b8-4413-9261-5ecac99d2578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114186097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1114186097
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1759366903
Short name T439
Test name
Test status
Simulation time 184104281898 ps
CPU time 290.7 seconds
Started Jul 01 06:40:36 PM PDT 24
Finished Jul 01 06:45:28 PM PDT 24
Peak memory 199936 kb
Host smart-87b03b15-19f1-49af-be2c-b7c3fa702c87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1759366903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1759366903
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.4211126592
Short name T941
Test name
Test status
Simulation time 7308528336 ps
CPU time 4.44 seconds
Started Jul 01 06:40:34 PM PDT 24
Finished Jul 01 06:40:40 PM PDT 24
Peak memory 199676 kb
Host smart-3187dc62-e1b4-4ec9-ac5f-5fe9779575a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211126592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4211126592
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.1690583435
Short name T560
Test name
Test status
Simulation time 13908269225 ps
CPU time 180.99 seconds
Started Jul 01 06:40:34 PM PDT 24
Finished Jul 01 06:43:37 PM PDT 24
Peak memory 200020 kb
Host smart-738dc4ba-46c9-44c7-ae1a-86b042e57443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690583435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1690583435
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3983096040
Short name T49
Test name
Test status
Simulation time 2344748157 ps
CPU time 6.54 seconds
Started Jul 01 06:40:34 PM PDT 24
Finished Jul 01 06:40:42 PM PDT 24
Peak memory 197968 kb
Host smart-b7b91fe0-491a-43b9-b015-1baa03746119
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3983096040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3983096040
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3727850809
Short name T744
Test name
Test status
Simulation time 23575952027 ps
CPU time 37.83 seconds
Started Jul 01 06:40:33 PM PDT 24
Finished Jul 01 06:41:11 PM PDT 24
Peak memory 199896 kb
Host smart-be36e389-67b3-44d2-820c-5f6eb18223a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727850809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3727850809
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1573710265
Short name T280
Test name
Test status
Simulation time 42362632633 ps
CPU time 25.43 seconds
Started Jul 01 06:40:35 PM PDT 24
Finished Jul 01 06:41:02 PM PDT 24
Peak memory 195780 kb
Host smart-cc1d6d01-215d-4fa2-9eab-9b31b83446ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573710265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1573710265
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2227065455
Short name T1041
Test name
Test status
Simulation time 328212731 ps
CPU time 0.99 seconds
Started Jul 01 06:40:34 PM PDT 24
Finished Jul 01 06:40:37 PM PDT 24
Peak memory 198400 kb
Host smart-61b67c90-1eb9-4665-ac2b-22e87381dbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227065455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2227065455
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3739878099
Short name T907
Test name
Test status
Simulation time 192326253860 ps
CPU time 462.85 seconds
Started Jul 01 06:40:34 PM PDT 24
Finished Jul 01 06:48:18 PM PDT 24
Peak memory 200052 kb
Host smart-2bf0a327-3cdd-4407-9562-35242924552d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739878099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3739878099
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.191861513
Short name T57
Test name
Test status
Simulation time 210577402537 ps
CPU time 593.05 seconds
Started Jul 01 06:40:34 PM PDT 24
Finished Jul 01 06:50:29 PM PDT 24
Peak memory 216612 kb
Host smart-c30d7d5a-5a47-4fb8-903d-f4d0cf19fbf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191861513 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.191861513
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2200172374
Short name T884
Test name
Test status
Simulation time 6853570567 ps
CPU time 28.21 seconds
Started Jul 01 06:40:34 PM PDT 24
Finished Jul 01 06:41:03 PM PDT 24
Peak memory 199816 kb
Host smart-83f08c1b-856c-4832-9d26-9fa1c998438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200172374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2200172374
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1102341941
Short name T276
Test name
Test status
Simulation time 80685870369 ps
CPU time 108.99 seconds
Started Jul 01 06:40:27 PM PDT 24
Finished Jul 01 06:42:16 PM PDT 24
Peak memory 200000 kb
Host smart-b15c9658-feda-403f-b77f-2c74ed6016a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102341941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1102341941
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1503206682
Short name T862
Test name
Test status
Simulation time 54879830 ps
CPU time 0.55 seconds
Started Jul 01 06:40:45 PM PDT 24
Finished Jul 01 06:40:47 PM PDT 24
Peak memory 195376 kb
Host smart-4376b074-34f3-4b7d-8ef7-d1c79ca5518f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503206682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1503206682
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2579457360
Short name T181
Test name
Test status
Simulation time 196118819015 ps
CPU time 62.67 seconds
Started Jul 01 06:40:34 PM PDT 24
Finished Jul 01 06:41:38 PM PDT 24
Peak memory 199992 kb
Host smart-02bd47af-c130-43b0-bf9b-2c857b05bc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579457360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2579457360
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.149048141
Short name T944
Test name
Test status
Simulation time 61768045312 ps
CPU time 28.7 seconds
Started Jul 01 06:40:35 PM PDT 24
Finished Jul 01 06:41:06 PM PDT 24
Peak memory 199532 kb
Host smart-e93cdc86-5b72-44ab-aee8-1fe5102bf8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149048141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.149048141
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3182069540
Short name T680
Test name
Test status
Simulation time 105392783271 ps
CPU time 11.49 seconds
Started Jul 01 06:40:33 PM PDT 24
Finished Jul 01 06:40:45 PM PDT 24
Peak memory 199732 kb
Host smart-1a9c91f7-9be7-4a75-a686-49bb77e08445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182069540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3182069540
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3001263299
Short name T926
Test name
Test status
Simulation time 51947716843 ps
CPU time 24.8 seconds
Started Jul 01 06:40:45 PM PDT 24
Finished Jul 01 06:41:11 PM PDT 24
Peak memory 199924 kb
Host smart-3c384599-ae8a-4e31-8f34-e3d4fd912138
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001263299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3001263299
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3540924736
Short name T592
Test name
Test status
Simulation time 156952973264 ps
CPU time 1275.56 seconds
Started Jul 01 06:40:44 PM PDT 24
Finished Jul 01 07:02:01 PM PDT 24
Peak memory 200064 kb
Host smart-46e2b82d-6307-49c2-8d96-5419d3447e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3540924736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3540924736
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2525786756
Short name T928
Test name
Test status
Simulation time 30342459 ps
CPU time 0.58 seconds
Started Jul 01 06:40:42 PM PDT 24
Finished Jul 01 06:40:43 PM PDT 24
Peak memory 195908 kb
Host smart-fceee407-653e-4bad-b3b7-93a058fcf637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525786756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2525786756
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.2941255984
Short name T395
Test name
Test status
Simulation time 21419427693 ps
CPU time 76.97 seconds
Started Jul 01 06:40:42 PM PDT 24
Finished Jul 01 06:42:01 PM PDT 24
Peak memory 199932 kb
Host smart-0d6b3079-75c1-4c25-8a21-0351fb4d9891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2941255984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2941255984
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3257884625
Short name T575
Test name
Test status
Simulation time 5097559244 ps
CPU time 8.61 seconds
Started Jul 01 06:40:37 PM PDT 24
Finished Jul 01 06:40:47 PM PDT 24
Peak memory 199312 kb
Host smart-0e3da904-3625-4d0f-81a0-e5c4d37f3557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3257884625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3257884625
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1650571224
Short name T146
Test name
Test status
Simulation time 9872378250 ps
CPU time 11.09 seconds
Started Jul 01 06:40:45 PM PDT 24
Finished Jul 01 06:40:58 PM PDT 24
Peak memory 199896 kb
Host smart-69482bfd-c392-40ee-80d3-bb3d45bbea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650571224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1650571224
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3109115330
Short name T445
Test name
Test status
Simulation time 4537166462 ps
CPU time 7.13 seconds
Started Jul 01 06:40:41 PM PDT 24
Finished Jul 01 06:40:49 PM PDT 24
Peak memory 196756 kb
Host smart-611ca15c-cd36-4e4f-8e76-4412e3ef0ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109115330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3109115330
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.820105472
Short name T366
Test name
Test status
Simulation time 268179197 ps
CPU time 1.43 seconds
Started Jul 01 06:40:33 PM PDT 24
Finished Jul 01 06:40:36 PM PDT 24
Peak memory 198392 kb
Host smart-ff282852-790c-43cc-bf1b-1451415517c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820105472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.820105472
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3931007620
Short name T60
Test name
Test status
Simulation time 137470999034 ps
CPU time 2249.46 seconds
Started Jul 01 06:40:42 PM PDT 24
Finished Jul 01 07:18:12 PM PDT 24
Peak memory 199968 kb
Host smart-54c18cbc-b048-4445-b1f5-afdcc5b2ddf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931007620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3931007620
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3007391491
Short name T340
Test name
Test status
Simulation time 119524827541 ps
CPU time 1146.76 seconds
Started Jul 01 06:40:42 PM PDT 24
Finished Jul 01 06:59:50 PM PDT 24
Peak memory 216572 kb
Host smart-028bc835-3517-4058-98d5-661939d93a63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007391491 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3007391491
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1760027716
Short name T362
Test name
Test status
Simulation time 761789633 ps
CPU time 2.02 seconds
Started Jul 01 06:40:42 PM PDT 24
Finished Jul 01 06:40:44 PM PDT 24
Peak memory 198552 kb
Host smart-ccfdc5a2-dc97-4566-9bd1-092337d09c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760027716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1760027716
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.584261311
Short name T652
Test name
Test status
Simulation time 278152915113 ps
CPU time 52.46 seconds
Started Jul 01 06:40:36 PM PDT 24
Finished Jul 01 06:41:30 PM PDT 24
Peak memory 199932 kb
Host smart-10959d4b-5190-42ea-9c6d-af7ef106db29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584261311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.584261311
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2680535242
Short name T673
Test name
Test status
Simulation time 15387953 ps
CPU time 0.57 seconds
Started Jul 01 06:35:09 PM PDT 24
Finished Jul 01 06:35:11 PM PDT 24
Peak memory 195328 kb
Host smart-81b9732b-adef-4ca7-89c8-de16804ec243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680535242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2680535242
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.4059832375
Short name T645
Test name
Test status
Simulation time 67917419724 ps
CPU time 103.74 seconds
Started Jul 01 06:35:01 PM PDT 24
Finished Jul 01 06:36:49 PM PDT 24
Peak memory 200164 kb
Host smart-c90c42c1-1be6-496d-b857-6df6a2e67998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059832375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.4059832375
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1307268030
Short name T428
Test name
Test status
Simulation time 97891695309 ps
CPU time 50.94 seconds
Started Jul 01 06:35:04 PM PDT 24
Finished Jul 01 06:35:57 PM PDT 24
Peak memory 199980 kb
Host smart-de105f7b-49bf-453b-b854-bc1cf9ec61c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307268030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1307268030
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.389491443
Short name T774
Test name
Test status
Simulation time 51379317264 ps
CPU time 76.47 seconds
Started Jul 01 06:35:00 PM PDT 24
Finished Jul 01 06:36:20 PM PDT 24
Peak memory 200064 kb
Host smart-c9e0061b-731f-4504-adb8-08bbff340b6c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389491443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.389491443
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.4170426606
Short name T115
Test name
Test status
Simulation time 142215577384 ps
CPU time 328.34 seconds
Started Jul 01 06:35:09 PM PDT 24
Finished Jul 01 06:40:39 PM PDT 24
Peak memory 200064 kb
Host smart-6f7bb2c4-6dc8-4f29-baa4-ff0ac7c9b96f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4170426606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.4170426606
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.418732133
Short name T446
Test name
Test status
Simulation time 9297717033 ps
CPU time 20.23 seconds
Started Jul 01 06:35:01 PM PDT 24
Finished Jul 01 06:35:25 PM PDT 24
Peak memory 198620 kb
Host smart-15ec3741-04ac-4049-99af-7900dcfd8873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418732133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.418732133
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.2461282341
Short name T541
Test name
Test status
Simulation time 11559831617 ps
CPU time 512.46 seconds
Started Jul 01 06:35:02 PM PDT 24
Finished Jul 01 06:43:38 PM PDT 24
Peak memory 200148 kb
Host smart-fc99eaef-98de-48d7-b47d-5982c0c2e15a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461282341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2461282341
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.839087435
Short name T113
Test name
Test status
Simulation time 4140448557 ps
CPU time 31.38 seconds
Started Jul 01 06:35:00 PM PDT 24
Finished Jul 01 06:35:35 PM PDT 24
Peak memory 198176 kb
Host smart-c6b38935-f805-4f73-aabb-8e3586403e11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839087435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.839087435
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.94917285
Short name T579
Test name
Test status
Simulation time 80409531492 ps
CPU time 63.2 seconds
Started Jul 01 06:35:03 PM PDT 24
Finished Jul 01 06:36:09 PM PDT 24
Peak memory 199944 kb
Host smart-1afed5f6-fed4-48c6-bf18-71376199817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94917285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.94917285
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.604696392
Short name T84
Test name
Test status
Simulation time 32187417362 ps
CPU time 5.78 seconds
Started Jul 01 06:35:03 PM PDT 24
Finished Jul 01 06:35:12 PM PDT 24
Peak memory 195932 kb
Host smart-69337bc5-6144-4a93-84cf-cdac505326ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604696392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.604696392
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1674370941
Short name T912
Test name
Test status
Simulation time 948085300 ps
CPU time 2.12 seconds
Started Jul 01 06:35:07 PM PDT 24
Finished Jul 01 06:35:11 PM PDT 24
Peak memory 198860 kb
Host smart-152704dd-22b8-44d6-91dc-5014128891d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674370941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1674370941
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.890948280
Short name T494
Test name
Test status
Simulation time 6729579229 ps
CPU time 27.69 seconds
Started Jul 01 06:35:02 PM PDT 24
Finished Jul 01 06:35:33 PM PDT 24
Peak memory 199996 kb
Host smart-751c72ae-0ee7-44c2-ae84-5fce749cce0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890948280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.890948280
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2530727012
Short name T264
Test name
Test status
Simulation time 27309767354 ps
CPU time 25.17 seconds
Started Jul 01 06:35:01 PM PDT 24
Finished Jul 01 06:35:30 PM PDT 24
Peak memory 200064 kb
Host smart-597cd686-5a8e-40c8-a062-47a3d4e96ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530727012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2530727012
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2079791932
Short name T54
Test name
Test status
Simulation time 71685700660 ps
CPU time 508.18 seconds
Started Jul 01 06:40:49 PM PDT 24
Finished Jul 01 06:49:18 PM PDT 24
Peak memory 216616 kb
Host smart-8b4503e6-3a4c-4885-893b-320730bc2617
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079791932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2079791932
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1886640175
Short name T537
Test name
Test status
Simulation time 44916184464 ps
CPU time 61.54 seconds
Started Jul 01 06:40:51 PM PDT 24
Finished Jul 01 06:41:54 PM PDT 24
Peak memory 199884 kb
Host smart-9b0a018b-7b8a-4c65-aa02-c58c01a657d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886640175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1886640175
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.33493019
Short name T703
Test name
Test status
Simulation time 45097676877 ps
CPU time 145.56 seconds
Started Jul 01 06:40:51 PM PDT 24
Finished Jul 01 06:43:18 PM PDT 24
Peak memory 216560 kb
Host smart-333487c7-d410-40ee-9832-1f2badf62543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33493019 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.33493019
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3945715367
Short name T795
Test name
Test status
Simulation time 55951703997 ps
CPU time 57.32 seconds
Started Jul 01 06:40:52 PM PDT 24
Finished Jul 01 06:41:50 PM PDT 24
Peak memory 200164 kb
Host smart-396e6651-fbea-4c10-8f49-769775d09fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945715367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3945715367
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3080198897
Short name T207
Test name
Test status
Simulation time 88793676151 ps
CPU time 141.26 seconds
Started Jul 01 06:40:50 PM PDT 24
Finished Jul 01 06:43:13 PM PDT 24
Peak memory 200092 kb
Host smart-e063f38d-bb7e-4420-b3ec-460b60252662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080198897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3080198897
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3029110924
Short name T1025
Test name
Test status
Simulation time 145732744017 ps
CPU time 814.12 seconds
Started Jul 01 06:40:49 PM PDT 24
Finished Jul 01 06:54:24 PM PDT 24
Peak memory 216428 kb
Host smart-8d8fc3d3-bb36-4ebf-a99e-4c40b9e2e5b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029110924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3029110924
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1118499273
Short name T1035
Test name
Test status
Simulation time 76364543176 ps
CPU time 123.73 seconds
Started Jul 01 06:40:52 PM PDT 24
Finished Jul 01 06:42:56 PM PDT 24
Peak memory 199836 kb
Host smart-4fe7aefe-1c45-4165-991c-f16f01757b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118499273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1118499273
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3222868312
Short name T832
Test name
Test status
Simulation time 19926765123 ps
CPU time 692.77 seconds
Started Jul 01 06:40:51 PM PDT 24
Finished Jul 01 06:52:25 PM PDT 24
Peak memory 215596 kb
Host smart-83643de1-f6da-4940-906c-77b1121c708d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222868312 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3222868312
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.275175245
Short name T503
Test name
Test status
Simulation time 109591219985 ps
CPU time 16.47 seconds
Started Jul 01 06:40:50 PM PDT 24
Finished Jul 01 06:41:08 PM PDT 24
Peak memory 200024 kb
Host smart-32d87f91-671f-4d54-8b8f-dc53191bf39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275175245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.275175245
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3595146629
Short name T543
Test name
Test status
Simulation time 36462143494 ps
CPU time 24.74 seconds
Started Jul 01 06:40:59 PM PDT 24
Finished Jul 01 06:41:26 PM PDT 24
Peak memory 200068 kb
Host smart-ebe964fe-e11c-4702-82d5-9fe98889fa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595146629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3595146629
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.194178853
Short name T823
Test name
Test status
Simulation time 75788842870 ps
CPU time 834.47 seconds
Started Jul 01 06:41:00 PM PDT 24
Finished Jul 01 06:54:57 PM PDT 24
Peak memory 224660 kb
Host smart-8992abf9-ef0b-427a-8fbc-31e9e2d7e1c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194178853 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.194178853
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3888201512
Short name T208
Test name
Test status
Simulation time 83658804803 ps
CPU time 83.76 seconds
Started Jul 01 06:40:59 PM PDT 24
Finished Jul 01 06:42:25 PM PDT 24
Peak memory 199904 kb
Host smart-2e48a7cd-98d4-4583-b8c9-5c8516dfa266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888201512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3888201512
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1315672118
Short name T422
Test name
Test status
Simulation time 58568302 ps
CPU time 0.55 seconds
Started Jul 01 06:35:08 PM PDT 24
Finished Jul 01 06:35:11 PM PDT 24
Peak memory 195608 kb
Host smart-68f63784-7e34-419b-9737-291695c5b8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315672118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1315672118
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.914966117
Short name T1083
Test name
Test status
Simulation time 409765356698 ps
CPU time 178.44 seconds
Started Jul 01 06:35:08 PM PDT 24
Finished Jul 01 06:38:08 PM PDT 24
Peak memory 199920 kb
Host smart-0d032a7f-145b-40b2-ad30-c541d06228b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914966117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.914966117
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3925697097
Short name T132
Test name
Test status
Simulation time 176847825105 ps
CPU time 396.89 seconds
Started Jul 01 06:35:13 PM PDT 24
Finished Jul 01 06:41:51 PM PDT 24
Peak memory 199936 kb
Host smart-159b52bc-c62b-43b3-8b0f-0119817a97af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925697097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3925697097
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.689373089
Short name T831
Test name
Test status
Simulation time 84376274071 ps
CPU time 43.47 seconds
Started Jul 01 06:35:07 PM PDT 24
Finished Jul 01 06:35:52 PM PDT 24
Peak memory 199964 kb
Host smart-b24802d8-78be-459d-94a3-9c797e7527d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689373089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.689373089
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2231081061
Short name T715
Test name
Test status
Simulation time 31360412840 ps
CPU time 52.49 seconds
Started Jul 01 06:35:08 PM PDT 24
Finished Jul 01 06:36:02 PM PDT 24
Peak memory 199988 kb
Host smart-671f9083-4901-4de0-b977-db12a7d729af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231081061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2231081061
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.150923999
Short name T764
Test name
Test status
Simulation time 127295104633 ps
CPU time 724.01 seconds
Started Jul 01 06:35:07 PM PDT 24
Finished Jul 01 06:47:12 PM PDT 24
Peak memory 199916 kb
Host smart-4a254dc7-57ab-47d3-9f4c-4a1ae4cb8229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150923999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.150923999
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.915849006
Short name T713
Test name
Test status
Simulation time 174094412 ps
CPU time 0.94 seconds
Started Jul 01 06:35:07 PM PDT 24
Finished Jul 01 06:35:09 PM PDT 24
Peak memory 197388 kb
Host smart-e3d88708-2d2c-4188-8590-c201f63d8077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915849006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.915849006
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3191130372
Short name T343
Test name
Test status
Simulation time 2541117233 ps
CPU time 8.35 seconds
Started Jul 01 06:35:07 PM PDT 24
Finished Jul 01 06:35:16 PM PDT 24
Peak memory 199572 kb
Host smart-ad47c5ca-8732-4405-92b9-3fb6dc763708
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191130372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3191130372
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1632984062
Short name T955
Test name
Test status
Simulation time 23917475626 ps
CPU time 39.18 seconds
Started Jul 01 06:35:13 PM PDT 24
Finished Jul 01 06:35:54 PM PDT 24
Peak memory 199992 kb
Host smart-04cfea08-d67c-4409-a875-e4b309176ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632984062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1632984062
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3955986328
Short name T568
Test name
Test status
Simulation time 44379525549 ps
CPU time 17 seconds
Started Jul 01 06:35:09 PM PDT 24
Finished Jul 01 06:35:28 PM PDT 24
Peak memory 196444 kb
Host smart-ea81700d-a308-493a-9476-74bd23d5043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955986328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3955986328
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.801137154
Short name T426
Test name
Test status
Simulation time 286246025 ps
CPU time 1.58 seconds
Started Jul 01 06:35:06 PM PDT 24
Finished Jul 01 06:35:08 PM PDT 24
Peak memory 198732 kb
Host smart-fc69cc3b-e5e3-4627-9d4a-9c2d5248c150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801137154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.801137154
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.360321986
Short name T827
Test name
Test status
Simulation time 282682658408 ps
CPU time 722.12 seconds
Started Jul 01 06:35:09 PM PDT 24
Finished Jul 01 06:47:13 PM PDT 24
Peak memory 199984 kb
Host smart-27c32a09-e0bb-4956-a8b9-db31a8741927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360321986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.360321986
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2690637729
Short name T339
Test name
Test status
Simulation time 82808703271 ps
CPU time 2068.93 seconds
Started Jul 01 06:35:07 PM PDT 24
Finished Jul 01 07:09:37 PM PDT 24
Peak memory 224680 kb
Host smart-7c52bd50-700a-4deb-a63b-63cd4c26f343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690637729 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2690637729
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2569409635
Short name T444
Test name
Test status
Simulation time 1899647550 ps
CPU time 3.48 seconds
Started Jul 01 06:35:08 PM PDT 24
Finished Jul 01 06:35:13 PM PDT 24
Peak memory 199332 kb
Host smart-55f940bb-0609-40f0-9d7c-4dff5480d46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569409635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2569409635
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.935287072
Short name T696
Test name
Test status
Simulation time 91529337958 ps
CPU time 71.4 seconds
Started Jul 01 06:35:13 PM PDT 24
Finished Jul 01 06:36:26 PM PDT 24
Peak memory 199916 kb
Host smart-bfd802de-9014-42bc-84fa-a7d99eda1c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935287072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.935287072
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2217846944
Short name T667
Test name
Test status
Simulation time 177670476398 ps
CPU time 195.3 seconds
Started Jul 01 06:41:01 PM PDT 24
Finished Jul 01 06:44:18 PM PDT 24
Peak memory 199936 kb
Host smart-b017e54e-9bc4-4b00-9b3c-148c966f2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217846944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2217846944
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3835593230
Short name T178
Test name
Test status
Simulation time 181308643008 ps
CPU time 863.4 seconds
Started Jul 01 06:41:02 PM PDT 24
Finished Jul 01 06:55:27 PM PDT 24
Peak memory 215708 kb
Host smart-b9b20e26-7deb-41f4-9197-31211a616950
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835593230 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3835593230
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1536449795
Short name T1055
Test name
Test status
Simulation time 66624901699 ps
CPU time 96.52 seconds
Started Jul 01 06:40:59 PM PDT 24
Finished Jul 01 06:42:38 PM PDT 24
Peak memory 199936 kb
Host smart-b13369f1-0eea-4874-9c46-99c2b995047a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536449795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1536449795
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2328700544
Short name T122
Test name
Test status
Simulation time 104468080785 ps
CPU time 265.63 seconds
Started Jul 01 06:40:59 PM PDT 24
Finished Jul 01 06:45:27 PM PDT 24
Peak memory 216632 kb
Host smart-2a9fe311-aefc-4f70-ba7b-cf516c6355e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328700544 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2328700544
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3826242732
Short name T476
Test name
Test status
Simulation time 88807997333 ps
CPU time 31.16 seconds
Started Jul 01 06:41:00 PM PDT 24
Finished Jul 01 06:41:33 PM PDT 24
Peak memory 199992 kb
Host smart-91910384-3819-4170-867e-a1c4199754fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826242732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3826242732
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1477808524
Short name T1081
Test name
Test status
Simulation time 39749037438 ps
CPU time 708.59 seconds
Started Jul 01 06:40:59 PM PDT 24
Finished Jul 01 06:52:49 PM PDT 24
Peak memory 215556 kb
Host smart-ca3e991d-b690-47d5-9848-98177a9ac869
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477808524 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1477808524
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1618091350
Short name T875
Test name
Test status
Simulation time 165312386093 ps
CPU time 71.3 seconds
Started Jul 01 06:40:58 PM PDT 24
Finished Jul 01 06:42:11 PM PDT 24
Peak memory 200016 kb
Host smart-bddff487-e765-47f1-9c6a-88bb4a706270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618091350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1618091350
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3537770536
Short name T639
Test name
Test status
Simulation time 15047972735 ps
CPU time 28.72 seconds
Started Jul 01 06:40:59 PM PDT 24
Finished Jul 01 06:41:30 PM PDT 24
Peak memory 199916 kb
Host smart-90808d76-aebe-4daa-9fd1-a64b0ab7282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537770536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3537770536
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1383433844
Short name T240
Test name
Test status
Simulation time 24601159792 ps
CPU time 11.87 seconds
Started Jul 01 06:40:59 PM PDT 24
Finished Jul 01 06:41:13 PM PDT 24
Peak memory 199972 kb
Host smart-cb9d4fca-da79-4a1f-ac1f-118081bcab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383433844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1383433844
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.292055878
Short name T500
Test name
Test status
Simulation time 17724100912 ps
CPU time 188.9 seconds
Started Jul 01 06:41:00 PM PDT 24
Finished Jul 01 06:44:11 PM PDT 24
Peak memory 208324 kb
Host smart-0a389421-f3af-4cc9-bc1a-c5985fc42cd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292055878 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.292055878
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2601727378
Short name T172
Test name
Test status
Simulation time 29945251124 ps
CPU time 46.22 seconds
Started Jul 01 06:41:02 PM PDT 24
Finished Jul 01 06:41:50 PM PDT 24
Peak memory 200000 kb
Host smart-454f129a-4db5-4266-9a9c-47cc379a9b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601727378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2601727378
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.4071374026
Short name T185
Test name
Test status
Simulation time 948425834144 ps
CPU time 530.22 seconds
Started Jul 01 06:40:59 PM PDT 24
Finished Jul 01 06:49:51 PM PDT 24
Peak memory 226124 kb
Host smart-e3f43764-593a-498e-9810-0886e9d71b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071374026 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.4071374026
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2178534403
Short name T412
Test name
Test status
Simulation time 155734143297 ps
CPU time 68.88 seconds
Started Jul 01 06:40:59 PM PDT 24
Finished Jul 01 06:42:10 PM PDT 24
Peak memory 199880 kb
Host smart-85062413-cb58-453a-98e5-c4b2349aaffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178534403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2178534403
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.514417935
Short name T565
Test name
Test status
Simulation time 15491119 ps
CPU time 0.58 seconds
Started Jul 01 06:35:14 PM PDT 24
Finished Jul 01 06:35:17 PM PDT 24
Peak memory 195312 kb
Host smart-3daf5af7-5e2c-4e0a-955d-abdc72754719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514417935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.514417935
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.384315786
Short name T161
Test name
Test status
Simulation time 46874106650 ps
CPU time 26.68 seconds
Started Jul 01 06:35:07 PM PDT 24
Finished Jul 01 06:35:35 PM PDT 24
Peak memory 200008 kb
Host smart-eb9d9cdc-9ad8-4a1d-94b3-f98d043df572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384315786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.384315786
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2108944717
Short name T740
Test name
Test status
Simulation time 38708827319 ps
CPU time 14.24 seconds
Started Jul 01 06:35:14 PM PDT 24
Finished Jul 01 06:35:32 PM PDT 24
Peak memory 199540 kb
Host smart-c5d9bc76-e345-4324-b6df-dc55977c7368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108944717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2108944717
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4075921646
Short name T925
Test name
Test status
Simulation time 5259857767 ps
CPU time 10.48 seconds
Started Jul 01 06:35:16 PM PDT 24
Finished Jul 01 06:35:29 PM PDT 24
Peak memory 200016 kb
Host smart-36a6541f-45eb-49c2-93a7-0fab1e982d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075921646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4075921646
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1904696739
Short name T730
Test name
Test status
Simulation time 47233259842 ps
CPU time 166 seconds
Started Jul 01 06:35:18 PM PDT 24
Finished Jul 01 06:38:06 PM PDT 24
Peak memory 199952 kb
Host smart-c60e4688-cb18-4afa-a0cb-a2bd489cca64
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904696739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1904696739
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3988623542
Short name T943
Test name
Test status
Simulation time 102906286153 ps
CPU time 423.72 seconds
Started Jul 01 06:35:18 PM PDT 24
Finished Jul 01 06:42:24 PM PDT 24
Peak memory 200068 kb
Host smart-b13d9673-4a24-468e-9828-97dd969fe670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988623542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3988623542
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.962811395
Short name T819
Test name
Test status
Simulation time 3965901438 ps
CPU time 1.74 seconds
Started Jul 01 06:35:17 PM PDT 24
Finished Jul 01 06:35:20 PM PDT 24
Peak memory 199332 kb
Host smart-f7f5a8b2-1a7f-470c-8eed-d2fea1caff6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962811395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.962811395
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.335789276
Short name T1015
Test name
Test status
Simulation time 11855211560 ps
CPU time 701.37 seconds
Started Jul 01 06:35:13 PM PDT 24
Finished Jul 01 06:46:57 PM PDT 24
Peak memory 199992 kb
Host smart-88294057-0eae-4b2b-9139-52c33c36bdbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335789276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.335789276
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.258775663
Short name T846
Test name
Test status
Simulation time 2355380588 ps
CPU time 2.83 seconds
Started Jul 01 06:35:17 PM PDT 24
Finished Jul 01 06:35:22 PM PDT 24
Peak memory 198148 kb
Host smart-8fd16d9d-16f4-4480-80a8-78e3f8dec26e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258775663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.258775663
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1822355222
Short name T861
Test name
Test status
Simulation time 61920311868 ps
CPU time 53.56 seconds
Started Jul 01 06:35:20 PM PDT 24
Finished Jul 01 06:36:15 PM PDT 24
Peak memory 200064 kb
Host smart-41cea99f-76df-405d-9c62-12310c382efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822355222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1822355222
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.4174655318
Short name T459
Test name
Test status
Simulation time 41363287847 ps
CPU time 9.44 seconds
Started Jul 01 06:35:20 PM PDT 24
Finished Jul 01 06:35:31 PM PDT 24
Peak memory 196500 kb
Host smart-e2fb9fce-a120-491c-ad00-aedddb42b664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174655318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4174655318
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.638266025
Short name T375
Test name
Test status
Simulation time 627434210 ps
CPU time 2.3 seconds
Started Jul 01 06:35:09 PM PDT 24
Finished Jul 01 06:35:13 PM PDT 24
Peak memory 199656 kb
Host smart-c522c6e9-32e5-42d2-adeb-a5702cf97b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638266025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.638266025
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1871201526
Short name T590
Test name
Test status
Simulation time 134616008806 ps
CPU time 64.23 seconds
Started Jul 01 06:35:16 PM PDT 24
Finished Jul 01 06:36:23 PM PDT 24
Peak memory 199876 kb
Host smart-7f0fed3b-0bf8-4779-9296-1fa7be34f4d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871201526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1871201526
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.76785830
Short name T981
Test name
Test status
Simulation time 7573588929 ps
CPU time 5.86 seconds
Started Jul 01 06:35:18 PM PDT 24
Finished Jul 01 06:35:25 PM PDT 24
Peak memory 199640 kb
Host smart-776c0f3a-b86f-46a9-b620-49186b659e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76785830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.76785830
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2781835238
Short name T671
Test name
Test status
Simulation time 249447774843 ps
CPU time 32.22 seconds
Started Jul 01 06:35:08 PM PDT 24
Finished Jul 01 06:35:41 PM PDT 24
Peak memory 199920 kb
Host smart-28fb1de5-2b79-4750-9ddf-a4524bde780e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781835238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2781835238
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2139977830
Short name T888
Test name
Test status
Simulation time 75327513388 ps
CPU time 120.4 seconds
Started Jul 01 06:40:58 PM PDT 24
Finished Jul 01 06:42:58 PM PDT 24
Peak memory 199980 kb
Host smart-fe4137a1-370f-4b40-8452-0996d58b2837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139977830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2139977830
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.423805335
Short name T233
Test name
Test status
Simulation time 232070986472 ps
CPU time 34.25 seconds
Started Jul 01 06:40:59 PM PDT 24
Finished Jul 01 06:41:35 PM PDT 24
Peak memory 200096 kb
Host smart-9aab1409-c7cb-4ff2-8c46-dce5cbcfbe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423805335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.423805335
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.931578457
Short name T746
Test name
Test status
Simulation time 179278084880 ps
CPU time 51.53 seconds
Started Jul 01 06:41:11 PM PDT 24
Finished Jul 01 06:42:04 PM PDT 24
Peak memory 200104 kb
Host smart-2a59cd9f-1de2-4507-bad3-301b1813f32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931578457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.931578457
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1353283543
Short name T970
Test name
Test status
Simulation time 10662692317 ps
CPU time 331.4 seconds
Started Jul 01 06:41:11 PM PDT 24
Finished Jul 01 06:46:43 PM PDT 24
Peak memory 216516 kb
Host smart-c440c24d-6661-4da2-8f5a-e1755629bb2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353283543 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1353283543
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2338194543
Short name T980
Test name
Test status
Simulation time 40352797332 ps
CPU time 29.21 seconds
Started Jul 01 06:41:10 PM PDT 24
Finished Jul 01 06:41:41 PM PDT 24
Peak memory 199996 kb
Host smart-d3b06195-3acd-4180-908e-fa12e84f9cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338194543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2338194543
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1786681723
Short name T351
Test name
Test status
Simulation time 50616307145 ps
CPU time 18.03 seconds
Started Jul 01 06:41:15 PM PDT 24
Finished Jul 01 06:41:34 PM PDT 24
Peak memory 200072 kb
Host smart-5e5733cc-a4a0-47c3-90d2-4b522f27956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786681723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1786681723
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3263284074
Short name T177
Test name
Test status
Simulation time 67194056254 ps
CPU time 46.13 seconds
Started Jul 01 06:41:13 PM PDT 24
Finished Jul 01 06:42:01 PM PDT 24
Peak memory 199952 kb
Host smart-7cd23020-a045-4f22-a417-11f1d546e711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263284074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3263284074
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1474919448
Short name T55
Test name
Test status
Simulation time 45934940568 ps
CPU time 421.63 seconds
Started Jul 01 06:41:12 PM PDT 24
Finished Jul 01 06:48:15 PM PDT 24
Peak memory 216452 kb
Host smart-be3276f1-17cb-4059-9119-7e8c035a42f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474919448 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1474919448
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3730271614
Short name T885
Test name
Test status
Simulation time 193342655261 ps
CPU time 43.52 seconds
Started Jul 01 06:41:12 PM PDT 24
Finished Jul 01 06:41:58 PM PDT 24
Peak memory 200004 kb
Host smart-08cf0c2c-d970-4f7c-8ba7-181c35b3d6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730271614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3730271614
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.943672980
Short name T219
Test name
Test status
Simulation time 99561657688 ps
CPU time 169.06 seconds
Started Jul 01 06:41:11 PM PDT 24
Finished Jul 01 06:44:01 PM PDT 24
Peak memory 199940 kb
Host smart-d22723e9-5c56-4dc6-8c6a-3549e78aa1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943672980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.943672980
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3521525088
Short name T28
Test name
Test status
Simulation time 18354975688 ps
CPU time 234.72 seconds
Started Jul 01 06:41:12 PM PDT 24
Finished Jul 01 06:45:08 PM PDT 24
Peak memory 208312 kb
Host smart-fd35a9f2-b78c-4d6f-b7a8-431988cdba27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521525088 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3521525088
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.575723931
Short name T1086
Test name
Test status
Simulation time 9333199485 ps
CPU time 15.52 seconds
Started Jul 01 06:41:11 PM PDT 24
Finished Jul 01 06:41:28 PM PDT 24
Peak memory 200000 kb
Host smart-89cd66f8-4c19-4571-ba27-8e680abcf1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575723931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.575723931
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.393015960
Short name T824
Test name
Test status
Simulation time 35313687 ps
CPU time 0.55 seconds
Started Jul 01 06:35:25 PM PDT 24
Finished Jul 01 06:35:28 PM PDT 24
Peak memory 195264 kb
Host smart-f159a758-3374-438e-a316-5043a62a5c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393015960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.393015960
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2968227666
Short name T1057
Test name
Test status
Simulation time 189699748310 ps
CPU time 34.52 seconds
Started Jul 01 06:35:14 PM PDT 24
Finished Jul 01 06:35:50 PM PDT 24
Peak memory 200044 kb
Host smart-56e0af2b-d583-4671-aa90-f0cae80309c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968227666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2968227666
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3748914849
Short name T442
Test name
Test status
Simulation time 223595546356 ps
CPU time 242.56 seconds
Started Jul 01 06:35:13 PM PDT 24
Finished Jul 01 06:39:18 PM PDT 24
Peak memory 199908 kb
Host smart-8c2adbbf-25ac-439c-b613-0a471228de99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748914849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3748914849
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1334965500
Short name T222
Test name
Test status
Simulation time 149554127096 ps
CPU time 49.33 seconds
Started Jul 01 06:35:15 PM PDT 24
Finished Jul 01 06:36:07 PM PDT 24
Peak memory 199936 kb
Host smart-7e1519de-eecb-4831-96f2-49a918a69771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334965500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1334965500
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3912631541
Short name T76
Test name
Test status
Simulation time 26038181457 ps
CPU time 17.72 seconds
Started Jul 01 06:35:20 PM PDT 24
Finished Jul 01 06:35:39 PM PDT 24
Peak memory 198304 kb
Host smart-f3f5de2c-a9a2-41b1-9afd-7665481506dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912631541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3912631541
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.218776796
Short name T914
Test name
Test status
Simulation time 150188680826 ps
CPU time 203.39 seconds
Started Jul 01 06:35:24 PM PDT 24
Finished Jul 01 06:38:50 PM PDT 24
Peak memory 199948 kb
Host smart-7a20a0b5-fabf-4827-9969-346367521f4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218776796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.218776796
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3495606153
Short name T479
Test name
Test status
Simulation time 5047409749 ps
CPU time 3.01 seconds
Started Jul 01 06:35:22 PM PDT 24
Finished Jul 01 06:35:27 PM PDT 24
Peak memory 195368 kb
Host smart-5ae8cb79-42cb-4e4e-80ec-3497086c7e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495606153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3495606153
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.2407626539
Short name T1023
Test name
Test status
Simulation time 19248403911 ps
CPU time 751.42 seconds
Started Jul 01 06:35:21 PM PDT 24
Finished Jul 01 06:47:54 PM PDT 24
Peak memory 199920 kb
Host smart-bb5f1491-688e-4a95-8689-689db03e15ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407626539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2407626539
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.201081232
Short name T935
Test name
Test status
Simulation time 6608201441 ps
CPU time 16.48 seconds
Started Jul 01 06:35:20 PM PDT 24
Finished Jul 01 06:35:38 PM PDT 24
Peak memory 198768 kb
Host smart-873feabe-e7d6-4c49-9b62-a4705ce81ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201081232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.201081232
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.275816408
Short name T657
Test name
Test status
Simulation time 246761376137 ps
CPU time 578.9 seconds
Started Jul 01 06:35:22 PM PDT 24
Finished Jul 01 06:45:02 PM PDT 24
Peak memory 199948 kb
Host smart-2d7adc97-e36e-4491-a110-840af6e2dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275816408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.275816408
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3116342166
Short name T608
Test name
Test status
Simulation time 6039420216 ps
CPU time 1.55 seconds
Started Jul 01 06:35:19 PM PDT 24
Finished Jul 01 06:35:23 PM PDT 24
Peak memory 196532 kb
Host smart-233ac432-7ad2-4e64-97ae-9b1c05e79fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116342166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3116342166
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1425800129
Short name T429
Test name
Test status
Simulation time 299298377 ps
CPU time 1.29 seconds
Started Jul 01 06:35:16 PM PDT 24
Finished Jul 01 06:35:20 PM PDT 24
Peak memory 198948 kb
Host smart-8c5e3450-cb6d-451b-a1dc-43d57663df06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425800129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1425800129
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.163362969
Short name T964
Test name
Test status
Simulation time 177855948103 ps
CPU time 274.77 seconds
Started Jul 01 06:35:26 PM PDT 24
Finished Jul 01 06:40:03 PM PDT 24
Peak memory 200008 kb
Host smart-5e8c4ea1-eaae-44a3-970e-4019272cea3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163362969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.163362969
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.326544601
Short name T632
Test name
Test status
Simulation time 1496270207 ps
CPU time 4.93 seconds
Started Jul 01 06:35:26 PM PDT 24
Finished Jul 01 06:35:33 PM PDT 24
Peak memory 199840 kb
Host smart-415591f6-beba-478d-9bac-98e1bfb5946a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326544601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.326544601
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2748960509
Short name T467
Test name
Test status
Simulation time 293401479928 ps
CPU time 34.5 seconds
Started Jul 01 06:35:16 PM PDT 24
Finished Jul 01 06:35:53 PM PDT 24
Peak memory 199888 kb
Host smart-61431ca4-c9ca-4569-aaef-d475489788ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748960509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2748960509
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.272963834
Short name T557
Test name
Test status
Simulation time 221584030730 ps
CPU time 93.93 seconds
Started Jul 01 06:41:10 PM PDT 24
Finished Jul 01 06:42:45 PM PDT 24
Peak memory 199996 kb
Host smart-8d575c0d-84bd-488a-ba2b-580b5c87db20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272963834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.272963834
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1835551590
Short name T813
Test name
Test status
Simulation time 125290758318 ps
CPU time 46.5 seconds
Started Jul 01 06:41:11 PM PDT 24
Finished Jul 01 06:42:00 PM PDT 24
Peak memory 199768 kb
Host smart-ba876aec-857e-4a29-9845-15401e257eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835551590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1835551590
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3718776959
Short name T860
Test name
Test status
Simulation time 47165831313 ps
CPU time 282.62 seconds
Started Jul 01 06:41:10 PM PDT 24
Finished Jul 01 06:45:54 PM PDT 24
Peak memory 216584 kb
Host smart-69f56adc-393d-4ea1-a897-7c3fbea46259
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718776959 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3718776959
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.4228692859
Short name T582
Test name
Test status
Simulation time 9145313349 ps
CPU time 15.18 seconds
Started Jul 01 06:41:14 PM PDT 24
Finished Jul 01 06:41:31 PM PDT 24
Peak memory 199940 kb
Host smart-a65f5122-9b67-463a-8150-c2db4ce3b58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228692859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.4228692859
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2290922379
Short name T450
Test name
Test status
Simulation time 113233627643 ps
CPU time 39.08 seconds
Started Jul 01 06:41:12 PM PDT 24
Finished Jul 01 06:41:53 PM PDT 24
Peak memory 200004 kb
Host smart-b3595fb6-7bf7-424a-9439-8abcf3bcf207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290922379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2290922379
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.4284568738
Short name T31
Test name
Test status
Simulation time 88226132697 ps
CPU time 502.44 seconds
Started Jul 01 06:41:10 PM PDT 24
Finished Jul 01 06:49:33 PM PDT 24
Peak memory 208388 kb
Host smart-cb7ddb53-0491-4300-9143-4d01e8c434bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284568738 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.4284568738
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1658699536
Short name T332
Test name
Test status
Simulation time 118196668412 ps
CPU time 191.94 seconds
Started Jul 01 06:41:13 PM PDT 24
Finished Jul 01 06:44:27 PM PDT 24
Peak memory 199936 kb
Host smart-f5cd5c9e-9515-4d87-a922-addf1e4c4d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658699536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1658699536
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.515716680
Short name T51
Test name
Test status
Simulation time 76796130795 ps
CPU time 1104.26 seconds
Started Jul 01 06:41:10 PM PDT 24
Finished Jul 01 06:59:35 PM PDT 24
Peak memory 216436 kb
Host smart-ec5f98d1-21f8-44ff-8033-bd1ab1a60ff4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515716680 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.515716680
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.779318252
Short name T79
Test name
Test status
Simulation time 36495438623 ps
CPU time 16.9 seconds
Started Jul 01 06:41:15 PM PDT 24
Finished Jul 01 06:41:33 PM PDT 24
Peak memory 200020 kb
Host smart-c2bbf5ba-6b69-4a92-8546-579deff6dbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779318252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.779318252
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2992036101
Short name T440
Test name
Test status
Simulation time 11666945135 ps
CPU time 153.5 seconds
Started Jul 01 06:41:20 PM PDT 24
Finished Jul 01 06:43:55 PM PDT 24
Peak memory 208316 kb
Host smart-838e9095-d642-4a55-833b-2eef1105926b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992036101 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2992036101
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.63651669
Short name T654
Test name
Test status
Simulation time 15949845204 ps
CPU time 33.98 seconds
Started Jul 01 06:41:19 PM PDT 24
Finished Jul 01 06:41:54 PM PDT 24
Peak memory 199864 kb
Host smart-81693962-2a91-4e01-9a3c-1be0dd474dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63651669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.63651669
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1712086707
Short name T119
Test name
Test status
Simulation time 171156466523 ps
CPU time 58.95 seconds
Started Jul 01 06:41:21 PM PDT 24
Finished Jul 01 06:42:22 PM PDT 24
Peak memory 199832 kb
Host smart-6aed0090-3183-4483-8c75-3172ac0d80d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712086707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1712086707
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3293220211
Short name T546
Test name
Test status
Simulation time 40790178556 ps
CPU time 672.23 seconds
Started Jul 01 06:41:22 PM PDT 24
Finished Jul 01 06:52:36 PM PDT 24
Peak memory 215980 kb
Host smart-e0c69c65-7aea-477d-a58b-48eea7d16cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293220211 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3293220211
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3496557463
Short name T661
Test name
Test status
Simulation time 63764929465 ps
CPU time 227.04 seconds
Started Jul 01 06:41:19 PM PDT 24
Finished Jul 01 06:45:08 PM PDT 24
Peak memory 216008 kb
Host smart-e0619178-c710-4f3e-af7d-d9e87d69651d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496557463 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3496557463
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.4020980050
Short name T380
Test name
Test status
Simulation time 37300596 ps
CPU time 0.59 seconds
Started Jul 01 06:35:25 PM PDT 24
Finished Jul 01 06:35:28 PM PDT 24
Peak memory 195312 kb
Host smart-7511b92c-3491-420f-bc7e-67e1e1f734df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020980050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4020980050
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3553902357
Short name T139
Test name
Test status
Simulation time 113057972893 ps
CPU time 371.28 seconds
Started Jul 01 06:35:23 PM PDT 24
Finished Jul 01 06:41:36 PM PDT 24
Peak memory 199888 kb
Host smart-2a6ab32b-86c6-4fda-8ba8-b0e4396a4969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553902357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3553902357
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1370024744
Short name T768
Test name
Test status
Simulation time 278136965967 ps
CPU time 112.51 seconds
Started Jul 01 06:35:26 PM PDT 24
Finished Jul 01 06:37:21 PM PDT 24
Peak memory 199936 kb
Host smart-b81a52ce-32c6-4448-a1ca-d6e0b7facddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370024744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1370024744
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3893982822
Short name T304
Test name
Test status
Simulation time 17817906349 ps
CPU time 25.72 seconds
Started Jul 01 06:35:20 PM PDT 24
Finished Jul 01 06:35:48 PM PDT 24
Peak memory 200016 kb
Host smart-8f6ae706-dd5e-4923-a9c8-5e0da5217f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893982822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3893982822
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.661497558
Short name T434
Test name
Test status
Simulation time 19884843295 ps
CPU time 16.52 seconds
Started Jul 01 06:35:20 PM PDT 24
Finished Jul 01 06:35:38 PM PDT 24
Peak memory 197572 kb
Host smart-551a8a31-b34d-4c6a-933e-943fb7e445ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661497558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.661497558
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3800071200
Short name T726
Test name
Test status
Simulation time 289803977022 ps
CPU time 318.19 seconds
Started Jul 01 06:35:28 PM PDT 24
Finished Jul 01 06:40:48 PM PDT 24
Peak memory 200004 kb
Host smart-9c3927f8-efea-4a32-8dd4-33ca2368be60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800071200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3800071200
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4293372796
Short name T812
Test name
Test status
Simulation time 5497914065 ps
CPU time 3.1 seconds
Started Jul 01 06:35:27 PM PDT 24
Finished Jul 01 06:35:32 PM PDT 24
Peak memory 198372 kb
Host smart-31f8038a-8f21-4d14-a1ff-2657bfd6f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293372796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4293372796
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.3488940257
Short name T739
Test name
Test status
Simulation time 7050990546 ps
CPU time 375.21 seconds
Started Jul 01 06:35:28 PM PDT 24
Finished Jul 01 06:41:45 PM PDT 24
Peak memory 200048 kb
Host smart-a4990ecc-4e57-4321-b2a7-50535a1bb103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488940257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3488940257
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3365839435
Short name T453
Test name
Test status
Simulation time 2447487093 ps
CPU time 4.28 seconds
Started Jul 01 06:35:20 PM PDT 24
Finished Jul 01 06:35:26 PM PDT 24
Peak memory 197856 kb
Host smart-7bb1b5a6-81da-46dc-a7e4-850a493f3aac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365839435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3365839435
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2270461860
Short name T974
Test name
Test status
Simulation time 62881287805 ps
CPU time 42.97 seconds
Started Jul 01 06:35:27 PM PDT 24
Finished Jul 01 06:36:12 PM PDT 24
Peak memory 200064 kb
Host smart-594999fa-1c2a-44ad-9004-891adda6f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270461860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2270461860
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3512501077
Short name T905
Test name
Test status
Simulation time 30605771799 ps
CPU time 42.03 seconds
Started Jul 01 06:35:24 PM PDT 24
Finished Jul 01 06:36:08 PM PDT 24
Peak memory 196376 kb
Host smart-17e8009b-dee8-4d3d-a045-f2ffa0482167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512501077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3512501077
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2029850088
Short name T289
Test name
Test status
Simulation time 694065840 ps
CPU time 1.45 seconds
Started Jul 01 06:35:23 PM PDT 24
Finished Jul 01 06:35:26 PM PDT 24
Peak memory 198848 kb
Host smart-ede0108a-fab5-4362-8e8a-25a3c70939ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029850088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2029850088
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1337850768
Short name T939
Test name
Test status
Simulation time 35952141289 ps
CPU time 537.55 seconds
Started Jul 01 06:35:24 PM PDT 24
Finished Jul 01 06:44:24 PM PDT 24
Peak memory 216584 kb
Host smart-50e5e4b2-d242-4663-a675-b667dc2d1daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337850768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1337850768
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1845371725
Short name T1031
Test name
Test status
Simulation time 2678299400 ps
CPU time 2.59 seconds
Started Jul 01 06:35:27 PM PDT 24
Finished Jul 01 06:35:32 PM PDT 24
Peak memory 198496 kb
Host smart-bdf32b4c-84fa-47af-9558-1dc8bc249fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845371725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1845371725
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3508931039
Short name T688
Test name
Test status
Simulation time 58641944089 ps
CPU time 44.91 seconds
Started Jul 01 06:35:23 PM PDT 24
Finished Jul 01 06:36:09 PM PDT 24
Peak memory 199928 kb
Host smart-e5ce251c-175d-4cfd-aee4-2b9d5e5095b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508931039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3508931039
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1469752816
Short name T305
Test name
Test status
Simulation time 17550973841 ps
CPU time 28.4 seconds
Started Jul 01 06:41:21 PM PDT 24
Finished Jul 01 06:41:51 PM PDT 24
Peak memory 200140 kb
Host smart-7f82b525-7373-4690-b8dd-dc5e58c19a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469752816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1469752816
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.579642153
Short name T752
Test name
Test status
Simulation time 51999525234 ps
CPU time 81.18 seconds
Started Jul 01 06:41:21 PM PDT 24
Finished Jul 01 06:42:44 PM PDT 24
Peak memory 199956 kb
Host smart-51c593a1-edb1-4bcb-9bf4-b097111d077d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579642153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.579642153
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4181865209
Short name T574
Test name
Test status
Simulation time 169176386884 ps
CPU time 55.58 seconds
Started Jul 01 06:41:21 PM PDT 24
Finished Jul 01 06:42:19 PM PDT 24
Peak memory 200032 kb
Host smart-458c9cca-33b6-4a8d-9cef-d4e441292d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181865209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4181865209
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2870784198
Short name T873
Test name
Test status
Simulation time 42599781162 ps
CPU time 386.65 seconds
Started Jul 01 06:41:22 PM PDT 24
Finished Jul 01 06:47:50 PM PDT 24
Peak memory 216568 kb
Host smart-b9ee448b-558c-467a-8ff5-55f6fa0de170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870784198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2870784198
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.4191728728
Short name T722
Test name
Test status
Simulation time 22173658239 ps
CPU time 37.23 seconds
Started Jul 01 06:41:20 PM PDT 24
Finished Jul 01 06:41:59 PM PDT 24
Peak memory 199948 kb
Host smart-82a474a5-8eba-47be-bacf-27d6c0cdf448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191728728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.4191728728
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3078177268
Short name T674
Test name
Test status
Simulation time 42077501423 ps
CPU time 64.57 seconds
Started Jul 01 06:41:21 PM PDT 24
Finished Jul 01 06:42:27 PM PDT 24
Peak memory 199984 kb
Host smart-5d4d51f7-06d1-4ee4-8e0f-6a1bb6aa4821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078177268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3078177268
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.388425949
Short name T338
Test name
Test status
Simulation time 17722281779 ps
CPU time 110.82 seconds
Started Jul 01 06:41:22 PM PDT 24
Finished Jul 01 06:43:15 PM PDT 24
Peak memory 208336 kb
Host smart-eb1136eb-9215-4cb3-9a42-3faba90fbcb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388425949 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.388425949
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2870673490
Short name T205
Test name
Test status
Simulation time 51111124508 ps
CPU time 71.4 seconds
Started Jul 01 06:41:21 PM PDT 24
Finished Jul 01 06:42:34 PM PDT 24
Peak memory 200064 kb
Host smart-8b00ef0f-5f65-416e-a269-f2e7e30f0493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870673490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2870673490
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.305027252
Short name T897
Test name
Test status
Simulation time 37178025553 ps
CPU time 334.55 seconds
Started Jul 01 06:41:20 PM PDT 24
Finished Jul 01 06:46:57 PM PDT 24
Peak memory 216488 kb
Host smart-88e6c83a-5b0d-4998-9cc9-adb47db83564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305027252 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.305027252
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.647017092
Short name T868
Test name
Test status
Simulation time 67302002512 ps
CPU time 61.45 seconds
Started Jul 01 06:41:21 PM PDT 24
Finished Jul 01 06:42:24 PM PDT 24
Peak memory 199924 kb
Host smart-c361425f-f495-49c1-8c57-86d25f777d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647017092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.647017092
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.773008545
Short name T953
Test name
Test status
Simulation time 241860401334 ps
CPU time 198.76 seconds
Started Jul 01 06:41:31 PM PDT 24
Finished Jul 01 06:44:51 PM PDT 24
Peak memory 199960 kb
Host smart-b75edf01-4a79-491f-a005-35501e2d63a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773008545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.773008545
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.581669691
Short name T559
Test name
Test status
Simulation time 329238434957 ps
CPU time 320.88 seconds
Started Jul 01 06:41:29 PM PDT 24
Finished Jul 01 06:46:51 PM PDT 24
Peak memory 216500 kb
Host smart-b161009b-7c53-4835-8b1b-2e02cbcc7cef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581669691 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.581669691
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1449958664
Short name T993
Test name
Test status
Simulation time 14299472723 ps
CPU time 22.07 seconds
Started Jul 01 06:41:30 PM PDT 24
Finished Jul 01 06:41:53 PM PDT 24
Peak memory 199880 kb
Host smart-d273ddcc-d4f8-4a08-a9a3-746afdc78dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449958664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1449958664
Directory /workspace/99.uart_fifo_reset/latest
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