Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	81887	1			T1	1		T2	2		T3	1
all_values[1]	81887	1			T1	1		T2	2		T3	1
all_values[2]	81887	1			T1	1		T2	2		T3	1
all_values[3]	81887	1			T1	1		T2	2		T3	1
all_values[4]	81887	1			T1	1		T2	2		T3	1
all_values[5]	81887	1			T1	1		T2	2		T3	1
all_values[6]	81887	1			T1	1		T2	2		T3	1
all_values[7]	81887	1			T1	1		T2	2		T3	1
all_values[8]	81887	1			T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

365519

1

T1

3

T2

11

T3

5

auto[1]

371464

1

T1

6

T2

7

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659927

1

T1

7

T2

15

T3

7

auto[1]

77056

1

T1

2

T2

3

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	20820	1			T6	7		T11	17		T36	20
all_values[0]	auto[0]	auto[1]	18069	1			T1	1		T2	1		T3	1
all_values[0]	auto[1]	auto[0]	23204	1			T2	1		T6	29		T10	8
all_values[0]	auto[1]	auto[1]	19794	1			T6	91		T7	1		T8	2
all_values[1]	auto[0]	auto[0]	38477	1			T2	2		T3	1		T4	2
all_values[1]	auto[0]	auto[1]	1337	1			T35	2		T14	8		T17	9
all_values[1]	auto[1]	auto[0]	40532	1			T1	1		T6	21		T8	3
all_values[1]	auto[1]	auto[1]	1541	1			T8	1		T11	12		T35	3
all_values[2]	auto[0]	auto[0]	39511	1			T1	1		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	2201	1			T2	1		T4	1		T6	3
all_values[2]	auto[1]	auto[0]	38290	1			T2	1		T5	1		T6	46
all_values[2]	auto[1]	auto[1]	1885	1			T6	1		T8	1		T10	1
all_values[3]	auto[0]	auto[0]	44166	1			T2	1		T3	1		T4	2
all_values[3]	auto[0]	auto[1]	272	1			T10	2		T14	3		T16	1
all_values[3]	auto[1]	auto[0]	37201	1			T1	1		T2	1		T5	1
all_values[3]	auto[1]	auto[1]	248	1			T17	1		T16	2		T22	3
all_values[4]	auto[0]	auto[0]	38177	1			T2	1		T4	2		T5	1
all_values[4]	auto[0]	auto[1]	388	1			T14	12		T17	2		T16	13
all_values[4]	auto[1]	auto[0]	42976	1			T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[1]	346	1			T14	8		T17	2		T16	3
all_values[5]	auto[0]	auto[0]	39284	1			T2	2		T3	1		T4	2
all_values[5]	auto[0]	auto[1]	157	1			T17	2		T16	1		T112	9
all_values[5]	auto[1]	auto[0]	42289	1			T1	1		T6	67		T8	2
all_values[5]	auto[1]	auto[1]	157	1			T17	2		T22	1		T112	4
all_values[6]	auto[0]	auto[0]	37339	1			T1	1		T2	1		T4	2
all_values[6]	auto[0]	auto[1]	143	1			T17	2		T16	2		T22	4
all_values[6]	auto[1]	auto[0]	44262	1			T2	1		T3	1		T6	103
all_values[6]	auto[1]	auto[1]	143	1			T22	1		T112	3		T33	2
all_values[7]	auto[0]	auto[0]	42655	1			T4	2		T5	1		T6	46
all_values[7]	auto[0]	auto[1]	368	1			T14	1		T17	4		T16	11
all_values[7]	auto[1]	auto[0]	38587	1			T1	1		T2	2		T3	1
all_values[7]	auto[1]	auto[1]	277	1			T14	1		T22	4		T97	2
all_values[8]	auto[0]	auto[0]	26679	1			T2	1		T6	15		T10	8
all_values[8]	auto[0]	auto[1]	15476	1			T2	1		T4	2		T6	2
all_values[8]	auto[1]	auto[0]	25478	1			T6	24		T11	4		T12	40
all_values[8]	auto[1]	auto[1]	14254	1			T1	1		T3	1		T5	1