Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2071	1			T1	3		T2	1		T3	1
auto[BaudRate115200]	1609	1			T1	3		T2	3		T6	2
auto[BaudRate230400]	1743	1			T2	2		T6	5		T8	3
auto[BaudRate128Kbps]	1579	1			T1	6		T4	1		T6	3
auto[BaudRate256Kbps]	1865	1			T1	3		T6	7		T8	2
auto[BaudRate1Mbps]	1407	1			T2	2		T8	1		T10	3
auto[BaudRate1p5Mbps]	1096	1			T2	2		T9	1		T11	1

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1516	1			T1	15		T8	10		T307	2
freqs[25]	1062	1			T2	10		T340	5		T202	5
freqs[48]	548	1			T13	33		T15	9		T16	9
freqs[50]	440	1			T131	10		T263	5		T285	2
freqs[100]	1114	1			T5	2		T11	6		T260	8

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	239	1			T1	3		T307	1		T135	1
auto[BaudRate9600]	freqs[25]	192	1			T2	1		T340	5		T32	1
auto[BaudRate9600]	freqs[48]	101	1			T13	9		T15	1		T16	1
auto[BaudRate9600]	freqs[50]	66	1			T131	1		T341	1		T342	1
auto[BaudRate9600]	freqs[100]	183	1			T5	2		T11	1		T132	2
auto[BaudRate115200]	freqs[24]	228	1			T1	3		T8	2		T307	1
auto[BaudRate115200]	freqs[25]	120	1			T2	3		T202	1		T32	5
auto[BaudRate115200]	freqs[48]	77	1			T13	9		T16	1		T269	1
auto[BaudRate115200]	freqs[50]	64	1			T131	2		T123	2		T157	5
auto[BaudRate115200]	freqs[100]	150	1			T260	1		T132	1		T102	1
auto[BaudRate230400]	freqs[24]	240	1			T8	3		T39	1		T40	2
auto[BaudRate230400]	freqs[25]	186	1			T2	2		T32	4		T120	4
auto[BaudRate230400]	freqs[48]	85	1			T13	3		T15	2		T16	2
auto[BaudRate230400]	freqs[50]	63	1			T285	1		T123	1		T157	1
auto[BaudRate230400]	freqs[100]	142	1			T11	1		T260	3		T102	1
auto[BaudRate128Kbps]	freqs[24]	189	1			T1	6		T8	2		T135	2
auto[BaudRate128Kbps]	freqs[25]	133	1			T202	1		T32	1		T120	4
auto[BaudRate128Kbps]	freqs[48]	67	1			T13	6		T269	2		T45	1
auto[BaudRate128Kbps]	freqs[50]	50	1			T131	2		T317	1		T123	1
auto[BaudRate128Kbps]	freqs[100]	141	1			T11	1		T260	1		T132	2
auto[BaudRate256Kbps]	freqs[24]	237	1			T1	3		T8	2		T136	1
auto[BaudRate256Kbps]	freqs[25]	154	1			T202	1		T32	2		T120	3
auto[BaudRate256Kbps]	freqs[48]	67	1			T15	1		T16	2		T267	1
auto[BaudRate256Kbps]	freqs[50]	71	1			T131	3		T263	2		T333	2
auto[BaudRate256Kbps]	freqs[100]	167	1			T11	2		T102	2		T278	1
auto[BaudRate1Mbps]	freqs[24]	218	1			T8	1		T135	2		T39	1
auto[BaudRate1Mbps]	freqs[25]	196	1			T2	2		T202	1		T32	3
auto[BaudRate1Mbps]	freqs[48]	79	1			T15	2		T16	1		T269	2
auto[BaudRate1Mbps]	freqs[50]	63	1			T131	1		T263	1		T50	1
auto[BaudRate1Mbps]	freqs[100]	162	1			T132	1		T102	2		T278	1
auto[BaudRate1p5Mbps]	freqs[25]	81	1			T2	2		T202	1		T32	1
auto[BaudRate1p5Mbps]	freqs[48]	72	1			T13	6		T15	3		T16	2
auto[BaudRate1p5Mbps]	freqs[50]	63	1			T131	1		T263	2		T285	1
auto[BaudRate1p5Mbps]	freqs[100]	169	1			T11	1		T260	3		T132	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded