Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	22048710	1			T1	2		T2	18		T3	1
all_levels[1]	154757	1			T2	2		T6	1200		T11	45
all_levels[2]	1905	1			T11	9		T17	9		T16	1
all_levels[3]	889	1			T11	2		T35	2		T17	5
all_levels[4]	635	1			T15	2		T17	2		T129	2
all_levels[5]	492	1			T2	1		T11	2		T17	1
all_levels[6]	365	1			T2	1		T11	1		T16	3
all_levels[7]	327	1			T17	1		T103	2		T130	1
all_levels[8]	292	1			T11	1		T129	2		T131	1
all_levels[9]	225	1			T11	1		T132	2		T22	1
all_levels[10]	177	1			T35	1		T100	1		T133	1
all_levels[11]	181	1			T6	1		T131	2		T22	1
all_levels[12]	145	1			T132	1		T133	1		T134	1
all_levels[13]	153	1			T135	1		T131	1		T97	1
all_levels[14]	126	1			T11	1		T129	1		T136	2
all_levels[15]	131	1			T6	1		T8	1		T11	1
all_levels[16]	115	1			T35	1		T131	1		T130	1
all_levels[17]	94	1			T103	1		T130	2		T137	1
all_levels[18]	96	1			T35	1		T130	1		T136	1
all_levels[19]	92	1			T2	2		T129	1		T131	1
all_levels[20]	69	1			T134	1		T138	1		T139	1
all_levels[21]	60	1			T35	1		T140	1		T141	1
all_levels[22]	68	1			T40	1		T119	1		T140	1
all_levels[23]	52	1			T97	1		T40	2		T32	2
all_levels[24]	55	1			T11	1		T131	1		T130	1
all_levels[25]	35	1			T112	1		T138	1		T142	1
all_levels[26]	44	1			T100	1		T119	1		T143	2
all_levels[27]	50	1			T103	1		T144	2		T44	1
all_levels[28]	38	1			T145	1		T146	1		T147	1
all_levels[29]	44	1			T132	1		T148	1		T112	1
all_levels[30]	40	1			T103	1		T30	1		T140	3
all_levels[31]	26	1			T2	1		T11	1		T149	1
all_levels[32]	25	1			T35	1		T150	1		T151	1
all_levels[33]	22	1			T152	1		T153	1		T154	2
all_levels[34]	35	1			T119	1		T155	1		T156	5
all_levels[35]	18	1			T140	2		T48	1		T157	1
all_levels[36]	30	1			T8	4		T135	1		T131	1
all_levels[37]	39	1			T131	1		T145	1		T33	1
all_levels[38]	27	1			T8	1		T138	1		T157	2
all_levels[39]	25	1			T10	1		T130	1		T158	2
all_levels[40]	26	1			T132	1		T97	1		T150	2
all_levels[41]	27	1			T10	4		T120	1		T159	1
all_levels[42]	15	1			T141	1		T51	1		T160	1
all_levels[43]	16	1			T129	1		T120	1		T105	1
all_levels[44]	13	1			T161	1		T162	1		T111	1
all_levels[45]	14	1			T150	1		T163	3		T164	1
all_levels[46]	10	1			T161	1		T165	1		T166	1
all_levels[47]	16	1			T164	1		T167	1		T109	1
all_levels[48]	9	1			T155	2		T168	1		T169	1
all_levels[49]	17	1			T170	2		T141	1		T171	1
all_levels[50]	6	1			T172	1		T173	1		T174	1
all_levels[51]	8	1			T137	1		T151	1		T159	1
all_levels[52]	9	1			T149	1		T175	1		T166	1
all_levels[53]	7	1			T141	1		T151	1		T147	1
all_levels[54]	7	1			T6	1		T129	1		T176	1
all_levels[55]	9	1			T97	1		T177	1		T114	1
all_levels[56]	12	1			T178	2		T179	1		T180	1
all_levels[57]	16	1			T137	1		T141	1		T149	2
all_levels[58]	8	1			T164	1		T181	1		T182	3
all_levels[59]	4	1			T159	1		T51	1		T183	1
all_levels[60]	7	1			T152	1		T121	3		T184	1
all_levels[61]	6	1			T120	1		T185	1		T186	1
all_levels[62]	10	1			T120	1		T187	1		T160	2
all_levels[63]	5	1			T109	1		T188	1		T189	1
all_levels[64]	98	1			T144	1		T142	3		T190	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22206577

1

T2

18

T6

58302

T8

10

auto[1]

4507

1

T1

2

T2

7

T3

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[50] , all_levels[51] , all_levels[52] , all_levels[53] , all_levels[54] , all_levels[55]]	[auto[1]]	--	--	6
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	22044697	1			T2	12		T6	57099		T8	7
all_levels[0]	auto[1]	4013	1			T1	2		T2	6		T3	1
all_levels[1]	auto[0]	154678	1			T2	2		T6	1200		T11	45
all_levels[1]	auto[1]	79	1			T103	1		T191	1		T120	1
all_levels[2]	auto[0]	1866	1			T11	9		T17	9		T16	1
all_levels[2]	auto[1]	39	1			T137	1		T119	1		T192	2
all_levels[3]	auto[0]	877	1			T11	2		T35	1		T17	5
all_levels[3]	auto[1]	12	1			T35	1		T120	1		T193	1
all_levels[4]	auto[0]	606	1			T15	1		T17	2		T129	2
all_levels[4]	auto[1]	29	1			T15	1		T116	2		T42	4
all_levels[5]	auto[0]	474	1			T2	1		T11	1		T17	1
all_levels[5]	auto[1]	18	1			T11	1		T103	1		T40	1
all_levels[6]	auto[0]	351	1			T2	1		T11	1		T16	3
all_levels[6]	auto[1]	14	1			T194	1		T195	1		T114	2
all_levels[7]	auto[0]	317	1			T17	1		T103	2		T130	1
all_levels[7]	auto[1]	10	1			T145	1		T196	1		T172	1
all_levels[8]	auto[0]	270	1			T11	1		T129	2		T131	1
all_levels[8]	auto[1]	22	1			T145	1		T197	2		T198	1
all_levels[9]	auto[0]	199	1			T11	1		T132	2		T22	1
all_levels[9]	auto[1]	26	1			T170	1		T151	1		T152	1
all_levels[10]	auto[0]	171	1			T35	1		T100	1		T133	1
all_levels[10]	auto[1]	6	1			T174	1		T199	2		T200	1
all_levels[11]	auto[0]	169	1			T6	1		T131	2		T22	1
all_levels[11]	auto[1]	12	1			T170	1		T160	1		T201	2
all_levels[12]	auto[0]	126	1			T132	1		T133	1		T134	1
all_levels[12]	auto[1]	19	1			T202	1		T203	1		T121	4
all_levels[13]	auto[0]	144	1			T135	1		T131	1		T97	1
all_levels[13]	auto[1]	9	1			T153	1		T69	1		T172	1
all_levels[14]	auto[0]	114	1			T11	1		T129	1		T136	1
all_levels[14]	auto[1]	12	1			T136	1		T144	2		T204	1
all_levels[15]	auto[0]	117	1			T6	1		T8	1		T11	1
all_levels[15]	auto[1]	14	1			T151	2		T205	1		T206	2
all_levels[16]	auto[0]	108	1			T35	1		T131	1		T130	1
all_levels[16]	auto[1]	7	1			T207	3		T208	1		T209	1
all_levels[17]	auto[0]	85	1			T103	1		T130	2		T137	1
all_levels[17]	auto[1]	9	1			T210	1		T119	1		T211	1
all_levels[18]	auto[0]	93	1			T35	1		T130	1		T136	1
all_levels[18]	auto[1]	3	1			T212	1		T213	1		T214	1
all_levels[19]	auto[0]	84	1			T2	1		T129	1		T131	1
all_levels[19]	auto[1]	8	1			T2	1		T215	1		T216	5
all_levels[20]	auto[0]	67	1			T134	1		T138	1		T139	1
all_levels[20]	auto[1]	2	1			T180	1		T217	1		-	-
all_levels[21]	auto[0]	53	1			T35	1		T140	1		T141	1
all_levels[21]	auto[1]	7	1			T163	1		T218	3		T219	1
all_levels[22]	auto[0]	62	1			T40	1		T119	1		T140	1
all_levels[22]	auto[1]	6	1			T162	1		T220	2		T221	1
all_levels[23]	auto[0]	51	1			T97	1		T40	2		T32	2
all_levels[23]	auto[1]	1	1			T222	1		-	-		-	-
all_levels[24]	auto[0]	49	1			T11	1		T131	1		T130	1
all_levels[24]	auto[1]	6	1			T223	4		T224	1		T225	1
all_levels[25]	auto[0]	31	1			T112	1		T138	1		T142	1
all_levels[25]	auto[1]	4	1			T226	1		T227	3		-	-
all_levels[26]	auto[0]	41	1			T100	1		T119	1		T143	1
all_levels[26]	auto[1]	3	1			T143	1		T193	1		T228	1
all_levels[27]	auto[0]	43	1			T103	1		T144	1		T44	1
all_levels[27]	auto[1]	7	1			T144	1		T217	1		T111	4
all_levels[28]	auto[0]	36	1			T145	1		T146	1		T147	1
all_levels[28]	auto[1]	2	1			T229	1		T230	1		-	-
all_levels[29]	auto[0]	39	1			T132	1		T148	1		T112	1
all_levels[29]	auto[1]	5	1			T231	1		T232	1		T233	3
all_levels[30]	auto[0]	30	1			T103	1		T30	1		T140	3
all_levels[30]	auto[1]	10	1			T234	1		T114	2		T235	2
all_levels[31]	auto[0]	24	1			T2	1		T11	1		T149	1
all_levels[31]	auto[1]	2	1			T236	2		-	-		-	-
all_levels[32]	auto[0]	23	1			T35	1		T150	1		T151	1
all_levels[32]	auto[1]	2	1			T237	2		-	-		-	-
all_levels[33]	auto[0]	15	1			T152	1		T153	1		T154	1
all_levels[33]	auto[1]	7	1			T154	1		T238	6		-	-
all_levels[34]	auto[0]	23	1			T119	1		T155	1		T156	1
all_levels[34]	auto[1]	12	1			T156	4		T223	2		T239	2
all_levels[35]	auto[0]	17	1			T140	1		T48	1		T157	1
all_levels[35]	auto[1]	1	1			T140	1		-	-		-	-
all_levels[36]	auto[0]	24	1			T8	1		T135	1		T131	1
all_levels[36]	auto[1]	6	1			T8	3		T240	1		T241	1
all_levels[37]	auto[0]	35	1			T131	1		T145	1		T33	1
all_levels[37]	auto[1]	4	1			T161	2		T242	1		T243	1
all_levels[38]	auto[0]	23	1			T8	1		T138	1		T157	2
all_levels[38]	auto[1]	4	1			T198	2		T244	2		-	-
all_levels[39]	auto[0]	23	1			T10	1		T130	1		T158	1
all_levels[39]	auto[1]	2	1			T158	1		T245	1		-	-
all_levels[40]	auto[0]	20	1			T132	1		T97	1		T150	1
all_levels[40]	auto[1]	6	1			T150	1		T246	3		T247	2
all_levels[41]	auto[0]	22	1			T10	1		T120	1		T159	1
all_levels[41]	auto[1]	5	1			T10	3		T248	1		T249	1
all_levels[42]	auto[0]	13	1			T141	1		T51	1		T160	1
all_levels[42]	auto[1]	2	1			T250	2		-	-		-	-
all_levels[43]	auto[0]	14	1			T129	1		T120	1		T105	1
all_levels[43]	auto[1]	2	1			T121	1		T248	1		-	-
all_levels[44]	auto[0]	13	1			T161	1		T162	1		T111	1
all_levels[45]	auto[0]	9	1			T150	1		T163	1		T164	1
all_levels[45]	auto[1]	5	1			T163	2		T251	3		-	-
all_levels[46]	auto[0]	10	1			T161	1		T165	1		T166	1
all_levels[47]	auto[0]	11	1			T164	1		T167	1		T109	1
all_levels[47]	auto[1]	5	1			T208	1		T252	1		T253	1
all_levels[48]	auto[0]	7	1			T155	1		T168	1		T169	1
all_levels[48]	auto[1]	2	1			T155	1		T254	1		-	-
all_levels[49]	auto[0]	16	1			T170	1		T141	1		T171	1
all_levels[49]	auto[1]	1	1			T170	1		-	-		-	-
all_levels[50]	auto[0]	6	1			T172	1		T173	1		T174	1
all_levels[51]	auto[0]	8	1			T137	1		T151	1		T159	1
all_levels[52]	auto[0]	9	1			T149	1		T175	1		T166	1
all_levels[53]	auto[0]	7	1			T141	1		T151	1		T147	1
all_levels[54]	auto[0]	7	1			T6	1		T129	1		T176	1
all_levels[55]	auto[0]	9	1			T97	1		T177	1		T114	1
all_levels[56]	auto[0]	10	1			T178	1		T179	1		T180	1
all_levels[56]	auto[1]	2	1			T178	1		T255	1		-	-
all_levels[57]	auto[0]	15	1			T137	1		T141	1		T149	2
all_levels[57]	auto[1]	1	1			T256	1		-	-		-	-
all_levels[58]	auto[0]	6	1			T164	1		T181	1		T182	1
all_levels[58]	auto[1]	2	1			T182	2		-	-		-	-
all_levels[59]	auto[0]	4	1			T159	1		T51	1		T183	1
all_levels[60]	auto[0]	5	1			T152	1		T121	1		T184	1
all_levels[60]	auto[1]	2	1			T121	2		-	-		-	-
all_levels[61]	auto[0]	5	1			T120	1		T185	1		T186	1
all_levels[61]	auto[1]	1	1			T257	1		-	-		-	-
all_levels[62]	auto[0]	9	1			T120	1		T187	1		T160	1
all_levels[62]	auto[1]	1	1			T160	1		-	-		-	-
all_levels[63]	auto[0]	5	1			T109	1		T188	1		T189	1
all_levels[64]	auto[0]	82	1			T144	1		T142	2		T190	1
all_levels[64]	auto[1]	16	1			T142	1		T258	1		T259	1