Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	81887	1			T1	1		T2	2		T3	1
all_pins[1]	81887	1			T1	1		T2	2		T3	1
all_pins[2]	81887	1			T1	1		T2	2		T3	1
all_pins[3]	81887	1			T1	1		T2	2		T3	1
all_pins[4]	81887	1			T1	1		T2	2		T3	1
all_pins[5]	81887	1			T1	1		T2	2		T3	1
all_pins[6]	81887	1			T1	1		T2	2		T3	1
all_pins[7]	81887	1			T1	1		T2	2		T3	1
all_pins[8]	81887	1			T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	697619	1			T1	8		T2	18		T3	8
values[0x1]	39364	1			T1	1		T3	1		T5	1
transitions[0x0=>0x1]	30339	1			T6	95		T7	1		T8	7
transitions[0x1=>0x0]	30154	1			T1	1		T3	1		T5	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	62018	1			T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	19869	1			T6	91		T7	1		T8	2
all_pins[0]	transitions[0x0=>0x1]	19246	1			T6	91		T7	1		T8	2
all_pins[0]	transitions[0x1=>0x0]	913	1			T8	1		T11	12		T35	1
all_pins[1]	values[0x0]	80351	1			T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	1536	1			T8	1		T11	12		T35	3
all_pins[1]	transitions[0x0=>0x1]	1433	1			T8	1		T11	12		T35	3
all_pins[1]	transitions[0x1=>0x0]	1837	1			T6	1		T8	1		T10	1
all_pins[2]	values[0x0]	79947	1			T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	1940	1			T6	1		T8	1		T10	1
all_pins[2]	transitions[0x0=>0x1]	1894	1			T6	1		T8	1		T10	1
all_pins[2]	transitions[0x1=>0x0]	202	1			T17	1		T16	2		T22	2
all_pins[3]	values[0x0]	81639	1			T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	248	1			T17	1		T16	2		T22	3
all_pins[3]	transitions[0x0=>0x1]	213	1			T17	1		T22	2		T122	2
all_pins[3]	transitions[0x1=>0x0]	311	1			T14	8		T17	2		T16	1
all_pins[4]	values[0x0]	81541	1			T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	346	1			T14	8		T17	2		T16	3
all_pins[4]	transitions[0x0=>0x1]	284	1			T14	8		T17	2		T16	3
all_pins[4]	transitions[0x1=>0x0]	126	1			T17	2		T16	2		T112	3
all_pins[5]	values[0x0]	81699	1			T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	188	1			T17	2		T16	2		T22	1
all_pins[5]	transitions[0x0=>0x1]	148	1			T17	2		T16	2		T22	1
all_pins[5]	transitions[0x1=>0x0]	611	1			T10	2		T35	3		T16	1
all_pins[6]	values[0x0]	81236	1			T1	1		T2	2		T3	1
all_pins[6]	values[0x1]	651	1			T10	2		T35	3		T16	1
all_pins[6]	transitions[0x0=>0x1]	610	1			T10	2		T35	3		T16	1
all_pins[6]	transitions[0x1=>0x0]	236	1			T14	1		T22	4		T97	2
all_pins[7]	values[0x0]	81610	1			T1	1		T2	2		T3	1
all_pins[7]	values[0x1]	277	1			T14	1		T22	4		T97	2
all_pins[7]	transitions[0x0=>0x1]	151	1			T22	1		T97	2		T130	2
all_pins[7]	transitions[0x1=>0x0]	14183	1			T1	1		T3	1		T5	1
all_pins[8]	values[0x0]	67578	1			T2	2		T4	2		T6	41
all_pins[8]	values[0x1]	14309	1			T1	1		T3	1		T5	1
all_pins[8]	transitions[0x0=>0x1]	6360	1			T6	3		T8	3		T11	3
all_pins[8]	transitions[0x1=>0x0]	11735	1			T6	4		T10	16		T11	1