Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6477011	1			T2	4		T5	1		T6	32541
all_levels[1]	1302157	1			T6	1022		T12	429		T36	62
all_levels[2]	249342	1			T6	1004		T12	429		T36	64
all_levels[3]	151040	1			T6	472		T12	426		T36	67
all_levels[4]	191714	1			T6	471		T12	426		T36	66
all_levels[5]	135854	1			T6	471		T12	430		T35	1
all_levels[6]	137500	1			T6	473		T12	429		T36	64
all_levels[7]	298088	1			T2	4		T6	440		T12	429
all_levels[8]	163116	1			T6	136		T11	3		T12	430
all_levels[9]	131780	1			T6	91		T10	2		T12	429
all_levels[10]	161209	1			T6	78		T12	430		T36	73
all_levels[11]	129865	1			T6	21		T10	2		T11	5
all_levels[12]	195609	1			T6	16		T11	3		T12	429
all_levels[13]	145966	1			T6	20		T12	429		T35	2
all_levels[14]	127762	1			T6	21		T12	428		T36	59
all_levels[15]	237994	1			T2	1		T6	18		T10	1
all_levels[16]	355737	1			T2	4		T6	19		T12	429
all_levels[17]	126900	1			T6	21		T12	424		T36	72
all_levels[18]	146638	1			T6	20		T12	419		T36	65
all_levels[19]	274335	1			T6	21		T12	422		T36	72
all_levels[20]	126083	1			T6	21		T12	429		T36	62
all_levels[21]	112398	1			T6	22		T8	3		T10	2
all_levels[22]	190905	1			T6	25		T12	428		T36	65
all_levels[23]	99646	1			T6	22		T12	428		T36	80
all_levels[24]	106085	1			T6	23		T12	430		T36	71
all_levels[25]	106410	1			T6	18		T12	422		T35	2
all_levels[26]	108855	1			T6	22		T10	1		T12	427
all_levels[27]	119860	1			T2	1		T6	22		T12	430
all_levels[28]	139484	1			T6	22		T12	420		T36	70
all_levels[29]	269611	1			T6	23		T12	429		T36	76
all_levels[30]	320933	1			T2	3		T6	24		T12	430
all_levels[31]	336116	1			T2	4		T6	361		T12	528
all_levels[32]	9034672	1			T2	8		T6	20325		T8	10

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22206577

1

T2

18

T6

58302

T8

10

auto[1]

4098

1

T2

11

T5

1

T6

4

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6474751	1			T2	2		T6	32541		T8	3
all_levels[0]	auto[1]	2260	1			T2	2		T5	1		T7	1
all_levels[1]	auto[0]	1301893	1			T6	1020		T12	429		T36	62
all_levels[1]	auto[1]	264	1			T6	2		T103	1		T191	4
all_levels[2]	auto[0]	249290	1			T6	1004		T12	429		T36	64
all_levels[2]	auto[1]	52	1			T210	1		T150	2		T178	1
all_levels[3]	auto[0]	150927	1			T6	472		T12	426		T36	67
all_levels[3]	auto[1]	113	1			T22	4		T21	4		T268	1
all_levels[4]	auto[0]	191686	1			T6	471		T12	426		T36	66
all_levels[4]	auto[1]	28	1			T15	4		T131	1		T136	2
all_levels[5]	auto[0]	135837	1			T6	471		T12	430		T35	1
all_levels[5]	auto[1]	17	1			T304	1		T178	1		T121	1
all_levels[6]	auto[0]	137468	1			T6	473		T12	429		T36	64
all_levels[6]	auto[1]	32	1			T142	1		T49	1		T346	2
all_levels[7]	auto[0]	297908	1			T2	3		T6	440		T12	429
all_levels[7]	auto[1]	180	1			T2	1		T39	1		T98	2
all_levels[8]	auto[0]	163103	1			T6	136		T11	2		T12	430
all_levels[8]	auto[1]	13	1			T11	1		T269	1		T271	1
all_levels[9]	auto[0]	131765	1			T6	91		T10	2		T12	429
all_levels[9]	auto[1]	15	1			T218	1		T347	1		T348	1
all_levels[10]	auto[0]	161187	1			T6	78		T12	430		T36	73
all_levels[10]	auto[1]	22	1			T103	3		T336	1		T196	1
all_levels[11]	auto[0]	129841	1			T6	21		T10	2		T11	5
all_levels[11]	auto[1]	24	1			T231	1		T338	1		T259	1
all_levels[12]	auto[0]	195585	1			T6	16		T11	3		T12	429
all_levels[12]	auto[1]	24	1			T133	1		T264	2		T194	1
all_levels[13]	auto[0]	145941	1			T6	20		T12	429		T35	1
all_levels[13]	auto[1]	25	1			T35	1		T33	1		T151	1
all_levels[14]	auto[0]	127737	1			T6	21		T12	428		T36	59
all_levels[14]	auto[1]	25	1			T17	1		T349	2		T341	1
all_levels[15]	auto[0]	237872	1			T2	1		T6	18		T10	1
all_levels[15]	auto[1]	122	1			T115	5		T120	4		T138	1
all_levels[16]	auto[0]	355708	1			T2	2		T6	19		T12	429
all_levels[16]	auto[1]	29	1			T2	2		T120	1		T155	1
all_levels[17]	auto[0]	126884	1			T6	21		T12	424		T36	72
all_levels[17]	auto[1]	16	1			T202	2		T271	2		T196	1
all_levels[18]	auto[0]	146624	1			T6	19		T12	419		T36	65
all_levels[18]	auto[1]	14	1			T6	1		T144	1		T198	3
all_levels[19]	auto[0]	274323	1			T6	21		T12	422		T36	72
all_levels[19]	auto[1]	12	1			T275	2		T350	2		T351	1
all_levels[20]	auto[0]	126064	1			T6	21		T12	429		T36	62
all_levels[20]	auto[1]	19	1			T137	1		T272	1		T180	3
all_levels[21]	auto[0]	112375	1			T6	22		T8	2		T10	2
all_levels[21]	auto[1]	23	1			T8	1		T156	1		T284	4
all_levels[22]	auto[0]	190891	1			T6	25		T12	428		T36	65
all_levels[22]	auto[1]	14	1			T310	1		T153	1		T197	1
all_levels[23]	auto[0]	99631	1			T6	22		T12	428		T36	80
all_levels[23]	auto[1]	15	1			T98	2		T103	2		T293	1
all_levels[24]	auto[0]	106073	1			T6	23		T12	430		T36	71
all_levels[24]	auto[1]	12	1			T153	1		T352	1		T195	2
all_levels[25]	auto[0]	106394	1			T6	18		T12	422		T35	2
all_levels[25]	auto[1]	16	1			T15	2		T150	1		T194	1
all_levels[26]	auto[0]	108838	1			T6	22		T10	1		T12	427
all_levels[26]	auto[1]	17	1			T191	1		T163	2		T152	2
all_levels[27]	auto[0]	119839	1			T2	1		T6	22		T12	430
all_levels[27]	auto[1]	21	1			T140	1		T326	1		T346	2
all_levels[28]	auto[0]	139462	1			T6	22		T12	420		T36	70
all_levels[28]	auto[1]	22	1			T269	1		T143	1		T206	3
all_levels[29]	auto[0]	269592	1			T6	23		T12	429		T36	76
all_levels[29]	auto[1]	19	1			T137	1		T155	1		T353	1
all_levels[30]	auto[0]	320911	1			T2	1		T6	24		T12	430
all_levels[30]	auto[1]	22	1			T2	2		T116	1		T298	1
all_levels[31]	auto[0]	336103	1			T2	2		T6	361		T12	528
all_levels[31]	auto[1]	13	1			T2	2		T140	1		T152	1
all_levels[32]	auto[0]	9034074	1			T2	6		T6	20324		T8	5
all_levels[32]	auto[1]	598	1			T2	2		T6	1		T8	5