Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	630	1			T17	4		T16	7		T22	11
all_values[1]	630	1			T17	4		T16	7		T22	11
all_values[2]	630	1			T17	4		T16	7		T22	11
all_values[3]	630	1			T17	4		T16	7		T22	11
all_values[4]	630	1			T17	4		T16	7		T22	11
all_values[5]	630	1			T17	4		T16	7		T22	11
all_values[6]	630	1			T17	4		T16	7		T22	11
all_values[7]	630	1			T17	4		T16	7		T22	11
all_values[8]	630	1			T17	4		T16	7		T22	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3089

1

T17

17

T16

34

T22

58

auto[1]

2581

1

T17

19

T16

29

T22

41

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1857

1

T17

9

T16

21

T22

39

auto[1]

3813

1

T17

27

T16

42

T22

60

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3389

1

T17

21

T16

38

T22

65

auto[1]

2281

1

T17

15

T16

25

T22

34

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	189	1			T17	2		T16	1		T22	4
all_values[0]	auto[0]	auto[1]	auto[1]	189	1			T17	1		T16	3		T22	2
all_values[0]	auto[1]	auto[0]	auto[1]	152	1			T16	2		T22	5		T29	2
all_values[0]	auto[1]	auto[1]	auto[1]	100	1			T17	1		T16	1		T112	2
all_values[1]	auto[0]	auto[0]	auto[0]	211	1			T16	3		T22	6		T29	2
all_values[1]	auto[0]	auto[1]	auto[0]	178	1			T17	2		T16	1		T22	2
all_values[1]	auto[1]	auto[0]	auto[1]	135	1			T17	1		T16	1		T22	2
all_values[1]	auto[1]	auto[1]	auto[1]	106	1			T17	1		T16	2		T22	1
all_values[2]	auto[0]	auto[0]	auto[0]	121	1			T22	2		T29	1		T112	1
all_values[2]	auto[0]	auto[0]	auto[1]	73	1			T16	1		T22	3		T112	1
all_values[2]	auto[0]	auto[1]	auto[0]	100	1			T17	2		T16	4		T22	1
all_values[2]	auto[0]	auto[1]	auto[1]	60	1			T22	1		T112	2		T33	2
all_values[2]	auto[1]	auto[0]	auto[1]	153	1			T17	2		T22	2		T112	3
all_values[2]	auto[1]	auto[1]	auto[1]	123	1			T16	2		T22	2		T112	2
all_values[3]	auto[0]	auto[0]	auto[0]	153	1			T16	3		T22	3		T29	2
all_values[3]	auto[0]	auto[0]	auto[1]	66	1			T112	1		T32	2		T33	2
all_values[3]	auto[0]	auto[1]	auto[0]	112	1			T17	3		T22	4		T29	2
all_values[3]	auto[0]	auto[1]	auto[1]	57	1			T16	1		T22	1		T112	1
all_values[3]	auto[1]	auto[0]	auto[1]	142	1			T17	1		T16	1		T22	2
all_values[3]	auto[1]	auto[1]	auto[1]	100	1			T16	2		T22	1		T112	2
all_values[4]	auto[0]	auto[0]	auto[0]	152	1			T16	1		T22	1		T29	1
all_values[4]	auto[0]	auto[0]	auto[1]	70	1			T17	1		T16	1		T22	3
all_values[4]	auto[0]	auto[1]	auto[0]	92	1			T17	1		T22	2		T29	1
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T16	2		T112	2		T32	1
all_values[4]	auto[1]	auto[0]	auto[1]	132	1			T17	1		T16	3		T22	2
all_values[4]	auto[1]	auto[1]	auto[1]	118	1			T17	1		T22	3		T112	2
all_values[5]	auto[0]	auto[0]	auto[0]	129	1			T16	2		T22	3		T29	1
all_values[5]	auto[0]	auto[0]	auto[1]	64	1			T17	1		T16	1		T112	7
all_values[5]	auto[0]	auto[1]	auto[0]	102	1			T16	2		T22	6		T29	2
all_values[5]	auto[0]	auto[1]	auto[1]	66	1			T17	1		T112	3		T33	1
all_values[5]	auto[1]	auto[0]	auto[1]	156	1			T17	2		T16	2		T22	1
all_values[5]	auto[1]	auto[1]	auto[1]	113	1			T22	1		T112	3		T30	1
all_values[6]	auto[0]	auto[0]	auto[0]	157	1			T17	1		T16	2		T22	1
all_values[6]	auto[0]	auto[0]	auto[1]	66	1			T17	2		T16	1		T22	1
all_values[6]	auto[0]	auto[1]	auto[0]	109	1			T16	1		T22	4		T112	5
all_values[6]	auto[0]	auto[1]	auto[1]	56	1			T112	1		T33	1		T124	2
all_values[6]	auto[1]	auto[0]	auto[1]	122	1			T16	1		T22	3		T29	2
all_values[6]	auto[1]	auto[1]	auto[1]	120	1			T17	1		T16	2		T22	2
all_values[7]	auto[0]	auto[0]	auto[0]	122	1			T16	1		T22	3		T29	1
all_values[7]	auto[0]	auto[0]	auto[1]	57	1			T17	2		T16	1		T22	1
all_values[7]	auto[0]	auto[1]	auto[0]	119	1			T16	1		T22	1		T112	5
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T22	1		T29	1		T112	2
all_values[7]	auto[1]	auto[0]	auto[1]	136	1			T17	1		T16	3		T22	3
all_values[7]	auto[1]	auto[1]	auto[1]	119	1			T17	1		T16	1		T22	2
all_values[8]	auto[0]	auto[0]	auto[1]	194	1			T16	2		T22	5		T29	1
all_values[8]	auto[0]	auto[1]	auto[1]	182	1			T17	2		T16	3		T22	4
all_values[8]	auto[1]	auto[0]	auto[1]	137	1			T16	1		T22	2		T29	1
all_values[8]	auto[1]	auto[1]	auto[1]	117	1			T17	2		T16	1		T112	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal