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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.55


Total test records in report: 1219
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T1038 /workspace/coverage/default/41.uart_smoke.2255954830 Jul 02 09:24:54 AM PDT 24 Jul 02 09:25:03 AM PDT 24 6061673910 ps
T1039 /workspace/coverage/default/46.uart_rx_oversample.2555378398 Jul 02 09:25:18 AM PDT 24 Jul 02 09:26:22 AM PDT 24 7073078713 ps
T1040 /workspace/coverage/default/40.uart_rx_start_bit_filter.1431954323 Jul 02 09:24:51 AM PDT 24 Jul 02 09:24:54 AM PDT 24 3063651311 ps
T1041 /workspace/coverage/default/47.uart_fifo_overflow.2803026952 Jul 02 09:25:23 AM PDT 24 Jul 02 09:26:02 AM PDT 24 50564454787 ps
T1042 /workspace/coverage/default/37.uart_rx_parity_err.308197960 Jul 02 09:24:41 AM PDT 24 Jul 02 09:24:57 AM PDT 24 9085409325 ps
T1043 /workspace/coverage/default/32.uart_rx_oversample.690725155 Jul 02 09:24:20 AM PDT 24 Jul 02 09:24:25 AM PDT 24 5397635547 ps
T227 /workspace/coverage/default/251.uart_fifo_reset.901224220 Jul 02 09:26:50 AM PDT 24 Jul 02 09:27:31 AM PDT 24 49101738441 ps
T1044 /workspace/coverage/default/170.uart_fifo_reset.3323550086 Jul 02 09:26:23 AM PDT 24 Jul 02 09:27:27 AM PDT 24 39823020014 ps
T1045 /workspace/coverage/default/42.uart_rx_parity_err.1472895176 Jul 02 09:25:04 AM PDT 24 Jul 02 09:25:15 AM PDT 24 23135014809 ps
T1046 /workspace/coverage/default/25.uart_stress_all.2741020974 Jul 02 09:23:55 AM PDT 24 Jul 02 09:26:04 AM PDT 24 74757676091 ps
T1047 /workspace/coverage/default/13.uart_long_xfer_wo_dly.2737883633 Jul 02 09:23:20 AM PDT 24 Jul 02 09:37:46 AM PDT 24 127482803065 ps
T1048 /workspace/coverage/default/4.uart_long_xfer_wo_dly.892267957 Jul 02 09:23:11 AM PDT 24 Jul 02 09:29:20 AM PDT 24 135517433588 ps
T1049 /workspace/coverage/default/18.uart_long_xfer_wo_dly.3695845922 Jul 02 09:23:30 AM PDT 24 Jul 02 09:27:30 AM PDT 24 156351556800 ps
T254 /workspace/coverage/default/198.uart_fifo_reset.832635725 Jul 02 09:26:33 AM PDT 24 Jul 02 09:26:42 AM PDT 24 12874004221 ps
T1050 /workspace/coverage/default/14.uart_rx_parity_err.3603384120 Jul 02 09:23:23 AM PDT 24 Jul 02 09:23:51 AM PDT 24 15488904786 ps
T1051 /workspace/coverage/default/3.uart_tx_ovrd.3919115874 Jul 02 09:23:00 AM PDT 24 Jul 02 09:23:22 AM PDT 24 13869834064 ps
T1052 /workspace/coverage/default/24.uart_fifo_overflow.2530551150 Jul 02 09:23:55 AM PDT 24 Jul 02 09:25:58 AM PDT 24 141426663574 ps
T1053 /workspace/coverage/default/2.uart_perf.2526634838 Jul 02 09:22:51 AM PDT 24 Jul 02 09:30:25 AM PDT 24 7741617117 ps
T1054 /workspace/coverage/default/31.uart_fifo_full.2012050787 Jul 02 09:24:15 AM PDT 24 Jul 02 09:26:22 AM PDT 24 87644211429 ps
T1055 /workspace/coverage/default/35.uart_fifo_full.941312507 Jul 02 09:24:32 AM PDT 24 Jul 02 09:24:48 AM PDT 24 38670003190 ps
T1056 /workspace/coverage/default/122.uart_fifo_reset.965647346 Jul 02 09:26:07 AM PDT 24 Jul 02 09:26:33 AM PDT 24 17573259956 ps
T1057 /workspace/coverage/default/148.uart_fifo_reset.3162125251 Jul 02 09:26:17 AM PDT 24 Jul 02 09:26:40 AM PDT 24 31475783185 ps
T1058 /workspace/coverage/default/46.uart_stress_all.2159691304 Jul 02 09:25:21 AM PDT 24 Jul 02 09:26:51 AM PDT 24 54608925673 ps
T1059 /workspace/coverage/default/36.uart_rx_oversample.3712400281 Jul 02 09:24:37 AM PDT 24 Jul 02 09:25:22 AM PDT 24 5303265444 ps
T1060 /workspace/coverage/default/11.uart_fifo_reset.1397117576 Jul 02 09:23:19 AM PDT 24 Jul 02 09:23:52 AM PDT 24 17432612481 ps
T1061 /workspace/coverage/default/4.uart_rx_start_bit_filter.3554314644 Jul 02 09:22:59 AM PDT 24 Jul 02 09:23:12 AM PDT 24 32859438536 ps
T1062 /workspace/coverage/default/42.uart_fifo_overflow.2745443780 Jul 02 09:24:59 AM PDT 24 Jul 02 09:29:32 AM PDT 24 152226962500 ps
T1063 /workspace/coverage/default/15.uart_tx_ovrd.4169920491 Jul 02 09:23:20 AM PDT 24 Jul 02 09:23:26 AM PDT 24 545873918 ps
T1064 /workspace/coverage/default/157.uart_fifo_reset.1576644651 Jul 02 09:26:19 AM PDT 24 Jul 02 09:26:30 AM PDT 24 9892507104 ps
T1065 /workspace/coverage/default/0.uart_rx_start_bit_filter.3756222643 Jul 02 09:22:43 AM PDT 24 Jul 02 09:22:44 AM PDT 24 541239264 ps
T1066 /workspace/coverage/default/25.uart_alert_test.1521191373 Jul 02 09:23:57 AM PDT 24 Jul 02 09:23:58 AM PDT 24 34552443 ps
T1067 /workspace/coverage/default/1.uart_fifo_overflow.1202730157 Jul 02 09:22:52 AM PDT 24 Jul 02 09:23:13 AM PDT 24 23270253751 ps
T1068 /workspace/coverage/default/79.uart_stress_all_with_rand_reset.4069667265 Jul 02 09:25:48 AM PDT 24 Jul 02 09:35:49 AM PDT 24 418974809758 ps
T1069 /workspace/coverage/default/47.uart_intr.4087288064 Jul 02 09:25:21 AM PDT 24 Jul 02 09:25:44 AM PDT 24 20597187693 ps
T1070 /workspace/coverage/default/11.uart_tx_rx.3153998307 Jul 02 09:23:16 AM PDT 24 Jul 02 09:23:21 AM PDT 24 1288613020 ps
T1071 /workspace/coverage/default/24.uart_fifo_full.43135107 Jul 02 09:24:02 AM PDT 24 Jul 02 09:24:16 AM PDT 24 33965210054 ps
T1072 /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3186756717 Jul 02 09:23:19 AM PDT 24 Jul 02 09:35:18 AM PDT 24 765519703762 ps
T1073 /workspace/coverage/default/13.uart_loopback.1275947878 Jul 02 09:23:19 AM PDT 24 Jul 02 09:23:30 AM PDT 24 10798545329 ps
T1074 /workspace/coverage/default/43.uart_rx_parity_err.3992731452 Jul 02 09:25:06 AM PDT 24 Jul 02 09:25:33 AM PDT 24 28772174494 ps
T1075 /workspace/coverage/default/28.uart_alert_test.3894883106 Jul 02 09:24:10 AM PDT 24 Jul 02 09:24:11 AM PDT 24 26002289 ps
T1076 /workspace/coverage/default/284.uart_fifo_reset.3662052348 Jul 02 09:27:03 AM PDT 24 Jul 02 09:28:34 AM PDT 24 117034685989 ps
T245 /workspace/coverage/default/127.uart_fifo_reset.1059825558 Jul 02 09:26:07 AM PDT 24 Jul 02 09:27:13 AM PDT 24 166726720864 ps
T1077 /workspace/coverage/default/16.uart_stress_all.2385468384 Jul 02 09:23:24 AM PDT 24 Jul 02 09:25:05 AM PDT 24 220243207788 ps
T1078 /workspace/coverage/default/279.uart_fifo_reset.3956939457 Jul 02 09:27:02 AM PDT 24 Jul 02 09:27:51 AM PDT 24 49441896405 ps
T1079 /workspace/coverage/default/9.uart_fifo_full.2606301430 Jul 02 09:23:06 AM PDT 24 Jul 02 09:23:27 AM PDT 24 87501416172 ps
T1080 /workspace/coverage/default/75.uart_fifo_reset.4257179518 Jul 02 09:25:47 AM PDT 24 Jul 02 09:28:44 AM PDT 24 110598535110 ps
T1081 /workspace/coverage/default/40.uart_rx_oversample.3031922081 Jul 02 09:24:49 AM PDT 24 Jul 02 09:24:56 AM PDT 24 3893307699 ps
T230 /workspace/coverage/default/53.uart_fifo_reset.3390005846 Jul 02 09:25:34 AM PDT 24 Jul 02 09:27:24 AM PDT 24 44903638447 ps
T1082 /workspace/coverage/default/3.uart_smoke.2724310500 Jul 02 09:23:05 AM PDT 24 Jul 02 09:23:42 AM PDT 24 5785100186 ps
T1083 /workspace/coverage/default/27.uart_rx_oversample.448837206 Jul 02 09:24:02 AM PDT 24 Jul 02 09:24:31 AM PDT 24 6359076481 ps
T1084 /workspace/coverage/default/28.uart_rx_parity_err.3979578032 Jul 02 09:24:05 AM PDT 24 Jul 02 09:24:53 AM PDT 24 25763058033 ps
T1085 /workspace/coverage/default/49.uart_fifo_full.3311067819 Jul 02 09:25:32 AM PDT 24 Jul 02 09:26:44 AM PDT 24 146140743156 ps
T1086 /workspace/coverage/default/40.uart_long_xfer_wo_dly.755633984 Jul 02 09:24:53 AM PDT 24 Jul 02 09:37:49 AM PDT 24 119147255066 ps
T1087 /workspace/coverage/default/37.uart_intr.4053485856 Jul 02 09:24:39 AM PDT 24 Jul 02 09:25:16 AM PDT 24 23039863916 ps
T1088 /workspace/coverage/cover_reg_top/17.uart_intr_test.3116034010 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:17 AM PDT 24 48599312 ps
T1089 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4061442436 Jul 02 09:46:06 AM PDT 24 Jul 02 09:46:09 AM PDT 24 22920660 ps
T1090 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.140016951 Jul 02 09:45:54 AM PDT 24 Jul 02 09:45:56 AM PDT 24 39250671 ps
T1091 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1823573010 Jul 02 09:46:03 AM PDT 24 Jul 02 09:46:06 AM PDT 24 57754012 ps
T56 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2276692213 Jul 02 09:46:12 AM PDT 24 Jul 02 09:46:14 AM PDT 24 21178263 ps
T1092 /workspace/coverage/cover_reg_top/10.uart_intr_test.2771585420 Jul 02 09:46:03 AM PDT 24 Jul 02 09:46:06 AM PDT 24 44156149 ps
T75 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.488748761 Jul 02 09:45:58 AM PDT 24 Jul 02 09:46:02 AM PDT 24 103432348 ps
T76 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3829466852 Jul 02 09:45:57 AM PDT 24 Jul 02 09:46:01 AM PDT 24 20402912 ps
T1093 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1974579695 Jul 02 09:46:05 AM PDT 24 Jul 02 09:46:08 AM PDT 24 80068901 ps
T1094 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1033979634 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:18 AM PDT 24 18989853 ps
T1095 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3605028355 Jul 02 09:46:06 AM PDT 24 Jul 02 09:46:08 AM PDT 24 37120067 ps
T1096 /workspace/coverage/cover_reg_top/18.uart_intr_test.2564228260 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:17 AM PDT 24 51382615 ps
T1097 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2629842411 Jul 02 09:46:13 AM PDT 24 Jul 02 09:46:15 AM PDT 24 75990980 ps
T1098 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1043334759 Jul 02 09:45:56 AM PDT 24 Jul 02 09:46:00 AM PDT 24 30219213 ps
T1099 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1378455570 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:17 AM PDT 24 27545284 ps
T57 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3687640728 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:17 AM PDT 24 48469456 ps
T1100 /workspace/coverage/cover_reg_top/46.uart_intr_test.2125585715 Jul 02 09:46:25 AM PDT 24 Jul 02 09:46:28 AM PDT 24 119189199 ps
T1101 /workspace/coverage/cover_reg_top/24.uart_intr_test.2197521279 Jul 02 09:46:16 AM PDT 24 Jul 02 09:46:18 AM PDT 24 40528617 ps
T77 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3533592076 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:07 AM PDT 24 54582313 ps
T1102 /workspace/coverage/cover_reg_top/32.uart_intr_test.3262318448 Jul 02 09:46:18 AM PDT 24 Jul 02 09:46:20 AM PDT 24 63544606 ps
T78 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1826718636 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:06 AM PDT 24 19003634 ps
T1103 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3439787803 Jul 02 09:46:10 AM PDT 24 Jul 02 09:46:13 AM PDT 24 291568459 ps
T1104 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1604579818 Jul 02 09:46:00 AM PDT 24 Jul 02 09:46:03 AM PDT 24 48838170 ps
T83 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3310859871 Jul 02 09:46:11 AM PDT 24 Jul 02 09:46:14 AM PDT 24 118761087 ps
T84 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2424364627 Jul 02 09:46:00 AM PDT 24 Jul 02 09:46:03 AM PDT 24 52155826 ps
T1105 /workspace/coverage/cover_reg_top/20.uart_intr_test.2046639864 Jul 02 09:46:16 AM PDT 24 Jul 02 09:46:18 AM PDT 24 18632000 ps
T1106 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3565929547 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:08 AM PDT 24 31890473 ps
T1107 /workspace/coverage/cover_reg_top/44.uart_intr_test.3624117815 Jul 02 09:46:21 AM PDT 24 Jul 02 09:46:22 AM PDT 24 36533612 ps
T85 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.17024606 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:18 AM PDT 24 552612753 ps
T1108 /workspace/coverage/cover_reg_top/39.uart_intr_test.206067649 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:22 AM PDT 24 63199619 ps
T125 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2197725870 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:07 AM PDT 24 407558026 ps
T1109 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3623865721 Jul 02 09:45:55 AM PDT 24 Jul 02 09:45:58 AM PDT 24 37064484 ps
T79 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.900522570 Jul 02 09:46:16 AM PDT 24 Jul 02 09:46:18 AM PDT 24 15118340 ps
T1110 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2383515902 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:07 AM PDT 24 24628128 ps
T1111 /workspace/coverage/cover_reg_top/35.uart_intr_test.771461250 Jul 02 09:46:23 AM PDT 24 Jul 02 09:46:24 AM PDT 24 30664512 ps
T86 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.940369734 Jul 02 09:46:05 AM PDT 24 Jul 02 09:46:08 AM PDT 24 340348830 ps
T1112 /workspace/coverage/cover_reg_top/13.uart_intr_test.2136139425 Jul 02 09:46:10 AM PDT 24 Jul 02 09:46:12 AM PDT 24 29728360 ps
T1113 /workspace/coverage/cover_reg_top/16.uart_intr_test.1215655954 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:22 AM PDT 24 11716594 ps
T58 /workspace/coverage/cover_reg_top/10.uart_csr_rw.1371251303 Jul 02 09:46:06 AM PDT 24 Jul 02 09:46:08 AM PDT 24 15925893 ps
T1114 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3269915876 Jul 02 09:45:55 AM PDT 24 Jul 02 09:45:59 AM PDT 24 17650358 ps
T1115 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1691356632 Jul 02 09:46:06 AM PDT 24 Jul 02 09:46:09 AM PDT 24 403308815 ps
T1116 /workspace/coverage/cover_reg_top/34.uart_intr_test.4098303432 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:22 AM PDT 24 12401900 ps
T59 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3584643956 Jul 02 09:45:55 AM PDT 24 Jul 02 09:45:59 AM PDT 24 56378515 ps
T1117 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1839340124 Jul 02 09:45:55 AM PDT 24 Jul 02 09:45:58 AM PDT 24 27583375 ps
T89 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1544693942 Jul 02 09:46:01 AM PDT 24 Jul 02 09:46:04 AM PDT 24 162293910 ps
T1118 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2219723095 Jul 02 09:46:03 AM PDT 24 Jul 02 09:46:06 AM PDT 24 87978541 ps
T1119 /workspace/coverage/cover_reg_top/14.uart_intr_test.1518858456 Jul 02 09:46:09 AM PDT 24 Jul 02 09:46:10 AM PDT 24 15937987 ps
T126 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.4240986463 Jul 02 09:46:02 AM PDT 24 Jul 02 09:46:06 AM PDT 24 214395055 ps
T91 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2193536292 Jul 02 09:45:58 AM PDT 24 Jul 02 09:46:01 AM PDT 24 50368951 ps
T80 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4257095419 Jul 02 09:46:11 AM PDT 24 Jul 02 09:46:12 AM PDT 24 77154702 ps
T1120 /workspace/coverage/cover_reg_top/0.uart_intr_test.705415045 Jul 02 09:45:56 AM PDT 24 Jul 02 09:45:59 AM PDT 24 35444366 ps
T1121 /workspace/coverage/cover_reg_top/43.uart_intr_test.1002046539 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:21 AM PDT 24 13524051 ps
T1122 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.866676183 Jul 02 09:46:00 AM PDT 24 Jul 02 09:46:03 AM PDT 24 18867917 ps
T1123 /workspace/coverage/cover_reg_top/15.uart_intr_test.3752204398 Jul 02 09:46:13 AM PDT 24 Jul 02 09:46:15 AM PDT 24 61513863 ps
T1124 /workspace/coverage/cover_reg_top/19.uart_tl_errors.884448525 Jul 02 09:46:14 AM PDT 24 Jul 02 09:46:17 AM PDT 24 68862762 ps
T87 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.424482564 Jul 02 09:45:57 AM PDT 24 Jul 02 09:46:01 AM PDT 24 527484134 ps
T88 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.982128056 Jul 02 09:46:05 AM PDT 24 Jul 02 09:46:08 AM PDT 24 77665403 ps
T81 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4286681495 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:22 AM PDT 24 122609853 ps
T1125 /workspace/coverage/cover_reg_top/49.uart_intr_test.1578546737 Jul 02 09:46:19 AM PDT 24 Jul 02 09:46:20 AM PDT 24 17597220 ps
T82 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3091142015 Jul 02 09:45:55 AM PDT 24 Jul 02 09:45:58 AM PDT 24 17605477 ps
T1126 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2067157471 Jul 02 09:45:54 AM PDT 24 Jul 02 09:45:57 AM PDT 24 26827862 ps
T1127 /workspace/coverage/cover_reg_top/23.uart_intr_test.1202449361 Jul 02 09:46:16 AM PDT 24 Jul 02 09:46:19 AM PDT 24 16511911 ps
T1128 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3180813307 Jul 02 09:46:05 AM PDT 24 Jul 02 09:46:08 AM PDT 24 75361377 ps
T1129 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2645323914 Jul 02 09:46:11 AM PDT 24 Jul 02 09:46:13 AM PDT 24 58837428 ps
T1130 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1495090800 Jul 02 09:45:57 AM PDT 24 Jul 02 09:46:01 AM PDT 24 34818076 ps
T1131 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.895524672 Jul 02 09:46:00 AM PDT 24 Jul 02 09:46:03 AM PDT 24 73812386 ps
T1132 /workspace/coverage/cover_reg_top/11.uart_intr_test.408887268 Jul 02 09:46:05 AM PDT 24 Jul 02 09:46:07 AM PDT 24 104838035 ps
T1133 /workspace/coverage/cover_reg_top/37.uart_intr_test.1518523073 Jul 02 09:46:25 AM PDT 24 Jul 02 09:46:28 AM PDT 24 13607051 ps
T93 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4246698351 Jul 02 09:46:13 AM PDT 24 Jul 02 09:46:15 AM PDT 24 182695511 ps
T1134 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1525162567 Jul 02 09:46:10 AM PDT 24 Jul 02 09:46:13 AM PDT 24 109076030 ps
T1135 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3980809169 Jul 02 09:46:05 AM PDT 24 Jul 02 09:46:08 AM PDT 24 34904765 ps
T1136 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2355801209 Jul 02 09:45:56 AM PDT 24 Jul 02 09:46:01 AM PDT 24 367701936 ps
T1137 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2874086281 Jul 02 09:46:00 AM PDT 24 Jul 02 09:46:03 AM PDT 24 19437857 ps
T1138 /workspace/coverage/cover_reg_top/28.uart_intr_test.3625883549 Jul 02 09:46:14 AM PDT 24 Jul 02 09:46:16 AM PDT 24 13083608 ps
T1139 /workspace/coverage/cover_reg_top/22.uart_intr_test.1532444788 Jul 02 09:46:14 AM PDT 24 Jul 02 09:46:16 AM PDT 24 15175225 ps
T1140 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1039225224 Jul 02 09:46:16 AM PDT 24 Jul 02 09:46:19 AM PDT 24 67283029 ps
T90 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2038400377 Jul 02 09:45:54 AM PDT 24 Jul 02 09:45:57 AM PDT 24 141496804 ps
T1141 /workspace/coverage/cover_reg_top/33.uart_intr_test.3712742092 Jul 02 09:46:23 AM PDT 24 Jul 02 09:46:24 AM PDT 24 20255472 ps
T1142 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1567473099 Jul 02 09:45:57 AM PDT 24 Jul 02 09:46:01 AM PDT 24 177844276 ps
T1143 /workspace/coverage/cover_reg_top/8.uart_csr_rw.961368490 Jul 02 09:46:00 AM PDT 24 Jul 02 09:46:03 AM PDT 24 103238676 ps
T1144 /workspace/coverage/cover_reg_top/26.uart_intr_test.2971501936 Jul 02 09:46:18 AM PDT 24 Jul 02 09:46:19 AM PDT 24 33196824 ps
T1145 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1686419303 Jul 02 09:45:57 AM PDT 24 Jul 02 09:46:00 AM PDT 24 32742391 ps
T1146 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1069007516 Jul 02 09:46:10 AM PDT 24 Jul 02 09:46:12 AM PDT 24 11513771 ps
T1147 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1549261349 Jul 02 09:46:02 AM PDT 24 Jul 02 09:46:06 AM PDT 24 491525758 ps
T1148 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1213806014 Jul 02 09:45:56 AM PDT 24 Jul 02 09:46:00 AM PDT 24 57981368 ps
T60 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3875006495 Jul 02 09:46:10 AM PDT 24 Jul 02 09:46:12 AM PDT 24 72068676 ps
T1149 /workspace/coverage/cover_reg_top/11.uart_csr_rw.473430546 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:06 AM PDT 24 14772108 ps
T1150 /workspace/coverage/cover_reg_top/1.uart_intr_test.3755399906 Jul 02 09:45:54 AM PDT 24 Jul 02 09:45:56 AM PDT 24 12953600 ps
T1151 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2444299086 Jul 02 09:46:13 AM PDT 24 Jul 02 09:46:15 AM PDT 24 162238145 ps
T127 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3244901063 Jul 02 09:46:10 AM PDT 24 Jul 02 09:46:12 AM PDT 24 123237551 ps
T1152 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3546319883 Jul 02 09:46:00 AM PDT 24 Jul 02 09:46:03 AM PDT 24 110890796 ps
T1153 /workspace/coverage/cover_reg_top/9.uart_intr_test.3205412625 Jul 02 09:46:02 AM PDT 24 Jul 02 09:46:04 AM PDT 24 22054701 ps
T1154 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3373585154 Jul 02 09:46:16 AM PDT 24 Jul 02 09:46:18 AM PDT 24 14229049 ps
T1155 /workspace/coverage/cover_reg_top/7.uart_csr_rw.2370346969 Jul 02 09:46:01 AM PDT 24 Jul 02 09:46:04 AM PDT 24 17446436 ps
T1156 /workspace/coverage/cover_reg_top/45.uart_intr_test.118286494 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:23 AM PDT 24 12798695 ps
T92 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1273753143 Jul 02 09:45:57 AM PDT 24 Jul 02 09:46:01 AM PDT 24 106569312 ps
T1157 /workspace/coverage/cover_reg_top/19.uart_intr_test.4283738230 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:17 AM PDT 24 50982372 ps
T1158 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2529884936 Jul 02 09:45:56 AM PDT 24 Jul 02 09:46:00 AM PDT 24 57454508 ps
T1159 /workspace/coverage/cover_reg_top/2.uart_intr_test.2184453199 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:06 AM PDT 24 11568306 ps
T1160 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1402911940 Jul 02 09:45:58 AM PDT 24 Jul 02 09:46:02 AM PDT 24 119309057 ps
T1161 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4197628924 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:17 AM PDT 24 60340658 ps
T1162 /workspace/coverage/cover_reg_top/42.uart_intr_test.1561257732 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:22 AM PDT 24 52696845 ps
T1163 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3732624839 Jul 02 09:46:12 AM PDT 24 Jul 02 09:46:15 AM PDT 24 123707877 ps
T1164 /workspace/coverage/cover_reg_top/12.uart_intr_test.828783946 Jul 02 09:46:02 AM PDT 24 Jul 02 09:46:05 AM PDT 24 99366730 ps
T1165 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4188575341 Jul 02 09:45:58 AM PDT 24 Jul 02 09:46:01 AM PDT 24 59925419 ps
T1166 /workspace/coverage/cover_reg_top/8.uart_intr_test.2214501323 Jul 02 09:46:03 AM PDT 24 Jul 02 09:46:06 AM PDT 24 14867139 ps
T1167 /workspace/coverage/cover_reg_top/12.uart_csr_rw.4110867071 Jul 02 09:46:14 AM PDT 24 Jul 02 09:46:15 AM PDT 24 14873743 ps
T1168 /workspace/coverage/cover_reg_top/17.uart_tl_errors.644004049 Jul 02 09:46:16 AM PDT 24 Jul 02 09:46:20 AM PDT 24 146755750 ps
T1169 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.542943319 Jul 02 09:46:01 AM PDT 24 Jul 02 09:46:04 AM PDT 24 60489416 ps
T1170 /workspace/coverage/cover_reg_top/27.uart_intr_test.1152828487 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:17 AM PDT 24 50132070 ps
T1171 /workspace/coverage/cover_reg_top/21.uart_intr_test.793815110 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:17 AM PDT 24 115257767 ps
T1172 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3471935049 Jul 02 09:46:05 AM PDT 24 Jul 02 09:46:08 AM PDT 24 42431382 ps
T1173 /workspace/coverage/cover_reg_top/5.uart_intr_test.4010636585 Jul 02 09:45:59 AM PDT 24 Jul 02 09:46:02 AM PDT 24 27056841 ps
T1174 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4186318420 Jul 02 09:46:12 AM PDT 24 Jul 02 09:46:14 AM PDT 24 67079775 ps
T1175 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2437622672 Jul 02 09:46:02 AM PDT 24 Jul 02 09:46:06 AM PDT 24 139140014 ps
T1176 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2027225967 Jul 02 09:46:08 AM PDT 24 Jul 02 09:46:10 AM PDT 24 155632859 ps
T1177 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3221786868 Jul 02 09:46:01 AM PDT 24 Jul 02 09:46:04 AM PDT 24 26134249 ps
T1178 /workspace/coverage/cover_reg_top/3.uart_intr_test.1490535291 Jul 02 09:46:01 AM PDT 24 Jul 02 09:46:04 AM PDT 24 26106068 ps
T61 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1416460506 Jul 02 09:45:54 AM PDT 24 Jul 02 09:45:59 AM PDT 24 226982421 ps
T1179 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1717325531 Jul 02 09:46:06 AM PDT 24 Jul 02 09:46:08 AM PDT 24 39724754 ps
T1180 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2913181661 Jul 02 09:46:09 AM PDT 24 Jul 02 09:46:10 AM PDT 24 26419133 ps
T1181 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1812418133 Jul 02 09:45:56 AM PDT 24 Jul 02 09:45:59 AM PDT 24 36676860 ps
T1182 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2435366435 Jul 02 09:46:14 AM PDT 24 Jul 02 09:46:16 AM PDT 24 140160703 ps
T1183 /workspace/coverage/cover_reg_top/38.uart_intr_test.742077202 Jul 02 09:46:21 AM PDT 24 Jul 02 09:46:22 AM PDT 24 48156226 ps
T1184 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3694276503 Jul 02 09:46:12 AM PDT 24 Jul 02 09:46:14 AM PDT 24 61323520 ps
T62 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1748429967 Jul 02 09:45:56 AM PDT 24 Jul 02 09:45:59 AM PDT 24 26226478 ps
T1185 /workspace/coverage/cover_reg_top/0.uart_tl_errors.1592465862 Jul 02 09:45:55 AM PDT 24 Jul 02 09:45:58 AM PDT 24 90268011 ps
T1186 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1872651293 Jul 02 09:46:13 AM PDT 24 Jul 02 09:46:15 AM PDT 24 27620068 ps
T1187 /workspace/coverage/cover_reg_top/1.uart_tl_errors.634777454 Jul 02 09:45:55 AM PDT 24 Jul 02 09:45:59 AM PDT 24 45080436 ps
T1188 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2837240282 Jul 02 09:46:00 AM PDT 24 Jul 02 09:46:04 AM PDT 24 97699212 ps
T1189 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1503037927 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:07 AM PDT 24 129280227 ps
T1190 /workspace/coverage/cover_reg_top/48.uart_intr_test.2318594425 Jul 02 09:46:19 AM PDT 24 Jul 02 09:46:20 AM PDT 24 78515910 ps
T1191 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.790596818 Jul 02 09:46:11 AM PDT 24 Jul 02 09:46:13 AM PDT 24 95345519 ps
T1192 /workspace/coverage/cover_reg_top/30.uart_intr_test.4016732625 Jul 02 09:46:18 AM PDT 24 Jul 02 09:46:19 AM PDT 24 22067263 ps
T1193 /workspace/coverage/cover_reg_top/18.uart_csr_rw.158540531 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:17 AM PDT 24 61916041 ps
T1194 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1056857144 Jul 02 09:46:14 AM PDT 24 Jul 02 09:46:15 AM PDT 24 154803774 ps
T1195 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.227751630 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:07 AM PDT 24 22467364 ps
T1196 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4054781753 Jul 02 09:46:03 AM PDT 24 Jul 02 09:46:06 AM PDT 24 82381500 ps
T1197 /workspace/coverage/cover_reg_top/29.uart_intr_test.3727451372 Jul 02 09:46:15 AM PDT 24 Jul 02 09:46:16 AM PDT 24 15017640 ps
T1198 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1774729762 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:23 AM PDT 24 46076313 ps
T63 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3512228769 Jul 02 09:46:00 AM PDT 24 Jul 02 09:46:03 AM PDT 24 37074895 ps
T1199 /workspace/coverage/cover_reg_top/9.uart_tl_errors.563456719 Jul 02 09:46:03 AM PDT 24 Jul 02 09:46:06 AM PDT 24 69937073 ps
T1200 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1544983354 Jul 02 09:46:12 AM PDT 24 Jul 02 09:46:14 AM PDT 24 117206473 ps
T1201 /workspace/coverage/cover_reg_top/31.uart_intr_test.259740644 Jul 02 09:46:16 AM PDT 24 Jul 02 09:46:19 AM PDT 24 35604167 ps
T1202 /workspace/coverage/cover_reg_top/4.uart_intr_test.3703412767 Jul 02 09:45:57 AM PDT 24 Jul 02 09:46:00 AM PDT 24 10865012 ps
T128 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2572742935 Jul 02 09:46:16 AM PDT 24 Jul 02 09:46:18 AM PDT 24 248301831 ps
T1203 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.151807512 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:06 AM PDT 24 13315409 ps
T1204 /workspace/coverage/cover_reg_top/7.uart_intr_test.3200735687 Jul 02 09:46:01 AM PDT 24 Jul 02 09:46:04 AM PDT 24 51158303 ps
T1205 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1352694938 Jul 02 09:45:56 AM PDT 24 Jul 02 09:45:59 AM PDT 24 27371577 ps
T1206 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1972084062 Jul 02 09:46:04 AM PDT 24 Jul 02 09:46:07 AM PDT 24 94520021 ps
T1207 /workspace/coverage/cover_reg_top/25.uart_intr_test.2060198643 Jul 02 09:46:18 AM PDT 24 Jul 02 09:46:19 AM PDT 24 42271162 ps
T1208 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2250831155 Jul 02 09:45:56 AM PDT 24 Jul 02 09:45:59 AM PDT 24 117078123 ps
T64 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4015528922 Jul 02 09:45:55 AM PDT 24 Jul 02 09:46:00 AM PDT 24 225228822 ps
T1209 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1785051191 Jul 02 09:46:05 AM PDT 24 Jul 02 09:46:08 AM PDT 24 31451151 ps
T1210 /workspace/coverage/cover_reg_top/41.uart_intr_test.2283782414 Jul 02 09:46:19 AM PDT 24 Jul 02 09:46:21 AM PDT 24 57855591 ps
T1211 /workspace/coverage/cover_reg_top/36.uart_intr_test.1056593422 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:21 AM PDT 24 22570852 ps
T74 /workspace/coverage/cover_reg_top/0.uart_csr_rw.563611781 Jul 02 09:45:56 AM PDT 24 Jul 02 09:46:00 AM PDT 24 15897789 ps
T1212 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.936155194 Jul 02 09:46:05 AM PDT 24 Jul 02 09:46:07 AM PDT 24 117929103 ps
T1213 /workspace/coverage/cover_reg_top/6.uart_intr_test.3377818531 Jul 02 09:46:03 AM PDT 24 Jul 02 09:46:05 AM PDT 24 12963703 ps
T1214 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1850579816 Jul 02 09:46:05 AM PDT 24 Jul 02 09:46:07 AM PDT 24 16818989 ps
T1215 /workspace/coverage/cover_reg_top/47.uart_intr_test.872165357 Jul 02 09:46:24 AM PDT 24 Jul 02 09:46:27 AM PDT 24 36793305 ps
T1216 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2054664477 Jul 02 09:45:57 AM PDT 24 Jul 02 09:46:00 AM PDT 24 56439159 ps
T1217 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1417048540 Jul 02 09:46:20 AM PDT 24 Jul 02 09:46:22 AM PDT 24 171704492 ps
T1218 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2588298690 Jul 02 09:46:00 AM PDT 24 Jul 02 09:46:04 AM PDT 24 296700420 ps
T1219 /workspace/coverage/cover_reg_top/40.uart_intr_test.3154136652 Jul 02 09:46:19 AM PDT 24 Jul 02 09:46:20 AM PDT 24 10797230 ps

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3377839715
Short name T6
Test name
Test status
Simulation time 158298582313 ps
CPU time 424.32 seconds
Started Jul 02 09:23:23 AM PDT 24
Finished Jul 02 09:30:31 AM PDT 24
Peak memory 210332 kb
Host smart-eb16c7dc-0608-43dc-ae4c-41cdf061d138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377839715 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3377839715
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.2342356605
Short name T17
Test name
Test status
Simulation time 155967894355 ps
CPU time 493.7 seconds
Started Jul 02 09:23:21 AM PDT 24
Finished Jul 02 09:31:39 AM PDT 24
Peak memory 199936 kb
Host smart-fc91d250-08d7-49fe-9cda-8887e84d5c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342356605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2342356605
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1645545717
Short name T29
Test name
Test status
Simulation time 190739119200 ps
CPU time 827.27 seconds
Started Jul 02 09:25:35 AM PDT 24
Finished Jul 02 09:39:23 AM PDT 24
Peak memory 216412 kb
Host smart-987434db-452f-4200-a1a9-68ba411a3cb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645545717 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1645545717
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.879736255
Short name T44
Test name
Test status
Simulation time 225601231025 ps
CPU time 531.11 seconds
Started Jul 02 09:25:00 AM PDT 24
Finished Jul 02 09:33:52 AM PDT 24
Peak memory 199900 kb
Host smart-ee3dbdfa-0b28-4a45-9b0a-ee61fea46e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879736255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.879736255
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1490499854
Short name T34
Test name
Test status
Simulation time 85851862629 ps
CPU time 221.04 seconds
Started Jul 02 09:25:51 AM PDT 24
Finished Jul 02 09:29:33 AM PDT 24
Peak memory 216484 kb
Host smart-6f6655ea-db3c-43a5-b104-e175a2c593e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490499854 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1490499854
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.322105104
Short name T120
Test name
Test status
Simulation time 513068656487 ps
CPU time 322.29 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:28:36 AM PDT 24
Peak memory 199884 kb
Host smart-6987f0b4-f3ee-4e5d-9883-08c2c36ba024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322105104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.322105104
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1128838784
Short name T22
Test name
Test status
Simulation time 55889825450 ps
CPU time 598.65 seconds
Started Jul 02 09:26:00 AM PDT 24
Finished Jul 02 09:36:00 AM PDT 24
Peak memory 216376 kb
Host smart-0af5e787-2b33-48f6-90e8-be037ef6ab6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128838784 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1128838784
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2291169284
Short name T271
Test name
Test status
Simulation time 17361116359 ps
CPU time 30.92 seconds
Started Jul 02 09:27:07 AM PDT 24
Finished Jul 02 09:27:38 AM PDT 24
Peak memory 200000 kb
Host smart-2f5f504a-0e8e-484e-bedb-aa46448b64cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291169284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2291169284
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.283309154
Short name T139
Test name
Test status
Simulation time 186543282341 ps
CPU time 27.82 seconds
Started Jul 02 09:24:15 AM PDT 24
Finished Jul 02 09:24:43 AM PDT 24
Peak memory 199980 kb
Host smart-d303eadd-9850-42e2-aa9b-f8e6677db5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283309154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.283309154
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3082012752
Short name T27
Test name
Test status
Simulation time 262005714 ps
CPU time 0.86 seconds
Started Jul 02 09:22:59 AM PDT 24
Finished Jul 02 09:23:01 AM PDT 24
Peak memory 218304 kb
Host smart-8e954c57-887f-4ce7-ad54-2c9561cb8b67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082012752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3082012752
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3179149503
Short name T8
Test name
Test status
Simulation time 31764624261 ps
CPU time 26.25 seconds
Started Jul 02 09:26:14 AM PDT 24
Finished Jul 02 09:26:41 AM PDT 24
Peak memory 199968 kb
Host smart-1425b83d-2a02-4da4-bf71-97319d61f9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179149503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3179149503
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3647638103
Short name T130
Test name
Test status
Simulation time 375774724874 ps
CPU time 39.27 seconds
Started Jul 02 09:23:05 AM PDT 24
Finished Jul 02 09:23:45 AM PDT 24
Peak memory 199652 kb
Host smart-33196f63-766d-4ce5-a821-28748c995c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647638103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3647638103
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3879746750
Short name T33
Test name
Test status
Simulation time 79868279757 ps
CPU time 989.65 seconds
Started Jul 02 09:25:59 AM PDT 24
Finished Jul 02 09:42:30 AM PDT 24
Peak memory 224768 kb
Host smart-d54d57cb-56b6-4a8f-8b4f-258c89242530
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879746750 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3879746750
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all.409384287
Short name T121
Test name
Test status
Simulation time 928771160819 ps
CPU time 232.75 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:27:16 AM PDT 24
Peak memory 199820 kb
Host smart-b9c16eac-8cd1-423b-bbe4-331313221c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409384287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.409384287
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2074811368
Short name T263
Test name
Test status
Simulation time 52510609938 ps
CPU time 128.78 seconds
Started Jul 02 09:24:11 AM PDT 24
Finished Jul 02 09:26:20 AM PDT 24
Peak memory 199912 kb
Host smart-fc36b339-9d91-4f75-ad83-4ad938056eec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2074811368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2074811368
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3800969157
Short name T164
Test name
Test status
Simulation time 221465879433 ps
CPU time 352.9 seconds
Started Jul 02 09:24:51 AM PDT 24
Finished Jul 02 09:30:44 AM PDT 24
Peak memory 200000 kb
Host smart-b1274d8b-1054-4346-beba-b1c4a1051f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800969157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3800969157
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2663949079
Short name T105
Test name
Test status
Simulation time 119342408782 ps
CPU time 502.78 seconds
Started Jul 02 09:24:26 AM PDT 24
Finished Jul 02 09:32:49 AM PDT 24
Peak memory 216528 kb
Host smart-8e5108f5-ccde-4d08-ae20-d5144e852a7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663949079 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2663949079
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1628633161
Short name T158
Test name
Test status
Simulation time 209646299684 ps
CPU time 44.83 seconds
Started Jul 02 09:26:22 AM PDT 24
Finished Jul 02 09:27:08 AM PDT 24
Peak memory 200000 kb
Host smart-68d2052d-a937-4d2c-9695-480fbde66782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628633161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1628633161
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2154222397
Short name T140
Test name
Test status
Simulation time 95594944691 ps
CPU time 241.48 seconds
Started Jul 02 09:27:03 AM PDT 24
Finished Jul 02 09:31:05 AM PDT 24
Peak memory 199968 kb
Host smart-4a7ae027-5832-4309-a1e1-b3d39e1a47a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154222397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2154222397
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1294700018
Short name T148
Test name
Test status
Simulation time 254551207730 ps
CPU time 126.89 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:25:27 AM PDT 24
Peak memory 199908 kb
Host smart-58b70d35-4357-4e7c-94b2-8dbc8732f5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294700018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1294700018
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2276692213
Short name T56
Test name
Test status
Simulation time 21178263 ps
CPU time 0.64 seconds
Started Jul 02 09:46:12 AM PDT 24
Finished Jul 02 09:46:14 AM PDT 24
Peak memory 196220 kb
Host smart-45b1f00c-1aa1-4966-8dc9-763ce49f3d17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276692213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2276692213
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.940369734
Short name T86
Test name
Test status
Simulation time 340348830 ps
CPU time 1.29 seconds
Started Jul 02 09:46:05 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 200076 kb
Host smart-a15c83bc-2439-4b91-9ea1-fcee1be98463
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940369734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.940369734
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3124456424
Short name T191
Test name
Test status
Simulation time 212525796847 ps
CPU time 374.47 seconds
Started Jul 02 09:26:51 AM PDT 24
Finished Jul 02 09:33:06 AM PDT 24
Peak memory 199932 kb
Host smart-2245d767-d8de-4e99-ba6c-f94494d3d95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124456424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3124456424
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_alert_test.3502604622
Short name T24
Test name
Test status
Simulation time 22789255 ps
CPU time 0.6 seconds
Started Jul 02 09:22:47 AM PDT 24
Finished Jul 02 09:22:48 AM PDT 24
Peak memory 195284 kb
Host smart-0284d857-cbed-4e56-813e-a38f45d050f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502604622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3502604622
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.793729531
Short name T187
Test name
Test status
Simulation time 54111202294 ps
CPU time 20.89 seconds
Started Jul 02 09:23:55 AM PDT 24
Finished Jul 02 09:24:18 AM PDT 24
Peak memory 199964 kb
Host smart-f70b0c09-ce1a-4578-86ab-af78620e1842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793729531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.793729531
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.99565227
Short name T151
Test name
Test status
Simulation time 14849373407 ps
CPU time 29.91 seconds
Started Jul 02 09:25:38 AM PDT 24
Finished Jul 02 09:26:08 AM PDT 24
Peak memory 199972 kb
Host smart-27a5f7c4-3c46-4a74-b30b-674be57b519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99565227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.99565227
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.4003080765
Short name T603
Test name
Test status
Simulation time 786884469010 ps
CPU time 839 seconds
Started Jul 02 09:25:59 AM PDT 24
Finished Jul 02 09:39:59 AM PDT 24
Peak memory 224732 kb
Host smart-ba1e6659-c4d3-4135-bfbb-90316e328703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003080765 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.4003080765
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3285506481
Short name T275
Test name
Test status
Simulation time 105452104580 ps
CPU time 41.72 seconds
Started Jul 02 09:23:34 AM PDT 24
Finished Jul 02 09:24:16 AM PDT 24
Peak memory 199936 kb
Host smart-885f6e64-fe82-4e2b-8b17-87e909ed3c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285506481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3285506481
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.616761102
Short name T15
Test name
Test status
Simulation time 28229163397 ps
CPU time 23.06 seconds
Started Jul 02 09:27:05 AM PDT 24
Finished Jul 02 09:27:29 AM PDT 24
Peak memory 199932 kb
Host smart-5751d434-fd1d-41b0-985d-2b7a122f658b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616761102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.616761102
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3763424747
Short name T149
Test name
Test status
Simulation time 112995433320 ps
CPU time 49.08 seconds
Started Jul 02 09:24:35 AM PDT 24
Finished Jul 02 09:25:24 AM PDT 24
Peak memory 199944 kb
Host smart-f345b1d4-d28d-4d4e-820a-a90b44a7c51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763424747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3763424747
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1822225653
Short name T119
Test name
Test status
Simulation time 134148307401 ps
CPU time 372.67 seconds
Started Jul 02 09:26:59 AM PDT 24
Finished Jul 02 09:33:13 AM PDT 24
Peak memory 199908 kb
Host smart-b6366d0c-8830-49ef-ab75-d817610d256c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822225653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1822225653
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2850159719
Short name T185
Test name
Test status
Simulation time 210479398160 ps
CPU time 1535.07 seconds
Started Jul 02 09:23:12 AM PDT 24
Finished Jul 02 09:48:48 AM PDT 24
Peak memory 225772 kb
Host smart-262d41a4-9384-4645-8ab7-15c7d29a7395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850159719 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2850159719
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3250803617
Short name T2
Test name
Test status
Simulation time 26030931073 ps
CPU time 14.62 seconds
Started Jul 02 09:25:59 AM PDT 24
Finished Jul 02 09:26:15 AM PDT 24
Peak memory 199916 kb
Host smart-c864a47a-52d1-4787-bd42-39ba518f286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250803617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3250803617
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2038400377
Short name T90
Test name
Test status
Simulation time 141496804 ps
CPU time 1.28 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:45:57 AM PDT 24
Peak memory 200248 kb
Host smart-b8a4efb8-d28b-4092-8a31-05563a36f638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038400377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2038400377
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2628309164
Short name T218
Test name
Test status
Simulation time 507603263665 ps
CPU time 55.64 seconds
Started Jul 02 09:23:14 AM PDT 24
Finished Jul 02 09:24:12 AM PDT 24
Peak memory 199928 kb
Host smart-65e7814d-1367-4b61-b10f-64ee877bc15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628309164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2628309164
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3411375119
Short name T51
Test name
Test status
Simulation time 277628783932 ps
CPU time 616.64 seconds
Started Jul 02 09:25:36 AM PDT 24
Finished Jul 02 09:35:53 AM PDT 24
Peak memory 216500 kb
Host smart-8e5a7667-0b80-45c0-be00-f96332ed0ddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411375119 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3411375119
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2009900063
Short name T40
Test name
Test status
Simulation time 57110671734 ps
CPU time 27.02 seconds
Started Jul 02 09:26:03 AM PDT 24
Finished Jul 02 09:26:31 AM PDT 24
Peak memory 199888 kb
Host smart-98b934b5-9c64-486e-8ae5-0a8ce9e9b0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009900063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2009900063
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.204898621
Short name T272
Test name
Test status
Simulation time 135255285670 ps
CPU time 247.84 seconds
Started Jul 02 09:23:23 AM PDT 24
Finished Jul 02 09:27:34 AM PDT 24
Peak memory 199900 kb
Host smart-85dcd23f-316d-4a76-bdc7-09bfd3869971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204898621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.204898621
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_stress_all.3944808541
Short name T114
Test name
Test status
Simulation time 79888470208 ps
CPU time 29.99 seconds
Started Jul 02 09:24:02 AM PDT 24
Finished Jul 02 09:24:34 AM PDT 24
Peak memory 199960 kb
Host smart-9d47a409-3b0b-4069-8322-6d2d077ed8f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944808541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3944808541
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3066450002
Short name T950
Test name
Test status
Simulation time 161399408143 ps
CPU time 464.21 seconds
Started Jul 02 09:23:59 AM PDT 24
Finished Jul 02 09:31:44 AM PDT 24
Peak memory 216400 kb
Host smart-ee2a24c4-d590-4f90-8036-6d834219c9cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066450002 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3066450002
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.598624167
Short name T217
Test name
Test status
Simulation time 174596894758 ps
CPU time 101.58 seconds
Started Jul 02 09:26:28 AM PDT 24
Finished Jul 02 09:28:10 AM PDT 24
Peak memory 200116 kb
Host smart-f9e55478-21bd-4613-a2ed-8b3776832858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598624167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.598624167
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2135985993
Short name T153
Test name
Test status
Simulation time 178138825307 ps
CPU time 65.88 seconds
Started Jul 02 09:26:32 AM PDT 24
Finished Jul 02 09:27:39 AM PDT 24
Peak memory 199852 kb
Host smart-9325a4b2-2b28-4af7-ad21-ee41c9afe126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135985993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2135985993
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2927523022
Short name T155
Test name
Test status
Simulation time 73895514264 ps
CPU time 118.59 seconds
Started Jul 02 09:26:07 AM PDT 24
Finished Jul 02 09:28:06 AM PDT 24
Peak memory 200012 kb
Host smart-0a1469e9-2043-452e-b77d-84f0c040bc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927523022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2927523022
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1274141964
Short name T160
Test name
Test status
Simulation time 310526823240 ps
CPU time 29.25 seconds
Started Jul 02 09:27:11 AM PDT 24
Finished Jul 02 09:27:40 AM PDT 24
Peak memory 199920 kb
Host smart-f8cde028-b606-499d-b1b3-ac4cec09bd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274141964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1274141964
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1925167019
Short name T269
Test name
Test status
Simulation time 127925547478 ps
CPU time 251.08 seconds
Started Jul 02 09:27:07 AM PDT 24
Finished Jul 02 09:31:19 AM PDT 24
Peak memory 199976 kb
Host smart-0ed9de38-0210-4caa-974a-e8036d637734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925167019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1925167019
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_full.941312507
Short name T1055
Test name
Test status
Simulation time 38670003190 ps
CPU time 15.62 seconds
Started Jul 02 09:24:32 AM PDT 24
Finished Jul 02 09:24:48 AM PDT 24
Peak memory 199820 kb
Host smart-4ef68e00-6e91-41cd-9b30-9d3f7c4c8993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941312507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.941312507
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2427538993
Short name T145
Test name
Test status
Simulation time 72981592898 ps
CPU time 119.98 seconds
Started Jul 02 09:24:29 AM PDT 24
Finished Jul 02 09:26:30 AM PDT 24
Peak memory 200028 kb
Host smart-49c54811-08f2-4d20-8953-2889d5bbea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427538993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2427538993
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.4031437587
Short name T206
Test name
Test status
Simulation time 8751869521 ps
CPU time 14.93 seconds
Started Jul 02 09:27:02 AM PDT 24
Finished Jul 02 09:27:18 AM PDT 24
Peak memory 199904 kb
Host smart-bf10dbc1-f894-481f-af5b-c17d0b98101d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031437587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.4031437587
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3688155157
Short name T131
Test name
Test status
Simulation time 59260598959 ps
CPU time 56.67 seconds
Started Jul 02 09:27:07 AM PDT 24
Finished Jul 02 09:28:04 AM PDT 24
Peak memory 200004 kb
Host smart-00fa077f-83b4-47ad-b552-b71eb321c4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688155157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3688155157
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.49376072
Short name T318
Test name
Test status
Simulation time 316150802182 ps
CPU time 494.06 seconds
Started Jul 02 09:22:45 AM PDT 24
Finished Jul 02 09:30:59 AM PDT 24
Peak memory 216468 kb
Host smart-fb41be55-6b43-4a3a-a36b-e0d411c1c218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49376072 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.49376072
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1830574198
Short name T198
Test name
Test status
Simulation time 76425926094 ps
CPU time 171.52 seconds
Started Jul 02 09:26:11 AM PDT 24
Finished Jul 02 09:29:03 AM PDT 24
Peak memory 199968 kb
Host smart-1b3adce8-73ce-4421-bdc3-6e5758ed14a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830574198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1830574198
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2546689988
Short name T231
Test name
Test status
Simulation time 119062149213 ps
CPU time 173.57 seconds
Started Jul 02 09:26:34 AM PDT 24
Finished Jul 02 09:29:28 AM PDT 24
Peak memory 199968 kb
Host smart-bee00bcb-e553-4be4-ab99-0f837e7818e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546689988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2546689988
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3947999254
Short name T257
Test name
Test status
Simulation time 54162900883 ps
CPU time 90.64 seconds
Started Jul 02 09:26:39 AM PDT 24
Finished Jul 02 09:28:10 AM PDT 24
Peak memory 199888 kb
Host smart-021da238-7d8b-491e-9436-9e7827a97b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947999254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3947999254
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2346449745
Short name T154
Test name
Test status
Simulation time 199523822629 ps
CPU time 81.12 seconds
Started Jul 02 09:27:03 AM PDT 24
Finished Jul 02 09:28:25 AM PDT 24
Peak memory 200000 kb
Host smart-32aee00f-a23e-49b4-b40c-d7216f80c51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346449745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2346449745
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2887242309
Short name T223
Test name
Test status
Simulation time 152454944444 ps
CPU time 135.83 seconds
Started Jul 02 09:25:33 AM PDT 24
Finished Jul 02 09:27:49 AM PDT 24
Peak memory 199948 kb
Host smart-bd86c855-8ce6-407a-91ad-a2a6fe5ea182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887242309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2887242309
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1929866796
Short name T208
Test name
Test status
Simulation time 93956762565 ps
CPU time 37.75 seconds
Started Jul 02 09:25:59 AM PDT 24
Finished Jul 02 09:26:38 AM PDT 24
Peak memory 199888 kb
Host smart-250baac2-15e2-43a0-86a7-a0e6df7adf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929866796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1929866796
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4246698351
Short name T93
Test name
Test status
Simulation time 182695511 ps
CPU time 0.98 seconds
Started Jul 02 09:46:13 AM PDT 24
Finished Jul 02 09:46:15 AM PDT 24
Peak memory 199708 kb
Host smart-75674591-aced-487c-be0c-b963c282e4e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246698351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4246698351
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.17024606
Short name T85
Test name
Test status
Simulation time 552612753 ps
CPU time 0.99 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:18 AM PDT 24
Peak memory 199728 kb
Host smart-f1d89f83-e553-47b7-bc95-491c8bf69fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17024606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.17024606
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_intr.2183970966
Short name T344
Test name
Test status
Simulation time 53311914302 ps
CPU time 6.77 seconds
Started Jul 02 09:22:44 AM PDT 24
Finished Jul 02 09:22:51 AM PDT 24
Peak memory 199324 kb
Host smart-29b93252-aa1b-4ed3-908b-534760bb0341
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183970966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2183970966
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_perf.352647770
Short name T545
Test name
Test status
Simulation time 12550576775 ps
CPU time 124.55 seconds
Started Jul 02 09:22:49 AM PDT 24
Finished Jul 02 09:24:55 AM PDT 24
Peak memory 199916 kb
Host smart-f7867e4a-f87b-4417-81c3-b2d2fcc624cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352647770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.352647770
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1851666545
Short name T182
Test name
Test status
Simulation time 49509016286 ps
CPU time 65.62 seconds
Started Jul 02 09:26:03 AM PDT 24
Finished Jul 02 09:27:10 AM PDT 24
Peak memory 199908 kb
Host smart-53b39ee1-8f96-4c6d-9cc7-58a36004074c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851666545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1851666545
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2331918495
Short name T213
Test name
Test status
Simulation time 90743665517 ps
CPU time 33.39 seconds
Started Jul 02 09:26:10 AM PDT 24
Finished Jul 02 09:26:44 AM PDT 24
Peak memory 199976 kb
Host smart-8add172f-7272-45da-b5e8-4f3e08782a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331918495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2331918495
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1147322327
Short name T251
Test name
Test status
Simulation time 48872017568 ps
CPU time 14.95 seconds
Started Jul 02 09:26:11 AM PDT 24
Finished Jul 02 09:26:26 AM PDT 24
Peak memory 199944 kb
Host smart-987aec34-6b2d-4466-a9c3-8625aa374e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147322327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1147322327
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2819369751
Short name T471
Test name
Test status
Simulation time 187618510908 ps
CPU time 254.96 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:27:35 AM PDT 24
Peak memory 199972 kb
Host smart-bf082d3c-c649-41b6-a658-1428841d5a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819369751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2819369751
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3119506791
Short name T229
Test name
Test status
Simulation time 18454322850 ps
CPU time 37.48 seconds
Started Jul 02 09:26:15 AM PDT 24
Finished Jul 02 09:26:53 AM PDT 24
Peak memory 199948 kb
Host smart-26587d24-66d3-485a-acc7-dc65e96623cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119506791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3119506791
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1258995210
Short name T199
Test name
Test status
Simulation time 148469899145 ps
CPU time 57.16 seconds
Started Jul 02 09:26:22 AM PDT 24
Finished Jul 02 09:27:20 AM PDT 24
Peak memory 199940 kb
Host smart-d307be0a-a3c7-4827-9cff-68bf68af96da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258995210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1258995210
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2269141453
Short name T954
Test name
Test status
Simulation time 40237788508 ps
CPU time 17.42 seconds
Started Jul 02 09:26:19 AM PDT 24
Finished Jul 02 09:26:37 AM PDT 24
Peak memory 199940 kb
Host smart-d2c0e5b3-cf05-4ead-b42a-3e0a898d0e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269141453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2269141453
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1192044065
Short name T228
Test name
Test status
Simulation time 136475717654 ps
CPU time 233.45 seconds
Started Jul 02 09:26:30 AM PDT 24
Finished Jul 02 09:30:25 AM PDT 24
Peak memory 199960 kb
Host smart-ef7f736d-3a9e-453f-904b-c8d984799323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192044065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1192044065
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2701528539
Short name T459
Test name
Test status
Simulation time 124463308245 ps
CPU time 85.63 seconds
Started Jul 02 09:23:02 AM PDT 24
Finished Jul 02 09:24:29 AM PDT 24
Peak memory 199936 kb
Host smart-52d869fc-97bc-4fbd-b175-130ba1eac1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701528539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2701528539
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1277792952
Short name T150
Test name
Test status
Simulation time 54643021056 ps
CPU time 490 seconds
Started Jul 02 09:26:34 AM PDT 24
Finished Jul 02 09:34:45 AM PDT 24
Peak memory 199932 kb
Host smart-40b1fcc7-86b2-4ffc-8da4-dd8219ae9347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277792952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1277792952
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3304501163
Short name T249
Test name
Test status
Simulation time 114093733793 ps
CPU time 65.39 seconds
Started Jul 02 09:26:38 AM PDT 24
Finished Jul 02 09:27:44 AM PDT 24
Peak memory 199944 kb
Host smart-dce1f2eb-0dc7-4ff8-9d33-a45f66c1e8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304501163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3304501163
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1718114039
Short name T170
Test name
Test status
Simulation time 51825578726 ps
CPU time 84.05 seconds
Started Jul 02 09:23:54 AM PDT 24
Finished Jul 02 09:25:20 AM PDT 24
Peak memory 199872 kb
Host smart-6110ef41-6276-41c0-be08-9f88698531df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718114039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1718114039
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.901224220
Short name T227
Test name
Test status
Simulation time 49101738441 ps
CPU time 40.87 seconds
Started Jul 02 09:26:50 AM PDT 24
Finished Jul 02 09:27:31 AM PDT 24
Peak memory 199992 kb
Host smart-1776750f-52d7-4be0-8c9c-96fb21273be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901224220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.901224220
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3712849475
Short name T161
Test name
Test status
Simulation time 64192960559 ps
CPU time 38.4 seconds
Started Jul 02 09:26:55 AM PDT 24
Finished Jul 02 09:27:34 AM PDT 24
Peak memory 199936 kb
Host smart-d5e3e2d9-e43b-4a70-9bb6-fc0f534807a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712849475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3712849475
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2875191867
Short name T222
Test name
Test status
Simulation time 16668776422 ps
CPU time 26.13 seconds
Started Jul 02 09:26:54 AM PDT 24
Finished Jul 02 09:27:21 AM PDT 24
Peak memory 199968 kb
Host smart-1aaf51b6-3aec-407c-9d87-67241f191a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875191867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2875191867
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1724522177
Short name T236
Test name
Test status
Simulation time 16639488860 ps
CPU time 21.54 seconds
Started Jul 02 09:27:02 AM PDT 24
Finished Jul 02 09:27:23 AM PDT 24
Peak memory 199932 kb
Host smart-2464375c-037e-4c12-8146-4814254f35cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724522177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1724522177
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.900841578
Short name T178
Test name
Test status
Simulation time 23722782239 ps
CPU time 36.52 seconds
Started Jul 02 09:27:07 AM PDT 24
Finished Jul 02 09:27:44 AM PDT 24
Peak memory 199992 kb
Host smart-f95a9921-bdda-4ef5-8a46-0d04232d33cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900841578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.900841578
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all.1780225716
Short name T250
Test name
Test status
Simulation time 254617076236 ps
CPU time 565.6 seconds
Started Jul 02 09:25:35 AM PDT 24
Finished Jul 02 09:35:01 AM PDT 24
Peak memory 199936 kb
Host smart-8d3828cd-0596-48c2-bbb3-b3ce297dd048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780225716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1780225716
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.4244924533
Short name T256
Test name
Test status
Simulation time 87617573755 ps
CPU time 60.48 seconds
Started Jul 02 09:25:54 AM PDT 24
Finished Jul 02 09:26:55 AM PDT 24
Peak memory 200012 kb
Host smart-0c821ba8-71ee-46e6-9032-b571af883975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244924533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4244924533
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.169744186
Short name T237
Test name
Test status
Simulation time 44391610821 ps
CPU time 15.75 seconds
Started Jul 02 09:25:56 AM PDT 24
Finished Jul 02 09:26:13 AM PDT 24
Peak memory 199928 kb
Host smart-97949f47-9345-41f5-acd8-877b31477585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169744186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.169744186
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3269915876
Short name T1114
Test name
Test status
Simulation time 17650358 ps
CPU time 0.77 seconds
Started Jul 02 09:45:55 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 197056 kb
Host smart-9b125d5a-accb-4553-a71f-3696c4e5d803
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269915876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3269915876
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1416460506
Short name T61
Test name
Test status
Simulation time 226982421 ps
CPU time 2.22 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 198412 kb
Host smart-9b4c3839-90cd-4566-9d25-67af5cc2e782
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416460506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1416460506
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.140016951
Short name T1090
Test name
Test status
Simulation time 39250671 ps
CPU time 0.59 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:45:56 AM PDT 24
Peak memory 196176 kb
Host smart-2e787506-a2ca-4fc3-afc2-b61f3746dda8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140016951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.140016951
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1839340124
Short name T1117
Test name
Test status
Simulation time 27583375 ps
CPU time 0.85 seconds
Started Jul 02 09:45:55 AM PDT 24
Finished Jul 02 09:45:58 AM PDT 24
Peak memory 200152 kb
Host smart-374b43cc-0403-459e-86ef-15ae174ab1ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839340124 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1839340124
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.563611781
Short name T74
Test name
Test status
Simulation time 15897789 ps
CPU time 0.64 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 196252 kb
Host smart-396496d9-c304-474c-914f-9aa03fc8ad5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563611781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.563611781
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.705415045
Short name T1120
Test name
Test status
Simulation time 35444366 ps
CPU time 0.58 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 195096 kb
Host smart-a9c51dd5-f98d-4096-ba42-0e3dbe10261e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705415045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.705415045
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2250831155
Short name T1208
Test name
Test status
Simulation time 117078123 ps
CPU time 0.77 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 197780 kb
Host smart-50edaea4-b3fe-4624-8ae9-761239815e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250831155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2250831155
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1592465862
Short name T1185
Test name
Test status
Simulation time 90268011 ps
CPU time 1.43 seconds
Started Jul 02 09:45:55 AM PDT 24
Finished Jul 02 09:45:58 AM PDT 24
Peak memory 200816 kb
Host smart-38eca755-5702-4072-b8ad-a89d39599fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592465862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1592465862
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.424482564
Short name T87
Test name
Test status
Simulation time 527484134 ps
CPU time 1.32 seconds
Started Jul 02 09:45:57 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 200116 kb
Host smart-3fd17a2c-5e08-40f6-9ed8-e4287a993b85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424482564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.424482564
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3584643956
Short name T59
Test name
Test status
Simulation time 56378515 ps
CPU time 0.8 seconds
Started Jul 02 09:45:55 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 197044 kb
Host smart-77319942-3ca4-490c-8343-9821059e236c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584643956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3584643956
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1691356632
Short name T1115
Test name
Test status
Simulation time 403308815 ps
CPU time 1.55 seconds
Started Jul 02 09:46:06 AM PDT 24
Finished Jul 02 09:46:09 AM PDT 24
Peak memory 198560 kb
Host smart-5fb43b4e-d506-4b88-b4a6-08b58c8bb7e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691356632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1691356632
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2067157471
Short name T1126
Test name
Test status
Simulation time 26827862 ps
CPU time 0.61 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:45:57 AM PDT 24
Peak memory 196212 kb
Host smart-21d059a9-8656-40d4-8ab4-424bc42e69f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067157471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2067157471
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1567473099
Short name T1142
Test name
Test status
Simulation time 177844276 ps
CPU time 0.69 seconds
Started Jul 02 09:45:57 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 199084 kb
Host smart-2034b906-a093-4457-9574-12f7b98336b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567473099 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1567473099
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3091142015
Short name T82
Test name
Test status
Simulation time 17605477 ps
CPU time 0.63 seconds
Started Jul 02 09:45:55 AM PDT 24
Finished Jul 02 09:45:58 AM PDT 24
Peak memory 196272 kb
Host smart-120298c4-0871-4cfb-b8e2-d522e6d9c934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091142015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3091142015
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3755399906
Short name T1150
Test name
Test status
Simulation time 12953600 ps
CPU time 0.62 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:45:56 AM PDT 24
Peak memory 195180 kb
Host smart-03404e2d-7c97-4f1f-8b7f-b608b0659cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755399906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3755399906
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1812418133
Short name T1181
Test name
Test status
Simulation time 36676860 ps
CPU time 0.83 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 197788 kb
Host smart-ed3f3135-eb0c-4e3f-bb7a-4175dbe6f9c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812418133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1812418133
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.634777454
Short name T1187
Test name
Test status
Simulation time 45080436 ps
CPU time 2.2 seconds
Started Jul 02 09:45:55 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 200856 kb
Host smart-d30a1a59-9936-4c69-8a30-307ded8c23fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634777454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.634777454
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1717325531
Short name T1179
Test name
Test status
Simulation time 39724754 ps
CPU time 1.01 seconds
Started Jul 02 09:46:06 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 200524 kb
Host smart-1f930cbf-0401-47e4-a3a5-0f7ad0ae02d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717325531 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1717325531
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1371251303
Short name T58
Test name
Test status
Simulation time 15925893 ps
CPU time 0.63 seconds
Started Jul 02 09:46:06 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 196200 kb
Host smart-dc11eccb-a30e-4ee5-bcb8-6285c2b14588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371251303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1371251303
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2771585420
Short name T1092
Test name
Test status
Simulation time 44156149 ps
CPU time 0.57 seconds
Started Jul 02 09:46:03 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 195124 kb
Host smart-05bab98e-6cab-402a-b946-344b8cd194cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771585420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2771585420
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.227751630
Short name T1195
Test name
Test status
Simulation time 22467364 ps
CPU time 0.68 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 196648 kb
Host smart-5bdb394b-6fa1-4c4a-81d0-28816e63b751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227751630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.227751630
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2437622672
Short name T1175
Test name
Test status
Simulation time 139140014 ps
CPU time 1.71 seconds
Started Jul 02 09:46:02 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 200860 kb
Host smart-b080bc1e-bbeb-4c8d-a1da-20d9c66f6a8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437622672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2437622672
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2197725870
Short name T125
Test name
Test status
Simulation time 407558026 ps
CPU time 1.23 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 200188 kb
Host smart-2d1d6a01-d14f-4c01-9e81-8f30f1725046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197725870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2197725870
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3605028355
Short name T1095
Test name
Test status
Simulation time 37120067 ps
CPU time 0.72 seconds
Started Jul 02 09:46:06 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 199260 kb
Host smart-bac1f209-d42c-42e9-8fca-162a9e0d9b19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605028355 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3605028355
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.473430546
Short name T1149
Test name
Test status
Simulation time 14772108 ps
CPU time 0.6 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 196180 kb
Host smart-8b0717f0-169a-44b5-b400-bf32bf37f2c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473430546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.473430546
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.408887268
Short name T1132
Test name
Test status
Simulation time 104838035 ps
CPU time 0.58 seconds
Started Jul 02 09:46:05 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 195120 kb
Host smart-b3145769-70f4-4ffd-9ff8-dab4a14f4d9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408887268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.408887268
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3533592076
Short name T77
Test name
Test status
Simulation time 54582313 ps
CPU time 0.77 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 195428 kb
Host smart-ac760cbd-a335-4a8e-a917-8b43fd21b568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533592076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3533592076
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3565929547
Short name T1106
Test name
Test status
Simulation time 31890473 ps
CPU time 1.66 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 200856 kb
Host smart-4b816940-6fa9-476f-8d2d-f0e3b81f8a86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565929547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3565929547
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4054781753
Short name T1196
Test name
Test status
Simulation time 82381500 ps
CPU time 1.31 seconds
Started Jul 02 09:46:03 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 199884 kb
Host smart-e1d6a1ce-f6dc-4641-adeb-18f109b2b4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054781753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4054781753
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2629842411
Short name T1097
Test name
Test status
Simulation time 75990980 ps
CPU time 0.69 seconds
Started Jul 02 09:46:13 AM PDT 24
Finished Jul 02 09:46:15 AM PDT 24
Peak memory 198504 kb
Host smart-5c56097d-2e92-4ab7-85ec-3a61fbb35c0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629842411 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2629842411
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.4110867071
Short name T1167
Test name
Test status
Simulation time 14873743 ps
CPU time 0.61 seconds
Started Jul 02 09:46:14 AM PDT 24
Finished Jul 02 09:46:15 AM PDT 24
Peak memory 196168 kb
Host smart-6360ae58-39bf-4fbf-86e6-9a247557eaa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110867071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.4110867071
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.828783946
Short name T1164
Test name
Test status
Simulation time 99366730 ps
CPU time 0.57 seconds
Started Jul 02 09:46:02 AM PDT 24
Finished Jul 02 09:46:05 AM PDT 24
Peak memory 195160 kb
Host smart-5057ce34-9e47-4227-b2a6-96af7e4773ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828783946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.828783946
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2913181661
Short name T1180
Test name
Test status
Simulation time 26419133 ps
CPU time 0.76 seconds
Started Jul 02 09:46:09 AM PDT 24
Finished Jul 02 09:46:10 AM PDT 24
Peak memory 196636 kb
Host smart-74828df1-1fa4-4311-945c-4ba6ec2d1b7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913181661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2913181661
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1503037927
Short name T1189
Test name
Test status
Simulation time 129280227 ps
CPU time 1.92 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 200840 kb
Host smart-8d9388c3-cd39-43b2-8829-dbf4f4fb3343
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503037927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1503037927
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.790596818
Short name T1191
Test name
Test status
Simulation time 95345519 ps
CPU time 0.95 seconds
Started Jul 02 09:46:11 AM PDT 24
Finished Jul 02 09:46:13 AM PDT 24
Peak memory 200584 kb
Host smart-4e6e0e96-3560-4db1-a30c-171cc04a3e3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790596818 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.790596818
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1069007516
Short name T1146
Test name
Test status
Simulation time 11513771 ps
CPU time 0.66 seconds
Started Jul 02 09:46:10 AM PDT 24
Finished Jul 02 09:46:12 AM PDT 24
Peak memory 196340 kb
Host smart-89622178-3f74-409b-b452-9af3b8467ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069007516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1069007516
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2136139425
Short name T1112
Test name
Test status
Simulation time 29728360 ps
CPU time 0.62 seconds
Started Jul 02 09:46:10 AM PDT 24
Finished Jul 02 09:46:12 AM PDT 24
Peak memory 195156 kb
Host smart-2d629338-fabf-4ff5-bf82-47bbf03815c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136139425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2136139425
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4257095419
Short name T80
Test name
Test status
Simulation time 77154702 ps
CPU time 0.74 seconds
Started Jul 02 09:46:11 AM PDT 24
Finished Jul 02 09:46:12 AM PDT 24
Peak memory 196528 kb
Host smart-faaf7f70-96d5-4aa3-86c8-43414ad14e70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257095419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.4257095419
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1525162567
Short name T1134
Test name
Test status
Simulation time 109076030 ps
CPU time 1.48 seconds
Started Jul 02 09:46:10 AM PDT 24
Finished Jul 02 09:46:13 AM PDT 24
Peak memory 200816 kb
Host smart-15257f4e-69ad-4d28-9f37-cd5f4e4acab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525162567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1525162567
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3310859871
Short name T83
Test name
Test status
Simulation time 118761087 ps
CPU time 1.35 seconds
Started Jul 02 09:46:11 AM PDT 24
Finished Jul 02 09:46:14 AM PDT 24
Peak memory 200080 kb
Host smart-b527b9ea-4b8b-44f3-be3d-e06c21485d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310859871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3310859871
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2645323914
Short name T1129
Test name
Test status
Simulation time 58837428 ps
CPU time 0.78 seconds
Started Jul 02 09:46:11 AM PDT 24
Finished Jul 02 09:46:13 AM PDT 24
Peak memory 199588 kb
Host smart-1df6bd9b-3b41-4fd2-a7de-4a5675db90b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645323914 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2645323914
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1518858456
Short name T1119
Test name
Test status
Simulation time 15937987 ps
CPU time 0.59 seconds
Started Jul 02 09:46:09 AM PDT 24
Finished Jul 02 09:46:10 AM PDT 24
Peak memory 195188 kb
Host smart-017d9594-1a09-476d-82bb-c9ccb7fa6085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518858456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1518858456
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4186318420
Short name T1174
Test name
Test status
Simulation time 67079775 ps
CPU time 0.81 seconds
Started Jul 02 09:46:12 AM PDT 24
Finished Jul 02 09:46:14 AM PDT 24
Peak memory 196816 kb
Host smart-837bba1d-65d3-48af-810a-36073d65e3aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186318420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4186318420
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3439787803
Short name T1103
Test name
Test status
Simulation time 291568459 ps
CPU time 1.73 seconds
Started Jul 02 09:46:10 AM PDT 24
Finished Jul 02 09:46:13 AM PDT 24
Peak memory 200852 kb
Host smart-44035b94-a207-44f7-9b58-14de3cf53f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439787803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3439787803
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2444299086
Short name T1151
Test name
Test status
Simulation time 162238145 ps
CPU time 0.79 seconds
Started Jul 02 09:46:13 AM PDT 24
Finished Jul 02 09:46:15 AM PDT 24
Peak memory 199516 kb
Host smart-a28a09a7-4e76-44d7-8a93-c9f56e347e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444299086 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2444299086
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3875006495
Short name T60
Test name
Test status
Simulation time 72068676 ps
CPU time 0.61 seconds
Started Jul 02 09:46:10 AM PDT 24
Finished Jul 02 09:46:12 AM PDT 24
Peak memory 196348 kb
Host smart-da7b3a2e-b4b3-4527-b93a-389724e06cfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875006495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3875006495
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3752204398
Short name T1123
Test name
Test status
Simulation time 61513863 ps
CPU time 0.57 seconds
Started Jul 02 09:46:13 AM PDT 24
Finished Jul 02 09:46:15 AM PDT 24
Peak memory 195156 kb
Host smart-6e923951-e8d1-411d-9f62-b42aeb571fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752204398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3752204398
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1544983354
Short name T1200
Test name
Test status
Simulation time 117206473 ps
CPU time 0.77 seconds
Started Jul 02 09:46:12 AM PDT 24
Finished Jul 02 09:46:14 AM PDT 24
Peak memory 197648 kb
Host smart-51554e37-cf48-47d6-b33e-8e6bd71ad4e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544983354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1544983354
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2027225967
Short name T1176
Test name
Test status
Simulation time 155632859 ps
CPU time 1.23 seconds
Started Jul 02 09:46:08 AM PDT 24
Finished Jul 02 09:46:10 AM PDT 24
Peak memory 200796 kb
Host smart-6e9f5458-6bc2-4c80-a69b-d0d50b391a1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027225967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2027225967
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3244901063
Short name T127
Test name
Test status
Simulation time 123237551 ps
CPU time 1.28 seconds
Started Jul 02 09:46:10 AM PDT 24
Finished Jul 02 09:46:12 AM PDT 24
Peak memory 200212 kb
Host smart-e8053a51-de3e-4924-8b83-89777f083e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244901063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3244901063
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1378455570
Short name T1099
Test name
Test status
Simulation time 27545284 ps
CPU time 1.19 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 200784 kb
Host smart-9e918a10-41cc-4ef1-8ea4-12556046d100
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378455570 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1378455570
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3373585154
Short name T1154
Test name
Test status
Simulation time 14229049 ps
CPU time 0.6 seconds
Started Jul 02 09:46:16 AM PDT 24
Finished Jul 02 09:46:18 AM PDT 24
Peak memory 196180 kb
Host smart-0f8643b6-6969-4ea9-b3dc-dff6069010c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373585154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3373585154
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1215655954
Short name T1113
Test name
Test status
Simulation time 11716594 ps
CPU time 0.58 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 195192 kb
Host smart-3200d07c-0300-4392-b8b8-48761371ec62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215655954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1215655954
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3694276503
Short name T1184
Test name
Test status
Simulation time 61323520 ps
CPU time 0.66 seconds
Started Jul 02 09:46:12 AM PDT 24
Finished Jul 02 09:46:14 AM PDT 24
Peak memory 195436 kb
Host smart-421ddf3a-cf88-40df-902f-a48bc2bd7039
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694276503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3694276503
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3732624839
Short name T1163
Test name
Test status
Simulation time 123707877 ps
CPU time 1.65 seconds
Started Jul 02 09:46:12 AM PDT 24
Finished Jul 02 09:46:15 AM PDT 24
Peak memory 200844 kb
Host smart-932e0dcf-0299-4be3-9f24-3dfc7a3c8ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732624839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3732624839
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2572742935
Short name T128
Test name
Test status
Simulation time 248301831 ps
CPU time 0.89 seconds
Started Jul 02 09:46:16 AM PDT 24
Finished Jul 02 09:46:18 AM PDT 24
Peak memory 199860 kb
Host smart-2df8d2a3-8245-426e-be7e-24b5eac99b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572742935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2572742935
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1056857144
Short name T1194
Test name
Test status
Simulation time 154803774 ps
CPU time 0.65 seconds
Started Jul 02 09:46:14 AM PDT 24
Finished Jul 02 09:46:15 AM PDT 24
Peak memory 198008 kb
Host smart-f7923f46-c583-4b0b-bf48-a12e53da7d6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056857144 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1056857144
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3687640728
Short name T57
Test name
Test status
Simulation time 48469456 ps
CPU time 0.58 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 196180 kb
Host smart-ac44b21f-fd64-40c0-bc9b-396d04739a46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687640728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3687640728
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3116034010
Short name T1088
Test name
Test status
Simulation time 48599312 ps
CPU time 0.6 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 195140 kb
Host smart-f7cf67a9-bd70-4615-8eee-676ad1ea1700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116034010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3116034010
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4286681495
Short name T81
Test name
Test status
Simulation time 122609853 ps
CPU time 0.76 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 197316 kb
Host smart-9b375321-a34e-49a2-984f-39dc7e9f46dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286681495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.4286681495
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.644004049
Short name T1168
Test name
Test status
Simulation time 146755750 ps
CPU time 1.62 seconds
Started Jul 02 09:46:16 AM PDT 24
Finished Jul 02 09:46:20 AM PDT 24
Peak memory 200764 kb
Host smart-68eb4d5e-2ba3-4320-b7e9-d157348d0299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644004049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.644004049
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1033979634
Short name T1094
Test name
Test status
Simulation time 18989853 ps
CPU time 0.68 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:18 AM PDT 24
Peak memory 197748 kb
Host smart-2ad18036-3ee2-415e-b8b2-b22be34301d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033979634 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1033979634
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.158540531
Short name T1193
Test name
Test status
Simulation time 61916041 ps
CPU time 0.64 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 196304 kb
Host smart-f7d9e773-c27e-4327-be25-60acf90258fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158540531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.158540531
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2564228260
Short name T1096
Test name
Test status
Simulation time 51382615 ps
CPU time 0.61 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 195160 kb
Host smart-a39be267-cee5-4414-9412-37ff3ce5f9cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564228260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2564228260
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1872651293
Short name T1186
Test name
Test status
Simulation time 27620068 ps
CPU time 0.78 seconds
Started Jul 02 09:46:13 AM PDT 24
Finished Jul 02 09:46:15 AM PDT 24
Peak memory 198440 kb
Host smart-42f45fce-d56b-47d3-a006-6b308e6784d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872651293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1872651293
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1039225224
Short name T1140
Test name
Test status
Simulation time 67283029 ps
CPU time 1.82 seconds
Started Jul 02 09:46:16 AM PDT 24
Finished Jul 02 09:46:19 AM PDT 24
Peak memory 200692 kb
Host smart-69937c84-4f07-4d24-b53b-ade48cbe732f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039225224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1039225224
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2435366435
Short name T1182
Test name
Test status
Simulation time 140160703 ps
CPU time 1.25 seconds
Started Jul 02 09:46:14 AM PDT 24
Finished Jul 02 09:46:16 AM PDT 24
Peak memory 200004 kb
Host smart-8ae688bb-a757-4a53-8245-0cff1c0aeabf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435366435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2435366435
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4197628924
Short name T1161
Test name
Test status
Simulation time 60340658 ps
CPU time 0.7 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 198192 kb
Host smart-09c38d7c-22a2-48ef-aebb-d00f492a4c50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197628924 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.4197628924
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1774729762
Short name T1198
Test name
Test status
Simulation time 46076313 ps
CPU time 0.61 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:23 AM PDT 24
Peak memory 196220 kb
Host smart-ab907f44-db18-4727-a50b-d23ebb8340aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774729762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1774729762
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.4283738230
Short name T1157
Test name
Test status
Simulation time 50982372 ps
CPU time 0.57 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 195208 kb
Host smart-075bb65b-c728-4556-a13a-9c4e43dd48e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283738230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.4283738230
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.900522570
Short name T79
Test name
Test status
Simulation time 15118340 ps
CPU time 0.63 seconds
Started Jul 02 09:46:16 AM PDT 24
Finished Jul 02 09:46:18 AM PDT 24
Peak memory 195180 kb
Host smart-d59d2c16-f287-40a8-9f40-d29f16b359d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900522570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.900522570
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.884448525
Short name T1124
Test name
Test status
Simulation time 68862762 ps
CPU time 1.02 seconds
Started Jul 02 09:46:14 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 200612 kb
Host smart-281a6287-c769-4826-bbb4-b62a4fa5fdc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884448525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.884448525
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1417048540
Short name T1217
Test name
Test status
Simulation time 171704492 ps
CPU time 0.96 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 199504 kb
Host smart-c6702e81-bcad-41b2-96f3-f044d27896b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417048540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1417048540
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1748429967
Short name T62
Test name
Test status
Simulation time 26226478 ps
CPU time 0.84 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 197204 kb
Host smart-cffdaff3-c853-4da5-ad8c-120ee606a6c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748429967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1748429967
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2355801209
Short name T1136
Test name
Test status
Simulation time 367701936 ps
CPU time 1.47 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 198336 kb
Host smart-07b2c942-945d-452c-bde7-d87c8f885db3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355801209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2355801209
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3471935049
Short name T1172
Test name
Test status
Simulation time 42431382 ps
CPU time 0.6 seconds
Started Jul 02 09:46:05 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 196180 kb
Host smart-51679cba-fc92-4db2-b549-34f7891283d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471935049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3471935049
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4188575341
Short name T1165
Test name
Test status
Simulation time 59925419 ps
CPU time 0.89 seconds
Started Jul 02 09:45:58 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 200628 kb
Host smart-61085448-8d67-4a6e-bb97-25845e77687f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188575341 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.4188575341
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1686419303
Short name T1145
Test name
Test status
Simulation time 32742391 ps
CPU time 0.6 seconds
Started Jul 02 09:45:57 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 196344 kb
Host smart-e78cb0fa-aafb-48e1-8e89-24900d7d4a6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686419303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1686419303
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2184453199
Short name T1159
Test name
Test status
Simulation time 11568306 ps
CPU time 0.62 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 195184 kb
Host smart-a6737f85-230b-4b76-ae8b-bcd34351c9cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184453199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2184453199
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3829466852
Short name T76
Test name
Test status
Simulation time 20402912 ps
CPU time 0.62 seconds
Started Jul 02 09:45:57 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 196424 kb
Host smart-1de803ab-cf84-4c12-b446-26965a773c62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829466852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3829466852
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2837240282
Short name T1188
Test name
Test status
Simulation time 97699212 ps
CPU time 2.15 seconds
Started Jul 02 09:46:00 AM PDT 24
Finished Jul 02 09:46:04 AM PDT 24
Peak memory 200824 kb
Host smart-8e04686a-903c-48ff-836e-8b9e73b39be1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837240282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2837240282
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1273753143
Short name T92
Test name
Test status
Simulation time 106569312 ps
CPU time 0.94 seconds
Started Jul 02 09:45:57 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 199768 kb
Host smart-e31ff0db-63d2-4bb6-93d3-c18796eb4cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273753143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1273753143
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2046639864
Short name T1105
Test name
Test status
Simulation time 18632000 ps
CPU time 0.54 seconds
Started Jul 02 09:46:16 AM PDT 24
Finished Jul 02 09:46:18 AM PDT 24
Peak memory 195124 kb
Host smart-8bbd990a-e7ba-4824-812a-0cd806ceea3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046639864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2046639864
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.793815110
Short name T1171
Test name
Test status
Simulation time 115257767 ps
CPU time 0.63 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 195092 kb
Host smart-7acc0b96-ccc0-4d4b-89b9-f6e6641fd7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793815110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.793815110
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1532444788
Short name T1139
Test name
Test status
Simulation time 15175225 ps
CPU time 0.54 seconds
Started Jul 02 09:46:14 AM PDT 24
Finished Jul 02 09:46:16 AM PDT 24
Peak memory 195200 kb
Host smart-bba17d20-3857-42df-9e4e-88a3e13c96b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532444788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1532444788
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1202449361
Short name T1127
Test name
Test status
Simulation time 16511911 ps
CPU time 0.58 seconds
Started Jul 02 09:46:16 AM PDT 24
Finished Jul 02 09:46:19 AM PDT 24
Peak memory 195056 kb
Host smart-7a2150cf-7603-4056-9d07-45f78ebcc530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202449361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1202449361
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2197521279
Short name T1101
Test name
Test status
Simulation time 40528617 ps
CPU time 0.59 seconds
Started Jul 02 09:46:16 AM PDT 24
Finished Jul 02 09:46:18 AM PDT 24
Peak memory 195200 kb
Host smart-1f76394d-5a7e-438b-b5ef-d55665e4cb7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197521279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2197521279
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2060198643
Short name T1207
Test name
Test status
Simulation time 42271162 ps
CPU time 0.54 seconds
Started Jul 02 09:46:18 AM PDT 24
Finished Jul 02 09:46:19 AM PDT 24
Peak memory 195036 kb
Host smart-6f83eea0-1b2a-4d95-b702-122429ecbd0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060198643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2060198643
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2971501936
Short name T1144
Test name
Test status
Simulation time 33196824 ps
CPU time 0.53 seconds
Started Jul 02 09:46:18 AM PDT 24
Finished Jul 02 09:46:19 AM PDT 24
Peak memory 195032 kb
Host smart-4e295706-f12e-4c33-8726-8616354aa016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971501936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2971501936
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1152828487
Short name T1170
Test name
Test status
Simulation time 50132070 ps
CPU time 0.58 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 195124 kb
Host smart-a50ecd06-d37b-4eea-bed7-d52ed52d6bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152828487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1152828487
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3625883549
Short name T1138
Test name
Test status
Simulation time 13083608 ps
CPU time 0.6 seconds
Started Jul 02 09:46:14 AM PDT 24
Finished Jul 02 09:46:16 AM PDT 24
Peak memory 195100 kb
Host smart-9a0558a7-9f96-400e-8caf-9c791c4258e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625883549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3625883549
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3727451372
Short name T1197
Test name
Test status
Simulation time 15017640 ps
CPU time 0.62 seconds
Started Jul 02 09:46:15 AM PDT 24
Finished Jul 02 09:46:16 AM PDT 24
Peak memory 195168 kb
Host smart-38cc8d14-ffc7-436d-b963-5344f23a6c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727451372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3727451372
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1974579695
Short name T1093
Test name
Test status
Simulation time 80068901 ps
CPU time 0.88 seconds
Started Jul 02 09:46:05 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 196948 kb
Host smart-87754ade-4413-4c55-89e4-965a21730232
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974579695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1974579695
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1402911940
Short name T1160
Test name
Test status
Simulation time 119309057 ps
CPU time 1.66 seconds
Started Jul 02 09:45:58 AM PDT 24
Finished Jul 02 09:46:02 AM PDT 24
Peak memory 198612 kb
Host smart-b783b15c-4fce-4428-aebb-0b878f6e42d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402911940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1402911940
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3623865721
Short name T1109
Test name
Test status
Simulation time 37064484 ps
CPU time 0.58 seconds
Started Jul 02 09:45:55 AM PDT 24
Finished Jul 02 09:45:58 AM PDT 24
Peak memory 196236 kb
Host smart-b6e08400-efcf-4386-ac5d-8a3a8702858a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623865721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3623865721
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.936155194
Short name T1212
Test name
Test status
Simulation time 117929103 ps
CPU time 0.79 seconds
Started Jul 02 09:46:05 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 199236 kb
Host smart-fa67d474-607f-40fb-bbaa-32a7f73c1091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936155194 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.936155194
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3980809169
Short name T1135
Test name
Test status
Simulation time 34904765 ps
CPU time 0.63 seconds
Started Jul 02 09:46:05 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 196176 kb
Host smart-30c711a3-abb3-4cd3-bd8a-1a3891ac97dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980809169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3980809169
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1490535291
Short name T1178
Test name
Test status
Simulation time 26106068 ps
CPU time 0.62 seconds
Started Jul 02 09:46:01 AM PDT 24
Finished Jul 02 09:46:04 AM PDT 24
Peak memory 195052 kb
Host smart-9a2c8b6d-dada-4ebb-8ffa-749a52b27807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490535291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1490535291
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1495090800
Short name T1130
Test name
Test status
Simulation time 34818076 ps
CPU time 0.6 seconds
Started Jul 02 09:45:57 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 195220 kb
Host smart-d02d72ba-68a7-410a-ab4f-efca21782040
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495090800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1495090800
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1213806014
Short name T1148
Test name
Test status
Simulation time 57981368 ps
CPU time 1.38 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 200792 kb
Host smart-a6c26c8a-37d8-41df-8f3e-e51cc7eed245
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213806014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1213806014
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.4240986463
Short name T126
Test name
Test status
Simulation time 214395055 ps
CPU time 0.94 seconds
Started Jul 02 09:46:02 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 199708 kb
Host smart-ec006320-58ef-45e6-ab2e-390410f81e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240986463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.4240986463
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.4016732625
Short name T1192
Test name
Test status
Simulation time 22067263 ps
CPU time 0.55 seconds
Started Jul 02 09:46:18 AM PDT 24
Finished Jul 02 09:46:19 AM PDT 24
Peak memory 195168 kb
Host smart-1e7fb4c2-18cb-49a1-b1ce-9f5c2ba80339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016732625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.4016732625
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.259740644
Short name T1201
Test name
Test status
Simulation time 35604167 ps
CPU time 0.57 seconds
Started Jul 02 09:46:16 AM PDT 24
Finished Jul 02 09:46:19 AM PDT 24
Peak memory 195052 kb
Host smart-1387640c-0e47-45eb-9e3c-42dd6a213ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259740644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.259740644
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3262318448
Short name T1102
Test name
Test status
Simulation time 63544606 ps
CPU time 0.59 seconds
Started Jul 02 09:46:18 AM PDT 24
Finished Jul 02 09:46:20 AM PDT 24
Peak memory 195180 kb
Host smart-0fc2ecd5-390b-4d30-9852-2b693252c541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262318448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3262318448
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3712742092
Short name T1141
Test name
Test status
Simulation time 20255472 ps
CPU time 0.55 seconds
Started Jul 02 09:46:23 AM PDT 24
Finished Jul 02 09:46:24 AM PDT 24
Peak memory 195168 kb
Host smart-5af91dc4-60a6-4ea4-8c37-7dde5cd4d75d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712742092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3712742092
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.4098303432
Short name T1116
Test name
Test status
Simulation time 12401900 ps
CPU time 0.56 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 195120 kb
Host smart-d8e951df-e62a-4de3-90c6-bd832f51f01d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098303432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4098303432
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.771461250
Short name T1111
Test name
Test status
Simulation time 30664512 ps
CPU time 0.59 seconds
Started Jul 02 09:46:23 AM PDT 24
Finished Jul 02 09:46:24 AM PDT 24
Peak memory 195192 kb
Host smart-588d1ce1-58b8-4a79-9b50-33944a1441c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771461250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.771461250
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1056593422
Short name T1211
Test name
Test status
Simulation time 22570852 ps
CPU time 0.6 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:21 AM PDT 24
Peak memory 195164 kb
Host smart-8544018b-c25d-4b1e-8920-e64a77a6ea2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056593422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1056593422
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1518523073
Short name T1133
Test name
Test status
Simulation time 13607051 ps
CPU time 0.58 seconds
Started Jul 02 09:46:25 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 195128 kb
Host smart-d6494be3-091f-4da8-829f-a1c3fd948e79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518523073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1518523073
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.742077202
Short name T1183
Test name
Test status
Simulation time 48156226 ps
CPU time 0.54 seconds
Started Jul 02 09:46:21 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 195216 kb
Host smart-2802eb08-9a23-4f3b-a7ec-5a14c3faeea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742077202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.742077202
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.206067649
Short name T1108
Test name
Test status
Simulation time 63199619 ps
CPU time 0.57 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 195140 kb
Host smart-67e074f2-9495-4f71-8fbe-003ef256856b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206067649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.206067649
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1352694938
Short name T1205
Test name
Test status
Simulation time 27371577 ps
CPU time 0.75 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 196968 kb
Host smart-2ac7445c-a101-4bcd-b323-596466409830
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352694938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1352694938
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4015528922
Short name T64
Test name
Test status
Simulation time 225228822 ps
CPU time 2.34 seconds
Started Jul 02 09:45:55 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 198684 kb
Host smart-b685fbc8-2700-45eb-b95c-929dcee02255
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015528922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4015528922
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2529884936
Short name T1158
Test name
Test status
Simulation time 57454508 ps
CPU time 0.58 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 196176 kb
Host smart-b7fd57cc-dc6a-49db-8ad4-36422b090f50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529884936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2529884936
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3546319883
Short name T1152
Test name
Test status
Simulation time 110890796 ps
CPU time 0.81 seconds
Started Jul 02 09:46:00 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 199360 kb
Host smart-6e4b20b2-fab5-4e40-abd3-dd9477d43187
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546319883 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3546319883
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2054664477
Short name T1216
Test name
Test status
Simulation time 56439159 ps
CPU time 0.64 seconds
Started Jul 02 09:45:57 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 196376 kb
Host smart-53c84418-d8b6-4c08-93fd-03c545f192f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054664477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2054664477
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3703412767
Short name T1202
Test name
Test status
Simulation time 10865012 ps
CPU time 0.6 seconds
Started Jul 02 09:45:57 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 195348 kb
Host smart-a23dfc7b-b482-45ad-a632-675db853f0a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703412767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3703412767
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2874086281
Short name T1137
Test name
Test status
Simulation time 19437857 ps
CPU time 0.67 seconds
Started Jul 02 09:46:00 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 196304 kb
Host smart-b07f138d-9c0a-461b-bf46-1ef19ccbaafd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874086281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2874086281
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1043334759
Short name T1098
Test name
Test status
Simulation time 30219213 ps
CPU time 1.49 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 200752 kb
Host smart-10c642bb-b8fb-45f2-aadc-5d0d8c8651e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043334759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1043334759
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2193536292
Short name T91
Test name
Test status
Simulation time 50368951 ps
CPU time 0.94 seconds
Started Jul 02 09:45:58 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 199700 kb
Host smart-1de0eab4-4f49-40d5-a79e-48a2db8f44e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193536292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2193536292
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3154136652
Short name T1219
Test name
Test status
Simulation time 10797230 ps
CPU time 0.61 seconds
Started Jul 02 09:46:19 AM PDT 24
Finished Jul 02 09:46:20 AM PDT 24
Peak memory 195128 kb
Host smart-b13561fc-a51d-40a1-9ccf-ee6687173f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154136652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3154136652
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2283782414
Short name T1210
Test name
Test status
Simulation time 57855591 ps
CPU time 0.54 seconds
Started Jul 02 09:46:19 AM PDT 24
Finished Jul 02 09:46:21 AM PDT 24
Peak memory 195116 kb
Host smart-24b003a0-52ac-43dd-8541-ae7ee2a81e7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283782414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2283782414
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1561257732
Short name T1162
Test name
Test status
Simulation time 52696845 ps
CPU time 0.59 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 195180 kb
Host smart-de0c0799-2804-4b8c-ac02-822b528e8313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561257732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1561257732
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1002046539
Short name T1121
Test name
Test status
Simulation time 13524051 ps
CPU time 0.59 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:21 AM PDT 24
Peak memory 195204 kb
Host smart-527580b9-68f3-4a7a-939d-0cbef8366c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002046539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1002046539
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3624117815
Short name T1107
Test name
Test status
Simulation time 36533612 ps
CPU time 0.53 seconds
Started Jul 02 09:46:21 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 195204 kb
Host smart-c7a77676-e8f3-4208-a9fa-fb76cd55b3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624117815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3624117815
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.118286494
Short name T1156
Test name
Test status
Simulation time 12798695 ps
CPU time 0.56 seconds
Started Jul 02 09:46:20 AM PDT 24
Finished Jul 02 09:46:23 AM PDT 24
Peak memory 195188 kb
Host smart-0b5eff31-439a-4d73-a80d-64e6b94929d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118286494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.118286494
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2125585715
Short name T1100
Test name
Test status
Simulation time 119189199 ps
CPU time 0.59 seconds
Started Jul 02 09:46:25 AM PDT 24
Finished Jul 02 09:46:28 AM PDT 24
Peak memory 195196 kb
Host smart-c8a15fc7-52af-47e8-9595-b1d53b596051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125585715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2125585715
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.872165357
Short name T1215
Test name
Test status
Simulation time 36793305 ps
CPU time 0.56 seconds
Started Jul 02 09:46:24 AM PDT 24
Finished Jul 02 09:46:27 AM PDT 24
Peak memory 195156 kb
Host smart-205b3ea6-c9a4-480c-a606-2ba82e54f2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872165357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.872165357
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2318594425
Short name T1190
Test name
Test status
Simulation time 78515910 ps
CPU time 0.58 seconds
Started Jul 02 09:46:19 AM PDT 24
Finished Jul 02 09:46:20 AM PDT 24
Peak memory 195188 kb
Host smart-75c6469f-822e-4718-b582-39131e2134d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318594425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2318594425
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1578546737
Short name T1125
Test name
Test status
Simulation time 17597220 ps
CPU time 0.6 seconds
Started Jul 02 09:46:19 AM PDT 24
Finished Jul 02 09:46:20 AM PDT 24
Peak memory 195120 kb
Host smart-05060dbc-9181-47c2-83c5-4da686061cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578546737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1578546737
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.542943319
Short name T1169
Test name
Test status
Simulation time 60489416 ps
CPU time 0.86 seconds
Started Jul 02 09:46:01 AM PDT 24
Finished Jul 02 09:46:04 AM PDT 24
Peak memory 200552 kb
Host smart-cd1170c8-0e43-4b3c-ab51-559d2405c284
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542943319 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.542943319
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3512228769
Short name T63
Test name
Test status
Simulation time 37074895 ps
CPU time 0.65 seconds
Started Jul 02 09:46:00 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 196220 kb
Host smart-5b88423d-a16d-425f-ae45-295849184b48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512228769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3512228769
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.4010636585
Short name T1173
Test name
Test status
Simulation time 27056841 ps
CPU time 0.64 seconds
Started Jul 02 09:45:59 AM PDT 24
Finished Jul 02 09:46:02 AM PDT 24
Peak memory 195028 kb
Host smart-191bcf33-a6a1-4edd-b3ae-325c659b47be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010636585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4010636585
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.151807512
Short name T1203
Test name
Test status
Simulation time 13315409 ps
CPU time 0.65 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 196452 kb
Host smart-b7827f8a-6e61-4f80-9884-328b429fe1bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151807512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.151807512
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1549261349
Short name T1147
Test name
Test status
Simulation time 491525758 ps
CPU time 2.13 seconds
Started Jul 02 09:46:02 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 200824 kb
Host smart-bede1665-c609-4e10-a6a0-88482ec3c5c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549261349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1549261349
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2219723095
Short name T1118
Test name
Test status
Simulation time 87978541 ps
CPU time 1.38 seconds
Started Jul 02 09:46:03 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 200176 kb
Host smart-a0580fda-7227-4a53-976a-c64c6348e017
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219723095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2219723095
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.866676183
Short name T1122
Test name
Test status
Simulation time 18867917 ps
CPU time 0.94 seconds
Started Jul 02 09:46:00 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 200620 kb
Host smart-fcb81b9f-0018-468e-a18b-371eeb3efc80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866676183 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.866676183
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1826718636
Short name T78
Test name
Test status
Simulation time 19003634 ps
CPU time 0.61 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 196236 kb
Host smart-0e3e865a-68db-400d-a0c7-46a47a446f50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826718636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1826718636
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3377818531
Short name T1213
Test name
Test status
Simulation time 12963703 ps
CPU time 0.59 seconds
Started Jul 02 09:46:03 AM PDT 24
Finished Jul 02 09:46:05 AM PDT 24
Peak memory 195180 kb
Host smart-b40a4da3-8d64-4558-8705-89865311428c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377818531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3377818531
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.895524672
Short name T1131
Test name
Test status
Simulation time 73812386 ps
CPU time 0.67 seconds
Started Jul 02 09:46:00 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 195536 kb
Host smart-3eec34fa-1e7a-4558-9ebd-4044f788c874
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895524672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.895524672
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3221786868
Short name T1177
Test name
Test status
Simulation time 26134249 ps
CPU time 1.26 seconds
Started Jul 02 09:46:01 AM PDT 24
Finished Jul 02 09:46:04 AM PDT 24
Peak memory 200764 kb
Host smart-926d3fc5-8e2c-4fe6-8f81-f9a51a60ae1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221786868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3221786868
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2424364627
Short name T84
Test name
Test status
Simulation time 52155826 ps
CPU time 1.03 seconds
Started Jul 02 09:46:00 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 199752 kb
Host smart-a1893b44-37be-422a-ab91-255000461cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424364627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2424364627
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4061442436
Short name T1089
Test name
Test status
Simulation time 22920660 ps
CPU time 0.77 seconds
Started Jul 02 09:46:06 AM PDT 24
Finished Jul 02 09:46:09 AM PDT 24
Peak memory 199540 kb
Host smart-14b5a087-958f-4498-891d-49a14c9c58ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061442436 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.4061442436
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2370346969
Short name T1155
Test name
Test status
Simulation time 17446436 ps
CPU time 0.64 seconds
Started Jul 02 09:46:01 AM PDT 24
Finished Jul 02 09:46:04 AM PDT 24
Peak memory 196184 kb
Host smart-1370633e-bb06-4ae9-a71e-f5a4fe0b6345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370346969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2370346969
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3200735687
Short name T1204
Test name
Test status
Simulation time 51158303 ps
CPU time 0.57 seconds
Started Jul 02 09:46:01 AM PDT 24
Finished Jul 02 09:46:04 AM PDT 24
Peak memory 195116 kb
Host smart-9cbad291-52ed-4976-b6f5-220228447073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200735687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3200735687
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.488748761
Short name T75
Test name
Test status
Simulation time 103432348 ps
CPU time 0.86 seconds
Started Jul 02 09:45:58 AM PDT 24
Finished Jul 02 09:46:02 AM PDT 24
Peak memory 197944 kb
Host smart-3ebcb56f-ba4b-4984-9dd7-0007fde20007
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488748761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.488748761
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2383515902
Short name T1110
Test name
Test status
Simulation time 24628128 ps
CPU time 1.32 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 200820 kb
Host smart-c7db6ad1-77f0-465b-8c5e-58899acda632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383515902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2383515902
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2588298690
Short name T1218
Test name
Test status
Simulation time 296700420 ps
CPU time 1.41 seconds
Started Jul 02 09:46:00 AM PDT 24
Finished Jul 02 09:46:04 AM PDT 24
Peak memory 200060 kb
Host smart-3957c8aa-0417-4452-acd0-e93d903840f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588298690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2588298690
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1785051191
Short name T1209
Test name
Test status
Simulation time 31451151 ps
CPU time 0.82 seconds
Started Jul 02 09:46:05 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 200624 kb
Host smart-e3ce8776-035f-4a2f-ab5a-a75f2e0851f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785051191 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1785051191
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.961368490
Short name T1143
Test name
Test status
Simulation time 103238676 ps
CPU time 0.6 seconds
Started Jul 02 09:46:00 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 196256 kb
Host smart-ce56f5c1-c802-47c6-a3e5-803db6856396
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961368490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.961368490
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2214501323
Short name T1166
Test name
Test status
Simulation time 14867139 ps
CPU time 0.59 seconds
Started Jul 02 09:46:03 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 195196 kb
Host smart-3800029e-9bce-4630-9c1f-8c99741abe06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214501323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2214501323
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1850579816
Short name T1214
Test name
Test status
Simulation time 16818989 ps
CPU time 0.74 seconds
Started Jul 02 09:46:05 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 196800 kb
Host smart-8d249a35-3717-407c-94dc-12f60a32eb3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850579816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1850579816
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1604579818
Short name T1104
Test name
Test status
Simulation time 48838170 ps
CPU time 1.55 seconds
Started Jul 02 09:46:00 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 200804 kb
Host smart-e71ee421-b178-4290-a3c3-4d29e7887978
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604579818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1604579818
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1544693942
Short name T89
Test name
Test status
Simulation time 162293910 ps
CPU time 0.94 seconds
Started Jul 02 09:46:01 AM PDT 24
Finished Jul 02 09:46:04 AM PDT 24
Peak memory 199352 kb
Host smart-ade32692-4271-45eb-a607-fb3480b981bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544693942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1544693942
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3180813307
Short name T1128
Test name
Test status
Simulation time 75361377 ps
CPU time 0.76 seconds
Started Jul 02 09:46:05 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 200548 kb
Host smart-c9e1861d-cab7-4509-8de9-8719d9746dcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180813307 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3180813307
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1823573010
Short name T1091
Test name
Test status
Simulation time 57754012 ps
CPU time 0.68 seconds
Started Jul 02 09:46:03 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 196356 kb
Host smart-857a549b-aeda-42c8-8fdf-17f8f0ea74c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823573010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1823573010
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3205412625
Short name T1153
Test name
Test status
Simulation time 22054701 ps
CPU time 0.6 seconds
Started Jul 02 09:46:02 AM PDT 24
Finished Jul 02 09:46:04 AM PDT 24
Peak memory 195172 kb
Host smart-45c82598-823f-4a8e-960e-fcf7f937ffcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205412625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3205412625
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1972084062
Short name T1206
Test name
Test status
Simulation time 94520021 ps
CPU time 0.78 seconds
Started Jul 02 09:46:04 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 197344 kb
Host smart-c23077ca-57f2-43a4-93b9-57b7ff3fb58d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972084062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1972084062
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.563456719
Short name T1199
Test name
Test status
Simulation time 69937073 ps
CPU time 1.12 seconds
Started Jul 02 09:46:03 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 200792 kb
Host smart-fdf3ff9d-b57c-4caf-818f-1032b201aa94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563456719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.563456719
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.982128056
Short name T88
Test name
Test status
Simulation time 77665403 ps
CPU time 1.35 seconds
Started Jul 02 09:46:05 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 200016 kb
Host smart-23fdc7c8-af4b-4edc-bb3a-96e4db754da0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982128056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.982128056
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2037717629
Short name T535
Test name
Test status
Simulation time 44522529 ps
CPU time 0.57 seconds
Started Jul 02 09:22:44 AM PDT 24
Finished Jul 02 09:22:45 AM PDT 24
Peak memory 195296 kb
Host smart-08dc970d-a404-4ed8-915c-74bad678d6a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037717629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2037717629
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3331803370
Short name T41
Test name
Test status
Simulation time 96197429887 ps
CPU time 19.78 seconds
Started Jul 02 09:22:41 AM PDT 24
Finished Jul 02 09:23:02 AM PDT 24
Peak memory 199912 kb
Host smart-e294b1bd-7001-466c-99db-1a2dff9eda91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331803370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3331803370
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.686835649
Short name T175
Test name
Test status
Simulation time 17048590825 ps
CPU time 26.03 seconds
Started Jul 02 09:22:42 AM PDT 24
Finished Jul 02 09:23:09 AM PDT 24
Peak memory 199972 kb
Host smart-ca231417-d866-4ad6-a8af-da54bc5524fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686835649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.686835649
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2481811819
Short name T421
Test name
Test status
Simulation time 112384954974 ps
CPU time 45.95 seconds
Started Jul 02 09:22:54 AM PDT 24
Finished Jul 02 09:23:40 AM PDT 24
Peak memory 199836 kb
Host smart-e79229cd-1907-4606-85d8-c90c47716ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481811819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2481811819
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2578617692
Short name T618
Test name
Test status
Simulation time 168464517621 ps
CPU time 71.18 seconds
Started Jul 02 09:22:54 AM PDT 24
Finished Jul 02 09:24:06 AM PDT 24
Peak memory 196716 kb
Host smart-bd9c870f-ac8c-4ab2-ae30-334a1fd3d8ef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578617692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2578617692
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.55122479
Short name T898
Test name
Test status
Simulation time 90571813755 ps
CPU time 724.36 seconds
Started Jul 02 09:22:51 AM PDT 24
Finished Jul 02 09:34:56 AM PDT 24
Peak memory 199888 kb
Host smart-7c3cf4f8-f057-4938-b657-eb7ca3c4ff5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55122479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.55122479
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2785030429
Short name T354
Test name
Test status
Simulation time 2884376045 ps
CPU time 5.16 seconds
Started Jul 02 09:22:51 AM PDT 24
Finished Jul 02 09:22:56 AM PDT 24
Peak memory 196256 kb
Host smart-a6409eb9-3eb0-4572-993e-1478595ccceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785030429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2785030429
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.1949083440
Short name T861
Test name
Test status
Simulation time 3963028288 ps
CPU time 60.59 seconds
Started Jul 02 09:22:43 AM PDT 24
Finished Jul 02 09:23:44 AM PDT 24
Peak memory 199868 kb
Host smart-55438252-3336-496f-8b4f-f19f9c4d559f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1949083440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1949083440
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3380040862
Short name T465
Test name
Test status
Simulation time 4559782234 ps
CPU time 32.87 seconds
Started Jul 02 09:22:44 AM PDT 24
Finished Jul 02 09:23:17 AM PDT 24
Peak memory 199876 kb
Host smart-1eb03d93-1f95-4868-96e7-08299a611e13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3380040862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3380040862
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2799178683
Short name T549
Test name
Test status
Simulation time 48889300151 ps
CPU time 35.23 seconds
Started Jul 02 09:22:42 AM PDT 24
Finished Jul 02 09:23:18 AM PDT 24
Peak memory 199972 kb
Host smart-7fa67482-2f11-466c-9a2c-9bbcd46866e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799178683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2799178683
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3756222643
Short name T1065
Test name
Test status
Simulation time 541239264 ps
CPU time 1.49 seconds
Started Jul 02 09:22:43 AM PDT 24
Finished Jul 02 09:22:44 AM PDT 24
Peak memory 195512 kb
Host smart-2aa71e43-ff98-4b05-a5e6-36257e66b2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756222643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3756222643
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.2400781538
Short name T453
Test name
Test status
Simulation time 11091233660 ps
CPU time 47.41 seconds
Started Jul 02 09:22:42 AM PDT 24
Finished Jul 02 09:23:29 AM PDT 24
Peak memory 199820 kb
Host smart-92719fdb-8591-41f4-9676-4badf1b39a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400781538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2400781538
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2053521437
Short name T188
Test name
Test status
Simulation time 215779067631 ps
CPU time 327.5 seconds
Started Jul 02 09:22:47 AM PDT 24
Finished Jul 02 09:28:15 AM PDT 24
Peak memory 199940 kb
Host smart-12ee3e56-1c1c-4414-82b8-96423ae8db00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053521437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2053521437
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3308157265
Short name T1032
Test name
Test status
Simulation time 923556499 ps
CPU time 2.77 seconds
Started Jul 02 09:22:45 AM PDT 24
Finished Jul 02 09:22:48 AM PDT 24
Peak memory 198448 kb
Host smart-fe3141e7-9bf5-4a65-8828-f70be7b55e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308157265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3308157265
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2602743832
Short name T703
Test name
Test status
Simulation time 44265781439 ps
CPU time 21.56 seconds
Started Jul 02 09:22:44 AM PDT 24
Finished Jul 02 09:23:06 AM PDT 24
Peak memory 199996 kb
Host smart-993f3210-0a1c-441d-aa08-a51f3c2f4c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602743832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2602743832
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.342675935
Short name T177
Test name
Test status
Simulation time 372299929469 ps
CPU time 369.74 seconds
Started Jul 02 09:22:46 AM PDT 24
Finished Jul 02 09:28:56 AM PDT 24
Peak memory 199956 kb
Host smart-e97f1ec2-5ee2-49f9-9ade-5d29e348012d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342675935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.342675935
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1202730157
Short name T1067
Test name
Test status
Simulation time 23270253751 ps
CPU time 21.14 seconds
Started Jul 02 09:22:52 AM PDT 24
Finished Jul 02 09:23:13 AM PDT 24
Peak memory 199968 kb
Host smart-56c34eb7-38ab-4b4e-a8b0-d4b701817ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202730157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1202730157
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2996252414
Short name T658
Test name
Test status
Simulation time 70457953199 ps
CPU time 95.87 seconds
Started Jul 02 09:22:50 AM PDT 24
Finished Jul 02 09:24:26 AM PDT 24
Peak memory 199928 kb
Host smart-8b9cdc69-b660-4f1f-94bb-2b30ad7b0798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996252414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2996252414
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2123569111
Short name T914
Test name
Test status
Simulation time 57835853949 ps
CPU time 576.09 seconds
Started Jul 02 09:22:56 AM PDT 24
Finished Jul 02 09:32:33 AM PDT 24
Peak memory 199940 kb
Host smart-754ebd13-68bf-4402-acad-33e4499e5205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2123569111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2123569111
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.389602255
Short name T968
Test name
Test status
Simulation time 10056069358 ps
CPU time 9.11 seconds
Started Jul 02 09:22:48 AM PDT 24
Finished Jul 02 09:22:57 AM PDT 24
Peak memory 200004 kb
Host smart-96b9669b-53fc-4870-a2d0-da61247bf8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389602255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.389602255
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.324586587
Short name T378
Test name
Test status
Simulation time 14171636462 ps
CPU time 6.24 seconds
Started Jul 02 09:22:47 AM PDT 24
Finished Jul 02 09:22:53 AM PDT 24
Peak memory 197292 kb
Host smart-f624ed28-9ac4-41e9-bd79-0ca334327a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324586587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.324586587
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1076620725
Short name T7
Test name
Test status
Simulation time 6213085091 ps
CPU time 53.7 seconds
Started Jul 02 09:22:43 AM PDT 24
Finished Jul 02 09:23:37 AM PDT 24
Peak memory 199212 kb
Host smart-b272c8ab-997f-46a8-b715-203165f97366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1076620725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1076620725
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1516541665
Short name T342
Test name
Test status
Simulation time 98186315666 ps
CPU time 133.08 seconds
Started Jul 02 09:22:49 AM PDT 24
Finished Jul 02 09:25:02 AM PDT 24
Peak memory 200016 kb
Host smart-503527de-9cfc-4d7c-be4a-e24e5b8e601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516541665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1516541665
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2327099893
Short name T606
Test name
Test status
Simulation time 35727645035 ps
CPU time 4.43 seconds
Started Jul 02 09:22:47 AM PDT 24
Finished Jul 02 09:22:52 AM PDT 24
Peak memory 196620 kb
Host smart-1f10503d-76c6-4301-9cf8-e25fb84f4a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327099893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2327099893
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1133165470
Short name T96
Test name
Test status
Simulation time 218995182 ps
CPU time 0.87 seconds
Started Jul 02 09:22:57 AM PDT 24
Finished Jul 02 09:22:58 AM PDT 24
Peak memory 218332 kb
Host smart-fd091acd-0686-47cc-8e8e-fe3ef159ad77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133165470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1133165470
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3361485717
Short name T906
Test name
Test status
Simulation time 692500424 ps
CPU time 2.61 seconds
Started Jul 02 09:23:00 AM PDT 24
Finished Jul 02 09:23:04 AM PDT 24
Peak memory 199792 kb
Host smart-dec950de-d734-4f87-b8fe-59a60e6e7979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361485717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3361485717
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2910999881
Short name T604
Test name
Test status
Simulation time 297705255874 ps
CPU time 499.99 seconds
Started Jul 02 09:23:07 AM PDT 24
Finished Jul 02 09:31:29 AM PDT 24
Peak memory 199948 kb
Host smart-dd414245-04d0-4c75-bdd5-cb40e04f05fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910999881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2910999881
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.894306538
Short name T503
Test name
Test status
Simulation time 287722706 ps
CPU time 1.15 seconds
Started Jul 02 09:22:54 AM PDT 24
Finished Jul 02 09:22:56 AM PDT 24
Peak memory 197952 kb
Host smart-32702883-9187-4201-9278-3bb357127d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894306538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.894306538
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3043409307
Short name T313
Test name
Test status
Simulation time 124176615779 ps
CPU time 62.12 seconds
Started Jul 02 09:23:09 AM PDT 24
Finished Jul 02 09:24:12 AM PDT 24
Peak memory 199932 kb
Host smart-1ed2d79c-7f6d-457d-9412-fab5012b5592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043409307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3043409307
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1978902049
Short name T736
Test name
Test status
Simulation time 40208910 ps
CPU time 0.54 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:23:25 AM PDT 24
Peak memory 195488 kb
Host smart-4fa20b16-8f2a-4162-8445-04ad36f34926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978902049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1978902049
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.195938414
Short name T135
Test name
Test status
Simulation time 118404453068 ps
CPU time 134.25 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:25:36 AM PDT 24
Peak memory 199972 kb
Host smart-79983be4-f308-49aa-9573-e9470d904747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195938414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.195938414
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3008727871
Short name T171
Test name
Test status
Simulation time 94316583928 ps
CPU time 129.24 seconds
Started Jul 02 09:23:21 AM PDT 24
Finished Jul 02 09:25:35 AM PDT 24
Peak memory 199916 kb
Host smart-f6abb9b3-1072-4106-a863-b2b914e72474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008727871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3008727871
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.4091361716
Short name T508
Test name
Test status
Simulation time 17900541448 ps
CPU time 29.44 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:23:49 AM PDT 24
Peak memory 199964 kb
Host smart-7b8022af-3f45-46d6-b6e0-251d8eab9b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091361716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.4091361716
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.863258252
Short name T443
Test name
Test status
Simulation time 35329971950 ps
CPU time 27.53 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:23:46 AM PDT 24
Peak memory 199056 kb
Host smart-b9112d03-5b12-4db8-88ad-4a021701f72f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863258252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.863258252
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3404520360
Short name T333
Test name
Test status
Simulation time 54527995636 ps
CPU time 111.67 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:25:11 AM PDT 24
Peak memory 199948 kb
Host smart-f8ae8519-8132-49b9-a4ee-53999531c183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404520360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3404520360
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.926430009
Short name T636
Test name
Test status
Simulation time 6604660347 ps
CPU time 12.59 seconds
Started Jul 02 09:23:15 AM PDT 24
Finished Jul 02 09:23:29 AM PDT 24
Peak memory 199852 kb
Host smart-b82dd754-38b3-4858-af3d-d2e4582be02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926430009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.926430009
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2025704950
Short name T558
Test name
Test status
Simulation time 39169225974 ps
CPU time 21.21 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:23:46 AM PDT 24
Peak memory 199968 kb
Host smart-2d53a3d2-3f5c-4513-98a6-1f85254b91c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025704950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2025704950
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2133960969
Short name T295
Test name
Test status
Simulation time 9967167580 ps
CPU time 45.84 seconds
Started Jul 02 09:23:22 AM PDT 24
Finished Jul 02 09:24:12 AM PDT 24
Peak memory 199924 kb
Host smart-0c04245d-44b8-4470-bbff-337d50248479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133960969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2133960969
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3423381106
Short name T38
Test name
Test status
Simulation time 5686791876 ps
CPU time 19.63 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:23:48 AM PDT 24
Peak memory 198964 kb
Host smart-765a40f3-fe54-41ce-a330-4437751506f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423381106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3423381106
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2585823831
Short name T957
Test name
Test status
Simulation time 41501079077 ps
CPU time 15.85 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:23:40 AM PDT 24
Peak memory 198040 kb
Host smart-c6c9a00b-b860-422d-bb7b-b4b149bead3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585823831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2585823831
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2661102525
Short name T854
Test name
Test status
Simulation time 5468825889 ps
CPU time 2.69 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:24 AM PDT 24
Peak memory 196236 kb
Host smart-6dea958d-ac4a-4b8b-99d8-ff643254d251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661102525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2661102525
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2799355464
Short name T965
Test name
Test status
Simulation time 108254412 ps
CPU time 0.87 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:22 AM PDT 24
Peak memory 197776 kb
Host smart-ff41889f-4410-4ba4-9b71-675ec9e30d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799355464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2799355464
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2437104060
Short name T522
Test name
Test status
Simulation time 79892429638 ps
CPU time 312.27 seconds
Started Jul 02 09:23:15 AM PDT 24
Finished Jul 02 09:28:28 AM PDT 24
Peak memory 216424 kb
Host smart-a5b35a37-2fd9-4428-b2d0-4d4b3ed0289f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437104060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2437104060
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1866987656
Short name T925
Test name
Test status
Simulation time 1339038449 ps
CPU time 1.79 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:23:21 AM PDT 24
Peak memory 199556 kb
Host smart-de7930f9-978e-4bec-b8d9-6fd6afd942c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866987656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1866987656
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3777446120
Short name T278
Test name
Test status
Simulation time 74539853217 ps
CPU time 176.96 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:26:25 AM PDT 24
Peak memory 199996 kb
Host smart-68f1cb54-97ea-4d26-a13d-de9797fc542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777446120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3777446120
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2370671846
Short name T448
Test name
Test status
Simulation time 157434095378 ps
CPU time 52.24 seconds
Started Jul 02 09:26:05 AM PDT 24
Finished Jul 02 09:26:58 AM PDT 24
Peak memory 199960 kb
Host smart-121d3242-d8a3-449e-aa93-73190d7b7a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370671846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2370671846
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1324157554
Short name T233
Test name
Test status
Simulation time 131585733024 ps
CPU time 187.79 seconds
Started Jul 02 09:26:07 AM PDT 24
Finished Jul 02 09:29:16 AM PDT 24
Peak memory 199948 kb
Host smart-ae486508-7b54-4a95-adf1-72318f2a9741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324157554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1324157554
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3060393200
Short name T647
Test name
Test status
Simulation time 156863809305 ps
CPU time 64.07 seconds
Started Jul 02 09:26:06 AM PDT 24
Finished Jul 02 09:27:10 AM PDT 24
Peak memory 199940 kb
Host smart-c5f2b499-caa5-4ce3-a7a9-8ac3eb35e8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060393200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3060393200
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3320757872
Short name T583
Test name
Test status
Simulation time 141460532426 ps
CPU time 47.01 seconds
Started Jul 02 09:26:03 AM PDT 24
Finished Jul 02 09:26:51 AM PDT 24
Peak memory 199940 kb
Host smart-a1b9eafe-0d14-4eeb-b078-be3085d17746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320757872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3320757872
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1735264519
Short name T715
Test name
Test status
Simulation time 103979370402 ps
CPU time 29.96 seconds
Started Jul 02 09:26:08 AM PDT 24
Finished Jul 02 09:26:39 AM PDT 24
Peak memory 199924 kb
Host smart-3163b8aa-8fdc-4d94-8c2a-f87f77b0f54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735264519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1735264519
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2141799949
Short name T973
Test name
Test status
Simulation time 179357324797 ps
CPU time 15.13 seconds
Started Jul 02 09:26:03 AM PDT 24
Finished Jul 02 09:26:19 AM PDT 24
Peak memory 199924 kb
Host smart-672be04e-74eb-40fb-a100-c2bf2874de7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141799949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2141799949
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3540044734
Short name T796
Test name
Test status
Simulation time 149080214628 ps
CPU time 86.22 seconds
Started Jul 02 09:26:02 AM PDT 24
Finished Jul 02 09:27:29 AM PDT 24
Peak memory 199936 kb
Host smart-de84c091-28ba-44fc-a10b-38cfc68d056f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540044734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3540044734
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3536063245
Short name T461
Test name
Test status
Simulation time 50995137611 ps
CPU time 23.61 seconds
Started Jul 02 09:26:03 AM PDT 24
Finished Jul 02 09:26:28 AM PDT 24
Peak memory 199692 kb
Host smart-194cc2e8-c35c-4a43-9acc-a976613bd73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536063245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3536063245
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.1782883554
Short name T358
Test name
Test status
Simulation time 92752422 ps
CPU time 0.55 seconds
Started Jul 02 09:23:14 AM PDT 24
Finished Jul 02 09:23:16 AM PDT 24
Peak memory 194776 kb
Host smart-759eaa48-9ea9-4a14-865c-503414733688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782883554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1782883554
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2769111167
Short name T436
Test name
Test status
Simulation time 49164941794 ps
CPU time 80.75 seconds
Started Jul 02 09:23:23 AM PDT 24
Finished Jul 02 09:24:48 AM PDT 24
Peak memory 199992 kb
Host smart-81c1ceac-8920-4a34-8139-85a658e7ca12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769111167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2769111167
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1470295933
Short name T971
Test name
Test status
Simulation time 26458887398 ps
CPU time 44.95 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:23:53 AM PDT 24
Peak memory 199884 kb
Host smart-1c63564f-f9c6-4ed4-86ca-d6fb9585a478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470295933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1470295933
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1397117576
Short name T1060
Test name
Test status
Simulation time 17432612481 ps
CPU time 29.04 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:52 AM PDT 24
Peak memory 199932 kb
Host smart-d4f7cef2-f3b2-4b95-9f78-89e65e03697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397117576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1397117576
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1573911930
Short name T559
Test name
Test status
Simulation time 24019446354 ps
CPU time 10.15 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:23:30 AM PDT 24
Peak memory 198280 kb
Host smart-50517297-c79d-4a26-941a-9dcf047069ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573911930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1573911930
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2885493220
Short name T390
Test name
Test status
Simulation time 136778574449 ps
CPU time 954.66 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:39:23 AM PDT 24
Peak memory 199912 kb
Host smart-7e1499bd-1906-4a39-9fdb-418a0c7b25a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885493220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2885493220
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3332089617
Short name T650
Test name
Test status
Simulation time 6265442545 ps
CPU time 8.8 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:23:16 AM PDT 24
Peak memory 198636 kb
Host smart-9bd686b5-e1cb-4038-9707-16c5c3a95f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332089617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3332089617
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.662638811
Short name T520
Test name
Test status
Simulation time 4554699552 ps
CPU time 45.16 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:24:00 AM PDT 24
Peak memory 200192 kb
Host smart-87fbc674-fce2-464b-a25d-162e507a09f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662638811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.662638811
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.973732260
Short name T642
Test name
Test status
Simulation time 5405304485 ps
CPU time 14.14 seconds
Started Jul 02 09:23:24 AM PDT 24
Finished Jul 02 09:23:42 AM PDT 24
Peak memory 198196 kb
Host smart-d5e0d033-6699-4728-8701-06915fec629e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973732260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.973732260
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.980137399
Short name T638
Test name
Test status
Simulation time 64091959874 ps
CPU time 29.06 seconds
Started Jul 02 09:23:21 AM PDT 24
Finished Jul 02 09:23:54 AM PDT 24
Peak memory 199964 kb
Host smart-2fc43654-e605-4f2d-8e4b-6a03a1f9ce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980137399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.980137399
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3395746483
Short name T472
Test name
Test status
Simulation time 27842312024 ps
CPU time 6.95 seconds
Started Jul 02 09:23:23 AM PDT 24
Finished Jul 02 09:23:34 AM PDT 24
Peak memory 196232 kb
Host smart-067501db-b751-4303-b681-173368f73759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395746483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3395746483
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.179514461
Short name T953
Test name
Test status
Simulation time 890354520 ps
CPU time 3.14 seconds
Started Jul 02 09:23:10 AM PDT 24
Finished Jul 02 09:23:14 AM PDT 24
Peak memory 199860 kb
Host smart-d0740580-330e-4d66-bf71-87846a496eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179514461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.179514461
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.635893315
Short name T659
Test name
Test status
Simulation time 346115014388 ps
CPU time 1058.6 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:41:03 AM PDT 24
Peak memory 199984 kb
Host smart-f5179b62-6baf-4c8e-86d9-04eaba6554f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635893315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.635893315
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.507575779
Short name T334
Test name
Test status
Simulation time 639347822 ps
CPU time 2.36 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:23:26 AM PDT 24
Peak memory 199504 kb
Host smart-21a3077f-d16e-4035-ae40-66eea397f78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507575779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.507575779
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3153998307
Short name T1070
Test name
Test status
Simulation time 1288613020 ps
CPU time 2.62 seconds
Started Jul 02 09:23:16 AM PDT 24
Finished Jul 02 09:23:21 AM PDT 24
Peak memory 196576 kb
Host smart-4e407933-050d-4eb6-b5af-b7e0d776e675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153998307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3153998307
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2700846580
Short name T531
Test name
Test status
Simulation time 49400613654 ps
CPU time 41.65 seconds
Started Jul 02 09:26:02 AM PDT 24
Finished Jul 02 09:26:44 AM PDT 24
Peak memory 199852 kb
Host smart-ac261423-d29c-4358-8989-6301242139d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700846580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2700846580
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2028923012
Short name T572
Test name
Test status
Simulation time 76354269564 ps
CPU time 245.43 seconds
Started Jul 02 09:26:02 AM PDT 24
Finished Jul 02 09:30:08 AM PDT 24
Peak memory 199892 kb
Host smart-18c6b2fe-1644-480b-89c3-a04481de81e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028923012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2028923012
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1971336819
Short name T335
Test name
Test status
Simulation time 64661979965 ps
CPU time 108.45 seconds
Started Jul 02 09:26:04 AM PDT 24
Finished Jul 02 09:27:53 AM PDT 24
Peak memory 200004 kb
Host smart-0f24a3cb-588c-42bb-9df5-727ce6c93252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971336819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1971336819
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.4183988763
Short name T205
Test name
Test status
Simulation time 67020096151 ps
CPU time 24.67 seconds
Started Jul 02 09:26:04 AM PDT 24
Finished Jul 02 09:26:30 AM PDT 24
Peak memory 199120 kb
Host smart-68d45e12-69dc-49d3-9d82-d8518aeb2ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183988763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4183988763
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3698493834
Short name T808
Test name
Test status
Simulation time 19770934086 ps
CPU time 31.74 seconds
Started Jul 02 09:26:03 AM PDT 24
Finished Jul 02 09:26:36 AM PDT 24
Peak memory 199872 kb
Host smart-ed811dec-cfe8-489b-9037-843a01d7d199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698493834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3698493834
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2704593302
Short name T577
Test name
Test status
Simulation time 157249985138 ps
CPU time 60.5 seconds
Started Jul 02 09:26:05 AM PDT 24
Finished Jul 02 09:27:06 AM PDT 24
Peak memory 199936 kb
Host smart-9e6542ed-9c50-43d5-ab8c-055c7f1c070b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704593302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2704593302
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2979014065
Short name T630
Test name
Test status
Simulation time 129917498693 ps
CPU time 57.69 seconds
Started Jul 02 09:26:04 AM PDT 24
Finished Jul 02 09:27:02 AM PDT 24
Peak memory 199944 kb
Host smart-4a01b988-cfed-4368-a005-6bd0af56944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979014065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2979014065
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.512616960
Short name T309
Test name
Test status
Simulation time 123853896714 ps
CPU time 88.82 seconds
Started Jul 02 09:26:10 AM PDT 24
Finished Jul 02 09:27:39 AM PDT 24
Peak memory 199976 kb
Host smart-f2c166df-3cf6-468d-81bc-f1d94815d347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512616960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.512616960
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2162253186
Short name T192
Test name
Test status
Simulation time 58672701395 ps
CPU time 42.69 seconds
Started Jul 02 09:26:07 AM PDT 24
Finished Jul 02 09:26:51 AM PDT 24
Peak memory 199932 kb
Host smart-3c464627-632f-4f83-a280-ecbf9e9c1c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162253186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2162253186
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2756981398
Short name T892
Test name
Test status
Simulation time 183339097623 ps
CPU time 262.48 seconds
Started Jul 02 09:26:07 AM PDT 24
Finished Jul 02 09:30:31 AM PDT 24
Peak memory 199884 kb
Host smart-b243cb5b-2284-4c0d-8479-d8b7fb1ceabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756981398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2756981398
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.833150533
Short name T388
Test name
Test status
Simulation time 41083341 ps
CPU time 0.55 seconds
Started Jul 02 09:23:23 AM PDT 24
Finished Jul 02 09:23:27 AM PDT 24
Peak memory 194920 kb
Host smart-d489dbdc-dc95-49ab-abf4-ac9797ba0003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833150533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.833150533
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1665559935
Short name T848
Test name
Test status
Simulation time 222508201558 ps
CPU time 224.84 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:27:08 AM PDT 24
Peak memory 199984 kb
Host smart-39ef152c-cddd-4937-ba02-3afaad968503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665559935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1665559935
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2400829293
Short name T98
Test name
Test status
Simulation time 88877297464 ps
CPU time 18.92 seconds
Started Jul 02 09:23:10 AM PDT 24
Finished Jul 02 09:23:29 AM PDT 24
Peak memory 199952 kb
Host smart-a5d3d4a9-c97e-4fd5-b839-0ef077788f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400829293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2400829293
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3762325601
Short name T470
Test name
Test status
Simulation time 31526599974 ps
CPU time 25.42 seconds
Started Jul 02 09:23:07 AM PDT 24
Finished Jul 02 09:23:34 AM PDT 24
Peak memory 199864 kb
Host smart-b4ba9aa2-88a6-4eb7-ac72-94d15d8a7108
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762325601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3762325601
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1823558239
Short name T640
Test name
Test status
Simulation time 40638287569 ps
CPU time 281.91 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:28:07 AM PDT 24
Peak memory 199988 kb
Host smart-06098b64-f95a-435e-8654-e66b613c6614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823558239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1823558239
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.4085266779
Short name T904
Test name
Test status
Simulation time 7540865752 ps
CPU time 7.58 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:23:26 AM PDT 24
Peak memory 198216 kb
Host smart-25a2ed26-17fb-45ed-8259-7b2b322e8ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085266779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4085266779
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1306827694
Short name T795
Test name
Test status
Simulation time 10589979405 ps
CPU time 8.64 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:23:16 AM PDT 24
Peak memory 196972 kb
Host smart-aabd976a-303f-4c91-90c8-9f37380d8b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306827694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1306827694
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3272528207
Short name T427
Test name
Test status
Simulation time 18813826001 ps
CPU time 242.36 seconds
Started Jul 02 09:23:09 AM PDT 24
Finished Jul 02 09:27:12 AM PDT 24
Peak memory 199940 kb
Host smart-f7fd0446-8f24-4423-b4b5-9ef91e56134e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272528207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3272528207
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1336614508
Short name T365
Test name
Test status
Simulation time 7531521686 ps
CPU time 15.63 seconds
Started Jul 02 09:23:22 AM PDT 24
Finished Jul 02 09:23:42 AM PDT 24
Peak memory 199908 kb
Host smart-d9ff0a9c-63e3-45b9-9bf6-d5a8d770ae2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1336614508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1336614508
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.315465053
Short name T970
Test name
Test status
Simulation time 32337988295 ps
CPU time 53.08 seconds
Started Jul 02 09:23:24 AM PDT 24
Finished Jul 02 09:24:21 AM PDT 24
Peak memory 199980 kb
Host smart-dcd6a5ce-b6e3-4664-bc82-4fb9479c4f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315465053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.315465053
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.4115813556
Short name T944
Test name
Test status
Simulation time 3596703384 ps
CPU time 5.89 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:29 AM PDT 24
Peak memory 196788 kb
Host smart-c840b5ef-ec43-4c77-8b64-c3d69e81a05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115813556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.4115813556
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3132694390
Short name T4
Test name
Test status
Simulation time 6295655397 ps
CPU time 7.2 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:23:26 AM PDT 24
Peak memory 199960 kb
Host smart-dfa67e9a-662e-44f0-bd08-75e406ad74ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132694390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3132694390
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1328552923
Short name T621
Test name
Test status
Simulation time 240465866115 ps
CPU time 116.8 seconds
Started Jul 02 09:23:14 AM PDT 24
Finished Jul 02 09:25:12 AM PDT 24
Peak memory 199824 kb
Host smart-9b14b732-50e0-42d3-9144-a144ca5c7f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328552923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1328552923
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1188303874
Short name T871
Test name
Test status
Simulation time 2142368488 ps
CPU time 1.93 seconds
Started Jul 02 09:23:16 AM PDT 24
Finished Jul 02 09:23:20 AM PDT 24
Peak memory 197832 kb
Host smart-0e8f64f6-11ec-4e6c-b3e5-72edc9a001ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188303874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1188303874
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3760113225
Short name T39
Test name
Test status
Simulation time 89097259021 ps
CPU time 56.72 seconds
Started Jul 02 09:23:10 AM PDT 24
Finished Jul 02 09:24:07 AM PDT 24
Peak memory 200020 kb
Host smart-2c622ff6-6d3b-4623-a941-00eedc7945b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760113225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3760113225
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2714613981
Short name T644
Test name
Test status
Simulation time 139471150190 ps
CPU time 53.61 seconds
Started Jul 02 09:26:07 AM PDT 24
Finished Jul 02 09:27:02 AM PDT 24
Peak memory 200008 kb
Host smart-7ab0ed5f-0fde-4bec-9e8c-af3e6c243c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714613981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2714613981
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.955615349
Short name T274
Test name
Test status
Simulation time 23412551557 ps
CPU time 19.17 seconds
Started Jul 02 09:26:10 AM PDT 24
Finished Jul 02 09:26:29 AM PDT 24
Peak memory 199976 kb
Host smart-14436947-e0fc-41f7-a628-a1fc5760344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955615349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.955615349
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.965647346
Short name T1056
Test name
Test status
Simulation time 17573259956 ps
CPU time 25.52 seconds
Started Jul 02 09:26:07 AM PDT 24
Finished Jul 02 09:26:33 AM PDT 24
Peak memory 199968 kb
Host smart-423da803-4e2a-403c-af63-a63a1128469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965647346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.965647346
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3511498158
Short name T852
Test name
Test status
Simulation time 241837269094 ps
CPU time 78.99 seconds
Started Jul 02 09:26:07 AM PDT 24
Finished Jul 02 09:27:27 AM PDT 24
Peak memory 199924 kb
Host smart-95645754-6010-492d-ac9e-4106c7260d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511498158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3511498158
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1220977652
Short name T196
Test name
Test status
Simulation time 27051648176 ps
CPU time 41.38 seconds
Started Jul 02 09:26:08 AM PDT 24
Finished Jul 02 09:26:50 AM PDT 24
Peak memory 199944 kb
Host smart-e7de95b2-5dc7-495b-9d22-f7bc7011cb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220977652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1220977652
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1059825558
Short name T245
Test name
Test status
Simulation time 166726720864 ps
CPU time 64.85 seconds
Started Jul 02 09:26:07 AM PDT 24
Finished Jul 02 09:27:13 AM PDT 24
Peak memory 199904 kb
Host smart-29678f94-e2ac-44b5-bb7f-1df7e84e716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059825558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1059825558
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1663852658
Short name T748
Test name
Test status
Simulation time 23184616887 ps
CPU time 78.8 seconds
Started Jul 02 09:26:07 AM PDT 24
Finished Jul 02 09:27:26 AM PDT 24
Peak memory 199988 kb
Host smart-0693bb02-54d6-4339-af19-ad09e424956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663852658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1663852658
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.315292225
Short name T239
Test name
Test status
Simulation time 6713216347 ps
CPU time 13.06 seconds
Started Jul 02 09:26:08 AM PDT 24
Finished Jul 02 09:26:22 AM PDT 24
Peak memory 200000 kb
Host smart-1c978547-dcc1-449c-879c-c04f33cb1f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315292225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.315292225
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2060917734
Short name T66
Test name
Test status
Simulation time 39624379 ps
CPU time 0.53 seconds
Started Jul 02 09:23:23 AM PDT 24
Finished Jul 02 09:23:28 AM PDT 24
Peak memory 195300 kb
Host smart-5a4da5b7-3ac6-4158-9027-0cb675faf851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060917734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2060917734
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2687165160
Short name T966
Test name
Test status
Simulation time 31193961520 ps
CPU time 59.06 seconds
Started Jul 02 09:23:15 AM PDT 24
Finished Jul 02 09:24:16 AM PDT 24
Peak memory 199948 kb
Host smart-2fcc1f2c-dd03-4339-82ec-84e8bb06eaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687165160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2687165160
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1416760324
Short name T856
Test name
Test status
Simulation time 185729934194 ps
CPU time 156.42 seconds
Started Jul 02 09:23:16 AM PDT 24
Finished Jul 02 09:25:55 AM PDT 24
Peak memory 199968 kb
Host smart-8dee945a-e2f2-4909-b3c9-b1584880408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416760324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1416760324
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.3806002835
Short name T737
Test name
Test status
Simulation time 6575782455 ps
CPU time 10.45 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:32 AM PDT 24
Peak memory 196716 kb
Host smart-c38e1b76-605d-4e0b-82b4-88f180715783
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806002835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3806002835
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2737883633
Short name T1047
Test name
Test status
Simulation time 127482803065 ps
CPU time 862.43 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:37:46 AM PDT 24
Peak memory 199952 kb
Host smart-54c87fba-4caa-4c3d-ad88-beff42aaf726
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737883633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2737883633
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1275947878
Short name T1073
Test name
Test status
Simulation time 10798545329 ps
CPU time 7.33 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:30 AM PDT 24
Peak memory 199620 kb
Host smart-8421b101-399c-4918-bb06-f1cf906bf804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275947878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1275947878
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.2538849182
Short name T495
Test name
Test status
Simulation time 11154917286 ps
CPU time 493.03 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:31:34 AM PDT 24
Peak memory 199944 kb
Host smart-83425272-0b6f-4e41-8b49-642ccd47d845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2538849182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2538849182
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1445584267
Short name T340
Test name
Test status
Simulation time 2773057250 ps
CPU time 5.5 seconds
Started Jul 02 09:23:16 AM PDT 24
Finished Jul 02 09:23:22 AM PDT 24
Peak memory 198588 kb
Host smart-97951c2a-d502-40e6-8e02-2e8f667f22b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445584267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1445584267
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3358086614
Short name T1013
Test name
Test status
Simulation time 92785337780 ps
CPU time 142.04 seconds
Started Jul 02 09:23:23 AM PDT 24
Finished Jul 02 09:25:49 AM PDT 24
Peak memory 199936 kb
Host smart-20a207d1-7bf7-4551-8399-ff8bf834101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358086614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3358086614
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.4264987791
Short name T279
Test name
Test status
Simulation time 3083713119 ps
CPU time 1.75 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:24 AM PDT 24
Peak memory 195948 kb
Host smart-8fc9bd8d-efb4-479e-9d42-7437d84f507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264987791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.4264987791
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3189656032
Short name T733
Test name
Test status
Simulation time 650334670 ps
CPU time 3.6 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:25 AM PDT 24
Peak memory 198944 kb
Host smart-ce268c40-c097-494a-9a29-e85f8ee82d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189656032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3189656032
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3674355014
Short name T762
Test name
Test status
Simulation time 121603613255 ps
CPU time 229.6 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:27:09 AM PDT 24
Peak memory 199976 kb
Host smart-c15e07de-1a26-443e-b36b-1d3cf00bbd93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674355014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3674355014
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2944599093
Short name T918
Test name
Test status
Simulation time 435426502 ps
CPU time 1.87 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:23:20 AM PDT 24
Peak memory 199208 kb
Host smart-423a1bb4-411b-4400-b2bf-0f328e50b3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944599093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2944599093
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1530780944
Short name T700
Test name
Test status
Simulation time 75808998209 ps
CPU time 150.73 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:25:55 AM PDT 24
Peak memory 199828 kb
Host smart-a7a97f6e-032f-48f9-8efc-2d1ba1905a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530780944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1530780944
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2109146635
Short name T875
Test name
Test status
Simulation time 8013102909 ps
CPU time 13.56 seconds
Started Jul 02 09:26:13 AM PDT 24
Finished Jul 02 09:26:27 AM PDT 24
Peak memory 199940 kb
Host smart-b21cfd4e-c521-4ca4-8649-cf33314b8505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109146635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2109146635
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3116959677
Short name T667
Test name
Test status
Simulation time 73652683377 ps
CPU time 27.9 seconds
Started Jul 02 09:26:11 AM PDT 24
Finished Jul 02 09:26:39 AM PDT 24
Peak memory 199996 kb
Host smart-39942080-b268-4718-9c5a-d0240cffa3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116959677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3116959677
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.514993785
Short name T1024
Test name
Test status
Simulation time 122647689134 ps
CPU time 26.35 seconds
Started Jul 02 09:26:10 AM PDT 24
Finished Jul 02 09:26:37 AM PDT 24
Peak memory 199952 kb
Host smart-c3643d74-f04e-423f-939f-f6baa750f6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514993785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.514993785
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3525569770
Short name T252
Test name
Test status
Simulation time 100620861332 ps
CPU time 154.86 seconds
Started Jul 02 09:26:10 AM PDT 24
Finished Jul 02 09:28:46 AM PDT 24
Peak memory 200004 kb
Host smart-4a5548c5-a98d-47bd-bd6a-d28585fa7085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525569770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3525569770
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1519576843
Short name T137
Test name
Test status
Simulation time 62366381764 ps
CPU time 41.57 seconds
Started Jul 02 09:26:11 AM PDT 24
Finished Jul 02 09:26:53 AM PDT 24
Peak memory 199848 kb
Host smart-2d476abf-3ee4-4205-9088-fe8e8c707ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519576843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1519576843
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3483034497
Short name T654
Test name
Test status
Simulation time 109230095256 ps
CPU time 38.51 seconds
Started Jul 02 09:26:10 AM PDT 24
Finished Jul 02 09:26:49 AM PDT 24
Peak memory 199960 kb
Host smart-1a8817b8-c35f-41d3-b1fb-78d9abbcf4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483034497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3483034497
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3658759527
Short name T625
Test name
Test status
Simulation time 18376906772 ps
CPU time 25.95 seconds
Started Jul 02 09:26:12 AM PDT 24
Finished Jul 02 09:26:38 AM PDT 24
Peak memory 199916 kb
Host smart-2e255cfd-66ce-439b-8c79-0739e3ba669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658759527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3658759527
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2087086030
Short name T568
Test name
Test status
Simulation time 124074052568 ps
CPU time 326.76 seconds
Started Jul 02 09:26:11 AM PDT 24
Finished Jul 02 09:31:38 AM PDT 24
Peak memory 199980 kb
Host smart-34110130-33c8-4f2a-86bc-6be5f766e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087086030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2087086030
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.37105807
Short name T499
Test name
Test status
Simulation time 12396852 ps
CPU time 0.54 seconds
Started Jul 02 09:23:26 AM PDT 24
Finished Jul 02 09:23:29 AM PDT 24
Peak memory 195300 kb
Host smart-c855a74a-2260-4dfc-8a81-9b56fad6592e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37105807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.37105807
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.4096298864
Short name T761
Test name
Test status
Simulation time 27812096049 ps
CPU time 49.17 seconds
Started Jul 02 09:23:21 AM PDT 24
Finished Jul 02 09:24:14 AM PDT 24
Peak memory 199996 kb
Host smart-e1862b02-00fe-4f8b-a002-2fbfa133c2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096298864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4096298864
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2055615026
Short name T946
Test name
Test status
Simulation time 71062113031 ps
CPU time 29.89 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:23:49 AM PDT 24
Peak memory 200008 kb
Host smart-93b61f85-d56d-46a0-a678-acf18c912cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055615026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2055615026
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.739863022
Short name T961
Test name
Test status
Simulation time 90821084262 ps
CPU time 85.28 seconds
Started Jul 02 09:23:24 AM PDT 24
Finished Jul 02 09:24:53 AM PDT 24
Peak memory 199988 kb
Host smart-d6394d52-79bb-44bf-8a51-21fc36c741bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739863022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.739863022
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2871278086
Short name T841
Test name
Test status
Simulation time 183290989047 ps
CPU time 68.8 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:24:32 AM PDT 24
Peak memory 199940 kb
Host smart-a0b524b9-65e7-409b-98d1-2e6ebb78cfa3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871278086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2871278086
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2584176883
Short name T543
Test name
Test status
Simulation time 92087341110 ps
CPU time 245.88 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:27:30 AM PDT 24
Peak memory 199928 kb
Host smart-f9074086-868e-471a-b39b-14571538fce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584176883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2584176883
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.545562158
Short name T400
Test name
Test status
Simulation time 8515329182 ps
CPU time 8.45 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:31 AM PDT 24
Peak memory 198676 kb
Host smart-581833e8-4e18-491f-b73f-aa1f7be1cd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545562158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.545562158
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.249290591
Short name T584
Test name
Test status
Simulation time 23992141259 ps
CPU time 311.74 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:28:35 AM PDT 24
Peak memory 199988 kb
Host smart-0e9fb138-79e3-45fb-bb38-d5944cff8a4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249290591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.249290591
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.918893501
Short name T527
Test name
Test status
Simulation time 1689941595 ps
CPU time 6.4 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:23:35 AM PDT 24
Peak memory 198244 kb
Host smart-8a5611d1-0ee2-4f1f-9277-89e2192db3a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918893501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.918893501
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3603384120
Short name T1050
Test name
Test status
Simulation time 15488904786 ps
CPU time 23.82 seconds
Started Jul 02 09:23:23 AM PDT 24
Finished Jul 02 09:23:51 AM PDT 24
Peak memory 199368 kb
Host smart-b4a8a714-6d8a-47ab-b17e-158cf8624c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603384120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3603384120
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1203727447
Short name T738
Test name
Test status
Simulation time 47317342248 ps
CPU time 13.24 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:36 AM PDT 24
Peak memory 196396 kb
Host smart-e9427ed6-58de-4971-8394-695b97924b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203727447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1203727447
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3790776927
Short name T864
Test name
Test status
Simulation time 6329382753 ps
CPU time 17.21 seconds
Started Jul 02 09:23:27 AM PDT 24
Finished Jul 02 09:23:47 AM PDT 24
Peak memory 199996 kb
Host smart-c74891ea-7743-4391-81b3-4bffe78ee3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790776927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3790776927
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.191372332
Short name T696
Test name
Test status
Simulation time 100576553163 ps
CPU time 154.88 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:25:57 AM PDT 24
Peak memory 199848 kb
Host smart-c59bbc5e-b930-4021-8941-c003d3ef3ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191372332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.191372332
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4262141032
Short name T65
Test name
Test status
Simulation time 739650719 ps
CPU time 2.24 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:24 AM PDT 24
Peak memory 199556 kb
Host smart-90564607-85bb-4d87-9329-e4a84f81bc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262141032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4262141032
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1783649397
Short name T605
Test name
Test status
Simulation time 30515272433 ps
CPU time 54.16 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:24:16 AM PDT 24
Peak memory 200000 kb
Host smart-9ece024d-2551-48fe-ba1f-fb793ec4c917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783649397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1783649397
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.4123600854
Short name T564
Test name
Test status
Simulation time 8315278961 ps
CPU time 8.64 seconds
Started Jul 02 09:26:10 AM PDT 24
Finished Jul 02 09:26:19 AM PDT 24
Peak memory 199944 kb
Host smart-b10971ff-270b-4b55-b95f-f7eb556cd228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123600854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.4123600854
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1549146404
Short name T653
Test name
Test status
Simulation time 27846412991 ps
CPU time 22.11 seconds
Started Jul 02 09:26:11 AM PDT 24
Finished Jul 02 09:26:34 AM PDT 24
Peak memory 199948 kb
Host smart-42dbef1b-7751-42ce-a5dd-f00bb2900762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549146404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1549146404
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2027759449
Short name T1017
Test name
Test status
Simulation time 107528339939 ps
CPU time 161.77 seconds
Started Jul 02 09:26:11 AM PDT 24
Finished Jul 02 09:28:54 AM PDT 24
Peak memory 199972 kb
Host smart-cb4ce3eb-07b4-449f-8f31-77487aaf21c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027759449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2027759449
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.90118613
Short name T440
Test name
Test status
Simulation time 212582219309 ps
CPU time 72.42 seconds
Started Jul 02 09:26:10 AM PDT 24
Finished Jul 02 09:27:23 AM PDT 24
Peak memory 200000 kb
Host smart-ea7b242e-6819-43cb-9c6f-2b1ac2992fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90118613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.90118613
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1865118438
Short name T827
Test name
Test status
Simulation time 9826002516 ps
CPU time 17.84 seconds
Started Jul 02 09:26:10 AM PDT 24
Finished Jul 02 09:26:29 AM PDT 24
Peak memory 199900 kb
Host smart-fb693db2-be66-4d5e-a27d-1251a4504455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865118438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1865118438
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.4196006557
Short name T449
Test name
Test status
Simulation time 196445238344 ps
CPU time 295.2 seconds
Started Jul 02 09:26:12 AM PDT 24
Finished Jul 02 09:31:08 AM PDT 24
Peak memory 199952 kb
Host smart-37b0fdc3-62fe-4fb4-846a-e9376abe6315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196006557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4196006557
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1990109038
Short name T383
Test name
Test status
Simulation time 240072755285 ps
CPU time 22.94 seconds
Started Jul 02 09:26:16 AM PDT 24
Finished Jul 02 09:26:39 AM PDT 24
Peak memory 199940 kb
Host smart-f1f61668-b2ba-4a08-88de-edf1d1eb9ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990109038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1990109038
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3162125251
Short name T1057
Test name
Test status
Simulation time 31475783185 ps
CPU time 23.44 seconds
Started Jul 02 09:26:17 AM PDT 24
Finished Jul 02 09:26:40 AM PDT 24
Peak memory 200208 kb
Host smart-3cd0215b-21c0-4949-90d9-1401e9b4e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162125251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3162125251
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.571449231
Short name T789
Test name
Test status
Simulation time 17751079840 ps
CPU time 26.96 seconds
Started Jul 02 09:26:15 AM PDT 24
Finished Jul 02 09:26:43 AM PDT 24
Peak memory 199964 kb
Host smart-6104dab8-d6c5-42ca-bd35-992463266fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571449231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.571449231
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.586975798
Short name T678
Test name
Test status
Simulation time 12041954 ps
CPU time 0.57 seconds
Started Jul 02 09:23:36 AM PDT 24
Finished Jul 02 09:23:38 AM PDT 24
Peak memory 195272 kb
Host smart-9fc20ab2-5abc-4803-b686-6338a091d89d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586975798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.586975798
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1819168767
Short name T308
Test name
Test status
Simulation time 133818241119 ps
CPU time 28.94 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:23:57 AM PDT 24
Peak memory 199968 kb
Host smart-1c5101ab-d178-4d34-a4af-c68b0a1812ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819168767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1819168767
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3566801002
Short name T1001
Test name
Test status
Simulation time 99031145437 ps
CPU time 8.6 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:32 AM PDT 24
Peak memory 199992 kb
Host smart-805b0ae8-ee36-4e81-ba3a-8489609415d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566801002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3566801002
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.812834158
Short name T664
Test name
Test status
Simulation time 58055381910 ps
CPU time 64.78 seconds
Started Jul 02 09:23:24 AM PDT 24
Finished Jul 02 09:24:33 AM PDT 24
Peak memory 199996 kb
Host smart-59e348bf-1d12-486d-be1d-48f5598d1ce2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812834158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.812834158
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.640914727
Short name T773
Test name
Test status
Simulation time 169777362016 ps
CPU time 398.16 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:30:02 AM PDT 24
Peak memory 199916 kb
Host smart-1b4887b7-1bcc-475e-b0d7-d4893c2afa51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640914727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.640914727
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.610593311
Short name T586
Test name
Test status
Simulation time 441501453 ps
CPU time 0.77 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:23 AM PDT 24
Peak memory 195756 kb
Host smart-47b4f23d-7a35-44ee-8405-94bb1baedf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610593311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.610593311
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.58048827
Short name T563
Test name
Test status
Simulation time 5783890279 ps
CPU time 162.4 seconds
Started Jul 02 09:23:24 AM PDT 24
Finished Jul 02 09:26:10 AM PDT 24
Peak memory 199836 kb
Host smart-94e37b07-44a4-4bd7-a801-a3b47314d868
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58048827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.58048827
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.4028810847
Short name T367
Test name
Test status
Simulation time 2961776850 ps
CPU time 3.96 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:27 AM PDT 24
Peak memory 198916 kb
Host smart-c3445815-de38-4437-a3ff-497419923fde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028810847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.4028810847
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1311396374
Short name T765
Test name
Test status
Simulation time 72407077024 ps
CPU time 51.41 seconds
Started Jul 02 09:23:21 AM PDT 24
Finished Jul 02 09:24:16 AM PDT 24
Peak memory 199844 kb
Host smart-a0af7188-131c-4b23-9eee-45bedc829a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311396374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1311396374
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1199379096
Short name T772
Test name
Test status
Simulation time 5749822400 ps
CPU time 9.45 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:23:38 AM PDT 24
Peak memory 196412 kb
Host smart-6b39d2bb-540b-44d0-a766-aae92931d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199379096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1199379096
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3592637289
Short name T446
Test name
Test status
Simulation time 5823891230 ps
CPU time 7.21 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:27 AM PDT 24
Peak memory 199588 kb
Host smart-107650d1-022e-4c08-8597-2bc8cdc6ae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592637289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3592637289
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2059117203
Short name T73
Test name
Test status
Simulation time 88643093218 ps
CPU time 727.51 seconds
Started Jul 02 09:23:21 AM PDT 24
Finished Jul 02 09:35:32 AM PDT 24
Peak memory 216536 kb
Host smart-166fcca3-cc25-4a89-a1a5-51a4664799a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059117203 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2059117203
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.4169920491
Short name T1063
Test name
Test status
Simulation time 545873918 ps
CPU time 1.99 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:23:26 AM PDT 24
Peak memory 199112 kb
Host smart-b3441f58-49ff-4d0d-adee-7dbd8437d312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169920491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.4169920491
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1346617721
Short name T404
Test name
Test status
Simulation time 7774178865 ps
CPU time 5.41 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:23:24 AM PDT 24
Peak memory 200004 kb
Host smart-c63387f4-6e4e-4ecd-a7fe-4ca6a8f6007b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346617721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1346617721
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1955431030
Short name T405
Test name
Test status
Simulation time 336962470061 ps
CPU time 662.55 seconds
Started Jul 02 09:26:20 AM PDT 24
Finished Jul 02 09:37:22 AM PDT 24
Peak memory 200004 kb
Host smart-dbc024db-8179-45d9-a8c7-2e9194ac42f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955431030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1955431030
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3600368379
Short name T565
Test name
Test status
Simulation time 111249192565 ps
CPU time 167.82 seconds
Started Jul 02 09:26:19 AM PDT 24
Finished Jul 02 09:29:07 AM PDT 24
Peak memory 200016 kb
Host smart-124d46a0-a316-4219-948a-6a81fae1bc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600368379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3600368379
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.880589008
Short name T866
Test name
Test status
Simulation time 93397172852 ps
CPU time 39.59 seconds
Started Jul 02 09:26:19 AM PDT 24
Finished Jul 02 09:26:59 AM PDT 24
Peak memory 199980 kb
Host smart-7da2bf39-1d2f-4278-8ba5-0e21e53bf609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880589008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.880589008
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1543867864
Short name T889
Test name
Test status
Simulation time 43875275726 ps
CPU time 34.13 seconds
Started Jul 02 09:26:22 AM PDT 24
Finished Jul 02 09:26:57 AM PDT 24
Peak memory 199924 kb
Host smart-34b321e7-3c0e-4274-b571-45690c85245f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543867864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1543867864
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3784670916
Short name T590
Test name
Test status
Simulation time 141399636237 ps
CPU time 79.4 seconds
Started Jul 02 09:26:21 AM PDT 24
Finished Jul 02 09:27:42 AM PDT 24
Peak memory 199944 kb
Host smart-8d8796c6-b488-4abc-acb2-30122aebd1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784670916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3784670916
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.4185249070
Short name T264
Test name
Test status
Simulation time 123985825099 ps
CPU time 194.36 seconds
Started Jul 02 09:26:22 AM PDT 24
Finished Jul 02 09:29:37 AM PDT 24
Peak memory 199960 kb
Host smart-27da0c32-409d-41ae-ad5d-14b48c5c044b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185249070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.4185249070
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1576644651
Short name T1064
Test name
Test status
Simulation time 9892507104 ps
CPU time 10.75 seconds
Started Jul 02 09:26:19 AM PDT 24
Finished Jul 02 09:26:30 AM PDT 24
Peak memory 199952 kb
Host smart-208f4016-35dc-44f7-8b47-a2751d638f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576644651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1576644651
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1932510864
Short name T588
Test name
Test status
Simulation time 49037362891 ps
CPU time 22.52 seconds
Started Jul 02 09:26:18 AM PDT 24
Finished Jul 02 09:26:41 AM PDT 24
Peak memory 199924 kb
Host smart-399f7c87-4d55-41b9-b054-e1e14efed0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932510864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1932510864
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3065962548
Short name T651
Test name
Test status
Simulation time 37996152422 ps
CPU time 20.08 seconds
Started Jul 02 09:26:19 AM PDT 24
Finished Jul 02 09:26:39 AM PDT 24
Peak memory 199976 kb
Host smart-cabebf38-1d3a-47f0-96ae-9e50eab07480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065962548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3065962548
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2915985389
Short name T788
Test name
Test status
Simulation time 44767069 ps
CPU time 0.57 seconds
Started Jul 02 09:23:40 AM PDT 24
Finished Jul 02 09:23:42 AM PDT 24
Peak memory 195300 kb
Host smart-9a53be2d-2a1f-4404-ac38-f2db91095d57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915985389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2915985389
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.422151035
Short name T47
Test name
Test status
Simulation time 92024005589 ps
CPU time 31.71 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:24:00 AM PDT 24
Peak memory 199944 kb
Host smart-5a752948-feca-43b1-87b7-8d64b21eef24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422151035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.422151035
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.222016828
Short name T698
Test name
Test status
Simulation time 207308749947 ps
CPU time 457.93 seconds
Started Jul 02 09:23:40 AM PDT 24
Finished Jul 02 09:31:20 AM PDT 24
Peak memory 200008 kb
Host smart-873b71cf-3a21-4340-b63d-45259271d2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222016828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.222016828
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2996133910
Short name T1035
Test name
Test status
Simulation time 46603308619 ps
CPU time 65 seconds
Started Jul 02 09:23:21 AM PDT 24
Finished Jul 02 09:24:30 AM PDT 24
Peak memory 199992 kb
Host smart-2c863543-ca05-416a-adf8-1a07286d53a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996133910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2996133910
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2782222616
Short name T462
Test name
Test status
Simulation time 257067892578 ps
CPU time 459.79 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:31:03 AM PDT 24
Peak memory 199084 kb
Host smart-01de71c3-7400-4eab-a635-0a74f8751b8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782222616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2782222616
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.723911954
Short name T779
Test name
Test status
Simulation time 344345788976 ps
CPU time 416.61 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:30:21 AM PDT 24
Peak memory 199936 kb
Host smart-c6438d8f-9af8-42ec-a3e3-1182354918af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723911954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.723911954
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2902709847
Short name T375
Test name
Test status
Simulation time 6666211344 ps
CPU time 8.33 seconds
Started Jul 02 09:23:21 AM PDT 24
Finished Jul 02 09:23:34 AM PDT 24
Peak memory 198904 kb
Host smart-6fdbe485-f0d1-47e9-baba-4275b87a0e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902709847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2902709847
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.3944472363
Short name T899
Test name
Test status
Simulation time 14237059743 ps
CPU time 205.49 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:26:49 AM PDT 24
Peak memory 199968 kb
Host smart-e6c0b623-29db-4eaf-bbe0-cc5921dcd1eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944472363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3944472363
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2320569848
Short name T989
Test name
Test status
Simulation time 1375652551 ps
CPU time 2.65 seconds
Started Jul 02 09:23:40 AM PDT 24
Finished Jul 02 09:23:44 AM PDT 24
Peak memory 196796 kb
Host smart-78774012-186f-475f-99d1-b6755e074396
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320569848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2320569848
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2636414236
Short name T496
Test name
Test status
Simulation time 159077071086 ps
CPU time 70.3 seconds
Started Jul 02 09:23:40 AM PDT 24
Finished Jul 02 09:24:52 AM PDT 24
Peak memory 200020 kb
Host smart-0b39cda3-ada6-46a3-9e4a-255bf36f2455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636414236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2636414236
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.726714637
Short name T937
Test name
Test status
Simulation time 1377874192 ps
CPU time 1.56 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:23:30 AM PDT 24
Peak memory 195552 kb
Host smart-85f058ca-649a-40c2-a3bd-d0fa95bfdda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726714637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.726714637
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1534052554
Short name T730
Test name
Test status
Simulation time 649155831 ps
CPU time 1.5 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:22 AM PDT 24
Peak memory 198460 kb
Host smart-e838a755-f330-4a9e-8404-ab2a07ff1f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534052554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1534052554
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2385468384
Short name T1077
Test name
Test status
Simulation time 220243207788 ps
CPU time 97.83 seconds
Started Jul 02 09:23:24 AM PDT 24
Finished Jul 02 09:25:05 AM PDT 24
Peak memory 199968 kb
Host smart-fb7b1f38-caa7-4fb6-bd0e-80c6c86f8a27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385468384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2385468384
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1139899117
Short name T107
Test name
Test status
Simulation time 18582217365 ps
CPU time 173.42 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:26:17 AM PDT 24
Peak memory 216452 kb
Host smart-32a88e2f-0390-4088-9488-e0c7170b25dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139899117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1139899117
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3724628546
Short name T528
Test name
Test status
Simulation time 2136372439 ps
CPU time 2.47 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:23:31 AM PDT 24
Peak memory 198388 kb
Host smart-3eb19e6d-ed7d-40ec-a77b-ba12546e5eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724628546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3724628546
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2114001811
Short name T978
Test name
Test status
Simulation time 68504146079 ps
CPU time 101.85 seconds
Started Jul 02 09:23:40 AM PDT 24
Finished Jul 02 09:25:23 AM PDT 24
Peak memory 199972 kb
Host smart-983be6ec-dfff-4629-ae9f-21e6431690f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114001811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2114001811
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.4112582504
Short name T69
Test name
Test status
Simulation time 34057975330 ps
CPU time 61.88 seconds
Started Jul 02 09:26:23 AM PDT 24
Finished Jul 02 09:27:25 AM PDT 24
Peak memory 199904 kb
Host smart-fd2aafb2-a84f-423f-b28b-69e67d9b85d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112582504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.4112582504
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.4058228441
Short name T180
Test name
Test status
Simulation time 77867677499 ps
CPU time 26.94 seconds
Started Jul 02 09:26:24 AM PDT 24
Finished Jul 02 09:26:52 AM PDT 24
Peak memory 199872 kb
Host smart-98670939-81e1-4de7-837a-9511080fdfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058228441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4058228441
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1581772335
Short name T353
Test name
Test status
Simulation time 67602129006 ps
CPU time 191.64 seconds
Started Jul 02 09:26:23 AM PDT 24
Finished Jul 02 09:29:35 AM PDT 24
Peak memory 200008 kb
Host smart-c0cdd917-5153-44d9-8648-7be01d083a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581772335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1581772335
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2734203346
Short name T290
Test name
Test status
Simulation time 95915796384 ps
CPU time 68.82 seconds
Started Jul 02 09:26:21 AM PDT 24
Finished Jul 02 09:27:31 AM PDT 24
Peak memory 199932 kb
Host smart-040cea54-fda7-45a9-920f-d946fe8ff20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734203346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2734203346
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2544124139
Short name T993
Test name
Test status
Simulation time 247385467318 ps
CPU time 27.13 seconds
Started Jul 02 09:26:23 AM PDT 24
Finished Jul 02 09:26:51 AM PDT 24
Peak memory 199968 kb
Host smart-19cfaa28-f621-4a06-86d4-2d0b0b6ca015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544124139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2544124139
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.523883756
Short name T969
Test name
Test status
Simulation time 66480907925 ps
CPU time 46.58 seconds
Started Jul 02 09:26:24 AM PDT 24
Finished Jul 02 09:27:11 AM PDT 24
Peak memory 199908 kb
Host smart-575e8675-3f93-41ac-9bd1-40047d2bb021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523883756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.523883756
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1226746310
Short name T764
Test name
Test status
Simulation time 17794876359 ps
CPU time 15.3 seconds
Started Jul 02 09:26:22 AM PDT 24
Finished Jul 02 09:26:38 AM PDT 24
Peak memory 199964 kb
Host smart-304e4ff3-e160-45b0-b95e-1c9a01de4c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226746310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1226746310
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3001636905
Short name T136
Test name
Test status
Simulation time 29650121856 ps
CPU time 13.33 seconds
Started Jul 02 09:26:22 AM PDT 24
Finished Jul 02 09:26:36 AM PDT 24
Peak memory 200004 kb
Host smart-70caea06-4192-4049-8214-bc94e000d346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001636905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3001636905
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2041404983
Short name T497
Test name
Test status
Simulation time 14556735 ps
CPU time 0.57 seconds
Started Jul 02 09:23:24 AM PDT 24
Finished Jul 02 09:23:28 AM PDT 24
Peak memory 195272 kb
Host smart-a58a48de-1d6c-4ab3-ac74-f443508d565e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041404983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2041404983
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1724000725
Short name T801
Test name
Test status
Simulation time 29016423118 ps
CPU time 45.62 seconds
Started Jul 02 09:23:40 AM PDT 24
Finished Jul 02 09:24:27 AM PDT 24
Peak memory 200008 kb
Host smart-68721c39-b88c-4c90-9b20-0da80de1de44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724000725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1724000725
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.800294334
Short name T720
Test name
Test status
Simulation time 136511254019 ps
CPU time 57.89 seconds
Started Jul 02 09:23:23 AM PDT 24
Finished Jul 02 09:24:24 AM PDT 24
Peak memory 199908 kb
Host smart-45f52b9d-778c-4046-a27f-7d36369056c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800294334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.800294334
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2695839153
Short name T258
Test name
Test status
Simulation time 17124518873 ps
CPU time 14.72 seconds
Started Jul 02 09:23:40 AM PDT 24
Finished Jul 02 09:23:56 AM PDT 24
Peak memory 199980 kb
Host smart-acfe74c6-35de-4d99-9e0f-12ccef07af8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695839153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2695839153
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.749900567
Short name T439
Test name
Test status
Simulation time 224104704217 ps
CPU time 199.23 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:26:47 AM PDT 24
Peak memory 199948 kb
Host smart-2f2938a1-4c98-4861-a186-ae5fc3bd5ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=749900567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.749900567
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2307618053
Short name T525
Test name
Test status
Simulation time 5832162764 ps
CPU time 7.9 seconds
Started Jul 02 09:23:27 AM PDT 24
Finished Jul 02 09:23:37 AM PDT 24
Peak memory 198696 kb
Host smart-6ad9a659-ec60-44af-8974-be136502d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307618053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2307618053
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.3220155002
Short name T320
Test name
Test status
Simulation time 16531067495 ps
CPU time 197.3 seconds
Started Jul 02 09:23:21 AM PDT 24
Finished Jul 02 09:26:43 AM PDT 24
Peak memory 199888 kb
Host smart-d0bf4651-76fa-4e58-bc5a-09c76cd0062d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220155002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3220155002
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.4000441374
Short name T395
Test name
Test status
Simulation time 4190559871 ps
CPU time 31.18 seconds
Started Jul 02 09:23:29 AM PDT 24
Finished Jul 02 09:24:02 AM PDT 24
Peak memory 197296 kb
Host smart-9d67cd03-51b0-4fd4-b1fa-68d062e1f5ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4000441374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4000441374
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3987019350
Short name T985
Test name
Test status
Simulation time 1543071478 ps
CPU time 1.15 seconds
Started Jul 02 09:23:27 AM PDT 24
Finished Jul 02 09:23:31 AM PDT 24
Peak memory 195588 kb
Host smart-750f1b5e-5876-49da-ba3c-5db9a6890176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987019350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3987019350
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.960690087
Short name T728
Test name
Test status
Simulation time 527036098 ps
CPU time 1.32 seconds
Started Jul 02 09:23:40 AM PDT 24
Finished Jul 02 09:23:43 AM PDT 24
Peak memory 198484 kb
Host smart-2e1d3e2d-189a-4380-99a3-fc8413d7b216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960690087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.960690087
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2110379392
Short name T677
Test name
Test status
Simulation time 301928857854 ps
CPU time 413.37 seconds
Started Jul 02 09:23:29 AM PDT 24
Finished Jul 02 09:30:24 AM PDT 24
Peak memory 199984 kb
Host smart-c0c315ba-3a2e-4e9e-99bc-aebff2322cd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110379392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2110379392
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3977401906
Short name T55
Test name
Test status
Simulation time 125864066848 ps
CPU time 344.48 seconds
Started Jul 02 09:23:22 AM PDT 24
Finished Jul 02 09:29:11 AM PDT 24
Peak memory 216508 kb
Host smart-8561abde-b18d-4f15-8092-6dc27f0f603a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977401906 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3977401906
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3135866014
Short name T743
Test name
Test status
Simulation time 7166109034 ps
CPU time 8.95 seconds
Started Jul 02 09:23:23 AM PDT 24
Finished Jul 02 09:23:36 AM PDT 24
Peak memory 199776 kb
Host smart-6d006fc7-7b58-42b8-a0f7-7dd8f3c37d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135866014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3135866014
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3926590428
Short name T288
Test name
Test status
Simulation time 175457471170 ps
CPU time 175.2 seconds
Started Jul 02 09:23:34 AM PDT 24
Finished Jul 02 09:26:30 AM PDT 24
Peak memory 199988 kb
Host smart-f1b386e7-cff2-4e08-9f41-0fe46199f0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926590428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3926590428
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3323550086
Short name T1044
Test name
Test status
Simulation time 39823020014 ps
CPU time 63.31 seconds
Started Jul 02 09:26:23 AM PDT 24
Finished Jul 02 09:27:27 AM PDT 24
Peak memory 199968 kb
Host smart-45ff013c-e1b4-4bdd-a7e0-6db34d601cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323550086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3323550086
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1861683671
Short name T253
Test name
Test status
Simulation time 9925789850 ps
CPU time 17.01 seconds
Started Jul 02 09:26:24 AM PDT 24
Finished Jul 02 09:26:41 AM PDT 24
Peak memory 199944 kb
Host smart-82af5381-af94-47e2-8999-231dde20c1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861683671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1861683671
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1655600461
Short name T1015
Test name
Test status
Simulation time 16251394573 ps
CPU time 14.34 seconds
Started Jul 02 09:26:22 AM PDT 24
Finished Jul 02 09:26:37 AM PDT 24
Peak memory 198308 kb
Host smart-accb7070-191b-4b77-9b86-14eab841ba24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655600461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1655600461
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3908084578
Short name T655
Test name
Test status
Simulation time 118440605285 ps
CPU time 204.26 seconds
Started Jul 02 09:26:24 AM PDT 24
Finished Jul 02 09:29:49 AM PDT 24
Peak memory 200004 kb
Host smart-3424d966-8dd9-496f-a428-5ab4a775536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908084578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3908084578
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3528708543
Short name T159
Test name
Test status
Simulation time 143525712843 ps
CPU time 44.08 seconds
Started Jul 02 09:26:27 AM PDT 24
Finished Jul 02 09:27:11 AM PDT 24
Peak memory 199916 kb
Host smart-59122008-9171-4ca9-a729-8c12ee11eb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528708543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3528708543
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2996092264
Short name T406
Test name
Test status
Simulation time 91025275151 ps
CPU time 7.8 seconds
Started Jul 02 09:26:27 AM PDT 24
Finished Jul 02 09:26:36 AM PDT 24
Peak memory 200012 kb
Host smart-8f29cbea-3cd6-4708-ab56-95433c8eab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996092264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2996092264
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1314972787
Short name T235
Test name
Test status
Simulation time 9590744275 ps
CPU time 15.8 seconds
Started Jul 02 09:26:26 AM PDT 24
Finished Jul 02 09:26:42 AM PDT 24
Peak memory 199776 kb
Host smart-c8ae88b6-354e-4c64-a234-45999f17ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314972787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1314972787
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2223194246
Short name T626
Test name
Test status
Simulation time 18888560072 ps
CPU time 19.02 seconds
Started Jul 02 09:26:27 AM PDT 24
Finished Jul 02 09:26:46 AM PDT 24
Peak memory 200020 kb
Host smart-c4b1831f-11d5-4fbb-8970-f2c15cdb61bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223194246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2223194246
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2483236605
Short name T809
Test name
Test status
Simulation time 36657250491 ps
CPU time 31.99 seconds
Started Jul 02 09:26:26 AM PDT 24
Finished Jul 02 09:26:58 AM PDT 24
Peak memory 199900 kb
Host smart-08d6eb79-56d1-41b8-a1ed-d50d7bcbd1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483236605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2483236605
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2844273325
Short name T23
Test name
Test status
Simulation time 10540274 ps
CPU time 0.56 seconds
Started Jul 02 09:23:34 AM PDT 24
Finished Jul 02 09:23:35 AM PDT 24
Peak memory 194540 kb
Host smart-8964f8b0-e0b5-41fb-b228-ab378c0d10bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844273325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2844273325
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2641025623
Short name T1006
Test name
Test status
Simulation time 142174808915 ps
CPU time 217.09 seconds
Started Jul 02 09:23:27 AM PDT 24
Finished Jul 02 09:27:06 AM PDT 24
Peak memory 199864 kb
Host smart-40a8aa17-8dad-41bf-93f7-cd1d5811d570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641025623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2641025623
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1934857810
Short name T442
Test name
Test status
Simulation time 152800927825 ps
CPU time 91.21 seconds
Started Jul 02 09:23:27 AM PDT 24
Finished Jul 02 09:25:00 AM PDT 24
Peak memory 199940 kb
Host smart-8cc1c155-2331-44ab-8504-fecdc1ed009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934857810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1934857810
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3910998951
Short name T326
Test name
Test status
Simulation time 68487822510 ps
CPU time 99.65 seconds
Started Jul 02 09:23:29 AM PDT 24
Finished Jul 02 09:25:11 AM PDT 24
Peak memory 200004 kb
Host smart-d3fd95af-a117-45ed-ab24-b022ffebab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910998951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3910998951
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.810270709
Short name T380
Test name
Test status
Simulation time 275663544941 ps
CPU time 86.5 seconds
Started Jul 02 09:23:29 AM PDT 24
Finished Jul 02 09:24:57 AM PDT 24
Peak memory 196900 kb
Host smart-b2c39b24-71c5-4a8d-871f-13509a0dbd69
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810270709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.810270709
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3695845922
Short name T1049
Test name
Test status
Simulation time 156351556800 ps
CPU time 239.18 seconds
Started Jul 02 09:23:30 AM PDT 24
Finished Jul 02 09:27:30 AM PDT 24
Peak memory 199892 kb
Host smart-83c70b8b-5b75-4e47-8bc7-0ee3ddae4731
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695845922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3695845922
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3384547784
Short name T422
Test name
Test status
Simulation time 5509714524 ps
CPU time 9.53 seconds
Started Jul 02 09:23:27 AM PDT 24
Finished Jul 02 09:23:39 AM PDT 24
Peak memory 198920 kb
Host smart-30674f02-fd0a-4691-b1f3-e4f1e77e03f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384547784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3384547784
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.2094044305
Short name T260
Test name
Test status
Simulation time 10120132748 ps
CPU time 556.74 seconds
Started Jul 02 09:23:28 AM PDT 24
Finished Jul 02 09:32:47 AM PDT 24
Peak memory 200092 kb
Host smart-7ca3b77c-6b13-4a67-8fbc-dbdb4c8d8dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2094044305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2094044305
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3078970572
Short name T721
Test name
Test status
Simulation time 7582587739 ps
CPU time 18.4 seconds
Started Jul 02 09:23:31 AM PDT 24
Finished Jul 02 09:23:51 AM PDT 24
Peak memory 199936 kb
Host smart-a5b67f36-4975-4ebc-a3eb-f6b958cf3ce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3078970572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3078970572
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.864798241
Short name T908
Test name
Test status
Simulation time 53255006027 ps
CPU time 107.18 seconds
Started Jul 02 09:23:26 AM PDT 24
Finished Jul 02 09:25:16 AM PDT 24
Peak memory 199896 kb
Host smart-7b62a42a-d483-42f9-87a9-478fca189ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864798241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.864798241
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2781142897
Short name T373
Test name
Test status
Simulation time 6132182275 ps
CPU time 2.91 seconds
Started Jul 02 09:23:26 AM PDT 24
Finished Jul 02 09:23:32 AM PDT 24
Peak memory 196376 kb
Host smart-001f45a4-0fda-4ff4-a6d6-560c5c9a4fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781142897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2781142897
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2691053989
Short name T734
Test name
Test status
Simulation time 713398775 ps
CPU time 3.21 seconds
Started Jul 02 09:23:22 AM PDT 24
Finished Jul 02 09:23:29 AM PDT 24
Peak memory 198404 kb
Host smart-dda5b4af-c8df-4691-9dea-3a14122ec375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691053989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2691053989
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1736456319
Short name T490
Test name
Test status
Simulation time 193390156642 ps
CPU time 313.53 seconds
Started Jul 02 09:23:24 AM PDT 24
Finished Jul 02 09:28:41 AM PDT 24
Peak memory 199976 kb
Host smart-0d9bbe99-e675-4def-96bf-f73672d9e513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736456319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1736456319
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3765832257
Short name T297
Test name
Test status
Simulation time 3326680494 ps
CPU time 1.56 seconds
Started Jul 02 09:23:28 AM PDT 24
Finished Jul 02 09:23:32 AM PDT 24
Peak memory 199128 kb
Host smart-7ef116c9-91e9-4a6a-b9a4-5b061e5dc474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765832257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3765832257
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1439518108
Short name T538
Test name
Test status
Simulation time 45321719623 ps
CPU time 68.34 seconds
Started Jul 02 09:23:22 AM PDT 24
Finished Jul 02 09:24:35 AM PDT 24
Peak memory 199860 kb
Host smart-356d3613-4dc7-4f1f-be3d-dae9e17b0587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439518108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1439518108
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2895648755
Short name T1036
Test name
Test status
Simulation time 333984810861 ps
CPU time 502.99 seconds
Started Jul 02 09:26:26 AM PDT 24
Finished Jul 02 09:34:49 AM PDT 24
Peak memory 200012 kb
Host smart-f7905ffd-d62b-4586-b807-f1994cc07e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895648755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2895648755
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2255714120
Short name T781
Test name
Test status
Simulation time 184266141018 ps
CPU time 39.7 seconds
Started Jul 02 09:26:28 AM PDT 24
Finished Jul 02 09:27:08 AM PDT 24
Peak memory 200024 kb
Host smart-fb84f1d2-ef67-4278-bbb2-6636ddc32b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255714120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2255714120
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3040269596
Short name T225
Test name
Test status
Simulation time 30521262869 ps
CPU time 26.44 seconds
Started Jul 02 09:26:26 AM PDT 24
Finished Jul 02 09:26:54 AM PDT 24
Peak memory 199984 kb
Host smart-8a951960-6f11-471d-b17d-7070ef78b5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040269596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3040269596
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3589678006
Short name T915
Test name
Test status
Simulation time 14778824353 ps
CPU time 21.51 seconds
Started Jul 02 09:26:27 AM PDT 24
Finished Jul 02 09:26:49 AM PDT 24
Peak memory 199932 kb
Host smart-b2773dd7-3738-4227-adec-28b88894f8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589678006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3589678006
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3623856607
Short name T554
Test name
Test status
Simulation time 14646403447 ps
CPU time 27.4 seconds
Started Jul 02 09:26:34 AM PDT 24
Finished Jul 02 09:27:02 AM PDT 24
Peak memory 199984 kb
Host smart-581d26c4-c6b6-46eb-99a2-b4a51fc72717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623856607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3623856607
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1376243644
Short name T799
Test name
Test status
Simulation time 96660998597 ps
CPU time 18.27 seconds
Started Jul 02 09:26:31 AM PDT 24
Finished Jul 02 09:26:51 AM PDT 24
Peak memory 200012 kb
Host smart-cd5cf4e1-498b-402e-a0ed-a1ef571fba8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376243644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1376243644
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2354843337
Short name T347
Test name
Test status
Simulation time 148363170867 ps
CPU time 238.18 seconds
Started Jul 02 09:26:30 AM PDT 24
Finished Jul 02 09:30:29 AM PDT 24
Peak memory 199916 kb
Host smart-845eb306-35c0-4131-98e5-a5c936aef372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354843337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2354843337
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2651522374
Short name T244
Test name
Test status
Simulation time 182331419667 ps
CPU time 162.9 seconds
Started Jul 02 09:26:30 AM PDT 24
Finished Jul 02 09:29:14 AM PDT 24
Peak memory 199972 kb
Host smart-3e2773e1-171e-48f4-bfbb-27ace44441fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651522374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2651522374
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1390242520
Short name T817
Test name
Test status
Simulation time 41038574 ps
CPU time 0.56 seconds
Started Jul 02 09:23:32 AM PDT 24
Finished Jul 02 09:23:34 AM PDT 24
Peak memory 195568 kb
Host smart-0088c8ca-8cce-44f1-879d-ea0a3653a4d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390242520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1390242520
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3243052631
Short name T186
Test name
Test status
Simulation time 28385040315 ps
CPU time 10.57 seconds
Started Jul 02 09:23:31 AM PDT 24
Finished Jul 02 09:23:43 AM PDT 24
Peak memory 199908 kb
Host smart-ca54c8eb-8f2b-4ce8-86d6-c48baaa6e70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243052631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3243052631
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.4203600029
Short name T923
Test name
Test status
Simulation time 133468560805 ps
CPU time 84.17 seconds
Started Jul 02 09:23:29 AM PDT 24
Finished Jul 02 09:24:55 AM PDT 24
Peak memory 199332 kb
Host smart-bbafb8bf-2974-47ff-afcc-243fe246ca5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203600029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.4203600029
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1122753266
Short name T596
Test name
Test status
Simulation time 68591171260 ps
CPU time 109.58 seconds
Started Jul 02 09:23:37 AM PDT 24
Finished Jul 02 09:25:28 AM PDT 24
Peak memory 199956 kb
Host smart-fce78efe-d292-4a7a-b044-92035e014e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122753266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1122753266
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3885817888
Short name T591
Test name
Test status
Simulation time 25305751192 ps
CPU time 43.34 seconds
Started Jul 02 09:23:27 AM PDT 24
Finished Jul 02 09:24:13 AM PDT 24
Peak memory 199828 kb
Host smart-3eaf4a08-0fb4-4e3a-8b23-dbb67afd1756
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885817888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3885817888
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1919973893
Short name T486
Test name
Test status
Simulation time 80947731931 ps
CPU time 609.56 seconds
Started Jul 02 09:23:37 AM PDT 24
Finished Jul 02 09:33:48 AM PDT 24
Peak memory 199984 kb
Host smart-a041f90c-8dda-4e57-953b-dae3e8502958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919973893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1919973893
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2406160285
Short name T822
Test name
Test status
Simulation time 10213837558 ps
CPU time 12.46 seconds
Started Jul 02 09:23:32 AM PDT 24
Finished Jul 02 09:23:46 AM PDT 24
Peak memory 199816 kb
Host smart-1484e23f-ffc4-4dad-9558-1e3df26cb101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406160285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2406160285
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.3649225323
Short name T633
Test name
Test status
Simulation time 19430391342 ps
CPU time 245.86 seconds
Started Jul 02 09:23:31 AM PDT 24
Finished Jul 02 09:27:38 AM PDT 24
Peak memory 199992 kb
Host smart-fd144912-5e3a-4a72-a3be-91589986b8ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649225323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3649225323
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1289293694
Short name T523
Test name
Test status
Simulation time 1601652344 ps
CPU time 3 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:23:31 AM PDT 24
Peak memory 198156 kb
Host smart-42c6c05f-d3dc-4a52-ade0-55534f72ddcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289293694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1289293694
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.647783669
Short name T996
Test name
Test status
Simulation time 152830012251 ps
CPU time 19.79 seconds
Started Jul 02 09:23:37 AM PDT 24
Finished Jul 02 09:23:58 AM PDT 24
Peak memory 199992 kb
Host smart-cab32d43-7ef9-4160-8788-4010bcdd4bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647783669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.647783669
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.456320168
Short name T1003
Test name
Test status
Simulation time 1787348733 ps
CPU time 3.01 seconds
Started Jul 02 09:23:32 AM PDT 24
Finished Jul 02 09:23:36 AM PDT 24
Peak memory 195564 kb
Host smart-c2104b1d-ba1c-4858-97c0-d8a850f6bc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456320168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.456320168
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2098555991
Short name T823
Test name
Test status
Simulation time 11584262060 ps
CPU time 25.55 seconds
Started Jul 02 09:23:28 AM PDT 24
Finished Jul 02 09:23:55 AM PDT 24
Peak memory 200136 kb
Host smart-44872874-e01c-4dc1-8866-c62d55e41e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098555991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2098555991
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.46019999
Short name T112
Test name
Test status
Simulation time 53948552843 ps
CPU time 22.43 seconds
Started Jul 02 09:23:31 AM PDT 24
Finished Jul 02 09:23:55 AM PDT 24
Peak memory 199876 kb
Host smart-1ed33b62-8e0f-4d56-bcef-c97022e0269a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46019999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.46019999
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4095735407
Short name T708
Test name
Test status
Simulation time 90728044761 ps
CPU time 476.04 seconds
Started Jul 02 09:23:31 AM PDT 24
Finished Jul 02 09:31:29 AM PDT 24
Peak memory 216460 kb
Host smart-a3d84ead-9f55-4853-8772-9575556213a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095735407 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4095735407
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.895641391
Short name T706
Test name
Test status
Simulation time 945556718 ps
CPU time 2.76 seconds
Started Jul 02 09:23:32 AM PDT 24
Finished Jul 02 09:23:36 AM PDT 24
Peak memory 198820 kb
Host smart-09021b41-4dfa-40a9-b05f-7632cd918538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895641391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.895641391
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2556786882
Short name T456
Test name
Test status
Simulation time 44983152031 ps
CPU time 55.34 seconds
Started Jul 02 09:23:25 AM PDT 24
Finished Jul 02 09:24:24 AM PDT 24
Peak memory 199932 kb
Host smart-fe3799d2-d557-4ac9-ae7c-2fe23119965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556786882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2556786882
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3965160346
Short name T454
Test name
Test status
Simulation time 6323231306 ps
CPU time 8.86 seconds
Started Jul 02 09:26:30 AM PDT 24
Finished Jul 02 09:26:40 AM PDT 24
Peak memory 198788 kb
Host smart-5a10d2ef-ef6e-4421-928b-fd0beb7459fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965160346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3965160346
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1328064200
Short name T429
Test name
Test status
Simulation time 46504627410 ps
CPU time 69.81 seconds
Started Jul 02 09:26:32 AM PDT 24
Finished Jul 02 09:27:43 AM PDT 24
Peak memory 199912 kb
Host smart-0c258537-92c0-46ae-a88e-d057088b50fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328064200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1328064200
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2384490004
Short name T631
Test name
Test status
Simulation time 115993021997 ps
CPU time 164.98 seconds
Started Jul 02 09:26:31 AM PDT 24
Finished Jul 02 09:29:17 AM PDT 24
Peak memory 199956 kb
Host smart-5eef89d0-5803-46d8-a85d-1b82783ab100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384490004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2384490004
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2903940710
Short name T49
Test name
Test status
Simulation time 45702869435 ps
CPU time 104.48 seconds
Started Jul 02 09:26:31 AM PDT 24
Finished Jul 02 09:28:17 AM PDT 24
Peak memory 199908 kb
Host smart-8a434222-9f63-4e15-90d3-ae7d44e47cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903940710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2903940710
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1977506209
Short name T224
Test name
Test status
Simulation time 118774827406 ps
CPU time 160.89 seconds
Started Jul 02 09:26:30 AM PDT 24
Finished Jul 02 09:29:12 AM PDT 24
Peak memory 199912 kb
Host smart-118163f7-21dc-4f30-af4a-769100604f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977506209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1977506209
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3849983179
Short name T144
Test name
Test status
Simulation time 19102662730 ps
CPU time 32.94 seconds
Started Jul 02 09:26:30 AM PDT 24
Finished Jul 02 09:27:04 AM PDT 24
Peak memory 199884 kb
Host smart-6201baa6-37f2-47c8-8024-bc2fc8f4ccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849983179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3849983179
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3103976667
Short name T197
Test name
Test status
Simulation time 72007681770 ps
CPU time 65.35 seconds
Started Jul 02 09:26:30 AM PDT 24
Finished Jul 02 09:27:36 AM PDT 24
Peak memory 200004 kb
Host smart-6a8b9ce2-e0d5-4d83-8f02-d789361b5dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103976667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3103976667
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.832635725
Short name T254
Test name
Test status
Simulation time 12874004221 ps
CPU time 8.5 seconds
Started Jul 02 09:26:33 AM PDT 24
Finished Jul 02 09:26:42 AM PDT 24
Peak memory 199928 kb
Host smart-c480daaf-58e7-4d3e-ae20-48695906320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832635725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.832635725
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1122417846
Short name T401
Test name
Test status
Simulation time 29778692507 ps
CPU time 10.17 seconds
Started Jul 02 09:26:32 AM PDT 24
Finished Jul 02 09:26:43 AM PDT 24
Peak memory 199472 kb
Host smart-0e44096a-94b2-4443-b8aa-530b2b32268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122417846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1122417846
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.676511532
Short name T356
Test name
Test status
Simulation time 65406595 ps
CPU time 0.56 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:23:09 AM PDT 24
Peak memory 195596 kb
Host smart-d85f943a-bb63-423a-b5ab-c00d1a67892e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676511532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.676511532
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2675422492
Short name T777
Test name
Test status
Simulation time 46918583064 ps
CPU time 14.75 seconds
Started Jul 02 09:22:51 AM PDT 24
Finished Jul 02 09:23:06 AM PDT 24
Peak memory 199904 kb
Host smart-e83c37a4-0b07-4854-a23e-525f724d7c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675422492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2675422492
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3159932686
Short name T425
Test name
Test status
Simulation time 89637682507 ps
CPU time 33.47 seconds
Started Jul 02 09:22:55 AM PDT 24
Finished Jul 02 09:23:29 AM PDT 24
Peak memory 199432 kb
Host smart-9f281703-701d-4872-b5b0-c75d1f7526e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159932686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3159932686
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3107174800
Short name T905
Test name
Test status
Simulation time 165649547090 ps
CPU time 293.92 seconds
Started Jul 02 09:22:57 AM PDT 24
Finished Jul 02 09:27:51 AM PDT 24
Peak memory 199860 kb
Host smart-730f8d19-d2d0-423d-9642-cf9a50b29296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107174800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3107174800
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2928913993
Short name T21
Test name
Test status
Simulation time 413164931335 ps
CPU time 80.96 seconds
Started Jul 02 09:23:03 AM PDT 24
Finished Jul 02 09:24:25 AM PDT 24
Peak memory 199852 kb
Host smart-7a8f0b0e-7f64-4f92-bbd8-addf557ace4f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928913993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2928913993
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3779200164
Short name T1004
Test name
Test status
Simulation time 177463075219 ps
CPU time 342 seconds
Started Jul 02 09:22:49 AM PDT 24
Finished Jul 02 09:28:32 AM PDT 24
Peak memory 199908 kb
Host smart-8cdd04f6-8d47-4c26-8463-0d3b8089c2d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779200164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3779200164
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2534853547
Short name T846
Test name
Test status
Simulation time 10020180785 ps
CPU time 9.81 seconds
Started Jul 02 09:23:00 AM PDT 24
Finished Jul 02 09:23:11 AM PDT 24
Peak memory 199976 kb
Host smart-d60bfd9a-40e4-4dfc-84f3-743cc38504e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534853547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2534853547
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.2526634838
Short name T1053
Test name
Test status
Simulation time 7741617117 ps
CPU time 454.07 seconds
Started Jul 02 09:22:51 AM PDT 24
Finished Jul 02 09:30:25 AM PDT 24
Peak memory 199888 kb
Host smart-6aaa835d-fc6f-4e7b-a717-bde55e07413a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526634838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2526634838
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3635332471
Short name T5
Test name
Test status
Simulation time 1579120270 ps
CPU time 5.74 seconds
Started Jul 02 09:22:49 AM PDT 24
Finished Jul 02 09:22:56 AM PDT 24
Peak memory 198308 kb
Host smart-e1394163-b13b-456a-851e-98fc8b973212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3635332471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3635332471
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1372612798
Short name T615
Test name
Test status
Simulation time 81090656105 ps
CPU time 41.66 seconds
Started Jul 02 09:23:04 AM PDT 24
Finished Jul 02 09:23:47 AM PDT 24
Peak memory 199928 kb
Host smart-b2e0d93e-c7fa-4a4a-b404-1e0308d3d35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372612798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1372612798
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3466377734
Short name T512
Test name
Test status
Simulation time 3793694263 ps
CPU time 6.14 seconds
Started Jul 02 09:22:50 AM PDT 24
Finished Jul 02 09:22:57 AM PDT 24
Peak memory 196008 kb
Host smart-228bbc4a-3930-4117-9e1c-6ea96aa7df66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466377734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3466377734
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.652057329
Short name T28
Test name
Test status
Simulation time 55972361 ps
CPU time 0.91 seconds
Started Jul 02 09:22:53 AM PDT 24
Finished Jul 02 09:22:54 AM PDT 24
Peak memory 218320 kb
Host smart-1fb91ef0-4af8-41d9-b5a5-e87c658287d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652057329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.652057329
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2433297407
Short name T963
Test name
Test status
Simulation time 478469360 ps
CPU time 1.19 seconds
Started Jul 02 09:22:47 AM PDT 24
Finished Jul 02 09:22:49 AM PDT 24
Peak memory 198456 kb
Host smart-96e03acc-2aef-4e8a-8f34-8a886c755214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433297407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2433297407
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3298851300
Short name T529
Test name
Test status
Simulation time 125492222372 ps
CPU time 1158.37 seconds
Started Jul 02 09:22:49 AM PDT 24
Finished Jul 02 09:42:08 AM PDT 24
Peak memory 199912 kb
Host smart-1522ff7c-5a0d-4dc5-abf3-a2c85ca10452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298851300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3298851300
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3414924184
Short name T666
Test name
Test status
Simulation time 240349569422 ps
CPU time 471.35 seconds
Started Jul 02 09:22:49 AM PDT 24
Finished Jul 02 09:30:41 AM PDT 24
Peak memory 216540 kb
Host smart-4a6771fa-52f6-45c9-8472-c02688462151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414924184 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3414924184
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1945260392
Short name T783
Test name
Test status
Simulation time 805328798 ps
CPU time 2.49 seconds
Started Jul 02 09:23:00 AM PDT 24
Finished Jul 02 09:23:03 AM PDT 24
Peak memory 199836 kb
Host smart-78a7b696-84bd-419d-a1a4-ef41167b30fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945260392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1945260392
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_alert_test.3004310058
Short name T437
Test name
Test status
Simulation time 25401503 ps
CPU time 0.56 seconds
Started Jul 02 09:23:33 AM PDT 24
Finished Jul 02 09:23:35 AM PDT 24
Peak memory 194736 kb
Host smart-80826206-2ced-432f-8ab9-b9a059ea3d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004310058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3004310058
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.29654063
Short name T303
Test name
Test status
Simulation time 64457032979 ps
CPU time 64.73 seconds
Started Jul 02 09:23:30 AM PDT 24
Finished Jul 02 09:24:36 AM PDT 24
Peak memory 199932 kb
Host smart-c138d488-9b1f-4871-b3fe-17422453cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29654063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.29654063
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2189067749
Short name T983
Test name
Test status
Simulation time 30583971150 ps
CPU time 29.91 seconds
Started Jul 02 09:23:30 AM PDT 24
Finished Jul 02 09:24:02 AM PDT 24
Peak memory 199996 kb
Host smart-281fb829-6070-4dfd-86bf-a265cba7836f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189067749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2189067749
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2711523311
Short name T917
Test name
Test status
Simulation time 62538976654 ps
CPU time 96.24 seconds
Started Jul 02 09:23:35 AM PDT 24
Finished Jul 02 09:25:12 AM PDT 24
Peak memory 199980 kb
Host smart-b9b2b245-a99c-43a5-b7c7-7154fcd21d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711523311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2711523311
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.970251479
Short name T317
Test name
Test status
Simulation time 9111438742 ps
CPU time 9.95 seconds
Started Jul 02 09:23:36 AM PDT 24
Finished Jul 02 09:23:48 AM PDT 24
Peak memory 199992 kb
Host smart-777ef8e2-5086-4359-a7ff-7ad37a750ae1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970251479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.970251479
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3323828679
Short name T487
Test name
Test status
Simulation time 104758495081 ps
CPU time 255.24 seconds
Started Jul 02 09:23:37 AM PDT 24
Finished Jul 02 09:27:53 AM PDT 24
Peak memory 199988 kb
Host smart-b5d36fd2-d201-47d2-8560-d1cd34f6eeb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323828679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3323828679
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2053038999
Short name T1025
Test name
Test status
Simulation time 2029269584 ps
CPU time 4.62 seconds
Started Jul 02 09:23:34 AM PDT 24
Finished Jul 02 09:23:40 AM PDT 24
Peak memory 198888 kb
Host smart-e1f22caf-db1b-45d6-b945-e8d800e1da4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053038999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2053038999
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2773202404
Short name T526
Test name
Test status
Simulation time 36652396314 ps
CPU time 10.75 seconds
Started Jul 02 09:23:35 AM PDT 24
Finished Jul 02 09:23:47 AM PDT 24
Peak memory 199752 kb
Host smart-324fd2a8-37fb-4577-a4ca-5fc61e93a8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773202404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2773202404
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3839446824
Short name T516
Test name
Test status
Simulation time 9759211469 ps
CPU time 383.92 seconds
Started Jul 02 09:23:35 AM PDT 24
Finished Jul 02 09:30:00 AM PDT 24
Peak memory 199980 kb
Host smart-42c5bb60-3fd0-4c3f-96e8-f0f26932a7a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3839446824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3839446824
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.871444037
Short name T411
Test name
Test status
Simulation time 2010558729 ps
CPU time 12.74 seconds
Started Jul 02 09:23:31 AM PDT 24
Finished Jul 02 09:23:45 AM PDT 24
Peak memory 196864 kb
Host smart-009184a6-3297-4a60-9c44-50c77daeac37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871444037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.871444037
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2031579387
Short name T1022
Test name
Test status
Simulation time 62492719360 ps
CPU time 101.19 seconds
Started Jul 02 09:23:29 AM PDT 24
Finished Jul 02 09:25:12 AM PDT 24
Peak memory 199932 kb
Host smart-0545b70c-f82c-4f92-a26b-7aad7504dd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031579387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2031579387
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.239763493
Short name T877
Test name
Test status
Simulation time 49570253210 ps
CPU time 11.65 seconds
Started Jul 02 09:23:32 AM PDT 24
Finished Jul 02 09:23:45 AM PDT 24
Peak memory 195740 kb
Host smart-aa26b6b3-5600-4bb6-a705-4abc34f0aaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239763493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.239763493
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3432553040
Short name T289
Test name
Test status
Simulation time 713244421 ps
CPU time 2.68 seconds
Started Jul 02 09:23:32 AM PDT 24
Finished Jul 02 09:23:36 AM PDT 24
Peak memory 198816 kb
Host smart-64974573-62b2-4814-9358-1d69c8bf6ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432553040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3432553040
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3613934922
Short name T345
Test name
Test status
Simulation time 156236077522 ps
CPU time 104.95 seconds
Started Jul 02 09:23:34 AM PDT 24
Finished Jul 02 09:25:20 AM PDT 24
Peak memory 199920 kb
Host smart-2cb80a7d-2af2-4a32-90ea-2a427b3aec37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613934922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3613934922
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.901194417
Short name T412
Test name
Test status
Simulation time 694143986 ps
CPU time 1.23 seconds
Started Jul 02 09:23:30 AM PDT 24
Finished Jul 02 09:23:33 AM PDT 24
Peak memory 198268 kb
Host smart-790590e7-4b71-474f-8b3b-14b371006c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901194417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.901194417
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.392447448
Short name T469
Test name
Test status
Simulation time 53789603623 ps
CPU time 29.16 seconds
Started Jul 02 09:23:31 AM PDT 24
Finished Jul 02 09:24:01 AM PDT 24
Peak memory 199896 kb
Host smart-6ac8a6b4-320a-41eb-a3f1-beef60bf17b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392447448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.392447448
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1251141015
Short name T813
Test name
Test status
Simulation time 45231990902 ps
CPU time 18.11 seconds
Started Jul 02 09:26:34 AM PDT 24
Finished Jul 02 09:26:53 AM PDT 24
Peak memory 199756 kb
Host smart-0749482a-be7f-47d5-bb4d-aaaed6f45ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251141015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1251141015
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1714957795
Short name T780
Test name
Test status
Simulation time 8678223131 ps
CPU time 12.27 seconds
Started Jul 02 09:26:34 AM PDT 24
Finished Jul 02 09:26:48 AM PDT 24
Peak memory 199880 kb
Host smart-21bc50ea-5cf8-4a8b-9f01-a5ce29a94f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714957795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1714957795
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3713498876
Short name T774
Test name
Test status
Simulation time 132920014637 ps
CPU time 33.83 seconds
Started Jul 02 09:26:34 AM PDT 24
Finished Jul 02 09:27:08 AM PDT 24
Peak memory 199860 kb
Host smart-a41245ca-13eb-46b8-8397-e4b10e4aba07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713498876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3713498876
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1781304670
Short name T578
Test name
Test status
Simulation time 21299978483 ps
CPU time 24.53 seconds
Started Jul 02 09:26:35 AM PDT 24
Finished Jul 02 09:27:00 AM PDT 24
Peak memory 199968 kb
Host smart-6d7bb883-3f65-41ad-bc80-22e78df27300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781304670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1781304670
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.311973949
Short name T195
Test name
Test status
Simulation time 275135469348 ps
CPU time 103.59 seconds
Started Jul 02 09:26:34 AM PDT 24
Finished Jul 02 09:28:19 AM PDT 24
Peak memory 199896 kb
Host smart-84bc6182-04bb-4f87-87e9-662d96ad0252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311973949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.311973949
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.776685573
Short name T476
Test name
Test status
Simulation time 32640671913 ps
CPU time 26.78 seconds
Started Jul 02 09:26:35 AM PDT 24
Finished Jul 02 09:27:03 AM PDT 24
Peak memory 200004 kb
Host smart-2d3752d1-13f1-485d-bfdd-092cb65682eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776685573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.776685573
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.238534916
Short name T431
Test name
Test status
Simulation time 54205670105 ps
CPU time 16.34 seconds
Started Jul 02 09:26:32 AM PDT 24
Finished Jul 02 09:26:50 AM PDT 24
Peak memory 199992 kb
Host smart-e56830a2-2e2e-4821-aba1-9d63426dce93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238534916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.238534916
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1732462943
Short name T561
Test name
Test status
Simulation time 84069542101 ps
CPU time 126.16 seconds
Started Jul 02 09:26:35 AM PDT 24
Finished Jul 02 09:28:43 AM PDT 24
Peak memory 199952 kb
Host smart-7d8f8ef2-9756-44c3-bd57-80f582c6d541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732462943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1732462943
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.723435216
Short name T623
Test name
Test status
Simulation time 13065022 ps
CPU time 0.58 seconds
Started Jul 02 09:23:39 AM PDT 24
Finished Jul 02 09:23:41 AM PDT 24
Peak memory 195564 kb
Host smart-23000811-8308-4ec4-8427-f6ee147960d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723435216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.723435216
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3034619212
Short name T132
Test name
Test status
Simulation time 76381027127 ps
CPU time 118.68 seconds
Started Jul 02 09:23:35 AM PDT 24
Finished Jul 02 09:25:35 AM PDT 24
Peak memory 199896 kb
Host smart-345cd4b6-5041-4ebe-9772-2757c78aacb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034619212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3034619212
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1676245764
Short name T157
Test name
Test status
Simulation time 18916868370 ps
CPU time 16.09 seconds
Started Jul 02 09:23:35 AM PDT 24
Finished Jul 02 09:23:52 AM PDT 24
Peak memory 199976 kb
Host smart-f12b5afd-ddb1-45a9-851d-60b1712a230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676245764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1676245764
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.2139817579
Short name T122
Test name
Test status
Simulation time 24738514362 ps
CPU time 4.87 seconds
Started Jul 02 09:23:39 AM PDT 24
Finished Jul 02 09:23:44 AM PDT 24
Peak memory 199932 kb
Host smart-164924db-f2db-42d3-87d2-1fe40121eea5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139817579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2139817579
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1356094985
Short name T671
Test name
Test status
Simulation time 145551258038 ps
CPU time 257.16 seconds
Started Jul 02 09:23:38 AM PDT 24
Finished Jul 02 09:27:56 AM PDT 24
Peak memory 199988 kb
Host smart-a13ec79b-1293-4973-91f5-71af2f9957fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1356094985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1356094985
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.4000280923
Short name T20
Test name
Test status
Simulation time 9845013909 ps
CPU time 17.6 seconds
Started Jul 02 09:23:41 AM PDT 24
Finished Jul 02 09:24:00 AM PDT 24
Peak memory 199596 kb
Host smart-f182c45c-545c-407c-8b59-be43fe22fdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000280923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.4000280923
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.471635610
Short name T695
Test name
Test status
Simulation time 31106045618 ps
CPU time 428.01 seconds
Started Jul 02 09:23:41 AM PDT 24
Finished Jul 02 09:30:50 AM PDT 24
Peak memory 199992 kb
Host smart-70d7203f-49ac-405a-8546-8bfdfe371e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471635610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.471635610
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2925431037
Short name T639
Test name
Test status
Simulation time 3564970175 ps
CPU time 8 seconds
Started Jul 02 09:23:41 AM PDT 24
Finished Jul 02 09:23:50 AM PDT 24
Peak memory 198500 kb
Host smart-37f19536-8b27-4837-957e-b8f957744ec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925431037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2925431037
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2294426414
Short name T381
Test name
Test status
Simulation time 16575678676 ps
CPU time 8.24 seconds
Started Jul 02 09:23:39 AM PDT 24
Finished Jul 02 09:23:49 AM PDT 24
Peak memory 199708 kb
Host smart-563fd422-45c8-4865-94fd-82b886729fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294426414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2294426414
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2581936567
Short name T689
Test name
Test status
Simulation time 1623629463 ps
CPU time 1.32 seconds
Started Jul 02 09:23:42 AM PDT 24
Finished Jul 02 09:23:44 AM PDT 24
Peak memory 195592 kb
Host smart-412cd013-109c-4b3e-901f-918763b8fc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581936567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2581936567
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2009508511
Short name T821
Test name
Test status
Simulation time 915610987 ps
CPU time 1.54 seconds
Started Jul 02 09:23:37 AM PDT 24
Finished Jul 02 09:23:40 AM PDT 24
Peak memory 198376 kb
Host smart-779da2fd-318a-4ee8-9b9b-c795a6e84754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009508511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2009508511
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2684682890
Short name T860
Test name
Test status
Simulation time 93597369581 ps
CPU time 163.26 seconds
Started Jul 02 09:23:39 AM PDT 24
Finished Jul 02 09:26:23 AM PDT 24
Peak memory 199832 kb
Host smart-f13b9e05-bb9b-40b8-98bd-506ff8505007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684682890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2684682890
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.875562125
Short name T108
Test name
Test status
Simulation time 19390689937 ps
CPU time 167.32 seconds
Started Jul 02 09:23:38 AM PDT 24
Finished Jul 02 09:26:27 AM PDT 24
Peak memory 211900 kb
Host smart-c85c5669-283d-4144-b18a-ab95d407b8ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875562125 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.875562125
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3172073203
Short name T862
Test name
Test status
Simulation time 7508371215 ps
CPU time 11.67 seconds
Started Jul 02 09:23:40 AM PDT 24
Finished Jul 02 09:23:54 AM PDT 24
Peak memory 199412 kb
Host smart-5f2f9025-978f-4f42-93c1-25ceb1bcf141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172073203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3172073203
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3906362782
Short name T903
Test name
Test status
Simulation time 179813585828 ps
CPU time 46.56 seconds
Started Jul 02 09:23:34 AM PDT 24
Finished Jul 02 09:24:22 AM PDT 24
Peak memory 200012 kb
Host smart-481b9749-8485-47d4-982c-e020e2a660d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906362782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3906362782
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.825565930
Short name T797
Test name
Test status
Simulation time 98565414647 ps
CPU time 160.8 seconds
Started Jul 02 09:26:35 AM PDT 24
Finished Jul 02 09:29:17 AM PDT 24
Peak memory 199968 kb
Host smart-0048af8e-a359-4b8c-97d3-bc63e1a2c24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825565930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.825565930
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2011123128
Short name T210
Test name
Test status
Simulation time 73883268264 ps
CPU time 72.16 seconds
Started Jul 02 09:26:35 AM PDT 24
Finished Jul 02 09:27:49 AM PDT 24
Peak memory 199900 kb
Host smart-b99b793d-4728-4906-ac3f-9dda82d45122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011123128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2011123128
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.860799232
Short name T203
Test name
Test status
Simulation time 12047684780 ps
CPU time 10.63 seconds
Started Jul 02 09:26:35 AM PDT 24
Finished Jul 02 09:26:47 AM PDT 24
Peak memory 199924 kb
Host smart-628af382-502f-4c7e-ba07-6f138a13a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860799232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.860799232
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2621360379
Short name T515
Test name
Test status
Simulation time 6853184832 ps
CPU time 9.74 seconds
Started Jul 02 09:26:38 AM PDT 24
Finished Jul 02 09:26:48 AM PDT 24
Peak memory 199348 kb
Host smart-f45bdbed-6a37-4d46-a072-cc196127222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621360379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2621360379
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1550992594
Short name T676
Test name
Test status
Simulation time 111038853611 ps
CPU time 185.23 seconds
Started Jul 02 09:26:40 AM PDT 24
Finished Jul 02 09:29:45 AM PDT 24
Peak memory 199860 kb
Host smart-30904b67-8e1b-4c89-bba6-fba2b916df2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550992594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1550992594
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3940407766
Short name T162
Test name
Test status
Simulation time 113144798166 ps
CPU time 43.78 seconds
Started Jul 02 09:26:38 AM PDT 24
Finished Jul 02 09:27:22 AM PDT 24
Peak memory 199848 kb
Host smart-794dd2be-eff5-40b4-80fb-b82e8b4d4a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940407766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3940407766
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1990132512
Short name T377
Test name
Test status
Simulation time 4943916507 ps
CPU time 9.26 seconds
Started Jul 02 09:26:39 AM PDT 24
Finished Jul 02 09:26:49 AM PDT 24
Peak memory 199848 kb
Host smart-381f0761-91df-4663-a49a-ac7f94e44868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990132512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1990132512
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3709209727
Short name T232
Test name
Test status
Simulation time 173076416445 ps
CPU time 59.15 seconds
Started Jul 02 09:26:39 AM PDT 24
Finished Jul 02 09:27:38 AM PDT 24
Peak memory 199964 kb
Host smart-1194f0b4-e1ff-4b05-aa47-b50197534529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709209727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3709209727
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3225359112
Short name T447
Test name
Test status
Simulation time 79106695681 ps
CPU time 132.83 seconds
Started Jul 02 09:26:39 AM PDT 24
Finished Jul 02 09:28:53 AM PDT 24
Peak memory 199888 kb
Host smart-eb424eae-e644-49f3-b0c1-787e0e5b8ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225359112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3225359112
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.838541108
Short name T376
Test name
Test status
Simulation time 30598929 ps
CPU time 0.57 seconds
Started Jul 02 09:23:43 AM PDT 24
Finished Jul 02 09:23:46 AM PDT 24
Peak memory 195224 kb
Host smart-bb7ef219-dd14-46e1-9e31-b67bbffe3239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838541108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.838541108
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3670987430
Short name T868
Test name
Test status
Simulation time 272741964040 ps
CPU time 277.35 seconds
Started Jul 02 09:23:43 AM PDT 24
Finished Jul 02 09:28:22 AM PDT 24
Peak memory 199912 kb
Host smart-2e6ced8a-a453-45c0-8411-5db738b9bcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670987430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3670987430
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.175959548
Short name T266
Test name
Test status
Simulation time 119347503070 ps
CPU time 58.23 seconds
Started Jul 02 09:23:44 AM PDT 24
Finished Jul 02 09:24:45 AM PDT 24
Peak memory 199972 kb
Host smart-5f7bc384-32a8-4d8a-aee5-dcd1721e894b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175959548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.175959548
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3774939391
Short name T220
Test name
Test status
Simulation time 13366631312 ps
CPU time 19.82 seconds
Started Jul 02 09:23:43 AM PDT 24
Finished Jul 02 09:24:04 AM PDT 24
Peak memory 199844 kb
Host smart-228ad21e-237c-4c72-a9fc-6a78334d2c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774939391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3774939391
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2253453626
Short name T277
Test name
Test status
Simulation time 137421766787 ps
CPU time 710.68 seconds
Started Jul 02 09:23:43 AM PDT 24
Finished Jul 02 09:35:36 AM PDT 24
Peak memory 199952 kb
Host smart-641e4810-6d0a-44ca-bf1a-20ffa4a89c52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253453626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2253453626
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2681567235
Short name T357
Test name
Test status
Simulation time 518714853 ps
CPU time 1.02 seconds
Started Jul 02 09:23:44 AM PDT 24
Finished Jul 02 09:23:47 AM PDT 24
Peak memory 195620 kb
Host smart-a8736ca6-3593-46fb-b789-b40917c3e27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681567235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2681567235
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.1342271610
Short name T710
Test name
Test status
Simulation time 5889725681 ps
CPU time 82.57 seconds
Started Jul 02 09:23:42 AM PDT 24
Finished Jul 02 09:25:05 AM PDT 24
Peak memory 199944 kb
Host smart-47fdab6b-4250-497f-bbed-8c0d9e901e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342271610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1342271610
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.789860105
Short name T372
Test name
Test status
Simulation time 1275485520 ps
CPU time 1.58 seconds
Started Jul 02 09:23:43 AM PDT 24
Finished Jul 02 09:23:46 AM PDT 24
Peak memory 196736 kb
Host smart-18458d83-c6d0-4ca7-888a-c07d3208864d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789860105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.789860105
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.4256245413
Short name T460
Test name
Test status
Simulation time 27954408225 ps
CPU time 18.44 seconds
Started Jul 02 09:23:45 AM PDT 24
Finished Jul 02 09:24:05 AM PDT 24
Peak memory 199940 kb
Host smart-e11ab46c-cf77-4df8-b3eb-954972c89d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256245413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.4256245413
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1580160431
Short name T901
Test name
Test status
Simulation time 45542025516 ps
CPU time 18.28 seconds
Started Jul 02 09:23:43 AM PDT 24
Finished Jul 02 09:24:03 AM PDT 24
Peak memory 195792 kb
Host smart-07aba62f-0849-46b9-acc8-85fe3e29664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580160431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1580160431
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1419124933
Short name T1026
Test name
Test status
Simulation time 731795600 ps
CPU time 1.3 seconds
Started Jul 02 09:23:39 AM PDT 24
Finished Jul 02 09:23:41 AM PDT 24
Peak memory 198684 kb
Host smart-b11ffd7e-4a2e-42f2-91d2-ae7e1c68f7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419124933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1419124933
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2337174320
Short name T283
Test name
Test status
Simulation time 992128270 ps
CPU time 2.97 seconds
Started Jul 02 09:23:43 AM PDT 24
Finished Jul 02 09:23:47 AM PDT 24
Peak memory 198564 kb
Host smart-4b58fafd-1ebb-4479-9166-09f0d1e4da65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337174320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2337174320
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.208312196
Short name T273
Test name
Test status
Simulation time 108788539779 ps
CPU time 77.22 seconds
Started Jul 02 09:23:42 AM PDT 24
Finished Jul 02 09:25:00 AM PDT 24
Peak memory 199952 kb
Host smart-384259b0-421e-4ff3-874b-731f8f0ae250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208312196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.208312196
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2356857204
Short name T849
Test name
Test status
Simulation time 135937599391 ps
CPU time 406.53 seconds
Started Jul 02 09:26:38 AM PDT 24
Finished Jul 02 09:33:25 AM PDT 24
Peak memory 199996 kb
Host smart-989395e8-af88-4dd6-9bb2-29d980899245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356857204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2356857204
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1827984314
Short name T201
Test name
Test status
Simulation time 14626338489 ps
CPU time 29.76 seconds
Started Jul 02 09:26:39 AM PDT 24
Finished Jul 02 09:27:09 AM PDT 24
Peak memory 199908 kb
Host smart-a2485af0-4c0f-4e01-98bb-c28e15f7edc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827984314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1827984314
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1414090533
Short name T370
Test name
Test status
Simulation time 10359822099 ps
CPU time 14.87 seconds
Started Jul 02 09:26:38 AM PDT 24
Finished Jul 02 09:26:53 AM PDT 24
Peak memory 199916 kb
Host smart-00d2f73d-d5d4-4051-9436-a32d3df03100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414090533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1414090533
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2965079871
Short name T919
Test name
Test status
Simulation time 65077404924 ps
CPU time 108.04 seconds
Started Jul 02 09:26:39 AM PDT 24
Finished Jul 02 09:28:27 AM PDT 24
Peak memory 199964 kb
Host smart-abb432a3-df97-415a-a3d0-a3699cd35037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965079871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2965079871
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3524417742
Short name T163
Test name
Test status
Simulation time 145236136433 ps
CPU time 319.14 seconds
Started Jul 02 09:26:36 AM PDT 24
Finished Jul 02 09:31:56 AM PDT 24
Peak memory 199924 kb
Host smart-3469af72-a03d-481d-b9a8-119ca460eb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524417742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3524417742
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2213555269
Short name T829
Test name
Test status
Simulation time 67778522259 ps
CPU time 343.27 seconds
Started Jul 02 09:26:42 AM PDT 24
Finished Jul 02 09:32:26 AM PDT 24
Peak memory 199992 kb
Host smart-8862b3a3-30fa-4646-a83b-c80b55ee5040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213555269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2213555269
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2975934159
Short name T348
Test name
Test status
Simulation time 26625800286 ps
CPU time 41.16 seconds
Started Jul 02 09:26:44 AM PDT 24
Finished Jul 02 09:27:25 AM PDT 24
Peak memory 199892 kb
Host smart-bbd03486-445e-4e44-bebe-7964dcb4782a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975934159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2975934159
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1580614676
Short name T366
Test name
Test status
Simulation time 41614982256 ps
CPU time 65.51 seconds
Started Jul 02 09:26:47 AM PDT 24
Finished Jul 02 09:27:53 AM PDT 24
Peak memory 199904 kb
Host smart-aeae2001-6379-403b-9e55-ac169c885267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580614676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1580614676
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.813465580
Short name T352
Test name
Test status
Simulation time 27256435755 ps
CPU time 5.25 seconds
Started Jul 02 09:26:47 AM PDT 24
Finished Jul 02 09:26:53 AM PDT 24
Peak memory 199988 kb
Host smart-cb1104e4-86ef-44f3-a8ec-53d7797212bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813465580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.813465580
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3274754788
Short name T682
Test name
Test status
Simulation time 15575953 ps
CPU time 0.56 seconds
Started Jul 02 09:23:50 AM PDT 24
Finished Jul 02 09:23:52 AM PDT 24
Peak memory 195600 kb
Host smart-3856039c-dad1-41d7-93db-b933819448b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274754788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3274754788
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1389039819
Short name T645
Test name
Test status
Simulation time 32058826169 ps
CPU time 54.31 seconds
Started Jul 02 09:23:44 AM PDT 24
Finished Jul 02 09:24:40 AM PDT 24
Peak memory 199972 kb
Host smart-03a92c3e-e823-4828-a051-e3f79400ed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389039819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1389039819
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4287982036
Short name T964
Test name
Test status
Simulation time 73483432316 ps
CPU time 30.29 seconds
Started Jul 02 09:23:46 AM PDT 24
Finished Jul 02 09:24:18 AM PDT 24
Peak memory 199924 kb
Host smart-2c476eb6-514c-43cf-afd8-6f9b5b41b556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287982036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4287982036
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.757566586
Short name T298
Test name
Test status
Simulation time 14216463780 ps
CPU time 22.11 seconds
Started Jul 02 09:23:46 AM PDT 24
Finished Jul 02 09:24:10 AM PDT 24
Peak memory 199692 kb
Host smart-88479c38-0f33-4d0c-809e-2aaaac6df60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757566586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.757566586
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2167936189
Short name T480
Test name
Test status
Simulation time 358075709186 ps
CPU time 124.59 seconds
Started Jul 02 09:23:50 AM PDT 24
Finished Jul 02 09:25:55 AM PDT 24
Peak memory 199944 kb
Host smart-a1bf6958-585c-4378-ae35-4bd9b198a349
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167936189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2167936189
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1168830948
Short name T913
Test name
Test status
Simulation time 140344971047 ps
CPU time 290.38 seconds
Started Jul 02 09:23:51 AM PDT 24
Finished Jul 02 09:28:43 AM PDT 24
Peak memory 199952 kb
Host smart-4df826b8-4835-45f2-b1ba-c34f38d2909f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168830948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1168830948
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2552506814
Short name T711
Test name
Test status
Simulation time 257686328 ps
CPU time 0.91 seconds
Started Jul 02 09:23:48 AM PDT 24
Finished Jul 02 09:23:50 AM PDT 24
Peak memory 197028 kb
Host smart-a9f8f512-17f5-4b4e-857a-2f889ff6c78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552506814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2552506814
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.4281481032
Short name T972
Test name
Test status
Simulation time 4076207325 ps
CPU time 210.73 seconds
Started Jul 02 09:23:47 AM PDT 24
Finished Jul 02 09:27:20 AM PDT 24
Peak memory 199960 kb
Host smart-7287e261-3dc5-47ef-8c4f-7c2b0e0d6a26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4281481032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4281481032
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1906358391
Short name T511
Test name
Test status
Simulation time 2556857010 ps
CPU time 18.67 seconds
Started Jul 02 09:23:49 AM PDT 24
Finished Jul 02 09:24:09 AM PDT 24
Peak memory 199076 kb
Host smart-6ddc2546-e9c6-47b8-906f-6706749c6f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1906358391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1906358391
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.473493353
Short name T458
Test name
Test status
Simulation time 150644551180 ps
CPU time 74.66 seconds
Started Jul 02 09:23:47 AM PDT 24
Finished Jul 02 09:25:03 AM PDT 24
Peak memory 199944 kb
Host smart-69e40bc2-76f7-41cf-b3db-72df60a6ec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473493353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.473493353
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2044636606
Short name T307
Test name
Test status
Simulation time 44457292419 ps
CPU time 18.95 seconds
Started Jul 02 09:23:48 AM PDT 24
Finished Jul 02 09:24:08 AM PDT 24
Peak memory 196212 kb
Host smart-5518f6ca-6877-4fa7-bddf-1f874acdc5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044636606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2044636606
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.365499716
Short name T536
Test name
Test status
Simulation time 281311273 ps
CPU time 1.1 seconds
Started Jul 02 09:23:43 AM PDT 24
Finished Jul 02 09:23:45 AM PDT 24
Peak memory 198844 kb
Host smart-cf212406-2234-4c75-a4fa-312e2a599e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365499716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.365499716
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3201203037
Short name T281
Test name
Test status
Simulation time 1588720903 ps
CPU time 1.55 seconds
Started Jul 02 09:23:49 AM PDT 24
Finished Jul 02 09:23:52 AM PDT 24
Peak memory 198288 kb
Host smart-375fc128-54c5-4755-bfd2-4d8ae5443a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201203037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3201203037
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.4244036539
Short name T722
Test name
Test status
Simulation time 105932480629 ps
CPU time 39.41 seconds
Started Jul 02 09:23:42 AM PDT 24
Finished Jul 02 09:24:23 AM PDT 24
Peak memory 200008 kb
Host smart-eed33cd4-f200-4223-9702-0906c964d856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244036539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.4244036539
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2418338135
Short name T407
Test name
Test status
Simulation time 87540792878 ps
CPU time 167.32 seconds
Started Jul 02 09:26:47 AM PDT 24
Finished Jul 02 09:29:35 AM PDT 24
Peak memory 199992 kb
Host smart-07a2b07a-20e4-4aef-8d85-7de2603a776a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418338135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2418338135
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1980763117
Short name T672
Test name
Test status
Simulation time 156285372441 ps
CPU time 14.09 seconds
Started Jul 02 09:26:46 AM PDT 24
Finished Jul 02 09:27:00 AM PDT 24
Peak memory 199664 kb
Host smart-c1c49c71-d771-433e-bdd1-0c1826a28cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980763117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1980763117
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3875276398
Short name T754
Test name
Test status
Simulation time 33327128204 ps
CPU time 16.35 seconds
Started Jul 02 09:26:43 AM PDT 24
Finished Jul 02 09:26:59 AM PDT 24
Peak memory 199860 kb
Host smart-1370421b-32a9-4055-a1bd-db024d4713e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875276398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3875276398
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2639462131
Short name T560
Test name
Test status
Simulation time 25605237729 ps
CPU time 43.56 seconds
Started Jul 02 09:26:42 AM PDT 24
Finished Jul 02 09:27:26 AM PDT 24
Peak memory 199960 kb
Host smart-b6f4e2c2-70ee-4b22-8e34-b47033fab390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639462131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2639462131
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.418964468
Short name T534
Test name
Test status
Simulation time 6716528044 ps
CPU time 9.36 seconds
Started Jul 02 09:26:43 AM PDT 24
Finished Jul 02 09:26:53 AM PDT 24
Peak memory 199980 kb
Host smart-16aae6a5-9ac6-45e1-a800-7a3badf475be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418964468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.418964468
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.4013158182
Short name T293
Test name
Test status
Simulation time 86993989229 ps
CPU time 18.64 seconds
Started Jul 02 09:26:42 AM PDT 24
Finished Jul 02 09:27:01 AM PDT 24
Peak memory 199916 kb
Host smart-c8277eed-e38b-495b-bc83-5505db5ff027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013158182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.4013158182
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.860793629
Short name T587
Test name
Test status
Simulation time 133111836379 ps
CPU time 208.61 seconds
Started Jul 02 09:26:45 AM PDT 24
Finished Jul 02 09:30:14 AM PDT 24
Peak memory 199928 kb
Host smart-f97e6009-7966-446b-8a9f-f0403bdd31f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860793629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.860793629
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.4084382347
Short name T948
Test name
Test status
Simulation time 71314801038 ps
CPU time 63.49 seconds
Started Jul 02 09:26:44 AM PDT 24
Finished Jul 02 09:27:48 AM PDT 24
Peak memory 199908 kb
Host smart-9ae8538a-01ca-44b6-ab60-664711c4d4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084382347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.4084382347
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1725034864
Short name T810
Test name
Test status
Simulation time 53372274715 ps
CPU time 13.58 seconds
Started Jul 02 09:26:46 AM PDT 24
Finished Jul 02 09:27:00 AM PDT 24
Peak memory 199916 kb
Host smart-1b9baec3-297a-429a-97b4-dd006c45f19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725034864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1725034864
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1667185625
Short name T103
Test name
Test status
Simulation time 194215733351 ps
CPU time 74.12 seconds
Started Jul 02 09:26:45 AM PDT 24
Finished Jul 02 09:28:00 AM PDT 24
Peak memory 199688 kb
Host smart-f1f36196-5032-48fc-aa1c-976ec8b6fd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667185625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1667185625
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.443622151
Short name T517
Test name
Test status
Simulation time 18907777 ps
CPU time 0.57 seconds
Started Jul 02 09:23:57 AM PDT 24
Finished Jul 02 09:23:58 AM PDT 24
Peak memory 194768 kb
Host smart-a0b5c38c-2587-4037-8138-b42e79da9614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443622151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.443622151
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.43135107
Short name T1071
Test name
Test status
Simulation time 33965210054 ps
CPU time 12.24 seconds
Started Jul 02 09:24:02 AM PDT 24
Finished Jul 02 09:24:16 AM PDT 24
Peak memory 199912 kb
Host smart-3120ca8f-6bfb-45f1-bf48-a61b079b90d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43135107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.43135107
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2530551150
Short name T1052
Test name
Test status
Simulation time 141426663574 ps
CPU time 121.73 seconds
Started Jul 02 09:23:55 AM PDT 24
Finished Jul 02 09:25:58 AM PDT 24
Peak memory 199952 kb
Host smart-4bde18a1-598d-41a6-a574-d8db9860283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530551150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2530551150
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.992467802
Short name T173
Test name
Test status
Simulation time 144116607208 ps
CPU time 239.8 seconds
Started Jul 02 09:23:52 AM PDT 24
Finished Jul 02 09:27:53 AM PDT 24
Peak memory 200204 kb
Host smart-8d0587c8-3af4-43dd-a968-94625504c4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992467802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.992467802
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1700768916
Short name T858
Test name
Test status
Simulation time 273598507742 ps
CPU time 263.44 seconds
Started Jul 02 09:23:57 AM PDT 24
Finished Jul 02 09:28:21 AM PDT 24
Peak memory 199912 kb
Host smart-47d82134-6722-4f26-9bc3-730470a0a2f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1700768916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1700768916
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2021283921
Short name T359
Test name
Test status
Simulation time 11372856717 ps
CPU time 9.04 seconds
Started Jul 02 09:23:53 AM PDT 24
Finished Jul 02 09:24:03 AM PDT 24
Peak memory 199844 kb
Host smart-d5b9fded-ac80-461b-b4b7-598d39e66c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021283921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2021283921
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.2718788578
Short name T690
Test name
Test status
Simulation time 15392188473 ps
CPU time 750.61 seconds
Started Jul 02 09:23:56 AM PDT 24
Finished Jul 02 09:36:28 AM PDT 24
Peak memory 199888 kb
Host smart-472e8a96-7f15-4ab1-831e-1b895e6d3350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2718788578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2718788578
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1208973873
Short name T466
Test name
Test status
Simulation time 7168038824 ps
CPU time 15.3 seconds
Started Jul 02 09:23:50 AM PDT 24
Finished Jul 02 09:24:06 AM PDT 24
Peak memory 198832 kb
Host smart-1800095b-889c-4fe6-924a-31f2165dc041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208973873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1208973873
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3840106962
Short name T474
Test name
Test status
Simulation time 25929809077 ps
CPU time 46.81 seconds
Started Jul 02 09:23:53 AM PDT 24
Finished Jul 02 09:24:41 AM PDT 24
Peak memory 199976 kb
Host smart-baba5fb5-9ce3-48ca-9cb6-85fd77211bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840106962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3840106962
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1631715608
Short name T433
Test name
Test status
Simulation time 2805277187 ps
CPU time 4.45 seconds
Started Jul 02 09:23:52 AM PDT 24
Finished Jul 02 09:23:58 AM PDT 24
Peak memory 196412 kb
Host smart-5a871c7d-5d22-4a87-aca5-5e05966f6f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631715608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1631715608
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2659416669
Short name T332
Test name
Test status
Simulation time 462561471 ps
CPU time 1.98 seconds
Started Jul 02 09:23:52 AM PDT 24
Finished Jul 02 09:23:55 AM PDT 24
Peak memory 199044 kb
Host smart-5cb436bb-8a6b-4c37-bc36-d2e86e0cb708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659416669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2659416669
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.693915477
Short name T189
Test name
Test status
Simulation time 237284725737 ps
CPU time 151.24 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:26:34 AM PDT 24
Peak memory 199892 kb
Host smart-2164b988-3590-4a6e-928d-82abc6518d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693915477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.693915477
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2350131171
Short name T616
Test name
Test status
Simulation time 183305944324 ps
CPU time 707.04 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:35:50 AM PDT 24
Peak memory 216484 kb
Host smart-5e59d0a6-322c-4c12-86da-7bbe0d135a3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350131171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2350131171
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.145190945
Short name T1021
Test name
Test status
Simulation time 494547267 ps
CPU time 1.61 seconds
Started Jul 02 09:23:54 AM PDT 24
Finished Jul 02 09:23:56 AM PDT 24
Peak memory 198992 kb
Host smart-85a94236-305c-4d1b-88c6-2b0b040adc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145190945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.145190945
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2794147837
Short name T311
Test name
Test status
Simulation time 80726211488 ps
CPU time 57.74 seconds
Started Jul 02 09:23:51 AM PDT 24
Finished Jul 02 09:24:50 AM PDT 24
Peak memory 200016 kb
Host smart-d4396ca3-7939-4844-9696-43a01ab671a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794147837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2794147837
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.196157301
Short name T1000
Test name
Test status
Simulation time 71185077166 ps
CPU time 78.6 seconds
Started Jul 02 09:26:45 AM PDT 24
Finished Jul 02 09:28:05 AM PDT 24
Peak memory 200204 kb
Host smart-2334826b-1608-4fd8-af65-ef0181ff3492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196157301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.196157301
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.167159534
Short name T949
Test name
Test status
Simulation time 254268025067 ps
CPU time 106.11 seconds
Started Jul 02 09:26:49 AM PDT 24
Finished Jul 02 09:28:35 AM PDT 24
Peak memory 199968 kb
Host smart-829ffe1f-9a76-4fcb-9352-894d0dd0ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167159534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.167159534
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.773328636
Short name T349
Test name
Test status
Simulation time 70802468379 ps
CPU time 24.15 seconds
Started Jul 02 09:26:46 AM PDT 24
Finished Jul 02 09:27:11 AM PDT 24
Peak memory 199136 kb
Host smart-606dfbde-2823-4b8a-8511-d8179c27c3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773328636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.773328636
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1457197166
Short name T116
Test name
Test status
Simulation time 30335861865 ps
CPU time 63.18 seconds
Started Jul 02 09:26:46 AM PDT 24
Finished Jul 02 09:27:50 AM PDT 24
Peak memory 199916 kb
Host smart-eca3a638-e229-4e0e-a506-410ffff36741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457197166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1457197166
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.4214442367
Short name T911
Test name
Test status
Simulation time 7771841913 ps
CPU time 6.8 seconds
Started Jul 02 09:26:52 AM PDT 24
Finished Jul 02 09:26:59 AM PDT 24
Peak memory 199956 kb
Host smart-1110af88-65e3-4c6b-a7d9-e57ff6218587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214442367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4214442367
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2730218960
Short name T156
Test name
Test status
Simulation time 65893127689 ps
CPU time 117.97 seconds
Started Jul 02 09:26:58 AM PDT 24
Finished Jul 02 09:28:57 AM PDT 24
Peak memory 199896 kb
Host smart-b252884c-d2d8-48c5-9e7c-cdd389fad9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730218960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2730218960
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.4008697910
Short name T649
Test name
Test status
Simulation time 16304497345 ps
CPU time 8.59 seconds
Started Jul 02 09:26:59 AM PDT 24
Finished Jul 02 09:27:08 AM PDT 24
Peak memory 199896 kb
Host smart-316672fe-773f-417e-a1b9-ce2ec8351d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008697910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.4008697910
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2640674781
Short name T806
Test name
Test status
Simulation time 159686510734 ps
CPU time 68.05 seconds
Started Jul 02 09:26:49 AM PDT 24
Finished Jul 02 09:27:58 AM PDT 24
Peak memory 199912 kb
Host smart-779d6895-3d1b-4207-a335-c2a5380d0d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640674781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2640674781
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2780211011
Short name T920
Test name
Test status
Simulation time 12784795617 ps
CPU time 11.46 seconds
Started Jul 02 09:26:56 AM PDT 24
Finished Jul 02 09:27:08 AM PDT 24
Peak memory 199916 kb
Host smart-9d05c971-9eb8-4bfb-89e1-08446cc43d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780211011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2780211011
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1521191373
Short name T1066
Test name
Test status
Simulation time 34552443 ps
CPU time 0.55 seconds
Started Jul 02 09:23:57 AM PDT 24
Finished Jul 02 09:23:58 AM PDT 24
Peak memory 195280 kb
Host smart-aef6be9a-90c0-4d39-a773-dd6fd7738327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521191373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1521191373
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.87077360
Short name T441
Test name
Test status
Simulation time 98362582723 ps
CPU time 18.77 seconds
Started Jul 02 09:23:55 AM PDT 24
Finished Jul 02 09:24:15 AM PDT 24
Peak memory 199876 kb
Host smart-93776520-50ce-404f-8927-a6a020fc044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87077360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.87077360
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.262191186
Short name T632
Test name
Test status
Simulation time 22838438009 ps
CPU time 18.61 seconds
Started Jul 02 09:23:55 AM PDT 24
Finished Jul 02 09:24:15 AM PDT 24
Peak memory 199728 kb
Host smart-8dbf3a9f-d20a-4ee4-8b28-056f04bba45b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262191186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.262191186
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.97099967
Short name T481
Test name
Test status
Simulation time 241796152759 ps
CPU time 331.94 seconds
Started Jul 02 09:23:55 AM PDT 24
Finished Jul 02 09:29:28 AM PDT 24
Peak memory 199952 kb
Host smart-e53af7b9-7b70-4eda-aebc-3ee48ce5427a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97099967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.97099967
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2494096127
Short name T776
Test name
Test status
Simulation time 10448868147 ps
CPU time 6.42 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:24:10 AM PDT 24
Peak memory 199216 kb
Host smart-cf62f1d2-3ecd-4335-a2c2-57d6bc680c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494096127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2494096127
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.3386496032
Short name T668
Test name
Test status
Simulation time 7524622564 ps
CPU time 73.67 seconds
Started Jul 02 09:23:55 AM PDT 24
Finished Jul 02 09:25:09 AM PDT 24
Peak memory 199944 kb
Host smart-1fa8fce0-2c1f-4330-8efd-10fe034e40bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386496032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3386496032
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2531970964
Short name T981
Test name
Test status
Simulation time 6775493957 ps
CPU time 62.95 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:25:06 AM PDT 24
Peak memory 198364 kb
Host smart-47e6d590-1f43-4e73-9477-6d67a21d9ef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531970964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2531970964
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3343891568
Short name T304
Test name
Test status
Simulation time 71555677018 ps
CPU time 28.73 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:24:32 AM PDT 24
Peak memory 199612 kb
Host smart-90fd1e2f-4092-41c7-ad27-c0830f311ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343891568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3343891568
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.4012918911
Short name T589
Test name
Test status
Simulation time 42248835687 ps
CPU time 62.34 seconds
Started Jul 02 09:23:56 AM PDT 24
Finished Jul 02 09:25:00 AM PDT 24
Peak memory 196380 kb
Host smart-4d4dbe2f-acd0-4370-8013-ae9539b60716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012918911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4012918911
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.550313090
Short name T438
Test name
Test status
Simulation time 5367475777 ps
CPU time 6.46 seconds
Started Jul 02 09:23:59 AM PDT 24
Finished Jul 02 09:24:07 AM PDT 24
Peak memory 199968 kb
Host smart-e26ed672-37dd-42a9-b0c5-c161e115292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550313090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.550313090
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2741020974
Short name T1046
Test name
Test status
Simulation time 74757676091 ps
CPU time 127 seconds
Started Jul 02 09:23:55 AM PDT 24
Finished Jul 02 09:26:04 AM PDT 24
Peak memory 199892 kb
Host smart-2950711c-e8f8-4a3b-8c34-8a5d895949f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741020974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2741020974
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1077165936
Short name T883
Test name
Test status
Simulation time 60027994410 ps
CPU time 554.96 seconds
Started Jul 02 09:24:00 AM PDT 24
Finished Jul 02 09:33:16 AM PDT 24
Peak memory 216428 kb
Host smart-38bdc7de-59e7-4705-a948-b71c9ee3ed67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077165936 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1077165936
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.480376317
Short name T101
Test name
Test status
Simulation time 1056518325 ps
CPU time 4.45 seconds
Started Jul 02 09:23:55 AM PDT 24
Finished Jul 02 09:24:01 AM PDT 24
Peak memory 198896 kb
Host smart-c77a54e7-da46-4bcb-a56b-37fff96ac2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480376317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.480376317
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2580922728
Short name T979
Test name
Test status
Simulation time 110843689434 ps
CPU time 137.37 seconds
Started Jul 02 09:24:00 AM PDT 24
Finished Jul 02 09:26:19 AM PDT 24
Peak memory 199972 kb
Host smart-cebb76fa-e50a-4c1e-b58c-4e0cbabb2b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580922728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2580922728
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.20258769
Short name T719
Test name
Test status
Simulation time 35300020417 ps
CPU time 56.75 seconds
Started Jul 02 09:26:50 AM PDT 24
Finished Jul 02 09:27:47 AM PDT 24
Peak memory 199956 kb
Host smart-55b0dc2c-5bc6-48be-bdbe-87bb7009172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20258769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.20258769
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3097064782
Short name T865
Test name
Test status
Simulation time 10226539706 ps
CPU time 14.11 seconds
Started Jul 02 09:26:49 AM PDT 24
Finished Jul 02 09:27:04 AM PDT 24
Peak memory 199988 kb
Host smart-940f3149-03a8-4777-8981-1cb52e0f4a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097064782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3097064782
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3753860688
Short name T248
Test name
Test status
Simulation time 134634364844 ps
CPU time 59.2 seconds
Started Jul 02 09:26:54 AM PDT 24
Finished Jul 02 09:27:53 AM PDT 24
Peak memory 199916 kb
Host smart-a6dd9050-2745-4846-80a8-ca88ce5ceb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753860688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3753860688
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1628713086
Short name T402
Test name
Test status
Simulation time 204267493413 ps
CPU time 89.03 seconds
Started Jul 02 09:26:54 AM PDT 24
Finished Jul 02 09:28:24 AM PDT 24
Peak memory 199976 kb
Host smart-e467b226-05aa-41ab-a043-e5c1e3c1f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628713086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1628713086
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2732174141
Short name T172
Test name
Test status
Simulation time 13435174319 ps
CPU time 23.46 seconds
Started Jul 02 09:26:57 AM PDT 24
Finished Jul 02 09:27:21 AM PDT 24
Peak memory 199896 kb
Host smart-a018877c-2b95-4df2-b7fc-b0991197f89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732174141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2732174141
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1090166185
Short name T200
Test name
Test status
Simulation time 101966078927 ps
CPU time 89.26 seconds
Started Jul 02 09:26:54 AM PDT 24
Finished Jul 02 09:28:24 AM PDT 24
Peak memory 199924 kb
Host smart-bad3a0b8-5d83-4e6c-ba92-ebc3fb2cf131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090166185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1090166185
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2115273138
Short name T10
Test name
Test status
Simulation time 78962657762 ps
CPU time 24.21 seconds
Started Jul 02 09:26:55 AM PDT 24
Finished Jul 02 09:27:20 AM PDT 24
Peak memory 199900 kb
Host smart-cf827816-7a98-499a-8411-00b2a60c5eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115273138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2115273138
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1647054317
Short name T826
Test name
Test status
Simulation time 95295226195 ps
CPU time 13.21 seconds
Started Jul 02 09:26:55 AM PDT 24
Finished Jul 02 09:27:09 AM PDT 24
Peak memory 198964 kb
Host smart-25cb7253-4a38-4130-b9b3-d141483b4125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647054317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1647054317
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.35198929
Short name T753
Test name
Test status
Simulation time 18556199 ps
CPU time 0.64 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:24:03 AM PDT 24
Peak memory 195260 kb
Host smart-080d3ae0-c030-4300-b83b-42fb27785f41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35198929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.35198929
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.216895424
Short name T286
Test name
Test status
Simulation time 37478524720 ps
CPU time 17.82 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:24:21 AM PDT 24
Peak memory 199968 kb
Host smart-60d3bca7-5aa5-4c79-88d0-dc927b759aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216895424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.216895424
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1044916070
Short name T166
Test name
Test status
Simulation time 187941698880 ps
CPU time 155.46 seconds
Started Jul 02 09:23:56 AM PDT 24
Finished Jul 02 09:26:33 AM PDT 24
Peak memory 199884 kb
Host smart-e307c874-9a73-4cdb-9e70-7f1a786d0aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044916070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1044916070
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3536794597
Short name T574
Test name
Test status
Simulation time 16442903055 ps
CPU time 34.51 seconds
Started Jul 02 09:23:56 AM PDT 24
Finished Jul 02 09:24:32 AM PDT 24
Peak memory 199928 kb
Host smart-74819156-ac86-4a56-bfbb-a47f6d87ecd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536794597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3536794597
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3222846650
Short name T657
Test name
Test status
Simulation time 33215476396 ps
CPU time 46.82 seconds
Started Jul 02 09:23:58 AM PDT 24
Finished Jul 02 09:24:46 AM PDT 24
Peak memory 199740 kb
Host smart-df0865c6-fce2-412a-ae94-370610219a14
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222846650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3222846650
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1261614109
Short name T540
Test name
Test status
Simulation time 51550178420 ps
CPU time 114.54 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:25:57 AM PDT 24
Peak memory 199968 kb
Host smart-2e200507-36e1-400f-9fc0-3d34602bbfbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1261614109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1261614109
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.4001204043
Short name T982
Test name
Test status
Simulation time 6016305848 ps
CPU time 3.84 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:24:07 AM PDT 24
Peak memory 197672 kb
Host smart-9156b883-9f78-44fe-a416-81a77d06a74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001204043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4001204043
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.2835551807
Short name T450
Test name
Test status
Simulation time 15441692499 ps
CPU time 209.67 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:27:33 AM PDT 24
Peak memory 199996 kb
Host smart-f9278279-b37a-4c29-a62e-02bb773f2dfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835551807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2835551807
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.267632119
Short name T843
Test name
Test status
Simulation time 5192334835 ps
CPU time 26.33 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:24:29 AM PDT 24
Peak memory 199364 kb
Host smart-711c2951-c22a-4c94-bff0-889f467a7ce2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267632119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.267632119
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3989164428
Short name T942
Test name
Test status
Simulation time 31163853918 ps
CPU time 19.72 seconds
Started Jul 02 09:24:02 AM PDT 24
Finished Jul 02 09:24:23 AM PDT 24
Peak memory 199956 kb
Host smart-42f1972e-7355-4357-bd48-81672bbd105c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989164428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3989164428
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3192236027
Short name T592
Test name
Test status
Simulation time 40621954101 ps
CPU time 8.93 seconds
Started Jul 02 09:23:59 AM PDT 24
Finished Jul 02 09:24:09 AM PDT 24
Peak memory 195928 kb
Host smart-f85764eb-ba74-4436-8df3-caf8b7c6908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192236027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3192236027
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1449735055
Short name T328
Test name
Test status
Simulation time 298985559 ps
CPU time 1.26 seconds
Started Jul 02 09:23:57 AM PDT 24
Finished Jul 02 09:23:59 AM PDT 24
Peak memory 198720 kb
Host smart-4027dd6c-3bf3-456b-9b4e-0e21c44e5fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449735055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1449735055
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2322195262
Short name T1014
Test name
Test status
Simulation time 7152687525 ps
CPU time 21.08 seconds
Started Jul 02 09:24:00 AM PDT 24
Finished Jul 02 09:24:22 AM PDT 24
Peak memory 199560 kb
Host smart-af9000bc-419c-49eb-8fca-7acf26c7cfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322195262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2322195262
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2491095060
Short name T692
Test name
Test status
Simulation time 9099940077 ps
CPU time 11.96 seconds
Started Jul 02 09:23:54 AM PDT 24
Finished Jul 02 09:24:08 AM PDT 24
Peak memory 197948 kb
Host smart-2566acae-cecd-447c-9cdc-82d15361fc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491095060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2491095060
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2800630763
Short name T787
Test name
Test status
Simulation time 113913547180 ps
CPU time 158.36 seconds
Started Jul 02 09:26:57 AM PDT 24
Finished Jul 02 09:29:35 AM PDT 24
Peak memory 199956 kb
Host smart-12cd8596-4cc1-4624-b967-de41edeb7668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800630763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2800630763
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3306358476
Short name T960
Test name
Test status
Simulation time 214869337510 ps
CPU time 114.39 seconds
Started Jul 02 09:26:59 AM PDT 24
Finished Jul 02 09:28:54 AM PDT 24
Peak memory 200032 kb
Host smart-48f400c5-97ba-430a-bfd4-f7d1726ecaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306358476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3306358476
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1011437671
Short name T607
Test name
Test status
Simulation time 35882622643 ps
CPU time 18.22 seconds
Started Jul 02 09:26:57 AM PDT 24
Finished Jul 02 09:27:16 AM PDT 24
Peak memory 199820 kb
Host smart-6cbbda93-e411-479c-9796-8db38cf66e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011437671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1011437671
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.4248757314
Short name T234
Test name
Test status
Simulation time 8846501367 ps
CPU time 16.51 seconds
Started Jul 02 09:26:59 AM PDT 24
Finished Jul 02 09:27:16 AM PDT 24
Peak memory 200024 kb
Host smart-654a849b-65ca-4292-aa68-a899a27bbe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248757314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.4248757314
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.504910436
Short name T181
Test name
Test status
Simulation time 97961697440 ps
CPU time 75.48 seconds
Started Jul 02 09:26:58 AM PDT 24
Finished Jul 02 09:28:14 AM PDT 24
Peak memory 199876 kb
Host smart-c28d00aa-bf3a-4931-adb2-67b55240f38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504910436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.504910436
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2986006177
Short name T133
Test name
Test status
Simulation time 66537154095 ps
CPU time 80.93 seconds
Started Jul 02 09:26:59 AM PDT 24
Finished Jul 02 09:28:20 AM PDT 24
Peak memory 199928 kb
Host smart-8a8538cd-ec86-4658-a48e-913647224600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986006177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2986006177
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.346270423
Short name T831
Test name
Test status
Simulation time 124820567589 ps
CPU time 182.05 seconds
Started Jul 02 09:26:57 AM PDT 24
Finished Jul 02 09:30:00 AM PDT 24
Peak memory 200000 kb
Host smart-f83ab34c-0ca4-4bae-b58e-ec3a01670e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346270423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.346270423
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1200884
Short name T241
Test name
Test status
Simulation time 173651236805 ps
CPU time 219.42 seconds
Started Jul 02 09:26:59 AM PDT 24
Finished Jul 02 09:30:39 AM PDT 24
Peak memory 199912 kb
Host smart-a12403c9-3462-422c-8749-b980ba2e5c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1200884
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.691688139
Short name T713
Test name
Test status
Simulation time 13675323 ps
CPU time 0.56 seconds
Started Jul 02 09:24:04 AM PDT 24
Finished Jul 02 09:24:06 AM PDT 24
Peak memory 194696 kb
Host smart-b28481c6-f24f-47ee-bfd9-bdcb0d61d9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691688139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.691688139
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2506868903
Short name T473
Test name
Test status
Simulation time 181579479947 ps
CPU time 69.76 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:25:13 AM PDT 24
Peak memory 200000 kb
Host smart-d8de0104-cdf5-46d1-8c8c-10e9c45515e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506868903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2506868903
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1221535660
Short name T857
Test name
Test status
Simulation time 70495918774 ps
CPU time 55.07 seconds
Started Jul 02 09:23:59 AM PDT 24
Finished Jul 02 09:24:55 AM PDT 24
Peak memory 199724 kb
Host smart-92944f40-4fb8-4990-a4e0-3309961acc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221535660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1221535660
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1201081505
Short name T910
Test name
Test status
Simulation time 20093635853 ps
CPU time 33.1 seconds
Started Jul 02 09:24:02 AM PDT 24
Finished Jul 02 09:24:37 AM PDT 24
Peak memory 199932 kb
Host smart-11910f9f-ea27-4d5b-b3c7-e87c543fda6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201081505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1201081505
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3886410847
Short name T544
Test name
Test status
Simulation time 7276035745 ps
CPU time 2.32 seconds
Started Jul 02 09:23:59 AM PDT 24
Finished Jul 02 09:24:02 AM PDT 24
Peak memory 196836 kb
Host smart-1ba88276-9207-498d-a651-a046b0a6e7dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886410847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3886410847
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3536064911
Short name T573
Test name
Test status
Simulation time 305903533491 ps
CPU time 461.85 seconds
Started Jul 02 09:24:03 AM PDT 24
Finished Jul 02 09:31:47 AM PDT 24
Peak memory 199836 kb
Host smart-25ee98c4-47b7-4473-bc75-e784e6a1ecbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536064911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3536064911
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2222319195
Short name T998
Test name
Test status
Simulation time 2768858280 ps
CPU time 1.19 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:24:04 AM PDT 24
Peak memory 197648 kb
Host smart-b9d52850-5d95-44f0-a647-079159aa8f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222319195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2222319195
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.3993558072
Short name T977
Test name
Test status
Simulation time 17859964931 ps
CPU time 898.86 seconds
Started Jul 02 09:24:02 AM PDT 24
Finished Jul 02 09:39:03 AM PDT 24
Peak memory 199960 kb
Host smart-6c3f943e-9414-404a-b4c9-543887419ca0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993558072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3993558072
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.448837206
Short name T1083
Test name
Test status
Simulation time 6359076481 ps
CPU time 27.87 seconds
Started Jul 02 09:24:02 AM PDT 24
Finished Jul 02 09:24:31 AM PDT 24
Peak memory 198744 kb
Host smart-98ada4b6-3845-42fa-b9ef-6cda6c44285f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448837206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.448837206
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.262654529
Short name T660
Test name
Test status
Simulation time 9189569327 ps
CPU time 7.44 seconds
Started Jul 02 09:24:03 AM PDT 24
Finished Jul 02 09:24:12 AM PDT 24
Peak memory 199548 kb
Host smart-102e5391-6ee5-4f32-a4f2-e6a1b3d3fde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262654529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.262654529
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1325649829
Short name T513
Test name
Test status
Simulation time 6483651469 ps
CPU time 5.7 seconds
Started Jul 02 09:23:59 AM PDT 24
Finished Jul 02 09:24:06 AM PDT 24
Peak memory 196660 kb
Host smart-86bb990f-db23-4dfc-9f78-c35b61c5a568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325649829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1325649829
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3017586679
Short name T478
Test name
Test status
Simulation time 5519450541 ps
CPU time 16.85 seconds
Started Jul 02 09:24:01 AM PDT 24
Finished Jul 02 09:24:19 AM PDT 24
Peak memory 199936 kb
Host smart-94ae9b11-6594-45e8-9d79-347c668cd64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017586679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3017586679
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1270119416
Short name T614
Test name
Test status
Simulation time 47732202691 ps
CPU time 71.18 seconds
Started Jul 02 09:24:06 AM PDT 24
Finished Jul 02 09:25:18 AM PDT 24
Peak memory 199944 kb
Host smart-34499963-8e2e-42bc-977c-6b2a604eac99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270119416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1270119416
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.4197878910
Short name T782
Test name
Test status
Simulation time 7975984089 ps
CPU time 13.48 seconds
Started Jul 02 09:24:03 AM PDT 24
Finished Jul 02 09:24:18 AM PDT 24
Peak memory 199616 kb
Host smart-5b5fae73-cc5b-43bf-99ad-4a5a59163996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197878910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.4197878910
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2873898034
Short name T1023
Test name
Test status
Simulation time 21868193391 ps
CPU time 11.69 seconds
Started Jul 02 09:23:56 AM PDT 24
Finished Jul 02 09:24:09 AM PDT 24
Peak memory 199908 kb
Host smart-cd4bad2b-edc7-47dc-88f9-6423065d4d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873898034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2873898034
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2608269878
Short name T207
Test name
Test status
Simulation time 58962990428 ps
CPU time 92.54 seconds
Started Jul 02 09:26:58 AM PDT 24
Finished Jul 02 09:28:31 AM PDT 24
Peak memory 199988 kb
Host smart-0ea73e07-78a9-4970-ae9d-437e179f0fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608269878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2608269878
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3280087281
Short name T759
Test name
Test status
Simulation time 3080537953 ps
CPU time 5.98 seconds
Started Jul 02 09:26:57 AM PDT 24
Finished Jul 02 09:27:03 AM PDT 24
Peak memory 199972 kb
Host smart-ee60d4ba-1297-4402-a734-dd944f0ec138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280087281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3280087281
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2587141884
Short name T869
Test name
Test status
Simulation time 17593504745 ps
CPU time 49.58 seconds
Started Jul 02 09:26:59 AM PDT 24
Finished Jul 02 09:27:49 AM PDT 24
Peak memory 199940 kb
Host smart-5daa6a34-c765-4bb9-8a3d-2b6f61ff7525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587141884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2587141884
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3338261510
Short name T646
Test name
Test status
Simulation time 25230814757 ps
CPU time 30.23 seconds
Started Jul 02 09:27:03 AM PDT 24
Finished Jul 02 09:27:34 AM PDT 24
Peak memory 198812 kb
Host smart-ed68cfab-7114-46be-890c-8a0905343e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338261510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3338261510
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2764815061
Short name T555
Test name
Test status
Simulation time 11279434384 ps
CPU time 19.79 seconds
Started Jul 02 09:27:03 AM PDT 24
Finished Jul 02 09:27:23 AM PDT 24
Peak memory 199600 kb
Host smart-9e9c5eb4-3fa4-42e3-b9f4-f8260d81974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764815061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2764815061
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3956939457
Short name T1078
Test name
Test status
Simulation time 49441896405 ps
CPU time 48.59 seconds
Started Jul 02 09:27:02 AM PDT 24
Finished Jul 02 09:27:51 AM PDT 24
Peak memory 199912 kb
Host smart-004dcd31-0ce9-4bb2-98d8-f8670ec2faa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956939457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3956939457
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3894883106
Short name T1075
Test name
Test status
Simulation time 26002289 ps
CPU time 0.58 seconds
Started Jul 02 09:24:10 AM PDT 24
Finished Jul 02 09:24:11 AM PDT 24
Peak memory 195224 kb
Host smart-1151127b-112a-4ff3-9389-978a530897fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894883106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3894883106
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3522211945
Short name T988
Test name
Test status
Simulation time 75960160830 ps
CPU time 103.68 seconds
Started Jul 02 09:24:04 AM PDT 24
Finished Jul 02 09:25:49 AM PDT 24
Peak memory 199936 kb
Host smart-4088eb36-e287-4093-a9dd-148d5eb9d8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522211945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3522211945
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2455196516
Short name T927
Test name
Test status
Simulation time 155242764383 ps
CPU time 216.94 seconds
Started Jul 02 09:24:03 AM PDT 24
Finished Jul 02 09:27:42 AM PDT 24
Peak memory 199964 kb
Host smart-c58bb374-b81a-4bd9-a5e3-d2cd0f67666d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455196516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2455196516
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2568307109
Short name T878
Test name
Test status
Simulation time 169916732323 ps
CPU time 596.83 seconds
Started Jul 02 09:24:04 AM PDT 24
Finished Jul 02 09:34:02 AM PDT 24
Peak memory 199968 kb
Host smart-d4b9ac40-13e9-4c52-8111-ab96bf8b2eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568307109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2568307109
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3522851863
Short name T415
Test name
Test status
Simulation time 283972577283 ps
CPU time 208.51 seconds
Started Jul 02 09:24:04 AM PDT 24
Finished Jul 02 09:27:33 AM PDT 24
Peak memory 199628 kb
Host smart-a470360e-20da-42f6-8a7d-4e8ac8d73493
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522851863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3522851863
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3296455223
Short name T299
Test name
Test status
Simulation time 78721457598 ps
CPU time 137.84 seconds
Started Jul 02 09:24:08 AM PDT 24
Finished Jul 02 09:26:27 AM PDT 24
Peak memory 199892 kb
Host smart-7e3faacf-14df-46fa-abab-1cdf45eec4b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296455223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3296455223
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1582764538
Short name T958
Test name
Test status
Simulation time 9260125020 ps
CPU time 7.79 seconds
Started Jul 02 09:24:04 AM PDT 24
Finished Jul 02 09:24:13 AM PDT 24
Peak memory 199684 kb
Host smart-1c18c9c9-014c-4871-8207-973245b6e359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582764538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1582764538
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.2705453647
Short name T611
Test name
Test status
Simulation time 10722743438 ps
CPU time 142.68 seconds
Started Jul 02 09:24:03 AM PDT 24
Finished Jul 02 09:26:27 AM PDT 24
Peak memory 199884 kb
Host smart-856e0333-5550-4e5a-91cb-aeb42eea5d3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705453647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2705453647
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.412244889
Short name T732
Test name
Test status
Simulation time 6317666008 ps
CPU time 17.78 seconds
Started Jul 02 09:24:04 AM PDT 24
Finished Jul 02 09:24:23 AM PDT 24
Peak memory 199176 kb
Host smart-4396c8d2-53e1-4cb2-ab33-d312af80bdb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412244889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.412244889
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3979578032
Short name T1084
Test name
Test status
Simulation time 25763058033 ps
CPU time 47.43 seconds
Started Jul 02 09:24:05 AM PDT 24
Finished Jul 02 09:24:53 AM PDT 24
Peak memory 199760 kb
Host smart-5209f5c3-c2dd-4024-bc24-65f14bcd7037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979578032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3979578032
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2373056803
Short name T396
Test name
Test status
Simulation time 1385861226 ps
CPU time 1.18 seconds
Started Jul 02 09:24:05 AM PDT 24
Finished Jul 02 09:24:07 AM PDT 24
Peak memory 195524 kb
Host smart-8645a741-3785-4f89-a967-993eddda0494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373056803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2373056803
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2047470947
Short name T71
Test name
Test status
Simulation time 270823880 ps
CPU time 1.73 seconds
Started Jul 02 09:24:05 AM PDT 24
Finished Jul 02 09:24:07 AM PDT 24
Peak memory 198756 kb
Host smart-fe2465c4-0db5-4d7c-ad6b-fd5a2519deec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047470947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2047470947
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3036874557
Short name T751
Test name
Test status
Simulation time 9364532319 ps
CPU time 8.96 seconds
Started Jul 02 09:24:04 AM PDT 24
Finished Jul 02 09:24:14 AM PDT 24
Peak memory 199552 kb
Host smart-3a86e9f4-db39-44d2-abd7-17f5111ac2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036874557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3036874557
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.802227022
Short name T548
Test name
Test status
Simulation time 48850216049 ps
CPU time 45.82 seconds
Started Jul 02 09:24:04 AM PDT 24
Finished Jul 02 09:24:51 AM PDT 24
Peak memory 199972 kb
Host smart-8c34a165-0f23-49b2-be71-b125065c28f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802227022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.802227022
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2132709717
Short name T547
Test name
Test status
Simulation time 40550369163 ps
CPU time 54.9 seconds
Started Jul 02 09:27:03 AM PDT 24
Finished Jul 02 09:27:58 AM PDT 24
Peak memory 199892 kb
Host smart-963c0537-430f-4c33-94b2-e7f2a49c260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132709717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2132709717
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.639717103
Short name T287
Test name
Test status
Simulation time 11476879726 ps
CPU time 14.21 seconds
Started Jul 02 09:27:05 AM PDT 24
Finished Jul 02 09:27:19 AM PDT 24
Peak memory 199944 kb
Host smart-6f356845-ce93-4d10-b5fe-14132f3b41cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639717103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.639717103
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2753255438
Short name T142
Test name
Test status
Simulation time 56610478682 ps
CPU time 25.18 seconds
Started Jul 02 09:27:06 AM PDT 24
Finished Jul 02 09:27:31 AM PDT 24
Peak memory 199932 kb
Host smart-fa00e818-796d-4992-a466-1ceb842cb2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753255438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2753255438
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3662052348
Short name T1076
Test name
Test status
Simulation time 117034685989 ps
CPU time 89.88 seconds
Started Jul 02 09:27:03 AM PDT 24
Finished Jul 02 09:28:34 AM PDT 24
Peak memory 199892 kb
Host smart-19fa9177-bec3-4de2-afe7-4d35a331c54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662052348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3662052348
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1509232934
Short name T1018
Test name
Test status
Simulation time 131171683355 ps
CPU time 39.4 seconds
Started Jul 02 09:27:06 AM PDT 24
Finished Jul 02 09:27:46 AM PDT 24
Peak memory 199944 kb
Host smart-8d538a73-35e2-4f9e-9086-0f0b7bd16d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509232934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1509232934
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1957547789
Short name T194
Test name
Test status
Simulation time 21054775621 ps
CPU time 33 seconds
Started Jul 02 09:27:11 AM PDT 24
Finished Jul 02 09:27:44 AM PDT 24
Peak memory 200004 kb
Host smart-632909da-e6c3-414c-b6e1-08d7e99ddcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957547789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1957547789
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1841748012
Short name T475
Test name
Test status
Simulation time 110245545900 ps
CPU time 11.83 seconds
Started Jul 02 09:27:07 AM PDT 24
Finished Jul 02 09:27:20 AM PDT 24
Peak memory 199888 kb
Host smart-3b98d7eb-94dc-4ab1-9b04-ab3e9df75c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841748012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1841748012
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.773837779
Short name T524
Test name
Test status
Simulation time 15978277 ps
CPU time 0.64 seconds
Started Jul 02 09:24:08 AM PDT 24
Finished Jul 02 09:24:09 AM PDT 24
Peak memory 195324 kb
Host smart-495262d0-e710-4312-937a-d3c8afe9248a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773837779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.773837779
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3325609553
Short name T600
Test name
Test status
Simulation time 51863811509 ps
CPU time 77.49 seconds
Started Jul 02 09:24:06 AM PDT 24
Finished Jul 02 09:25:24 AM PDT 24
Peak memory 199980 kb
Host smart-596f8853-2b11-4b1a-a450-f2c6cba08880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325609553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3325609553
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.357758613
Short name T702
Test name
Test status
Simulation time 111619190248 ps
CPU time 153.49 seconds
Started Jul 02 09:24:07 AM PDT 24
Finished Jul 02 09:26:41 AM PDT 24
Peak memory 199980 kb
Host smart-48921ce6-637f-4ded-8fed-adcf39419c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357758613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.357758613
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.980855493
Short name T221
Test name
Test status
Simulation time 298733093658 ps
CPU time 69.92 seconds
Started Jul 02 09:24:07 AM PDT 24
Finished Jul 02 09:25:18 AM PDT 24
Peak memory 199940 kb
Host smart-48942a72-e987-46c7-871b-c031c48d5169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980855493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.980855493
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1834140105
Short name T624
Test name
Test status
Simulation time 17581684198 ps
CPU time 11.35 seconds
Started Jul 02 09:24:08 AM PDT 24
Finished Jul 02 09:24:20 AM PDT 24
Peak memory 199884 kb
Host smart-3f04d23a-c8d0-47f4-b196-24112cb1608f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834140105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1834140105
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_loopback.1090645834
Short name T922
Test name
Test status
Simulation time 92124380 ps
CPU time 0.58 seconds
Started Jul 02 09:24:11 AM PDT 24
Finished Jul 02 09:24:12 AM PDT 24
Peak memory 195716 kb
Host smart-8ba6f338-90e0-472c-a54d-586b7784ac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090645834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1090645834
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.782115165
Short name T280
Test name
Test status
Simulation time 8272627614 ps
CPU time 419.2 seconds
Started Jul 02 09:24:06 AM PDT 24
Finished Jul 02 09:31:06 AM PDT 24
Peak memory 199960 kb
Host smart-a6a1728e-3287-4e8b-a5a6-e8821c7b5061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=782115165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.782115165
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3299488157
Short name T355
Test name
Test status
Simulation time 1925260612 ps
CPU time 2.59 seconds
Started Jul 02 09:24:08 AM PDT 24
Finished Jul 02 09:24:11 AM PDT 24
Peak memory 198120 kb
Host smart-1b402fac-71d2-4fd3-9b2c-af3737e89fe4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3299488157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3299488157
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3834342530
Short name T167
Test name
Test status
Simulation time 267629356816 ps
CPU time 68.59 seconds
Started Jul 02 09:24:08 AM PDT 24
Finished Jul 02 09:25:17 AM PDT 24
Peak memory 199892 kb
Host smart-6cd55d22-f767-4d88-ac3f-e9138bf7b5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834342530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3834342530
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2937103283
Short name T974
Test name
Test status
Simulation time 2186411074 ps
CPU time 2.38 seconds
Started Jul 02 09:24:08 AM PDT 24
Finished Jul 02 09:24:11 AM PDT 24
Peak memory 195384 kb
Host smart-d7b1af79-c00b-4a8b-a2a8-78e11848057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937103283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2937103283
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3373539313
Short name T941
Test name
Test status
Simulation time 446240679 ps
CPU time 2.26 seconds
Started Jul 02 09:24:11 AM PDT 24
Finished Jul 02 09:24:14 AM PDT 24
Peak memory 198628 kb
Host smart-04eff482-5ef2-4258-80a2-7e7a1ae35c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373539313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3373539313
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1340468508
Short name T268
Test name
Test status
Simulation time 156923482251 ps
CPU time 315.68 seconds
Started Jul 02 09:24:06 AM PDT 24
Finished Jul 02 09:29:22 AM PDT 24
Peak memory 199880 kb
Host smart-933a1b3e-362a-4c11-ba6c-e3f040e4bb62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340468508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1340468508
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2947225267
Short name T111
Test name
Test status
Simulation time 378644114543 ps
CPU time 881.38 seconds
Started Jul 02 09:24:08 AM PDT 24
Finished Jul 02 09:38:50 AM PDT 24
Peak memory 216612 kb
Host smart-8e65d807-5e55-4935-a4da-7ef166af2ece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947225267 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2947225267
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3504487749
Short name T315
Test name
Test status
Simulation time 897372097 ps
CPU time 1.84 seconds
Started Jul 02 09:24:06 AM PDT 24
Finished Jul 02 09:24:09 AM PDT 24
Peak memory 199908 kb
Host smart-90dd95a2-a20d-42a4-8cd9-462e700d5c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504487749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3504487749
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1720671128
Short name T812
Test name
Test status
Simulation time 69526578766 ps
CPU time 101.38 seconds
Started Jul 02 09:24:08 AM PDT 24
Finished Jul 02 09:25:50 AM PDT 24
Peak memory 199956 kb
Host smart-0f09df60-af04-48c3-9290-c11b7761d4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720671128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1720671128
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1290768993
Short name T240
Test name
Test status
Simulation time 102560327500 ps
CPU time 43.85 seconds
Started Jul 02 09:27:08 AM PDT 24
Finished Jul 02 09:27:52 AM PDT 24
Peak memory 199952 kb
Host smart-a4722288-4b0e-4190-85aa-304846cdeffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290768993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1290768993
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.266534543
Short name T895
Test name
Test status
Simulation time 36920731604 ps
CPU time 69.62 seconds
Started Jul 02 09:27:10 AM PDT 24
Finished Jul 02 09:28:20 AM PDT 24
Peak memory 199928 kb
Host smart-9a42c514-f84a-4eb9-8a22-e21b63507f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266534543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.266534543
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1924805697
Short name T766
Test name
Test status
Simulation time 112790956840 ps
CPU time 45.4 seconds
Started Jul 02 09:27:12 AM PDT 24
Finished Jul 02 09:27:58 AM PDT 24
Peak memory 199988 kb
Host smart-1ac02beb-a280-4a56-b62d-e9f310370c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924805697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1924805697
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3744471599
Short name T174
Test name
Test status
Simulation time 49218244447 ps
CPU time 29.1 seconds
Started Jul 02 09:27:08 AM PDT 24
Finished Jul 02 09:27:38 AM PDT 24
Peak memory 199644 kb
Host smart-e4b4dc3c-b51d-442d-827c-81f25e306122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744471599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3744471599
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1193194748
Short name T790
Test name
Test status
Simulation time 49713818910 ps
CPU time 20.03 seconds
Started Jul 02 09:27:09 AM PDT 24
Finished Jul 02 09:27:29 AM PDT 24
Peak memory 200028 kb
Host smart-7cb5321d-e1d2-414f-81bd-1e565e8a6ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193194748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1193194748
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1700498487
Short name T138
Test name
Test status
Simulation time 22099187335 ps
CPU time 33.71 seconds
Started Jul 02 09:27:05 AM PDT 24
Finished Jul 02 09:27:39 AM PDT 24
Peak memory 199960 kb
Host smart-abe27042-e4d1-4587-a10b-6bc5037646f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700498487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1700498487
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.519852155
Short name T740
Test name
Test status
Simulation time 48187938448 ps
CPU time 21.94 seconds
Started Jul 02 09:27:11 AM PDT 24
Finished Jul 02 09:27:33 AM PDT 24
Peak memory 199968 kb
Host smart-69e7438b-8ad5-486c-9595-914391286097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519852155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.519852155
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.79436329
Short name T723
Test name
Test status
Simulation time 17550307 ps
CPU time 0.62 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:23:15 AM PDT 24
Peak memory 195316 kb
Host smart-24dd1822-74a0-499b-8721-6e3c2fe94d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79436329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.79436329
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.166481231
Short name T836
Test name
Test status
Simulation time 38575944622 ps
CPU time 13.88 seconds
Started Jul 02 09:22:49 AM PDT 24
Finished Jul 02 09:23:04 AM PDT 24
Peak memory 199972 kb
Host smart-75bc439f-e9aa-456b-8cfb-a547111169a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166481231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.166481231
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.738774490
Short name T498
Test name
Test status
Simulation time 111187924293 ps
CPU time 46.57 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:23:54 AM PDT 24
Peak memory 199964 kb
Host smart-2b7d0eae-e15d-4821-ba0e-af171038135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738774490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.738774490
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.343930131
Short name T35
Test name
Test status
Simulation time 31407346327 ps
CPU time 19.06 seconds
Started Jul 02 09:23:03 AM PDT 24
Finished Jul 02 09:23:22 AM PDT 24
Peak memory 200004 kb
Host smart-7d4bd7b7-370a-4c45-8eff-d0dc67d95834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343930131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.343930131
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3052495419
Short name T634
Test name
Test status
Simulation time 28334133700 ps
CPU time 6.54 seconds
Started Jul 02 09:22:50 AM PDT 24
Finished Jul 02 09:22:57 AM PDT 24
Peak memory 197400 kb
Host smart-5e6f179a-270f-40c5-b8a7-91b056d49e8b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052495419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3052495419
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2740852268
Short name T484
Test name
Test status
Simulation time 142495866446 ps
CPU time 775.1 seconds
Started Jul 02 09:22:59 AM PDT 24
Finished Jul 02 09:35:54 AM PDT 24
Peak memory 199920 kb
Host smart-059ad329-3ccd-49f2-9de2-f8978c946c36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740852268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2740852268
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1766709625
Short name T936
Test name
Test status
Simulation time 124193328 ps
CPU time 0.65 seconds
Started Jul 02 09:23:04 AM PDT 24
Finished Jul 02 09:23:06 AM PDT 24
Peak memory 196024 kb
Host smart-c2c45d14-e935-41ac-af28-68686e009c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766709625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1766709625
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.1111031915
Short name T537
Test name
Test status
Simulation time 11188270045 ps
CPU time 521.24 seconds
Started Jul 02 09:22:55 AM PDT 24
Finished Jul 02 09:31:37 AM PDT 24
Peak memory 200020 kb
Host smart-9cc549ed-ae74-437b-8b85-e6a119a9eb33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1111031915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1111031915
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3662689697
Short name T363
Test name
Test status
Simulation time 2217427095 ps
CPU time 15.11 seconds
Started Jul 02 09:23:00 AM PDT 24
Finished Jul 02 09:23:15 AM PDT 24
Peak memory 198260 kb
Host smart-23c2f397-e780-41f3-a024-a7b900e1d65c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3662689697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3662689697
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2757878483
Short name T987
Test name
Test status
Simulation time 18153466438 ps
CPU time 13.68 seconds
Started Jul 02 09:22:54 AM PDT 24
Finished Jul 02 09:23:09 AM PDT 24
Peak memory 199956 kb
Host smart-f3ec4340-6e6d-4e8d-bb70-1ee4005fa4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757878483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2757878483
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2590201809
Short name T663
Test name
Test status
Simulation time 2392687766 ps
CPU time 2.52 seconds
Started Jul 02 09:23:07 AM PDT 24
Finished Jul 02 09:23:11 AM PDT 24
Peak memory 196356 kb
Host smart-63570092-ce3c-4301-83fa-16ae2b7896d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590201809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2590201809
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.337436867
Short name T95
Test name
Test status
Simulation time 34044948 ps
CPU time 0.77 seconds
Started Jul 02 09:22:58 AM PDT 24
Finished Jul 02 09:22:59 AM PDT 24
Peak memory 218188 kb
Host smart-209fa2d1-9c93-4da3-98e7-4867d41ec8db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337436867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.337436867
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2724310500
Short name T1082
Test name
Test status
Simulation time 5785100186 ps
CPU time 35.69 seconds
Started Jul 02 09:23:05 AM PDT 24
Finished Jul 02 09:23:42 AM PDT 24
Peak memory 199500 kb
Host smart-1eabd4a5-b3c2-425a-8d79-6978da1a6c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724310500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2724310500
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3148801903
Short name T980
Test name
Test status
Simulation time 72525370639 ps
CPU time 845.85 seconds
Started Jul 02 09:22:49 AM PDT 24
Finished Jul 02 09:36:56 AM PDT 24
Peak memory 216512 kb
Host smart-4265641b-dbd6-453c-a030-19b23504f77c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148801903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3148801903
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3919115874
Short name T1051
Test name
Test status
Simulation time 13869834064 ps
CPU time 21.64 seconds
Started Jul 02 09:23:00 AM PDT 24
Finished Jul 02 09:23:22 AM PDT 24
Peak memory 199988 kb
Host smart-411be07e-7f5d-4d04-9d8d-92cc035fceb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919115874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3919115874
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.671019517
Short name T270
Test name
Test status
Simulation time 154259611024 ps
CPU time 56.81 seconds
Started Jul 02 09:22:58 AM PDT 24
Finished Jul 02 09:24:01 AM PDT 24
Peak memory 199892 kb
Host smart-75cbab37-c8b8-4fdd-b808-fbc0d46abdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671019517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.671019517
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.219815798
Short name T399
Test name
Test status
Simulation time 13538138 ps
CPU time 0.55 seconds
Started Jul 02 09:24:17 AM PDT 24
Finished Jul 02 09:24:18 AM PDT 24
Peak memory 195564 kb
Host smart-a4c299ae-ebba-4591-920e-92bf1f7a2651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219815798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.219815798
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1720682964
Short name T739
Test name
Test status
Simulation time 28253719580 ps
CPU time 19.91 seconds
Started Jul 02 09:24:11 AM PDT 24
Finished Jul 02 09:24:32 AM PDT 24
Peak memory 199916 kb
Host smart-7b0751e2-c23d-41a2-86c5-98f414a2d28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720682964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1720682964
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2043745290
Short name T712
Test name
Test status
Simulation time 65184247670 ps
CPU time 33.04 seconds
Started Jul 02 09:24:12 AM PDT 24
Finished Jul 02 09:24:46 AM PDT 24
Peak memory 199936 kb
Host smart-ce1d97d3-7b8f-40ba-a129-246c7b222f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043745290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2043745290
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3910423960
Short name T794
Test name
Test status
Simulation time 99178691043 ps
CPU time 204.31 seconds
Started Jul 02 09:24:10 AM PDT 24
Finished Jul 02 09:27:35 AM PDT 24
Peak memory 199908 kb
Host smart-6a4bc267-f933-44b7-9ee1-4966d7aa5bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910423960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3910423960
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.938348433
Short name T896
Test name
Test status
Simulation time 5959352522 ps
CPU time 14.69 seconds
Started Jul 02 09:24:12 AM PDT 24
Finished Jul 02 09:24:28 AM PDT 24
Peak memory 199764 kb
Host smart-9817ebe7-23bc-46b4-b35b-342e3eaf6dfb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938348433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.938348433
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3089248565
Short name T418
Test name
Test status
Simulation time 247474013594 ps
CPU time 146.31 seconds
Started Jul 02 09:24:11 AM PDT 24
Finished Jul 02 09:26:38 AM PDT 24
Peak memory 199948 kb
Host smart-d3a2df7f-a7a9-4e41-8d16-01f42d289dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089248565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3089248565
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3441140678
Short name T571
Test name
Test status
Simulation time 7209601803 ps
CPU time 8.55 seconds
Started Jul 02 09:24:10 AM PDT 24
Finished Jul 02 09:24:19 AM PDT 24
Peak memory 199668 kb
Host smart-45c82255-966d-48eb-b1fe-14f3981a0356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441140678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3441140678
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.3907901891
Short name T386
Test name
Test status
Simulation time 12230326569 ps
CPU time 733.72 seconds
Started Jul 02 09:24:13 AM PDT 24
Finished Jul 02 09:36:27 AM PDT 24
Peak memory 199960 kb
Host smart-8e816d98-b871-4c65-bfee-073c1940a22a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3907901891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3907901891
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2752695860
Short name T824
Test name
Test status
Simulation time 3500358877 ps
CPU time 24.39 seconds
Started Jul 02 09:24:11 AM PDT 24
Finished Jul 02 09:24:36 AM PDT 24
Peak memory 198628 kb
Host smart-3ad434f9-d2d1-4b87-815a-cb331c61e069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752695860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2752695860
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1245040533
Short name T327
Test name
Test status
Simulation time 73865870271 ps
CPU time 45.35 seconds
Started Jul 02 09:24:12 AM PDT 24
Finished Jul 02 09:24:58 AM PDT 24
Peak memory 199936 kb
Host smart-9d494186-f588-402a-bd4b-7088e35c2ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245040533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1245040533
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.959002261
Short name T403
Test name
Test status
Simulation time 41508176208 ps
CPU time 15.88 seconds
Started Jul 02 09:24:11 AM PDT 24
Finished Jul 02 09:24:27 AM PDT 24
Peak memory 195932 kb
Host smart-1b5f4045-3f5c-4e43-945c-9791b797dce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959002261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.959002261
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3088507715
Short name T675
Test name
Test status
Simulation time 726333549 ps
CPU time 1.66 seconds
Started Jul 02 09:24:07 AM PDT 24
Finished Jul 02 09:24:09 AM PDT 24
Peak memory 198252 kb
Host smart-0374f581-704d-4061-ab1a-e70ab6f5048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088507715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3088507715
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1830382313
Short name T943
Test name
Test status
Simulation time 13174261747 ps
CPU time 23.06 seconds
Started Jul 02 09:24:16 AM PDT 24
Finished Jul 02 09:24:40 AM PDT 24
Peak memory 199800 kb
Host smart-cafd9b1e-eb40-43d7-8639-23979fc42ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830382313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1830382313
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.567803124
Short name T940
Test name
Test status
Simulation time 57315123663 ps
CPU time 311.8 seconds
Started Jul 02 09:24:12 AM PDT 24
Finished Jul 02 09:29:25 AM PDT 24
Peak memory 208312 kb
Host smart-9d03756d-84d2-48e2-bd62-f2bc6913d1cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567803124 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.567803124
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3402670673
Short name T673
Test name
Test status
Simulation time 743748394 ps
CPU time 3.12 seconds
Started Jul 02 09:24:09 AM PDT 24
Finished Jul 02 09:24:13 AM PDT 24
Peak memory 199648 kb
Host smart-5fe4e1f3-80db-4262-b677-6ec11435463a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402670673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3402670673
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.107033439
Short name T835
Test name
Test status
Simulation time 108940468736 ps
CPU time 153.91 seconds
Started Jul 02 09:24:10 AM PDT 24
Finished Jul 02 09:26:44 AM PDT 24
Peak memory 199828 kb
Host smart-4303d5a1-860a-47fa-8ddf-edc157473848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107033439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.107033439
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2561288816
Short name T593
Test name
Test status
Simulation time 78084032 ps
CPU time 0.62 seconds
Started Jul 02 09:24:20 AM PDT 24
Finished Jul 02 09:24:22 AM PDT 24
Peak memory 195480 kb
Host smart-1c9a9939-e310-4a46-855d-b064e2af6766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561288816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2561288816
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2012050787
Short name T1054
Test name
Test status
Simulation time 87644211429 ps
CPU time 125.89 seconds
Started Jul 02 09:24:15 AM PDT 24
Finished Jul 02 09:26:22 AM PDT 24
Peak memory 199904 kb
Host smart-39eb0cf2-b204-4b44-9509-aaa14fc11161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012050787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2012050787
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1993781368
Short name T314
Test name
Test status
Simulation time 52606892659 ps
CPU time 92.47 seconds
Started Jul 02 09:24:15 AM PDT 24
Finished Jul 02 09:25:49 AM PDT 24
Peak memory 199852 kb
Host smart-248e26d0-7b99-4c1a-937e-10f08dd415bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993781368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1993781368
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.791968750
Short name T341
Test name
Test status
Simulation time 52020363630 ps
CPU time 79.77 seconds
Started Jul 02 09:24:17 AM PDT 24
Finished Jul 02 09:25:37 AM PDT 24
Peak memory 199968 kb
Host smart-7157f25c-5886-4199-a656-b408a7e271e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791968750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.791968750
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.64829124
Short name T834
Test name
Test status
Simulation time 40988073401 ps
CPU time 22.64 seconds
Started Jul 02 09:24:16 AM PDT 24
Finished Jul 02 09:24:39 AM PDT 24
Peak memory 200004 kb
Host smart-a8a1f0ef-9eb9-4a4f-b886-08cd58e2a7a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64829124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.64829124
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.216448855
Short name T853
Test name
Test status
Simulation time 115273858520 ps
CPU time 579.6 seconds
Started Jul 02 09:24:19 AM PDT 24
Finished Jul 02 09:33:59 AM PDT 24
Peak memory 199956 kb
Host smart-2ed7484b-5507-4126-a4e3-2c77717803f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216448855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.216448855
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.733708518
Short name T468
Test name
Test status
Simulation time 13286468533 ps
CPU time 5.66 seconds
Started Jul 02 09:24:24 AM PDT 24
Finished Jul 02 09:24:30 AM PDT 24
Peak memory 199660 kb
Host smart-98e12e00-ff9d-45cf-85a0-6d36b8c47360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733708518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.733708518
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.2609410835
Short name T714
Test name
Test status
Simulation time 16685883547 ps
CPU time 987.8 seconds
Started Jul 02 09:24:19 AM PDT 24
Finished Jul 02 09:40:48 AM PDT 24
Peak memory 199912 kb
Host smart-22bd9b58-9192-4312-8be2-edb7007ca5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609410835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2609410835
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.243768692
Short name T3
Test name
Test status
Simulation time 1489334921 ps
CPU time 3.02 seconds
Started Jul 02 09:24:15 AM PDT 24
Finished Jul 02 09:24:19 AM PDT 24
Peak memory 197932 kb
Host smart-8eb18ae5-af5a-42e1-bd71-98c8a8a4f1fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243768692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.243768692
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1900554619
Short name T792
Test name
Test status
Simulation time 3030805052 ps
CPU time 4.92 seconds
Started Jul 02 09:24:16 AM PDT 24
Finished Jul 02 09:24:21 AM PDT 24
Peak memory 196472 kb
Host smart-87a1a226-2ee5-4a9a-a245-c11e649b29ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900554619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1900554619
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2756879890
Short name T321
Test name
Test status
Simulation time 461675996 ps
CPU time 2.04 seconds
Started Jul 02 09:24:15 AM PDT 24
Finished Jul 02 09:24:18 AM PDT 24
Peak memory 198956 kb
Host smart-98e3482e-b258-4327-bb0b-385eb84662ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756879890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2756879890
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.186752696
Short name T179
Test name
Test status
Simulation time 99019495618 ps
CPU time 157.45 seconds
Started Jul 02 09:24:19 AM PDT 24
Finished Jul 02 09:26:57 AM PDT 24
Peak memory 199904 kb
Host smart-147a3222-20be-469d-8c60-c55a33c3921c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186752696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.186752696
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3059326093
Short name T786
Test name
Test status
Simulation time 91404171922 ps
CPU time 271.21 seconds
Started Jul 02 09:24:20 AM PDT 24
Finished Jul 02 09:28:52 AM PDT 24
Peak memory 209696 kb
Host smart-317c5e45-174e-42ce-8d1a-321bb98bd28b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059326093 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3059326093
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3823851405
Short name T637
Test name
Test status
Simulation time 6827758346 ps
CPU time 29.79 seconds
Started Jul 02 09:24:18 AM PDT 24
Finished Jul 02 09:24:49 AM PDT 24
Peak memory 199348 kb
Host smart-8327f8df-ebd6-478d-a1fb-398d35f57aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823851405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3823851405
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1082906153
Short name T707
Test name
Test status
Simulation time 152745468794 ps
CPU time 29.8 seconds
Started Jul 02 09:24:20 AM PDT 24
Finished Jul 02 09:24:51 AM PDT 24
Peak memory 199936 kb
Host smart-70cee85f-d7a4-4863-a7e5-2d8bb1d8768d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082906153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1082906153
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1951789063
Short name T94
Test name
Test status
Simulation time 36818342 ps
CPU time 0.57 seconds
Started Jul 02 09:24:23 AM PDT 24
Finished Jul 02 09:24:24 AM PDT 24
Peak memory 195304 kb
Host smart-e0816fbb-6670-4f1d-b072-9d44f4c578c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951789063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1951789063
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1875450967
Short name T832
Test name
Test status
Simulation time 28337897235 ps
CPU time 46.48 seconds
Started Jul 02 09:24:27 AM PDT 24
Finished Jul 02 09:25:14 AM PDT 24
Peak memory 199940 kb
Host smart-bb9d2c43-6a3a-47e9-8cc4-f192cf6ab5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875450967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1875450967
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1399811921
Short name T598
Test name
Test status
Simulation time 120671456937 ps
CPU time 88.12 seconds
Started Jul 02 09:24:18 AM PDT 24
Finished Jul 02 09:25:47 AM PDT 24
Peak memory 199900 kb
Host smart-dbc02344-3068-4742-a5cd-3797d4ad9cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399811921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1399811921
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3743901920
Short name T215
Test name
Test status
Simulation time 96450174768 ps
CPU time 46.2 seconds
Started Jul 02 09:24:20 AM PDT 24
Finished Jul 02 09:25:07 AM PDT 24
Peak memory 199920 kb
Host smart-e0142274-c221-42b6-be57-a6971571e23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743901920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3743901920
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3046321548
Short name T115
Test name
Test status
Simulation time 24858617481 ps
CPU time 7.64 seconds
Started Jul 02 09:24:18 AM PDT 24
Finished Jul 02 09:24:27 AM PDT 24
Peak memory 200028 kb
Host smart-b82b9f74-6773-4329-9e1f-c6fae398a194
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046321548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3046321548
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3909204617
Short name T705
Test name
Test status
Simulation time 120493612564 ps
CPU time 598.28 seconds
Started Jul 02 09:24:26 AM PDT 24
Finished Jul 02 09:34:25 AM PDT 24
Peak memory 200004 kb
Host smart-76051f3e-72cd-446d-914e-d9774aa5c4f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909204617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3909204617
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.854911901
Short name T410
Test name
Test status
Simulation time 9946848587 ps
CPU time 9.78 seconds
Started Jul 02 09:24:26 AM PDT 24
Finished Jul 02 09:24:37 AM PDT 24
Peak memory 199924 kb
Host smart-763764ac-c2c9-488a-a8c5-cbecd880947a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854911901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.854911901
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.402161255
Short name T12
Test name
Test status
Simulation time 5483535758 ps
CPU time 290.45 seconds
Started Jul 02 09:24:39 AM PDT 24
Finished Jul 02 09:29:30 AM PDT 24
Peak memory 200008 kb
Host smart-6d40fdec-4d34-4889-aca4-f66176ba51a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402161255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.402161255
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.690725155
Short name T1043
Test name
Test status
Simulation time 5397635547 ps
CPU time 3.72 seconds
Started Jul 02 09:24:20 AM PDT 24
Finished Jul 02 09:24:25 AM PDT 24
Peak memory 198284 kb
Host smart-1fabc91d-500c-4f32-9c2f-baf001948927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690725155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.690725155
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1117976716
Short name T1002
Test name
Test status
Simulation time 62870210908 ps
CPU time 118.62 seconds
Started Jul 02 09:24:19 AM PDT 24
Finished Jul 02 09:26:18 AM PDT 24
Peak memory 199964 kb
Host smart-9b112475-3c41-4037-9523-4eb46287cf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117976716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1117976716
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2396132186
Short name T424
Test name
Test status
Simulation time 39028870245 ps
CPU time 65.31 seconds
Started Jul 02 09:24:19 AM PDT 24
Finished Jul 02 09:25:25 AM PDT 24
Peak memory 196148 kb
Host smart-24df1bfd-978d-4087-befd-8fb4a5747991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396132186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2396132186
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3072429486
Short name T9
Test name
Test status
Simulation time 271556462 ps
CPU time 1.8 seconds
Started Jul 02 09:24:20 AM PDT 24
Finished Jul 02 09:24:23 AM PDT 24
Peak memory 199732 kb
Host smart-75612534-1728-4db7-ba2e-855e0208530e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072429486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3072429486
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.346367773
Short name T113
Test name
Test status
Simulation time 206975260707 ps
CPU time 967.01 seconds
Started Jul 02 09:24:23 AM PDT 24
Finished Jul 02 09:40:30 AM PDT 24
Peak memory 199884 kb
Host smart-289f887b-e369-4f64-bc9f-87da87900c46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346367773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.346367773
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.734874872
Short name T882
Test name
Test status
Simulation time 585021236 ps
CPU time 1.55 seconds
Started Jul 02 09:24:20 AM PDT 24
Finished Jul 02 09:24:22 AM PDT 24
Peak memory 198772 kb
Host smart-fa4be76c-5e01-4d45-be33-89ecbae20751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734874872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.734874872
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.4253472465
Short name T324
Test name
Test status
Simulation time 45422079081 ps
CPU time 63.32 seconds
Started Jul 02 09:24:22 AM PDT 24
Finished Jul 02 09:25:25 AM PDT 24
Peak memory 199948 kb
Host smart-2cd21c86-d428-4747-aac5-e8bdca36434b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253472465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.4253472465
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.12470321
Short name T627
Test name
Test status
Simulation time 94912018 ps
CPU time 0.61 seconds
Started Jul 02 09:24:25 AM PDT 24
Finished Jul 02 09:24:26 AM PDT 24
Peak memory 195296 kb
Host smart-c374be94-14ff-46ed-859a-f4d2a35afdb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12470321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.12470321
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3244581426
Short name T804
Test name
Test status
Simulation time 60370475320 ps
CPU time 88.16 seconds
Started Jul 02 09:24:22 AM PDT 24
Finished Jul 02 09:25:51 AM PDT 24
Peak memory 199948 kb
Host smart-e4412626-ac94-4d51-8df9-61d4db9bea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244581426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3244581426
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.332832467
Short name T337
Test name
Test status
Simulation time 23383991728 ps
CPU time 10.6 seconds
Started Jul 02 09:24:26 AM PDT 24
Finished Jul 02 09:24:38 AM PDT 24
Peak memory 198816 kb
Host smart-df86f381-c566-455d-9b13-bc03f42268a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332832467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.332832467
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3637999805
Short name T211
Test name
Test status
Simulation time 51683386359 ps
CPU time 72.6 seconds
Started Jul 02 09:24:25 AM PDT 24
Finished Jul 02 09:25:38 AM PDT 24
Peak memory 199908 kb
Host smart-b8842898-532f-40b2-a352-9cc7a9e4bda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637999805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3637999805
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1593391054
Short name T935
Test name
Test status
Simulation time 22525525401 ps
CPU time 22.24 seconds
Started Jul 02 09:24:27 AM PDT 24
Finished Jul 02 09:24:50 AM PDT 24
Peak memory 199972 kb
Host smart-f82cc256-3306-4c54-a223-8d97cba1146f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593391054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1593391054
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2280400185
Short name T683
Test name
Test status
Simulation time 138666579899 ps
CPU time 441.93 seconds
Started Jul 02 09:24:25 AM PDT 24
Finished Jul 02 09:31:48 AM PDT 24
Peak memory 199892 kb
Host smart-30337a80-e460-4305-9168-c1dd0d596195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280400185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2280400185
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1399133434
Short name T533
Test name
Test status
Simulation time 6688267627 ps
CPU time 6.02 seconds
Started Jul 02 09:24:24 AM PDT 24
Finished Jul 02 09:24:30 AM PDT 24
Peak memory 199844 kb
Host smart-af2b386b-939d-409b-8f89-ed0d73a85067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399133434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1399133434
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.2274667881
Short name T803
Test name
Test status
Simulation time 15334041632 ps
CPU time 864.41 seconds
Started Jul 02 09:24:22 AM PDT 24
Finished Jul 02 09:38:48 AM PDT 24
Peak memory 199992 kb
Host smart-ec29d416-b50f-4010-8cc4-164409654b31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274667881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2274667881
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1976050440
Short name T934
Test name
Test status
Simulation time 3058481273 ps
CPU time 13 seconds
Started Jul 02 09:24:22 AM PDT 24
Finished Jul 02 09:24:35 AM PDT 24
Peak memory 199080 kb
Host smart-5c6bb2ce-1f89-4319-88ac-cd2e13f287e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976050440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1976050440
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1371997250
Short name T930
Test name
Test status
Simulation time 19156915003 ps
CPU time 14.67 seconds
Started Jul 02 09:24:24 AM PDT 24
Finished Jul 02 09:24:39 AM PDT 24
Peak memory 199956 kb
Host smart-4f058971-eebb-4f7a-861e-f0fec742d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371997250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1371997250
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2359122307
Short name T749
Test name
Test status
Simulation time 4305707904 ps
CPU time 1.73 seconds
Started Jul 02 09:24:24 AM PDT 24
Finished Jul 02 09:24:26 AM PDT 24
Peak memory 196448 kb
Host smart-f0415f5e-f19b-4c18-9742-4c9b9ef96fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359122307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2359122307
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1325205029
Short name T1031
Test name
Test status
Simulation time 507401068 ps
CPU time 3 seconds
Started Jul 02 09:24:23 AM PDT 24
Finished Jul 02 09:24:27 AM PDT 24
Peak memory 198372 kb
Host smart-53fd0305-0414-4746-84ca-977c06711d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325205029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1325205029
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.960078398
Short name T811
Test name
Test status
Simulation time 71135462089 ps
CPU time 34.88 seconds
Started Jul 02 09:24:22 AM PDT 24
Finished Jul 02 09:24:58 AM PDT 24
Peak memory 199984 kb
Host smart-5bcce8e9-598f-4eb1-b34d-8b55a36e187a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960078398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.960078398
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.4130900057
Short name T104
Test name
Test status
Simulation time 76376976841 ps
CPU time 890.29 seconds
Started Jul 02 09:24:24 AM PDT 24
Finished Jul 02 09:39:15 AM PDT 24
Peak memory 216512 kb
Host smart-93933226-c987-4e6e-a2a9-2454c638cba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130900057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.4130900057
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.843562695
Short name T384
Test name
Test status
Simulation time 876253928 ps
CPU time 3.28 seconds
Started Jul 02 09:24:22 AM PDT 24
Finished Jul 02 09:24:26 AM PDT 24
Peak memory 199500 kb
Host smart-58e20adf-7562-42c5-a723-c689039dda8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843562695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.843562695
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.665114408
Short name T798
Test name
Test status
Simulation time 43446151153 ps
CPU time 36.89 seconds
Started Jul 02 09:24:23 AM PDT 24
Finished Jul 02 09:25:00 AM PDT 24
Peak memory 199920 kb
Host smart-ce18e105-1376-4f00-a7cf-19e1f9d99785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665114408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.665114408
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.474086495
Short name T394
Test name
Test status
Simulation time 46274911 ps
CPU time 0.64 seconds
Started Jul 02 09:24:30 AM PDT 24
Finished Jul 02 09:24:31 AM PDT 24
Peak memory 195796 kb
Host smart-0e7c3667-e49e-4d73-88c0-bd488a44f7d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474086495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.474086495
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.831773795
Short name T488
Test name
Test status
Simulation time 155255537987 ps
CPU time 112.44 seconds
Started Jul 02 09:24:26 AM PDT 24
Finished Jul 02 09:26:20 AM PDT 24
Peak memory 199972 kb
Host smart-2d16ccf3-5f25-43ee-a208-298c3f2e9551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831773795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.831773795
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3144939326
Short name T793
Test name
Test status
Simulation time 35411105076 ps
CPU time 31.41 seconds
Started Jul 02 09:24:30 AM PDT 24
Finished Jul 02 09:25:02 AM PDT 24
Peak memory 199916 kb
Host smart-ef9e9d11-cdd2-4f3d-8973-2e605a35974b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144939326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3144939326
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3771305374
Short name T505
Test name
Test status
Simulation time 159175174097 ps
CPU time 346.36 seconds
Started Jul 02 09:24:25 AM PDT 24
Finished Jul 02 09:30:12 AM PDT 24
Peak memory 199892 kb
Host smart-524ed92f-6053-422c-8a9c-2fb2cb351202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771305374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3771305374
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4134530423
Short name T830
Test name
Test status
Simulation time 7287373234 ps
CPU time 6.79 seconds
Started Jul 02 09:24:27 AM PDT 24
Finished Jul 02 09:24:34 AM PDT 24
Peak memory 199912 kb
Host smart-b11f45cb-48ef-4499-8b86-92acb2091176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134530423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4134530423
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.335712021
Short name T685
Test name
Test status
Simulation time 15553957083 ps
CPU time 230.06 seconds
Started Jul 02 09:24:25 AM PDT 24
Finished Jul 02 09:28:16 AM PDT 24
Peak memory 199976 kb
Host smart-7d868099-d0ce-4cd7-bc18-cbf49890a341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335712021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.335712021
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2998237310
Short name T641
Test name
Test status
Simulation time 5275140626 ps
CPU time 35.98 seconds
Started Jul 02 09:24:27 AM PDT 24
Finished Jul 02 09:25:04 AM PDT 24
Peak memory 197844 kb
Host smart-e4c3c180-4be2-47c1-a1d0-8aa7bd12ef4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998237310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2998237310
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4128680220
Short name T310
Test name
Test status
Simulation time 14362508510 ps
CPU time 23.42 seconds
Started Jul 02 09:24:27 AM PDT 24
Finished Jul 02 09:24:51 AM PDT 24
Peak memory 199512 kb
Host smart-9b31e19c-4670-4c30-9d6a-42db0698cbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128680220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4128680220
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2428606623
Short name T608
Test name
Test status
Simulation time 30093945489 ps
CPU time 12.3 seconds
Started Jul 02 09:24:28 AM PDT 24
Finished Jul 02 09:24:41 AM PDT 24
Peak memory 195868 kb
Host smart-d3c49037-5231-4814-81b2-73d6662dab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428606623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2428606623
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3545499335
Short name T518
Test name
Test status
Simulation time 451806024 ps
CPU time 1.27 seconds
Started Jul 02 09:24:26 AM PDT 24
Finished Jul 02 09:24:28 AM PDT 24
Peak memory 199528 kb
Host smart-a14d3e11-9b84-433f-addf-f36719bba941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545499335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3545499335
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2582028551
Short name T530
Test name
Test status
Simulation time 994572816 ps
CPU time 3.34 seconds
Started Jul 02 09:24:30 AM PDT 24
Finished Jul 02 09:24:34 AM PDT 24
Peak memory 198796 kb
Host smart-d0f5ad60-3a2d-46a3-aaf9-dbff0d221f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582028551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2582028551
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2662989163
Short name T282
Test name
Test status
Simulation time 115561983341 ps
CPU time 192.85 seconds
Started Jul 02 09:24:26 AM PDT 24
Finished Jul 02 09:27:40 AM PDT 24
Peak memory 200000 kb
Host smart-bdd7ea0b-7640-43c7-974c-94135b0ac21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662989163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2662989163
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.242516928
Short name T566
Test name
Test status
Simulation time 101791763 ps
CPU time 0.57 seconds
Started Jul 02 09:24:39 AM PDT 24
Finished Jul 02 09:24:40 AM PDT 24
Peak memory 195344 kb
Host smart-e7ff494c-9957-42e6-b00c-47bcc74ff49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242516928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.242516928
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2045931271
Short name T613
Test name
Test status
Simulation time 150277031413 ps
CPU time 43.65 seconds
Started Jul 02 09:24:29 AM PDT 24
Finished Jul 02 09:25:14 AM PDT 24
Peak memory 199948 kb
Host smart-91ad5829-289e-45b3-ba4b-a2b4e49f59cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045931271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2045931271
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.2066747731
Short name T123
Test name
Test status
Simulation time 52570544238 ps
CPU time 54.19 seconds
Started Jul 02 09:24:30 AM PDT 24
Finished Jul 02 09:25:24 AM PDT 24
Peak memory 199964 kb
Host smart-6fb10956-2d01-4efb-9b68-9780f0b56249
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066747731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2066747731
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3598319683
Short name T420
Test name
Test status
Simulation time 61441223880 ps
CPU time 105 seconds
Started Jul 02 09:24:35 AM PDT 24
Finished Jul 02 09:26:20 AM PDT 24
Peak memory 199912 kb
Host smart-2a9e8d86-7a91-4af4-969e-f6ad966fe694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598319683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3598319683
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1049811476
Short name T959
Test name
Test status
Simulation time 5838670669 ps
CPU time 8.61 seconds
Started Jul 02 09:24:34 AM PDT 24
Finished Jul 02 09:24:43 AM PDT 24
Peak memory 199136 kb
Host smart-384132b4-3099-45b7-ae19-8c021be0109f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049811476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1049811476
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.826177470
Short name T992
Test name
Test status
Simulation time 21802577027 ps
CPU time 243.39 seconds
Started Jul 02 09:24:32 AM PDT 24
Finished Jul 02 09:28:36 AM PDT 24
Peak memory 199960 kb
Host smart-4daa6ef6-ea74-4ccd-a514-c40d5970b693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826177470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.826177470
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2232677257
Short name T435
Test name
Test status
Simulation time 2510298523 ps
CPU time 6.88 seconds
Started Jul 02 09:24:29 AM PDT 24
Finished Jul 02 09:24:36 AM PDT 24
Peak memory 199104 kb
Host smart-5112c109-e971-4b1d-b578-bffd5144085c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232677257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2232677257
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1399636840
Short name T519
Test name
Test status
Simulation time 73242587059 ps
CPU time 114.79 seconds
Started Jul 02 09:24:29 AM PDT 24
Finished Jul 02 09:26:25 AM PDT 24
Peak memory 200020 kb
Host smart-8d5f27d1-b0f7-4dfb-b661-61701825f02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399636840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1399636840
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1202325467
Short name T838
Test name
Test status
Simulation time 2282575848 ps
CPU time 2.67 seconds
Started Jul 02 09:24:31 AM PDT 24
Finished Jul 02 09:24:35 AM PDT 24
Peak memory 195624 kb
Host smart-da873db3-43b7-404b-bfd0-44ed61c7782a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202325467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1202325467
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1834368349
Short name T300
Test name
Test status
Simulation time 5833033409 ps
CPU time 13.11 seconds
Started Jul 02 09:24:32 AM PDT 24
Finished Jul 02 09:24:45 AM PDT 24
Peak memory 199908 kb
Host smart-3623245f-23ce-41f9-9949-bb98e77f2fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834368349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1834368349
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3659843693
Short name T351
Test name
Test status
Simulation time 188670004177 ps
CPU time 172.15 seconds
Started Jul 02 09:24:36 AM PDT 24
Finished Jul 02 09:27:29 AM PDT 24
Peak memory 200012 kb
Host smart-ca3393fd-0e4b-4393-8bbc-9c9db890500b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659843693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3659843693
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1084223751
Short name T339
Test name
Test status
Simulation time 149831094204 ps
CPU time 733.49 seconds
Started Jul 02 09:24:34 AM PDT 24
Finished Jul 02 09:36:48 AM PDT 24
Peak memory 216424 kb
Host smart-8b376494-452d-44bc-87be-6d3fda8b8084
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084223751 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1084223751
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.785121569
Short name T929
Test name
Test status
Simulation time 995068947 ps
CPU time 1.53 seconds
Started Jul 02 09:24:35 AM PDT 24
Finished Jul 02 09:24:37 AM PDT 24
Peak memory 198612 kb
Host smart-fc6fa8f1-d0e6-4adf-93d7-9f746b27d7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785121569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.785121569
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2859063278
Short name T1034
Test name
Test status
Simulation time 143993514992 ps
CPU time 11.33 seconds
Started Jul 02 09:24:29 AM PDT 24
Finished Jul 02 09:24:41 AM PDT 24
Peak memory 196596 kb
Host smart-b073809c-8107-4fa0-b03c-a0499fc3dc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859063278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2859063278
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.4047832099
Short name T379
Test name
Test status
Simulation time 47459568 ps
CPU time 0.61 seconds
Started Jul 02 09:24:38 AM PDT 24
Finished Jul 02 09:24:39 AM PDT 24
Peak memory 195800 kb
Host smart-f8d27eca-1d41-463a-8f0c-566b8c8f30e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047832099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.4047832099
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1906785092
Short name T828
Test name
Test status
Simulation time 40145299719 ps
CPU time 7.2 seconds
Started Jul 02 09:24:34 AM PDT 24
Finished Jul 02 09:24:41 AM PDT 24
Peak memory 199944 kb
Host smart-fdbfa54f-b87b-4049-b8ef-fbef99fc8399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906785092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1906785092
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3306192346
Short name T1008
Test name
Test status
Simulation time 65998122569 ps
CPU time 40.34 seconds
Started Jul 02 09:24:34 AM PDT 24
Finished Jul 02 09:25:15 AM PDT 24
Peak memory 199972 kb
Host smart-864c0b54-01eb-442a-9945-88418bb74bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306192346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3306192346
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.600313972
Short name T747
Test name
Test status
Simulation time 11547487535 ps
CPU time 3.91 seconds
Started Jul 02 09:24:38 AM PDT 24
Finished Jul 02 09:24:42 AM PDT 24
Peak memory 200012 kb
Host smart-03492860-e1b2-4214-bded-e2a8d99f3393
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600313972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.600313972
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2754867433
Short name T546
Test name
Test status
Simulation time 64741282003 ps
CPU time 241.73 seconds
Started Jul 02 09:24:36 AM PDT 24
Finished Jul 02 09:28:38 AM PDT 24
Peak memory 199892 kb
Host smart-b7bf2e4b-2056-4c06-ba1c-ee63e853884c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754867433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2754867433
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3762976220
Short name T757
Test name
Test status
Simulation time 4264521057 ps
CPU time 10.8 seconds
Started Jul 02 09:24:42 AM PDT 24
Finished Jul 02 09:24:54 AM PDT 24
Peak memory 199160 kb
Host smart-ebd7276d-9d3f-4f54-8f1d-d3c03b9bec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762976220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3762976220
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3650611628
Short name T939
Test name
Test status
Simulation time 184508796084 ps
CPU time 53.61 seconds
Started Jul 02 09:24:38 AM PDT 24
Finished Jul 02 09:25:32 AM PDT 24
Peak memory 200072 kb
Host smart-ae756160-9632-4a1f-b6c9-565087b3898a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650611628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3650611628
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.579135164
Short name T45
Test name
Test status
Simulation time 8748157179 ps
CPU time 223.77 seconds
Started Jul 02 09:24:38 AM PDT 24
Finished Jul 02 09:28:22 AM PDT 24
Peak memory 199992 kb
Host smart-79a3f25a-c2eb-42c5-adc7-d1f23766b872
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579135164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.579135164
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3712400281
Short name T1059
Test name
Test status
Simulation time 5303265444 ps
CPU time 44.49 seconds
Started Jul 02 09:24:37 AM PDT 24
Finished Jul 02 09:25:22 AM PDT 24
Peak memory 199076 kb
Host smart-d11a6f27-157e-4bd9-aade-7d280b661c21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712400281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3712400281
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.4172586987
Short name T541
Test name
Test status
Simulation time 176296835663 ps
CPU time 75.85 seconds
Started Jul 02 09:24:37 AM PDT 24
Finished Jul 02 09:25:53 AM PDT 24
Peak memory 199856 kb
Host smart-f80da184-fdb8-43b5-833b-89ae0bd204d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172586987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.4172586987
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.774000317
Short name T986
Test name
Test status
Simulation time 1761398741 ps
CPU time 1.24 seconds
Started Jul 02 09:24:37 AM PDT 24
Finished Jul 02 09:24:39 AM PDT 24
Peak memory 195320 kb
Host smart-cafa3924-72c3-4686-a72d-3ff57b34e36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774000317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.774000317
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3906786214
Short name T477
Test name
Test status
Simulation time 656230700 ps
CPU time 2.17 seconds
Started Jul 02 09:24:34 AM PDT 24
Finished Jul 02 09:24:37 AM PDT 24
Peak memory 199564 kb
Host smart-9473bbe5-85d9-49c4-85cc-228ba0d1e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906786214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3906786214
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2019488827
Short name T863
Test name
Test status
Simulation time 32188787614 ps
CPU time 22.9 seconds
Started Jul 02 09:24:38 AM PDT 24
Finished Jul 02 09:25:01 AM PDT 24
Peak memory 199904 kb
Host smart-d9e2ae99-7447-444d-bcb8-1eefd494f3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019488827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2019488827
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2844261017
Short name T16
Test name
Test status
Simulation time 40069790328 ps
CPU time 225.18 seconds
Started Jul 02 09:24:38 AM PDT 24
Finished Jul 02 09:28:24 AM PDT 24
Peak memory 215828 kb
Host smart-4f399819-e32b-4ae1-b48f-3fef9f823c3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844261017 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2844261017
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3908351175
Short name T976
Test name
Test status
Simulation time 13458938697 ps
CPU time 19.51 seconds
Started Jul 02 09:24:42 AM PDT 24
Finished Jul 02 09:25:03 AM PDT 24
Peak memory 199948 kb
Host smart-4bdce02a-2bf1-4c81-b802-f28fd626e095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908351175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3908351175
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1138689490
Short name T807
Test name
Test status
Simulation time 10324268607 ps
CPU time 16.5 seconds
Started Jul 02 09:24:36 AM PDT 24
Finished Jul 02 09:24:53 AM PDT 24
Peak memory 199964 kb
Host smart-f477980a-a674-49d6-b529-ae764f20f94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138689490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1138689490
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.969811697
Short name T581
Test name
Test status
Simulation time 13108910 ps
CPU time 0.56 seconds
Started Jul 02 09:24:42 AM PDT 24
Finished Jul 02 09:24:44 AM PDT 24
Peak memory 194292 kb
Host smart-fac711d4-ffc4-4642-8516-2a4ec5cecba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969811697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.969811697
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2996269824
Short name T102
Test name
Test status
Simulation time 38783314699 ps
CPU time 76.22 seconds
Started Jul 02 09:24:42 AM PDT 24
Finished Jul 02 09:25:59 AM PDT 24
Peak memory 199936 kb
Host smart-f2115ca1-be9d-4381-8669-0912b9af1af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996269824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2996269824
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2314051994
Short name T842
Test name
Test status
Simulation time 65065645714 ps
CPU time 26.14 seconds
Started Jul 02 09:24:42 AM PDT 24
Finished Jul 02 09:25:08 AM PDT 24
Peak memory 199940 kb
Host smart-e296fb8f-ef44-46cb-accf-77b516b93060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314051994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2314051994
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4030681753
Short name T216
Test name
Test status
Simulation time 115843593349 ps
CPU time 20.24 seconds
Started Jul 02 09:24:42 AM PDT 24
Finished Jul 02 09:25:03 AM PDT 24
Peak memory 199736 kb
Host smart-7133ddf9-bb65-40f7-a80d-df870e4437c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030681753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4030681753
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.4053485856
Short name T1087
Test name
Test status
Simulation time 23039863916 ps
CPU time 36.72 seconds
Started Jul 02 09:24:39 AM PDT 24
Finished Jul 02 09:25:16 AM PDT 24
Peak memory 199876 kb
Host smart-50ae4b25-e2aa-4597-b347-ed6c8391a90a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053485856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4053485856
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4228398787
Short name T912
Test name
Test status
Simulation time 107586703054 ps
CPU time 142.25 seconds
Started Jul 02 09:24:41 AM PDT 24
Finished Jul 02 09:27:04 AM PDT 24
Peak memory 199896 kb
Host smart-16e99580-b18d-4f0c-a8e3-12e340df49a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228398787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4228398787
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1379194401
Short name T550
Test name
Test status
Simulation time 9791176439 ps
CPU time 16.68 seconds
Started Jul 02 09:24:43 AM PDT 24
Finished Jul 02 09:25:00 AM PDT 24
Peak memory 199456 kb
Host smart-72fb950c-c0c1-4543-9b71-06917ea7b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379194401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1379194401
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.3717334613
Short name T557
Test name
Test status
Simulation time 14332681107 ps
CPU time 193.27 seconds
Started Jul 02 09:24:40 AM PDT 24
Finished Jul 02 09:27:53 AM PDT 24
Peak memory 199888 kb
Host smart-86259561-bc2d-481e-94f1-ed07c2985f60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3717334613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3717334613
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.607102798
Short name T635
Test name
Test status
Simulation time 2748088492 ps
CPU time 19.06 seconds
Started Jul 02 09:24:43 AM PDT 24
Finished Jul 02 09:25:03 AM PDT 24
Peak memory 198280 kb
Host smart-5abd418f-837f-40fc-a2b6-1b93e13610b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607102798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.607102798
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.308197960
Short name T1042
Test name
Test status
Simulation time 9085409325 ps
CPU time 16.07 seconds
Started Jul 02 09:24:41 AM PDT 24
Finished Jul 02 09:24:57 AM PDT 24
Peak memory 199916 kb
Host smart-db58f087-baea-4641-b47b-0e0b6fb41362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308197960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.308197960
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3874903387
Short name T994
Test name
Test status
Simulation time 1473391241 ps
CPU time 1.86 seconds
Started Jul 02 09:24:44 AM PDT 24
Finished Jul 02 09:24:46 AM PDT 24
Peak memory 195560 kb
Host smart-b59a33cd-5ba7-456d-997c-d94e60fdd3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874903387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3874903387
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.114759137
Short name T414
Test name
Test status
Simulation time 279718426 ps
CPU time 0.97 seconds
Started Jul 02 09:24:41 AM PDT 24
Finished Jul 02 09:24:42 AM PDT 24
Peak memory 198528 kb
Host smart-0ffdbb0b-1d58-45ed-9b26-be7eeffbbbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114759137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.114759137
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3864287175
Short name T1010
Test name
Test status
Simulation time 176829526785 ps
CPU time 284.88 seconds
Started Jul 02 09:24:42 AM PDT 24
Finished Jul 02 09:29:28 AM PDT 24
Peak memory 199892 kb
Host smart-e415dcf4-dca6-47c7-8d60-60393f3a0204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864287175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3864287175
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1375867042
Short name T693
Test name
Test status
Simulation time 1770743954 ps
CPU time 1.78 seconds
Started Jul 02 09:24:41 AM PDT 24
Finished Jul 02 09:24:44 AM PDT 24
Peak memory 199140 kb
Host smart-fe53ae4f-3317-4e16-a143-6fa24a0ae544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375867042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1375867042
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1009657351
Short name T767
Test name
Test status
Simulation time 360130668278 ps
CPU time 160.89 seconds
Started Jul 02 09:24:40 AM PDT 24
Finished Jul 02 09:27:21 AM PDT 24
Peak memory 199952 kb
Host smart-53e9ff6f-2ff8-468b-b49e-104d469ba673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009657351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1009657351
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3473039992
Short name T464
Test name
Test status
Simulation time 25422131 ps
CPU time 0.57 seconds
Started Jul 02 09:24:48 AM PDT 24
Finished Jul 02 09:24:49 AM PDT 24
Peak memory 195596 kb
Host smart-08f347d3-16ad-42e7-b2e6-5a0de909a19a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473039992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3473039992
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.340349891
Short name T134
Test name
Test status
Simulation time 39953452780 ps
CPU time 62.32 seconds
Started Jul 02 09:24:41 AM PDT 24
Finished Jul 02 09:25:44 AM PDT 24
Peak memory 199980 kb
Host smart-1962054f-3ee3-4167-b216-322afb65f377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340349891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.340349891
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3113402583
Short name T933
Test name
Test status
Simulation time 197781314927 ps
CPU time 400.33 seconds
Started Jul 02 09:24:42 AM PDT 24
Finished Jul 02 09:31:23 AM PDT 24
Peak memory 199988 kb
Host smart-314aa1d6-aeaf-4d8e-95a2-3185c2aff236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113402583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3113402583
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3307953611
Short name T483
Test name
Test status
Simulation time 98667234984 ps
CPU time 65.42 seconds
Started Jul 02 09:24:44 AM PDT 24
Finished Jul 02 09:25:50 AM PDT 24
Peak memory 199960 kb
Host smart-db49d2b7-22e6-428f-a933-d787e88d460b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307953611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3307953611
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1657467791
Short name T1029
Test name
Test status
Simulation time 72906725780 ps
CPU time 102.02 seconds
Started Jul 02 09:24:46 AM PDT 24
Finished Jul 02 09:26:29 AM PDT 24
Peak memory 199940 kb
Host smart-da14cfb9-7a93-47c3-bf1e-55cf0b167a4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657467791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1657467791
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.466542535
Short name T622
Test name
Test status
Simulation time 295007486383 ps
CPU time 370.94 seconds
Started Jul 02 09:24:46 AM PDT 24
Finished Jul 02 09:30:58 AM PDT 24
Peak memory 199952 kb
Host smart-e9284b2f-ce27-4f40-9b8c-4cf3d5dabb64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466542535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.466542535
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2321795341
Short name T413
Test name
Test status
Simulation time 3377772539 ps
CPU time 4.92 seconds
Started Jul 02 09:24:46 AM PDT 24
Finished Jul 02 09:24:51 AM PDT 24
Peak memory 199988 kb
Host smart-807e7c70-55c2-4def-b060-40c514d0bcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321795341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2321795341
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.504039983
Short name T68
Test name
Test status
Simulation time 1311567592 ps
CPU time 1.07 seconds
Started Jul 02 09:24:47 AM PDT 24
Finished Jul 02 09:24:49 AM PDT 24
Peak memory 198060 kb
Host smart-7e880ab6-0d7e-4c80-af50-5ecb11214ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504039983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.504039983
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1195147503
Short name T387
Test name
Test status
Simulation time 2909767307 ps
CPU time 168.73 seconds
Started Jul 02 09:24:48 AM PDT 24
Finished Jul 02 09:27:37 AM PDT 24
Peak memory 199944 kb
Host smart-421d0d6a-3544-4fad-ace8-3fea50876819
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1195147503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1195147503
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1999537444
Short name T620
Test name
Test status
Simulation time 1605562757 ps
CPU time 2.66 seconds
Started Jul 02 09:24:42 AM PDT 24
Finished Jul 02 09:24:46 AM PDT 24
Peak memory 197976 kb
Host smart-968731f9-996a-4924-b5d7-3d41955a559e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1999537444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1999537444
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3121587485
Short name T597
Test name
Test status
Simulation time 123406690619 ps
CPU time 181.38 seconds
Started Jul 02 09:24:49 AM PDT 24
Finished Jul 02 09:27:51 AM PDT 24
Peak memory 199876 kb
Host smart-0b553d31-359a-41ae-9632-d7d92b788073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121587485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3121587485
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.513372572
Short name T731
Test name
Test status
Simulation time 28858386128 ps
CPU time 10.85 seconds
Started Jul 02 09:24:46 AM PDT 24
Finished Jul 02 09:24:57 AM PDT 24
Peak memory 196196 kb
Host smart-fba0e9c8-95ce-4757-9208-48684ef624ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513372572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.513372572
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.141991214
Short name T1027
Test name
Test status
Simulation time 430845453 ps
CPU time 2.02 seconds
Started Jul 02 09:24:41 AM PDT 24
Finished Jul 02 09:24:43 AM PDT 24
Peak memory 199584 kb
Host smart-d3544f13-827f-4c65-b3de-5e18ae4688e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141991214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.141991214
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.542412475
Short name T428
Test name
Test status
Simulation time 13242167274 ps
CPU time 14.56 seconds
Started Jul 02 09:24:46 AM PDT 24
Finished Jul 02 09:25:02 AM PDT 24
Peak memory 199964 kb
Host smart-687d9a83-7dbc-4fd9-b266-d834a31174d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542412475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.542412475
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2379289675
Short name T485
Test name
Test status
Simulation time 8257337410 ps
CPU time 12.17 seconds
Started Jul 02 09:24:43 AM PDT 24
Finished Jul 02 09:24:56 AM PDT 24
Peak memory 199928 kb
Host smart-71fe670d-50fa-48c6-ab4e-85fb27c62424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379289675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2379289675
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1226751490
Short name T25
Test name
Test status
Simulation time 31552629 ps
CPU time 0.55 seconds
Started Jul 02 09:24:49 AM PDT 24
Finished Jul 02 09:24:50 AM PDT 24
Peak memory 195580 kb
Host smart-4f0bd2e2-132c-4f80-97d4-d1e7d1f866ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226751490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1226751490
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3295111914
Short name T845
Test name
Test status
Simulation time 75096420824 ps
CPU time 51.65 seconds
Started Jul 02 09:24:49 AM PDT 24
Finished Jul 02 09:25:41 AM PDT 24
Peak memory 199944 kb
Host smart-e87d02a7-45f3-4d4e-8b86-df518cb39eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295111914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3295111914
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.251441410
Short name T176
Test name
Test status
Simulation time 12123518053 ps
CPU time 22.17 seconds
Started Jul 02 09:24:47 AM PDT 24
Finished Jul 02 09:25:10 AM PDT 24
Peak memory 199896 kb
Host smart-e9f8942e-2532-46df-9b2e-cc3d39aa5331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251441410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.251441410
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2661976501
Short name T467
Test name
Test status
Simulation time 31942176994 ps
CPU time 23.04 seconds
Started Jul 02 09:24:46 AM PDT 24
Finished Jul 02 09:25:10 AM PDT 24
Peak memory 199912 kb
Host smart-2622ae88-a995-4169-af35-5a004121af3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661976501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2661976501
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.460838684
Short name T72
Test name
Test status
Simulation time 232730602309 ps
CPU time 342.95 seconds
Started Jul 02 09:24:47 AM PDT 24
Finished Jul 02 09:30:31 AM PDT 24
Peak memory 197808 kb
Host smart-47153397-e940-42d7-a16a-4432db06d0af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460838684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.460838684
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1390836469
Short name T945
Test name
Test status
Simulation time 46491229089 ps
CPU time 354 seconds
Started Jul 02 09:24:48 AM PDT 24
Finished Jul 02 09:30:42 AM PDT 24
Peak memory 199932 kb
Host smart-08a52212-5126-45ff-bbc3-64d61585fe88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390836469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1390836469
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1620490454
Short name T393
Test name
Test status
Simulation time 6116375978 ps
CPU time 6.22 seconds
Started Jul 02 09:24:50 AM PDT 24
Finished Jul 02 09:24:57 AM PDT 24
Peak memory 199640 kb
Host smart-8f122965-6432-4a86-8708-1d12e85c459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620490454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1620490454
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.1300598425
Short name T991
Test name
Test status
Simulation time 20826119660 ps
CPU time 68.91 seconds
Started Jul 02 09:24:49 AM PDT 24
Finished Jul 02 09:25:58 AM PDT 24
Peak memory 199924 kb
Host smart-01053b8a-e620-473d-a55c-11c68bd4988e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300598425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1300598425
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1192811632
Short name T392
Test name
Test status
Simulation time 5103901048 ps
CPU time 39.65 seconds
Started Jul 02 09:24:49 AM PDT 24
Finished Jul 02 09:25:29 AM PDT 24
Peak memory 198896 kb
Host smart-81430fed-84f2-494c-b858-79e6bd7558a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192811632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1192811632
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2425891477
Short name T190
Test name
Test status
Simulation time 61101976223 ps
CPU time 23.6 seconds
Started Jul 02 09:24:47 AM PDT 24
Finished Jul 02 09:25:11 AM PDT 24
Peak memory 199892 kb
Host smart-8de774ce-991e-428f-a3d1-117da696238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425891477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2425891477
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3136040502
Short name T975
Test name
Test status
Simulation time 4049420717 ps
CPU time 2.12 seconds
Started Jul 02 09:24:50 AM PDT 24
Finished Jul 02 09:24:53 AM PDT 24
Peak memory 196168 kb
Host smart-e1da3964-cfe3-415a-972d-10259f693091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136040502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3136040502
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3851128908
Short name T292
Test name
Test status
Simulation time 103364106 ps
CPU time 0.98 seconds
Started Jul 02 09:24:51 AM PDT 24
Finished Jul 02 09:24:52 AM PDT 24
Peak memory 198672 kb
Host smart-c8e94dda-f40b-47e6-b3b3-723eb4ca98b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851128908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3851128908
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2974181080
Short name T212
Test name
Test status
Simulation time 199687661313 ps
CPU time 282.49 seconds
Started Jul 02 09:24:53 AM PDT 24
Finished Jul 02 09:29:36 AM PDT 24
Peak memory 199988 kb
Host smart-66c27184-e065-4f17-9de7-111b0002b7e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974181080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2974181080
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.457581720
Short name T507
Test name
Test status
Simulation time 551528999 ps
CPU time 1.56 seconds
Started Jul 02 09:24:47 AM PDT 24
Finished Jul 02 09:24:49 AM PDT 24
Peak memory 196880 kb
Host smart-63c00241-e041-4aa7-88dd-cac58628127e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457581720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.457581720
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1430701341
Short name T302
Test name
Test status
Simulation time 32870168186 ps
CPU time 67.15 seconds
Started Jul 02 09:24:50 AM PDT 24
Finished Jul 02 09:25:58 AM PDT 24
Peak memory 199904 kb
Host smart-b80418e8-d035-4d46-a5e9-6f391f0f050a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430701341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1430701341
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3389316216
Short name T368
Test name
Test status
Simulation time 11406606 ps
CPU time 0.57 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:23:08 AM PDT 24
Peak memory 194256 kb
Host smart-1d78bc0f-4b61-43f5-960a-f1bc5443c906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389316216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3389316216
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2944755107
Short name T463
Test name
Test status
Simulation time 110281429453 ps
CPU time 130.1 seconds
Started Jul 02 09:23:02 AM PDT 24
Finished Jul 02 09:25:13 AM PDT 24
Peak memory 199948 kb
Host smart-7459ec9c-043f-4169-ae22-70ecf2b974bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944755107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2944755107
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3355381555
Short name T493
Test name
Test status
Simulation time 109756995419 ps
CPU time 168.8 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:25:56 AM PDT 24
Peak memory 199980 kb
Host smart-0eaf3a1e-2a43-4c81-b44d-5e9f7b14131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355381555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3355381555
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1178532968
Short name T879
Test name
Test status
Simulation time 103456266686 ps
CPU time 153.83 seconds
Started Jul 02 09:23:05 AM PDT 24
Finished Jul 02 09:25:41 AM PDT 24
Peak memory 199924 kb
Host smart-579edec4-7141-4447-968d-0ec2859fc5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178532968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1178532968
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2898443590
Short name T343
Test name
Test status
Simulation time 6854583868 ps
CPU time 5.73 seconds
Started Jul 02 09:23:05 AM PDT 24
Finished Jul 02 09:23:11 AM PDT 24
Peak memory 200196 kb
Host smart-4421a22d-7395-4ef4-b181-bcb4b16c6221
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898443590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2898443590
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.892267957
Short name T1048
Test name
Test status
Simulation time 135517433588 ps
CPU time 368.02 seconds
Started Jul 02 09:23:11 AM PDT 24
Finished Jul 02 09:29:20 AM PDT 24
Peak memory 199956 kb
Host smart-85b2f716-97b9-486d-9862-774fb7f894e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=892267957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.892267957
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2210807956
Short name T444
Test name
Test status
Simulation time 3884314540 ps
CPU time 2.56 seconds
Started Jul 02 09:22:53 AM PDT 24
Finished Jul 02 09:22:55 AM PDT 24
Peak memory 198684 kb
Host smart-b9d82970-7e2d-43da-98ec-3e45e4483d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210807956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2210807956
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.3513154687
Short name T885
Test name
Test status
Simulation time 26261286098 ps
CPU time 167.64 seconds
Started Jul 02 09:23:05 AM PDT 24
Finished Jul 02 09:25:55 AM PDT 24
Peak memory 199880 kb
Host smart-121eb746-94fc-494c-9aa6-955b9bc98f89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513154687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3513154687
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.960750113
Short name T364
Test name
Test status
Simulation time 7188702383 ps
CPU time 3.92 seconds
Started Jul 02 09:23:02 AM PDT 24
Finished Jul 02 09:23:07 AM PDT 24
Peak memory 199352 kb
Host smart-a350e22e-7fc8-4e28-ac08-5a1b2bbca52f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960750113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.960750113
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2228902049
Short name T417
Test name
Test status
Simulation time 147150189457 ps
CPU time 128.25 seconds
Started Jul 02 09:23:05 AM PDT 24
Finished Jul 02 09:25:15 AM PDT 24
Peak memory 199752 kb
Host smart-49d3062c-01a7-42f7-a54c-90dc0cd54086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228902049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2228902049
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3554314644
Short name T1061
Test name
Test status
Simulation time 32859438536 ps
CPU time 12.6 seconds
Started Jul 02 09:22:59 AM PDT 24
Finished Jul 02 09:23:12 AM PDT 24
Peak memory 196024 kb
Host smart-6e4e28ab-80c7-44d5-bafe-c4e798ab4e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554314644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3554314644
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.885941270
Short name T26
Test name
Test status
Simulation time 183364196 ps
CPU time 0.88 seconds
Started Jul 02 09:22:53 AM PDT 24
Finished Jul 02 09:22:54 AM PDT 24
Peak memory 218280 kb
Host smart-63a0523e-b3c9-4853-97ab-80c382c4c304
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885941270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.885941270
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2232941453
Short name T50
Test name
Test status
Simulation time 475372907 ps
CPU time 2.4 seconds
Started Jul 02 09:23:04 AM PDT 24
Finished Jul 02 09:23:07 AM PDT 24
Peak memory 198184 kb
Host smart-dc249dbe-7720-42e9-9ba9-f1397ef39f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232941453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2232941453
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3673965305
Short name T169
Test name
Test status
Simulation time 184333682944 ps
CPU time 244.18 seconds
Started Jul 02 09:23:08 AM PDT 24
Finished Jul 02 09:27:14 AM PDT 24
Peak memory 216504 kb
Host smart-45e86639-c8fc-4832-970c-d6b2d78fdb8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673965305 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3673965305
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1569538239
Short name T502
Test name
Test status
Simulation time 984688832 ps
CPU time 2.98 seconds
Started Jul 02 09:23:04 AM PDT 24
Finished Jul 02 09:23:08 AM PDT 24
Peak memory 198592 kb
Host smart-679a08f7-cb73-42e9-ad43-6c1575251641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569538239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1569538239
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2656381554
Short name T662
Test name
Test status
Simulation time 136340475592 ps
CPU time 31.31 seconds
Started Jul 02 09:23:04 AM PDT 24
Finished Jul 02 09:23:36 AM PDT 24
Peak memory 199808 kb
Host smart-d1e7779e-dad7-42fc-8148-46e5099b6d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656381554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2656381554
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.360519978
Short name T1028
Test name
Test status
Simulation time 10973668 ps
CPU time 0.57 seconds
Started Jul 02 09:24:54 AM PDT 24
Finished Jul 02 09:24:55 AM PDT 24
Peak memory 194256 kb
Host smart-bc7feaed-5191-4158-a247-4dce8a9d03e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360519978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.360519978
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3894038894
Short name T1019
Test name
Test status
Simulation time 121150893164 ps
CPU time 271.6 seconds
Started Jul 02 09:24:51 AM PDT 24
Finished Jul 02 09:29:23 AM PDT 24
Peak memory 199852 kb
Host smart-058ba7da-fa34-4220-8614-bdbbda411b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894038894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3894038894
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1016083955
Short name T926
Test name
Test status
Simulation time 26109406941 ps
CPU time 8.62 seconds
Started Jul 02 09:24:55 AM PDT 24
Finished Jul 02 09:25:05 AM PDT 24
Peak memory 199984 kb
Host smart-a581e06b-9b2f-471a-976d-50f59581bc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016083955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1016083955
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2198831675
Short name T426
Test name
Test status
Simulation time 29819112723 ps
CPU time 29.12 seconds
Started Jul 02 09:24:51 AM PDT 24
Finished Jul 02 09:25:21 AM PDT 24
Peak memory 199776 kb
Host smart-ef2ca3f5-3ff8-4b14-ad22-11c55922b1a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198831675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2198831675
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.755633984
Short name T1086
Test name
Test status
Simulation time 119147255066 ps
CPU time 774.9 seconds
Started Jul 02 09:24:53 AM PDT 24
Finished Jul 02 09:37:49 AM PDT 24
Peak memory 199912 kb
Host smart-7a93bb26-c785-477c-964e-824cae09bdaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755633984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.755633984
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3389537391
Short name T551
Test name
Test status
Simulation time 7602057130 ps
CPU time 6.52 seconds
Started Jul 02 09:24:55 AM PDT 24
Finished Jul 02 09:25:02 AM PDT 24
Peak memory 200008 kb
Host smart-0b395da7-54a0-45d1-9f14-8bb57b20b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389537391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3389537391
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.2161434931
Short name T872
Test name
Test status
Simulation time 7546863046 ps
CPU time 337.34 seconds
Started Jul 02 09:24:56 AM PDT 24
Finished Jul 02 09:30:34 AM PDT 24
Peak memory 199924 kb
Host smart-dff66d2b-0b4c-4bd0-aa5a-f67b6591cfe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161434931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2161434931
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3031922081
Short name T1081
Test name
Test status
Simulation time 3893307699 ps
CPU time 6.29 seconds
Started Jul 02 09:24:49 AM PDT 24
Finished Jul 02 09:24:56 AM PDT 24
Peak memory 198916 kb
Host smart-9f4fa1d0-dfe1-4e35-af67-8087bc766006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031922081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3031922081
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.4215502712
Short name T709
Test name
Test status
Simulation time 36963695523 ps
CPU time 15.41 seconds
Started Jul 02 09:24:51 AM PDT 24
Finished Jul 02 09:25:07 AM PDT 24
Peak memory 199968 kb
Host smart-93087add-d3fa-4c05-8207-7fe12b3206c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215502712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.4215502712
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1431954323
Short name T1040
Test name
Test status
Simulation time 3063651311 ps
CPU time 2.86 seconds
Started Jul 02 09:24:51 AM PDT 24
Finished Jul 02 09:24:54 AM PDT 24
Peak memory 195924 kb
Host smart-f9d96f58-5564-4503-a718-d68036efa913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431954323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1431954323
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2430720113
Short name T629
Test name
Test status
Simulation time 309661489 ps
CPU time 2.13 seconds
Started Jul 02 09:24:50 AM PDT 24
Finished Jul 02 09:24:53 AM PDT 24
Peak memory 198940 kb
Host smart-4ab40f61-ad28-409c-9825-04b5e38f8dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430720113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2430720113
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3602318722
Short name T53
Test name
Test status
Simulation time 42566366283 ps
CPU time 453.29 seconds
Started Jul 02 09:24:55 AM PDT 24
Finished Jul 02 09:32:29 AM PDT 24
Peak memory 216556 kb
Host smart-f9984aef-d08d-4bca-bc39-4cdc20c2d7f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602318722 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3602318722
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2847144174
Short name T575
Test name
Test status
Simulation time 288161000 ps
CPU time 1.1 seconds
Started Jul 02 09:24:55 AM PDT 24
Finished Jul 02 09:24:56 AM PDT 24
Peak memory 196584 kb
Host smart-e876c014-79e2-4cc8-ac4d-a8979001a6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847144174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2847144174
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.76897411
Short name T325
Test name
Test status
Simulation time 37719216515 ps
CPU time 71.71 seconds
Started Jul 02 09:24:50 AM PDT 24
Finished Jul 02 09:26:02 AM PDT 24
Peak memory 199904 kb
Host smart-5e8ec2ce-590c-4731-a434-64cd57d2d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76897411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.76897411
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1127009224
Short name T851
Test name
Test status
Simulation time 31402896 ps
CPU time 0.57 seconds
Started Jul 02 09:24:57 AM PDT 24
Finished Jul 02 09:24:58 AM PDT 24
Peak memory 195292 kb
Host smart-9e783c10-074c-4a93-94f1-a01aea70a387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127009224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1127009224
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2771722864
Short name T319
Test name
Test status
Simulation time 43300952923 ps
CPU time 66.2 seconds
Started Jul 02 09:24:53 AM PDT 24
Finished Jul 02 09:26:00 AM PDT 24
Peak memory 199904 kb
Host smart-5cc77a4e-8bcc-4b64-9925-89d8bdb419e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771722864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2771722864
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.33124742
Short name T1016
Test name
Test status
Simulation time 12639121447 ps
CPU time 21.06 seconds
Started Jul 02 09:24:55 AM PDT 24
Finished Jul 02 09:25:17 AM PDT 24
Peak memory 200096 kb
Host smart-32f7c12b-ac84-460c-b818-d9ad403e0291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33124742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.33124742
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1521716066
Short name T585
Test name
Test status
Simulation time 29562729387 ps
CPU time 81.49 seconds
Started Jul 02 09:24:56 AM PDT 24
Finished Jul 02 09:26:18 AM PDT 24
Peak memory 199960 kb
Host smart-5e4bd72b-5441-409a-a242-e7d3e3ffbfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521716066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1521716066
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1321926440
Short name T884
Test name
Test status
Simulation time 186417991524 ps
CPU time 238.04 seconds
Started Jul 02 09:24:54 AM PDT 24
Finished Jul 02 09:28:53 AM PDT 24
Peak memory 199888 kb
Host smart-121b962d-5b5e-4e0b-b740-fd4ebb8aa537
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321926440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1321926440
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.334874100
Short name T847
Test name
Test status
Simulation time 27002722876 ps
CPU time 179.24 seconds
Started Jul 02 09:24:59 AM PDT 24
Finished Jul 02 09:27:58 AM PDT 24
Peak memory 199944 kb
Host smart-e57db885-480f-40be-8cd0-35d80ab1cc95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=334874100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.334874100
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.521754143
Short name T628
Test name
Test status
Simulation time 955836805 ps
CPU time 1.31 seconds
Started Jul 02 09:25:00 AM PDT 24
Finished Jul 02 09:25:02 AM PDT 24
Peak memory 195384 kb
Host smart-3e92f73b-73ec-403d-9510-18681be7d455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521754143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.521754143
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.4260698465
Short name T322
Test name
Test status
Simulation time 4265016045 ps
CPU time 204.34 seconds
Started Jul 02 09:24:58 AM PDT 24
Finished Jul 02 09:28:23 AM PDT 24
Peak memory 200008 kb
Host smart-920073cb-ff75-4d8e-9c22-89dbc0900a22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260698465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.4260698465
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.374344457
Short name T360
Test name
Test status
Simulation time 7018696711 ps
CPU time 27.14 seconds
Started Jul 02 09:24:55 AM PDT 24
Finished Jul 02 09:25:23 AM PDT 24
Peak memory 198148 kb
Host smart-7ce37cbb-abe0-45c4-90fa-1e038317bf7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374344457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.374344457
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.724370981
Short name T724
Test name
Test status
Simulation time 176764608456 ps
CPU time 48.54 seconds
Started Jul 02 09:25:00 AM PDT 24
Finished Jul 02 09:25:50 AM PDT 24
Peak memory 199968 kb
Host smart-a553fb0b-cd46-42ea-97ef-f206a13f1fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724370981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.724370981
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1016197328
Short name T669
Test name
Test status
Simulation time 34292489294 ps
CPU time 46.63 seconds
Started Jul 02 09:24:58 AM PDT 24
Finished Jul 02 09:25:45 AM PDT 24
Peak memory 196704 kb
Host smart-4ac90744-6605-480f-946a-df375ba8571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016197328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1016197328
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2255954830
Short name T1038
Test name
Test status
Simulation time 6061673910 ps
CPU time 8.34 seconds
Started Jul 02 09:24:54 AM PDT 24
Finished Jul 02 09:25:03 AM PDT 24
Peak memory 199944 kb
Host smart-855c310b-b248-47da-a682-c0cc34a25a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255954830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2255954830
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1307082790
Short name T305
Test name
Test status
Simulation time 737313397 ps
CPU time 2.2 seconds
Started Jul 02 09:24:59 AM PDT 24
Finished Jul 02 09:25:02 AM PDT 24
Peak memory 199120 kb
Host smart-f92489c1-42e6-40ce-ab31-67d9d53f4bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307082790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1307082790
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1920604176
Short name T900
Test name
Test status
Simulation time 70232269174 ps
CPU time 36.28 seconds
Started Jul 02 09:24:53 AM PDT 24
Finished Jul 02 09:25:29 AM PDT 24
Peak memory 199976 kb
Host smart-78619e13-7673-4b86-8298-47b097dff388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920604176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1920604176
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1455976524
Short name T952
Test name
Test status
Simulation time 14087386 ps
CPU time 0.58 seconds
Started Jul 02 09:25:05 AM PDT 24
Finished Jul 02 09:25:06 AM PDT 24
Peak memory 195316 kb
Host smart-100d363b-1c3f-4b5d-9001-dd7b07333ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455976524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1455976524
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2619600078
Short name T1020
Test name
Test status
Simulation time 31953141687 ps
CPU time 12.86 seconds
Started Jul 02 09:24:57 AM PDT 24
Finished Jul 02 09:25:10 AM PDT 24
Peak memory 199948 kb
Host smart-db063684-196b-4090-847e-ad2377b2aa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619600078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2619600078
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2745443780
Short name T1062
Test name
Test status
Simulation time 152226962500 ps
CPU time 272.58 seconds
Started Jul 02 09:24:59 AM PDT 24
Finished Jul 02 09:29:32 AM PDT 24
Peak memory 200008 kb
Host smart-dc7d259c-abd1-4909-bce4-0afa4553ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745443780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2745443780
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.9617811
Short name T661
Test name
Test status
Simulation time 33380077804 ps
CPU time 64.08 seconds
Started Jul 02 09:25:00 AM PDT 24
Finished Jul 02 09:26:05 AM PDT 24
Peak memory 199960 kb
Host smart-0ad68da3-ab31-4116-bdd7-e733ef827f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9617811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.9617811
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1980299083
Short name T556
Test name
Test status
Simulation time 76085612154 ps
CPU time 29.47 seconds
Started Jul 02 09:24:58 AM PDT 24
Finished Jul 02 09:25:28 AM PDT 24
Peak memory 196600 kb
Host smart-de3df58b-1b79-4a59-8aa5-182d81a141bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980299083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1980299083
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2371018563
Short name T784
Test name
Test status
Simulation time 152712924040 ps
CPU time 883.26 seconds
Started Jul 02 09:25:09 AM PDT 24
Finished Jul 02 09:39:53 AM PDT 24
Peak memory 199928 kb
Host smart-460a03a1-b51d-4a86-b550-5563812575da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371018563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2371018563
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1002588972
Short name T947
Test name
Test status
Simulation time 3148708322 ps
CPU time 8.15 seconds
Started Jul 02 09:25:01 AM PDT 24
Finished Jul 02 09:25:09 AM PDT 24
Peak memory 199808 kb
Host smart-d42f230a-842d-4215-9206-6355f24be20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002588972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1002588972
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.308277230
Short name T37
Test name
Test status
Simulation time 14011276776 ps
CPU time 230.27 seconds
Started Jul 02 09:25:02 AM PDT 24
Finished Jul 02 09:28:54 AM PDT 24
Peak memory 199968 kb
Host smart-4184e85c-f196-451f-9cd0-3a04562147ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308277230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.308277230
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3979201699
Short name T880
Test name
Test status
Simulation time 1305804384 ps
CPU time 0.97 seconds
Started Jul 02 09:24:59 AM PDT 24
Finished Jul 02 09:25:00 AM PDT 24
Peak memory 195664 kb
Host smart-4feeafc1-6313-45e3-8033-4b1bfe2b3487
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979201699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3979201699
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1472895176
Short name T1045
Test name
Test status
Simulation time 23135014809 ps
CPU time 9.7 seconds
Started Jul 02 09:25:04 AM PDT 24
Finished Jul 02 09:25:15 AM PDT 24
Peak memory 197824 kb
Host smart-9b9d53a3-e99f-4e35-b394-f851a1f50ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472895176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1472895176
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2160091661
Short name T881
Test name
Test status
Simulation time 3049638411 ps
CPU time 5.37 seconds
Started Jul 02 09:25:02 AM PDT 24
Finished Jul 02 09:25:09 AM PDT 24
Peak memory 196344 kb
Host smart-f1289173-5c52-4c06-990e-2552f4103e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160091661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2160091661
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3226422894
Short name T894
Test name
Test status
Simulation time 5979317949 ps
CPU time 11.76 seconds
Started Jul 02 09:24:57 AM PDT 24
Finished Jul 02 09:25:09 AM PDT 24
Peak memory 199860 kb
Host smart-d0e20940-732b-4508-95f1-93af2f811838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226422894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3226422894
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3787982411
Short name T701
Test name
Test status
Simulation time 266563047820 ps
CPU time 171.52 seconds
Started Jul 02 09:25:02 AM PDT 24
Finished Jul 02 09:27:55 AM PDT 24
Peak memory 199904 kb
Host smart-df9b3af2-35c6-4893-aac4-897249c07f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787982411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3787982411
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.4188786438
Short name T32
Test name
Test status
Simulation time 57415175604 ps
CPU time 283.03 seconds
Started Jul 02 09:25:01 AM PDT 24
Finished Jul 02 09:29:45 AM PDT 24
Peak memory 209328 kb
Host smart-2d1643d9-60d5-428d-b044-b6af3bd724c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188786438 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.4188786438
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2046234308
Short name T323
Test name
Test status
Simulation time 1817367149 ps
CPU time 2.26 seconds
Started Jul 02 09:25:03 AM PDT 24
Finished Jul 02 09:25:06 AM PDT 24
Peak memory 198048 kb
Host smart-4e46976f-7129-4577-be8f-81ce79deecd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046234308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2046234308
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1129218750
Short name T741
Test name
Test status
Simulation time 50680933071 ps
CPU time 35.43 seconds
Started Jul 02 09:24:58 AM PDT 24
Finished Jul 02 09:25:34 AM PDT 24
Peak memory 199748 kb
Host smart-94d2b8f8-29f9-4c42-af17-737b78437e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129218750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1129218750
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2387730171
Short name T369
Test name
Test status
Simulation time 23725091 ps
CPU time 0.56 seconds
Started Jul 02 09:25:08 AM PDT 24
Finished Jul 02 09:25:09 AM PDT 24
Peak memory 195296 kb
Host smart-02011797-1afe-49e3-8d2a-5a533041a1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387730171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2387730171
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1085566806
Short name T183
Test name
Test status
Simulation time 59146377714 ps
CPU time 30.49 seconds
Started Jul 02 09:25:01 AM PDT 24
Finished Jul 02 09:25:33 AM PDT 24
Peak memory 200016 kb
Host smart-43ea98ed-0332-49c7-956e-1e1872dadacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085566806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1085566806
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1564253107
Short name T408
Test name
Test status
Simulation time 31512740918 ps
CPU time 51.63 seconds
Started Jul 02 09:25:02 AM PDT 24
Finished Jul 02 09:25:55 AM PDT 24
Peak memory 199972 kb
Host smart-9bb4cfe5-8907-4ad8-bf24-d2ee9636e10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564253107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1564253107
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1388740037
Short name T246
Test name
Test status
Simulation time 144286370429 ps
CPU time 55.38 seconds
Started Jul 02 09:25:04 AM PDT 24
Finished Jul 02 09:26:00 AM PDT 24
Peak memory 199932 kb
Host smart-6fde9a1c-5461-4684-85ef-1e0c88fa0a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388740037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1388740037
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3590898477
Short name T510
Test name
Test status
Simulation time 36415945742 ps
CPU time 62.38 seconds
Started Jul 02 09:25:07 AM PDT 24
Finished Jul 02 09:26:10 AM PDT 24
Peak memory 199172 kb
Host smart-4514e78f-bf7a-4f58-84f5-1bad820b7ff6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590898477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3590898477
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3489676439
Short name T855
Test name
Test status
Simulation time 20198907528 ps
CPU time 32.05 seconds
Started Jul 02 09:25:06 AM PDT 24
Finished Jul 02 09:25:39 AM PDT 24
Peak memory 199980 kb
Host smart-6c65f7d5-1089-432a-8520-7ea365d89e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489676439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3489676439
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.858023841
Short name T729
Test name
Test status
Simulation time 2872370357 ps
CPU time 5.42 seconds
Started Jul 02 09:25:06 AM PDT 24
Finished Jul 02 09:25:13 AM PDT 24
Peak memory 196348 kb
Host smart-57aa04a1-f558-4152-85b3-e1ae05a26455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858023841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.858023841
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.3047739887
Short name T482
Test name
Test status
Simulation time 10859391339 ps
CPU time 130.53 seconds
Started Jul 02 09:25:05 AM PDT 24
Finished Jul 02 09:27:17 AM PDT 24
Peak memory 199916 kb
Host smart-33598f18-34ab-4f55-bfdd-f63ee6b21740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047739887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3047739887
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.648065253
Short name T362
Test name
Test status
Simulation time 1490529045 ps
CPU time 3.02 seconds
Started Jul 02 09:25:09 AM PDT 24
Finished Jul 02 09:25:13 AM PDT 24
Peak memory 199084 kb
Host smart-d592ba79-9021-4b1e-9a49-e590b5cc6b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=648065253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.648065253
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3992731452
Short name T1074
Test name
Test status
Simulation time 28772174494 ps
CPU time 26.08 seconds
Started Jul 02 09:25:06 AM PDT 24
Finished Jul 02 09:25:33 AM PDT 24
Peak memory 199924 kb
Host smart-7b606155-7d81-4997-8e5a-d2e47ae193b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992731452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3992731452
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2067825799
Short name T744
Test name
Test status
Simulation time 3337249181 ps
CPU time 4.96 seconds
Started Jul 02 09:25:07 AM PDT 24
Finished Jul 02 09:25:13 AM PDT 24
Peak memory 196244 kb
Host smart-02420c9f-7ed2-4e8b-8823-45ae6e1e7f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067825799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2067825799
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.4004937345
Short name T267
Test name
Test status
Simulation time 5522349727 ps
CPU time 15.88 seconds
Started Jul 02 09:25:05 AM PDT 24
Finished Jul 02 09:25:22 AM PDT 24
Peak memory 199908 kb
Host smart-ed8f0ebd-223f-4cd5-aec5-f639b89ae8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004937345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.4004937345
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1446276293
Short name T165
Test name
Test status
Simulation time 343927770092 ps
CPU time 985.98 seconds
Started Jul 02 09:25:08 AM PDT 24
Finished Jul 02 09:41:35 AM PDT 24
Peak memory 199968 kb
Host smart-75c08b12-2cd7-4c70-9d84-f664c260f0c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446276293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1446276293
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.159799165
Short name T582
Test name
Test status
Simulation time 406995381 ps
CPU time 1.84 seconds
Started Jul 02 09:25:07 AM PDT 24
Finished Jul 02 09:25:10 AM PDT 24
Peak memory 198604 kb
Host smart-b91882c2-371e-4607-87a4-95622afdb108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159799165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.159799165
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2458200006
Short name T70
Test name
Test status
Simulation time 83001283037 ps
CPU time 23.04 seconds
Started Jul 02 09:25:05 AM PDT 24
Finished Jul 02 09:25:29 AM PDT 24
Peak memory 199964 kb
Host smart-f1d6de93-5edd-4544-9d24-189965f1a986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458200006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2458200006
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3035034712
Short name T742
Test name
Test status
Simulation time 12089104 ps
CPU time 0.56 seconds
Started Jul 02 09:25:10 AM PDT 24
Finished Jul 02 09:25:11 AM PDT 24
Peak memory 194952 kb
Host smart-f4f6a6db-4990-4737-95a4-61d84a8a28b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035034712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3035034712
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.566088400
Short name T385
Test name
Test status
Simulation time 179439471605 ps
CPU time 69.35 seconds
Started Jul 02 09:25:11 AM PDT 24
Finished Jul 02 09:26:22 AM PDT 24
Peak memory 199976 kb
Host smart-ac2b7495-7788-45f2-8daa-7e37638c3586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566088400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.566088400
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3220057977
Short name T818
Test name
Test status
Simulation time 20376882927 ps
CPU time 30.89 seconds
Started Jul 02 09:25:15 AM PDT 24
Finished Jul 02 09:25:47 AM PDT 24
Peak memory 199960 kb
Host smart-4ab25ab1-bcf4-4a5c-897b-bf1692a82d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220057977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3220057977
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3845470427
Short name T152
Test name
Test status
Simulation time 97640814737 ps
CPU time 140.91 seconds
Started Jul 02 09:25:13 AM PDT 24
Finished Jul 02 09:27:35 AM PDT 24
Peak memory 199908 kb
Host smart-f1be014c-04a9-417c-a6ae-739bc0e023c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845470427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3845470427
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3064787413
Short name T382
Test name
Test status
Simulation time 18177641386 ps
CPU time 8.99 seconds
Started Jul 02 09:25:09 AM PDT 24
Finished Jul 02 09:25:19 AM PDT 24
Peak memory 199936 kb
Host smart-e74e1054-642a-4443-9f28-44123cc4f964
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064787413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3064787413
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3897415690
Short name T492
Test name
Test status
Simulation time 109298454039 ps
CPU time 243.5 seconds
Started Jul 02 09:25:10 AM PDT 24
Finished Jul 02 09:29:14 AM PDT 24
Peak memory 199952 kb
Host smart-5a425c29-5b3c-4fa4-a58c-e769698dda72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3897415690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3897415690
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3772768923
Short name T718
Test name
Test status
Simulation time 8318717011 ps
CPU time 2.33 seconds
Started Jul 02 09:25:11 AM PDT 24
Finished Jul 02 09:25:14 AM PDT 24
Peak memory 199256 kb
Host smart-915f088a-124d-4001-bbf1-4bca4b506aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772768923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3772768923
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.949504867
Short name T887
Test name
Test status
Simulation time 9198981383 ps
CPU time 132.61 seconds
Started Jul 02 09:25:11 AM PDT 24
Finished Jul 02 09:27:25 AM PDT 24
Peak memory 199948 kb
Host smart-73e06f3d-9e84-4ca1-963d-c6d554f89413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949504867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.949504867
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1809251537
Short name T1009
Test name
Test status
Simulation time 7232730881 ps
CPU time 13.68 seconds
Started Jul 02 09:25:12 AM PDT 24
Finished Jul 02 09:25:27 AM PDT 24
Peak memory 199272 kb
Host smart-b8c42ca1-ed99-434f-82ff-bb23c4bcab46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809251537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1809251537
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3814344038
Short name T141
Test name
Test status
Simulation time 62164382619 ps
CPU time 24.4 seconds
Started Jul 02 09:25:11 AM PDT 24
Finished Jul 02 09:25:36 AM PDT 24
Peak memory 199932 kb
Host smart-41dc036c-7961-41b1-9f42-62a8d11f75f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814344038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3814344038
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3315384481
Short name T716
Test name
Test status
Simulation time 2345279345 ps
CPU time 1.56 seconds
Started Jul 02 09:25:12 AM PDT 24
Finished Jul 02 09:25:15 AM PDT 24
Peak memory 195544 kb
Host smart-d13b0c9b-2848-4e3e-8973-d053d3d96262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315384481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3315384481
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1188702931
Short name T769
Test name
Test status
Simulation time 919141978 ps
CPU time 1.64 seconds
Started Jul 02 09:25:09 AM PDT 24
Finished Jul 02 09:25:11 AM PDT 24
Peak memory 199888 kb
Host smart-ee15e7ed-d1a2-45d7-8b30-816e60949bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188702931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1188702931
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1147727105
Short name T681
Test name
Test status
Simulation time 39623242299 ps
CPU time 249.64 seconds
Started Jul 02 09:25:11 AM PDT 24
Finished Jul 02 09:29:22 AM PDT 24
Peak memory 215528 kb
Host smart-a4ffe0b0-5353-4a72-bd10-265e3843542a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147727105 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1147727105
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.19707326
Short name T844
Test name
Test status
Simulation time 900380053 ps
CPU time 2.71 seconds
Started Jul 02 09:25:13 AM PDT 24
Finished Jul 02 09:25:16 AM PDT 24
Peak memory 199916 kb
Host smart-59a9b79d-10fe-4845-a6ff-ae3ea7bcdead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19707326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.19707326
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3455455725
Short name T726
Test name
Test status
Simulation time 76306938635 ps
CPU time 30.74 seconds
Started Jul 02 09:25:06 AM PDT 24
Finished Jul 02 09:25:38 AM PDT 24
Peak memory 200108 kb
Host smart-7f102f7a-b68e-4a66-b78d-eec56ed41a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455455725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3455455725
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1229546790
Short name T770
Test name
Test status
Simulation time 12572154 ps
CPU time 0.55 seconds
Started Jul 02 09:25:20 AM PDT 24
Finished Jul 02 09:25:21 AM PDT 24
Peak memory 194200 kb
Host smart-8a27008c-3129-4e75-b654-caadc6ca0ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229546790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1229546790
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1675814626
Short name T184
Test name
Test status
Simulation time 154592558597 ps
CPU time 137.22 seconds
Started Jul 02 09:25:15 AM PDT 24
Finished Jul 02 09:27:33 AM PDT 24
Peak memory 200192 kb
Host smart-3ae34676-16e1-4bd2-949b-458f699eb1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675814626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1675814626
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.575279157
Short name T117
Test name
Test status
Simulation time 25980226350 ps
CPU time 22.22 seconds
Started Jul 02 09:25:17 AM PDT 24
Finished Jul 02 09:25:40 AM PDT 24
Peak memory 199952 kb
Host smart-2419799c-93d5-400a-abaa-c3f7127ffe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575279157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.575279157
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3642802908
Short name T491
Test name
Test status
Simulation time 19403611073 ps
CPU time 29.2 seconds
Started Jul 02 09:25:16 AM PDT 24
Finished Jul 02 09:25:47 AM PDT 24
Peak memory 199908 kb
Host smart-8ccf1546-01cb-4bac-aafe-3a450d823f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642802908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3642802908
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2327829527
Short name T775
Test name
Test status
Simulation time 986185067 ps
CPU time 0.9 seconds
Started Jul 02 09:25:15 AM PDT 24
Finished Jul 02 09:25:17 AM PDT 24
Peak memory 196304 kb
Host smart-2984cd4f-5cc9-4b8b-85c2-df9cb395f87b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327829527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2327829527
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2016811646
Short name T36
Test name
Test status
Simulation time 107731242728 ps
CPU time 339.35 seconds
Started Jul 02 09:25:14 AM PDT 24
Finished Jul 02 09:30:54 AM PDT 24
Peak memory 199976 kb
Host smart-3afb400f-5db6-4557-9d87-8f24dc15c5d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016811646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2016811646
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2461950564
Short name T13
Test name
Test status
Simulation time 9597715072 ps
CPU time 14.65 seconds
Started Jul 02 09:25:13 AM PDT 24
Finished Jul 02 09:25:29 AM PDT 24
Peak memory 199416 kb
Host smart-75476f35-e7cb-4752-9685-d82b4ba8db48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461950564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2461950564
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.689819677
Short name T656
Test name
Test status
Simulation time 9154753779 ps
CPU time 93.31 seconds
Started Jul 02 09:25:15 AM PDT 24
Finished Jul 02 09:26:50 AM PDT 24
Peak memory 199988 kb
Host smart-6be45200-e4b9-426d-89c5-00e507c358ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689819677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.689819677
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3463157176
Short name T99
Test name
Test status
Simulation time 3984939397 ps
CPU time 10.23 seconds
Started Jul 02 09:25:13 AM PDT 24
Finished Jul 02 09:25:24 AM PDT 24
Peak memory 198552 kb
Host smart-26fa8d45-c0a2-4346-9fd3-8e8a46ab72a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3463157176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3463157176
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3489791538
Short name T859
Test name
Test status
Simulation time 26288456769 ps
CPU time 10.4 seconds
Started Jul 02 09:25:16 AM PDT 24
Finished Jul 02 09:25:27 AM PDT 24
Peak memory 199972 kb
Host smart-267e828d-09ce-4b6c-9507-5387ae841d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489791538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3489791538
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3806997867
Short name T371
Test name
Test status
Simulation time 51842919322 ps
CPU time 38.92 seconds
Started Jul 02 09:25:15 AM PDT 24
Finished Jul 02 09:25:54 AM PDT 24
Peak memory 195956 kb
Host smart-4d74bb18-9f33-45e1-b1e2-8b6bb3f9afaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806997867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3806997867
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2281394219
Short name T312
Test name
Test status
Simulation time 934037905 ps
CPU time 3.64 seconds
Started Jul 02 09:25:11 AM PDT 24
Finished Jul 02 09:25:16 AM PDT 24
Peak memory 198860 kb
Host smart-de6741d4-d54b-4fd7-af70-b3e7c8b89a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281394219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2281394219
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2860848897
Short name T168
Test name
Test status
Simulation time 170462099638 ps
CPU time 613.01 seconds
Started Jul 02 09:25:15 AM PDT 24
Finished Jul 02 09:35:29 AM PDT 24
Peak memory 199892 kb
Host smart-8a60d328-f2a3-41ab-b2ce-bdcd3f123405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860848897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2860848897
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2076084001
Short name T932
Test name
Test status
Simulation time 865290628 ps
CPU time 2.36 seconds
Started Jul 02 09:25:15 AM PDT 24
Finished Jul 02 09:25:19 AM PDT 24
Peak memory 198732 kb
Host smart-efb5fc9a-af50-4c91-b17c-e96b7ed57da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076084001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2076084001
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3372162370
Short name T452
Test name
Test status
Simulation time 167818981782 ps
CPU time 71.39 seconds
Started Jul 02 09:25:14 AM PDT 24
Finished Jul 02 09:26:26 AM PDT 24
Peak memory 199944 kb
Host smart-59711d10-19a1-4823-b22b-92671b670dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372162370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3372162370
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.554609171
Short name T735
Test name
Test status
Simulation time 18515484 ps
CPU time 0.55 seconds
Started Jul 02 09:25:24 AM PDT 24
Finished Jul 02 09:25:25 AM PDT 24
Peak memory 194460 kb
Host smart-51bdfc2e-438b-47c2-a65a-2831414bb1e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554609171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.554609171
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1759414985
Short name T670
Test name
Test status
Simulation time 84243333107 ps
CPU time 15.47 seconds
Started Jul 02 09:25:16 AM PDT 24
Finished Jul 02 09:25:33 AM PDT 24
Peak memory 199996 kb
Host smart-309dd75e-45d7-4539-9373-ea37400b0fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759414985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1759414985
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1389571351
Short name T129
Test name
Test status
Simulation time 139378933058 ps
CPU time 63.9 seconds
Started Jul 02 09:25:17 AM PDT 24
Finished Jul 02 09:26:22 AM PDT 24
Peak memory 199924 kb
Host smart-7b838e6e-b24c-4795-8053-757801321749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389571351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1389571351
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.280231413
Short name T931
Test name
Test status
Simulation time 17793222265 ps
CPU time 26.36 seconds
Started Jul 02 09:25:17 AM PDT 24
Finished Jul 02 09:25:45 AM PDT 24
Peak memory 199924 kb
Host smart-223c2af4-a792-48f2-aafd-e83dc7ec45c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280231413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.280231413
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2128479877
Short name T763
Test name
Test status
Simulation time 61714797669 ps
CPU time 32.43 seconds
Started Jul 02 09:25:18 AM PDT 24
Finished Jul 02 09:25:51 AM PDT 24
Peak memory 198812 kb
Host smart-798f1539-abf8-4f0e-af58-ffb59754f9a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128479877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2128479877
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1260535516
Short name T902
Test name
Test status
Simulation time 71740797250 ps
CPU time 352.3 seconds
Started Jul 02 09:25:23 AM PDT 24
Finished Jul 02 09:31:16 AM PDT 24
Peak memory 200020 kb
Host smart-7260c6d9-5fc1-4bff-829a-48e4f5bee81b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260535516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1260535516
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2790007434
Short name T619
Test name
Test status
Simulation time 1494954437 ps
CPU time 2.85 seconds
Started Jul 02 09:25:17 AM PDT 24
Finished Jul 02 09:25:21 AM PDT 24
Peak memory 195928 kb
Host smart-ea5a4d6a-f0da-4fb7-999e-988c78dae58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790007434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2790007434
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.3901754784
Short name T296
Test name
Test status
Simulation time 19875262297 ps
CPU time 71.95 seconds
Started Jul 02 09:25:19 AM PDT 24
Finished Jul 02 09:26:31 AM PDT 24
Peak memory 199992 kb
Host smart-8e9cb2d2-37b1-4f37-9803-c6942cc9e8b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3901754784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3901754784
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2555378398
Short name T1039
Test name
Test status
Simulation time 7073078713 ps
CPU time 62.92 seconds
Started Jul 02 09:25:18 AM PDT 24
Finished Jul 02 09:26:22 AM PDT 24
Peak memory 197920 kb
Host smart-2d36e473-02a7-4cdc-ac7b-29082095acf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555378398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2555378398
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1076481099
Short name T97
Test name
Test status
Simulation time 32304752950 ps
CPU time 19.75 seconds
Started Jul 02 09:25:18 AM PDT 24
Finished Jul 02 09:25:38 AM PDT 24
Peak memory 199960 kb
Host smart-6d388a3d-0344-4ef4-a640-1117af1b32c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076481099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1076481099
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2057876313
Short name T434
Test name
Test status
Simulation time 6294148014 ps
CPU time 3.5 seconds
Started Jul 02 09:25:19 AM PDT 24
Finished Jul 02 09:25:23 AM PDT 24
Peak memory 196036 kb
Host smart-4f56d2eb-64a1-47b8-b137-8fb265c5b343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057876313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2057876313
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.410845932
Short name T419
Test name
Test status
Simulation time 5556864742 ps
CPU time 6.85 seconds
Started Jul 02 09:25:17 AM PDT 24
Finished Jul 02 09:25:25 AM PDT 24
Peak memory 199828 kb
Host smart-08a8d130-66a8-4e69-86eb-f78213b3993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410845932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.410845932
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2159691304
Short name T1058
Test name
Test status
Simulation time 54608925673 ps
CPU time 89.08 seconds
Started Jul 02 09:25:21 AM PDT 24
Finished Jul 02 09:26:51 AM PDT 24
Peak memory 199900 kb
Host smart-dd9e2c3e-e9e4-498e-8e5e-1be140f5fdf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159691304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2159691304
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1930899903
Short name T697
Test name
Test status
Simulation time 1110366164 ps
CPU time 1.44 seconds
Started Jul 02 09:25:21 AM PDT 24
Finished Jul 02 09:25:23 AM PDT 24
Peak memory 199788 kb
Host smart-06275144-c6e0-4291-bbb0-0b9e20e84091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930899903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1930899903
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3760435517
Short name T819
Test name
Test status
Simulation time 40086264902 ps
CPU time 16.41 seconds
Started Jul 02 09:25:19 AM PDT 24
Finished Jul 02 09:25:36 AM PDT 24
Peak memory 199928 kb
Host smart-21ff74cf-7992-49c6-b1bc-4c7d10bd5efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760435517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3760435517
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.369098870
Short name T888
Test name
Test status
Simulation time 21133965 ps
CPU time 0.58 seconds
Started Jul 02 09:25:29 AM PDT 24
Finished Jul 02 09:25:30 AM PDT 24
Peak memory 195564 kb
Host smart-c2fd961a-cd2a-43f0-b445-0cc12ae0a305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369098870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.369098870
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1203040573
Short name T984
Test name
Test status
Simulation time 30242524060 ps
CPU time 31.36 seconds
Started Jul 02 09:25:23 AM PDT 24
Finished Jul 02 09:25:55 AM PDT 24
Peak memory 199972 kb
Host smart-7f2fdc7c-cedc-4012-8225-9be5e89e1496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203040573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1203040573
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2803026952
Short name T1041
Test name
Test status
Simulation time 50564454787 ps
CPU time 38.42 seconds
Started Jul 02 09:25:23 AM PDT 24
Finished Jul 02 09:26:02 AM PDT 24
Peak memory 199812 kb
Host smart-ba449a61-0e3b-4111-a090-4c238737a89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803026952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2803026952
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.110817913
Short name T814
Test name
Test status
Simulation time 16052015398 ps
CPU time 45 seconds
Started Jul 02 09:25:23 AM PDT 24
Finished Jul 02 09:26:08 AM PDT 24
Peak memory 199788 kb
Host smart-dd2a82f9-3c65-468e-9f6c-85a04e47bb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110817913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.110817913
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.4087288064
Short name T1069
Test name
Test status
Simulation time 20597187693 ps
CPU time 22.75 seconds
Started Jul 02 09:25:21 AM PDT 24
Finished Jul 02 09:25:44 AM PDT 24
Peak memory 199968 kb
Host smart-272ab4ad-53da-4049-8dcd-36d44a7ed7ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087288064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4087288064
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2042139510
Short name T768
Test name
Test status
Simulation time 111189992992 ps
CPU time 816.67 seconds
Started Jul 02 09:25:26 AM PDT 24
Finished Jul 02 09:39:03 AM PDT 24
Peak memory 199972 kb
Host smart-af075357-638e-48cf-b81e-d2e62a39fe51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2042139510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2042139510
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1751603275
Short name T374
Test name
Test status
Simulation time 5153577159 ps
CPU time 4.01 seconds
Started Jul 02 09:25:25 AM PDT 24
Finished Jul 02 09:25:29 AM PDT 24
Peak memory 198420 kb
Host smart-a478bb40-d8eb-4071-9010-6c0a15986ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751603275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1751603275
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.3043238888
Short name T489
Test name
Test status
Simulation time 11074576965 ps
CPU time 64.41 seconds
Started Jul 02 09:25:28 AM PDT 24
Finished Jul 02 09:26:33 AM PDT 24
Peak memory 199992 kb
Host smart-ab069638-4a04-4285-b073-fd2c01738357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3043238888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3043238888
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.740308345
Short name T1011
Test name
Test status
Simulation time 6646267267 ps
CPU time 22.78 seconds
Started Jul 02 09:25:26 AM PDT 24
Finished Jul 02 09:25:49 AM PDT 24
Peak memory 199244 kb
Host smart-110df853-8111-4a89-b198-90fdee10372c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740308345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.740308345
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3392226725
Short name T331
Test name
Test status
Simulation time 77408874531 ps
CPU time 27.95 seconds
Started Jul 02 09:25:29 AM PDT 24
Finished Jul 02 09:25:58 AM PDT 24
Peak memory 199900 kb
Host smart-bad945bc-0ac4-4198-a815-c00c6081d387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392226725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3392226725
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1001874008
Short name T1007
Test name
Test status
Simulation time 5534774839 ps
CPU time 3.67 seconds
Started Jul 02 09:25:23 AM PDT 24
Finished Jul 02 09:25:28 AM PDT 24
Peak memory 196076 kb
Host smart-5e24b73f-3a5d-4237-82ef-036156b49b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001874008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1001874008
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1527099141
Short name T694
Test name
Test status
Simulation time 5911755632 ps
CPU time 13.69 seconds
Started Jul 02 09:25:25 AM PDT 24
Finished Jul 02 09:25:39 AM PDT 24
Peak memory 199484 kb
Host smart-69ca5a1b-1791-40df-8079-490379f3c11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527099141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1527099141
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2389966547
Short name T962
Test name
Test status
Simulation time 236315167915 ps
CPU time 75.68 seconds
Started Jul 02 09:25:30 AM PDT 24
Finished Jul 02 09:26:47 AM PDT 24
Peak memory 199952 kb
Host smart-074850e3-0a2b-4793-96be-c56f745c9e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389966547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2389966547
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.228015473
Short name T967
Test name
Test status
Simulation time 261863701205 ps
CPU time 917 seconds
Started Jul 02 09:25:28 AM PDT 24
Finished Jul 02 09:40:46 AM PDT 24
Peak memory 224812 kb
Host smart-4d4875f1-bcc7-463b-a14d-c6fe5d8c47ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228015473 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.228015473
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2203128050
Short name T570
Test name
Test status
Simulation time 7616304709 ps
CPU time 9.55 seconds
Started Jul 02 09:25:27 AM PDT 24
Finished Jul 02 09:25:37 AM PDT 24
Peak memory 199980 kb
Host smart-0e3a606f-beea-454f-b997-e2f1a8417bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203128050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2203128050
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3986515981
Short name T1012
Test name
Test status
Simulation time 102255651146 ps
CPU time 208.22 seconds
Started Jul 02 09:25:23 AM PDT 24
Finished Jul 02 09:28:52 AM PDT 24
Peak memory 199884 kb
Host smart-9dd478a2-bc16-4550-a29d-3052a7df45cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986515981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3986515981
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3918301102
Short name T601
Test name
Test status
Simulation time 36004300 ps
CPU time 0.55 seconds
Started Jul 02 09:25:31 AM PDT 24
Finished Jul 02 09:25:33 AM PDT 24
Peak memory 195292 kb
Host smart-004320ef-18e1-46d4-a92c-24a0ca491284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918301102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3918301102
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2527581469
Short name T48
Test name
Test status
Simulation time 72044215548 ps
CPU time 30.16 seconds
Started Jul 02 09:25:29 AM PDT 24
Finished Jul 02 09:26:01 AM PDT 24
Peak memory 199888 kb
Host smart-026b94c2-01a0-461b-8ce3-9e847a5841cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527581469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2527581469
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.329764061
Short name T891
Test name
Test status
Simulation time 95404836258 ps
CPU time 80.29 seconds
Started Jul 02 09:25:29 AM PDT 24
Finished Jul 02 09:26:50 AM PDT 24
Peak memory 199956 kb
Host smart-769e5b5b-ef26-4914-a483-1936be265ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329764061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.329764061
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.194245830
Short name T42
Test name
Test status
Simulation time 41376470116 ps
CPU time 67.73 seconds
Started Jul 02 09:25:33 AM PDT 24
Finished Jul 02 09:26:41 AM PDT 24
Peak memory 199820 kb
Host smart-8e2ad782-392d-43c7-bb35-ca2d01c998bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194245830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.194245830
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3558237620
Short name T118
Test name
Test status
Simulation time 57479539854 ps
CPU time 19.79 seconds
Started Jul 02 09:25:27 AM PDT 24
Finished Jul 02 09:25:48 AM PDT 24
Peak memory 198552 kb
Host smart-a6e4fc8e-6872-446c-9042-2221a77981bb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558237620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3558237620
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.891744256
Short name T506
Test name
Test status
Simulation time 120775799185 ps
CPU time 322.6 seconds
Started Jul 02 09:25:30 AM PDT 24
Finished Jul 02 09:30:54 AM PDT 24
Peak memory 199912 kb
Host smart-6da0063a-7c80-4118-9ac4-34b32d5ff99f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891744256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.891744256
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.300153176
Short name T43
Test name
Test status
Simulation time 8543683417 ps
CPU time 3.71 seconds
Started Jul 02 09:25:27 AM PDT 24
Finished Jul 02 09:25:32 AM PDT 24
Peak memory 199984 kb
Host smart-2335a249-a156-493e-b774-0f86271495e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300153176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.300153176
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.633653640
Short name T760
Test name
Test status
Simulation time 12354688399 ps
CPU time 179.97 seconds
Started Jul 02 09:25:30 AM PDT 24
Finished Jul 02 09:28:31 AM PDT 24
Peak memory 199952 kb
Host smart-f0262547-81e2-4809-a665-903eef463fcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633653640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.633653640
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.212901816
Short name T397
Test name
Test status
Simulation time 4020911358 ps
CPU time 8.09 seconds
Started Jul 02 09:25:27 AM PDT 24
Finished Jul 02 09:25:35 AM PDT 24
Peak memory 199236 kb
Host smart-b455ac18-e73b-4ce7-8912-5a63b12970cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212901816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.212901816
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2872315222
Short name T617
Test name
Test status
Simulation time 192255864972 ps
CPU time 74.28 seconds
Started Jul 02 09:25:28 AM PDT 24
Finished Jul 02 09:26:44 AM PDT 24
Peak memory 199996 kb
Host smart-755cd32c-28c8-4890-9926-0f4f163150f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872315222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2872315222
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1798348290
Short name T599
Test name
Test status
Simulation time 5540560735 ps
CPU time 9.25 seconds
Started Jul 02 09:25:28 AM PDT 24
Finished Jul 02 09:25:38 AM PDT 24
Peak memory 196244 kb
Host smart-f66ad566-39a2-43e9-af7e-894753e834c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798348290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1798348290
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.542677039
Short name T553
Test name
Test status
Simulation time 482877916 ps
CPU time 1.33 seconds
Started Jul 02 09:25:28 AM PDT 24
Finished Jul 02 09:25:30 AM PDT 24
Peak memory 199904 kb
Host smart-75bc8be0-feb2-438d-a77e-d8a8baccbe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542677039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.542677039
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.4235272416
Short name T19
Test name
Test status
Simulation time 34116229107 ps
CPU time 923.38 seconds
Started Jul 02 09:25:29 AM PDT 24
Finished Jul 02 09:40:54 AM PDT 24
Peak memory 216364 kb
Host smart-0383e37b-d574-4d4c-ad12-e0f690c80044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235272416 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.4235272416
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.291896134
Short name T594
Test name
Test status
Simulation time 1057109121 ps
CPU time 4.38 seconds
Started Jul 02 09:25:27 AM PDT 24
Finished Jul 02 09:25:31 AM PDT 24
Peak memory 199840 kb
Host smart-a8b58a37-48b7-4948-be67-0a7c0806fc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291896134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.291896134
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2075737617
Short name T686
Test name
Test status
Simulation time 23568714281 ps
CPU time 30.26 seconds
Started Jul 02 09:25:28 AM PDT 24
Finished Jul 02 09:25:59 AM PDT 24
Peak memory 200004 kb
Host smart-ba251bce-f09c-475d-a323-197463bf2911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075737617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2075737617
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2166383519
Short name T704
Test name
Test status
Simulation time 12418631 ps
CPU time 0.55 seconds
Started Jul 02 09:25:35 AM PDT 24
Finished Jul 02 09:25:36 AM PDT 24
Peak memory 195316 kb
Host smart-7d9d9e41-47f5-49d7-a543-fc5c6606f856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166383519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2166383519
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3311067819
Short name T1085
Test name
Test status
Simulation time 146140743156 ps
CPU time 71.41 seconds
Started Jul 02 09:25:32 AM PDT 24
Finished Jul 02 09:26:44 AM PDT 24
Peak memory 200000 kb
Host smart-2fb4e458-43f2-44bc-b675-e72695b2aef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311067819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3311067819
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2857189624
Short name T771
Test name
Test status
Simulation time 135711036239 ps
CPU time 55.68 seconds
Started Jul 02 09:25:32 AM PDT 24
Finished Jul 02 09:26:28 AM PDT 24
Peak memory 199876 kb
Host smart-09ca77e2-65a0-488f-8d52-be9255a2ade0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857189624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2857189624
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3003837289
Short name T595
Test name
Test status
Simulation time 65853303378 ps
CPU time 27.25 seconds
Started Jul 02 09:25:31 AM PDT 24
Finished Jul 02 09:25:59 AM PDT 24
Peak memory 200020 kb
Host smart-02edea14-a75d-48cf-ba8d-29553e4a50c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003837289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3003837289
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.68122835
Short name T665
Test name
Test status
Simulation time 7675564900 ps
CPU time 7.34 seconds
Started Jul 02 09:25:31 AM PDT 24
Finished Jul 02 09:25:39 AM PDT 24
Peak memory 200016 kb
Host smart-238ee4c8-9ea6-471d-9daa-aeef7bd3f3fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68122835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.68122835
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3057665794
Short name T907
Test name
Test status
Simulation time 213335850626 ps
CPU time 289.33 seconds
Started Jul 02 09:25:38 AM PDT 24
Finished Jul 02 09:30:28 AM PDT 24
Peak memory 199952 kb
Host smart-4b943ed2-a68f-4da1-9772-d03b51b7ad22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3057665794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3057665794
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.413761473
Short name T1
Test name
Test status
Simulation time 1977814367 ps
CPU time 1.62 seconds
Started Jul 02 09:25:35 AM PDT 24
Finished Jul 02 09:25:37 AM PDT 24
Peak memory 197068 kb
Host smart-1a8f87ca-784e-48ff-96e5-a47ad38f84e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413761473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.413761473
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.3181596543
Short name T778
Test name
Test status
Simulation time 16439226859 ps
CPU time 847.17 seconds
Started Jul 02 09:25:38 AM PDT 24
Finished Jul 02 09:39:46 AM PDT 24
Peak memory 199960 kb
Host smart-00ebfdb2-c04e-496d-8c06-9329ece01d37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3181596543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3181596543
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3012670699
Short name T955
Test name
Test status
Simulation time 4007355981 ps
CPU time 15.83 seconds
Started Jul 02 09:25:30 AM PDT 24
Finished Jul 02 09:25:47 AM PDT 24
Peak memory 198124 kb
Host smart-1286af28-2b95-4bec-9e4d-16f148f8155b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012670699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3012670699
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.262213219
Short name T514
Test name
Test status
Simulation time 28286210901 ps
CPU time 25.99 seconds
Started Jul 02 09:25:34 AM PDT 24
Finished Jul 02 09:26:00 AM PDT 24
Peak memory 199836 kb
Host smart-5efb7b90-112a-4bf0-8de8-3279417fe6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262213219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.262213219
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.914522163
Short name T876
Test name
Test status
Simulation time 3288062604 ps
CPU time 1.81 seconds
Started Jul 02 09:25:34 AM PDT 24
Finished Jul 02 09:25:37 AM PDT 24
Peak memory 195864 kb
Host smart-b469b552-7044-41d8-a711-dd5a98a3e69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914522163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.914522163
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.778024515
Short name T291
Test name
Test status
Simulation time 509581145 ps
CPU time 1.63 seconds
Started Jul 02 09:25:33 AM PDT 24
Finished Jul 02 09:25:35 AM PDT 24
Peak memory 199520 kb
Host smart-32e1bc4e-c44e-42dc-a341-98fa12370e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778024515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.778024515
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3251126370
Short name T576
Test name
Test status
Simulation time 47779488456 ps
CPU time 1248.03 seconds
Started Jul 02 09:25:35 AM PDT 24
Finished Jul 02 09:46:24 AM PDT 24
Peak memory 215984 kb
Host smart-1845e3c9-8b56-4a90-84ae-aac093f7faf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251126370 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3251126370
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.621666545
Short name T928
Test name
Test status
Simulation time 755533762 ps
CPU time 1.26 seconds
Started Jul 02 09:25:37 AM PDT 24
Finished Jul 02 09:25:39 AM PDT 24
Peak memory 198740 kb
Host smart-f269acc1-0413-4419-86de-9a6cdefc9928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621666545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.621666545
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1583174626
Short name T874
Test name
Test status
Simulation time 42436755483 ps
CPU time 15.26 seconds
Started Jul 02 09:25:30 AM PDT 24
Finished Jul 02 09:25:46 AM PDT 24
Peak memory 199996 kb
Host smart-2a537ed2-95ce-48b1-934e-a6c7728db153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583174626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1583174626
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.741215545
Short name T521
Test name
Test status
Simulation time 39259030 ps
CPU time 0.59 seconds
Started Jul 02 09:23:08 AM PDT 24
Finished Jul 02 09:23:10 AM PDT 24
Peak memory 195308 kb
Host smart-48509e75-2670-44a7-b8e6-85e0f05246a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741215545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.741215545
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1680455084
Short name T100
Test name
Test status
Simulation time 117289508038 ps
CPU time 230.2 seconds
Started Jul 02 09:22:59 AM PDT 24
Finished Jul 02 09:26:50 AM PDT 24
Peak memory 199944 kb
Host smart-41cd8429-d64e-4982-8474-97f731f632fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680455084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1680455084
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.143242404
Short name T756
Test name
Test status
Simulation time 26781335214 ps
CPU time 44.54 seconds
Started Jul 02 09:23:10 AM PDT 24
Finished Jul 02 09:23:55 AM PDT 24
Peak memory 199884 kb
Host smart-7e3073bb-2410-4e26-9d4d-e1a7614afc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143242404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.143242404
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.968819034
Short name T687
Test name
Test status
Simulation time 75770016048 ps
CPU time 385.47 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:29:45 AM PDT 24
Peak memory 199992 kb
Host smart-a2578e3e-e7f8-4a5c-8f1f-bc08ae1e3d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968819034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.968819034
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1009670213
Short name T1030
Test name
Test status
Simulation time 23938225702 ps
CPU time 13.65 seconds
Started Jul 02 09:23:07 AM PDT 24
Finished Jul 02 09:23:22 AM PDT 24
Peak memory 199920 kb
Host smart-48b61820-a69a-4a08-bc58-a21a68308e44
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009670213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1009670213
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.4274364676
Short name T391
Test name
Test status
Simulation time 75985287090 ps
CPU time 369.42 seconds
Started Jul 02 09:23:16 AM PDT 24
Finished Jul 02 09:29:27 AM PDT 24
Peak memory 199928 kb
Host smart-db2f94ac-8b12-4b13-ac42-7eb6eec9bbef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274364676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.4274364676
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1354121044
Short name T820
Test name
Test status
Simulation time 8450594281 ps
CPU time 17.73 seconds
Started Jul 02 09:23:07 AM PDT 24
Finished Jul 02 09:23:26 AM PDT 24
Peak memory 199940 kb
Host smart-57ae2aa8-e174-4fda-8f4e-91c561cee483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354121044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1354121044
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.643832397
Short name T416
Test name
Test status
Simulation time 15769873025 ps
CPU time 495.53 seconds
Started Jul 02 09:23:15 AM PDT 24
Finished Jul 02 09:31:32 AM PDT 24
Peak memory 199952 kb
Host smart-5ae23a20-9c6e-4f6c-999b-3ca28390050d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643832397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.643832397
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1676815185
Short name T867
Test name
Test status
Simulation time 5847494320 ps
CPU time 13.01 seconds
Started Jul 02 09:23:14 AM PDT 24
Finished Jul 02 09:23:29 AM PDT 24
Peak memory 199460 kb
Host smart-bbbc9463-5f67-4931-9ccb-b018573f194f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1676815185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1676815185
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1230783579
Short name T552
Test name
Test status
Simulation time 50702038132 ps
CPU time 37.59 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:23:45 AM PDT 24
Peak memory 195916 kb
Host smart-fa9770c7-3272-4be2-8cb5-3f806f22a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230783579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1230783579
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.949768774
Short name T684
Test name
Test status
Simulation time 911365136 ps
CPU time 2.29 seconds
Started Jul 02 09:22:51 AM PDT 24
Finished Jul 02 09:22:54 AM PDT 24
Peak memory 198864 kb
Host smart-d17158e7-997d-4d78-aec4-07d0eafc1acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949768774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.949768774
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2506674440
Short name T1005
Test name
Test status
Simulation time 115490096053 ps
CPU time 58.95 seconds
Started Jul 02 09:23:16 AM PDT 24
Finished Jul 02 09:24:16 AM PDT 24
Peak memory 199912 kb
Host smart-00b3fed9-67a4-422a-922a-9ab65a49d2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506674440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2506674440
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1005852396
Short name T688
Test name
Test status
Simulation time 2142511652 ps
CPU time 2.34 seconds
Started Jul 02 09:23:10 AM PDT 24
Finished Jul 02 09:23:13 AM PDT 24
Peak memory 198852 kb
Host smart-c2d9080c-81b5-4191-84fc-6840e69e1cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005852396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1005852396
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1467382831
Short name T265
Test name
Test status
Simulation time 109940129206 ps
CPU time 271.63 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:27:39 AM PDT 24
Peak memory 199892 kb
Host smart-7a5f8963-7094-46aa-8384-5726e54c370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467382831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1467382831
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2574311417
Short name T956
Test name
Test status
Simulation time 20682688734 ps
CPU time 29.85 seconds
Started Jul 02 09:25:36 AM PDT 24
Finished Jul 02 09:26:06 AM PDT 24
Peak memory 199932 kb
Host smart-260a62d9-817b-4838-a7a4-8dff324c9731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574311417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2574311417
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3977182069
Short name T870
Test name
Test status
Simulation time 65564049582 ps
CPU time 286.51 seconds
Started Jul 02 09:25:36 AM PDT 24
Finished Jul 02 09:30:23 AM PDT 24
Peak memory 215676 kb
Host smart-2e6816bb-254b-4450-8a12-0a37341d77b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977182069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3977182069
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1552115613
Short name T336
Test name
Test status
Simulation time 80480467137 ps
CPU time 28.9 seconds
Started Jul 02 09:25:37 AM PDT 24
Finished Jul 02 09:26:06 AM PDT 24
Peak memory 199908 kb
Host smart-0049cca3-558c-472f-a857-2794af0feb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552115613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1552115613
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3390005846
Short name T230
Test name
Test status
Simulation time 44903638447 ps
CPU time 109.05 seconds
Started Jul 02 09:25:34 AM PDT 24
Finished Jul 02 09:27:24 AM PDT 24
Peak memory 199964 kb
Host smart-a3f66871-e1e1-4e60-b806-5ebfd3f1cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390005846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3390005846
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.403824830
Short name T501
Test name
Test status
Simulation time 27098606913 ps
CPU time 264.06 seconds
Started Jul 02 09:25:37 AM PDT 24
Finished Jul 02 09:30:02 AM PDT 24
Peak memory 215620 kb
Host smart-ae60b03e-db15-461f-948c-e8dbb3dd2736
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403824830 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.403824830
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.522257464
Short name T247
Test name
Test status
Simulation time 219531359363 ps
CPU time 60.5 seconds
Started Jul 02 09:25:38 AM PDT 24
Finished Jul 02 09:26:40 AM PDT 24
Peak memory 200040 kb
Host smart-b94facaa-7d57-4071-8072-4a69ce7db751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522257464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.522257464
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3636237306
Short name T109
Test name
Test status
Simulation time 896673790971 ps
CPU time 1095.56 seconds
Started Jul 02 09:25:38 AM PDT 24
Finished Jul 02 09:43:55 AM PDT 24
Peak memory 230340 kb
Host smart-e8b91ba2-fa63-45bd-b4a7-b49d0f276e40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636237306 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3636237306
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3121012708
Short name T259
Test name
Test status
Simulation time 17470726891 ps
CPU time 8.06 seconds
Started Jul 02 09:25:39 AM PDT 24
Finished Jul 02 09:25:48 AM PDT 24
Peak memory 199924 kb
Host smart-1d1e848c-e8dd-4b7e-a935-71c2bae6064f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121012708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3121012708
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3456927893
Short name T886
Test name
Test status
Simulation time 47415720124 ps
CPU time 26.77 seconds
Started Jul 02 09:25:38 AM PDT 24
Finished Jul 02 09:26:06 AM PDT 24
Peak memory 200016 kb
Host smart-bab2d6c8-0240-48b4-8b4c-1efbf2761936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456927893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3456927893
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3239576833
Short name T346
Test name
Test status
Simulation time 19698917543 ps
CPU time 8.62 seconds
Started Jul 02 09:25:43 AM PDT 24
Finished Jul 02 09:25:52 AM PDT 24
Peak memory 199964 kb
Host smart-46816327-a780-4e7c-92e5-f39bc0676ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239576833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3239576833
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1936646797
Short name T242
Test name
Test status
Simulation time 134287967851 ps
CPU time 741.38 seconds
Started Jul 02 09:25:39 AM PDT 24
Finished Jul 02 09:38:01 AM PDT 24
Peak memory 216456 kb
Host smart-e220feca-4f72-4504-9998-c811e0fa54f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936646797 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1936646797
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2282916177
Short name T802
Test name
Test status
Simulation time 11905441350 ps
CPU time 17.13 seconds
Started Jul 02 09:25:38 AM PDT 24
Finished Jul 02 09:25:56 AM PDT 24
Peak memory 199932 kb
Host smart-e4a82b28-f1c2-4031-9085-ea034465a321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282916177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2282916177
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3355669183
Short name T106
Test name
Test status
Simulation time 7223022566 ps
CPU time 63.59 seconds
Started Jul 02 09:25:40 AM PDT 24
Finished Jul 02 09:26:44 AM PDT 24
Peak memory 216560 kb
Host smart-41b612f2-587e-42c8-b1ac-70e1ee47c202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355669183 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3355669183
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2897815344
Short name T805
Test name
Test status
Simulation time 41641972 ps
CPU time 0.56 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:23:08 AM PDT 24
Peak memory 194256 kb
Host smart-4f519bea-2c0e-4bb1-88ec-6fd007f350d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897815344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2897815344
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1583499578
Short name T837
Test name
Test status
Simulation time 118022798852 ps
CPU time 46.2 seconds
Started Jul 02 09:23:05 AM PDT 24
Finished Jul 02 09:23:52 AM PDT 24
Peak memory 199960 kb
Host smart-50aea049-38ba-4a0b-9dd6-742107fba613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583499578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1583499578
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2361703131
Short name T758
Test name
Test status
Simulation time 22923786215 ps
CPU time 9.89 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:23:24 AM PDT 24
Peak memory 199772 kb
Host smart-228f4739-8009-4843-8b63-02e1225e7f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361703131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2361703131
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1401715217
Short name T457
Test name
Test status
Simulation time 34632842596 ps
CPU time 26.58 seconds
Started Jul 02 09:23:05 AM PDT 24
Finished Jul 02 09:23:33 AM PDT 24
Peak memory 199904 kb
Host smart-822b00b7-8bad-4aea-b645-efe83019e35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401715217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1401715217
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3329432848
Short name T276
Test name
Test status
Simulation time 15812263188 ps
CPU time 32.88 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:23:47 AM PDT 24
Peak memory 199892 kb
Host smart-bf60b6e1-6ea0-4ac6-af23-9412807c0167
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329432848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3329432848
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3341147176
Short name T752
Test name
Test status
Simulation time 108580186041 ps
CPU time 240.04 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:27:20 AM PDT 24
Peak memory 199900 kb
Host smart-f3518bb6-5312-4636-b68e-32c0a1f9ed5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3341147176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3341147176
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1783875981
Short name T389
Test name
Test status
Simulation time 2261757075 ps
CPU time 3.86 seconds
Started Jul 02 09:23:11 AM PDT 24
Finished Jul 02 09:23:15 AM PDT 24
Peak memory 199012 kb
Host smart-c97136c8-5b95-4641-a2f2-4f22ee644df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783875981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1783875981
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.3476205744
Short name T610
Test name
Test status
Simulation time 21245760688 ps
CPU time 245.71 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:27:20 AM PDT 24
Peak memory 200004 kb
Host smart-507bdb74-41e4-4d54-8d58-29cb0a68e96b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476205744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3476205744
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.984476671
Short name T800
Test name
Test status
Simulation time 6239459685 ps
CPU time 55.27 seconds
Started Jul 02 09:23:05 AM PDT 24
Finished Jul 02 09:24:01 AM PDT 24
Peak memory 198912 kb
Host smart-10deab7b-142b-4218-98db-1baae11fd2a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984476671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.984476671
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3589194380
Short name T643
Test name
Test status
Simulation time 113247771470 ps
CPU time 157.4 seconds
Started Jul 02 09:23:20 AM PDT 24
Finished Jul 02 09:26:02 AM PDT 24
Peak memory 199960 kb
Host smart-8887523f-e7c7-4a7a-b53e-ceff6f45d319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589194380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3589194380
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3644969275
Short name T745
Test name
Test status
Simulation time 818328629 ps
CPU time 1.62 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:23:09 AM PDT 24
Peak memory 195556 kb
Host smart-78123657-a685-456a-bcb2-ce19178ff525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644969275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3644969275
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3009558666
Short name T674
Test name
Test status
Simulation time 6158607544 ps
CPU time 13.37 seconds
Started Jul 02 09:23:07 AM PDT 24
Finished Jul 02 09:23:22 AM PDT 24
Peak memory 199908 kb
Host smart-6a997936-7459-4415-a8d5-fdf4b8da7772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009558666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3009558666
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.78853379
Short name T833
Test name
Test status
Simulation time 18239676206 ps
CPU time 522.52 seconds
Started Jul 02 09:23:10 AM PDT 24
Finished Jul 02 09:31:53 AM PDT 24
Peak memory 199880 kb
Host smart-b6a08888-8ea9-4d95-a2cc-e93f4e72e01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78853379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.78853379
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2568386052
Short name T214
Test name
Test status
Simulation time 24811692078 ps
CPU time 272.58 seconds
Started Jul 02 09:23:11 AM PDT 24
Finished Jul 02 09:27:44 AM PDT 24
Peak memory 215540 kb
Host smart-e6acaf0b-e88f-4bf4-b434-ac0f77ce2d76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568386052 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2568386052
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1991439800
Short name T569
Test name
Test status
Simulation time 7247250581 ps
CPU time 14.45 seconds
Started Jul 02 09:23:05 AM PDT 24
Finished Jul 02 09:23:21 AM PDT 24
Peak memory 199928 kb
Host smart-32c2b9f7-6a22-4426-83cc-4f39a39bc62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991439800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1991439800
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.130277761
Short name T746
Test name
Test status
Simulation time 6149477050 ps
CPU time 10.29 seconds
Started Jul 02 09:23:15 AM PDT 24
Finished Jul 02 09:23:27 AM PDT 24
Peak memory 197580 kb
Host smart-00bca6a0-314e-4600-b51f-51cb49abf0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130277761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.130277761
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1706637813
Short name T204
Test name
Test status
Simulation time 27607056899 ps
CPU time 11.54 seconds
Started Jul 02 09:25:38 AM PDT 24
Finished Jul 02 09:25:51 AM PDT 24
Peak memory 200036 kb
Host smart-ca59c300-2c76-460e-b857-a1b257892f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706637813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1706637813
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2902089403
Short name T504
Test name
Test status
Simulation time 17667046463 ps
CPU time 33.55 seconds
Started Jul 02 09:25:38 AM PDT 24
Finished Jul 02 09:26:12 AM PDT 24
Peak memory 199976 kb
Host smart-2f76d377-cab6-4b40-a9fd-1225e67e2ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902089403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2902089403
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3330894362
Short name T924
Test name
Test status
Simulation time 23183916220 ps
CPU time 326.53 seconds
Started Jul 02 09:25:41 AM PDT 24
Finished Jul 02 09:31:08 AM PDT 24
Peak memory 216540 kb
Host smart-3e8e3ef0-dad0-4aee-b4f7-7844a28454ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330894362 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3330894362
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1823346695
Short name T284
Test name
Test status
Simulation time 69061394107 ps
CPU time 30.02 seconds
Started Jul 02 09:25:42 AM PDT 24
Finished Jul 02 09:26:12 AM PDT 24
Peak memory 200004 kb
Host smart-7b7eff41-820e-48a1-aea2-2e84a3f0363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823346695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1823346695
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.330152431
Short name T124
Test name
Test status
Simulation time 32336855230 ps
CPU time 614.37 seconds
Started Jul 02 09:25:46 AM PDT 24
Finished Jul 02 09:36:02 AM PDT 24
Peak memory 216536 kb
Host smart-330b264d-671c-4ab8-865c-888f886a68e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330152431 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.330152431
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2827587509
Short name T785
Test name
Test status
Simulation time 61825752914 ps
CPU time 31.6 seconds
Started Jul 02 09:25:43 AM PDT 24
Finished Jul 02 09:26:16 AM PDT 24
Peak memory 199936 kb
Host smart-c830d3ba-afd2-436d-8a6d-c369dd3a9364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827587509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2827587509
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3922415769
Short name T52
Test name
Test status
Simulation time 102291118255 ps
CPU time 320.72 seconds
Started Jul 02 09:25:41 AM PDT 24
Finished Jul 02 09:31:03 AM PDT 24
Peak memory 216544 kb
Host smart-a75ce193-5b38-4a1f-bece-20dc583844be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922415769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3922415769
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2902263636
Short name T916
Test name
Test status
Simulation time 165488437499 ps
CPU time 25.03 seconds
Started Jul 02 09:25:43 AM PDT 24
Finished Jul 02 09:26:09 AM PDT 24
Peak memory 199960 kb
Host smart-083afe82-0bd7-4711-8562-5f4979868330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902263636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2902263636
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3489218678
Short name T542
Test name
Test status
Simulation time 19005512587 ps
CPU time 31.41 seconds
Started Jul 02 09:25:43 AM PDT 24
Finished Jul 02 09:26:15 AM PDT 24
Peak memory 199784 kb
Host smart-ad95a33a-563d-412d-83b0-34c12ac56ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489218678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3489218678
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2890969252
Short name T825
Test name
Test status
Simulation time 15518240856 ps
CPU time 18.33 seconds
Started Jul 02 09:25:43 AM PDT 24
Finished Jul 02 09:26:01 AM PDT 24
Peak memory 199940 kb
Host smart-3c0bf9ad-e2e1-4299-9a9a-5b259fa719bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890969252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2890969252
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2415146140
Short name T840
Test name
Test status
Simulation time 115519771833 ps
CPU time 47.16 seconds
Started Jul 02 09:25:43 AM PDT 24
Finished Jul 02 09:26:30 AM PDT 24
Peak memory 199544 kb
Host smart-5e958673-13b7-474f-a96d-003aec4de5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415146140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2415146140
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1438199062
Short name T602
Test name
Test status
Simulation time 122698258085 ps
CPU time 183 seconds
Started Jul 02 09:25:42 AM PDT 24
Finished Jul 02 09:28:46 AM PDT 24
Peak memory 199968 kb
Host smart-0c280d87-2dfe-4049-aa0a-ed82130aa298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438199062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1438199062
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2831712912
Short name T579
Test name
Test status
Simulation time 56895366722 ps
CPU time 195.92 seconds
Started Jul 02 09:25:42 AM PDT 24
Finished Jul 02 09:28:59 AM PDT 24
Peak memory 215528 kb
Host smart-a09452b4-5458-4e1a-b261-51bb731774ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831712912 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2831712912
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.987182714
Short name T146
Test name
Test status
Simulation time 67295986687 ps
CPU time 22.16 seconds
Started Jul 02 09:25:44 AM PDT 24
Finished Jul 02 09:26:07 AM PDT 24
Peak memory 199504 kb
Host smart-f42a284e-0540-4615-8486-148d2adb7a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987182714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.987182714
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.904448352
Short name T921
Test name
Test status
Simulation time 79049987955 ps
CPU time 470.2 seconds
Started Jul 02 09:25:41 AM PDT 24
Finished Jul 02 09:33:32 AM PDT 24
Peak memory 211236 kb
Host smart-8099b497-5404-4466-ad08-3471d3b0c851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904448352 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.904448352
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1169843629
Short name T432
Test name
Test status
Simulation time 46633958 ps
CPU time 0.55 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:21 AM PDT 24
Peak memory 195280 kb
Host smart-d995cfaa-a20a-4523-869f-101f150c5a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169843629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1169843629
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.705217662
Short name T301
Test name
Test status
Simulation time 197105340206 ps
CPU time 562.7 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:32:37 AM PDT 24
Peak memory 199892 kb
Host smart-20c91a32-e294-4f62-92ae-2c0848e4e5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705217662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.705217662
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.4165304008
Short name T990
Test name
Test status
Simulation time 78555900022 ps
CPU time 53.85 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:24:13 AM PDT 24
Peak memory 199968 kb
Host smart-65beeb41-9ac2-45f5-a735-c48e2e74345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165304008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.4165304008
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2457847606
Short name T316
Test name
Test status
Simulation time 184628057139 ps
CPU time 48.92 seconds
Started Jul 02 09:23:07 AM PDT 24
Finished Jul 02 09:23:57 AM PDT 24
Peak memory 199940 kb
Host smart-f7b21df4-9a72-43e7-a935-602ce21c37b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457847606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2457847606
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2364853963
Short name T306
Test name
Test status
Simulation time 71706488659 ps
CPU time 305.29 seconds
Started Jul 02 09:23:11 AM PDT 24
Finished Jul 02 09:28:17 AM PDT 24
Peak memory 199996 kb
Host smart-6c1b1cba-a1f5-49c4-a857-1933f5b5c56d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364853963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2364853963
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.365834500
Short name T680
Test name
Test status
Simulation time 94044979120 ps
CPU time 856.45 seconds
Started Jul 02 09:23:14 AM PDT 24
Finished Jul 02 09:37:32 AM PDT 24
Peak memory 199976 kb
Host smart-3c9dae0c-dcde-4658-ad70-6bfe53828dab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365834500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.365834500
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1821611566
Short name T445
Test name
Test status
Simulation time 7705644269 ps
CPU time 3.26 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:23:17 AM PDT 24
Peak memory 199920 kb
Host smart-5218597e-cb94-44c3-9694-19080a2c02a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821611566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1821611566
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.1496684940
Short name T532
Test name
Test status
Simulation time 6491433754 ps
CPU time 325.73 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:28:48 AM PDT 24
Peak memory 199924 kb
Host smart-975a0d0b-3bdc-4f5e-8882-5e8da2d179ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496684940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1496684940
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3536097759
Short name T652
Test name
Test status
Simulation time 5351935105 ps
CPU time 11.01 seconds
Started Jul 02 09:23:15 AM PDT 24
Finished Jul 02 09:23:27 AM PDT 24
Peak memory 199192 kb
Host smart-018bc8ea-0073-48b5-8958-8ed6f6627cdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536097759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3536097759
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.773200014
Short name T430
Test name
Test status
Simulation time 15885556066 ps
CPU time 19.21 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:41 AM PDT 24
Peak memory 199556 kb
Host smart-5be62341-ab1a-461f-ad9b-cedf3fac41f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773200014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.773200014
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2102040941
Short name T727
Test name
Test status
Simulation time 3391741566 ps
CPU time 5.67 seconds
Started Jul 02 09:23:11 AM PDT 24
Finished Jul 02 09:23:18 AM PDT 24
Peak memory 196036 kb
Host smart-723311d7-df3f-4410-8067-873de3d196ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102040941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2102040941
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1792623806
Short name T494
Test name
Test status
Simulation time 122926185 ps
CPU time 0.77 seconds
Started Jul 02 09:23:04 AM PDT 24
Finished Jul 02 09:23:06 AM PDT 24
Peak memory 196948 kb
Host smart-7dda869b-19bc-4aae-bab8-f068aa529d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792623806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1792623806
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1796626962
Short name T209
Test name
Test status
Simulation time 174297811969 ps
CPU time 134.78 seconds
Started Jul 02 09:23:14 AM PDT 24
Finished Jul 02 09:25:30 AM PDT 24
Peak memory 199904 kb
Host smart-3597afb7-41fd-4d33-8a40-849236730dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796626962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1796626962
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3186756717
Short name T1072
Test name
Test status
Simulation time 765519703762 ps
CPU time 716.09 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:35:18 AM PDT 24
Peak memory 216476 kb
Host smart-3268ef11-3e82-40b5-a8b4-4ca8faab4e23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186756717 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3186756717
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.951411981
Short name T18
Test name
Test status
Simulation time 947783671 ps
CPU time 3.12 seconds
Started Jul 02 09:23:16 AM PDT 24
Finished Jul 02 09:23:20 AM PDT 24
Peak memory 198880 kb
Host smart-917960f6-cbb5-47a6-9110-57f1d8eca5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951411981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.951411981
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1723297369
Short name T725
Test name
Test status
Simulation time 132020516716 ps
CPU time 122.2 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:25:10 AM PDT 24
Peak memory 199996 kb
Host smart-664faf81-6b1f-42d9-9249-3abb9d031b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723297369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1723297369
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2477684549
Short name T839
Test name
Test status
Simulation time 101244108893 ps
CPU time 46.02 seconds
Started Jul 02 09:25:44 AM PDT 24
Finished Jul 02 09:26:31 AM PDT 24
Peak memory 199932 kb
Host smart-45eb2f56-e67c-4cbc-a10e-6826712b535d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477684549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2477684549
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.575245224
Short name T890
Test name
Test status
Simulation time 350680430032 ps
CPU time 238.97 seconds
Started Jul 02 09:25:40 AM PDT 24
Finished Jul 02 09:29:40 AM PDT 24
Peak memory 216548 kb
Host smart-97716682-5f02-427a-845a-967b32fcef63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575245224 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.575245224
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1409854603
Short name T648
Test name
Test status
Simulation time 47796158388 ps
CPU time 24.6 seconds
Started Jul 02 09:25:45 AM PDT 24
Finished Jul 02 09:26:10 AM PDT 24
Peak memory 199960 kb
Host smart-35b578bc-8fc5-46f4-8cd9-f82e185536cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409854603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1409854603
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.920883763
Short name T938
Test name
Test status
Simulation time 58870481915 ps
CPU time 24.93 seconds
Started Jul 02 09:25:43 AM PDT 24
Finished Jul 02 09:26:09 AM PDT 24
Peak memory 199872 kb
Host smart-ae33aae8-3437-4c16-9382-d62d4699510a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920883763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.920883763
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.40077372
Short name T31
Test name
Test status
Simulation time 143067187533 ps
CPU time 373.26 seconds
Started Jul 02 09:25:44 AM PDT 24
Finished Jul 02 09:31:58 AM PDT 24
Peak memory 216472 kb
Host smart-2552a711-a619-46b2-8d67-f72a36ae59e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077372 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.40077372
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2600568324
Short name T11
Test name
Test status
Simulation time 71856990522 ps
CPU time 102.23 seconds
Started Jul 02 09:25:46 AM PDT 24
Finished Jul 02 09:27:29 AM PDT 24
Peak memory 199972 kb
Host smart-48175266-0907-45e4-8810-1f2e536577e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600568324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2600568324
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3296408828
Short name T850
Test name
Test status
Simulation time 402372036852 ps
CPU time 472.98 seconds
Started Jul 02 09:25:49 AM PDT 24
Finished Jul 02 09:33:42 AM PDT 24
Peak memory 216376 kb
Host smart-06db2de2-d2d9-45b8-aba8-1fbe52c7de6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296408828 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3296408828
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3025025000
Short name T46
Test name
Test status
Simulation time 49029426774 ps
CPU time 17.82 seconds
Started Jul 02 09:25:48 AM PDT 24
Finished Jul 02 09:26:07 AM PDT 24
Peak memory 199996 kb
Host smart-c9f653f9-610d-416e-ae1e-2b8dbe2ed083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025025000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3025025000
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3138027339
Short name T338
Test name
Test status
Simulation time 363929447075 ps
CPU time 747.98 seconds
Started Jul 02 09:25:47 AM PDT 24
Finished Jul 02 09:38:16 AM PDT 24
Peak memory 216456 kb
Host smart-2f3c1b6d-eb0e-47ef-aa5d-9579393517c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138027339 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3138027339
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.4257179518
Short name T1080
Test name
Test status
Simulation time 110598535110 ps
CPU time 175.86 seconds
Started Jul 02 09:25:47 AM PDT 24
Finished Jul 02 09:28:44 AM PDT 24
Peak memory 199904 kb
Host smart-b035faca-b3cf-44e3-81a4-58a05d08da91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257179518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.4257179518
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2652318753
Short name T110
Test name
Test status
Simulation time 47463338883 ps
CPU time 397.63 seconds
Started Jul 02 09:25:46 AM PDT 24
Finished Jul 02 09:32:25 AM PDT 24
Peak memory 212784 kb
Host smart-4fdd3f70-737d-41bc-bd5b-bae32dd502a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652318753 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2652318753
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1041942043
Short name T1037
Test name
Test status
Simulation time 65298992456 ps
CPU time 28.16 seconds
Started Jul 02 09:25:46 AM PDT 24
Finished Jul 02 09:26:15 AM PDT 24
Peak memory 198888 kb
Host smart-f1285ab0-b52e-44aa-837c-7996efd4045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041942043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1041942043
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3341976132
Short name T350
Test name
Test status
Simulation time 11032493671 ps
CPU time 18.49 seconds
Started Jul 02 09:25:47 AM PDT 24
Finished Jul 02 09:26:07 AM PDT 24
Peak memory 199924 kb
Host smart-a89655c2-391c-4608-ba21-9b11ae9a9764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341976132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3341976132
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1557682292
Short name T999
Test name
Test status
Simulation time 160352150512 ps
CPU time 56.67 seconds
Started Jul 02 09:25:46 AM PDT 24
Finished Jul 02 09:26:44 AM PDT 24
Peak memory 200000 kb
Host smart-b09b9151-6ee1-46e2-b6dd-874ed8124d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557682292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1557682292
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.487296100
Short name T30
Test name
Test status
Simulation time 11179462110 ps
CPU time 95.72 seconds
Started Jul 02 09:25:48 AM PDT 24
Finished Jul 02 09:27:25 AM PDT 24
Peak memory 216448 kb
Host smart-5205580a-1151-4332-b1e8-d307e0b1653d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487296100 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.487296100
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3623354955
Short name T580
Test name
Test status
Simulation time 58053579164 ps
CPU time 55.8 seconds
Started Jul 02 09:25:47 AM PDT 24
Finished Jul 02 09:26:44 AM PDT 24
Peak memory 199956 kb
Host smart-fa274b75-93d8-433e-9076-7d7150946fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623354955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3623354955
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.4069667265
Short name T1068
Test name
Test status
Simulation time 418974809758 ps
CPU time 600.46 seconds
Started Jul 02 09:25:48 AM PDT 24
Finished Jul 02 09:35:49 AM PDT 24
Peak memory 216504 kb
Host smart-d48f024b-ac80-422b-a0a8-fa5dd6e8cdf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069667265 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.4069667265
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2705472419
Short name T995
Test name
Test status
Simulation time 26686515 ps
CPU time 0.57 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:21 AM PDT 24
Peak memory 195272 kb
Host smart-e0e46961-080e-44a3-9909-67e75a2dd67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705472419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2705472419
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.487722634
Short name T755
Test name
Test status
Simulation time 235658828109 ps
CPU time 526.85 seconds
Started Jul 02 09:23:11 AM PDT 24
Finished Jul 02 09:31:58 AM PDT 24
Peak memory 200008 kb
Host smart-2311ecb8-5af7-418e-b373-9d56d401dc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487722634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.487722634
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.856532841
Short name T679
Test name
Test status
Simulation time 137305029509 ps
CPU time 112.55 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:25:06 AM PDT 24
Peak memory 200160 kb
Host smart-20b3b40d-81d7-4255-9bda-618d4490796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856532841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.856532841
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2301776842
Short name T1033
Test name
Test status
Simulation time 123513148856 ps
CPU time 37.61 seconds
Started Jul 02 09:23:12 AM PDT 24
Finished Jul 02 09:23:51 AM PDT 24
Peak memory 199924 kb
Host smart-1e0577bc-6bd6-469a-90d4-1ece5cd70d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301776842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2301776842
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.353063938
Short name T14
Test name
Test status
Simulation time 44384109642 ps
CPU time 10.88 seconds
Started Jul 02 09:23:12 AM PDT 24
Finished Jul 02 09:23:23 AM PDT 24
Peak memory 199916 kb
Host smart-f33787e7-5b80-44b6-8b6a-305aad5145db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353063938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.353063938
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1228567550
Short name T717
Test name
Test status
Simulation time 124372225923 ps
CPU time 765.68 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:36:00 AM PDT 24
Peak memory 199976 kb
Host smart-694ceeda-a0c9-45ae-bbbc-6983bf3c8464
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1228567550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1228567550
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.193506696
Short name T815
Test name
Test status
Simulation time 5905029276 ps
CPU time 7.24 seconds
Started Jul 02 09:23:12 AM PDT 24
Finished Jul 02 09:23:20 AM PDT 24
Peak memory 199604 kb
Host smart-6e849710-9907-4826-b366-630bede2c622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193506696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.193506696
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.1944124386
Short name T699
Test name
Test status
Simulation time 13774072342 ps
CPU time 179.77 seconds
Started Jul 02 09:23:08 AM PDT 24
Finished Jul 02 09:26:09 AM PDT 24
Peak memory 199908 kb
Host smart-bbf09fe6-9bcd-4a5f-95e6-943fe01ae368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944124386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1944124386
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1664591523
Short name T361
Test name
Test status
Simulation time 2863062260 ps
CPU time 5.64 seconds
Started Jul 02 09:23:18 AM PDT 24
Finished Jul 02 09:23:27 AM PDT 24
Peak memory 199052 kb
Host smart-b32ed2a8-4af2-43dc-a9bf-ab5b32533582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1664591523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1664591523
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2023125926
Short name T897
Test name
Test status
Simulation time 147613032190 ps
CPU time 90.11 seconds
Started Jul 02 09:23:12 AM PDT 24
Finished Jul 02 09:24:43 AM PDT 24
Peak memory 199864 kb
Host smart-d24ac6cb-32f9-48ca-a6ae-2c6c6d43487c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023125926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2023125926
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.361576583
Short name T509
Test name
Test status
Simulation time 35620281230 ps
CPU time 13.48 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:36 AM PDT 24
Peak memory 195760 kb
Host smart-0112fa2f-d0ec-4b6c-bc8f-0b02d0f11ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361576583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.361576583
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2782875355
Short name T285
Test name
Test status
Simulation time 296894823 ps
CPU time 1.12 seconds
Started Jul 02 09:23:16 AM PDT 24
Finished Jul 02 09:23:18 AM PDT 24
Peak memory 198588 kb
Host smart-13063bd2-8b52-488b-8049-ce87e78c1335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782875355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2782875355
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.259402067
Short name T294
Test name
Test status
Simulation time 8311809308 ps
CPU time 9.34 seconds
Started Jul 02 09:23:12 AM PDT 24
Finished Jul 02 09:23:23 AM PDT 24
Peak memory 199204 kb
Host smart-4f5e3887-6868-487c-8708-d9f959f4bdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259402067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.259402067
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.787433111
Short name T567
Test name
Test status
Simulation time 159157950063 ps
CPU time 32.2 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:54 AM PDT 24
Peak memory 199884 kb
Host smart-8197a658-7333-4c63-a530-0850d43aca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787433111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.787433111
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3624061487
Short name T873
Test name
Test status
Simulation time 322399298049 ps
CPU time 56.91 seconds
Started Jul 02 09:25:51 AM PDT 24
Finished Jul 02 09:26:49 AM PDT 24
Peak memory 199948 kb
Host smart-ee591635-36d5-4d82-b491-eb49aefed9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624061487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3624061487
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2378502244
Short name T500
Test name
Test status
Simulation time 28532468345 ps
CPU time 46.56 seconds
Started Jul 02 09:25:50 AM PDT 24
Finished Jul 02 09:26:37 AM PDT 24
Peak memory 199864 kb
Host smart-1a0b5852-5e82-40d5-880a-5d94120877d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378502244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2378502244
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.874696649
Short name T143
Test name
Test status
Simulation time 207050352115 ps
CPU time 95.41 seconds
Started Jul 02 09:25:50 AM PDT 24
Finished Jul 02 09:27:26 AM PDT 24
Peak memory 199904 kb
Host smart-404cea6d-d652-411f-9839-40f98766a550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874696649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.874696649
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.289912623
Short name T479
Test name
Test status
Simulation time 29632733757 ps
CPU time 11.67 seconds
Started Jul 02 09:25:50 AM PDT 24
Finished Jul 02 09:26:02 AM PDT 24
Peak memory 199904 kb
Host smart-8a77e30a-d3a2-43e8-8992-4bcd744c46c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289912623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.289912623
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1791806803
Short name T816
Test name
Test status
Simulation time 18640285130 ps
CPU time 176.13 seconds
Started Jul 02 09:25:51 AM PDT 24
Finished Jul 02 09:28:48 AM PDT 24
Peak memory 215548 kb
Host smart-70855807-e3ed-4444-8a63-a8d2394da91e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791806803 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1791806803
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1380300880
Short name T951
Test name
Test status
Simulation time 28168695784 ps
CPU time 11.15 seconds
Started Jul 02 09:25:50 AM PDT 24
Finished Jul 02 09:26:02 AM PDT 24
Peak memory 199692 kb
Host smart-a120d714-012c-4d0f-9f09-f6fa6fa60d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380300880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1380300880
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.611114259
Short name T54
Test name
Test status
Simulation time 300148130685 ps
CPU time 1201.37 seconds
Started Jul 02 09:25:52 AM PDT 24
Finished Jul 02 09:45:54 AM PDT 24
Peak memory 228576 kb
Host smart-78b193d1-ba7e-4b28-b3f3-d9614dce8928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611114259 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.611114259
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1424552071
Short name T691
Test name
Test status
Simulation time 89339436308 ps
CPU time 60.92 seconds
Started Jul 02 09:25:51 AM PDT 24
Finished Jul 02 09:26:53 AM PDT 24
Peak memory 200012 kb
Host smart-fe12d184-1f56-435f-b25a-99a0ec0ca6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424552071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1424552071
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2489823329
Short name T243
Test name
Test status
Simulation time 123714919508 ps
CPU time 192.31 seconds
Started Jul 02 09:25:50 AM PDT 24
Finished Jul 02 09:29:03 AM PDT 24
Peak memory 199816 kb
Host smart-aeecd70e-c46c-4723-9b3d-bf9a3c30a53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489823329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2489823329
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2832602135
Short name T791
Test name
Test status
Simulation time 71957906057 ps
CPU time 475.9 seconds
Started Jul 02 09:25:56 AM PDT 24
Finished Jul 02 09:33:53 AM PDT 24
Peak memory 216612 kb
Host smart-33344f4d-398c-4634-97dd-e83b0b38f3bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832602135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2832602135
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3533846399
Short name T423
Test name
Test status
Simulation time 11922786783 ps
CPU time 19.93 seconds
Started Jul 02 09:25:56 AM PDT 24
Finished Jul 02 09:26:17 AM PDT 24
Peak memory 199940 kb
Host smart-2a4862bf-ce5b-45a9-b45f-a127b4101987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533846399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3533846399
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2703507602
Short name T997
Test name
Test status
Simulation time 68372710 ps
CPU time 0.53 seconds
Started Jul 02 09:23:08 AM PDT 24
Finished Jul 02 09:23:10 AM PDT 24
Peak memory 195300 kb
Host smart-f41b7614-274a-4223-95f3-733135da13c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703507602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2703507602
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2606301430
Short name T1079
Test name
Test status
Simulation time 87501416172 ps
CPU time 19.04 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:23:27 AM PDT 24
Peak memory 199880 kb
Host smart-9dd81901-56d6-462d-b937-8261bbe6d629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606301430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2606301430
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.769441677
Short name T451
Test name
Test status
Simulation time 27088917132 ps
CPU time 10.97 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:23:34 AM PDT 24
Peak memory 198604 kb
Host smart-cac333f2-c2bd-4467-af2f-c7741146c960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769441677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.769441677
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3901617067
Short name T255
Test name
Test status
Simulation time 112523262726 ps
CPU time 32.09 seconds
Started Jul 02 09:23:11 AM PDT 24
Finished Jul 02 09:23:44 AM PDT 24
Peak memory 199884 kb
Host smart-6bc08bdc-0cd1-43f9-a66a-889b0ff5ddc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901617067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3901617067
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2137132581
Short name T261
Test name
Test status
Simulation time 31832278187 ps
CPU time 56.13 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:24:04 AM PDT 24
Peak memory 199264 kb
Host smart-4dc43c4d-0c83-4fe9-bedb-cfe3bd1f1d7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137132581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2137132581
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1126258792
Short name T409
Test name
Test status
Simulation time 102162959467 ps
CPU time 157.99 seconds
Started Jul 02 09:23:19 AM PDT 24
Finished Jul 02 09:26:01 AM PDT 24
Peak memory 199932 kb
Host smart-c5ae3df0-3248-4cff-8f43-c6b91164016e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126258792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1126258792
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2534528855
Short name T398
Test name
Test status
Simulation time 8025711485 ps
CPU time 12.98 seconds
Started Jul 02 09:23:08 AM PDT 24
Finished Jul 02 09:23:22 AM PDT 24
Peak memory 199800 kb
Host smart-01d2e5e0-d976-4317-ad02-c512ddde7239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534528855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2534528855
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.428811535
Short name T455
Test name
Test status
Simulation time 19936558619 ps
CPU time 1126.64 seconds
Started Jul 02 09:23:06 AM PDT 24
Finished Jul 02 09:41:54 AM PDT 24
Peak memory 199872 kb
Host smart-7801a94f-9c73-4232-83e3-9b1249582685
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428811535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.428811535
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3220311451
Short name T909
Test name
Test status
Simulation time 4836047034 ps
CPU time 43 seconds
Started Jul 02 09:23:12 AM PDT 24
Finished Jul 02 09:23:57 AM PDT 24
Peak memory 198204 kb
Host smart-51343889-82ce-4845-831d-d2943399b12f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220311451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3220311451
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.874185061
Short name T329
Test name
Test status
Simulation time 216279595542 ps
CPU time 102.19 seconds
Started Jul 02 09:23:13 AM PDT 24
Finished Jul 02 09:24:56 AM PDT 24
Peak memory 199988 kb
Host smart-dba917a8-f7b5-4cfb-a852-f8aee94b6920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874185061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.874185061
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3732170687
Short name T262
Test name
Test status
Simulation time 40305984788 ps
CPU time 52.42 seconds
Started Jul 02 09:23:08 AM PDT 24
Finished Jul 02 09:24:02 AM PDT 24
Peak memory 195756 kb
Host smart-63bb94d7-066a-4e8e-9b0e-7d62707ce140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732170687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3732170687
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.797706491
Short name T612
Test name
Test status
Simulation time 281717708 ps
CPU time 0.91 seconds
Started Jul 02 09:23:17 AM PDT 24
Finished Jul 02 09:23:20 AM PDT 24
Peak memory 198512 kb
Host smart-54866f78-5e1c-49b2-b4fc-8ca8beb8611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797706491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.797706491
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1370644663
Short name T330
Test name
Test status
Simulation time 13006947109 ps
CPU time 4.08 seconds
Started Jul 02 09:23:15 AM PDT 24
Finished Jul 02 09:23:21 AM PDT 24
Peak memory 199260 kb
Host smart-67f3f9ec-0889-44f4-98c5-dffe07462a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370644663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1370644663
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3364621782
Short name T750
Test name
Test status
Simulation time 63925563773 ps
CPU time 114.07 seconds
Started Jul 02 09:23:16 AM PDT 24
Finished Jul 02 09:25:12 AM PDT 24
Peak memory 199956 kb
Host smart-0c0d473e-42b9-4722-9b4f-3181665195b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364621782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3364621782
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2794270605
Short name T893
Test name
Test status
Simulation time 40035079780 ps
CPU time 54.29 seconds
Started Jul 02 09:25:54 AM PDT 24
Finished Jul 02 09:26:49 AM PDT 24
Peak memory 200004 kb
Host smart-28d2ba7d-eefb-49f5-8699-7e6d15dc0f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794270605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2794270605
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1429499078
Short name T67
Test name
Test status
Simulation time 66529364200 ps
CPU time 714.47 seconds
Started Jul 02 09:25:56 AM PDT 24
Finished Jul 02 09:37:51 AM PDT 24
Peak memory 224696 kb
Host smart-05559eb5-c819-460f-98c0-2ca0095b647c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429499078 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1429499078
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2755363663
Short name T219
Test name
Test status
Simulation time 67455094071 ps
CPU time 17.16 seconds
Started Jul 02 09:25:56 AM PDT 24
Finished Jul 02 09:26:14 AM PDT 24
Peak memory 199952 kb
Host smart-a72040cf-d5bd-4c83-ad9d-e33468db0ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755363663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2755363663
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.736748541
Short name T147
Test name
Test status
Simulation time 92910509120 ps
CPU time 542.73 seconds
Started Jul 02 09:25:53 AM PDT 24
Finished Jul 02 09:34:56 AM PDT 24
Peak memory 213236 kb
Host smart-88d60009-9c50-46b6-9188-736101837fc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736748541 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.736748541
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.156098194
Short name T193
Test name
Test status
Simulation time 129686760983 ps
CPU time 35.31 seconds
Started Jul 02 09:26:00 AM PDT 24
Finished Jul 02 09:26:36 AM PDT 24
Peak memory 199936 kb
Host smart-3988b613-171b-41d4-915b-0ec76b3c34b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156098194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.156098194
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3220565164
Short name T202
Test name
Test status
Simulation time 83376133281 ps
CPU time 41.11 seconds
Started Jul 02 09:25:59 AM PDT 24
Finished Jul 02 09:26:41 AM PDT 24
Peak memory 200152 kb
Host smart-323b5cd9-fd90-4c38-8c6d-06b8183fbddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220565164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3220565164
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2201736635
Short name T226
Test name
Test status
Simulation time 99793934900 ps
CPU time 37.43 seconds
Started Jul 02 09:25:59 AM PDT 24
Finished Jul 02 09:26:38 AM PDT 24
Peak memory 199764 kb
Host smart-bd4d1aa7-5a40-4ad7-a566-49a60f028765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201736635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2201736635
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3541950984
Short name T562
Test name
Test status
Simulation time 45068393397 ps
CPU time 58.38 seconds
Started Jul 02 09:25:58 AM PDT 24
Finished Jul 02 09:26:57 AM PDT 24
Peak memory 199988 kb
Host smart-c23cfc32-67e1-4efe-8ade-bc52efee2618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541950984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3541950984
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2240617343
Short name T609
Test name
Test status
Simulation time 91274987114 ps
CPU time 53.51 seconds
Started Jul 02 09:26:00 AM PDT 24
Finished Jul 02 09:26:54 AM PDT 24
Peak memory 199912 kb
Host smart-74af9521-6460-46db-a666-1c1130f4fe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240617343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2240617343
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2433372294
Short name T238
Test name
Test status
Simulation time 130117731665 ps
CPU time 133.47 seconds
Started Jul 02 09:25:58 AM PDT 24
Finished Jul 02 09:28:12 AM PDT 24
Peak memory 199992 kb
Host smart-8958e252-7eed-40da-acd9-94a5f5a81dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433372294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2433372294
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.855878174
Short name T539
Test name
Test status
Simulation time 101975455873 ps
CPU time 246.34 seconds
Started Jul 02 09:26:00 AM PDT 24
Finished Jul 02 09:30:07 AM PDT 24
Peak memory 216500 kb
Host smart-347d61e8-c9e4-487d-9d00-eaadc6f241fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855878174 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.855878174
Directory /workspace/97.uart_stress_all_with_rand_reset/latest
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