Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	93654	1			T1	1		T2	24		T4	89
all_values[1]	93654	1			T1	1		T2	24		T4	89
all_values[2]	93654	1			T1	1		T2	24		T4	89
all_values[3]	93654	1			T1	1		T2	24		T4	89
all_values[4]	93654	1			T1	1		T2	24		T4	89
all_values[5]	93654	1			T1	1		T2	24		T4	89
all_values[6]	93654	1			T1	1		T2	24		T4	89
all_values[7]	93654	1			T1	1		T2	24		T4	89
all_values[8]	93654	1			T1	1		T2	24		T4	89

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

433534

1

T1

5

T2

38

T4

298

auto[1]

409352

1

T1

4

T2

178

T4

503

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

765733

1

T1

7

T2

204

T4

640

auto[1]

77153

1

T1

2

T2

12

T4

161

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27986	1			T2	8		T8	16		T12	2
all_values[0]	auto[0]	auto[1]	19312	1			T1	1		T2	2		T4	13
all_values[0]	auto[1]	auto[0]	26604	1			T2	13		T4	7		T6	24
all_values[0]	auto[1]	auto[1]	19752	1			T2	1		T4	69		T6	50
all_values[1]	auto[0]	auto[0]	50299	1			T2	14		T4	15		T6	30
all_values[1]	auto[0]	auto[1]	1438	1			T6	9		T13	8		T16	9
all_values[1]	auto[1]	auto[0]	40611	1			T1	1		T2	10		T4	74
all_values[1]	auto[1]	auto[1]	1306	1			T8	8		T16	1		T15	11
all_values[2]	auto[0]	auto[0]	47584	1			T1	1		T4	42		T5	1
all_values[2]	auto[0]	auto[1]	2299	1			T4	1		T6	1		T7	1
all_values[2]	auto[1]	auto[0]	41795	1			T2	18		T4	39		T6	71
all_values[2]	auto[1]	auto[1]	1976	1			T2	6		T4	7		T6	3
all_values[3]	auto[0]	auto[0]	44446	1			T1	1		T4	56		T5	1
all_values[3]	auto[0]	auto[1]	269	1			T14	3		T16	3		T71	2
all_values[3]	auto[1]	auto[0]	48712	1			T2	24		T4	33		T6	5
all_values[3]	auto[1]	auto[1]	227	1			T14	1		T15	2		T71	1
all_values[4]	auto[0]	auto[0]	47423	1			T1	1		T4	46		T6	73
all_values[4]	auto[0]	auto[1]	263	1			T8	1		T71	2		T21	7
all_values[4]	auto[1]	auto[0]	45596	1			T2	24		T4	43		T5	1
all_values[4]	auto[1]	auto[1]	372	1			T8	12		T15	1		T18	15
all_values[5]	auto[0]	auto[0]	48885	1			T4	33		T5	1		T7	2
all_values[5]	auto[0]	auto[1]	128	1			T16	2		T71	2		T21	6
all_values[5]	auto[1]	auto[0]	44493	1			T1	1		T2	24		T4	56
all_values[5]	auto[1]	auto[1]	148	1			T16	1		T71	1		T21	5
all_values[6]	auto[0]	auto[0]	48292	1			T4	31		T5	1		T6	39
all_values[6]	auto[0]	auto[1]	145	1			T21	6		T31	3		T231	1
all_values[6]	auto[1]	auto[0]	45071	1			T1	1		T2	24		T4	58
all_values[6]	auto[1]	auto[1]	146	1			T21	6		T72	3		T29	5
all_values[7]	auto[0]	auto[0]	45333	1			T4	56		T6	36		T7	2
all_values[7]	auto[0]	auto[1]	265	1			T8	2		T16	3		T71	4
all_values[7]	auto[1]	auto[0]	47808	1			T1	1		T2	24		T4	33
all_values[7]	auto[1]	auto[1]	248	1			T16	1		T71	2		T21	4
all_values[8]	auto[0]	auto[0]	34148	1			T2	13		T4	4		T8	73
all_values[8]	auto[0]	auto[1]	15019	1			T1	1		T2	1		T4	1
all_values[8]	auto[1]	auto[0]	30647	1			T2	8		T4	14		T6	72
all_values[8]	auto[1]	auto[1]	13840	1			T2	2		T4	70		T5	1