Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2098

1

T1

1

T2

1

T3

11

auto[UartRx]

2098

1

T1

1

T2

1

T3

11

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3823	1			T1	2		T2	2		T3	22
values[1]	32	1			T16	2		T15	1		T31	1
values[2]	36	1			T8	2		T28	1		T31	1
values[3]	31	1			T16	1		T15	1		T21	1
values[4]	30	1			T15	1		T28	1		T30	1
values[5]	40	1			T8	1		T16	1		T28	1
values[6]	38	1			T8	1		T16	1		T27	1
values[7]	32	1			T8	1		T27	1		T28	4
values[8]	32	1			T8	1		T15	2		T21	2
values[9]	43	1			T8	2		T16	2		T21	2
values[10]	40	1			T8	2		T16	1		T21	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	1984	1			T1	1		T2	1		T3	11
auto[UartTx]	values[1]	11	1			T44	1		T332	2		T45	1
auto[UartTx]	values[2]	8	1			T326	1		T144	1		T333	1
auto[UartTx]	values[3]	9	1			T15	1		T31	1		T334	1
auto[UartTx]	values[4]	7	1			T335	1		T336	1		T337	1
auto[UartTx]	values[5]	17	1			T16	1		T28	1		T32	1
auto[UartTx]	values[6]	8	1			T8	1		T84	1		T338	1
auto[UartTx]	values[7]	10	1			T27	1		T28	1		T29	1
auto[UartTx]	values[8]	6	1			T29	1		T83	1		T42	1
auto[UartTx]	values[9]	18	1			T8	2		T16	2		T21	1
auto[UartTx]	values[10]	17	1			T21	1		T28	1		T29	3
auto[UartRx]	values[0]	1839	1			T1	1		T2	1		T3	11
auto[UartRx]	values[1]	21	1			T16	2		T15	1		T31	1
auto[UartRx]	values[2]	28	1			T8	2		T28	1		T31	1
auto[UartRx]	values[3]	22	1			T16	1		T21	1		T28	1
auto[UartRx]	values[4]	23	1			T15	1		T28	1		T30	1
auto[UartRx]	values[5]	23	1			T8	1		T29	1		T32	1
auto[UartRx]	values[6]	30	1			T16	1		T27	1		T29	2
auto[UartRx]	values[7]	22	1			T8	1		T28	3		T29	1
auto[UartRx]	values[8]	26	1			T8	1		T15	2		T21	2
auto[UartRx]	values[9]	25	1			T21	1		T29	1		T31	1
auto[UartRx]	values[10]	23	1			T8	2		T16	1		T21	1