Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2071	1			T4	3		T5	1		T6	2
auto[BaudRate115200]	1720	1			T1	3		T2	2		T7	1
auto[BaudRate230400]	1643	1			T1	6		T2	1		T4	1
auto[BaudRate128Kbps]	1625	1			T1	3		T4	3		T6	3
auto[BaudRate256Kbps]	1912	1			T2	1		T4	1		T6	1
auto[BaudRate1Mbps]	1482	1			T2	1		T7	1		T8	11
auto[BaudRate1p5Mbps]	1073	1			T2	1		T6	2		T8	16

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1075	1			T4	8		T12	9		T40	2
freqs[25]	1080	1			T14	9		T108	10		T161	6
freqs[48]	458	1			T2	6		T303	2		T292	2
freqs[50]	464	1			T5	1		T105	8		T277	2
freqs[100]	881	1			T7	2		T11	3		T265	6

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	212	1			T4	3		T12	4		T247	2
auto[BaudRate9600]	freqs[25]	205	1			T14	1		T108	1		T339	19
auto[BaudRate9600]	freqs[48]	52	1			T303	1		T292	1		T159	1
auto[BaudRate9600]	freqs[50]	58	1			T5	1		T105	1		T20	2
auto[BaudRate9600]	freqs[100]	137	1			T11	1		T265	2		T295	1
auto[BaudRate115200]	freqs[24]	163	1			T12	1		T247	1		T89	2
auto[BaudRate115200]	freqs[25]	167	1			T14	2		T108	2		T131	1
auto[BaudRate115200]	freqs[48]	57	1			T2	2		T120	2		T262	3
auto[BaudRate115200]	freqs[50]	63	1			T105	1		T20	5		T340	3
auto[BaudRate115200]	freqs[100]	136	1			T7	1		T330	3		T271	2
auto[BaudRate230400]	freqs[24]	145	1			T4	1		T278	1		T89	4
auto[BaudRate230400]	freqs[25]	150	1			T14	2		T108	1		T161	1
auto[BaudRate230400]	freqs[48]	67	1			T2	1		T159	4		T120	3
auto[BaudRate230400]	freqs[50]	71	1			T105	1		T20	3		T340	3
auto[BaudRate230400]	freqs[100]	125	1			T295	1		T330	1		T31	9
auto[BaudRate128Kbps]	freqs[24]	181	1			T4	3		T40	1		T247	2
auto[BaudRate128Kbps]	freqs[25]	139	1			T14	1		T108	2		T161	2
auto[BaudRate128Kbps]	freqs[48]	78	1			T292	1		T159	1		T120	1
auto[BaudRate128Kbps]	freqs[50]	52	1			T105	1		T277	1		T20	2
auto[BaudRate128Kbps]	freqs[100]	95	1			T265	2		T31	11		T130	6
auto[BaudRate256Kbps]	freqs[24]	141	1			T4	1		T12	2		T40	1
auto[BaudRate256Kbps]	freqs[25]	170	1			T108	2		T161	1		T244	1
auto[BaudRate256Kbps]	freqs[48]	60	1			T2	1		T159	2		T341	2
auto[BaudRate256Kbps]	freqs[50]	87	1			T105	2		T20	5		T340	6
auto[BaudRate256Kbps]	freqs[100]	126	1			T11	2		T31	3		T130	14
auto[BaudRate1Mbps]	freqs[24]	153	1			T12	2		T247	1		T89	1
auto[BaudRate1Mbps]	freqs[25]	168	1			T14	3		T108	2		T161	2
auto[BaudRate1Mbps]	freqs[48]	73	1			T2	1		T303	1		T159	2
auto[BaudRate1Mbps]	freqs[50]	61	1			T105	1		T277	1		T20	5
auto[BaudRate1Mbps]	freqs[100]	148	1			T7	1		T31	20		T130	24
auto[BaudRate1p5Mbps]	freqs[25]	81	1			T131	1		T146	1		T253	1
auto[BaudRate1p5Mbps]	freqs[48]	71	1			T2	1		T120	1		T341	2
auto[BaudRate1p5Mbps]	freqs[50]	72	1			T105	1		T20	6		T257	1
auto[BaudRate1p5Mbps]	freqs[100]	114	1			T265	2		T31	9		T276	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded