Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	27372902	1			T1	2		T2	27		T4	177
all_levels[1]	185564	1			T4	11		T6	34		T8	23
all_levels[2]	1805	1			T4	11		T6	10		T8	7
all_levels[3]	910	1			T4	6		T6	6		T8	8
all_levels[4]	612	1			T2	1		T4	1		T8	3
all_levels[5]	449	1			T4	5		T8	2		T16	4
all_levels[6]	407	1			T4	1		T6	1		T8	1
all_levels[7]	286	1			T4	1		T8	1		T12	1
all_levels[8]	240	1			T2	1		T4	2		T6	2
all_levels[9]	200	1			T4	1		T16	1		T71	2
all_levels[10]	181	1			T16	2		T35	1		T101	2
all_levels[11]	156	1			T16	1		T39	1		T71	1
all_levels[12]	124	1			T2	2		T4	1		T8	1
all_levels[13]	131	1			T16	2		T71	1		T20	4
all_levels[14]	136	1			T14	1		T16	1		T71	2
all_levels[15]	105	1			T16	1		T41	2		T102	2
all_levels[16]	108	1			T16	1		T20	1		T72	1
all_levels[17]	81	1			T101	2		T103	1		T104	1
all_levels[18]	65	1			T2	1		T13	3		T15	1
all_levels[19]	77	1			T71	1		T105	1		T101	1
all_levels[20]	70	1			T8	1		T71	1		T106	1
all_levels[21]	65	1			T16	1		T101	1		T91	4
all_levels[22]	66	1			T16	2		T101	1		T106	1
all_levels[23]	71	1			T72	1		T104	1		T107	1
all_levels[24]	44	1			T108	2		T103	2		T109	1
all_levels[25]	42	1			T21	1		T72	1		T36	1
all_levels[26]	47	1			T16	1		T110	2		T111	3
all_levels[27]	44	1			T106	1		T36	2		T111	2
all_levels[28]	42	1			T108	1		T106	1		T111	2
all_levels[29]	36	1			T112	1		T113	1		T88	1
all_levels[30]	28	1			T72	2		T114	1		T115	2
all_levels[31]	27	1			T106	1		T89	1		T111	1
all_levels[32]	36	1			T21	1		T89	1		T116	1
all_levels[33]	20	1			T16	1		T30	2		T117	1
all_levels[34]	24	1			T108	1		T118	1		T89	1
all_levels[35]	32	1			T2	3		T94	1		T119	1
all_levels[36]	19	1			T120	1		T121	1		T122	3
all_levels[37]	26	1			T110	2		T123	1		T124	2
all_levels[38]	24	1			T13	1		T71	1		T101	1
all_levels[39]	14	1			T16	1		T125	1		T32	1
all_levels[40]	9	1			T126	1		T127	1		T128	1
all_levels[41]	22	1			T72	1		T129	2		T125	1
all_levels[42]	18	1			T16	1		T118	1		T130	1
all_levels[43]	11	1			T71	1		T131	1		T132	1
all_levels[44]	31	1			T16	1		T71	1		T116	1
all_levels[45]	22	1			T71	1		T29	1		T116	1
all_levels[46]	20	1			T108	3		T133	1		T134	1
all_levels[47]	20	1			T14	2		T16	1		T135	1
all_levels[48]	18	1			T112	1		T32	1		T120	1
all_levels[49]	17	1			T118	1		T136	1		T137	1
all_levels[50]	11	1			T89	1		T133	1		T138	1
all_levels[51]	8	1			T29	1		T139	1		T140	1
all_levels[52]	10	1			T27	1		T36	1		T112	1
all_levels[53]	7	1			T141	1		T142	1		T143	1
all_levels[54]	10	1			T21	1		T20	2		T144	1
all_levels[55]	11	1			T71	1		T145	1		T144	1
all_levels[56]	9	1			T27	1		T146	1		T135	1
all_levels[57]	6	1			T14	2		T91	1		T147	1
all_levels[58]	9	1			T148	1		T149	1		T150	2
all_levels[59]	5	1			T8	1		T151	2		T152	1
all_levels[60]	9	1			T14	2		T153	1		T152	1
all_levels[61]	11	1			T108	4		T154	1		T155	1
all_levels[62]	5	1			T127	1		T156	2		T157	1
all_levels[63]	6	1			T21	1		T149	1		T158	1
all_levels[64]	111	1			T8	2		T71	1		T21	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27561801

1

T2

30

T4

217

T6

135

auto[1]

3931

1

T1

2

T2

5

T5

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[39] , all_levels[40]]	[auto[1]]	--	--	2
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[51] , all_levels[52] , all_levels[53]]	[auto[1]]	--	--	3
[all_levels[55] , all_levels[56]]	[auto[1]]	--	--	2
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	27369458	1			T2	24		T4	177		T6	83
all_levels[0]	auto[1]	3444	1			T1	2		T2	3		T5	1
all_levels[1]	auto[0]	185483	1			T4	11		T6	34		T8	23
all_levels[1]	auto[1]	81	1			T105	3		T159	3		T91	1
all_levels[2]	auto[0]	1781	1			T4	11		T6	10		T8	7
all_levels[2]	auto[1]	24	1			T41	2		T103	1		T160	2
all_levels[3]	auto[0]	879	1			T4	6		T6	6		T8	8
all_levels[3]	auto[1]	31	1			T12	2		T108	1		T110	1
all_levels[4]	auto[0]	592	1			T2	1		T4	1		T8	3
all_levels[4]	auto[1]	20	1			T161	1		T162	3		T148	2
all_levels[5]	auto[0]	434	1			T4	5		T8	2		T16	4
all_levels[5]	auto[1]	15	1			T109	1		T148	2		T85	1
all_levels[6]	auto[0]	387	1			T4	1		T6	1		T8	1
all_levels[6]	auto[1]	20	1			T163	1		T164	1		T165	2
all_levels[7]	auto[0]	275	1			T4	1		T8	1		T12	1
all_levels[7]	auto[1]	11	1			T161	1		T110	1		T166	1
all_levels[8]	auto[0]	232	1			T2	1		T4	2		T6	1
all_levels[8]	auto[1]	8	1			T6	1		T167	2		T168	1
all_levels[9]	auto[0]	191	1			T4	1		T16	1		T71	2
all_levels[9]	auto[1]	9	1			T169	2		T144	1		T170	3
all_levels[10]	auto[0]	174	1			T16	2		T35	1		T101	2
all_levels[10]	auto[1]	7	1			T171	1		T172	1		T173	3
all_levels[11]	auto[0]	148	1			T16	1		T39	1		T71	1
all_levels[11]	auto[1]	8	1			T174	1		T175	1		T176	1
all_levels[12]	auto[0]	111	1			T2	2		T4	1		T8	1
all_levels[12]	auto[1]	13	1			T177	2		T178	1		T179	1
all_levels[13]	auto[0]	114	1			T16	2		T71	1		T20	2
all_levels[13]	auto[1]	17	1			T20	2		T109	1		T180	1
all_levels[14]	auto[0]	125	1			T14	1		T16	1		T71	2
all_levels[14]	auto[1]	11	1			T117	4		T181	1		T182	2
all_levels[15]	auto[0]	96	1			T16	1		T41	1		T102	1
all_levels[15]	auto[1]	9	1			T41	1		T102	1		T180	1
all_levels[16]	auto[0]	93	1			T16	1		T20	1		T72	1
all_levels[16]	auto[1]	15	1			T161	1		T109	1		T183	4
all_levels[17]	auto[0]	73	1			T101	2		T103	1		T104	1
all_levels[17]	auto[1]	8	1			T145	1		T184	2		T88	1
all_levels[18]	auto[0]	59	1			T2	1		T13	1		T15	1
all_levels[18]	auto[1]	6	1			T13	2		T185	3		T186	1
all_levels[19]	auto[0]	70	1			T71	1		T105	1		T101	1
all_levels[19]	auto[1]	7	1			T140	4		T172	1		T187	1
all_levels[20]	auto[0]	64	1			T8	1		T71	1		T106	1
all_levels[20]	auto[1]	6	1			T184	1		T188	4		T189	1
all_levels[21]	auto[0]	58	1			T16	1		T101	1		T91	1
all_levels[21]	auto[1]	7	1			T91	3		T126	1		T181	1
all_levels[22]	auto[0]	62	1			T16	2		T101	1		T106	1
all_levels[22]	auto[1]	4	1			T144	1		T190	1		T191	2
all_levels[23]	auto[0]	59	1			T72	1		T104	1		T107	1
all_levels[23]	auto[1]	12	1			T177	1		T192	3		T193	2
all_levels[24]	auto[0]	41	1			T108	1		T103	1		T109	1
all_levels[24]	auto[1]	3	1			T108	1		T103	1		T194	1
all_levels[25]	auto[0]	39	1			T21	1		T72	1		T36	1
all_levels[25]	auto[1]	3	1			T195	1		T196	1		T197	1
all_levels[26]	auto[0]	41	1			T16	1		T110	1		T111	2
all_levels[26]	auto[1]	6	1			T110	1		T111	1		T198	3
all_levels[27]	auto[0]	37	1			T106	1		T36	1		T111	2
all_levels[27]	auto[1]	7	1			T36	1		T199	1		T200	2
all_levels[28]	auto[0]	39	1			T108	1		T106	1		T111	1
all_levels[28]	auto[1]	3	1			T111	1		T201	1		T202	1
all_levels[29]	auto[0]	28	1			T112	1		T113	1		T88	1
all_levels[29]	auto[1]	8	1			T186	1		T203	3		T204	3
all_levels[30]	auto[0]	24	1			T72	2		T114	1		T115	1
all_levels[30]	auto[1]	4	1			T115	1		T205	2		T206	1
all_levels[31]	auto[0]	22	1			T106	1		T89	1		T111	1
all_levels[31]	auto[1]	5	1			T207	1		T194	1		T208	1
all_levels[32]	auto[0]	31	1			T21	1		T89	1		T116	1
all_levels[32]	auto[1]	5	1			T176	1		T209	1		T128	1
all_levels[33]	auto[0]	20	1			T16	1		T30	2		T117	1
all_levels[34]	auto[0]	22	1			T108	1		T118	1		T89	1
all_levels[34]	auto[1]	2	1			T94	2		-	-		-	-
all_levels[35]	auto[0]	21	1			T2	1		T94	1		T119	1
all_levels[35]	auto[1]	11	1			T2	2		T210	1		T86	2
all_levels[36]	auto[0]	15	1			T120	1		T121	1		T122	1
all_levels[36]	auto[1]	4	1			T122	2		T211	2		-	-
all_levels[37]	auto[0]	20	1			T110	1		T123	1		T124	1
all_levels[37]	auto[1]	6	1			T110	1		T124	1		T153	4
all_levels[38]	auto[0]	22	1			T13	1		T71	1		T101	1
all_levels[38]	auto[1]	2	1			T212	1		T213	1		-	-
all_levels[39]	auto[0]	14	1			T16	1		T125	1		T32	1
all_levels[40]	auto[0]	9	1			T126	1		T127	1		T128	1
all_levels[41]	auto[0]	19	1			T72	1		T129	2		T125	1
all_levels[41]	auto[1]	3	1			T194	1		T214	1		T215	1
all_levels[42]	auto[0]	14	1			T16	1		T118	1		T130	1
all_levels[42]	auto[1]	4	1			T216	1		T217	3		-	-
all_levels[43]	auto[0]	10	1			T71	1		T131	1		T132	1
all_levels[43]	auto[1]	1	1			T218	1		-	-		-	-
all_levels[44]	auto[0]	23	1			T16	1		T71	1		T116	1
all_levels[44]	auto[1]	8	1			T219	4		T220	1		T172	1
all_levels[45]	auto[0]	20	1			T71	1		T29	1		T116	1
all_levels[45]	auto[1]	2	1			T221	2		-	-		-	-
all_levels[46]	auto[0]	16	1			T108	2		T133	1		T134	1
all_levels[46]	auto[1]	4	1			T108	1		T222	3		-	-
all_levels[47]	auto[0]	15	1			T14	1		T16	1		T135	1
all_levels[47]	auto[1]	5	1			T14	1		T223	1		T149	1
all_levels[48]	auto[0]	18	1			T112	1		T32	1		T120	1
all_levels[49]	auto[0]	14	1			T118	1		T136	1		T137	1
all_levels[49]	auto[1]	3	1			T224	1		T144	2		-	-
all_levels[50]	auto[0]	9	1			T89	1		T133	1		T138	1
all_levels[50]	auto[1]	2	1			T225	2		-	-		-	-
all_levels[51]	auto[0]	8	1			T29	1		T139	1		T140	1
all_levels[52]	auto[0]	10	1			T27	1		T36	1		T112	1
all_levels[53]	auto[0]	7	1			T141	1		T142	1		T143	1
all_levels[54]	auto[0]	8	1			T21	1		T20	1		T144	1
all_levels[54]	auto[1]	2	1			T20	1		T226	1		-	-
all_levels[55]	auto[0]	11	1			T71	1		T145	1		T144	1
all_levels[56]	auto[0]	9	1			T27	1		T146	1		T135	1
all_levels[57]	auto[0]	5	1			T14	1		T91	1		T147	1
all_levels[57]	auto[1]	1	1			T14	1		-	-		-	-
all_levels[58]	auto[0]	6	1			T148	1		T149	1		T150	1
all_levels[58]	auto[1]	3	1			T150	1		T227	2		-	-
all_levels[59]	auto[0]	4	1			T8	1		T151	1		T152	1
all_levels[59]	auto[1]	1	1			T151	1		-	-		-	-
all_levels[60]	auto[0]	8	1			T14	1		T153	1		T152	1
all_levels[60]	auto[1]	1	1			T14	1		-	-		-	-
all_levels[61]	auto[0]	8	1			T108	1		T154	1		T155	1
all_levels[61]	auto[1]	3	1			T108	3		-	-		-	-
all_levels[62]	auto[0]	4	1			T127	1		T156	1		T157	1
all_levels[62]	auto[1]	1	1			T156	1		-	-		-	-
all_levels[63]	auto[0]	6	1			T21	1		T149	1		T158	1
all_levels[64]	auto[0]	86	1			T8	2		T71	1		T21	2
all_levels[64]	auto[1]	25	1			T228	4		T229	1		T230	3