Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 1 7 87.50 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 1 7 87.50


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1066 1 T6 9 T16 2 T15 7
all_levels[1] 623 1 T8 4 T16 8 T71 1
all_levels[2] 376 1 T39 1 T21 2 T27 2
all_levels[3] 312 1 T71 7 T27 4 T89 4
all_levels[4] 182 1 T15 4 T90 12 T91 18
all_levels[5] 136 1 T8 4 T13 8 T21 20
all_levels[6] 49 1 T72 2 T92 14 T93 2

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