Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	93654	1			T1	1		T2	24		T4	89
all_pins[1]	93654	1			T1	1		T2	24		T4	89
all_pins[2]	93654	1			T1	1		T2	24		T4	89
all_pins[3]	93654	1			T1	1		T2	24		T4	89
all_pins[4]	93654	1			T1	1		T2	24		T4	89
all_pins[5]	93654	1			T1	1		T2	24		T4	89
all_pins[6]	93654	1			T1	1		T2	24		T4	89
all_pins[7]	93654	1			T1	1		T2	24		T4	89
all_pins[8]	93654	1			T1	1		T2	24		T4	89

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	804116	1			T1	9		T2	206		T4	655
values[0x1]	38770	1			T2	10		T4	146		T5	1
transitions[0x0=>0x1]	31156	1			T2	10		T4	90		T6	55
transitions[0x1=>0x0]	30949	1			T2	10		T4	89		T5	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	73860	1			T1	1		T2	23		T4	20
all_pins[0]	values[0x1]	19794	1			T2	1		T4	69		T6	50
all_pins[0]	transitions[0x0=>0x1]	19365	1			T2	1		T4	69		T6	50
all_pins[0]	transitions[0x1=>0x0]	875	1			T8	4		T15	9		T71	7
all_pins[1]	values[0x0]	92350	1			T1	1		T2	24		T4	89
all_pins[1]	values[0x1]	1304	1			T8	8		T16	1		T15	11
all_pins[1]	transitions[0x0=>0x1]	1208	1			T8	8		T16	1		T15	11
all_pins[1]	transitions[0x1=>0x0]	1918	1			T2	6		T4	7		T6	3
all_pins[2]	values[0x0]	91640	1			T1	1		T2	18		T4	82
all_pins[2]	values[0x1]	2014	1			T2	6		T4	7		T6	3
all_pins[2]	transitions[0x0=>0x1]	1954	1			T2	6		T4	7		T6	3
all_pins[2]	transitions[0x1=>0x0]	167	1			T15	2		T21	4		T109	1
all_pins[3]	values[0x0]	93427	1			T1	1		T2	24		T4	89
all_pins[3]	values[0x1]	227	1			T14	1		T15	2		T71	1
all_pins[3]	transitions[0x0=>0x1]	193	1			T14	1		T15	2		T71	1
all_pins[3]	transitions[0x1=>0x0]	338	1			T8	12		T15	1		T18	15
all_pins[4]	values[0x0]	93282	1			T1	1		T2	24		T4	89
all_pins[4]	values[0x1]	372	1			T8	12		T15	1		T18	15
all_pins[4]	transitions[0x0=>0x1]	315	1			T8	12		T15	1		T18	15
all_pins[4]	transitions[0x1=>0x0]	127	1			T16	1		T71	1		T21	4
all_pins[5]	values[0x0]	93470	1			T1	1		T2	24		T4	89
all_pins[5]	values[0x1]	184	1			T16	1		T71	1		T21	7
all_pins[5]	transitions[0x0=>0x1]	139	1			T16	1		T71	1		T21	7
all_pins[5]	transitions[0x1=>0x0]	706	1			T2	1		T14	3		T16	6
all_pins[6]	values[0x0]	92903	1			T1	1		T2	23		T4	89
all_pins[6]	values[0x1]	751	1			T2	1		T14	3		T16	6
all_pins[6]	transitions[0x0=>0x1]	711	1			T2	1		T14	3		T16	6
all_pins[6]	transitions[0x1=>0x0]	208	1			T16	1		T71	2		T21	3
all_pins[7]	values[0x0]	93406	1			T1	1		T2	24		T4	89
all_pins[7]	values[0x1]	248	1			T16	1		T71	2		T21	4
all_pins[7]	transitions[0x0=>0x1]	141	1			T71	2		T101	1		T20	7
all_pins[7]	transitions[0x1=>0x0]	13769	1			T2	2		T4	70		T5	1
all_pins[8]	values[0x0]	79778	1			T1	1		T2	22		T4	19
all_pins[8]	values[0x1]	13876	1			T2	2		T4	70		T5	1
all_pins[8]	transitions[0x0=>0x1]	7130	1			T2	2		T4	14		T6	2
all_pins[8]	transitions[0x1=>0x0]	12841	1			T2	1		T4	12		T6	49