Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7414661	1			T2	12		T4	111		T5	1
all_levels[1]	1236154	1			T4	61		T6	102		T8	12632
all_levels[2]	333980	1			T8	1516		T16	2		T34	789
all_levels[3]	320327	1			T8	95		T11	1		T16	2
all_levels[4]	241216	1			T2	9		T4	3		T8	1711
all_levels[5]	309801	1			T2	1		T8	61		T11	4
all_levels[6]	276976	1			T8	57		T16	2		T34	793
all_levels[7]	485665	1			T8	54		T11	3		T14	1
all_levels[8]	835038	1			T4	1		T6	4		T8	61
all_levels[9]	428484	1			T8	58		T11	1		T12	2
all_levels[10]	217044	1			T8	54		T11	4		T12	2
all_levels[11]	236670	1			T2	1		T8	64		T16	3
all_levels[12]	225835	1			T6	8		T8	34		T11	159
all_levels[13]	252321	1			T4	1		T6	11		T8	33
all_levels[14]	350407	1			T6	3		T8	33		T14	1
all_levels[15]	208400	1			T8	1093		T34	793		T39	2
all_levels[16]	312000	1			T8	1		T16	2		T34	771
all_levels[17]	344295	1			T4	1		T6	5		T8	2
all_levels[18]	186296	1			T4	1		T8	3		T16	2
all_levels[19]	187637	1			T8	2		T12	8		T16	4
all_levels[20]	221114	1			T2	2		T4	1		T8	2
all_levels[21]	193975	1			T4	2		T8	4		T16	5
all_levels[22]	237809	1			T8	3		T16	5		T34	792
all_levels[23]	176461	1			T4	5		T8	1		T14	1
all_levels[24]	175899	1			T8	3		T16	3		T34	793
all_levels[25]	189073	1			T8	6		T12	2		T16	4
all_levels[26]	278089	1			T8	6		T16	3		T34	782
all_levels[27]	205788	1			T8	3		T16	1		T34	793
all_levels[28]	164239	1			T8	7		T34	787		T15	6113
all_levels[29]	338494	1			T8	3		T16	1		T34	794
all_levels[30]	176054	1			T8	6		T16	1		T34	793
all_levels[31]	447018	1			T2	1		T8	5		T14	2
all_levels[32]	10358205	1			T2	11		T4	31		T6	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27561801

1

T2

30

T4

217

T6

135

auto[1]

3624

1

T2

7

T4

1

T5

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7412609	1			T2	8		T4	110		T6	5
all_levels[0]	auto[1]	2052	1			T2	4		T4	1		T5	1
all_levels[1]	auto[0]	1235876	1			T4	61		T6	100		T8	12632
all_levels[1]	auto[1]	278	1			T6	2		T16	1		T41	1
all_levels[2]	auto[0]	333933	1			T8	1516		T16	2		T34	789
all_levels[2]	auto[1]	47	1			T105	2		T108	1		T104	4
all_levels[3]	auto[0]	320256	1			T8	88		T11	1		T16	2
all_levels[3]	auto[1]	71	1			T8	7		T291	5		T20	2
all_levels[4]	auto[0]	241200	1			T2	8		T4	3		T8	1711
all_levels[4]	auto[1]	16	1			T2	1		T180	1		T163	1
all_levels[5]	auto[0]	309778	1			T2	1		T8	61		T11	4
all_levels[5]	auto[1]	23	1			T35	2		T106	1		T265	1
all_levels[6]	auto[0]	276953	1			T8	57		T16	2		T34	793
all_levels[6]	auto[1]	23	1			T38	1		T89	3		T267	1
all_levels[7]	auto[0]	485595	1			T8	54		T11	3		T14	1
all_levels[7]	auto[1]	70	1			T108	1		T83	1		T263	3
all_levels[8]	auto[0]	835026	1			T4	1		T6	2		T8	61
all_levels[8]	auto[1]	12	1			T6	2		T35	1		T20	1
all_levels[9]	auto[0]	428454	1			T8	58		T11	1		T12	2
all_levels[9]	auto[1]	30	1			T35	3		T108	1		T159	1
all_levels[10]	auto[0]	217017	1			T8	54		T11	4		T12	2
all_levels[10]	auto[1]	27	1			T14	1		T250	1		T130	1
all_levels[11]	auto[0]	236643	1			T2	1		T8	64		T16	3
all_levels[11]	auto[1]	27	1			T103	1		T239	1		T107	1
all_levels[12]	auto[0]	225808	1			T6	8		T8	34		T11	159
all_levels[12]	auto[1]	27	1			T41	1		T105	1		T91	2
all_levels[13]	auto[0]	252285	1			T4	1		T6	11		T8	33
all_levels[13]	auto[1]	36	1			T102	1		T250	1		T314	1
all_levels[14]	auto[0]	350389	1			T6	3		T8	33		T14	1
all_levels[14]	auto[1]	18	1			T110	1		T342	2		T149	1
all_levels[15]	auto[0]	208370	1			T8	1093		T34	793		T39	2
all_levels[15]	auto[1]	30	1			T41	2		T20	1		T161	1
all_levels[16]	auto[0]	311977	1			T8	1		T16	2		T34	771
all_levels[16]	auto[1]	23	1			T166	2		T343	1		T344	1
all_levels[17]	auto[0]	344265	1			T4	1		T6	4		T8	2
all_levels[17]	auto[1]	30	1			T6	1		T12	2		T159	2
all_levels[18]	auto[0]	186284	1			T4	1		T8	3		T16	2
all_levels[18]	auto[1]	12	1			T247	2		T162	2		T345	1
all_levels[19]	auto[0]	187624	1			T8	2		T12	5		T16	4
all_levels[19]	auto[1]	13	1			T12	3		T20	1		T346	1
all_levels[20]	auto[0]	221081	1			T2	2		T4	1		T8	2
all_levels[20]	auto[1]	33	1			T71	1		T242	1		T110	1
all_levels[21]	auto[0]	193954	1			T4	2		T8	4		T16	5
all_levels[21]	auto[1]	21	1			T159	1		T347	2		T201	3
all_levels[22]	auto[0]	237780	1			T8	3		T16	5		T34	792
all_levels[22]	auto[1]	29	1			T265	1		T317	1		T344	3
all_levels[23]	auto[0]	176453	1			T4	5		T8	1		T14	1
all_levels[23]	auto[1]	8	1			T174	1		T85	1		T144	1
all_levels[24]	auto[0]	175885	1			T8	3		T16	2		T34	793
all_levels[24]	auto[1]	14	1			T16	1		T177	1		T88	1
all_levels[25]	auto[0]	189056	1			T8	6		T12	1		T16	4
all_levels[25]	auto[1]	17	1			T12	1		T210	1		T348	2
all_levels[26]	auto[0]	278064	1			T8	6		T16	3		T34	782
all_levels[26]	auto[1]	25	1			T349	1		T317	1		T174	3
all_levels[27]	auto[0]	205771	1			T8	3		T16	1		T34	793
all_levels[27]	auto[1]	17	1			T36	1		T110	1		T83	2
all_levels[28]	auto[0]	164221	1			T8	7		T34	787		T15	6113
all_levels[28]	auto[1]	18	1			T180	1		T177	2		T350	1
all_levels[29]	auto[0]	338484	1			T8	3		T16	1		T34	794
all_levels[29]	auto[1]	10	1			T36	1		T111	1		T149	1
all_levels[30]	auto[0]	176039	1			T8	6		T16	1		T34	793
all_levels[30]	auto[1]	15	1			T109	1		T91	1		T351	1
all_levels[31]	auto[0]	447005	1			T2	1		T8	5		T14	1
all_levels[31]	auto[1]	13	1			T14	1		T89	2		T31	1
all_levels[32]	auto[0]	10357666	1			T2	9		T4	31		T6	2
all_levels[32]	auto[1]	539	1			T2	2		T8	1		T12	2