Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	565	1			T16	4		T71	7		T21	18
all_values[1]	565	1			T16	4		T71	7		T21	18
all_values[2]	565	1			T16	4		T71	7		T21	18
all_values[3]	565	1			T16	4		T71	7		T21	18
all_values[4]	565	1			T16	4		T71	7		T21	18
all_values[5]	565	1			T16	4		T71	7		T21	18
all_values[6]	565	1			T16	4		T71	7		T21	18
all_values[7]	565	1			T16	4		T71	7		T21	18
all_values[8]	565	1			T16	4		T71	7		T21	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2745

1

T16

18

T71

32

T21

79

auto[1]

2340

1

T16

18

T71

31

T21

83

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1697

1

T16

14

T71

24

T21

53

auto[1]

3388

1

T16

22

T71

39

T21

109

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3016

1

T16

25

T71

40

T21

97

auto[1]

2069

1

T16

11

T71

23

T21

65

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	187	1			T71	3		T21	5		T72	1
all_values[0]	auto[0]	auto[1]	auto[1]	141	1			T16	2		T21	4		T72	2
all_values[0]	auto[1]	auto[0]	auto[1]	135	1			T16	1		T71	3		T21	2
all_values[0]	auto[1]	auto[1]	auto[1]	102	1			T16	1		T71	1		T21	7
all_values[1]	auto[0]	auto[0]	auto[0]	198	1			T71	2		T21	6		T72	1
all_values[1]	auto[0]	auto[1]	auto[0]	156	1			T16	2		T71	3		T21	6
all_values[1]	auto[1]	auto[0]	auto[1]	108	1			T16	1		T71	1		T21	5
all_values[1]	auto[1]	auto[1]	auto[1]	103	1			T16	1		T71	1		T21	1
all_values[2]	auto[0]	auto[0]	auto[0]	113	1			T16	1		T21	1		T29	2
all_values[2]	auto[0]	auto[0]	auto[1]	56	1			T71	1		T21	2		T31	2
all_values[2]	auto[0]	auto[1]	auto[0]	110	1			T16	1		T71	1		T21	3
all_values[2]	auto[0]	auto[1]	auto[1]	54	1			T71	2		T29	1		T31	1
all_values[2]	auto[1]	auto[0]	auto[1]	113	1			T16	1		T21	8		T31	2
all_values[2]	auto[1]	auto[1]	auto[1]	119	1			T16	1		T71	3		T21	4
all_values[3]	auto[0]	auto[0]	auto[0]	106	1			T16	1		T71	3		T21	3
all_values[3]	auto[0]	auto[0]	auto[1]	52	1			T16	2		T21	1		T72	1
all_values[3]	auto[0]	auto[1]	auto[0]	113	1			T71	2		T21	5		T29	3
all_values[3]	auto[0]	auto[1]	auto[1]	53	1			T21	2		T29	2		T94	2
all_values[3]	auto[1]	auto[0]	auto[1]	135	1			T16	1		T21	4		T72	1
all_values[3]	auto[1]	auto[1]	auto[1]	106	1			T71	2		T21	3		T72	1
all_values[4]	auto[0]	auto[0]	auto[0]	147	1			T16	2		T71	2		T21	4
all_values[4]	auto[0]	auto[0]	auto[1]	44	1			T71	1		T21	1		T88	2
all_values[4]	auto[0]	auto[1]	auto[0]	97	1			T16	2		T21	7		T31	5
all_values[4]	auto[0]	auto[1]	auto[1]	46	1			T21	3		T72	1		T29	1
all_values[4]	auto[1]	auto[0]	auto[1]	139	1			T71	3		T21	1		T72	2
all_values[4]	auto[1]	auto[1]	auto[1]	92	1			T71	1		T21	2		T72	1
all_values[5]	auto[0]	auto[0]	auto[0]	123	1			T16	1		T21	2		T31	4
all_values[5]	auto[0]	auto[0]	auto[1]	57	1			T16	1		T71	1		T21	5
all_values[5]	auto[0]	auto[1]	auto[0]	90	1			T71	3		T21	2		T31	4
all_values[5]	auto[0]	auto[1]	auto[1]	61	1			T16	1		T21	2		T72	2
all_values[5]	auto[1]	auto[0]	auto[1]	132	1			T71	2		T21	3		T29	1
all_values[5]	auto[1]	auto[1]	auto[1]	102	1			T16	1		T71	1		T21	4
all_values[6]	auto[0]	auto[0]	auto[0]	123	1			T16	2		T71	3		T21	3
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T21	3		T88	2		T95	1
all_values[6]	auto[0]	auto[1]	auto[0]	73	1			T16	2		T71	3		T21	1
all_values[6]	auto[0]	auto[1]	auto[1]	69	1			T21	3		T72	2		T29	2
all_values[6]	auto[1]	auto[0]	auto[1]	124	1			T21	3		T72	1		T29	1
all_values[6]	auto[1]	auto[1]	auto[1]	108	1			T71	1		T21	5		T72	1
all_values[7]	auto[0]	auto[0]	auto[0]	132	1			T21	3		T29	5		T31	3
all_values[7]	auto[0]	auto[0]	auto[1]	48	1			T16	1		T71	1		T29	1
all_values[7]	auto[0]	auto[1]	auto[0]	116	1			T71	2		T21	7		T72	2
all_values[7]	auto[0]	auto[1]	auto[1]	50	1			T16	1		T71	1		T94	1
all_values[7]	auto[1]	auto[0]	auto[1]	103	1			T16	1		T21	3		T29	1
all_values[7]	auto[1]	auto[1]	auto[1]	116	1			T16	1		T71	3		T21	5
all_values[8]	auto[0]	auto[0]	auto[1]	178	1			T16	2		T71	5		T21	9
all_values[8]	auto[0]	auto[1]	auto[1]	155	1			T16	1		T71	1		T21	4
all_values[8]	auto[1]	auto[0]	auto[1]	124	1			T71	1		T21	2		T29	3
all_values[8]	auto[1]	auto[1]	auto[1]	108	1			T16	1		T21	3		T29	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal