Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.55


Total test records in report: 1226
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T1036 /workspace/coverage/default/17.uart_rx_parity_err.3576081672 Jul 03 05:43:16 PM PDT 24 Jul 03 05:43:56 PM PDT 24 95719019724 ps
T1037 /workspace/coverage/default/39.uart_rx_start_bit_filter.4204949990 Jul 03 05:44:18 PM PDT 24 Jul 03 05:44:20 PM PDT 24 1762211938 ps
T1038 /workspace/coverage/default/13.uart_fifo_reset.813987651 Jul 03 05:43:23 PM PDT 24 Jul 03 05:45:08 PM PDT 24 74684586227 ps
T1039 /workspace/coverage/default/46.uart_intr.4158856611 Jul 03 05:44:44 PM PDT 24 Jul 03 05:45:40 PM PDT 24 146906813598 ps
T1040 /workspace/coverage/default/229.uart_fifo_reset.2473698137 Jul 03 05:45:53 PM PDT 24 Jul 03 05:48:35 PM PDT 24 93730934193 ps
T1041 /workspace/coverage/default/12.uart_rx_oversample.1928628987 Jul 03 05:43:24 PM PDT 24 Jul 03 05:43:27 PM PDT 24 2482410272 ps
T1042 /workspace/coverage/default/30.uart_perf.1103467315 Jul 03 05:43:58 PM PDT 24 Jul 03 05:45:15 PM PDT 24 14591980760 ps
T1043 /workspace/coverage/default/28.uart_alert_test.1615834502 Jul 03 05:43:44 PM PDT 24 Jul 03 05:43:45 PM PDT 24 20645712 ps
T1044 /workspace/coverage/default/210.uart_fifo_reset.1152038355 Jul 03 05:45:44 PM PDT 24 Jul 03 05:45:58 PM PDT 24 87906340284 ps
T197 /workspace/coverage/default/0.uart_fifo_reset.2630809245 Jul 03 05:42:40 PM PDT 24 Jul 03 05:43:23 PM PDT 24 59868678723 ps
T1045 /workspace/coverage/default/91.uart_fifo_reset.2738086788 Jul 03 05:45:14 PM PDT 24 Jul 03 05:46:33 PM PDT 24 89012769936 ps
T1046 /workspace/coverage/default/182.uart_fifo_reset.3958788670 Jul 03 05:45:34 PM PDT 24 Jul 03 05:50:52 PM PDT 24 193474482643 ps
T1047 /workspace/coverage/default/45.uart_fifo_overflow.352966908 Jul 03 05:44:39 PM PDT 24 Jul 03 05:44:51 PM PDT 24 28001223089 ps
T1048 /workspace/coverage/default/2.uart_fifo_overflow.2150778702 Jul 03 05:42:58 PM PDT 24 Jul 03 05:46:19 PM PDT 24 90349876089 ps
T1049 /workspace/coverage/default/140.uart_fifo_reset.3263143903 Jul 03 05:45:28 PM PDT 24 Jul 03 05:47:52 PM PDT 24 58801732169 ps
T1050 /workspace/coverage/default/16.uart_alert_test.2440751651 Jul 03 05:43:17 PM PDT 24 Jul 03 05:43:18 PM PDT 24 15474396 ps
T1051 /workspace/coverage/default/15.uart_fifo_full.779170806 Jul 03 05:43:12 PM PDT 24 Jul 03 05:43:43 PM PDT 24 107113549023 ps
T1052 /workspace/coverage/default/11.uart_long_xfer_wo_dly.1851644342 Jul 03 05:43:15 PM PDT 24 Jul 03 05:50:05 PM PDT 24 81277492726 ps
T1053 /workspace/coverage/default/13.uart_fifo_overflow.3065575546 Jul 03 05:43:18 PM PDT 24 Jul 03 05:44:22 PM PDT 24 74729001461 ps
T1054 /workspace/coverage/default/19.uart_rx_parity_err.2377913046 Jul 03 05:43:22 PM PDT 24 Jul 03 05:44:42 PM PDT 24 49711828801 ps
T1055 /workspace/coverage/default/7.uart_tx_rx.2853540322 Jul 03 05:43:07 PM PDT 24 Jul 03 05:43:22 PM PDT 24 10194071257 ps
T1056 /workspace/coverage/default/9.uart_tx_rx.3684274528 Jul 03 05:43:04 PM PDT 24 Jul 03 05:43:19 PM PDT 24 9654952838 ps
T1057 /workspace/coverage/default/32.uart_tx_ovrd.3201315274 Jul 03 05:44:00 PM PDT 24 Jul 03 05:44:03 PM PDT 24 2868187374 ps
T1058 /workspace/coverage/default/20.uart_fifo_overflow.3859682788 Jul 03 05:43:18 PM PDT 24 Jul 03 05:44:11 PM PDT 24 38344943617 ps
T1059 /workspace/coverage/default/24.uart_smoke.3318532484 Jul 03 05:43:42 PM PDT 24 Jul 03 05:43:44 PM PDT 24 314678828 ps
T1060 /workspace/coverage/default/25.uart_fifo_full.1411016637 Jul 03 05:43:27 PM PDT 24 Jul 03 05:45:20 PM PDT 24 73433804126 ps
T1061 /workspace/coverage/default/16.uart_tx_rx.912275559 Jul 03 05:43:29 PM PDT 24 Jul 03 05:44:46 PM PDT 24 59078512386 ps
T1062 /workspace/coverage/default/15.uart_intr.2204686342 Jul 03 05:43:28 PM PDT 24 Jul 03 05:44:59 PM PDT 24 217674077696 ps
T1063 /workspace/coverage/default/56.uart_fifo_reset.334474233 Jul 03 05:44:56 PM PDT 24 Jul 03 05:47:14 PM PDT 24 76684736700 ps
T1064 /workspace/coverage/default/34.uart_smoke.1103087377 Jul 03 05:44:03 PM PDT 24 Jul 03 05:44:12 PM PDT 24 6246361199 ps
T1065 /workspace/coverage/default/25.uart_rx_parity_err.1841596024 Jul 03 05:43:47 PM PDT 24 Jul 03 05:44:29 PM PDT 24 127116578576 ps
T1066 /workspace/coverage/default/13.uart_perf.3892184896 Jul 03 05:43:16 PM PDT 24 Jul 03 05:46:40 PM PDT 24 12870700784 ps
T1067 /workspace/coverage/default/141.uart_fifo_reset.227030786 Jul 03 05:45:24 PM PDT 24 Jul 03 05:46:27 PM PDT 24 77878137832 ps
T1068 /workspace/coverage/default/19.uart_intr.2511241914 Jul 03 05:43:18 PM PDT 24 Jul 03 05:43:47 PM PDT 24 45139682536 ps
T1069 /workspace/coverage/default/16.uart_rx_parity_err.2414104449 Jul 03 05:43:20 PM PDT 24 Jul 03 05:44:01 PM PDT 24 24890181001 ps
T1070 /workspace/coverage/default/10.uart_fifo_reset.642623073 Jul 03 05:43:05 PM PDT 24 Jul 03 05:44:22 PM PDT 24 53902946785 ps
T1071 /workspace/coverage/default/55.uart_stress_all_with_rand_reset.203836170 Jul 03 05:44:55 PM PDT 24 Jul 03 05:50:03 PM PDT 24 31226862414 ps
T1072 /workspace/coverage/default/6.uart_fifo_overflow.3502255948 Jul 03 05:43:10 PM PDT 24 Jul 03 05:44:05 PM PDT 24 82556433285 ps
T1073 /workspace/coverage/default/17.uart_fifo_overflow.1014620287 Jul 03 05:43:13 PM PDT 24 Jul 03 05:44:06 PM PDT 24 49855425507 ps
T1074 /workspace/coverage/default/35.uart_rx_oversample.3833235147 Jul 03 05:44:01 PM PDT 24 Jul 03 05:44:09 PM PDT 24 6586339723 ps
T1075 /workspace/coverage/default/30.uart_loopback.3560826170 Jul 03 05:43:59 PM PDT 24 Jul 03 05:44:09 PM PDT 24 4495849480 ps
T1076 /workspace/coverage/default/7.uart_fifo_reset.2576083336 Jul 03 05:42:54 PM PDT 24 Jul 03 05:43:34 PM PDT 24 411122700944 ps
T1077 /workspace/coverage/default/67.uart_fifo_reset.1615605394 Jul 03 05:44:59 PM PDT 24 Jul 03 05:45:21 PM PDT 24 27213213573 ps
T215 /workspace/coverage/default/105.uart_fifo_reset.3632001153 Jul 03 05:45:15 PM PDT 24 Jul 03 05:46:31 PM PDT 24 173401584815 ps
T1078 /workspace/coverage/default/12.uart_perf.1361072656 Jul 03 05:43:19 PM PDT 24 Jul 03 05:49:00 PM PDT 24 6213344968 ps
T1079 /workspace/coverage/default/38.uart_perf.2416695460 Jul 03 05:44:14 PM PDT 24 Jul 03 05:50:19 PM PDT 24 15634732003 ps
T1080 /workspace/coverage/default/7.uart_rx_oversample.901272269 Jul 03 05:43:11 PM PDT 24 Jul 03 05:43:13 PM PDT 24 1398764340 ps
T1081 /workspace/coverage/default/3.uart_fifo_overflow.3958280586 Jul 03 05:42:49 PM PDT 24 Jul 03 05:45:49 PM PDT 24 242875075139 ps
T1082 /workspace/coverage/default/115.uart_fifo_reset.1324254314 Jul 03 05:45:21 PM PDT 24 Jul 03 05:45:38 PM PDT 24 91320540929 ps
T1083 /workspace/coverage/default/240.uart_fifo_reset.1337912878 Jul 03 05:45:52 PM PDT 24 Jul 03 05:46:11 PM PDT 24 12666760784 ps
T1084 /workspace/coverage/default/26.uart_long_xfer_wo_dly.1623592493 Jul 03 05:43:34 PM PDT 24 Jul 03 05:48:54 PM PDT 24 112781353412 ps
T1085 /workspace/coverage/default/32.uart_loopback.727811793 Jul 03 05:44:00 PM PDT 24 Jul 03 05:44:12 PM PDT 24 5967255897 ps
T1086 /workspace/coverage/default/17.uart_loopback.2811302965 Jul 03 05:43:34 PM PDT 24 Jul 03 05:43:36 PM PDT 24 917359237 ps
T1087 /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2801016883 Jul 03 05:45:09 PM PDT 24 Jul 03 05:47:07 PM PDT 24 33637395575 ps
T1088 /workspace/coverage/default/32.uart_fifo_overflow.3773663819 Jul 03 05:44:00 PM PDT 24 Jul 03 05:44:42 PM PDT 24 102280297046 ps
T1089 /workspace/coverage/default/2.uart_smoke.901170832 Jul 03 05:42:42 PM PDT 24 Jul 03 05:42:44 PM PDT 24 317770526 ps
T1090 /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3807861737 Jul 03 05:44:13 PM PDT 24 Jul 03 05:48:27 PM PDT 24 22596719357 ps
T1091 /workspace/coverage/default/2.uart_long_xfer_wo_dly.3026858365 Jul 03 05:42:57 PM PDT 24 Jul 03 05:48:00 PM PDT 24 282030106614 ps
T1092 /workspace/coverage/default/31.uart_smoke.500366074 Jul 03 05:43:52 PM PDT 24 Jul 03 05:43:55 PM PDT 24 502630950 ps
T1093 /workspace/coverage/default/172.uart_fifo_reset.3129638351 Jul 03 05:45:30 PM PDT 24 Jul 03 05:46:25 PM PDT 24 196005584961 ps
T1094 /workspace/coverage/default/34.uart_alert_test.1353544525 Jul 03 05:44:04 PM PDT 24 Jul 03 05:44:05 PM PDT 24 11023091 ps
T1095 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1218797010 Jul 03 05:35:17 PM PDT 24 Jul 03 05:35:18 PM PDT 24 80309006 ps
T1096 /workspace/coverage/cover_reg_top/11.uart_intr_test.3452339385 Jul 03 05:35:20 PM PDT 24 Jul 03 05:35:21 PM PDT 24 13279878 ps
T1097 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1768079484 Jul 03 05:35:07 PM PDT 24 Jul 03 05:35:08 PM PDT 24 30898658 ps
T1098 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2468591301 Jul 03 05:35:13 PM PDT 24 Jul 03 05:35:14 PM PDT 24 93014436 ps
T1099 /workspace/coverage/cover_reg_top/25.uart_intr_test.4224429719 Jul 03 05:35:32 PM PDT 24 Jul 03 05:35:33 PM PDT 24 20551343 ps
T1100 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1383927342 Jul 03 05:35:25 PM PDT 24 Jul 03 05:35:27 PM PDT 24 217664336 ps
T73 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1918629048 Jul 03 05:35:02 PM PDT 24 Jul 03 05:35:04 PM PDT 24 309507012 ps
T1101 /workspace/coverage/cover_reg_top/4.uart_tl_errors.189134635 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:07 PM PDT 24 76464535 ps
T1102 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.172513147 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:07 PM PDT 24 36665856 ps
T1103 /workspace/coverage/cover_reg_top/49.uart_intr_test.2221813821 Jul 03 05:35:37 PM PDT 24 Jul 03 05:35:38 PM PDT 24 11595079 ps
T1104 /workspace/coverage/cover_reg_top/19.uart_intr_test.1059219905 Jul 03 05:35:32 PM PDT 24 Jul 03 05:35:33 PM PDT 24 31371825 ps
T50 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2960341491 Jul 03 05:35:30 PM PDT 24 Jul 03 05:35:31 PM PDT 24 33892404 ps
T74 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2695311020 Jul 03 05:35:34 PM PDT 24 Jul 03 05:35:36 PM PDT 24 606409095 ps
T1105 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1734233375 Jul 03 05:35:08 PM PDT 24 Jul 03 05:35:09 PM PDT 24 184288541 ps
T1106 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3853352895 Jul 03 05:35:15 PM PDT 24 Jul 03 05:35:16 PM PDT 24 36971393 ps
T62 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1494146781 Jul 03 05:35:40 PM PDT 24 Jul 03 05:35:41 PM PDT 24 15035049 ps
T1107 /workspace/coverage/cover_reg_top/18.uart_intr_test.3450744584 Jul 03 05:35:29 PM PDT 24 Jul 03 05:35:30 PM PDT 24 38089615 ps
T63 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2058783393 Jul 03 05:35:35 PM PDT 24 Jul 03 05:35:36 PM PDT 24 33604134 ps
T1108 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1942646685 Jul 03 05:35:16 PM PDT 24 Jul 03 05:35:18 PM PDT 24 27073936 ps
T1109 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2136321760 Jul 03 05:35:13 PM PDT 24 Jul 03 05:35:14 PM PDT 24 66794274 ps
T1110 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.30664317 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:06 PM PDT 24 34544043 ps
T1111 /workspace/coverage/cover_reg_top/27.uart_intr_test.2835430308 Jul 03 05:35:32 PM PDT 24 Jul 03 05:35:33 PM PDT 24 16681628 ps
T1112 /workspace/coverage/cover_reg_top/43.uart_intr_test.2556830341 Jul 03 05:35:37 PM PDT 24 Jul 03 05:35:38 PM PDT 24 54290995 ps
T1113 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3084326407 Jul 03 05:35:03 PM PDT 24 Jul 03 05:35:06 PM PDT 24 155848226 ps
T1114 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1014089516 Jul 03 05:34:59 PM PDT 24 Jul 03 05:35:01 PM PDT 24 84682243 ps
T51 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2438855557 Jul 03 05:35:02 PM PDT 24 Jul 03 05:35:03 PM PDT 24 21383394 ps
T1115 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1386296822 Jul 03 05:35:22 PM PDT 24 Jul 03 05:35:23 PM PDT 24 150430067 ps
T64 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4142276249 Jul 03 05:35:20 PM PDT 24 Jul 03 05:35:21 PM PDT 24 72677282 ps
T75 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3389665090 Jul 03 05:35:29 PM PDT 24 Jul 03 05:35:31 PM PDT 24 143865923 ps
T65 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2449805788 Jul 03 05:35:24 PM PDT 24 Jul 03 05:35:25 PM PDT 24 18731560 ps
T1116 /workspace/coverage/cover_reg_top/37.uart_intr_test.1413674199 Jul 03 05:35:39 PM PDT 24 Jul 03 05:35:40 PM PDT 24 11279719 ps
T1117 /workspace/coverage/cover_reg_top/33.uart_intr_test.1979112749 Jul 03 05:35:33 PM PDT 24 Jul 03 05:35:34 PM PDT 24 44807961 ps
T1118 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2957127257 Jul 03 05:35:01 PM PDT 24 Jul 03 05:35:03 PM PDT 24 44891495 ps
T1119 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1655034582 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:07 PM PDT 24 91929429 ps
T1120 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3184742949 Jul 03 05:35:07 PM PDT 24 Jul 03 05:35:09 PM PDT 24 128817709 ps
T66 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.4197341110 Jul 03 05:35:15 PM PDT 24 Jul 03 05:35:16 PM PDT 24 62735852 ps
T1121 /workspace/coverage/cover_reg_top/46.uart_intr_test.553882734 Jul 03 05:35:38 PM PDT 24 Jul 03 05:35:39 PM PDT 24 31680150 ps
T1122 /workspace/coverage/cover_reg_top/14.uart_intr_test.3954933967 Jul 03 05:35:27 PM PDT 24 Jul 03 05:35:27 PM PDT 24 13453819 ps
T1123 /workspace/coverage/cover_reg_top/20.uart_intr_test.2293221292 Jul 03 05:35:33 PM PDT 24 Jul 03 05:35:34 PM PDT 24 46932580 ps
T1124 /workspace/coverage/cover_reg_top/35.uart_intr_test.305813291 Jul 03 05:35:35 PM PDT 24 Jul 03 05:35:36 PM PDT 24 37535992 ps
T1125 /workspace/coverage/cover_reg_top/44.uart_intr_test.3935840029 Jul 03 05:35:39 PM PDT 24 Jul 03 05:35:40 PM PDT 24 26111352 ps
T1126 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3985810057 Jul 03 05:35:31 PM PDT 24 Jul 03 05:35:33 PM PDT 24 29774303 ps
T1127 /workspace/coverage/cover_reg_top/28.uart_intr_test.1710189224 Jul 03 05:35:32 PM PDT 24 Jul 03 05:35:33 PM PDT 24 27381691 ps
T67 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3131563533 Jul 03 05:35:32 PM PDT 24 Jul 03 05:35:33 PM PDT 24 60626628 ps
T1128 /workspace/coverage/cover_reg_top/8.uart_intr_test.1276802974 Jul 03 05:35:13 PM PDT 24 Jul 03 05:35:14 PM PDT 24 14970508 ps
T1129 /workspace/coverage/cover_reg_top/9.uart_tl_errors.817577849 Jul 03 05:35:17 PM PDT 24 Jul 03 05:35:18 PM PDT 24 26141354 ps
T1130 /workspace/coverage/cover_reg_top/6.uart_tl_errors.412720852 Jul 03 05:35:12 PM PDT 24 Jul 03 05:35:15 PM PDT 24 213208627 ps
T1131 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.950625043 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:07 PM PDT 24 65040802 ps
T68 /workspace/coverage/cover_reg_top/6.uart_csr_rw.367013001 Jul 03 05:35:09 PM PDT 24 Jul 03 05:35:10 PM PDT 24 38800904 ps
T1132 /workspace/coverage/cover_reg_top/16.uart_tl_errors.77286295 Jul 03 05:35:28 PM PDT 24 Jul 03 05:35:30 PM PDT 24 352864129 ps
T1133 /workspace/coverage/cover_reg_top/23.uart_intr_test.3955386814 Jul 03 05:35:38 PM PDT 24 Jul 03 05:35:39 PM PDT 24 14369672 ps
T61 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4152816627 Jul 03 05:34:58 PM PDT 24 Jul 03 05:34:59 PM PDT 24 17229016 ps
T69 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2633620580 Jul 03 05:35:19 PM PDT 24 Jul 03 05:35:19 PM PDT 24 18813504 ps
T1134 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2514160915 Jul 03 05:35:27 PM PDT 24 Jul 03 05:35:28 PM PDT 24 79088718 ps
T1135 /workspace/coverage/cover_reg_top/36.uart_intr_test.3453403454 Jul 03 05:35:38 PM PDT 24 Jul 03 05:35:39 PM PDT 24 80151778 ps
T70 /workspace/coverage/cover_reg_top/8.uart_csr_rw.271280722 Jul 03 05:35:16 PM PDT 24 Jul 03 05:35:17 PM PDT 24 10960429 ps
T1136 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1798247961 Jul 03 05:35:09 PM PDT 24 Jul 03 05:35:10 PM PDT 24 36245817 ps
T1137 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3101844536 Jul 03 05:35:09 PM PDT 24 Jul 03 05:35:11 PM PDT 24 121907840 ps
T1138 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.935278384 Jul 03 05:35:23 PM PDT 24 Jul 03 05:35:25 PM PDT 24 46120836 ps
T1139 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3689577047 Jul 03 05:35:16 PM PDT 24 Jul 03 05:35:17 PM PDT 24 28281770 ps
T1140 /workspace/coverage/cover_reg_top/40.uart_intr_test.3756014550 Jul 03 05:35:40 PM PDT 24 Jul 03 05:35:41 PM PDT 24 16899682 ps
T1141 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1886033409 Jul 03 05:35:29 PM PDT 24 Jul 03 05:35:31 PM PDT 24 841146125 ps
T1142 /workspace/coverage/cover_reg_top/29.uart_intr_test.2640913626 Jul 03 05:35:34 PM PDT 24 Jul 03 05:35:35 PM PDT 24 51104995 ps
T1143 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2120898110 Jul 03 05:35:29 PM PDT 24 Jul 03 05:35:30 PM PDT 24 399443899 ps
T1144 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3578283069 Jul 03 05:35:19 PM PDT 24 Jul 03 05:35:20 PM PDT 24 43489096 ps
T1145 /workspace/coverage/cover_reg_top/21.uart_intr_test.144506725 Jul 03 05:35:34 PM PDT 24 Jul 03 05:35:35 PM PDT 24 14790600 ps
T1146 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3097469398 Jul 03 05:35:22 PM PDT 24 Jul 03 05:35:24 PM PDT 24 946085287 ps
T80 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3527446334 Jul 03 05:35:24 PM PDT 24 Jul 03 05:35:25 PM PDT 24 193937474 ps
T1147 /workspace/coverage/cover_reg_top/2.uart_intr_test.2150563671 Jul 03 05:35:01 PM PDT 24 Jul 03 05:35:02 PM PDT 24 41508587 ps
T1148 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2287793721 Jul 03 05:35:29 PM PDT 24 Jul 03 05:35:31 PM PDT 24 34118711 ps
T52 /workspace/coverage/cover_reg_top/11.uart_csr_rw.5532599 Jul 03 05:35:20 PM PDT 24 Jul 03 05:35:21 PM PDT 24 15880721 ps
T1149 /workspace/coverage/cover_reg_top/9.uart_intr_test.2996508119 Jul 03 05:35:16 PM PDT 24 Jul 03 05:35:17 PM PDT 24 17413068 ps
T1150 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3444912299 Jul 03 05:35:24 PM PDT 24 Jul 03 05:35:25 PM PDT 24 18254399 ps
T96 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.5591241 Jul 03 05:35:25 PM PDT 24 Jul 03 05:35:26 PM PDT 24 93656592 ps
T1151 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3722611300 Jul 03 05:35:07 PM PDT 24 Jul 03 05:35:08 PM PDT 24 85447279 ps
T1152 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2221097653 Jul 03 05:35:12 PM PDT 24 Jul 03 05:35:13 PM PDT 24 23201125 ps
T76 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.848498031 Jul 03 05:35:28 PM PDT 24 Jul 03 05:35:29 PM PDT 24 180147508 ps
T53 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3172313915 Jul 03 05:35:02 PM PDT 24 Jul 03 05:35:03 PM PDT 24 55823707 ps
T1153 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2073445303 Jul 03 05:34:57 PM PDT 24 Jul 03 05:34:59 PM PDT 24 20785026 ps
T1154 /workspace/coverage/cover_reg_top/3.uart_intr_test.2316950118 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:06 PM PDT 24 19745246 ps
T98 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.600622159 Jul 03 05:35:18 PM PDT 24 Jul 03 05:35:19 PM PDT 24 47597657 ps
T54 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1004675865 Jul 03 05:35:04 PM PDT 24 Jul 03 05:35:07 PM PDT 24 84687121 ps
T1155 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1833438235 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:06 PM PDT 24 11190442 ps
T77 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.990999632 Jul 03 05:35:19 PM PDT 24 Jul 03 05:35:20 PM PDT 24 93379484 ps
T1156 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3625889151 Jul 03 05:35:27 PM PDT 24 Jul 03 05:35:28 PM PDT 24 43759826 ps
T1157 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3421212771 Jul 03 05:35:32 PM PDT 24 Jul 03 05:35:34 PM PDT 24 87511424 ps
T1158 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.865321149 Jul 03 05:35:09 PM PDT 24 Jul 03 05:35:10 PM PDT 24 15574293 ps
T1159 /workspace/coverage/cover_reg_top/5.uart_intr_test.1091576594 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:07 PM PDT 24 22077115 ps
T1160 /workspace/coverage/cover_reg_top/31.uart_intr_test.1700059380 Jul 03 05:35:34 PM PDT 24 Jul 03 05:35:35 PM PDT 24 43153860 ps
T1161 /workspace/coverage/cover_reg_top/6.uart_intr_test.2644433402 Jul 03 05:35:10 PM PDT 24 Jul 03 05:35:11 PM PDT 24 20598534 ps
T1162 /workspace/coverage/cover_reg_top/13.uart_intr_test.3505450606 Jul 03 05:35:22 PM PDT 24 Jul 03 05:35:23 PM PDT 24 13663527 ps
T99 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3256697186 Jul 03 05:35:12 PM PDT 24 Jul 03 05:35:13 PM PDT 24 202867189 ps
T1163 /workspace/coverage/cover_reg_top/32.uart_intr_test.295708566 Jul 03 05:35:31 PM PDT 24 Jul 03 05:35:32 PM PDT 24 11243464 ps
T1164 /workspace/coverage/cover_reg_top/34.uart_intr_test.3113721735 Jul 03 05:35:32 PM PDT 24 Jul 03 05:35:33 PM PDT 24 12817453 ps
T1165 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.571642124 Jul 03 05:35:08 PM PDT 24 Jul 03 05:35:09 PM PDT 24 97740728 ps
T1166 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2367274740 Jul 03 05:35:28 PM PDT 24 Jul 03 05:35:29 PM PDT 24 191180585 ps
T1167 /workspace/coverage/cover_reg_top/26.uart_intr_test.857316073 Jul 03 05:35:35 PM PDT 24 Jul 03 05:35:35 PM PDT 24 31825799 ps
T1168 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1960408623 Jul 03 05:35:01 PM PDT 24 Jul 03 05:35:02 PM PDT 24 31282690 ps
T1169 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3622591626 Jul 03 05:35:28 PM PDT 24 Jul 03 05:35:29 PM PDT 24 74034719 ps
T1170 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2888191867 Jul 03 05:35:30 PM PDT 24 Jul 03 05:35:31 PM PDT 24 62765183 ps
T1171 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1486772667 Jul 03 05:35:13 PM PDT 24 Jul 03 05:35:14 PM PDT 24 87141932 ps
T1172 /workspace/coverage/cover_reg_top/13.uart_tl_errors.4176192730 Jul 03 05:35:20 PM PDT 24 Jul 03 05:35:22 PM PDT 24 182426460 ps
T1173 /workspace/coverage/cover_reg_top/48.uart_intr_test.416645038 Jul 03 05:35:38 PM PDT 24 Jul 03 05:35:39 PM PDT 24 34154037 ps
T1174 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1674341653 Jul 03 05:35:22 PM PDT 24 Jul 03 05:35:23 PM PDT 24 41446403 ps
T1175 /workspace/coverage/cover_reg_top/16.uart_csr_rw.4200720431 Jul 03 05:35:29 PM PDT 24 Jul 03 05:35:30 PM PDT 24 18676512 ps
T55 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2088470492 Jul 03 05:35:04 PM PDT 24 Jul 03 05:35:05 PM PDT 24 60396127 ps
T1176 /workspace/coverage/cover_reg_top/24.uart_intr_test.2927714286 Jul 03 05:35:35 PM PDT 24 Jul 03 05:35:36 PM PDT 24 57840999 ps
T1177 /workspace/coverage/cover_reg_top/22.uart_intr_test.3356253107 Jul 03 05:35:34 PM PDT 24 Jul 03 05:35:35 PM PDT 24 25415706 ps
T1178 /workspace/coverage/cover_reg_top/13.uart_csr_rw.4000710173 Jul 03 05:35:24 PM PDT 24 Jul 03 05:35:25 PM PDT 24 144800841 ps
T1179 /workspace/coverage/cover_reg_top/39.uart_intr_test.3340913196 Jul 03 05:35:39 PM PDT 24 Jul 03 05:35:40 PM PDT 24 16230654 ps
T100 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1919582617 Jul 03 05:35:03 PM PDT 24 Jul 03 05:35:04 PM PDT 24 125563428 ps
T1180 /workspace/coverage/cover_reg_top/17.uart_intr_test.3426013865 Jul 03 05:35:30 PM PDT 24 Jul 03 05:35:31 PM PDT 24 16611140 ps
T1181 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3371432507 Jul 03 05:35:04 PM PDT 24 Jul 03 05:35:05 PM PDT 24 52641470 ps
T1182 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3525609374 Jul 03 05:35:35 PM PDT 24 Jul 03 05:35:36 PM PDT 24 21999872 ps
T1183 /workspace/coverage/cover_reg_top/41.uart_intr_test.2599729039 Jul 03 05:35:41 PM PDT 24 Jul 03 05:35:42 PM PDT 24 15683290 ps
T1184 /workspace/coverage/cover_reg_top/38.uart_intr_test.4001030423 Jul 03 05:35:38 PM PDT 24 Jul 03 05:35:39 PM PDT 24 41753279 ps
T1185 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2582465115 Jul 03 05:35:08 PM PDT 24 Jul 03 05:35:09 PM PDT 24 63145620 ps
T1186 /workspace/coverage/cover_reg_top/45.uart_intr_test.2075645587 Jul 03 05:35:37 PM PDT 24 Jul 03 05:35:38 PM PDT 24 14381107 ps
T1187 /workspace/coverage/cover_reg_top/16.uart_intr_test.2513699470 Jul 03 05:35:28 PM PDT 24 Jul 03 05:35:29 PM PDT 24 45241638 ps
T1188 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.717646501 Jul 03 05:35:08 PM PDT 24 Jul 03 05:35:09 PM PDT 24 61556441 ps
T1189 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3079785338 Jul 03 05:34:59 PM PDT 24 Jul 03 05:35:00 PM PDT 24 17992030 ps
T1190 /workspace/coverage/cover_reg_top/12.uart_tl_errors.34544890 Jul 03 05:35:23 PM PDT 24 Jul 03 05:35:25 PM PDT 24 63101649 ps
T1191 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.530542549 Jul 03 05:35:11 PM PDT 24 Jul 03 05:35:12 PM PDT 24 168923688 ps
T1192 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3095388337 Jul 03 05:35:18 PM PDT 24 Jul 03 05:35:19 PM PDT 24 29178461 ps
T1193 /workspace/coverage/cover_reg_top/15.uart_intr_test.1730567435 Jul 03 05:35:26 PM PDT 24 Jul 03 05:35:27 PM PDT 24 27340645 ps
T56 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2146814703 Jul 03 05:35:02 PM PDT 24 Jul 03 05:35:05 PM PDT 24 262307932 ps
T1194 /workspace/coverage/cover_reg_top/30.uart_intr_test.1199064511 Jul 03 05:35:33 PM PDT 24 Jul 03 05:35:33 PM PDT 24 19541155 ps
T1195 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3818039481 Jul 03 05:35:19 PM PDT 24 Jul 03 05:35:22 PM PDT 24 109088037 ps
T78 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.53618585 Jul 03 05:35:25 PM PDT 24 Jul 03 05:35:26 PM PDT 24 53668300 ps
T1196 /workspace/coverage/cover_reg_top/10.uart_intr_test.813332572 Jul 03 05:35:16 PM PDT 24 Jul 03 05:35:17 PM PDT 24 39915592 ps
T1197 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1340940964 Jul 03 05:35:09 PM PDT 24 Jul 03 05:35:11 PM PDT 24 75915371 ps
T1198 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.323506170 Jul 03 05:34:59 PM PDT 24 Jul 03 05:35:00 PM PDT 24 12691337 ps
T57 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1152977832 Jul 03 05:35:10 PM PDT 24 Jul 03 05:35:11 PM PDT 24 23992681 ps
T1199 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1224002112 Jul 03 05:35:08 PM PDT 24 Jul 03 05:35:09 PM PDT 24 37666922 ps
T58 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.472407156 Jul 03 05:35:04 PM PDT 24 Jul 03 05:35:05 PM PDT 24 322716088 ps
T1200 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1076647836 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:06 PM PDT 24 100791996 ps
T1201 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3779344439 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:06 PM PDT 24 28247530 ps
T1202 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1487999377 Jul 03 05:35:16 PM PDT 24 Jul 03 05:35:17 PM PDT 24 98154648 ps
T1203 /workspace/coverage/cover_reg_top/47.uart_intr_test.1908381602 Jul 03 05:35:39 PM PDT 24 Jul 03 05:35:40 PM PDT 24 68395729 ps
T1204 /workspace/coverage/cover_reg_top/15.uart_csr_rw.292876901 Jul 03 05:35:24 PM PDT 24 Jul 03 05:35:25 PM PDT 24 56393512 ps
T1205 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3291097907 Jul 03 05:35:17 PM PDT 24 Jul 03 05:35:19 PM PDT 24 18942762 ps
T1206 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2476176731 Jul 03 05:35:13 PM PDT 24 Jul 03 05:35:16 PM PDT 24 103397938 ps
T1207 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2308878645 Jul 03 05:35:07 PM PDT 24 Jul 03 05:35:09 PM PDT 24 27184265 ps
T97 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3850824881 Jul 03 05:35:23 PM PDT 24 Jul 03 05:35:25 PM PDT 24 91401203 ps
T1208 /workspace/coverage/cover_reg_top/2.uart_tl_errors.492367217 Jul 03 05:35:06 PM PDT 24 Jul 03 05:35:08 PM PDT 24 43648277 ps
T1209 /workspace/coverage/cover_reg_top/0.uart_intr_test.3002784847 Jul 03 05:34:58 PM PDT 24 Jul 03 05:34:59 PM PDT 24 13707880 ps
T59 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2482446961 Jul 03 05:35:05 PM PDT 24 Jul 03 05:35:06 PM PDT 24 37560023 ps
T1210 /workspace/coverage/cover_reg_top/10.uart_csr_rw.1752159376 Jul 03 05:35:17 PM PDT 24 Jul 03 05:35:18 PM PDT 24 44520939 ps
T1211 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2301164174 Jul 03 05:35:19 PM PDT 24 Jul 03 05:35:20 PM PDT 24 25591951 ps
T1212 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2298826326 Jul 03 05:35:13 PM PDT 24 Jul 03 05:35:14 PM PDT 24 259555069 ps
T1213 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2727145649 Jul 03 05:35:16 PM PDT 24 Jul 03 05:35:19 PM PDT 24 378479330 ps
T1214 /workspace/coverage/cover_reg_top/42.uart_intr_test.2062854886 Jul 03 05:35:37 PM PDT 24 Jul 03 05:35:38 PM PDT 24 43322705 ps
T1215 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3176427941 Jul 03 05:35:30 PM PDT 24 Jul 03 05:35:33 PM PDT 24 483047138 ps
T1216 /workspace/coverage/cover_reg_top/4.uart_intr_test.1190741431 Jul 03 05:35:08 PM PDT 24 Jul 03 05:35:09 PM PDT 24 33209914 ps
T79 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3855505031 Jul 03 05:35:08 PM PDT 24 Jul 03 05:35:09 PM PDT 24 747732587 ps
T1217 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2776741186 Jul 03 05:35:20 PM PDT 24 Jul 03 05:35:21 PM PDT 24 55882815 ps
T1218 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2667545399 Jul 03 05:35:09 PM PDT 24 Jul 03 05:35:11 PM PDT 24 94312787 ps
T1219 /workspace/coverage/cover_reg_top/12.uart_intr_test.1969762634 Jul 03 05:35:20 PM PDT 24 Jul 03 05:35:21 PM PDT 24 93284597 ps
T1220 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2865025480 Jul 03 05:35:17 PM PDT 24 Jul 03 05:35:18 PM PDT 24 47297561 ps
T1221 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1504229476 Jul 03 05:35:07 PM PDT 24 Jul 03 05:35:08 PM PDT 24 42770977 ps
T1222 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2827455380 Jul 03 05:35:06 PM PDT 24 Jul 03 05:35:07 PM PDT 24 23437764 ps
T1223 /workspace/coverage/cover_reg_top/5.uart_csr_rw.4125357587 Jul 03 05:35:10 PM PDT 24 Jul 03 05:35:11 PM PDT 24 15679415 ps
T1224 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2893616787 Jul 03 05:35:24 PM PDT 24 Jul 03 05:35:25 PM PDT 24 103724375 ps
T1225 /workspace/coverage/cover_reg_top/1.uart_intr_test.1894415963 Jul 03 05:35:01 PM PDT 24 Jul 03 05:35:02 PM PDT 24 16302117 ps
T1226 /workspace/coverage/cover_reg_top/7.uart_intr_test.374463190 Jul 03 05:35:11 PM PDT 24 Jul 03 05:35:12 PM PDT 24 54748847 ps

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.4040464907
Short name T8
Test name
Test status
Simulation time 162416634713 ps
CPU time 1210.74 seconds
Started Jul 03 05:43:04 PM PDT 24
Finished Jul 03 06:03:15 PM PDT 24
Peak memory 231520 kb
Host smart-6013bcbc-2d9e-46e0-8e10-72b4d579561f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040464907 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.4040464907
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2921419679
Short name T16
Test name
Test status
Simulation time 95197889790 ps
CPU time 840.2 seconds
Started Jul 03 05:44:55 PM PDT 24
Finished Jul 03 05:58:56 PM PDT 24
Peak memory 227140 kb
Host smart-f606b322-403a-44fb-ab0a-b161a4433f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921419679 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2921419679
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.3020421565
Short name T20
Test name
Test status
Simulation time 278285429442 ps
CPU time 278.09 seconds
Started Jul 03 05:44:40 PM PDT 24
Finished Jul 03 05:49:18 PM PDT 24
Peak memory 199964 kb
Host smart-5c3742c5-b9e8-4753-92bb-65951995093e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020421565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3020421565
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.300909355
Short name T21
Test name
Test status
Simulation time 226513522489 ps
CPU time 596.78 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:53:27 PM PDT 24
Peak memory 216584 kb
Host smart-fcfe92ea-397e-4618-b205-0727a71111f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300909355 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.300909355
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.1299965246
Short name T72
Test name
Test status
Simulation time 197938155858 ps
CPU time 304.26 seconds
Started Jul 03 05:43:43 PM PDT 24
Finished Jul 03 05:48:48 PM PDT 24
Peak memory 200020 kb
Host smart-02b86047-8237-4478-8c11-5698d58929a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299965246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1299965246
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.4287115087
Short name T243
Test name
Test status
Simulation time 109032338773 ps
CPU time 1112.23 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 06:02:33 PM PDT 24
Peak memory 199848 kb
Host smart-b11a0b36-3400-47d8-82f0-8e0ae81cc68c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287115087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.4287115087
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_stress_all.4132127301
Short name T130
Test name
Test status
Simulation time 227081883564 ps
CPU time 1320.78 seconds
Started Jul 03 05:42:51 PM PDT 24
Finished Jul 03 06:04:52 PM PDT 24
Peak memory 199908 kb
Host smart-8e776e7d-2b9e-4b32-aca5-e4616e9e91f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132127301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.4132127301
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_sec_cm.765276808
Short name T3
Test name
Test status
Simulation time 139792611 ps
CPU time 0.8 seconds
Started Jul 03 05:42:57 PM PDT 24
Finished Jul 03 05:42:58 PM PDT 24
Peak memory 218384 kb
Host smart-441292b4-519d-47b6-a423-a1cc9e7ba1db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765276808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.765276808
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.745924044
Short name T250
Test name
Test status
Simulation time 283349882928 ps
CPU time 192.91 seconds
Started Jul 03 05:45:37 PM PDT 24
Finished Jul 03 05:48:51 PM PDT 24
Peak memory 199952 kb
Host smart-ccadea05-5b96-4d1a-8258-165f6f96e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745924044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.745924044
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1522474486
Short name T4
Test name
Test status
Simulation time 337720766060 ps
CPU time 141.82 seconds
Started Jul 03 05:43:05 PM PDT 24
Finished Jul 03 05:45:28 PM PDT 24
Peak memory 199928 kb
Host smart-3ae24801-aadb-4da6-a7a2-3d3953ccdc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522474486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1522474486
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2998487162
Short name T89
Test name
Test status
Simulation time 40685316816 ps
CPU time 32.33 seconds
Started Jul 03 05:44:54 PM PDT 24
Finished Jul 03 05:45:27 PM PDT 24
Peak memory 200000 kb
Host smart-426cf742-4052-4e7e-b51e-3b64cfd5006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998487162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2998487162
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.482941838
Short name T136
Test name
Test status
Simulation time 328921491186 ps
CPU time 339.96 seconds
Started Jul 03 05:43:17 PM PDT 24
Finished Jul 03 05:48:57 PM PDT 24
Peak memory 199848 kb
Host smart-6d320a02-2e17-4a02-a914-6f859ace9410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482941838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.482941838
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.170255096
Short name T31
Test name
Test status
Simulation time 84482823073 ps
CPU time 733.96 seconds
Started Jul 03 05:44:58 PM PDT 24
Finished Jul 03 05:57:12 PM PDT 24
Peak memory 216552 kb
Host smart-07400489-7148-49be-97d2-a1cc219f7ddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170255096 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.170255096
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3284083391
Short name T2
Test name
Test status
Simulation time 19292387144 ps
CPU time 16.08 seconds
Started Jul 03 05:45:31 PM PDT 24
Finished Jul 03 05:45:47 PM PDT 24
Peak memory 199928 kb
Host smart-29119539-9741-42eb-8bfe-f454b7295bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284083391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3284083391
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2192668689
Short name T108
Test name
Test status
Simulation time 64517791253 ps
CPU time 43.41 seconds
Started Jul 03 05:45:23 PM PDT 24
Finished Jul 03 05:46:06 PM PDT 24
Peak memory 199912 kb
Host smart-31d1769c-1ca4-49a3-a01b-8032412063a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192668689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2192668689
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1994222259
Short name T194
Test name
Test status
Simulation time 70527425588 ps
CPU time 38.88 seconds
Started Jul 03 05:46:11 PM PDT 24
Finished Jul 03 05:46:50 PM PDT 24
Peak memory 199824 kb
Host smart-1e8a918b-4aea-4672-952a-39e578a57ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994222259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1994222259
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1918629048
Short name T73
Test name
Test status
Simulation time 309507012 ps
CPU time 1.38 seconds
Started Jul 03 05:35:02 PM PDT 24
Finished Jul 03 05:35:04 PM PDT 24
Peak memory 200288 kb
Host smart-ea3f5cf1-d606-4009-b50a-d5ea6f2b3f94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918629048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1918629048
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3925329262
Short name T144
Test name
Test status
Simulation time 965621115150 ps
CPU time 1040.95 seconds
Started Jul 03 05:43:33 PM PDT 24
Finished Jul 03 06:00:55 PM PDT 24
Peak memory 229720 kb
Host smart-69c63345-acc0-43e1-85d1-c95b5eb47b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925329262 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3925329262
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_alert_test.2097347002
Short name T24
Test name
Test status
Simulation time 22715213 ps
CPU time 0.57 seconds
Started Jul 03 05:43:03 PM PDT 24
Finished Jul 03 05:43:04 PM PDT 24
Peak memory 195328 kb
Host smart-36b2239c-bda9-4884-914c-d4a85feb8a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097347002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2097347002
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2960341491
Short name T50
Test name
Test status
Simulation time 33892404 ps
CPU time 0.63 seconds
Started Jul 03 05:35:30 PM PDT 24
Finished Jul 03 05:35:31 PM PDT 24
Peak memory 196176 kb
Host smart-8849b006-0ed5-44f0-a10d-6ca9cd9fc22f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960341491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2960341491
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1473236265
Short name T114
Test name
Test status
Simulation time 113760862625 ps
CPU time 107.08 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:45:46 PM PDT 24
Peak memory 199988 kb
Host smart-6e506d5c-9783-4f9f-b329-8c51917edb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473236265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1473236265
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_perf.713208441
Short name T254
Test name
Test status
Simulation time 29476058108 ps
CPU time 355.82 seconds
Started Jul 03 05:43:01 PM PDT 24
Finished Jul 03 05:48:58 PM PDT 24
Peak memory 199952 kb
Host smart-911185ed-2844-4ce5-ac28-b31cb2084e3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713208441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.713208441
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.287032292
Short name T228
Test name
Test status
Simulation time 171346726517 ps
CPU time 190.89 seconds
Started Jul 03 05:45:17 PM PDT 24
Finished Jul 03 05:48:28 PM PDT 24
Peak memory 200004 kb
Host smart-f71ddc4f-e0a6-419c-b280-1d0dea5a8188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287032292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.287032292
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4272871732
Short name T181
Test name
Test status
Simulation time 43178865633 ps
CPU time 50.82 seconds
Started Jul 03 05:45:56 PM PDT 24
Finished Jul 03 05:46:47 PM PDT 24
Peak memory 199920 kb
Host smart-406e1a5e-c055-453f-b756-6a3ba9cce0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272871732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4272871732
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2592177421
Short name T109
Test name
Test status
Simulation time 102680384781 ps
CPU time 45.39 seconds
Started Jul 03 05:45:29 PM PDT 24
Finished Jul 03 05:46:15 PM PDT 24
Peak memory 199872 kb
Host smart-5931ba0a-3ec1-4482-ac71-52377e1df0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592177421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2592177421
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.458593196
Short name T27
Test name
Test status
Simulation time 134134385196 ps
CPU time 278.49 seconds
Started Jul 03 05:45:17 PM PDT 24
Finished Jul 03 05:49:55 PM PDT 24
Peak memory 216460 kb
Host smart-e8584b27-06cb-473d-b7f1-3a6892cef115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458593196 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.458593196
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1330485071
Short name T544
Test name
Test status
Simulation time 667081458824 ps
CPU time 1096.88 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 06:01:33 PM PDT 24
Peak memory 216580 kb
Host smart-148cd687-a1da-4248-a829-26bb714d6094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330485071 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1330485071
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.626168706
Short name T14
Test name
Test status
Simulation time 142893793035 ps
CPU time 53.51 seconds
Started Jul 03 05:45:27 PM PDT 24
Finished Jul 03 05:46:21 PM PDT 24
Peak memory 200004 kb
Host smart-92434ff9-56c3-4c32-91a7-2c1063e70653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626168706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.626168706
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.2625297701
Short name T113
Test name
Test status
Simulation time 224206877622 ps
CPU time 807.82 seconds
Started Jul 03 05:43:50 PM PDT 24
Finished Jul 03 05:57:19 PM PDT 24
Peak memory 199948 kb
Host smart-5ffa2cec-4ea9-4246-b909-9e763d030fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625297701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2625297701
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1575170185
Short name T111
Test name
Test status
Simulation time 28006355599 ps
CPU time 12.42 seconds
Started Jul 03 05:45:27 PM PDT 24
Finished Jul 03 05:45:39 PM PDT 24
Peak memory 199900 kb
Host smart-b31bcf5c-8ca5-4813-96d4-9a9e12be54db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575170185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1575170185
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all.2615309855
Short name T143
Test name
Test status
Simulation time 427065927920 ps
CPU time 81.91 seconds
Started Jul 03 05:43:55 PM PDT 24
Finished Jul 03 05:45:17 PM PDT 24
Peak memory 199816 kb
Host smart-20468a4b-e39b-4b58-b4b1-2622ca01a483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615309855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2615309855
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3389665090
Short name T75
Test name
Test status
Simulation time 143865923 ps
CPU time 0.93 seconds
Started Jul 03 05:35:29 PM PDT 24
Finished Jul 03 05:35:31 PM PDT 24
Peak memory 199512 kb
Host smart-3c04d4b7-a9c5-43dd-b323-a92520a1b87d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389665090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3389665090
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/19.uart_perf.441749231
Short name T387
Test name
Test status
Simulation time 12644954935 ps
CPU time 613.4 seconds
Started Jul 03 05:43:38 PM PDT 24
Finished Jul 03 05:53:52 PM PDT 24
Peak memory 199940 kb
Host smart-c590c3ae-2a0b-4d99-8ce1-96a649a92cfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441749231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.441749231
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1800113429
Short name T223
Test name
Test status
Simulation time 156171411036 ps
CPU time 67.64 seconds
Started Jul 03 05:44:02 PM PDT 24
Finished Jul 03 05:45:10 PM PDT 24
Peak memory 199760 kb
Host smart-820791ac-c00a-4f6b-8e72-18d6be67597f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800113429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1800113429
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3592647554
Short name T225
Test name
Test status
Simulation time 92214197885 ps
CPU time 172.81 seconds
Started Jul 03 05:45:28 PM PDT 24
Finished Jul 03 05:48:21 PM PDT 24
Peak memory 199916 kb
Host smart-1079cc25-6baf-4c67-b621-254f148e7916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592647554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3592647554
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1076647836
Short name T1200
Test name
Test status
Simulation time 100791996 ps
CPU time 0.89 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:06 PM PDT 24
Peak memory 199360 kb
Host smart-8c1eb373-06b0-4972-ab38-e659b6f35688
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076647836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1076647836
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3375359232
Short name T159
Test name
Test status
Simulation time 20027874320 ps
CPU time 18.19 seconds
Started Jul 03 05:45:53 PM PDT 24
Finished Jul 03 05:46:11 PM PDT 24
Peak memory 199856 kb
Host smart-204502df-16fe-4bf3-84ec-12bd3ec18312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375359232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3375359232
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3808598351
Short name T156
Test name
Test status
Simulation time 102864506411 ps
CPU time 84.62 seconds
Started Jul 03 05:46:16 PM PDT 24
Finished Jul 03 05:47:41 PM PDT 24
Peak memory 199940 kb
Host smart-ab672d7a-7d8e-4b88-99ae-aa44efdcedd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808598351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3808598351
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1228724310
Short name T115
Test name
Test status
Simulation time 131876026671 ps
CPU time 98.07 seconds
Started Jul 03 05:45:20 PM PDT 24
Finished Jul 03 05:46:58 PM PDT 24
Peak memory 199892 kb
Host smart-1f58ab06-ea38-41d3-b4dd-62ce4eab98b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228724310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1228724310
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.4027155391
Short name T48
Test name
Test status
Simulation time 210528276816 ps
CPU time 790.73 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:56:33 PM PDT 24
Peak memory 216452 kb
Host smart-5a511478-1a2d-4d12-949d-60cdd8179afd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027155391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.4027155391
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3263143903
Short name T1049
Test name
Test status
Simulation time 58801732169 ps
CPU time 143.47 seconds
Started Jul 03 05:45:28 PM PDT 24
Finished Jul 03 05:47:52 PM PDT 24
Peak memory 200012 kb
Host smart-d090e34a-4b46-4dbc-bb94-f3551994e25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263143903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3263143903
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1312199942
Short name T28
Test name
Test status
Simulation time 37454785953 ps
CPU time 826.03 seconds
Started Jul 03 05:44:54 PM PDT 24
Finished Jul 03 05:58:41 PM PDT 24
Peak memory 216552 kb
Host smart-83915804-9154-4443-9a7d-89f97e2915b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312199942 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1312199942
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1604450905
Short name T150
Test name
Test status
Simulation time 77028716182 ps
CPU time 67.86 seconds
Started Jul 03 05:45:21 PM PDT 24
Finished Jul 03 05:46:29 PM PDT 24
Peak memory 199896 kb
Host smart-c5f53a83-77ff-4a49-89d9-e1fd38aaddb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604450905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1604450905
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.864976616
Short name T185
Test name
Test status
Simulation time 39088897164 ps
CPU time 17.83 seconds
Started Jul 03 05:45:23 PM PDT 24
Finished Jul 03 05:45:41 PM PDT 24
Peak memory 199916 kb
Host smart-0f3b0720-bda2-409c-acb3-bcabee298fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864976616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.864976616
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2566994528
Short name T795
Test name
Test status
Simulation time 18602551272 ps
CPU time 31.86 seconds
Started Jul 03 05:45:41 PM PDT 24
Finished Jul 03 05:46:14 PM PDT 24
Peak memory 199964 kb
Host smart-2eab93e5-6e3c-4761-8186-71ade109e105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566994528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2566994528
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1735753364
Short name T85
Test name
Test status
Simulation time 534125464195 ps
CPU time 452.75 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:51:03 PM PDT 24
Peak memory 214460 kb
Host smart-282461e8-bfb5-4d6f-90ee-992965229077
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735753364 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1735753364
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all.3638379382
Short name T418
Test name
Test status
Simulation time 243534327455 ps
CPU time 1753.5 seconds
Started Jul 03 05:44:55 PM PDT 24
Finished Jul 03 06:14:09 PM PDT 24
Peak memory 199856 kb
Host smart-48979ea3-2945-475f-90ae-eacde936ffb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638379382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3638379382
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.4096211222
Short name T276
Test name
Test status
Simulation time 97073293514 ps
CPU time 154.18 seconds
Started Jul 03 05:45:27 PM PDT 24
Finished Jul 03 05:48:02 PM PDT 24
Peak memory 199960 kb
Host smart-0a0db8d5-19bd-4a9f-b3b4-9e8d146b175d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096211222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.4096211222
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2117930739
Short name T220
Test name
Test status
Simulation time 112476689350 ps
CPU time 44.85 seconds
Started Jul 03 05:45:34 PM PDT 24
Finished Jul 03 05:46:19 PM PDT 24
Peak memory 199584 kb
Host smart-d8c40fa4-402b-4bf8-82ea-524e4c54b841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117930739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2117930739
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2992883825
Short name T110
Test name
Test status
Simulation time 68946238189 ps
CPU time 174.6 seconds
Started Jul 03 05:45:47 PM PDT 24
Finished Jul 03 05:48:42 PM PDT 24
Peak memory 200016 kb
Host smart-20f2e1e7-ba00-414f-9d88-a41511bfff30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992883825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2992883825
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1256687034
Short name T218
Test name
Test status
Simulation time 29022895723 ps
CPU time 34.96 seconds
Started Jul 03 05:44:59 PM PDT 24
Finished Jul 03 05:45:35 PM PDT 24
Peak memory 199920 kb
Host smart-ce10a576-8055-4cbc-b728-85d0e0dc1904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256687034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1256687034
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1312431643
Short name T213
Test name
Test status
Simulation time 192955995676 ps
CPU time 168.59 seconds
Started Jul 03 05:45:13 PM PDT 24
Finished Jul 03 05:48:02 PM PDT 24
Peak memory 199980 kb
Host smart-999e4107-dfe2-4841-9d7d-913144398db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312431643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1312431643
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2630809245
Short name T197
Test name
Test status
Simulation time 59868678723 ps
CPU time 42.57 seconds
Started Jul 03 05:42:40 PM PDT 24
Finished Jul 03 05:43:23 PM PDT 24
Peak memory 199936 kb
Host smart-b0d9c3f8-590a-4df1-bdd2-37b320c204bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630809245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2630809245
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_tx_rx.407038727
Short name T1029
Test name
Test status
Simulation time 15784336984 ps
CPU time 16.04 seconds
Started Jul 03 05:43:10 PM PDT 24
Finished Jul 03 05:43:27 PM PDT 24
Peak memory 199828 kb
Host smart-51b18c34-a739-407d-8e89-a1221c888b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407038727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.407038727
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.235699009
Short name T287
Test name
Test status
Simulation time 49087613598 ps
CPU time 22.22 seconds
Started Jul 03 05:43:32 PM PDT 24
Finished Jul 03 05:43:54 PM PDT 24
Peak memory 199844 kb
Host smart-12ca9201-d4d5-4ff6-b10d-9ef9ca2b8772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235699009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.235699009
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2972162642
Short name T200
Test name
Test status
Simulation time 122865932464 ps
CPU time 115.11 seconds
Started Jul 03 05:45:19 PM PDT 24
Finished Jul 03 05:47:14 PM PDT 24
Peak memory 200000 kb
Host smart-34f2fd49-cd6a-4030-8040-d36e52c49e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972162642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2972162642
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3885895045
Short name T193
Test name
Test status
Simulation time 99724905032 ps
CPU time 145.27 seconds
Started Jul 03 05:45:20 PM PDT 24
Finished Jul 03 05:47:46 PM PDT 24
Peak memory 200000 kb
Host smart-0595dec1-50fb-46ca-b52a-ffc95cc22c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885895045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3885895045
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.99612662
Short name T168
Test name
Test status
Simulation time 25138935494 ps
CPU time 17.31 seconds
Started Jul 03 05:45:20 PM PDT 24
Finished Jul 03 05:45:38 PM PDT 24
Peak memory 199996 kb
Host smart-9c78ae90-cdcb-4fe8-91ee-0e7ff4718272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99612662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.99612662
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2195497510
Short name T704
Test name
Test status
Simulation time 63616250899 ps
CPU time 104.77 seconds
Started Jul 03 05:45:24 PM PDT 24
Finished Jul 03 05:47:09 PM PDT 24
Peak memory 199864 kb
Host smart-41e24129-6b4a-4e33-85b5-c33c5306de1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195497510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2195497510
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2850754759
Short name T216
Test name
Test status
Simulation time 166209719001 ps
CPU time 36.58 seconds
Started Jul 03 05:42:53 PM PDT 24
Finished Jul 03 05:43:35 PM PDT 24
Peak memory 199912 kb
Host smart-65fef67c-2729-40e1-8d6a-2a69a4a29561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850754759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2850754759
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1579364904
Short name T151
Test name
Test status
Simulation time 44858524306 ps
CPU time 71.29 seconds
Started Jul 03 05:45:40 PM PDT 24
Finished Jul 03 05:46:52 PM PDT 24
Peak memory 199924 kb
Host smart-999ab8fc-3294-4e77-8ba6-bae8c85040ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579364904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1579364904
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1948195122
Short name T176
Test name
Test status
Simulation time 107264260137 ps
CPU time 85.27 seconds
Started Jul 03 05:45:43 PM PDT 24
Finished Jul 03 05:47:08 PM PDT 24
Peak memory 199964 kb
Host smart-837836a8-ce11-4cdc-b06b-7440ce8f81e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948195122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1948195122
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2827084973
Short name T188
Test name
Test status
Simulation time 128685513386 ps
CPU time 56.08 seconds
Started Jul 03 05:43:24 PM PDT 24
Finished Jul 03 05:44:20 PM PDT 24
Peak memory 199968 kb
Host smart-104aceff-2b2c-4476-8072-9b583a367fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827084973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2827084973
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.433018111
Short name T211
Test name
Test status
Simulation time 89198051403 ps
CPU time 77.79 seconds
Started Jul 03 05:45:54 PM PDT 24
Finished Jul 03 05:47:12 PM PDT 24
Peak memory 199852 kb
Host smart-621ac3e2-e8ad-413e-a151-3dec7dcd059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433018111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.433018111
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.2085254619
Short name T94
Test name
Test status
Simulation time 188303768277 ps
CPU time 488.61 seconds
Started Jul 03 05:42:55 PM PDT 24
Finished Jul 03 05:51:04 PM PDT 24
Peak memory 199928 kb
Host smart-2414a746-5ad4-46d4-9b65-9e6381d5b702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085254619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2085254619
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2268703849
Short name T221
Test name
Test status
Simulation time 43061621239 ps
CPU time 17.56 seconds
Started Jul 03 05:45:06 PM PDT 24
Finished Jul 03 05:45:24 PM PDT 24
Peak memory 200008 kb
Host smart-f2ffc66f-4d91-4b3b-a907-c21dd354f511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268703849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2268703849
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2073445303
Short name T1153
Test name
Test status
Simulation time 20785026 ps
CPU time 0.69 seconds
Started Jul 03 05:34:57 PM PDT 24
Finished Jul 03 05:34:59 PM PDT 24
Peak memory 196264 kb
Host smart-bb221a92-f407-4c40-940a-cbd113bb26cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073445303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2073445303
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.172513147
Short name T1102
Test name
Test status
Simulation time 36665856 ps
CPU time 1.39 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:07 PM PDT 24
Peak memory 198312 kb
Host smart-81d145fc-07c4-42ac-af07-4e3d1053a311
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172513147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.172513147
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4152816627
Short name T61
Test name
Test status
Simulation time 17229016 ps
CPU time 0.57 seconds
Started Jul 03 05:34:58 PM PDT 24
Finished Jul 03 05:34:59 PM PDT 24
Peak memory 196100 kb
Host smart-2ead77d9-9087-4bb8-b9ba-d97e36a2c970
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152816627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4152816627
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1014089516
Short name T1114
Test name
Test status
Simulation time 84682243 ps
CPU time 1.27 seconds
Started Jul 03 05:34:59 PM PDT 24
Finished Jul 03 05:35:01 PM PDT 24
Peak memory 200892 kb
Host smart-4a53ac74-054c-4051-942e-7b17175b9012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014089516 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1014089516
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3079785338
Short name T1189
Test name
Test status
Simulation time 17992030 ps
CPU time 0.65 seconds
Started Jul 03 05:34:59 PM PDT 24
Finished Jul 03 05:35:00 PM PDT 24
Peak memory 196308 kb
Host smart-047d6b53-aca4-4d05-9726-9b045e51dfd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079785338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3079785338
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3002784847
Short name T1209
Test name
Test status
Simulation time 13707880 ps
CPU time 0.6 seconds
Started Jul 03 05:34:58 PM PDT 24
Finished Jul 03 05:34:59 PM PDT 24
Peak memory 195152 kb
Host smart-5b2f8352-a983-4204-9057-215714b848dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002784847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3002784847
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.323506170
Short name T1198
Test name
Test status
Simulation time 12691337 ps
CPU time 0.6 seconds
Started Jul 03 05:34:59 PM PDT 24
Finished Jul 03 05:35:00 PM PDT 24
Peak memory 195156 kb
Host smart-00dd2294-2180-4de2-9fee-9217e8509d6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323506170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.323506170
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2957127257
Short name T1118
Test name
Test status
Simulation time 44891495 ps
CPU time 1.7 seconds
Started Jul 03 05:35:01 PM PDT 24
Finished Jul 03 05:35:03 PM PDT 24
Peak memory 200800 kb
Host smart-887b6053-aea5-4739-8d61-10692d6b67f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957127257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2957127257
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1919582617
Short name T100
Test name
Test status
Simulation time 125563428 ps
CPU time 1.19 seconds
Started Jul 03 05:35:03 PM PDT 24
Finished Jul 03 05:35:04 PM PDT 24
Peak memory 199944 kb
Host smart-69783bf0-4bc5-4de8-97d3-1919cb1fb048
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919582617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1919582617
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.472407156
Short name T58
Test name
Test status
Simulation time 322716088 ps
CPU time 0.79 seconds
Started Jul 03 05:35:04 PM PDT 24
Finished Jul 03 05:35:05 PM PDT 24
Peak memory 197324 kb
Host smart-e5a7b583-5333-4de1-9ba1-0d3c85f1f248
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472407156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.472407156
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3184742949
Short name T1120
Test name
Test status
Simulation time 128817709 ps
CPU time 1.41 seconds
Started Jul 03 05:35:07 PM PDT 24
Finished Jul 03 05:35:09 PM PDT 24
Peak memory 198396 kb
Host smart-5cd67e3c-e1a0-4522-bfc5-be056485431c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184742949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3184742949
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3172313915
Short name T53
Test name
Test status
Simulation time 55823707 ps
CPU time 0.61 seconds
Started Jul 03 05:35:02 PM PDT 24
Finished Jul 03 05:35:03 PM PDT 24
Peak memory 196128 kb
Host smart-994c27c7-54dc-40ba-81cf-3de6072c228c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172313915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3172313915
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.950625043
Short name T1131
Test name
Test status
Simulation time 65040802 ps
CPU time 1.38 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:07 PM PDT 24
Peak memory 200768 kb
Host smart-b210d0f1-d25a-45f9-84d9-0fea72b4dc48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950625043 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.950625043
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3722611300
Short name T1151
Test name
Test status
Simulation time 85447279 ps
CPU time 0.59 seconds
Started Jul 03 05:35:07 PM PDT 24
Finished Jul 03 05:35:08 PM PDT 24
Peak memory 196180 kb
Host smart-44fbb051-fe45-4297-89e6-5cce5bd08f5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722611300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3722611300
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1894415963
Short name T1225
Test name
Test status
Simulation time 16302117 ps
CPU time 0.55 seconds
Started Jul 03 05:35:01 PM PDT 24
Finished Jul 03 05:35:02 PM PDT 24
Peak memory 195224 kb
Host smart-c88c6a91-85e5-4fd4-b7f8-8645de38e278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894415963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1894415963
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.717646501
Short name T1188
Test name
Test status
Simulation time 61556441 ps
CPU time 0.79 seconds
Started Jul 03 05:35:08 PM PDT 24
Finished Jul 03 05:35:09 PM PDT 24
Peak memory 196772 kb
Host smart-7a9751f0-2a41-44f7-a9f9-cb04107259a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717646501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.717646501
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3084326407
Short name T1113
Test name
Test status
Simulation time 155848226 ps
CPU time 2.06 seconds
Started Jul 03 05:35:03 PM PDT 24
Finished Jul 03 05:35:06 PM PDT 24
Peak memory 200776 kb
Host smart-8ed20045-ec9b-4e90-8b9f-0aeabafc80b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084326407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3084326407
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3853352895
Short name T1106
Test name
Test status
Simulation time 36971393 ps
CPU time 0.78 seconds
Started Jul 03 05:35:15 PM PDT 24
Finished Jul 03 05:35:16 PM PDT 24
Peak memory 200524 kb
Host smart-14a561e6-cadf-4e2a-beb8-044b379ba4af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853352895 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3853352895
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1752159376
Short name T1210
Test name
Test status
Simulation time 44520939 ps
CPU time 0.61 seconds
Started Jul 03 05:35:17 PM PDT 24
Finished Jul 03 05:35:18 PM PDT 24
Peak memory 196148 kb
Host smart-e59c50d7-ac70-4c07-af23-4e745901a260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752159376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1752159376
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.813332572
Short name T1196
Test name
Test status
Simulation time 39915592 ps
CPU time 0.56 seconds
Started Jul 03 05:35:16 PM PDT 24
Finished Jul 03 05:35:17 PM PDT 24
Peak memory 195132 kb
Host smart-749998ab-5c93-49b8-b85e-850bd427a53b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813332572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.813332572
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1487999377
Short name T1202
Test name
Test status
Simulation time 98154648 ps
CPU time 0.73 seconds
Started Jul 03 05:35:16 PM PDT 24
Finished Jul 03 05:35:17 PM PDT 24
Peak memory 197724 kb
Host smart-c6c2bc72-eb06-4891-ba44-224c1dcaa13b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487999377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1487999377
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2727145649
Short name T1213
Test name
Test status
Simulation time 378479330 ps
CPU time 2.19 seconds
Started Jul 03 05:35:16 PM PDT 24
Finished Jul 03 05:35:19 PM PDT 24
Peak memory 200796 kb
Host smart-be286eb6-6f1f-4cd6-8392-d0b182735863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727145649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2727145649
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.990999632
Short name T77
Test name
Test status
Simulation time 93379484 ps
CPU time 1 seconds
Started Jul 03 05:35:19 PM PDT 24
Finished Jul 03 05:35:20 PM PDT 24
Peak memory 199604 kb
Host smart-7744007b-30e3-409e-8fcd-140221d1817b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990999632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.990999632
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1386296822
Short name T1115
Test name
Test status
Simulation time 150430067 ps
CPU time 0.85 seconds
Started Jul 03 05:35:22 PM PDT 24
Finished Jul 03 05:35:23 PM PDT 24
Peak memory 200620 kb
Host smart-d602f89f-c29d-41bf-a6da-4491d057925a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386296822 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1386296822
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.5532599
Short name T52
Test name
Test status
Simulation time 15880721 ps
CPU time 0.58 seconds
Started Jul 03 05:35:20 PM PDT 24
Finished Jul 03 05:35:21 PM PDT 24
Peak memory 196136 kb
Host smart-1f6285f3-ba16-4643-84cc-05240469341d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5532599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.5532599
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3452339385
Short name T1096
Test name
Test status
Simulation time 13279878 ps
CPU time 0.57 seconds
Started Jul 03 05:35:20 PM PDT 24
Finished Jul 03 05:35:21 PM PDT 24
Peak memory 195148 kb
Host smart-0c9c64fb-db25-4d08-baa6-96f2905f49bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452339385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3452339385
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2633620580
Short name T69
Test name
Test status
Simulation time 18813504 ps
CPU time 0.65 seconds
Started Jul 03 05:35:19 PM PDT 24
Finished Jul 03 05:35:19 PM PDT 24
Peak memory 197364 kb
Host smart-b752b081-0560-4186-9fab-04b882352910
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633620580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2633620580
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3818039481
Short name T1195
Test name
Test status
Simulation time 109088037 ps
CPU time 2.41 seconds
Started Jul 03 05:35:19 PM PDT 24
Finished Jul 03 05:35:22 PM PDT 24
Peak memory 200804 kb
Host smart-e2d28d0d-9315-4d11-85e4-732926bbe62c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818039481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3818039481
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2865025480
Short name T1220
Test name
Test status
Simulation time 47297561 ps
CPU time 0.98 seconds
Started Jul 03 05:35:17 PM PDT 24
Finished Jul 03 05:35:18 PM PDT 24
Peak memory 199672 kb
Host smart-27da8397-f464-4793-95e5-53de9dcfc809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865025480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2865025480
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3095388337
Short name T1192
Test name
Test status
Simulation time 29178461 ps
CPU time 0.75 seconds
Started Jul 03 05:35:18 PM PDT 24
Finished Jul 03 05:35:19 PM PDT 24
Peak memory 199020 kb
Host smart-345b1030-cb3e-4379-b205-e1f106c71966
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095388337 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3095388337
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1674341653
Short name T1174
Test name
Test status
Simulation time 41446403 ps
CPU time 0.6 seconds
Started Jul 03 05:35:22 PM PDT 24
Finished Jul 03 05:35:23 PM PDT 24
Peak memory 196180 kb
Host smart-c8783187-a208-4954-8fdc-37771fd1df12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674341653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1674341653
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1969762634
Short name T1219
Test name
Test status
Simulation time 93284597 ps
CPU time 0.57 seconds
Started Jul 03 05:35:20 PM PDT 24
Finished Jul 03 05:35:21 PM PDT 24
Peak memory 195160 kb
Host smart-8a8558c5-7b01-419a-b170-9240accab354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969762634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1969762634
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4142276249
Short name T64
Test name
Test status
Simulation time 72677282 ps
CPU time 0.63 seconds
Started Jul 03 05:35:20 PM PDT 24
Finished Jul 03 05:35:21 PM PDT 24
Peak memory 195288 kb
Host smart-3a72a6db-9b4d-4290-8cbb-8f2de23d53b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142276249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.4142276249
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.34544890
Short name T1190
Test name
Test status
Simulation time 63101649 ps
CPU time 1.46 seconds
Started Jul 03 05:35:23 PM PDT 24
Finished Jul 03 05:35:25 PM PDT 24
Peak memory 200880 kb
Host smart-742a9e99-6dd8-46b4-b1d8-ad98d1533533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34544890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.34544890
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3850824881
Short name T97
Test name
Test status
Simulation time 91401203 ps
CPU time 1.33 seconds
Started Jul 03 05:35:23 PM PDT 24
Finished Jul 03 05:35:25 PM PDT 24
Peak memory 199968 kb
Host smart-4f1109e2-34e5-4df5-89ac-a08cce957729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850824881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3850824881
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2301164174
Short name T1211
Test name
Test status
Simulation time 25591951 ps
CPU time 0.85 seconds
Started Jul 03 05:35:19 PM PDT 24
Finished Jul 03 05:35:20 PM PDT 24
Peak memory 200556 kb
Host smart-696521ce-63be-418c-ae10-26c4f341b81f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301164174 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2301164174
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.4000710173
Short name T1178
Test name
Test status
Simulation time 144800841 ps
CPU time 0.62 seconds
Started Jul 03 05:35:24 PM PDT 24
Finished Jul 03 05:35:25 PM PDT 24
Peak memory 196204 kb
Host smart-45f847fc-7fb0-4794-b281-8d8cacc73d00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000710173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.4000710173
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3505450606
Short name T1162
Test name
Test status
Simulation time 13663527 ps
CPU time 0.59 seconds
Started Jul 03 05:35:22 PM PDT 24
Finished Jul 03 05:35:23 PM PDT 24
Peak memory 195020 kb
Host smart-46770099-9ca5-460e-8689-37e8b7e15199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505450606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3505450606
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2776741186
Short name T1217
Test name
Test status
Simulation time 55882815 ps
CPU time 0.76 seconds
Started Jul 03 05:35:20 PM PDT 24
Finished Jul 03 05:35:21 PM PDT 24
Peak memory 197760 kb
Host smart-e3f62446-d667-419c-a17d-c2c549701dc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776741186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2776741186
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.4176192730
Short name T1172
Test name
Test status
Simulation time 182426460 ps
CPU time 2.25 seconds
Started Jul 03 05:35:20 PM PDT 24
Finished Jul 03 05:35:22 PM PDT 24
Peak memory 200852 kb
Host smart-1bae4742-fd37-49f6-bbcf-a0cb8687559c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176192730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4176192730
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3527446334
Short name T80
Test name
Test status
Simulation time 193937474 ps
CPU time 0.99 seconds
Started Jul 03 05:35:24 PM PDT 24
Finished Jul 03 05:35:25 PM PDT 24
Peak memory 199556 kb
Host smart-67aedf99-bdff-4d4b-8d09-3696cd8e8e14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527446334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3527446334
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.935278384
Short name T1138
Test name
Test status
Simulation time 46120836 ps
CPU time 0.8 seconds
Started Jul 03 05:35:23 PM PDT 24
Finished Jul 03 05:35:25 PM PDT 24
Peak memory 200596 kb
Host smart-ff74450a-ae35-4d49-93f8-3e0dbd15aa00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935278384 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.935278384
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2893616787
Short name T1224
Test name
Test status
Simulation time 103724375 ps
CPU time 0.6 seconds
Started Jul 03 05:35:24 PM PDT 24
Finished Jul 03 05:35:25 PM PDT 24
Peak memory 196216 kb
Host smart-c40e4483-3964-43df-a612-0f012d5d1892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893616787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2893616787
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3954933967
Short name T1122
Test name
Test status
Simulation time 13453819 ps
CPU time 0.56 seconds
Started Jul 03 05:35:27 PM PDT 24
Finished Jul 03 05:35:27 PM PDT 24
Peak memory 195196 kb
Host smart-67100c0f-89e8-4b87-862c-e8eb23024f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954933967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3954933967
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2449805788
Short name T65
Test name
Test status
Simulation time 18731560 ps
CPU time 0.68 seconds
Started Jul 03 05:35:24 PM PDT 24
Finished Jul 03 05:35:25 PM PDT 24
Peak memory 195304 kb
Host smart-a0c6136c-d619-4089-9f96-50634574373d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449805788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2449805788
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3097469398
Short name T1146
Test name
Test status
Simulation time 946085287 ps
CPU time 2 seconds
Started Jul 03 05:35:22 PM PDT 24
Finished Jul 03 05:35:24 PM PDT 24
Peak memory 200796 kb
Host smart-8ddf4bc9-604b-4709-a738-8730d38b7e09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097469398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3097469398
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.53618585
Short name T78
Test name
Test status
Simulation time 53668300 ps
CPU time 0.97 seconds
Started Jul 03 05:35:25 PM PDT 24
Finished Jul 03 05:35:26 PM PDT 24
Peak memory 199824 kb
Host smart-0600183e-8915-4eb8-8b5d-17021aa8ff09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53618585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.53618585
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3421212771
Short name T1157
Test name
Test status
Simulation time 87511424 ps
CPU time 1.18 seconds
Started Jul 03 05:35:32 PM PDT 24
Finished Jul 03 05:35:34 PM PDT 24
Peak memory 200772 kb
Host smart-a9c186b9-fcca-48c3-b3e9-656e4524d245
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421212771 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3421212771
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.292876901
Short name T1204
Test name
Test status
Simulation time 56393512 ps
CPU time 0.6 seconds
Started Jul 03 05:35:24 PM PDT 24
Finished Jul 03 05:35:25 PM PDT 24
Peak memory 196356 kb
Host smart-9efdc9e7-7938-427d-beae-18cf2f760a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292876901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.292876901
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1730567435
Short name T1193
Test name
Test status
Simulation time 27340645 ps
CPU time 0.56 seconds
Started Jul 03 05:35:26 PM PDT 24
Finished Jul 03 05:35:27 PM PDT 24
Peak memory 195080 kb
Host smart-dfb9e260-bd00-4bf7-9c22-ccf98dd56aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730567435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1730567435
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3444912299
Short name T1150
Test name
Test status
Simulation time 18254399 ps
CPU time 0.69 seconds
Started Jul 03 05:35:24 PM PDT 24
Finished Jul 03 05:35:25 PM PDT 24
Peak memory 196628 kb
Host smart-979e5ee6-8945-4041-be6f-075b2f4d782e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444912299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3444912299
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1383927342
Short name T1100
Test name
Test status
Simulation time 217664336 ps
CPU time 1.3 seconds
Started Jul 03 05:35:25 PM PDT 24
Finished Jul 03 05:35:27 PM PDT 24
Peak memory 200828 kb
Host smart-0117be31-7588-4872-80f1-0202c7a94b24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383927342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1383927342
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.5591241
Short name T96
Test name
Test status
Simulation time 93656592 ps
CPU time 0.96 seconds
Started Jul 03 05:35:25 PM PDT 24
Finished Jul 03 05:35:26 PM PDT 24
Peak memory 199732 kb
Host smart-d9083161-f5f4-49a3-86b5-f5f3062868f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5591241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.5591241
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2120898110
Short name T1143
Test name
Test status
Simulation time 399443899 ps
CPU time 0.89 seconds
Started Jul 03 05:35:29 PM PDT 24
Finished Jul 03 05:35:30 PM PDT 24
Peak memory 200644 kb
Host smart-595e7d0b-e63a-4d9a-b75d-b476875f94da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120898110 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2120898110
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.4200720431
Short name T1175
Test name
Test status
Simulation time 18676512 ps
CPU time 0.61 seconds
Started Jul 03 05:35:29 PM PDT 24
Finished Jul 03 05:35:30 PM PDT 24
Peak memory 196252 kb
Host smart-3e85a223-c234-47dd-ae26-cfdee7070d26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200720431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4200720431
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2513699470
Short name T1187
Test name
Test status
Simulation time 45241638 ps
CPU time 0.57 seconds
Started Jul 03 05:35:28 PM PDT 24
Finished Jul 03 05:35:29 PM PDT 24
Peak memory 195180 kb
Host smart-c47f35df-24c6-4fb3-aba7-f83615e88a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513699470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2513699470
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2367274740
Short name T1166
Test name
Test status
Simulation time 191180585 ps
CPU time 0.71 seconds
Started Jul 03 05:35:28 PM PDT 24
Finished Jul 03 05:35:29 PM PDT 24
Peak memory 197908 kb
Host smart-a66dbd7a-dffd-4fe5-a076-aabe1f5f445d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367274740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2367274740
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.77286295
Short name T1132
Test name
Test status
Simulation time 352864129 ps
CPU time 1.03 seconds
Started Jul 03 05:35:28 PM PDT 24
Finished Jul 03 05:35:30 PM PDT 24
Peak memory 200556 kb
Host smart-547b96ff-8c27-4b1d-8fe6-067137cbafee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77286295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.77286295
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2514160915
Short name T1134
Test name
Test status
Simulation time 79088718 ps
CPU time 1.06 seconds
Started Jul 03 05:35:27 PM PDT 24
Finished Jul 03 05:35:28 PM PDT 24
Peak memory 200636 kb
Host smart-2cb0cc95-f81f-4078-91e0-a34e8a64283e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514160915 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2514160915
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3426013865
Short name T1180
Test name
Test status
Simulation time 16611140 ps
CPU time 0.56 seconds
Started Jul 03 05:35:30 PM PDT 24
Finished Jul 03 05:35:31 PM PDT 24
Peak memory 195096 kb
Host smart-25c86b6b-44ad-445c-ada8-b2e52e7f7c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426013865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3426013865
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3131563533
Short name T67
Test name
Test status
Simulation time 60626628 ps
CPU time 0.79 seconds
Started Jul 03 05:35:32 PM PDT 24
Finished Jul 03 05:35:33 PM PDT 24
Peak memory 197536 kb
Host smart-985eb1c8-d8bb-4278-a2ce-3a5bdc1eaa33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131563533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3131563533
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3176427941
Short name T1215
Test name
Test status
Simulation time 483047138 ps
CPU time 2.41 seconds
Started Jul 03 05:35:30 PM PDT 24
Finished Jul 03 05:35:33 PM PDT 24
Peak memory 200824 kb
Host smart-72900dc7-b724-45f4-b6ef-577836502986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176427941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3176427941
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.848498031
Short name T76
Test name
Test status
Simulation time 180147508 ps
CPU time 0.97 seconds
Started Jul 03 05:35:28 PM PDT 24
Finished Jul 03 05:35:29 PM PDT 24
Peak memory 199708 kb
Host smart-2b5ffea9-3fdf-4279-802e-13970eb09ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848498031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.848498031
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3985810057
Short name T1126
Test name
Test status
Simulation time 29774303 ps
CPU time 0.89 seconds
Started Jul 03 05:35:31 PM PDT 24
Finished Jul 03 05:35:33 PM PDT 24
Peak memory 200568 kb
Host smart-d483a56b-95ba-4151-8415-a9c6dc3dba2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985810057 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3985810057
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3622591626
Short name T1169
Test name
Test status
Simulation time 74034719 ps
CPU time 0.6 seconds
Started Jul 03 05:35:28 PM PDT 24
Finished Jul 03 05:35:29 PM PDT 24
Peak memory 196100 kb
Host smart-09039fb0-79a8-4a12-abf8-03992cddec06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622591626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3622591626
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3450744584
Short name T1107
Test name
Test status
Simulation time 38089615 ps
CPU time 0.56 seconds
Started Jul 03 05:35:29 PM PDT 24
Finished Jul 03 05:35:30 PM PDT 24
Peak memory 195160 kb
Host smart-fa4cadb1-da9b-4244-bdd8-195e1ddff4d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450744584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3450744584
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2888191867
Short name T1170
Test name
Test status
Simulation time 62765183 ps
CPU time 0.66 seconds
Started Jul 03 05:35:30 PM PDT 24
Finished Jul 03 05:35:31 PM PDT 24
Peak memory 196596 kb
Host smart-1f26d285-925d-4acf-a11d-33c9957bb52b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888191867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2888191867
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1886033409
Short name T1141
Test name
Test status
Simulation time 841146125 ps
CPU time 1.77 seconds
Started Jul 03 05:35:29 PM PDT 24
Finished Jul 03 05:35:31 PM PDT 24
Peak memory 200852 kb
Host smart-5af3cccb-d2a5-4f03-a115-ab5ae64d4323
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886033409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1886033409
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3625889151
Short name T1156
Test name
Test status
Simulation time 43759826 ps
CPU time 0.97 seconds
Started Jul 03 05:35:27 PM PDT 24
Finished Jul 03 05:35:28 PM PDT 24
Peak memory 199720 kb
Host smart-8c3a73a5-2970-4e80-850a-49708a79411d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625889151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3625889151
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3525609374
Short name T1182
Test name
Test status
Simulation time 21999872 ps
CPU time 0.73 seconds
Started Jul 03 05:35:35 PM PDT 24
Finished Jul 03 05:35:36 PM PDT 24
Peak memory 199380 kb
Host smart-712db2cd-1105-44e3-9531-02d10b4d88e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525609374 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3525609374
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2058783393
Short name T63
Test name
Test status
Simulation time 33604134 ps
CPU time 0.58 seconds
Started Jul 03 05:35:35 PM PDT 24
Finished Jul 03 05:35:36 PM PDT 24
Peak memory 196152 kb
Host smart-5e53458a-5f1d-44c5-8ddd-7f9c6b1cb715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058783393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2058783393
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1059219905
Short name T1104
Test name
Test status
Simulation time 31371825 ps
CPU time 0.56 seconds
Started Jul 03 05:35:32 PM PDT 24
Finished Jul 03 05:35:33 PM PDT 24
Peak memory 195168 kb
Host smart-42c8cf2e-018d-42b6-bd36-6d92c57a2935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059219905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1059219905
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1494146781
Short name T62
Test name
Test status
Simulation time 15035049 ps
CPU time 0.73 seconds
Started Jul 03 05:35:40 PM PDT 24
Finished Jul 03 05:35:41 PM PDT 24
Peak memory 197748 kb
Host smart-23e2d723-a56f-48a7-8d64-be42e80cba37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494146781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1494146781
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2287793721
Short name T1148
Test name
Test status
Simulation time 34118711 ps
CPU time 1.67 seconds
Started Jul 03 05:35:29 PM PDT 24
Finished Jul 03 05:35:31 PM PDT 24
Peak memory 200852 kb
Host smart-98de360d-6bbd-40d3-9ff9-b61ae7f8cdb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287793721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2287793721
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2695311020
Short name T74
Test name
Test status
Simulation time 606409095 ps
CPU time 1.25 seconds
Started Jul 03 05:35:34 PM PDT 24
Finished Jul 03 05:35:36 PM PDT 24
Peak memory 200096 kb
Host smart-36f0ac27-fd58-46e5-a385-12c5ab4a1b50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695311020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2695311020
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1960408623
Short name T1168
Test name
Test status
Simulation time 31282690 ps
CPU time 0.73 seconds
Started Jul 03 05:35:01 PM PDT 24
Finished Jul 03 05:35:02 PM PDT 24
Peak memory 196948 kb
Host smart-5a50618f-9ab1-4c80-9400-9e9431f936d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960408623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1960408623
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2146814703
Short name T56
Test name
Test status
Simulation time 262307932 ps
CPU time 2.66 seconds
Started Jul 03 05:35:02 PM PDT 24
Finished Jul 03 05:35:05 PM PDT 24
Peak memory 198820 kb
Host smart-58963ced-91b7-404a-934a-c78b426172bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146814703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2146814703
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2438855557
Short name T51
Test name
Test status
Simulation time 21383394 ps
CPU time 0.61 seconds
Started Jul 03 05:35:02 PM PDT 24
Finished Jul 03 05:35:03 PM PDT 24
Peak memory 196156 kb
Host smart-1a80a8cb-d021-4c1a-97cf-f8a055052a6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438855557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2438855557
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.571642124
Short name T1165
Test name
Test status
Simulation time 97740728 ps
CPU time 0.85 seconds
Started Jul 03 05:35:08 PM PDT 24
Finished Jul 03 05:35:09 PM PDT 24
Peak memory 200584 kb
Host smart-3a2d8152-a9c3-4102-ae7c-94323ea74f1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571642124 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.571642124
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1833438235
Short name T1155
Test name
Test status
Simulation time 11190442 ps
CPU time 0.59 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:06 PM PDT 24
Peak memory 196252 kb
Host smart-1e54dd4f-c51b-4900-9821-7d5a1d57ffc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833438235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1833438235
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2150563671
Short name T1147
Test name
Test status
Simulation time 41508587 ps
CPU time 0.59 seconds
Started Jul 03 05:35:01 PM PDT 24
Finished Jul 03 05:35:02 PM PDT 24
Peak memory 195120 kb
Host smart-1e492684-c0f4-4b6c-a816-b627042f1a84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150563671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2150563671
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3779344439
Short name T1201
Test name
Test status
Simulation time 28247530 ps
CPU time 0.77 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:06 PM PDT 24
Peak memory 196752 kb
Host smart-201d38a7-ec9a-4fb6-9992-d4d1578185fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779344439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3779344439
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.492367217
Short name T1208
Test name
Test status
Simulation time 43648277 ps
CPU time 1.17 seconds
Started Jul 03 05:35:06 PM PDT 24
Finished Jul 03 05:35:08 PM PDT 24
Peak memory 200824 kb
Host smart-b49ceaee-c079-4550-b61a-8352b93b5dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492367217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.492367217
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2293221292
Short name T1123
Test name
Test status
Simulation time 46932580 ps
CPU time 0.58 seconds
Started Jul 03 05:35:33 PM PDT 24
Finished Jul 03 05:35:34 PM PDT 24
Peak memory 195152 kb
Host smart-88eab958-576e-412d-bdc6-483a2669ec30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293221292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2293221292
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.144506725
Short name T1145
Test name
Test status
Simulation time 14790600 ps
CPU time 0.58 seconds
Started Jul 03 05:35:34 PM PDT 24
Finished Jul 03 05:35:35 PM PDT 24
Peak memory 195068 kb
Host smart-c3bfd838-b6c2-4677-847e-94cbbf24d82b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144506725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.144506725
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3356253107
Short name T1177
Test name
Test status
Simulation time 25415706 ps
CPU time 0.57 seconds
Started Jul 03 05:35:34 PM PDT 24
Finished Jul 03 05:35:35 PM PDT 24
Peak memory 195160 kb
Host smart-439ba4d4-186c-4189-b574-8479d73ef0c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356253107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3356253107
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3955386814
Short name T1133
Test name
Test status
Simulation time 14369672 ps
CPU time 0.58 seconds
Started Jul 03 05:35:38 PM PDT 24
Finished Jul 03 05:35:39 PM PDT 24
Peak memory 195216 kb
Host smart-77185f84-fab5-49a7-a7a0-be52c01be56b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955386814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3955386814
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2927714286
Short name T1176
Test name
Test status
Simulation time 57840999 ps
CPU time 0.6 seconds
Started Jul 03 05:35:35 PM PDT 24
Finished Jul 03 05:35:36 PM PDT 24
Peak memory 195200 kb
Host smart-12652a53-4c93-4099-aa4c-109b6b60a8f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927714286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2927714286
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.4224429719
Short name T1099
Test name
Test status
Simulation time 20551343 ps
CPU time 0.57 seconds
Started Jul 03 05:35:32 PM PDT 24
Finished Jul 03 05:35:33 PM PDT 24
Peak memory 195152 kb
Host smart-7bbbe764-c5e5-4634-a1db-5ca41c176264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224429719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.4224429719
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.857316073
Short name T1167
Test name
Test status
Simulation time 31825799 ps
CPU time 0.56 seconds
Started Jul 03 05:35:35 PM PDT 24
Finished Jul 03 05:35:35 PM PDT 24
Peak memory 195172 kb
Host smart-dacb8842-9d88-4dad-9852-781cca79ec7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857316073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.857316073
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2835430308
Short name T1111
Test name
Test status
Simulation time 16681628 ps
CPU time 0.57 seconds
Started Jul 03 05:35:32 PM PDT 24
Finished Jul 03 05:35:33 PM PDT 24
Peak memory 195160 kb
Host smart-ba41fb2e-0391-4059-992f-2de9f3be6d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835430308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2835430308
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1710189224
Short name T1127
Test name
Test status
Simulation time 27381691 ps
CPU time 0.6 seconds
Started Jul 03 05:35:32 PM PDT 24
Finished Jul 03 05:35:33 PM PDT 24
Peak memory 195148 kb
Host smart-8b3387bf-4796-4627-9f39-05dfcf226815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710189224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1710189224
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2640913626
Short name T1142
Test name
Test status
Simulation time 51104995 ps
CPU time 0.59 seconds
Started Jul 03 05:35:34 PM PDT 24
Finished Jul 03 05:35:35 PM PDT 24
Peak memory 195168 kb
Host smart-b710d1b4-aeb6-4941-9cd3-e71f0ce72ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640913626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2640913626
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1152977832
Short name T57
Test name
Test status
Simulation time 23992681 ps
CPU time 0.77 seconds
Started Jul 03 05:35:10 PM PDT 24
Finished Jul 03 05:35:11 PM PDT 24
Peak memory 196912 kb
Host smart-8ff76f16-2793-449c-91e2-b9112c723277
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152977832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1152977832
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1004675865
Short name T54
Test name
Test status
Simulation time 84687121 ps
CPU time 2.24 seconds
Started Jul 03 05:35:04 PM PDT 24
Finished Jul 03 05:35:07 PM PDT 24
Peak memory 198728 kb
Host smart-9784f1bb-83a8-42c2-afd9-af95e6df0469
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004675865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1004675865
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.865321149
Short name T1158
Test name
Test status
Simulation time 15574293 ps
CPU time 0.58 seconds
Started Jul 03 05:35:09 PM PDT 24
Finished Jul 03 05:35:10 PM PDT 24
Peak memory 195176 kb
Host smart-baec0c26-cabe-4042-9cbf-1d159e98bc51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865321149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.865321149
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1768079484
Short name T1097
Test name
Test status
Simulation time 30898658 ps
CPU time 0.86 seconds
Started Jul 03 05:35:07 PM PDT 24
Finished Jul 03 05:35:08 PM PDT 24
Peak memory 200592 kb
Host smart-1576050d-e663-4e4d-8a13-101131b94149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768079484 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1768079484
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2482446961
Short name T59
Test name
Test status
Simulation time 37560023 ps
CPU time 0.54 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:06 PM PDT 24
Peak memory 196204 kb
Host smart-8fcddf8c-72e3-4bbe-a1d8-1907423f632a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482446961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2482446961
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2316950118
Short name T1154
Test name
Test status
Simulation time 19745246 ps
CPU time 0.55 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:06 PM PDT 24
Peak memory 195184 kb
Host smart-93189ecd-06ff-4936-8904-93191459eaa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316950118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2316950118
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3371432507
Short name T1181
Test name
Test status
Simulation time 52641470 ps
CPU time 0.62 seconds
Started Jul 03 05:35:04 PM PDT 24
Finished Jul 03 05:35:05 PM PDT 24
Peak memory 196228 kb
Host smart-d4cf7f13-5e1f-4434-93bb-952260d73dcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371432507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3371432507
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1734233375
Short name T1105
Test name
Test status
Simulation time 184288541 ps
CPU time 1.1 seconds
Started Jul 03 05:35:08 PM PDT 24
Finished Jul 03 05:35:09 PM PDT 24
Peak memory 200552 kb
Host smart-e85faebc-83a5-47dd-aa81-7a49ea3ba2f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734233375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1734233375
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1340940964
Short name T1197
Test name
Test status
Simulation time 75915371 ps
CPU time 0.87 seconds
Started Jul 03 05:35:09 PM PDT 24
Finished Jul 03 05:35:11 PM PDT 24
Peak memory 199520 kb
Host smart-22a96bca-817e-46bd-a927-2e467658aaaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340940964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1340940964
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1199064511
Short name T1194
Test name
Test status
Simulation time 19541155 ps
CPU time 0.55 seconds
Started Jul 03 05:35:33 PM PDT 24
Finished Jul 03 05:35:33 PM PDT 24
Peak memory 195084 kb
Host smart-ac639313-21f2-476f-a9ed-103c5e6cc932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199064511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1199064511
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1700059380
Short name T1160
Test name
Test status
Simulation time 43153860 ps
CPU time 0.59 seconds
Started Jul 03 05:35:34 PM PDT 24
Finished Jul 03 05:35:35 PM PDT 24
Peak memory 195144 kb
Host smart-35f295ba-41d5-4563-8676-581e5ef19972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700059380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1700059380
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.295708566
Short name T1163
Test name
Test status
Simulation time 11243464 ps
CPU time 0.57 seconds
Started Jul 03 05:35:31 PM PDT 24
Finished Jul 03 05:35:32 PM PDT 24
Peak memory 195172 kb
Host smart-53f849d4-e501-4d8c-9b00-cdc581bf846f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295708566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.295708566
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1979112749
Short name T1117
Test name
Test status
Simulation time 44807961 ps
CPU time 0.65 seconds
Started Jul 03 05:35:33 PM PDT 24
Finished Jul 03 05:35:34 PM PDT 24
Peak memory 195148 kb
Host smart-011de72e-8f1a-4903-986c-49c1b3ffbfb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979112749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1979112749
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3113721735
Short name T1164
Test name
Test status
Simulation time 12817453 ps
CPU time 0.58 seconds
Started Jul 03 05:35:32 PM PDT 24
Finished Jul 03 05:35:33 PM PDT 24
Peak memory 195144 kb
Host smart-bbb3e114-5b56-4b19-b538-3437014bd853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113721735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3113721735
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.305813291
Short name T1124
Test name
Test status
Simulation time 37535992 ps
CPU time 0.55 seconds
Started Jul 03 05:35:35 PM PDT 24
Finished Jul 03 05:35:36 PM PDT 24
Peak memory 195136 kb
Host smart-71feef5a-0157-4b39-8dd6-b45f28bb7a4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305813291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.305813291
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3453403454
Short name T1135
Test name
Test status
Simulation time 80151778 ps
CPU time 0.59 seconds
Started Jul 03 05:35:38 PM PDT 24
Finished Jul 03 05:35:39 PM PDT 24
Peak memory 195116 kb
Host smart-d18d2f58-4209-4ebd-a1d2-7fa89df9b0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453403454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3453403454
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1413674199
Short name T1116
Test name
Test status
Simulation time 11279719 ps
CPU time 0.56 seconds
Started Jul 03 05:35:39 PM PDT 24
Finished Jul 03 05:35:40 PM PDT 24
Peak memory 195064 kb
Host smart-e327f18f-6652-424b-89d5-e518820d8793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413674199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1413674199
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.4001030423
Short name T1184
Test name
Test status
Simulation time 41753279 ps
CPU time 0.6 seconds
Started Jul 03 05:35:38 PM PDT 24
Finished Jul 03 05:35:39 PM PDT 24
Peak memory 195148 kb
Host smart-7e7fb032-34ad-4a01-ac55-29807fc79080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001030423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.4001030423
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3340913196
Short name T1179
Test name
Test status
Simulation time 16230654 ps
CPU time 0.58 seconds
Started Jul 03 05:35:39 PM PDT 24
Finished Jul 03 05:35:40 PM PDT 24
Peak memory 195092 kb
Host smart-32640396-cab1-4833-9264-b980c899de2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340913196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3340913196
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1224002112
Short name T1199
Test name
Test status
Simulation time 37666922 ps
CPU time 0.66 seconds
Started Jul 03 05:35:08 PM PDT 24
Finished Jul 03 05:35:09 PM PDT 24
Peak memory 196132 kb
Host smart-12863060-c134-4d7e-ad55-c30d0c84f302
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224002112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1224002112
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1655034582
Short name T1119
Test name
Test status
Simulation time 91929429 ps
CPU time 1.52 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:07 PM PDT 24
Peak memory 198508 kb
Host smart-a7c71594-60b5-4ced-a89f-2ac2b4e752bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655034582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1655034582
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.30664317
Short name T1110
Test name
Test status
Simulation time 34544043 ps
CPU time 0.58 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:06 PM PDT 24
Peak memory 196200 kb
Host smart-898b1dcb-7b7f-4e2b-b3d4-500cbd36f769
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30664317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.30664317
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2308878645
Short name T1207
Test name
Test status
Simulation time 27184265 ps
CPU time 1.42 seconds
Started Jul 03 05:35:07 PM PDT 24
Finished Jul 03 05:35:09 PM PDT 24
Peak memory 200804 kb
Host smart-a2c4d269-4b72-41e8-9d56-2a25835e0ec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308878645 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2308878645
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2088470492
Short name T55
Test name
Test status
Simulation time 60396127 ps
CPU time 0.63 seconds
Started Jul 03 05:35:04 PM PDT 24
Finished Jul 03 05:35:05 PM PDT 24
Peak memory 196344 kb
Host smart-c58140c4-7f42-443d-8d0c-880ee48b30c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088470492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2088470492
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1190741431
Short name T1216
Test name
Test status
Simulation time 33209914 ps
CPU time 0.57 seconds
Started Jul 03 05:35:08 PM PDT 24
Finished Jul 03 05:35:09 PM PDT 24
Peak memory 195228 kb
Host smart-2388577b-a187-46fa-902c-68a3a0d10875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190741431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1190741431
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2827455380
Short name T1222
Test name
Test status
Simulation time 23437764 ps
CPU time 0.63 seconds
Started Jul 03 05:35:06 PM PDT 24
Finished Jul 03 05:35:07 PM PDT 24
Peak memory 196420 kb
Host smart-e9f221b6-50bd-48e5-8002-554270af3d28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827455380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2827455380
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.189134635
Short name T1101
Test name
Test status
Simulation time 76464535 ps
CPU time 1.72 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:07 PM PDT 24
Peak memory 200852 kb
Host smart-36faafb4-e938-4f89-a511-85b1213b2a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189134635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.189134635
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3855505031
Short name T79
Test name
Test status
Simulation time 747732587 ps
CPU time 1.04 seconds
Started Jul 03 05:35:08 PM PDT 24
Finished Jul 03 05:35:09 PM PDT 24
Peak memory 199876 kb
Host smart-852d3b91-0b7b-4fb0-bc29-0cb4184c2bff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855505031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3855505031
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3756014550
Short name T1140
Test name
Test status
Simulation time 16899682 ps
CPU time 0.58 seconds
Started Jul 03 05:35:40 PM PDT 24
Finished Jul 03 05:35:41 PM PDT 24
Peak memory 195144 kb
Host smart-9dfa21b3-71ab-4c0c-b5dc-4b4d2881b525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756014550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3756014550
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2599729039
Short name T1183
Test name
Test status
Simulation time 15683290 ps
CPU time 0.57 seconds
Started Jul 03 05:35:41 PM PDT 24
Finished Jul 03 05:35:42 PM PDT 24
Peak memory 195184 kb
Host smart-555bc445-e683-4147-b504-9da5418ca925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599729039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2599729039
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2062854886
Short name T1214
Test name
Test status
Simulation time 43322705 ps
CPU time 0.6 seconds
Started Jul 03 05:35:37 PM PDT 24
Finished Jul 03 05:35:38 PM PDT 24
Peak memory 195112 kb
Host smart-1466fb29-ba23-4e3d-8d76-65c616c05fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062854886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2062854886
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2556830341
Short name T1112
Test name
Test status
Simulation time 54290995 ps
CPU time 0.57 seconds
Started Jul 03 05:35:37 PM PDT 24
Finished Jul 03 05:35:38 PM PDT 24
Peak memory 195044 kb
Host smart-7bbaa2d8-aa24-429d-a0a2-f1611de65eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556830341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2556830341
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3935840029
Short name T1125
Test name
Test status
Simulation time 26111352 ps
CPU time 0.55 seconds
Started Jul 03 05:35:39 PM PDT 24
Finished Jul 03 05:35:40 PM PDT 24
Peak memory 195152 kb
Host smart-9675a70c-ef46-4c62-aa94-480a23a9a3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935840029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3935840029
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2075645587
Short name T1186
Test name
Test status
Simulation time 14381107 ps
CPU time 0.61 seconds
Started Jul 03 05:35:37 PM PDT 24
Finished Jul 03 05:35:38 PM PDT 24
Peak memory 195124 kb
Host smart-1aec9119-1d7e-499a-877a-c2e16f7d76e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075645587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2075645587
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.553882734
Short name T1121
Test name
Test status
Simulation time 31680150 ps
CPU time 0.56 seconds
Started Jul 03 05:35:38 PM PDT 24
Finished Jul 03 05:35:39 PM PDT 24
Peak memory 195152 kb
Host smart-5f65915b-9ed4-4271-a4a2-b84a1cbc86ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553882734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.553882734
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1908381602
Short name T1203
Test name
Test status
Simulation time 68395729 ps
CPU time 0.58 seconds
Started Jul 03 05:35:39 PM PDT 24
Finished Jul 03 05:35:40 PM PDT 24
Peak memory 195188 kb
Host smart-a3dd6a6e-cb9a-4ba9-927f-689730c7dfa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908381602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1908381602
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.416645038
Short name T1173
Test name
Test status
Simulation time 34154037 ps
CPU time 0.6 seconds
Started Jul 03 05:35:38 PM PDT 24
Finished Jul 03 05:35:39 PM PDT 24
Peak memory 195196 kb
Host smart-5d0e8cf4-9d4f-499f-91ef-493abdfa4a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416645038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.416645038
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2221813821
Short name T1103
Test name
Test status
Simulation time 11595079 ps
CPU time 0.58 seconds
Started Jul 03 05:35:37 PM PDT 24
Finished Jul 03 05:35:38 PM PDT 24
Peak memory 195152 kb
Host smart-02ec1be1-0767-4003-a4d8-c0085c1cded3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221813821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2221813821
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1798247961
Short name T1136
Test name
Test status
Simulation time 36245817 ps
CPU time 0.7 seconds
Started Jul 03 05:35:09 PM PDT 24
Finished Jul 03 05:35:10 PM PDT 24
Peak memory 199388 kb
Host smart-2896b7ee-b60d-477d-b192-fbd38bad0685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798247961 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1798247961
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.4125357587
Short name T1223
Test name
Test status
Simulation time 15679415 ps
CPU time 0.63 seconds
Started Jul 03 05:35:10 PM PDT 24
Finished Jul 03 05:35:11 PM PDT 24
Peak memory 196604 kb
Host smart-d18e74cb-d35f-467b-ac43-3275f73cad82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125357587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.4125357587
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1091576594
Short name T1159
Test name
Test status
Simulation time 22077115 ps
CPU time 0.55 seconds
Started Jul 03 05:35:05 PM PDT 24
Finished Jul 03 05:35:07 PM PDT 24
Peak memory 195044 kb
Host smart-9bf29ea7-2b7b-4dd2-8cb0-4fca7537ec29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091576594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1091576594
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2582465115
Short name T1185
Test name
Test status
Simulation time 63145620 ps
CPU time 0.68 seconds
Started Jul 03 05:35:08 PM PDT 24
Finished Jul 03 05:35:09 PM PDT 24
Peak memory 197440 kb
Host smart-e962ef2c-2d59-4578-a561-46de5b39ae50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582465115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2582465115
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3101844536
Short name T1137
Test name
Test status
Simulation time 121907840 ps
CPU time 1.36 seconds
Started Jul 03 05:35:09 PM PDT 24
Finished Jul 03 05:35:11 PM PDT 24
Peak memory 199872 kb
Host smart-0480a064-4e91-4c00-a990-a8a5716c8028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101844536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3101844536
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1504229476
Short name T1221
Test name
Test status
Simulation time 42770977 ps
CPU time 0.95 seconds
Started Jul 03 05:35:07 PM PDT 24
Finished Jul 03 05:35:08 PM PDT 24
Peak memory 199820 kb
Host smart-6944bc8a-ebc6-467c-8f06-1b7cf2160c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504229476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1504229476
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2468591301
Short name T1098
Test name
Test status
Simulation time 93014436 ps
CPU time 0.88 seconds
Started Jul 03 05:35:13 PM PDT 24
Finished Jul 03 05:35:14 PM PDT 24
Peak memory 200588 kb
Host smart-a3b56321-6cfc-4109-96ba-e3974d1b4640
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468591301 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2468591301
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.367013001
Short name T68
Test name
Test status
Simulation time 38800904 ps
CPU time 0.56 seconds
Started Jul 03 05:35:09 PM PDT 24
Finished Jul 03 05:35:10 PM PDT 24
Peak memory 196160 kb
Host smart-1d6f3ab5-a2a4-41ff-894c-ed31b1156a94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367013001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.367013001
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2644433402
Short name T1161
Test name
Test status
Simulation time 20598534 ps
CPU time 0.58 seconds
Started Jul 03 05:35:10 PM PDT 24
Finished Jul 03 05:35:11 PM PDT 24
Peak memory 195108 kb
Host smart-de775e89-f419-4246-986a-8821f46f8c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644433402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2644433402
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.530542549
Short name T1191
Test name
Test status
Simulation time 168923688 ps
CPU time 0.72 seconds
Started Jul 03 05:35:11 PM PDT 24
Finished Jul 03 05:35:12 PM PDT 24
Peak memory 197544 kb
Host smart-27b7da5d-2220-43fc-ba31-11d0f1cd954e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530542549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.530542549
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.412720852
Short name T1130
Test name
Test status
Simulation time 213208627 ps
CPU time 2.08 seconds
Started Jul 03 05:35:12 PM PDT 24
Finished Jul 03 05:35:15 PM PDT 24
Peak memory 200752 kb
Host smart-f5da1c16-bb54-4c9f-9d8b-7c4faabe1cae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412720852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.412720852
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2667545399
Short name T1218
Test name
Test status
Simulation time 94312787 ps
CPU time 1.42 seconds
Started Jul 03 05:35:09 PM PDT 24
Finished Jul 03 05:35:11 PM PDT 24
Peak memory 200124 kb
Host smart-741dbc61-b463-40ca-a452-9dffe6cb6224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667545399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2667545399
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3689577047
Short name T1139
Test name
Test status
Simulation time 28281770 ps
CPU time 0.77 seconds
Started Jul 03 05:35:16 PM PDT 24
Finished Jul 03 05:35:17 PM PDT 24
Peak memory 200536 kb
Host smart-bc538850-d5af-449b-bc8d-1ff126f83857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689577047 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3689577047
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1486772667
Short name T1171
Test name
Test status
Simulation time 87141932 ps
CPU time 0.59 seconds
Started Jul 03 05:35:13 PM PDT 24
Finished Jul 03 05:35:14 PM PDT 24
Peak memory 196172 kb
Host smart-03468031-ef28-44f7-95e5-1a26fb515f00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486772667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1486772667
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.374463190
Short name T1226
Test name
Test status
Simulation time 54748847 ps
CPU time 0.6 seconds
Started Jul 03 05:35:11 PM PDT 24
Finished Jul 03 05:35:12 PM PDT 24
Peak memory 195172 kb
Host smart-c63d96e9-d560-4e49-bde1-f3426e38fa87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374463190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.374463190
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.4197341110
Short name T66
Test name
Test status
Simulation time 62735852 ps
CPU time 0.75 seconds
Started Jul 03 05:35:15 PM PDT 24
Finished Jul 03 05:35:16 PM PDT 24
Peak memory 197860 kb
Host smart-56d31c88-e529-463a-ac0b-16eaeba67767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197341110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.4197341110
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2476176731
Short name T1206
Test name
Test status
Simulation time 103397938 ps
CPU time 1.9 seconds
Started Jul 03 05:35:13 PM PDT 24
Finished Jul 03 05:35:16 PM PDT 24
Peak memory 200764 kb
Host smart-ca8ad941-4f3c-4647-9e81-7654d9d04f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476176731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2476176731
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3256697186
Short name T99
Test name
Test status
Simulation time 202867189 ps
CPU time 0.93 seconds
Started Jul 03 05:35:12 PM PDT 24
Finished Jul 03 05:35:13 PM PDT 24
Peak memory 199604 kb
Host smart-f373b3c7-1265-4dcb-b009-bac429e88f14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256697186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3256697186
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1942646685
Short name T1108
Test name
Test status
Simulation time 27073936 ps
CPU time 1.24 seconds
Started Jul 03 05:35:16 PM PDT 24
Finished Jul 03 05:35:18 PM PDT 24
Peak memory 200772 kb
Host smart-61ddf529-b9d9-41b6-8d46-adfa86a45a80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942646685 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1942646685
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.271280722
Short name T70
Test name
Test status
Simulation time 10960429 ps
CPU time 0.6 seconds
Started Jul 03 05:35:16 PM PDT 24
Finished Jul 03 05:35:17 PM PDT 24
Peak memory 196088 kb
Host smart-755d9aa0-7dca-4059-8b41-ef2842f2a4bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271280722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.271280722
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1276802974
Short name T1128
Test name
Test status
Simulation time 14970508 ps
CPU time 0.57 seconds
Started Jul 03 05:35:13 PM PDT 24
Finished Jul 03 05:35:14 PM PDT 24
Peak memory 195116 kb
Host smart-ecbac70c-89b9-46be-8d40-b875ed821df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276802974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1276802974
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2221097653
Short name T1152
Test name
Test status
Simulation time 23201125 ps
CPU time 0.72 seconds
Started Jul 03 05:35:12 PM PDT 24
Finished Jul 03 05:35:13 PM PDT 24
Peak memory 197820 kb
Host smart-de09ab1f-88c5-4921-a80a-e67c17127633
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221097653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2221097653
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2136321760
Short name T1109
Test name
Test status
Simulation time 66794274 ps
CPU time 1.05 seconds
Started Jul 03 05:35:13 PM PDT 24
Finished Jul 03 05:35:14 PM PDT 24
Peak memory 200528 kb
Host smart-5f930704-b95a-445b-854e-db2cfe49b910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136321760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2136321760
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2298826326
Short name T1212
Test name
Test status
Simulation time 259555069 ps
CPU time 0.94 seconds
Started Jul 03 05:35:13 PM PDT 24
Finished Jul 03 05:35:14 PM PDT 24
Peak memory 199684 kb
Host smart-aede517e-18bb-45f1-a65a-e14f66f5ee3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298826326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2298826326
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1218797010
Short name T1095
Test name
Test status
Simulation time 80309006 ps
CPU time 0.76 seconds
Started Jul 03 05:35:17 PM PDT 24
Finished Jul 03 05:35:18 PM PDT 24
Peak memory 199220 kb
Host smart-dbeddb01-0f2a-442b-ba84-a029a5c3e46f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218797010 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1218797010
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3578283069
Short name T1144
Test name
Test status
Simulation time 43489096 ps
CPU time 0.6 seconds
Started Jul 03 05:35:19 PM PDT 24
Finished Jul 03 05:35:20 PM PDT 24
Peak memory 195904 kb
Host smart-5c3fd549-5511-4417-8faa-6733854b7ff0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578283069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3578283069
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2996508119
Short name T1149
Test name
Test status
Simulation time 17413068 ps
CPU time 0.58 seconds
Started Jul 03 05:35:16 PM PDT 24
Finished Jul 03 05:35:17 PM PDT 24
Peak memory 195164 kb
Host smart-c5dcd083-2255-42e4-8ef8-b61c69d62ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996508119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2996508119
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3291097907
Short name T1205
Test name
Test status
Simulation time 18942762 ps
CPU time 0.8 seconds
Started Jul 03 05:35:17 PM PDT 24
Finished Jul 03 05:35:19 PM PDT 24
Peak memory 197832 kb
Host smart-13ee4d99-a30b-4938-bb17-c64694e350fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291097907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3291097907
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.817577849
Short name T1129
Test name
Test status
Simulation time 26141354 ps
CPU time 1.24 seconds
Started Jul 03 05:35:17 PM PDT 24
Finished Jul 03 05:35:18 PM PDT 24
Peak memory 200860 kb
Host smart-956b80a9-3c6c-4474-a157-a7cebb354859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817577849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.817577849
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.600622159
Short name T98
Test name
Test status
Simulation time 47597657 ps
CPU time 0.98 seconds
Started Jul 03 05:35:18 PM PDT 24
Finished Jul 03 05:35:19 PM PDT 24
Peak memory 199560 kb
Host smart-811aaa56-cf47-4460-a21a-c5465e5ccdb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600622159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.600622159
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1540144446
Short name T502
Test name
Test status
Simulation time 43944657 ps
CPU time 0.58 seconds
Started Jul 03 05:42:56 PM PDT 24
Finished Jul 03 05:42:57 PM PDT 24
Peak memory 195312 kb
Host smart-5dcef672-9d90-4bc0-8a0d-4549daaf1890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540144446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1540144446
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.413217998
Short name T722
Test name
Test status
Simulation time 114077467742 ps
CPU time 13.72 seconds
Started Jul 03 05:42:53 PM PDT 24
Finished Jul 03 05:43:07 PM PDT 24
Peak memory 199712 kb
Host smart-cdf6b0a2-18b2-480b-b5a0-d60e3125e6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413217998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.413217998
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.737486520
Short name T118
Test name
Test status
Simulation time 31367415806 ps
CPU time 37.22 seconds
Started Jul 03 05:42:45 PM PDT 24
Finished Jul 03 05:43:23 PM PDT 24
Peak memory 199880 kb
Host smart-eb87a05d-a7e9-4380-93cd-6aef21f2b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737486520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.737486520
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.3105702085
Short name T533
Test name
Test status
Simulation time 64130522327 ps
CPU time 92.38 seconds
Started Jul 03 05:43:01 PM PDT 24
Finished Jul 03 05:44:33 PM PDT 24
Peak memory 199900 kb
Host smart-0d7d584e-d5f3-4211-8db1-4fdebc70e017
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105702085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3105702085
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1573099746
Short name T417
Test name
Test status
Simulation time 127366548547 ps
CPU time 519.38 seconds
Started Jul 03 05:42:41 PM PDT 24
Finished Jul 03 05:51:22 PM PDT 24
Peak memory 199940 kb
Host smart-7de22c4d-5020-4d38-bf0b-ad1c26d6eb15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573099746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1573099746
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.339287007
Short name T604
Test name
Test status
Simulation time 2539712085 ps
CPU time 5.11 seconds
Started Jul 03 05:42:47 PM PDT 24
Finished Jul 03 05:42:52 PM PDT 24
Peak memory 196384 kb
Host smart-e559936d-52f3-40d4-bb33-7bd31c2b4e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339287007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.339287007
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.3513010158
Short name T729
Test name
Test status
Simulation time 13426562001 ps
CPU time 719.43 seconds
Started Jul 03 05:42:52 PM PDT 24
Finished Jul 03 05:54:52 PM PDT 24
Peak memory 200000 kb
Host smart-5a001903-3479-41ea-b590-99a9af5c66c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513010158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3513010158
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1925969872
Short name T422
Test name
Test status
Simulation time 1385198766 ps
CPU time 2.42 seconds
Started Jul 03 05:42:42 PM PDT 24
Finished Jul 03 05:42:45 PM PDT 24
Peak memory 197844 kb
Host smart-bc400e40-9069-451f-85fe-3707eb663c42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1925969872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1925969872
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.533623192
Short name T281
Test name
Test status
Simulation time 59890474066 ps
CPU time 99.37 seconds
Started Jul 03 05:42:40 PM PDT 24
Finished Jul 03 05:44:22 PM PDT 24
Peak memory 200016 kb
Host smart-4b1de888-e450-4159-ab13-b73450c019fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533623192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.533623192
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.4044526732
Short name T386
Test name
Test status
Simulation time 4444899796 ps
CPU time 7.61 seconds
Started Jul 03 05:42:40 PM PDT 24
Finished Jul 03 05:42:50 PM PDT 24
Peak memory 196012 kb
Host smart-4dfbaec9-a46b-4fc3-ab05-182c74ab731f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044526732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4044526732
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1142041982
Short name T82
Test name
Test status
Simulation time 109070310 ps
CPU time 0.83 seconds
Started Jul 03 05:42:48 PM PDT 24
Finished Jul 03 05:42:50 PM PDT 24
Peak memory 218308 kb
Host smart-a8ba037b-bf23-45b3-9123-b53a37e83308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142041982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1142041982
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2444542704
Short name T865
Test name
Test status
Simulation time 577577501 ps
CPU time 1.96 seconds
Started Jul 03 05:42:39 PM PDT 24
Finished Jul 03 05:42:44 PM PDT 24
Peak memory 199448 kb
Host smart-2b286606-6d7a-4ac1-97ac-f524d2fa13c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444542704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2444542704
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1553700307
Short name T312
Test name
Test status
Simulation time 42612802357 ps
CPU time 326.39 seconds
Started Jul 03 05:42:40 PM PDT 24
Finished Jul 03 05:48:07 PM PDT 24
Peak memory 216520 kb
Host smart-6b9692dc-a35e-4982-b71b-f65df303af89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553700307 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1553700307
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2557407914
Short name T639
Test name
Test status
Simulation time 1646000897 ps
CPU time 2.61 seconds
Started Jul 03 05:42:56 PM PDT 24
Finished Jul 03 05:42:59 PM PDT 24
Peak memory 198232 kb
Host smart-95a2893b-4091-4837-8527-44d9ff65eb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557407914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2557407914
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2031651156
Short name T848
Test name
Test status
Simulation time 36088228279 ps
CPU time 15.14 seconds
Started Jul 03 05:42:42 PM PDT 24
Finished Jul 03 05:42:58 PM PDT 24
Peak memory 199964 kb
Host smart-0cac6411-cf24-451c-b1bf-c8cfc923788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031651156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2031651156
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4283276787
Short name T610
Test name
Test status
Simulation time 47615397314 ps
CPU time 25.92 seconds
Started Jul 03 05:42:41 PM PDT 24
Finished Jul 03 05:43:08 PM PDT 24
Peak memory 199996 kb
Host smart-9d130552-da6d-491f-84db-ddf005c40188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283276787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4283276787
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.605511353
Short name T1004
Test name
Test status
Simulation time 25262529002 ps
CPU time 30.57 seconds
Started Jul 03 05:42:42 PM PDT 24
Finished Jul 03 05:43:14 PM PDT 24
Peak memory 199848 kb
Host smart-0650e9d6-2ee5-416a-aff4-edae538d1107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605511353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.605511353
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.4211091155
Short name T104
Test name
Test status
Simulation time 25255269865 ps
CPU time 38.27 seconds
Started Jul 03 05:43:06 PM PDT 24
Finished Jul 03 05:43:45 PM PDT 24
Peak memory 199968 kb
Host smart-e15e5c23-10ec-49c2-99f6-b140e560bb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211091155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.4211091155
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1469160218
Short name T597
Test name
Test status
Simulation time 433469154960 ps
CPU time 622.47 seconds
Started Jul 03 05:42:41 PM PDT 24
Finished Jul 03 05:53:04 PM PDT 24
Peak memory 199912 kb
Host smart-f8b4d357-a186-442f-9081-fb31a7c43ed3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469160218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1469160218
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3971355822
Short name T700
Test name
Test status
Simulation time 58837534532 ps
CPU time 442.62 seconds
Started Jul 03 05:42:42 PM PDT 24
Finished Jul 03 05:50:06 PM PDT 24
Peak memory 199876 kb
Host smart-df69a8a7-7e74-4aec-952c-bab42cf0701a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971355822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3971355822
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1136986490
Short name T605
Test name
Test status
Simulation time 4950290520 ps
CPU time 25.28 seconds
Started Jul 03 05:43:06 PM PDT 24
Finished Jul 03 05:43:31 PM PDT 24
Peak memory 199644 kb
Host smart-2541874b-8ade-4880-b128-b33d3bf7d1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136986490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1136986490
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.192694920
Short name T802
Test name
Test status
Simulation time 6428335672 ps
CPU time 88.29 seconds
Started Jul 03 05:42:49 PM PDT 24
Finished Jul 03 05:44:18 PM PDT 24
Peak memory 199912 kb
Host smart-1947fcae-7e22-4d73-8535-e191f12d5ff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192694920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.192694920
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.137009347
Short name T428
Test name
Test status
Simulation time 4960491630 ps
CPU time 41.09 seconds
Started Jul 03 05:42:40 PM PDT 24
Finished Jul 03 05:43:22 PM PDT 24
Peak memory 199328 kb
Host smart-10a5efc9-4181-4857-94b9-6c21c4fa0540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137009347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.137009347
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3208074016
Short name T827
Test name
Test status
Simulation time 17445204033 ps
CPU time 15.12 seconds
Started Jul 03 05:42:39 PM PDT 24
Finished Jul 03 05:42:55 PM PDT 24
Peak memory 199760 kb
Host smart-8154b438-4190-40e5-bd48-26d3fd52b1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208074016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3208074016
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3275749548
Short name T864
Test name
Test status
Simulation time 2807558349 ps
CPU time 1.28 seconds
Started Jul 03 05:42:41 PM PDT 24
Finished Jul 03 05:42:43 PM PDT 24
Peak memory 195972 kb
Host smart-db6ce115-09c5-43b9-b3eb-1b287802f337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275749548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3275749548
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2000647297
Short name T81
Test name
Test status
Simulation time 359590214 ps
CPU time 0.87 seconds
Started Jul 03 05:43:02 PM PDT 24
Finished Jul 03 05:43:04 PM PDT 24
Peak memory 218480 kb
Host smart-23208b0b-a061-4e18-b3a0-8bf10f0561d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000647297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2000647297
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2008568226
Short name T366
Test name
Test status
Simulation time 6071553896 ps
CPU time 7.58 seconds
Started Jul 03 05:42:49 PM PDT 24
Finished Jul 03 05:42:57 PM PDT 24
Peak memory 199752 kb
Host smart-bba97e24-df49-45ba-9521-3e5e3cc91512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008568226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2008568226
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.189229013
Short name T816
Test name
Test status
Simulation time 6997132362 ps
CPU time 14.56 seconds
Started Jul 03 05:42:40 PM PDT 24
Finished Jul 03 05:42:56 PM PDT 24
Peak memory 199904 kb
Host smart-b7932954-9a8d-4dfd-92de-1a270935a3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189229013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.189229013
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3873664508
Short name T929
Test name
Test status
Simulation time 37509139788 ps
CPU time 31.31 seconds
Started Jul 03 05:43:06 PM PDT 24
Finished Jul 03 05:43:37 PM PDT 24
Peak memory 199996 kb
Host smart-292245c3-e70e-4fc2-98db-35a407a85523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873664508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3873664508
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1238370137
Short name T589
Test name
Test status
Simulation time 14117966 ps
CPU time 0.59 seconds
Started Jul 03 05:43:11 PM PDT 24
Finished Jul 03 05:43:12 PM PDT 24
Peak memory 195476 kb
Host smart-218bc4c8-0b2f-4540-87c4-d0b701a2d0fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238370137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1238370137
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1152225498
Short name T837
Test name
Test status
Simulation time 241875070430 ps
CPU time 302.95 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:48:16 PM PDT 24
Peak memory 199936 kb
Host smart-52f156e5-ec03-46be-9d53-7534a8e11cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152225498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1152225498
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2555830796
Short name T856
Test name
Test status
Simulation time 71093557206 ps
CPU time 109.92 seconds
Started Jul 03 05:43:03 PM PDT 24
Finished Jul 03 05:44:54 PM PDT 24
Peak memory 199880 kb
Host smart-4e26ad3c-0240-4f5a-847c-a3d9b1270183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555830796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2555830796
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.642623073
Short name T1070
Test name
Test status
Simulation time 53902946785 ps
CPU time 76.76 seconds
Started Jul 03 05:43:05 PM PDT 24
Finished Jul 03 05:44:22 PM PDT 24
Peak memory 199832 kb
Host smart-50029d5f-1f50-4ce7-bf36-13758cfda0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642623073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.642623073
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3927063053
Short name T990
Test name
Test status
Simulation time 9104645221 ps
CPU time 14.77 seconds
Started Jul 03 05:43:17 PM PDT 24
Finished Jul 03 05:43:32 PM PDT 24
Peak memory 196772 kb
Host smart-8cc2b084-466b-4d07-a735-43daab019f41
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927063053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3927063053
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.887200374
Short name T531
Test name
Test status
Simulation time 41738409589 ps
CPU time 114.77 seconds
Started Jul 03 05:43:04 PM PDT 24
Finished Jul 03 05:44:59 PM PDT 24
Peak memory 200016 kb
Host smart-42d791ac-ac75-4ece-ac67-941e3cbce87a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887200374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.887200374
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2255606693
Short name T492
Test name
Test status
Simulation time 27820281 ps
CPU time 0.6 seconds
Started Jul 03 05:43:06 PM PDT 24
Finished Jul 03 05:43:07 PM PDT 24
Peak memory 195784 kb
Host smart-620847f1-7467-4719-bef4-0faa946bafae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255606693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2255606693
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.818406055
Short name T607
Test name
Test status
Simulation time 22929510758 ps
CPU time 15.69 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:43:32 PM PDT 24
Peak memory 197436 kb
Host smart-d53f2c51-b5ed-4cbc-bbb1-7432243e0bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818406055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.818406055
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2810544934
Short name T514
Test name
Test status
Simulation time 35682338647 ps
CPU time 2018.24 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 06:17:05 PM PDT 24
Peak memory 199912 kb
Host smart-64628db8-7990-4eff-840b-c3471894bb97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2810544934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2810544934
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.362385693
Short name T17
Test name
Test status
Simulation time 3373452205 ps
CPU time 12.22 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:43:29 PM PDT 24
Peak memory 199048 kb
Host smart-275835f0-1bad-475d-99e6-436083c0490e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362385693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.362385693
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.813630222
Short name T977
Test name
Test status
Simulation time 10061529374 ps
CPU time 14.74 seconds
Started Jul 03 05:43:13 PM PDT 24
Finished Jul 03 05:43:29 PM PDT 24
Peak memory 199968 kb
Host smart-dd2b7184-db30-4bb2-909f-898b648efa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813630222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.813630222
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1254397122
Short name T805
Test name
Test status
Simulation time 57054433668 ps
CPU time 43.91 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:44:00 PM PDT 24
Peak memory 195740 kb
Host smart-c1f329a1-1627-4573-b0e1-15b96e41ac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254397122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1254397122
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.781417497
Short name T278
Test name
Test status
Simulation time 479268511 ps
CPU time 1.27 seconds
Started Jul 03 05:43:13 PM PDT 24
Finished Jul 03 05:43:15 PM PDT 24
Peak memory 198680 kb
Host smart-7d7e042a-5298-4fb3-ba35-907e4218f2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781417497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.781417497
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.936334818
Short name T527
Test name
Test status
Simulation time 2683138197 ps
CPU time 2.08 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:43:19 PM PDT 24
Peak memory 199840 kb
Host smart-866a9c44-00bf-4872-8284-df9b254484cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936334818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.936334818
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1120033140
Short name T198
Test name
Test status
Simulation time 140150369467 ps
CPU time 119.35 seconds
Started Jul 03 05:45:17 PM PDT 24
Finished Jul 03 05:47:17 PM PDT 24
Peak memory 200004 kb
Host smart-56071cea-7a4f-4599-94ec-eb3ba8acd601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120033140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1120033140
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3961003799
Short name T252
Test name
Test status
Simulation time 54942810355 ps
CPU time 21.83 seconds
Started Jul 03 05:45:15 PM PDT 24
Finished Jul 03 05:45:37 PM PDT 24
Peak memory 199912 kb
Host smart-6ea4dfbb-e7db-4725-814c-28f07f804181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961003799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3961003799
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1124147260
Short name T899
Test name
Test status
Simulation time 213208162052 ps
CPU time 337.04 seconds
Started Jul 03 05:45:17 PM PDT 24
Finished Jul 03 05:50:54 PM PDT 24
Peak memory 199988 kb
Host smart-42c1a2f2-496d-4a6a-9236-62058aa2ebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124147260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1124147260
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3821169281
Short name T900
Test name
Test status
Simulation time 66952259817 ps
CPU time 97.88 seconds
Started Jul 03 05:45:18 PM PDT 24
Finished Jul 03 05:46:56 PM PDT 24
Peak memory 199964 kb
Host smart-b457978f-6a7b-4827-bf43-a1ea19f4cf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821169281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3821169281
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3632001153
Short name T215
Test name
Test status
Simulation time 173401584815 ps
CPU time 75.72 seconds
Started Jul 03 05:45:15 PM PDT 24
Finished Jul 03 05:46:31 PM PDT 24
Peak memory 199972 kb
Host smart-e1591696-c596-4d28-9179-fd2981b0b999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632001153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3632001153
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1588454654
Short name T190
Test name
Test status
Simulation time 18588988855 ps
CPU time 45.37 seconds
Started Jul 03 05:45:16 PM PDT 24
Finished Jul 03 05:46:01 PM PDT 24
Peak memory 200004 kb
Host smart-bc251475-35be-49cc-9306-8462db4fb9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588454654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1588454654
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1791587151
Short name T180
Test name
Test status
Simulation time 77603165511 ps
CPU time 113.61 seconds
Started Jul 03 05:45:16 PM PDT 24
Finished Jul 03 05:47:10 PM PDT 24
Peak memory 199960 kb
Host smart-f550c91f-4bd9-4679-bff5-0455e7e4bb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791587151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1791587151
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2644353513
Short name T625
Test name
Test status
Simulation time 29860119820 ps
CPU time 24.4 seconds
Started Jul 03 05:45:22 PM PDT 24
Finished Jul 03 05:45:47 PM PDT 24
Peak memory 199776 kb
Host smart-28e67698-5a37-433b-80ba-57178042587b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644353513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2644353513
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.1243721602
Short name T679
Test name
Test status
Simulation time 27528672 ps
CPU time 0.55 seconds
Started Jul 03 05:43:13 PM PDT 24
Finished Jul 03 05:43:14 PM PDT 24
Peak memory 195296 kb
Host smart-8e362563-b688-4bc5-ab69-88e1df64a57d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243721602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1243721602
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.341295065
Short name T857
Test name
Test status
Simulation time 39963067331 ps
CPU time 66.48 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:44:23 PM PDT 24
Peak memory 199804 kb
Host smart-dd5fb4ee-77fe-4744-a40e-27477ce8e0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341295065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.341295065
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3882327480
Short name T132
Test name
Test status
Simulation time 22697654879 ps
CPU time 9.55 seconds
Started Jul 03 05:43:11 PM PDT 24
Finished Jul 03 05:43:21 PM PDT 24
Peak memory 199748 kb
Host smart-84537be0-437a-4295-961b-fee45da8d373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882327480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3882327480
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2109683338
Short name T793
Test name
Test status
Simulation time 111839605149 ps
CPU time 263.17 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:47:49 PM PDT 24
Peak memory 199176 kb
Host smart-84a5fc7e-1376-4a77-9f13-a665660b581d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109683338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2109683338
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1951956076
Short name T771
Test name
Test status
Simulation time 223290708740 ps
CPU time 141.36 seconds
Started Jul 03 05:43:13 PM PDT 24
Finished Jul 03 05:45:35 PM PDT 24
Peak memory 199976 kb
Host smart-210e853f-cfdf-45dc-97ae-e9eeb37dd496
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951956076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1951956076
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1851644342
Short name T1052
Test name
Test status
Simulation time 81277492726 ps
CPU time 409.12 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:50:05 PM PDT 24
Peak memory 199816 kb
Host smart-d7dca78b-3459-4dc2-914c-3b03970b0e94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851644342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1851644342
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1390051249
Short name T399
Test name
Test status
Simulation time 2610617943 ps
CPU time 4.77 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:43:21 PM PDT 24
Peak memory 199200 kb
Host smart-07eca879-c086-405b-97d1-d923a9a73ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390051249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1390051249
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1904177699
Short name T738
Test name
Test status
Simulation time 91531819943 ps
CPU time 16.18 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:43:33 PM PDT 24
Peak memory 199848 kb
Host smart-cff4d8b8-6aaf-41b0-88fc-af9a23b367be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904177699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1904177699
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.77218864
Short name T613
Test name
Test status
Simulation time 16086945695 ps
CPU time 180.2 seconds
Started Jul 03 05:43:19 PM PDT 24
Finished Jul 03 05:46:20 PM PDT 24
Peak memory 199816 kb
Host smart-4799b5d3-87f7-4ead-beb2-fcc09eb3e3a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77218864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.77218864
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1149892437
Short name T460
Test name
Test status
Simulation time 6704221548 ps
CPU time 12.47 seconds
Started Jul 03 05:43:08 PM PDT 24
Finished Jul 03 05:43:20 PM PDT 24
Peak memory 198776 kb
Host smart-4333c38c-5245-468a-bd7a-77d1c7b69da0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149892437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1149892437
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4029597028
Short name T293
Test name
Test status
Simulation time 2373952656 ps
CPU time 1.64 seconds
Started Jul 03 05:43:32 PM PDT 24
Finished Jul 03 05:43:34 PM PDT 24
Peak memory 195820 kb
Host smart-b8c3c0a2-de95-4a8f-b856-4e68f462f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029597028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4029597028
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1471928453
Short name T327
Test name
Test status
Simulation time 5734607757 ps
CPU time 16.53 seconds
Started Jul 03 05:42:58 PM PDT 24
Finished Jul 03 05:43:15 PM PDT 24
Peak memory 199888 kb
Host smart-744938d1-8a27-47fd-bccd-0a73d3d87460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471928453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1471928453
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.279053690
Short name T15
Test name
Test status
Simulation time 43331310933 ps
CPU time 936.56 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:58:53 PM PDT 24
Peak memory 215632 kb
Host smart-bd6999ff-1b3e-4ad4-a33f-e2ae556db439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279053690 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.279053690
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1453591393
Short name T505
Test name
Test status
Simulation time 824099647 ps
CPU time 1.6 seconds
Started Jul 03 05:43:07 PM PDT 24
Finished Jul 03 05:43:08 PM PDT 24
Peak memory 198424 kb
Host smart-bad03d89-22de-4dca-b73c-2c5d856db4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453591393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1453591393
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3724518893
Short name T272
Test name
Test status
Simulation time 80635528304 ps
CPU time 97.92 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:44:53 PM PDT 24
Peak memory 200020 kb
Host smart-65815ff3-6a1c-4451-8cc7-8dee259fb824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724518893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3724518893
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1826031907
Short name T302
Test name
Test status
Simulation time 18771450308 ps
CPU time 32.19 seconds
Started Jul 03 05:45:19 PM PDT 24
Finished Jul 03 05:45:51 PM PDT 24
Peak memory 199900 kb
Host smart-6dd3bbb2-24a4-4680-b0b2-f2c117d9919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826031907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1826031907
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2942649076
Short name T454
Test name
Test status
Simulation time 268049869097 ps
CPU time 49.39 seconds
Started Jul 03 05:45:19 PM PDT 24
Finished Jul 03 05:46:09 PM PDT 24
Peak memory 199904 kb
Host smart-e23fd2ea-dbb0-40c1-8b0d-e9522294134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942649076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2942649076
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1324254314
Short name T1082
Test name
Test status
Simulation time 91320540929 ps
CPU time 17.27 seconds
Started Jul 03 05:45:21 PM PDT 24
Finished Jul 03 05:45:38 PM PDT 24
Peak memory 199976 kb
Host smart-19b2293a-f064-446d-9d8c-1e6145ef20e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324254314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1324254314
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3470279526
Short name T632
Test name
Test status
Simulation time 32266197858 ps
CPU time 24.86 seconds
Started Jul 03 05:45:22 PM PDT 24
Finished Jul 03 05:45:47 PM PDT 24
Peak memory 199900 kb
Host smart-18a1c0d5-189c-4378-b958-fd3e4170f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470279526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3470279526
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1565885275
Short name T755
Test name
Test status
Simulation time 291913850479 ps
CPU time 164.71 seconds
Started Jul 03 05:45:21 PM PDT 24
Finished Jul 03 05:48:06 PM PDT 24
Peak memory 199944 kb
Host smart-db5f2d20-5282-4a60-b723-dc7f763fdf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565885275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1565885275
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2667579073
Short name T247
Test name
Test status
Simulation time 62444674083 ps
CPU time 51.6 seconds
Started Jul 03 05:45:24 PM PDT 24
Finished Jul 03 05:46:16 PM PDT 24
Peak memory 200008 kb
Host smart-4ba44ab2-d441-4c97-beb1-470cca508c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667579073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2667579073
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3929646172
Short name T485
Test name
Test status
Simulation time 15373969 ps
CPU time 0.53 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:15 PM PDT 24
Peak memory 195204 kb
Host smart-b110e236-2a53-4fd4-987b-212fdb75a5f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929646172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3929646172
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1918720273
Short name T1017
Test name
Test status
Simulation time 59689427750 ps
CPU time 19.92 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:43:47 PM PDT 24
Peak memory 199936 kb
Host smart-508e88ad-a9cf-46ba-b170-e2c8dc0db3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918720273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1918720273
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1646202490
Short name T967
Test name
Test status
Simulation time 20741193283 ps
CPU time 30.11 seconds
Started Jul 03 05:43:10 PM PDT 24
Finished Jul 03 05:43:41 PM PDT 24
Peak memory 199900 kb
Host smart-cf6f388d-2025-4625-b900-ed3fbfeae9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646202490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1646202490
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.573343879
Short name T843
Test name
Test status
Simulation time 36213999281 ps
CPU time 33.09 seconds
Started Jul 03 05:43:39 PM PDT 24
Finished Jul 03 05:44:13 PM PDT 24
Peak memory 199976 kb
Host smart-a993e89a-877c-4360-afb8-617bc5b7ab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573343879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.573343879
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1377800672
Short name T291
Test name
Test status
Simulation time 28484991790 ps
CPU time 4.63 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:43:28 PM PDT 24
Peak memory 199952 kb
Host smart-a990a87e-b102-4bf7-819b-666423ac48b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377800672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1377800672
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.312815733
Short name T985
Test name
Test status
Simulation time 58867253875 ps
CPU time 430.46 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:50:28 PM PDT 24
Peak memory 199876 kb
Host smart-2a8a5cff-a06e-4683-8ec4-0fa9320e9b30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312815733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.312815733
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1383588441
Short name T1
Test name
Test status
Simulation time 1506285253 ps
CPU time 1.48 seconds
Started Jul 03 05:43:21 PM PDT 24
Finished Jul 03 05:43:23 PM PDT 24
Peak memory 197284 kb
Host smart-95e19ecf-647a-4a8e-94fe-7b14b5e44ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383588441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1383588441
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1968691753
Short name T500
Test name
Test status
Simulation time 3880503153 ps
CPU time 6.41 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:43:32 PM PDT 24
Peak memory 199992 kb
Host smart-adcd651b-3b1f-404d-b4a9-ce25916ad519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968691753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1968691753
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1361072656
Short name T1078
Test name
Test status
Simulation time 6213344968 ps
CPU time 341.19 seconds
Started Jul 03 05:43:19 PM PDT 24
Finished Jul 03 05:49:00 PM PDT 24
Peak memory 199908 kb
Host smart-9d93c721-5846-40be-b88e-02f960437258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361072656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1361072656
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1928628987
Short name T1041
Test name
Test status
Simulation time 2482410272 ps
CPU time 1.94 seconds
Started Jul 03 05:43:24 PM PDT 24
Finished Jul 03 05:43:27 PM PDT 24
Peak memory 198500 kb
Host smart-ed1ab2d9-a93e-426f-862c-65352a49a215
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928628987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1928628987
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3373209258
Short name T1032
Test name
Test status
Simulation time 40624001670 ps
CPU time 17.57 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:33 PM PDT 24
Peak memory 199188 kb
Host smart-0ce5f1f9-2dd5-441a-ad73-28be96b93349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373209258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3373209258
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3815317318
Short name T528
Test name
Test status
Simulation time 6974361103 ps
CPU time 1.93 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:43:15 PM PDT 24
Peak memory 196224 kb
Host smart-4dd44246-877f-4329-9178-c7436dbda39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815317318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3815317318
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3362979600
Short name T303
Test name
Test status
Simulation time 5296163238 ps
CPU time 12.43 seconds
Started Jul 03 05:43:11 PM PDT 24
Finished Jul 03 05:43:24 PM PDT 24
Peak memory 199676 kb
Host smart-146a8933-482c-4a5e-a474-d532df05dc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362979600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3362979600
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.253975217
Short name T410
Test name
Test status
Simulation time 847363725 ps
CPU time 2.98 seconds
Started Jul 03 05:43:19 PM PDT 24
Finished Jul 03 05:43:23 PM PDT 24
Peak memory 198860 kb
Host smart-ec4838d0-4020-47bc-b757-2b70247447c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253975217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.253975217
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2610122125
Short name T1025
Test name
Test status
Simulation time 78695579151 ps
CPU time 130.47 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:45:37 PM PDT 24
Peak memory 199892 kb
Host smart-221ae3df-ef60-444f-aa51-ae40793d0c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610122125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2610122125
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2080222642
Short name T192
Test name
Test status
Simulation time 6424757645 ps
CPU time 11.12 seconds
Started Jul 03 05:45:19 PM PDT 24
Finished Jul 03 05:45:31 PM PDT 24
Peak memory 199884 kb
Host smart-d9b9d098-07ea-4fe9-ad47-e0be3310df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080222642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2080222642
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.192191647
Short name T947
Test name
Test status
Simulation time 56362316573 ps
CPU time 123.92 seconds
Started Jul 03 05:45:23 PM PDT 24
Finished Jul 03 05:47:27 PM PDT 24
Peak memory 199928 kb
Host smart-c65c8cf0-5826-49a8-aa61-6c8fb65334df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192191647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.192191647
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2606388310
Short name T260
Test name
Test status
Simulation time 22690857594 ps
CPU time 36.51 seconds
Started Jul 03 05:45:21 PM PDT 24
Finished Jul 03 05:45:58 PM PDT 24
Peak memory 199916 kb
Host smart-b1fde647-0725-4674-926b-81160a252195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606388310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2606388310
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3237357411
Short name T912
Test name
Test status
Simulation time 45665767664 ps
CPU time 35.95 seconds
Started Jul 03 05:45:23 PM PDT 24
Finished Jul 03 05:45:59 PM PDT 24
Peak memory 199952 kb
Host smart-27fd171a-f3b2-4cab-a2e5-a461404f5aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237357411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3237357411
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3721987923
Short name T583
Test name
Test status
Simulation time 78059551231 ps
CPU time 35.44 seconds
Started Jul 03 05:45:22 PM PDT 24
Finished Jul 03 05:45:58 PM PDT 24
Peak memory 199920 kb
Host smart-471a54e3-d435-4771-87a4-89ec062d5156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721987923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3721987923
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.60276777
Short name T588
Test name
Test status
Simulation time 94187596505 ps
CPU time 59.72 seconds
Started Jul 03 05:45:23 PM PDT 24
Finished Jul 03 05:46:23 PM PDT 24
Peak memory 199944 kb
Host smart-a6bfb713-674d-4ba7-91fe-f2ad1846123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60276777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.60276777
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2878732765
Short name T764
Test name
Test status
Simulation time 24385610754 ps
CPU time 36.94 seconds
Started Jul 03 05:45:23 PM PDT 24
Finished Jul 03 05:46:01 PM PDT 24
Peak memory 199944 kb
Host smart-4b982aa1-60ac-4359-9602-b5b211f084b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878732765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2878732765
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1556767683
Short name T425
Test name
Test status
Simulation time 11480090 ps
CPU time 0.55 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:43:22 PM PDT 24
Peak memory 195568 kb
Host smart-b51c2dd9-7b39-44b1-a24f-eb9e3bd7c532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556767683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1556767683
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3197263892
Short name T721
Test name
Test status
Simulation time 26143926566 ps
CPU time 42.19 seconds
Started Jul 03 05:43:18 PM PDT 24
Finished Jul 03 05:44:01 PM PDT 24
Peak memory 199884 kb
Host smart-43e44053-e299-41bb-923a-b7cdb0473dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197263892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3197263892
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3065575546
Short name T1053
Test name
Test status
Simulation time 74729001461 ps
CPU time 63.64 seconds
Started Jul 03 05:43:18 PM PDT 24
Finished Jul 03 05:44:22 PM PDT 24
Peak memory 199896 kb
Host smart-c45f20d4-4f26-4fba-843d-4d3708868263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065575546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3065575546
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.813987651
Short name T1038
Test name
Test status
Simulation time 74684586227 ps
CPU time 104.04 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:45:08 PM PDT 24
Peak memory 199896 kb
Host smart-3e05e857-572d-4dcc-bc75-f972a3209d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813987651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.813987651
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3368635160
Short name T660
Test name
Test status
Simulation time 16821133725 ps
CPU time 10.29 seconds
Started Jul 03 05:43:10 PM PDT 24
Finished Jul 03 05:43:20 PM PDT 24
Peak memory 198584 kb
Host smart-940c8215-f1e5-4a5f-bf50-8286beabe111
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368635160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3368635160
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.956771646
Short name T318
Test name
Test status
Simulation time 167601761208 ps
CPU time 185.04 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:46:28 PM PDT 24
Peak memory 199936 kb
Host smart-78371d7d-e037-47a9-8e21-25ff7c6bdfc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956771646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.956771646
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3399547857
Short name T835
Test name
Test status
Simulation time 9479729586 ps
CPU time 7.26 seconds
Started Jul 03 05:43:18 PM PDT 24
Finished Jul 03 05:43:26 PM PDT 24
Peak memory 199728 kb
Host smart-bb0c9c34-3d62-41c9-992c-0ff1d56211c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399547857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3399547857
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.3892184896
Short name T1066
Test name
Test status
Simulation time 12870700784 ps
CPU time 202.81 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:46:40 PM PDT 24
Peak memory 199972 kb
Host smart-8182f040-4573-4cd7-8c39-a575a7e652b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892184896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3892184896
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3747341432
Short name T354
Test name
Test status
Simulation time 5899278950 ps
CPU time 7.68 seconds
Started Jul 03 05:43:17 PM PDT 24
Finished Jul 03 05:43:25 PM PDT 24
Peak memory 199332 kb
Host smart-6148bcb7-a310-48ca-af62-a0fa9433fce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747341432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3747341432
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2174104367
Short name T614
Test name
Test status
Simulation time 200042501993 ps
CPU time 195.48 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:46:30 PM PDT 24
Peak memory 199816 kb
Host smart-606a94e1-02fc-4b21-8d52-b8275015358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174104367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2174104367
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.287219986
Short name T1034
Test name
Test status
Simulation time 35111712694 ps
CPU time 12.49 seconds
Started Jul 03 05:43:17 PM PDT 24
Finished Jul 03 05:43:30 PM PDT 24
Peak memory 196808 kb
Host smart-956d1ed2-414b-49be-9449-2dc3f851304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287219986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.287219986
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3758456818
Short name T651
Test name
Test status
Simulation time 5563994965 ps
CPU time 7.65 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:43:31 PM PDT 24
Peak memory 199908 kb
Host smart-683dcfb6-02e5-4577-86cc-7bf3f9cbe199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758456818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3758456818
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.208470897
Short name T88
Test name
Test status
Simulation time 259484949569 ps
CPU time 1092.52 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 06:01:27 PM PDT 24
Peak memory 199892 kb
Host smart-76d104dd-2047-47d4-9c4d-69418dce5302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208470897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.208470897
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1833556794
Short name T592
Test name
Test status
Simulation time 1008499410 ps
CPU time 6.03 seconds
Started Jul 03 05:43:13 PM PDT 24
Finished Jul 03 05:43:20 PM PDT 24
Peak memory 198912 kb
Host smart-686f25ac-cdd7-469a-bed9-98d9e6b10184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833556794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1833556794
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2398732257
Short name T448
Test name
Test status
Simulation time 75367213494 ps
CPU time 34.94 seconds
Started Jul 03 05:43:24 PM PDT 24
Finished Jul 03 05:44:00 PM PDT 24
Peak memory 199908 kb
Host smart-09a8a0aa-3c05-4662-b240-6a43cf10996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398732257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2398732257
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.4252112459
Short name T563
Test name
Test status
Simulation time 11262315267 ps
CPU time 21.32 seconds
Started Jul 03 05:45:23 PM PDT 24
Finished Jul 03 05:45:44 PM PDT 24
Peak memory 199808 kb
Host smart-0676a780-dd16-4996-9637-b52918a730e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252112459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.4252112459
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.4219238181
Short name T148
Test name
Test status
Simulation time 21174041673 ps
CPU time 10.52 seconds
Started Jul 03 05:45:23 PM PDT 24
Finished Jul 03 05:45:34 PM PDT 24
Peak memory 199936 kb
Host smart-677a764a-fbca-498e-b269-f0fc7e520b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219238181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.4219238181
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.899700718
Short name T911
Test name
Test status
Simulation time 56054983199 ps
CPU time 75.07 seconds
Started Jul 03 05:45:24 PM PDT 24
Finished Jul 03 05:46:39 PM PDT 24
Peak memory 199968 kb
Host smart-679f323b-9b13-42f6-a192-d734279f0185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899700718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.899700718
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.631355485
Short name T497
Test name
Test status
Simulation time 62163444366 ps
CPU time 48.35 seconds
Started Jul 03 05:45:31 PM PDT 24
Finished Jul 03 05:46:19 PM PDT 24
Peak memory 199944 kb
Host smart-ca8c079c-582a-47ce-a7ca-f6238f85ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631355485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.631355485
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3852664422
Short name T442
Test name
Test status
Simulation time 17570294845 ps
CPU time 29.48 seconds
Started Jul 03 05:45:31 PM PDT 24
Finished Jul 03 05:46:00 PM PDT 24
Peak memory 199928 kb
Host smart-a9aa0355-6edb-429c-ad7b-09fd079f21cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852664422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3852664422
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1705874381
Short name T628
Test name
Test status
Simulation time 24529272324 ps
CPU time 11.36 seconds
Started Jul 03 05:45:28 PM PDT 24
Finished Jul 03 05:45:40 PM PDT 24
Peak memory 199896 kb
Host smart-3608eea7-3277-45ef-987e-29f93aa413ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705874381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1705874381
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4088571419
Short name T342
Test name
Test status
Simulation time 59816234021 ps
CPU time 19.9 seconds
Started Jul 03 05:45:23 PM PDT 24
Finished Jul 03 05:45:43 PM PDT 24
Peak memory 199760 kb
Host smart-79553d72-60df-431b-8e13-bba43adf7975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088571419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4088571419
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1161370190
Short name T732
Test name
Test status
Simulation time 22779010444 ps
CPU time 20.15 seconds
Started Jul 03 05:45:28 PM PDT 24
Finished Jul 03 05:45:48 PM PDT 24
Peak memory 199824 kb
Host smart-6005073d-e4e0-4404-a136-62834f6e7679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161370190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1161370190
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4277203569
Short name T175
Test name
Test status
Simulation time 145005377697 ps
CPU time 107.97 seconds
Started Jul 03 05:45:23 PM PDT 24
Finished Jul 03 05:47:11 PM PDT 24
Peak memory 199920 kb
Host smart-cd2df08a-0711-463b-b3e1-1ef62ec6f62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277203569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4277203569
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3288580714
Short name T901
Test name
Test status
Simulation time 28723376 ps
CPU time 0.57 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:15 PM PDT 24
Peak memory 195248 kb
Host smart-91a4e6c2-36e5-4eb3-87ed-b2a910a52f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288580714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3288580714
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3708387533
Short name T842
Test name
Test status
Simulation time 106062964478 ps
CPU time 357.77 seconds
Started Jul 03 05:43:13 PM PDT 24
Finished Jul 03 05:49:11 PM PDT 24
Peak memory 199888 kb
Host smart-46940059-d004-4938-a2a6-0cf3019ba3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708387533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3708387533
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.580033851
Short name T935
Test name
Test status
Simulation time 27907036591 ps
CPU time 13.42 seconds
Started Jul 03 05:43:09 PM PDT 24
Finished Jul 03 05:43:23 PM PDT 24
Peak memory 200008 kb
Host smart-fdc64498-728b-4a08-8718-55b9016fa0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580033851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.580033851
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.694681539
Short name T806
Test name
Test status
Simulation time 78084891216 ps
CPU time 65.26 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:44:18 PM PDT 24
Peak memory 199900 kb
Host smart-5ce390cf-efec-4ece-8b46-353ecb6554bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694681539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.694681539
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1420704989
Short name T1003
Test name
Test status
Simulation time 26063472440 ps
CPU time 62.26 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:44:18 PM PDT 24
Peak memory 199980 kb
Host smart-9e843c31-bd99-46a3-acd1-0caa2739eac6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420704989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1420704989
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1778069576
Short name T668
Test name
Test status
Simulation time 96882793090 ps
CPU time 257.95 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:47:30 PM PDT 24
Peak memory 200024 kb
Host smart-4f9d1b4d-b054-4dcb-b50a-be0d74e1538e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1778069576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1778069576
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2569893022
Short name T906
Test name
Test status
Simulation time 4172208039 ps
CPU time 2.52 seconds
Started Jul 03 05:43:19 PM PDT 24
Finished Jul 03 05:43:22 PM PDT 24
Peak memory 198052 kb
Host smart-d1edf0d8-c581-4d8e-9eec-74dffe5f2670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569893022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2569893022
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.3561469404
Short name T839
Test name
Test status
Simulation time 12875171309 ps
CPU time 160.62 seconds
Started Jul 03 05:43:06 PM PDT 24
Finished Jul 03 05:45:47 PM PDT 24
Peak memory 199956 kb
Host smart-6a591f60-1056-4fdd-a9e2-ccb959d31b21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561469404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3561469404
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3815876687
Short name T685
Test name
Test status
Simulation time 4481193562 ps
CPU time 35.18 seconds
Started Jul 03 05:43:21 PM PDT 24
Finished Jul 03 05:43:57 PM PDT 24
Peak memory 198164 kb
Host smart-cb70d45a-4032-4d83-ba2e-7a598ae00289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3815876687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3815876687
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.149662748
Short name T922
Test name
Test status
Simulation time 19800209424 ps
CPU time 7.41 seconds
Started Jul 03 05:43:17 PM PDT 24
Finished Jul 03 05:43:25 PM PDT 24
Peak memory 199576 kb
Host smart-f24fd7b0-28a0-4505-8c11-cefdaf46397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149662748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.149662748
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.121078781
Short name T754
Test name
Test status
Simulation time 4553775081 ps
CPU time 7.45 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:22 PM PDT 24
Peak memory 196044 kb
Host smart-65a50c12-0dd4-4c76-a039-f97f1c877fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121078781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.121078781
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.495967200
Short name T1023
Test name
Test status
Simulation time 753957675 ps
CPU time 1.3 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:43:25 PM PDT 24
Peak memory 198344 kb
Host smart-03f9b5b7-d66b-4f4e-a47f-d59008160744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495967200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.495967200
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4005129427
Short name T295
Test name
Test status
Simulation time 6213732544 ps
CPU time 18.73 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:43:34 PM PDT 24
Peak memory 199480 kb
Host smart-71512301-934d-4e4c-a245-9d7cb090f1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005129427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4005129427
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1480160410
Short name T38
Test name
Test status
Simulation time 68077486392 ps
CPU time 50.7 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:44:07 PM PDT 24
Peak memory 199896 kb
Host smart-e4fd68c9-c010-4b56-8b0e-41bde402a09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480160410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1480160410
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.227030786
Short name T1067
Test name
Test status
Simulation time 77878137832 ps
CPU time 63.29 seconds
Started Jul 03 05:45:24 PM PDT 24
Finished Jul 03 05:46:27 PM PDT 24
Peak memory 199904 kb
Host smart-fc10b10f-2693-4b65-9ac5-8965c4e1f039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227030786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.227030786
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1735795650
Short name T160
Test name
Test status
Simulation time 177935228156 ps
CPU time 74.69 seconds
Started Jul 03 05:45:25 PM PDT 24
Finished Jul 03 05:46:40 PM PDT 24
Peak memory 200000 kb
Host smart-2bbd4ad3-f0b2-4ad9-acde-bb37fef35dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735795650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1735795650
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1653040936
Short name T724
Test name
Test status
Simulation time 169989259220 ps
CPU time 53.41 seconds
Started Jul 03 05:45:24 PM PDT 24
Finished Jul 03 05:46:18 PM PDT 24
Peak memory 199928 kb
Host smart-39e52e77-cd73-4770-b9c3-cb15360de1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653040936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1653040936
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2892102613
Short name T955
Test name
Test status
Simulation time 25649123195 ps
CPU time 17.32 seconds
Started Jul 03 05:45:27 PM PDT 24
Finished Jul 03 05:45:45 PM PDT 24
Peak memory 199892 kb
Host smart-72be37c4-d687-4ac1-b8f8-99aaa0ba0998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892102613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2892102613
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3973938192
Short name T133
Test name
Test status
Simulation time 43099344772 ps
CPU time 76.61 seconds
Started Jul 03 05:45:25 PM PDT 24
Finished Jul 03 05:46:42 PM PDT 24
Peak memory 199904 kb
Host smart-72ff106c-543e-4209-9169-2c46a66acb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973938192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3973938192
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.688106943
Short name T966
Test name
Test status
Simulation time 36740352173 ps
CPU time 27.56 seconds
Started Jul 03 05:45:28 PM PDT 24
Finished Jul 03 05:45:56 PM PDT 24
Peak memory 199964 kb
Host smart-2cd716fc-c58d-49d5-a78d-ff582d58bdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688106943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.688106943
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2582199077
Short name T552
Test name
Test status
Simulation time 97457591199 ps
CPU time 77.94 seconds
Started Jul 03 05:45:28 PM PDT 24
Finished Jul 03 05:46:46 PM PDT 24
Peak memory 199948 kb
Host smart-6de54954-5424-4f4d-b29d-b9ae0501f3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582199077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2582199077
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.781227918
Short name T703
Test name
Test status
Simulation time 38355899459 ps
CPU time 16.49 seconds
Started Jul 03 05:45:30 PM PDT 24
Finished Jul 03 05:45:47 PM PDT 24
Peak memory 199908 kb
Host smart-b52c8096-5746-4b2d-b320-6bfe6a5a7965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781227918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.781227918
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3955593957
Short name T219
Test name
Test status
Simulation time 21145733904 ps
CPU time 34.53 seconds
Started Jul 03 05:45:26 PM PDT 24
Finished Jul 03 05:46:01 PM PDT 24
Peak memory 199844 kb
Host smart-a2bd70bf-25f3-4343-84e6-a2fc4a54f5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955593957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3955593957
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3012017105
Short name T501
Test name
Test status
Simulation time 42219891 ps
CPU time 0.57 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:43:27 PM PDT 24
Peak memory 195296 kb
Host smart-72ef6135-03e7-4a26-844c-7d5f74e692a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012017105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3012017105
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.779170806
Short name T1051
Test name
Test status
Simulation time 107113549023 ps
CPU time 31.1 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:43:43 PM PDT 24
Peak memory 199944 kb
Host smart-fa031412-8b72-4b1e-8dd6-0ba97732dc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779170806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.779170806
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.4267120259
Short name T487
Test name
Test status
Simulation time 51425976444 ps
CPU time 24.23 seconds
Started Jul 03 05:43:18 PM PDT 24
Finished Jul 03 05:43:43 PM PDT 24
Peak memory 199776 kb
Host smart-436219fd-3150-42cb-9dc5-36aa1b74ef5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267120259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.4267120259
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2155632448
Short name T321
Test name
Test status
Simulation time 127548103255 ps
CPU time 102.18 seconds
Started Jul 03 05:43:07 PM PDT 24
Finished Jul 03 05:44:49 PM PDT 24
Peak memory 199820 kb
Host smart-311a795b-72e0-4ad4-98bf-a4c7b552ace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155632448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2155632448
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2204686342
Short name T1062
Test name
Test status
Simulation time 217674077696 ps
CPU time 90 seconds
Started Jul 03 05:43:28 PM PDT 24
Finished Jul 03 05:44:59 PM PDT 24
Peak memory 199976 kb
Host smart-d2ba7468-0dbf-4bf5-a366-da405c6f8540
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204686342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2204686342
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.4215460277
Short name T781
Test name
Test status
Simulation time 128419158691 ps
CPU time 747.87 seconds
Started Jul 03 05:43:33 PM PDT 24
Finished Jul 03 05:56:01 PM PDT 24
Peak memory 199944 kb
Host smart-e8f25780-ea6f-4c83-b347-72d13f0f50a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215460277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.4215460277
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1036714286
Short name T368
Test name
Test status
Simulation time 9037725064 ps
CPU time 17.12 seconds
Started Jul 03 05:43:18 PM PDT 24
Finished Jul 03 05:43:35 PM PDT 24
Peak memory 199348 kb
Host smart-9c48a219-afef-4021-9337-b07be283e00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036714286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1036714286
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2543915815
Short name T832
Test name
Test status
Simulation time 22533505075 ps
CPU time 13.03 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:43:30 PM PDT 24
Peak memory 197276 kb
Host smart-ce9e2380-bd92-401d-a72c-3922dae3ad24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543915815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2543915815
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1454541946
Short name T915
Test name
Test status
Simulation time 22014593770 ps
CPU time 555.49 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:52:27 PM PDT 24
Peak memory 199984 kb
Host smart-72459b0e-dbc1-4dd5-b8ca-e45621fdcf9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1454541946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1454541946
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.4285012301
Short name T892
Test name
Test status
Simulation time 6065370912 ps
CPU time 47.89 seconds
Started Jul 03 05:43:21 PM PDT 24
Finished Jul 03 05:44:09 PM PDT 24
Peak memory 198092 kb
Host smart-b462e949-ac52-4840-9f12-e7a7440c0a5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285012301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.4285012301
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2632052726
Short name T690
Test name
Test status
Simulation time 253059505454 ps
CPU time 579.44 seconds
Started Jul 03 05:43:18 PM PDT 24
Finished Jul 03 05:52:58 PM PDT 24
Peak memory 199924 kb
Host smart-dcb064c1-3ef3-48fd-8cdb-e0737d124ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632052726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2632052726
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2321189038
Short name T7
Test name
Test status
Simulation time 3414646761 ps
CPU time 5.93 seconds
Started Jul 03 05:43:36 PM PDT 24
Finished Jul 03 05:43:42 PM PDT 24
Peak memory 196512 kb
Host smart-06001a93-7058-43bd-8927-e3ede6ddced2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321189038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2321189038
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2768131046
Short name T873
Test name
Test status
Simulation time 1040442189 ps
CPU time 1.42 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:43:28 PM PDT 24
Peak memory 199476 kb
Host smart-4ce37118-814e-42fb-9697-871c687327e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768131046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2768131046
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1104730412
Short name T730
Test name
Test status
Simulation time 125361096174 ps
CPU time 291.07 seconds
Started Jul 03 05:43:21 PM PDT 24
Finished Jul 03 05:48:12 PM PDT 24
Peak memory 199948 kb
Host smart-01d43e4c-104a-44aa-9816-27f4947c65a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104730412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1104730412
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3127894799
Short name T631
Test name
Test status
Simulation time 1004956997 ps
CPU time 4.41 seconds
Started Jul 03 05:43:20 PM PDT 24
Finished Jul 03 05:43:25 PM PDT 24
Peak memory 198972 kb
Host smart-c4f6c0b2-13cd-4714-8b51-c3ee85a2026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127894799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3127894799
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2634118159
Short name T791
Test name
Test status
Simulation time 39303899579 ps
CPU time 74.03 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:44:42 PM PDT 24
Peak memory 199980 kb
Host smart-619b5062-47a4-4581-a58d-06b90053f84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634118159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2634118159
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1022645898
Short name T564
Test name
Test status
Simulation time 97292773255 ps
CPU time 38.91 seconds
Started Jul 03 05:45:29 PM PDT 24
Finished Jul 03 05:46:09 PM PDT 24
Peak memory 199948 kb
Host smart-da0dbe2e-ecf1-4ac0-a5ee-705f59bda8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022645898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1022645898
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.887937458
Short name T749
Test name
Test status
Simulation time 71348416980 ps
CPU time 28.62 seconds
Started Jul 03 05:45:27 PM PDT 24
Finished Jul 03 05:45:55 PM PDT 24
Peak memory 199912 kb
Host smart-1d1b1439-5a91-4c10-aea3-0a5e1013ca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887937458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.887937458
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3760836347
Short name T204
Test name
Test status
Simulation time 95809553203 ps
CPU time 37.87 seconds
Started Jul 03 05:45:27 PM PDT 24
Finished Jul 03 05:46:05 PM PDT 24
Peak memory 199944 kb
Host smart-1b6fd89d-2905-411d-b91a-cb083d468882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760836347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3760836347
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1116636523
Short name T689
Test name
Test status
Simulation time 64189417023 ps
CPU time 90.03 seconds
Started Jul 03 05:45:29 PM PDT 24
Finished Jul 03 05:46:59 PM PDT 24
Peak memory 200004 kb
Host smart-9a4aa636-fdb4-4835-9c6c-ee2aadfd4ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116636523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1116636523
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3985489581
Short name T147
Test name
Test status
Simulation time 53712971972 ps
CPU time 36.87 seconds
Started Jul 03 05:45:27 PM PDT 24
Finished Jul 03 05:46:04 PM PDT 24
Peak memory 199968 kb
Host smart-23fae955-74d8-4743-8819-9d86776129ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985489581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3985489581
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2098438760
Short name T441
Test name
Test status
Simulation time 157346824747 ps
CPU time 102.06 seconds
Started Jul 03 05:45:29 PM PDT 24
Finished Jul 03 05:47:11 PM PDT 24
Peak memory 199932 kb
Host smart-54e6fba1-d269-4f7d-b7a8-9e4c60e4f0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098438760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2098438760
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1897100164
Short name T6
Test name
Test status
Simulation time 132262072213 ps
CPU time 110.64 seconds
Started Jul 03 05:45:25 PM PDT 24
Finished Jul 03 05:47:16 PM PDT 24
Peak memory 199940 kb
Host smart-22206090-a4ea-45d9-8c48-7ed6e9254d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897100164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1897100164
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2332384181
Short name T253
Test name
Test status
Simulation time 52375155362 ps
CPU time 26.54 seconds
Started Jul 03 05:45:27 PM PDT 24
Finished Jul 03 05:45:54 PM PDT 24
Peak memory 199900 kb
Host smart-f92dcf3b-7903-49c9-8f3f-ac0299f0a17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332384181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2332384181
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2440751651
Short name T1050
Test name
Test status
Simulation time 15474396 ps
CPU time 0.57 seconds
Started Jul 03 05:43:17 PM PDT 24
Finished Jul 03 05:43:18 PM PDT 24
Peak memory 195324 kb
Host smart-2fe7f5c4-5044-4ba1-8a96-3dbee0d4f821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440751651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2440751651
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.4075203748
Short name T953
Test name
Test status
Simulation time 150122305110 ps
CPU time 37.19 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:52 PM PDT 24
Peak memory 199992 kb
Host smart-1de8285e-77b8-4679-b458-8efd612accd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075203748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4075203748
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.981084412
Short name T815
Test name
Test status
Simulation time 147151242958 ps
CPU time 141.06 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:45:51 PM PDT 24
Peak memory 199984 kb
Host smart-231890b0-f840-4869-8208-2ba0457adfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981084412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.981084412
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1838698929
Short name T855
Test name
Test status
Simulation time 66719430136 ps
CPU time 151.96 seconds
Started Jul 03 05:43:17 PM PDT 24
Finished Jul 03 05:45:49 PM PDT 24
Peak memory 199972 kb
Host smart-83d1b15f-f428-4072-8d99-5e01f9c771a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838698929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1838698929
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2350386979
Short name T452
Test name
Test status
Simulation time 20402911439 ps
CPU time 35.74 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:44:01 PM PDT 24
Peak memory 199976 kb
Host smart-cdf2ae73-be9a-4ce5-8294-0b675fe25fd2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350386979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2350386979
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.137761525
Short name T941
Test name
Test status
Simulation time 115646193384 ps
CPU time 712.21 seconds
Started Jul 03 05:43:38 PM PDT 24
Finished Jul 03 05:55:30 PM PDT 24
Peak memory 199956 kb
Host smart-810e2eee-b060-4e15-99b9-5dc506bd22c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137761525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.137761525
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3086255096
Short name T598
Test name
Test status
Simulation time 11097397280 ps
CPU time 7.66 seconds
Started Jul 03 05:43:17 PM PDT 24
Finished Jul 03 05:43:25 PM PDT 24
Peak memory 199284 kb
Host smart-f46fce0f-a84c-43e8-8cfa-e64200b915f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086255096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3086255096
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.267079396
Short name T409
Test name
Test status
Simulation time 14259741506 ps
CPU time 444.42 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:50:37 PM PDT 24
Peak memory 199876 kb
Host smart-0ed9e743-d4e6-4d22-b6b2-9b17752e244e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267079396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.267079396
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.895256900
Short name T612
Test name
Test status
Simulation time 6043089810 ps
CPU time 22.32 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:38 PM PDT 24
Peak memory 198216 kb
Host smart-a514dcf2-74b5-4c18-9d58-fe44bda0383e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895256900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.895256900
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2414104449
Short name T1069
Test name
Test status
Simulation time 24890181001 ps
CPU time 40.28 seconds
Started Jul 03 05:43:20 PM PDT 24
Finished Jul 03 05:44:01 PM PDT 24
Peak memory 199932 kb
Host smart-1c336df5-8a94-42a3-8588-4da0c62ee748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414104449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2414104449
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3495163974
Short name T269
Test name
Test status
Simulation time 3707978947 ps
CPU time 3.77 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:43:16 PM PDT 24
Peak memory 196788 kb
Host smart-9e09f7fd-c4fc-4f4f-89f7-aeb23dd6e4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495163974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3495163974
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1402058139
Short name T988
Test name
Test status
Simulation time 318774809 ps
CPU time 1.21 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:43:24 PM PDT 24
Peak memory 198244 kb
Host smart-9845c123-b482-4a59-a0ce-86720e68e098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402058139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1402058139
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2106233604
Short name T186
Test name
Test status
Simulation time 361203518531 ps
CPU time 224.51 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:47:11 PM PDT 24
Peak memory 199948 kb
Host smart-156b2f1e-9df5-4869-a35f-a99c4c79485a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106233604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2106233604
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2408216853
Short name T706
Test name
Test status
Simulation time 43016684537 ps
CPU time 467.88 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:51:03 PM PDT 24
Peak memory 216520 kb
Host smart-5117179b-0702-4ded-8b32-86eb42c662d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408216853 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2408216853
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2714672341
Short name T244
Test name
Test status
Simulation time 1102835398 ps
CPU time 1.48 seconds
Started Jul 03 05:43:19 PM PDT 24
Finished Jul 03 05:43:20 PM PDT 24
Peak memory 198564 kb
Host smart-6f183a5e-1861-4467-a6ba-0050e7eb8622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714672341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2714672341
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.912275559
Short name T1061
Test name
Test status
Simulation time 59078512386 ps
CPU time 76.54 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:44:46 PM PDT 24
Peak memory 199836 kb
Host smart-7852d2a8-e0d9-48b0-9654-551c1d23d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912275559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.912275559
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1913010517
Short name T205
Test name
Test status
Simulation time 480679111085 ps
CPU time 121.29 seconds
Started Jul 03 05:45:30 PM PDT 24
Finished Jul 03 05:47:31 PM PDT 24
Peak memory 199944 kb
Host smart-4e063d21-b198-41d1-908a-942c82ab97a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913010517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1913010517
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.605660076
Short name T768
Test name
Test status
Simulation time 61869813266 ps
CPU time 22.68 seconds
Started Jul 03 05:45:27 PM PDT 24
Finished Jul 03 05:45:50 PM PDT 24
Peak memory 200000 kb
Host smart-06b7bd46-8fbe-4bc3-855f-d824ecd52286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605660076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.605660076
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3390618635
Short name T998
Test name
Test status
Simulation time 84600551097 ps
CPU time 30.99 seconds
Started Jul 03 05:45:25 PM PDT 24
Finished Jul 03 05:45:56 PM PDT 24
Peak memory 200008 kb
Host smart-22b2bf44-2992-4da7-85e0-46792eedfe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390618635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3390618635
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3513690823
Short name T525
Test name
Test status
Simulation time 228707158244 ps
CPU time 357.6 seconds
Started Jul 03 05:45:26 PM PDT 24
Finished Jul 03 05:51:23 PM PDT 24
Peak memory 199920 kb
Host smart-5217e7ac-7fa8-4766-b0fb-72a8fa1a2bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513690823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3513690823
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.694190741
Short name T270
Test name
Test status
Simulation time 71147093529 ps
CPU time 92.52 seconds
Started Jul 03 05:45:29 PM PDT 24
Finished Jul 03 05:47:02 PM PDT 24
Peak memory 199920 kb
Host smart-2ac6b20f-48ee-44e3-b4db-42ac380ae7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694190741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.694190741
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.4172645280
Short name T669
Test name
Test status
Simulation time 71000314637 ps
CPU time 24.28 seconds
Started Jul 03 05:45:29 PM PDT 24
Finished Jul 03 05:45:54 PM PDT 24
Peak memory 199952 kb
Host smart-886a41af-a494-4cbb-ae0b-1be6656baeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172645280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.4172645280
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1450936698
Short name T575
Test name
Test status
Simulation time 14998066997 ps
CPU time 42.3 seconds
Started Jul 03 05:45:30 PM PDT 24
Finished Jul 03 05:46:13 PM PDT 24
Peak memory 199964 kb
Host smart-4866fbfa-b34f-4e69-9e67-ad1f2eb43d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450936698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1450936698
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2553117423
Short name T529
Test name
Test status
Simulation time 170044367384 ps
CPU time 33 seconds
Started Jul 03 05:45:29 PM PDT 24
Finished Jul 03 05:46:02 PM PDT 24
Peak memory 200000 kb
Host smart-8f5186b7-5432-4703-9bda-712731229e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553117423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2553117423
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2349642797
Short name T523
Test name
Test status
Simulation time 28177267 ps
CPU time 0.52 seconds
Started Jul 03 05:43:30 PM PDT 24
Finished Jul 03 05:43:31 PM PDT 24
Peak memory 194256 kb
Host smart-a1b8c5c2-087e-4df4-9a7c-cedd4816e545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349642797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2349642797
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.4140952965
Short name T788
Test name
Test status
Simulation time 27666421131 ps
CPU time 37.71 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:44:04 PM PDT 24
Peak memory 199932 kb
Host smart-b9133994-9b52-4614-be60-5d976f2edee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140952965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.4140952965
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1014620287
Short name T1073
Test name
Test status
Simulation time 49855425507 ps
CPU time 52.27 seconds
Started Jul 03 05:43:13 PM PDT 24
Finished Jul 03 05:44:06 PM PDT 24
Peak memory 199940 kb
Host smart-5432867b-9b9c-48be-a611-f10e1143fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014620287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1014620287
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3957474894
Short name T725
Test name
Test status
Simulation time 63562730900 ps
CPU time 60.39 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:44:23 PM PDT 24
Peak memory 200008 kb
Host smart-79564b13-a24b-468d-b199-a62e682bee3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957474894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3957474894
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1687451082
Short name T696
Test name
Test status
Simulation time 11656806087 ps
CPU time 9.64 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:43:33 PM PDT 24
Peak memory 197424 kb
Host smart-4be8984f-98c2-4b32-9d6a-389bc556d5b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687451082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1687451082
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1915837084
Short name T259
Test name
Test status
Simulation time 57250129385 ps
CPU time 286.08 seconds
Started Jul 03 05:43:20 PM PDT 24
Finished Jul 03 05:48:06 PM PDT 24
Peak memory 199944 kb
Host smart-b790238b-89a3-4b00-a4b7-66fb165e874a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915837084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1915837084
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2811302965
Short name T1086
Test name
Test status
Simulation time 917359237 ps
CPU time 1.12 seconds
Started Jul 03 05:43:34 PM PDT 24
Finished Jul 03 05:43:36 PM PDT 24
Peak memory 197128 kb
Host smart-4def6355-9ce4-4c10-8262-d647b176e5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811302965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2811302965
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.3950749103
Short name T494
Test name
Test status
Simulation time 6756904918 ps
CPU time 231.17 seconds
Started Jul 03 05:43:20 PM PDT 24
Finished Jul 03 05:47:12 PM PDT 24
Peak memory 199876 kb
Host smart-077f6e9e-5243-48ed-9e1b-82482e22c540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3950749103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3950749103
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2532767182
Short name T718
Test name
Test status
Simulation time 3907375615 ps
CPU time 8.02 seconds
Started Jul 03 05:43:39 PM PDT 24
Finished Jul 03 05:43:48 PM PDT 24
Peak memory 197840 kb
Host smart-30d9a88a-42f6-4f40-aec9-cd9ddb3bf6c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532767182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2532767182
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3576081672
Short name T1036
Test name
Test status
Simulation time 95719019724 ps
CPU time 38.83 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:43:56 PM PDT 24
Peak memory 199928 kb
Host smart-d37c5ea2-c483-486e-9432-0e146d246464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576081672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3576081672
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2407285171
Short name T789
Test name
Test status
Simulation time 2993316997 ps
CPU time 4.63 seconds
Started Jul 03 05:43:39 PM PDT 24
Finished Jul 03 05:43:45 PM PDT 24
Peak memory 196468 kb
Host smart-14a75de5-b86a-4341-b467-cd199f2fe27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407285171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2407285171
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2917697958
Short name T640
Test name
Test status
Simulation time 472727665 ps
CPU time 1.66 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:43:29 PM PDT 24
Peak memory 198892 kb
Host smart-67c465e8-69ba-4676-9a51-00fe8388a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917697958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2917697958
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2086571457
Short name T812
Test name
Test status
Simulation time 78591858173 ps
CPU time 130.21 seconds
Started Jul 03 05:43:32 PM PDT 24
Finished Jul 03 05:45:43 PM PDT 24
Peak memory 199980 kb
Host smart-d72411a2-b69f-4cfb-b989-b677ea991707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086571457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2086571457
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2727910976
Short name T821
Test name
Test status
Simulation time 43216749176 ps
CPU time 254.06 seconds
Started Jul 03 05:43:11 PM PDT 24
Finished Jul 03 05:47:25 PM PDT 24
Peak memory 208308 kb
Host smart-7e8db82b-2c4e-47dd-815b-17e04288f233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727910976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2727910976
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.538716987
Short name T914
Test name
Test status
Simulation time 1486671571 ps
CPU time 1.69 seconds
Started Jul 03 05:43:27 PM PDT 24
Finished Jul 03 05:43:30 PM PDT 24
Peak memory 199660 kb
Host smart-549323b4-423f-496e-9513-c36d1e32bf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538716987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.538716987
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2975561400
Short name T298
Test name
Test status
Simulation time 237421869193 ps
CPU time 53.39 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:44:09 PM PDT 24
Peak memory 199960 kb
Host smart-98662528-83b7-4e6e-8515-7c038633ce18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975561400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2975561400
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.134454041
Short name T534
Test name
Test status
Simulation time 32397701593 ps
CPU time 49.29 seconds
Started Jul 03 05:45:33 PM PDT 24
Finished Jul 03 05:46:23 PM PDT 24
Peak memory 199988 kb
Host smart-bfa38b5e-bc3f-481a-9653-be6994c78ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134454041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.134454041
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3129638351
Short name T1093
Test name
Test status
Simulation time 196005584961 ps
CPU time 54.84 seconds
Started Jul 03 05:45:30 PM PDT 24
Finished Jul 03 05:46:25 PM PDT 24
Peak memory 199924 kb
Host smart-2623d840-6f20-413e-941f-739afe9f096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129638351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3129638351
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.896116904
Short name T820
Test name
Test status
Simulation time 76015814025 ps
CPU time 30.9 seconds
Started Jul 03 05:45:30 PM PDT 24
Finished Jul 03 05:46:01 PM PDT 24
Peak memory 199972 kb
Host smart-1b9e33cb-9f7d-4c4a-b8f0-309169b66485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896116904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.896116904
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3378340531
Short name T41
Test name
Test status
Simulation time 13646625301 ps
CPU time 20.06 seconds
Started Jul 03 05:45:30 PM PDT 24
Finished Jul 03 05:45:50 PM PDT 24
Peak memory 199788 kb
Host smart-268557f6-aaef-4795-9e21-a11ff6c0a258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378340531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3378340531
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1353934546
Short name T126
Test name
Test status
Simulation time 82125938902 ps
CPU time 131.03 seconds
Started Jul 03 05:45:29 PM PDT 24
Finished Jul 03 05:47:40 PM PDT 24
Peak memory 199712 kb
Host smart-74fac834-4730-487f-9c2f-f5601b84e46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353934546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1353934546
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2975362221
Short name T12
Test name
Test status
Simulation time 122304386703 ps
CPU time 62.22 seconds
Started Jul 03 05:45:34 PM PDT 24
Finished Jul 03 05:46:36 PM PDT 24
Peak memory 199824 kb
Host smart-9c5dad10-c726-41cf-99f7-813d28c0d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975362221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2975362221
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2395463364
Short name T517
Test name
Test status
Simulation time 74806906790 ps
CPU time 39.74 seconds
Started Jul 03 05:45:33 PM PDT 24
Finished Jul 03 05:46:13 PM PDT 24
Peak memory 199908 kb
Host smart-a8f3d6da-e585-471a-8e4b-3416c4a9b9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395463364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2395463364
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1444404684
Short name T684
Test name
Test status
Simulation time 22134191120 ps
CPU time 24.97 seconds
Started Jul 03 05:45:32 PM PDT 24
Finished Jul 03 05:45:57 PM PDT 24
Peak memory 199908 kb
Host smart-c2b29e7e-cc94-42d6-867a-4d064a0f1acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444404684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1444404684
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.4115699975
Short name T846
Test name
Test status
Simulation time 12379697 ps
CPU time 0.59 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:43:23 PM PDT 24
Peak memory 195276 kb
Host smart-45eee5f8-2a9b-4718-9297-66a1c6f4cdb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115699975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.4115699975
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1972034620
Short name T238
Test name
Test status
Simulation time 117770205489 ps
CPU time 237.97 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:47:24 PM PDT 24
Peak memory 199232 kb
Host smart-03b8cc13-e7c6-4f46-b765-be97de129d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972034620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1972034620
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3200690258
Short name T468
Test name
Test status
Simulation time 86615877268 ps
CPU time 36.73 seconds
Started Jul 03 05:43:37 PM PDT 24
Finished Jul 03 05:44:14 PM PDT 24
Peak memory 199956 kb
Host smart-57b13e6d-3205-4516-bbfb-55ff6986ab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200690258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3200690258
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.993143411
Short name T629
Test name
Test status
Simulation time 18905252139 ps
CPU time 6.91 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:21 PM PDT 24
Peak memory 198652 kb
Host smart-27c16d4a-bf4e-4151-807c-73e76e7da004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993143411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.993143411
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3468894825
Short name T656
Test name
Test status
Simulation time 46508213240 ps
CPU time 63.98 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:44:31 PM PDT 24
Peak memory 199884 kb
Host smart-8e94a436-d120-4c2a-8765-ec1b52e1c38e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468894825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3468894825
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2336742964
Short name T458
Test name
Test status
Simulation time 187968222799 ps
CPU time 1182.33 seconds
Started Jul 03 05:43:18 PM PDT 24
Finished Jul 03 06:03:01 PM PDT 24
Peak memory 199892 kb
Host smart-36b4e20f-23a7-4948-bae3-7e78bd106c1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2336742964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2336742964
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.759636458
Short name T404
Test name
Test status
Simulation time 8253839864 ps
CPU time 6.62 seconds
Started Jul 03 05:43:13 PM PDT 24
Finished Jul 03 05:43:20 PM PDT 24
Peak memory 199268 kb
Host smart-5ab4adca-79ee-44ea-9833-871aaaf18924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759636458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.759636458
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.983613963
Short name T710
Test name
Test status
Simulation time 9399860619 ps
CPU time 266.05 seconds
Started Jul 03 05:43:11 PM PDT 24
Finished Jul 03 05:47:37 PM PDT 24
Peak memory 199952 kb
Host smart-b139a868-9f29-4227-bd38-2e219eec2465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983613963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.983613963
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.94852529
Short name T5
Test name
Test status
Simulation time 1486421200 ps
CPU time 3.14 seconds
Started Jul 03 05:43:21 PM PDT 24
Finished Jul 03 05:43:24 PM PDT 24
Peak memory 196796 kb
Host smart-dbaeb6bf-012c-494c-b89a-5632b019ff80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94852529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.94852529
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2276999910
Short name T146
Test name
Test status
Simulation time 9761160870 ps
CPU time 5.12 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:20 PM PDT 24
Peak memory 199984 kb
Host smart-d1cbab87-47b5-40f7-a2c6-24446e81ec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276999910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2276999910
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3924060077
Short name T782
Test name
Test status
Simulation time 506777922 ps
CPU time 1.22 seconds
Started Jul 03 05:43:42 PM PDT 24
Finished Jul 03 05:43:44 PM PDT 24
Peak memory 195420 kb
Host smart-e6391d3f-021a-4cc5-b278-ee9a35dd353c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924060077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3924060077
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3758805476
Short name T522
Test name
Test status
Simulation time 1003941388 ps
CPU time 1.79 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:43:19 PM PDT 24
Peak memory 198388 kb
Host smart-c0ea686d-4e22-4f05-807b-8b73ac29aab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758805476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3758805476
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.4036485073
Short name T337
Test name
Test status
Simulation time 185389909393 ps
CPU time 622.51 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:53:49 PM PDT 24
Peak memory 214712 kb
Host smart-41abf111-ce12-4088-ba13-379195f9d09c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036485073 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.4036485073
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3326246461
Short name T972
Test name
Test status
Simulation time 1108959317 ps
CPU time 2.24 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:43:19 PM PDT 24
Peak memory 198404 kb
Host smart-257e08ae-c9d6-4383-b31a-7a0fe30f87a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326246461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3326246461
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.779084197
Short name T264
Test name
Test status
Simulation time 102621615678 ps
CPU time 83.05 seconds
Started Jul 03 05:43:19 PM PDT 24
Finished Jul 03 05:44:43 PM PDT 24
Peak memory 199992 kb
Host smart-8f2fb085-a014-4703-9c03-8c91e189774b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779084197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.779084197
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3252140054
Short name T524
Test name
Test status
Simulation time 113629746420 ps
CPU time 51.77 seconds
Started Jul 03 05:45:33 PM PDT 24
Finished Jul 03 05:46:26 PM PDT 24
Peak memory 199964 kb
Host smart-ad1c5330-7217-4d6e-99fc-7c87a0ac4ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252140054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3252140054
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.506374743
Short name T919
Test name
Test status
Simulation time 41469491498 ps
CPU time 19.6 seconds
Started Jul 03 05:45:33 PM PDT 24
Finished Jul 03 05:45:53 PM PDT 24
Peak memory 200012 kb
Host smart-d060a9e7-62ab-4773-a2bb-793d3d945d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506374743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.506374743
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3958788670
Short name T1046
Test name
Test status
Simulation time 193474482643 ps
CPU time 317.91 seconds
Started Jul 03 05:45:34 PM PDT 24
Finished Jul 03 05:50:52 PM PDT 24
Peak memory 199776 kb
Host smart-43e275cc-ddbc-4321-86d8-b6fafcb68563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958788670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3958788670
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3769293649
Short name T838
Test name
Test status
Simulation time 37941497321 ps
CPU time 54.91 seconds
Started Jul 03 05:45:33 PM PDT 24
Finished Jul 03 05:46:28 PM PDT 24
Peak memory 199868 kb
Host smart-7da8aeec-6441-4d9d-abd9-b205808a0eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769293649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3769293649
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.850219642
Short name T249
Test name
Test status
Simulation time 9320156568 ps
CPU time 5.84 seconds
Started Jul 03 05:45:36 PM PDT 24
Finished Jul 03 05:45:42 PM PDT 24
Peak memory 199924 kb
Host smart-3395dd35-d027-4530-864f-44131d480582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850219642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.850219642
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1874467229
Short name T963
Test name
Test status
Simulation time 54447051140 ps
CPU time 92.58 seconds
Started Jul 03 05:45:37 PM PDT 24
Finished Jul 03 05:47:10 PM PDT 24
Peak memory 200008 kb
Host smart-364b80e8-008b-4510-8410-d652b54ea464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874467229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1874467229
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.769224136
Short name T229
Test name
Test status
Simulation time 265004626253 ps
CPU time 30.88 seconds
Started Jul 03 05:45:39 PM PDT 24
Finished Jul 03 05:46:10 PM PDT 24
Peak memory 199956 kb
Host smart-fce7ccde-2244-447c-961e-feaef9b6bc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769224136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.769224136
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3423836959
Short name T720
Test name
Test status
Simulation time 31561949776 ps
CPU time 21.14 seconds
Started Jul 03 05:45:38 PM PDT 24
Finished Jul 03 05:45:59 PM PDT 24
Peak memory 199940 kb
Host smart-b2a6e176-1953-4876-ab61-ac9143b3aeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423836959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3423836959
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1914435663
Short name T992
Test name
Test status
Simulation time 38586765997 ps
CPU time 50.65 seconds
Started Jul 03 05:45:35 PM PDT 24
Finished Jul 03 05:46:26 PM PDT 24
Peak memory 199904 kb
Host smart-8dfeecc6-7000-4574-b894-f413af7ca2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914435663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1914435663
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3482008052
Short name T433
Test name
Test status
Simulation time 149080665 ps
CPU time 0.53 seconds
Started Jul 03 05:43:30 PM PDT 24
Finished Jul 03 05:43:31 PM PDT 24
Peak memory 195624 kb
Host smart-9ca84331-0cd6-4787-95f8-309b6a6b4677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482008052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3482008052
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.902758550
Short name T678
Test name
Test status
Simulation time 22134682269 ps
CPU time 19.88 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:43:44 PM PDT 24
Peak memory 199876 kb
Host smart-cbc0dd5f-8024-4841-beb7-8de434ce7226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902758550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.902758550
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2696869132
Short name T392
Test name
Test status
Simulation time 117812737706 ps
CPU time 183.4 seconds
Started Jul 03 05:43:32 PM PDT 24
Finished Jul 03 05:46:36 PM PDT 24
Peak memory 199952 kb
Host smart-3d59640b-6952-4a2e-8cb8-4e2401bcdc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696869132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2696869132
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.992378914
Short name T145
Test name
Test status
Simulation time 107047259728 ps
CPU time 89.03 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:44:46 PM PDT 24
Peak memory 199924 kb
Host smart-c3a3db8c-ab19-4589-b461-f0a6b2e269dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992378914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.992378914
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2511241914
Short name T1068
Test name
Test status
Simulation time 45139682536 ps
CPU time 28.36 seconds
Started Jul 03 05:43:18 PM PDT 24
Finished Jul 03 05:43:47 PM PDT 24
Peak memory 199940 kb
Host smart-89cd6aff-fcbc-406c-9b03-1d610574998d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511241914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2511241914
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.722221623
Short name T756
Test name
Test status
Simulation time 91616534651 ps
CPU time 396.24 seconds
Started Jul 03 05:43:37 PM PDT 24
Finished Jul 03 05:50:14 PM PDT 24
Peak memory 199992 kb
Host smart-37213f64-bf37-4d72-8f7d-f18a742e9bf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722221623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.722221623
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1064110662
Short name T662
Test name
Test status
Simulation time 9451715824 ps
CPU time 4.9 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:43:29 PM PDT 24
Peak memory 198640 kb
Host smart-c76a01cf-17bd-47f1-852c-ae80a498a300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064110662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1064110662
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2015273487
Short name T615
Test name
Test status
Simulation time 6244703033 ps
CPU time 15.31 seconds
Started Jul 03 05:43:09 PM PDT 24
Finished Jul 03 05:43:25 PM PDT 24
Peak memory 198904 kb
Host smart-7d696293-fd1b-4311-b92d-036acf066ff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015273487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2015273487
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2377913046
Short name T1054
Test name
Test status
Simulation time 49711828801 ps
CPU time 80.17 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:44:42 PM PDT 24
Peak memory 199944 kb
Host smart-5886b06c-c7ef-4266-835b-096df4e47822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377913046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2377913046
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.748187512
Short name T934
Test name
Test status
Simulation time 36562622557 ps
CPU time 15.34 seconds
Started Jul 03 05:43:41 PM PDT 24
Finished Jul 03 05:43:57 PM PDT 24
Peak memory 195952 kb
Host smart-67ea5613-657b-405a-9bb2-ed7f3599295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748187512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.748187512
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1968723625
Short name T453
Test name
Test status
Simulation time 304541505 ps
CPU time 0.94 seconds
Started Jul 03 05:43:19 PM PDT 24
Finished Jul 03 05:43:20 PM PDT 24
Peak memory 198384 kb
Host smart-cd23a93c-b735-42e1-a671-871fcf5381c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968723625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1968723625
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.4135208788
Short name T674
Test name
Test status
Simulation time 255408633820 ps
CPU time 1568.3 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 06:09:31 PM PDT 24
Peak memory 199884 kb
Host smart-241d444c-62b4-40a7-93b7-585ca4e37d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135208788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.4135208788
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1355290391
Short name T47
Test name
Test status
Simulation time 263507739653 ps
CPU time 838.96 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:57:26 PM PDT 24
Peak memory 224776 kb
Host smart-fc13af6b-0294-45b6-b501-45cda626208b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355290391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1355290391
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3187125413
Short name T750
Test name
Test status
Simulation time 1471644954 ps
CPU time 2.49 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:43:28 PM PDT 24
Peak memory 198720 kb
Host smart-13e9189b-7c75-4295-8fe6-26d06638a55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187125413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3187125413
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.815119940
Short name T305
Test name
Test status
Simulation time 38340319187 ps
CPU time 57.8 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:44:21 PM PDT 24
Peak memory 199996 kb
Host smart-65c9e733-b25c-4380-9581-69b561e41645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815119940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.815119940
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2956121803
Short name T1008
Test name
Test status
Simulation time 140764095626 ps
CPU time 131.11 seconds
Started Jul 03 05:45:39 PM PDT 24
Finished Jul 03 05:47:50 PM PDT 24
Peak memory 199972 kb
Host smart-a98b0aca-1b01-4321-b703-57670899f3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956121803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2956121803
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.362588285
Short name T847
Test name
Test status
Simulation time 26932686796 ps
CPU time 18.43 seconds
Started Jul 03 05:45:36 PM PDT 24
Finished Jul 03 05:45:55 PM PDT 24
Peak memory 199572 kb
Host smart-00eb07a0-8d23-4e97-8631-970839b3e20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362588285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.362588285
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2691323788
Short name T363
Test name
Test status
Simulation time 122548346296 ps
CPU time 20.79 seconds
Started Jul 03 05:45:38 PM PDT 24
Finished Jul 03 05:45:59 PM PDT 24
Peak memory 199948 kb
Host smart-97adaf86-6a57-4e6b-b352-af3eb78fb14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691323788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2691323788
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1938279941
Short name T823
Test name
Test status
Simulation time 31953035518 ps
CPU time 13.14 seconds
Started Jul 03 05:45:36 PM PDT 24
Finished Jul 03 05:45:49 PM PDT 24
Peak memory 199896 kb
Host smart-9497510c-35dc-4088-befd-b5718af43c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938279941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1938279941
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2711866820
Short name T926
Test name
Test status
Simulation time 17027784081 ps
CPU time 29.15 seconds
Started Jul 03 05:45:34 PM PDT 24
Finished Jul 03 05:46:03 PM PDT 24
Peak memory 199968 kb
Host smart-4ffb48dd-98a7-4a37-863a-e71a97b9d2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711866820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2711866820
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3851657923
Short name T117
Test name
Test status
Simulation time 26592784063 ps
CPU time 11.85 seconds
Started Jul 03 05:45:38 PM PDT 24
Finished Jul 03 05:45:51 PM PDT 24
Peak memory 199912 kb
Host smart-1df8d3d5-2214-4b24-9c7f-ed7244f448be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851657923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3851657923
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2086891362
Short name T811
Test name
Test status
Simulation time 70902853773 ps
CPU time 24.49 seconds
Started Jul 03 05:45:36 PM PDT 24
Finished Jul 03 05:46:01 PM PDT 24
Peak memory 199944 kb
Host smart-7603f9cf-42f0-415d-9d26-14dbb4b017a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086891362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2086891362
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3528289047
Short name T786
Test name
Test status
Simulation time 88047173918 ps
CPU time 15.24 seconds
Started Jul 03 05:45:40 PM PDT 24
Finished Jul 03 05:45:56 PM PDT 24
Peak memory 199988 kb
Host smart-e99b581a-a765-422e-a7bb-aa49b5b89dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528289047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3528289047
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3628512958
Short name T734
Test name
Test status
Simulation time 40631283965 ps
CPU time 18.46 seconds
Started Jul 03 05:45:41 PM PDT 24
Finished Jul 03 05:46:00 PM PDT 24
Peak memory 199952 kb
Host smart-211aab29-c118-4693-957a-09c863cca29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628512958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3628512958
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1444984184
Short name T1026
Test name
Test status
Simulation time 19943283784 ps
CPU time 27.95 seconds
Started Jul 03 05:45:40 PM PDT 24
Finished Jul 03 05:46:09 PM PDT 24
Peak memory 199876 kb
Host smart-7b7ffc32-2a90-4a9e-a022-57a4aa4b3f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444984184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1444984184
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2747799754
Short name T691
Test name
Test status
Simulation time 41477822 ps
CPU time 0.56 seconds
Started Jul 03 05:42:39 PM PDT 24
Finished Jul 03 05:42:45 PM PDT 24
Peak memory 195292 kb
Host smart-bb21a91f-9586-4398-b244-0853720c8e6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747799754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2747799754
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1317875416
Short name T325
Test name
Test status
Simulation time 110881969494 ps
CPU time 45.48 seconds
Started Jul 03 05:42:49 PM PDT 24
Finished Jul 03 05:43:35 PM PDT 24
Peak memory 199940 kb
Host smart-e8af7a80-0e1b-4049-86e3-9df0f527137d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317875416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1317875416
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2150778702
Short name T1048
Test name
Test status
Simulation time 90349876089 ps
CPU time 199.87 seconds
Started Jul 03 05:42:58 PM PDT 24
Finished Jul 03 05:46:19 PM PDT 24
Peak memory 199968 kb
Host smart-54c91d77-929d-49a0-b90d-301379b7de0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150778702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2150778702
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.737476836
Short name T271
Test name
Test status
Simulation time 37186887555 ps
CPU time 54.58 seconds
Started Jul 03 05:42:39 PM PDT 24
Finished Jul 03 05:43:37 PM PDT 24
Peak memory 199804 kb
Host smart-7e7297f5-df77-4a3a-a1c7-51eb3c8e3286
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737476836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.737476836
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3026858365
Short name T1091
Test name
Test status
Simulation time 282030106614 ps
CPU time 302.56 seconds
Started Jul 03 05:42:57 PM PDT 24
Finished Jul 03 05:48:00 PM PDT 24
Peak memory 199960 kb
Host smart-ae9bbba7-3ee6-42f4-9900-94cf58014b3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3026858365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3026858365
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.515050089
Short name T340
Test name
Test status
Simulation time 3335501162 ps
CPU time 3.97 seconds
Started Jul 03 05:42:50 PM PDT 24
Finished Jul 03 05:42:54 PM PDT 24
Peak memory 199928 kb
Host smart-77dea26c-47bc-4843-a9cb-e81e0eb5f698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515050089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.515050089
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.226962038
Short name T481
Test name
Test status
Simulation time 13319140579 ps
CPU time 673.21 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:54:29 PM PDT 24
Peak memory 199992 kb
Host smart-81278848-cf2c-400c-bc81-2de008d9badd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=226962038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.226962038
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1554934507
Short name T482
Test name
Test status
Simulation time 2531223610 ps
CPU time 16.2 seconds
Started Jul 03 05:42:51 PM PDT 24
Finished Jul 03 05:43:07 PM PDT 24
Peak memory 199276 kb
Host smart-513d4cc2-ef1e-43fc-8811-a4c6ad3f911b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1554934507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1554934507
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.627895952
Short name T516
Test name
Test status
Simulation time 32738745850 ps
CPU time 47.15 seconds
Started Jul 03 05:42:57 PM PDT 24
Finished Jul 03 05:43:45 PM PDT 24
Peak memory 199944 kb
Host smart-1b805572-b85e-44c5-a2e3-ad43a3063066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627895952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.627895952
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2272845232
Short name T970
Test name
Test status
Simulation time 3762751564 ps
CPU time 3.11 seconds
Started Jul 03 05:42:51 PM PDT 24
Finished Jul 03 05:42:55 PM PDT 24
Peak memory 196436 kb
Host smart-b1029b9c-000f-434b-abac-58dd9e85efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272845232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2272845232
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.901170832
Short name T1089
Test name
Test status
Simulation time 317770526 ps
CPU time 1.05 seconds
Started Jul 03 05:42:42 PM PDT 24
Finished Jul 03 05:42:44 PM PDT 24
Peak memory 198708 kb
Host smart-fc8d4dd8-a281-473e-923e-4f7d6da2140a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901170832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.901170832
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2344082113
Short name T71
Test name
Test status
Simulation time 400243539979 ps
CPU time 83.04 seconds
Started Jul 03 05:42:56 PM PDT 24
Finished Jul 03 05:44:19 PM PDT 24
Peak memory 199980 kb
Host smart-f934064e-60fd-49d0-b3d7-a79f0f08f6ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344082113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2344082113
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1327854672
Short name T796
Test name
Test status
Simulation time 2233673928 ps
CPU time 2.14 seconds
Started Jul 03 05:42:52 PM PDT 24
Finished Jul 03 05:42:54 PM PDT 24
Peak memory 198584 kb
Host smart-a6f095cb-0ace-435e-9d9e-4cf5a047c2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327854672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1327854672
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.4048590742
Short name T240
Test name
Test status
Simulation time 19246292446 ps
CPU time 31.4 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:43:48 PM PDT 24
Peak memory 199996 kb
Host smart-158149f4-45b5-49ca-82a6-95f9909ad19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048590742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4048590742
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.4140242228
Short name T949
Test name
Test status
Simulation time 46477784 ps
CPU time 0.57 seconds
Started Jul 03 05:43:32 PM PDT 24
Finished Jul 03 05:43:33 PM PDT 24
Peak memory 195308 kb
Host smart-df7ccc36-5b4b-4113-9adc-2499886e4bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140242228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.4140242228
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.544153095
Short name T423
Test name
Test status
Simulation time 52677854354 ps
CPU time 45.78 seconds
Started Jul 03 05:43:24 PM PDT 24
Finished Jul 03 05:44:11 PM PDT 24
Peak memory 199952 kb
Host smart-f752673f-3952-4b0e-bfcc-223c7928a02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544153095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.544153095
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3859682788
Short name T1058
Test name
Test status
Simulation time 38344943617 ps
CPU time 52.92 seconds
Started Jul 03 05:43:18 PM PDT 24
Finished Jul 03 05:44:11 PM PDT 24
Peak memory 200004 kb
Host smart-94e87db0-24a7-4276-a312-88c9dd148737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859682788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3859682788
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2265492897
Short name T196
Test name
Test status
Simulation time 119656350527 ps
CPU time 190.34 seconds
Started Jul 03 05:43:36 PM PDT 24
Finished Jul 03 05:46:47 PM PDT 24
Peak memory 199924 kb
Host smart-c0198415-0c7a-4ec8-8034-e935991a487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265492897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2265492897
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.849331864
Short name T818
Test name
Test status
Simulation time 28481053024 ps
CPU time 54.56 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:44:20 PM PDT 24
Peak memory 199944 kb
Host smart-6b07b47f-e7b7-455c-bf24-82e06f3eeebb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849331864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.849331864
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3499760058
Short name T1028
Test name
Test status
Simulation time 82065694774 ps
CPU time 136.78 seconds
Started Jul 03 05:43:45 PM PDT 24
Finished Jul 03 05:46:02 PM PDT 24
Peak memory 199928 kb
Host smart-ce244bec-e3ac-4d21-810c-a086b1040437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499760058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3499760058
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2822980084
Short name T644
Test name
Test status
Simulation time 637349060 ps
CPU time 1.16 seconds
Started Jul 03 05:43:27 PM PDT 24
Finished Jul 03 05:43:29 PM PDT 24
Peak memory 196000 kb
Host smart-5802787b-5c48-4643-b8bc-67953b1b9f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822980084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2822980084
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.2325901242
Short name T683
Test name
Test status
Simulation time 14426146975 ps
CPU time 332.58 seconds
Started Jul 03 05:43:36 PM PDT 24
Finished Jul 03 05:49:09 PM PDT 24
Peak memory 199896 kb
Host smart-35a3ae35-3e18-4f8a-a27c-a7b4d4163a18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325901242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2325901242
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2707120380
Short name T854
Test name
Test status
Simulation time 5470871663 ps
CPU time 12.5 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:43:38 PM PDT 24
Peak memory 199948 kb
Host smart-59352eb1-342c-4162-a0b2-d20bc19c527b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2707120380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2707120380
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3760535380
Short name T512
Test name
Test status
Simulation time 100844141380 ps
CPU time 159.74 seconds
Started Jul 03 05:43:42 PM PDT 24
Finished Jul 03 05:46:22 PM PDT 24
Peak memory 200004 kb
Host smart-cb13fc0f-4500-41e7-99d6-cffba817fe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760535380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3760535380
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1290099419
Short name T421
Test name
Test status
Simulation time 4628082359 ps
CPU time 7.88 seconds
Started Jul 03 05:43:44 PM PDT 24
Finished Jul 03 05:43:52 PM PDT 24
Peak memory 196000 kb
Host smart-1cc7ce44-5d62-4977-91e4-6ed33a552545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290099419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1290099419
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1716991889
Short name T361
Test name
Test status
Simulation time 6132556698 ps
CPU time 5.6 seconds
Started Jul 03 05:43:24 PM PDT 24
Finished Jul 03 05:43:30 PM PDT 24
Peak memory 199888 kb
Host smart-ea5fbb32-daee-44fa-a521-edba8ddcde80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716991889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1716991889
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3878241449
Short name T647
Test name
Test status
Simulation time 5740380059 ps
CPU time 3.13 seconds
Started Jul 03 05:43:36 PM PDT 24
Finished Jul 03 05:43:39 PM PDT 24
Peak memory 199988 kb
Host smart-008dade4-d614-4ce7-bb45-f8ef04a2a932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878241449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3878241449
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1877887561
Short name T43
Test name
Test status
Simulation time 93458976133 ps
CPU time 229.6 seconds
Started Jul 03 05:43:44 PM PDT 24
Finished Jul 03 05:47:34 PM PDT 24
Peak memory 216316 kb
Host smart-12c703ea-1974-4d7a-81de-aef8dbb943f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877887561 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1877887561
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.4144331133
Short name T381
Test name
Test status
Simulation time 1429781740 ps
CPU time 2.83 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:43:32 PM PDT 24
Peak memory 199628 kb
Host smart-f0d9bfa3-aae9-46be-bfb8-c05e0d05c740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144331133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.4144331133
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3085129945
Short name T1011
Test name
Test status
Simulation time 49562678021 ps
CPU time 90.2 seconds
Started Jul 03 05:43:44 PM PDT 24
Finished Jul 03 05:45:15 PM PDT 24
Peak memory 199932 kb
Host smart-bc82ccd8-166e-4668-8542-b83b690fcef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085129945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3085129945
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.362866960
Short name T149
Test name
Test status
Simulation time 90935003725 ps
CPU time 52.44 seconds
Started Jul 03 05:45:42 PM PDT 24
Finished Jul 03 05:46:35 PM PDT 24
Peak memory 199932 kb
Host smart-dccadc2b-943a-4068-9619-9c9c2c344fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362866960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.362866960
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2352660177
Short name T178
Test name
Test status
Simulation time 12849511963 ps
CPU time 25.1 seconds
Started Jul 03 05:45:42 PM PDT 24
Finished Jul 03 05:46:07 PM PDT 24
Peak memory 199948 kb
Host smart-5694f88f-8ed7-4c78-96f5-41885d0c3f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352660177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2352660177
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.489275848
Short name T170
Test name
Test status
Simulation time 66454282762 ps
CPU time 29.28 seconds
Started Jul 03 05:45:42 PM PDT 24
Finished Jul 03 05:46:12 PM PDT 24
Peak memory 199968 kb
Host smart-3418abf4-e1ad-4b10-9a93-1107bae0d58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489275848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.489275848
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2532116052
Short name T1033
Test name
Test status
Simulation time 28473672333 ps
CPU time 40.36 seconds
Started Jul 03 05:45:42 PM PDT 24
Finished Jul 03 05:46:22 PM PDT 24
Peak memory 199968 kb
Host smart-adb9e1dd-9463-4b97-8109-3ff0314bca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532116052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2532116052
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3097660443
Short name T819
Test name
Test status
Simulation time 152844205966 ps
CPU time 28.14 seconds
Started Jul 03 05:45:41 PM PDT 24
Finished Jul 03 05:46:10 PM PDT 24
Peak memory 199956 kb
Host smart-74254398-cc58-41b3-86b3-3597e9531e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097660443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3097660443
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2464831657
Short name T265
Test name
Test status
Simulation time 114160943076 ps
CPU time 158.03 seconds
Started Jul 03 05:45:41 PM PDT 24
Finished Jul 03 05:48:20 PM PDT 24
Peak memory 199948 kb
Host smart-7b417f92-ace8-4da7-8888-050d6ffdf262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464831657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2464831657
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3475221008
Short name T13
Test name
Test status
Simulation time 16486548087 ps
CPU time 21.13 seconds
Started Jul 03 05:45:43 PM PDT 24
Finished Jul 03 05:46:05 PM PDT 24
Peak memory 199980 kb
Host smart-d4eac893-699c-4ec5-9c3e-e2330f9f2011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475221008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3475221008
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2691529797
Short name T776
Test name
Test status
Simulation time 11489123 ps
CPU time 0.57 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:43:27 PM PDT 24
Peak memory 195588 kb
Host smart-5615a0ba-1134-464b-9c86-611e20d9eba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691529797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2691529797
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.970291255
Short name T1014
Test name
Test status
Simulation time 173272430735 ps
CPU time 132.52 seconds
Started Jul 03 05:43:41 PM PDT 24
Finished Jul 03 05:45:54 PM PDT 24
Peak memory 199916 kb
Host smart-d713a139-0949-429d-a531-cfd9a69861fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970291255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.970291255
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.40265057
Short name T825
Test name
Test status
Simulation time 165918019036 ps
CPU time 99.34 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:45:03 PM PDT 24
Peak memory 199960 kb
Host smart-c36a5fe4-dd62-459f-b4c2-307b5c398e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40265057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.40265057
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.2321454775
Short name T560
Test name
Test status
Simulation time 167916971302 ps
CPU time 234.25 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:47:24 PM PDT 24
Peak memory 198044 kb
Host smart-981cd862-818d-431c-a61a-2355be055212
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321454775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2321454775
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3166511403
Short name T579
Test name
Test status
Simulation time 253891378739 ps
CPU time 362.97 seconds
Started Jul 03 05:43:27 PM PDT 24
Finished Jul 03 05:49:30 PM PDT 24
Peak memory 199972 kb
Host smart-5eb866bf-550c-42e0-a47e-9aa9334a8d27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166511403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3166511403
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2057372424
Short name T866
Test name
Test status
Simulation time 7358925995 ps
CPU time 15.87 seconds
Started Jul 03 05:43:36 PM PDT 24
Finished Jul 03 05:43:52 PM PDT 24
Peak memory 199944 kb
Host smart-fb8dd93b-409c-42ae-9291-104923264825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057372424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2057372424
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3126327311
Short name T875
Test name
Test status
Simulation time 26054182578 ps
CPU time 17.97 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:43:48 PM PDT 24
Peak memory 198968 kb
Host smart-dc8c99d9-f47a-48bc-bba8-920057f71920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126327311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3126327311
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3038482466
Short name T467
Test name
Test status
Simulation time 5585658709 ps
CPU time 54.31 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:44:17 PM PDT 24
Peak memory 199964 kb
Host smart-193bb633-8698-4ee4-b177-1c183f85eafe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3038482466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3038482466
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.542772813
Short name T420
Test name
Test status
Simulation time 4004012763 ps
CPU time 7.47 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:43:38 PM PDT 24
Peak memory 198064 kb
Host smart-3bb0ea17-5d9a-48bb-909a-552567fd9f69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542772813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.542772813
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.376563708
Short name T746
Test name
Test status
Simulation time 37223495670 ps
CPU time 15.75 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:43:38 PM PDT 24
Peak memory 199868 kb
Host smart-f0b981fb-76ee-46fa-8bbb-ab4328ccd0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376563708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.376563708
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1823907227
Short name T406
Test name
Test status
Simulation time 2470271167 ps
CPU time 1.25 seconds
Started Jul 03 05:43:46 PM PDT 24
Finished Jul 03 05:43:48 PM PDT 24
Peak memory 196492 kb
Host smart-4951ae81-4baf-4c97-8b2e-291394d3aa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823907227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1823907227
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3975593064
Short name T745
Test name
Test status
Simulation time 293957255 ps
CPU time 1.01 seconds
Started Jul 03 05:43:38 PM PDT 24
Finished Jul 03 05:43:39 PM PDT 24
Peak memory 198580 kb
Host smart-cf33af2f-c3ab-4dac-a6d2-12f3e2ccbb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975593064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3975593064
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2723949856
Short name T886
Test name
Test status
Simulation time 1226680433 ps
CPU time 2.31 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:43:28 PM PDT 24
Peak memory 198804 kb
Host smart-a7cf1e97-069b-4378-85ac-6ea78dbd6ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723949856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2723949856
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.4074116314
Short name T11
Test name
Test status
Simulation time 24477143029 ps
CPU time 40.82 seconds
Started Jul 03 05:43:40 PM PDT 24
Finished Jul 03 05:44:22 PM PDT 24
Peak memory 199912 kb
Host smart-451abff0-dead-4eda-b27a-23e7181290c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074116314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.4074116314
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1152038355
Short name T1044
Test name
Test status
Simulation time 87906340284 ps
CPU time 13.47 seconds
Started Jul 03 05:45:44 PM PDT 24
Finished Jul 03 05:45:58 PM PDT 24
Peak memory 199928 kb
Host smart-352de7ca-c67b-478b-a087-01b687de6b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152038355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1152038355
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2450446728
Short name T140
Test name
Test status
Simulation time 120598785445 ps
CPU time 101.2 seconds
Started Jul 03 05:45:46 PM PDT 24
Finished Jul 03 05:47:28 PM PDT 24
Peak memory 199876 kb
Host smart-82b86b10-78a7-4744-8120-1226b5e83cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450446728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2450446728
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2430643523
Short name T585
Test name
Test status
Simulation time 30146325995 ps
CPU time 50.21 seconds
Started Jul 03 05:45:43 PM PDT 24
Finished Jul 03 05:46:34 PM PDT 24
Peak memory 199932 kb
Host smart-45908208-8216-49fa-acd4-013acc1e3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430643523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2430643523
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2694524911
Short name T103
Test name
Test status
Simulation time 249249495221 ps
CPU time 355.12 seconds
Started Jul 03 05:45:44 PM PDT 24
Finished Jul 03 05:51:39 PM PDT 24
Peak memory 199972 kb
Host smart-ca3da13d-f31d-4908-87c3-0704afffa7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694524911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2694524911
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2994127104
Short name T763
Test name
Test status
Simulation time 64240721342 ps
CPU time 112.89 seconds
Started Jul 03 05:45:46 PM PDT 24
Finished Jul 03 05:47:40 PM PDT 24
Peak memory 199960 kb
Host smart-0b967124-81d5-4ddd-a719-ed3f0b29e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994127104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2994127104
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3127392349
Short name T349
Test name
Test status
Simulation time 146140206688 ps
CPU time 53.42 seconds
Started Jul 03 05:45:44 PM PDT 24
Finished Jul 03 05:46:38 PM PDT 24
Peak memory 199908 kb
Host smart-1c35d6fc-a4eb-4e64-a514-f4cb1e1a6c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127392349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3127392349
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2569143678
Short name T154
Test name
Test status
Simulation time 115027168302 ps
CPU time 39.97 seconds
Started Jul 03 05:45:47 PM PDT 24
Finished Jul 03 05:46:27 PM PDT 24
Peak memory 199848 kb
Host smart-b21465bd-60ac-4520-b429-9c19cab398ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569143678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2569143678
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.4268309737
Short name T773
Test name
Test status
Simulation time 97595191756 ps
CPU time 177.62 seconds
Started Jul 03 05:45:52 PM PDT 24
Finished Jul 03 05:48:49 PM PDT 24
Peak memory 199924 kb
Host smart-30cb30ec-7084-4387-99a1-9ca400701c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268309737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.4268309737
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.925597950
Short name T172
Test name
Test status
Simulation time 13500671405 ps
CPU time 23.78 seconds
Started Jul 03 05:45:47 PM PDT 24
Finished Jul 03 05:46:11 PM PDT 24
Peak memory 199892 kb
Host smart-799dfbf1-c25e-41f2-85f3-2f2419d3a8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925597950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.925597950
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2129904635
Short name T932
Test name
Test status
Simulation time 54050052718 ps
CPU time 103.19 seconds
Started Jul 03 05:45:48 PM PDT 24
Finished Jul 03 05:47:31 PM PDT 24
Peak memory 199960 kb
Host smart-497bd754-42a1-4895-a284-67501934f949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129904635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2129904635
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2039167663
Short name T761
Test name
Test status
Simulation time 13179474 ps
CPU time 0.57 seconds
Started Jul 03 05:43:39 PM PDT 24
Finished Jul 03 05:43:40 PM PDT 24
Peak memory 195284 kb
Host smart-ffaa6523-64d1-43bf-b399-5b5159e63f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039167663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2039167663
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.900948618
Short name T116
Test name
Test status
Simulation time 34158500178 ps
CPU time 23.4 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:43:47 PM PDT 24
Peak memory 199976 kb
Host smart-14447a76-76dd-4359-a10e-68e9b1426314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900948618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.900948618
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2119523933
Short name T918
Test name
Test status
Simulation time 40931460591 ps
CPU time 60.54 seconds
Started Jul 03 05:43:43 PM PDT 24
Finished Jul 03 05:44:44 PM PDT 24
Peak memory 199848 kb
Host smart-16d905d1-9f69-4c14-8f35-62d6c17ed123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119523933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2119523933
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3357901741
Short name T518
Test name
Test status
Simulation time 31567935356 ps
CPU time 13.97 seconds
Started Jul 03 05:43:19 PM PDT 24
Finished Jul 03 05:43:34 PM PDT 24
Peak memory 199968 kb
Host smart-c37eab7a-0e91-45cc-a903-fe3647526506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357901741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3357901741
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.543296737
Short name T555
Test name
Test status
Simulation time 188826432344 ps
CPU time 145.7 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:45:55 PM PDT 24
Peak memory 199756 kb
Host smart-3cdf1439-4b86-4467-9489-89b6ac8ae38d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543296737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.543296737
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1424728033
Short name T591
Test name
Test status
Simulation time 159051053759 ps
CPU time 469.33 seconds
Started Jul 03 05:43:44 PM PDT 24
Finished Jul 03 05:51:34 PM PDT 24
Peak memory 200016 kb
Host smart-459b1086-8104-4bb9-82d5-5f5f44d5fc2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1424728033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1424728033
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3761958348
Short name T352
Test name
Test status
Simulation time 8025977010 ps
CPU time 3.97 seconds
Started Jul 03 05:43:38 PM PDT 24
Finished Jul 03 05:43:42 PM PDT 24
Peak memory 199284 kb
Host smart-0ba06cc4-ea49-4145-a6db-cbbb41ae3060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761958348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3761958348
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.932168947
Short name T578
Test name
Test status
Simulation time 23356231775 ps
CPU time 1200.43 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 06:03:30 PM PDT 24
Peak memory 199900 kb
Host smart-3152cb0a-a296-443d-a7ad-c99b11e43b85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932168947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.932168947
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1652842729
Short name T395
Test name
Test status
Simulation time 7329340736 ps
CPU time 63.36 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:44:29 PM PDT 24
Peak memory 199036 kb
Host smart-95bd71f8-dcef-4e2e-9891-633670c1a303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652842729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1652842729
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3752726162
Short name T652
Test name
Test status
Simulation time 239530971285 ps
CPU time 90.81 seconds
Started Jul 03 05:43:46 PM PDT 24
Finished Jul 03 05:45:18 PM PDT 24
Peak memory 199940 kb
Host smart-b413e1a8-1b18-4eb7-85d5-c12e306318dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752726162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3752726162
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.342801140
Short name T401
Test name
Test status
Simulation time 2537058451 ps
CPU time 4.73 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:43:31 PM PDT 24
Peak memory 196376 kb
Host smart-fa2d5448-195b-4000-ab29-e99736b141ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342801140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.342801140
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.4266862281
Short name T292
Test name
Test status
Simulation time 6239064787 ps
CPU time 20.22 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:43:46 PM PDT 24
Peak memory 199788 kb
Host smart-fbd4466b-7e05-4c32-a7b3-a69014394ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266862281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.4266862281
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1850236667
Short name T573
Test name
Test status
Simulation time 276986210551 ps
CPU time 94.67 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:44:58 PM PDT 24
Peak memory 199920 kb
Host smart-51a3ce2a-b6aa-48c9-9581-2e874eb36bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850236667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1850236667
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.368415365
Short name T797
Test name
Test status
Simulation time 586561086 ps
CPU time 2.32 seconds
Started Jul 03 05:43:41 PM PDT 24
Finished Jul 03 05:43:44 PM PDT 24
Peak memory 199844 kb
Host smart-1c8f1a0c-99b9-445f-9feb-5c58888823af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368415365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.368415365
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2646347607
Short name T858
Test name
Test status
Simulation time 170214311024 ps
CPU time 65.44 seconds
Started Jul 03 05:43:34 PM PDT 24
Finished Jul 03 05:44:40 PM PDT 24
Peak memory 199968 kb
Host smart-15efe296-5ee8-4612-acaa-35a4f069f218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646347607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2646347607
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1457878925
Short name T400
Test name
Test status
Simulation time 28015110181 ps
CPU time 47.15 seconds
Started Jul 03 05:45:46 PM PDT 24
Finished Jul 03 05:46:34 PM PDT 24
Peak memory 199948 kb
Host smart-f8615b7f-5c67-4189-8a33-571b7e8a65ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457878925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1457878925
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2639437782
Short name T230
Test name
Test status
Simulation time 480291065493 ps
CPU time 70.39 seconds
Started Jul 03 05:45:44 PM PDT 24
Finished Jul 03 05:46:55 PM PDT 24
Peak memory 199856 kb
Host smart-96ea0d8d-e640-4cfb-8e85-36bc86c812d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639437782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2639437782
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3881796356
Short name T850
Test name
Test status
Simulation time 74514293321 ps
CPU time 27.38 seconds
Started Jul 03 05:45:48 PM PDT 24
Finished Jul 03 05:46:16 PM PDT 24
Peak memory 199964 kb
Host smart-a8f4fd66-3661-4526-9eeb-e1685e19332b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881796356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3881796356
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1796463428
Short name T167
Test name
Test status
Simulation time 98827383138 ps
CPU time 281.22 seconds
Started Jul 03 05:45:48 PM PDT 24
Finished Jul 03 05:50:30 PM PDT 24
Peak memory 199952 kb
Host smart-f33661e2-421c-4337-9461-22265ec18a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796463428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1796463428
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.365347188
Short name T163
Test name
Test status
Simulation time 80980901229 ps
CPU time 31.14 seconds
Started Jul 03 05:45:54 PM PDT 24
Finished Jul 03 05:46:25 PM PDT 24
Peak memory 199984 kb
Host smart-ce461d22-34e1-429c-9f48-fa4750dd9320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365347188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.365347188
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2586042509
Short name T173
Test name
Test status
Simulation time 43633595613 ps
CPU time 32.66 seconds
Started Jul 03 05:45:47 PM PDT 24
Finished Jul 03 05:46:20 PM PDT 24
Peak memory 199928 kb
Host smart-e24f6ebf-c4e1-45da-986a-48ce1176b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586042509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2586042509
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3911050984
Short name T289
Test name
Test status
Simulation time 23289031590 ps
CPU time 27.38 seconds
Started Jul 03 05:45:52 PM PDT 24
Finished Jul 03 05:46:19 PM PDT 24
Peak memory 199984 kb
Host smart-5eefecd5-15aa-4091-afae-fbcc8dd6d31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911050984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3911050984
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.737496501
Short name T1035
Test name
Test status
Simulation time 116909120267 ps
CPU time 159.73 seconds
Started Jul 03 05:45:46 PM PDT 24
Finished Jul 03 05:48:27 PM PDT 24
Peak memory 199984 kb
Host smart-a9963662-aa0e-4da6-a6e8-a06add961146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737496501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.737496501
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2473698137
Short name T1040
Test name
Test status
Simulation time 93730934193 ps
CPU time 161.97 seconds
Started Jul 03 05:45:53 PM PDT 24
Finished Jul 03 05:48:35 PM PDT 24
Peak memory 199924 kb
Host smart-ffdf39e1-5ef6-43f7-b760-dc40bc847667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473698137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2473698137
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.4011890893
Short name T1015
Test name
Test status
Simulation time 23010806 ps
CPU time 0.55 seconds
Started Jul 03 05:43:27 PM PDT 24
Finished Jul 03 05:43:28 PM PDT 24
Peak memory 195324 kb
Host smart-7b15d662-5c1d-4698-903b-30186ed87c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011890893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.4011890893
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1091922621
Short name T888
Test name
Test status
Simulation time 31358037480 ps
CPU time 14.07 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:43:41 PM PDT 24
Peak memory 199868 kb
Host smart-1a293a70-b43e-4041-b6aa-42c5cea84d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091922621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1091922621
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.678701620
Short name T675
Test name
Test status
Simulation time 27558132785 ps
CPU time 38.02 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:44:05 PM PDT 24
Peak memory 199944 kb
Host smart-cfefafb7-cb9c-4bbe-a08a-ad3727b7e53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678701620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.678701620
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2408033391
Short name T125
Test name
Test status
Simulation time 179213012639 ps
CPU time 253.34 seconds
Started Jul 03 05:43:25 PM PDT 24
Finished Jul 03 05:47:39 PM PDT 24
Peak memory 199932 kb
Host smart-d3b63f03-dd9e-4010-b218-594d3f2b6a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408033391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2408033391
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3183832577
Short name T543
Test name
Test status
Simulation time 29285791150 ps
CPU time 19.98 seconds
Started Jul 03 05:43:43 PM PDT 24
Finished Jul 03 05:44:03 PM PDT 24
Peak memory 199372 kb
Host smart-7e3bc5e0-b495-4c41-bc7b-ed0462c21e0d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183832577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3183832577
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2844843114
Short name T294
Test name
Test status
Simulation time 124581387491 ps
CPU time 1191.19 seconds
Started Jul 03 05:43:33 PM PDT 24
Finished Jul 03 06:03:24 PM PDT 24
Peak memory 200012 kb
Host smart-e8c05172-0eb0-41ed-9068-52a49aa7df8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2844843114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2844843114
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.303202847
Short name T803
Test name
Test status
Simulation time 1220546671 ps
CPU time 9.94 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:43:37 PM PDT 24
Peak memory 198528 kb
Host smart-dd233312-5352-447a-a8a9-94508c8160a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303202847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.303202847
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.1878970142
Short name T248
Test name
Test status
Simulation time 8764729479 ps
CPU time 174.99 seconds
Started Jul 03 05:43:36 PM PDT 24
Finished Jul 03 05:46:31 PM PDT 24
Peak memory 199936 kb
Host smart-130663c9-358a-40af-8bb0-557cdb6e00fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878970142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1878970142
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2177283967
Short name T339
Test name
Test status
Simulation time 7580963473 ps
CPU time 16.56 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:43:46 PM PDT 24
Peak memory 199252 kb
Host smart-ed8ccb39-64fa-4e28-81d6-f3ab37799907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177283967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2177283967
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1665630469
Short name T101
Test name
Test status
Simulation time 186431000147 ps
CPU time 80.45 seconds
Started Jul 03 05:43:28 PM PDT 24
Finished Jul 03 05:44:49 PM PDT 24
Peak memory 199916 kb
Host smart-e4239758-b30a-4fb8-8565-f700202c62c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665630469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1665630469
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.925709322
Short name T740
Test name
Test status
Simulation time 3201169743 ps
CPU time 1.08 seconds
Started Jul 03 05:43:27 PM PDT 24
Finished Jul 03 05:43:29 PM PDT 24
Peak memory 195952 kb
Host smart-e5ddda75-2815-4b6b-ba4c-a398a834b532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925709322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.925709322
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4148853545
Short name T649
Test name
Test status
Simulation time 5999575899 ps
CPU time 11.65 seconds
Started Jul 03 05:43:28 PM PDT 24
Finished Jul 03 05:43:40 PM PDT 24
Peak memory 199728 kb
Host smart-aafe81ac-b7a9-4cd0-9e92-8ab22975d4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148853545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4148853545
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.808894597
Short name T739
Test name
Test status
Simulation time 1089562756 ps
CPU time 3.42 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:43:33 PM PDT 24
Peak memory 198832 kb
Host smart-89c2f3eb-968e-40d8-a65c-12bf7f82ba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808894597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.808894597
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2895522455
Short name T938
Test name
Test status
Simulation time 13706018293 ps
CPU time 20.23 seconds
Started Jul 03 05:43:35 PM PDT 24
Finished Jul 03 05:43:55 PM PDT 24
Peak memory 199912 kb
Host smart-e2c204aa-abcd-492d-8bba-39769b07d820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895522455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2895522455
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1348071775
Short name T1010
Test name
Test status
Simulation time 77740324391 ps
CPU time 9.83 seconds
Started Jul 03 05:45:51 PM PDT 24
Finished Jul 03 05:46:01 PM PDT 24
Peak memory 198932 kb
Host smart-9180022c-0b92-420c-b949-1c922452b284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348071775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1348071775
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2600685527
Short name T996
Test name
Test status
Simulation time 154200220443 ps
CPU time 26.2 seconds
Started Jul 03 05:45:52 PM PDT 24
Finished Jul 03 05:46:19 PM PDT 24
Peak memory 200012 kb
Host smart-a531aa7b-427b-4663-936d-d93dad546940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600685527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2600685527
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2754160711
Short name T702
Test name
Test status
Simulation time 189325473484 ps
CPU time 198.58 seconds
Started Jul 03 05:45:52 PM PDT 24
Finished Jul 03 05:49:11 PM PDT 24
Peak memory 199940 kb
Host smart-93f4173c-52ae-4b77-b895-4efac1708eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754160711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2754160711
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.642583280
Short name T345
Test name
Test status
Simulation time 33172678231 ps
CPU time 28.33 seconds
Started Jul 03 05:45:49 PM PDT 24
Finished Jul 03 05:46:18 PM PDT 24
Peak memory 199916 kb
Host smart-1fb120bd-b13b-4f24-bd79-0c544de323da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642583280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.642583280
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2019978602
Short name T594
Test name
Test status
Simulation time 298708181659 ps
CPU time 83.87 seconds
Started Jul 03 05:45:50 PM PDT 24
Finished Jul 03 05:47:15 PM PDT 24
Peak memory 199956 kb
Host smart-d4738ded-d5e7-4365-8455-400b32bb9003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019978602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2019978602
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2426826505
Short name T876
Test name
Test status
Simulation time 96301634243 ps
CPU time 30.98 seconds
Started Jul 03 05:45:51 PM PDT 24
Finished Jul 03 05:46:22 PM PDT 24
Peak memory 199924 kb
Host smart-f81cec1f-c96a-425d-b50a-0f807aa4261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426826505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2426826505
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.513609600
Short name T945
Test name
Test status
Simulation time 59274391753 ps
CPU time 29.34 seconds
Started Jul 03 05:45:53 PM PDT 24
Finished Jul 03 05:46:23 PM PDT 24
Peak memory 199944 kb
Host smart-fce0f9df-03cb-4d6f-a448-41d0cbdd0b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513609600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.513609600
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1624912889
Short name T174
Test name
Test status
Simulation time 30083205350 ps
CPU time 24.93 seconds
Started Jul 03 05:45:51 PM PDT 24
Finished Jul 03 05:46:16 PM PDT 24
Peak memory 199948 kb
Host smart-4b2809a2-89d7-4139-b20b-15ffd8358d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624912889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1624912889
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1681498977
Short name T235
Test name
Test status
Simulation time 87140846740 ps
CPU time 8.69 seconds
Started Jul 03 05:45:54 PM PDT 24
Finished Jul 03 05:46:03 PM PDT 24
Peak memory 199692 kb
Host smart-3267a75a-8ed9-4eb7-b8b4-96cfa4f08cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681498977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1681498977
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1818631943
Short name T601
Test name
Test status
Simulation time 59376035 ps
CPU time 0.6 seconds
Started Jul 03 05:43:36 PM PDT 24
Finished Jul 03 05:43:37 PM PDT 24
Peak memory 194900 kb
Host smart-d8ad6447-4b45-43e6-9549-78629e1ed76c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818631943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1818631943
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1344611289
Short name T933
Test name
Test status
Simulation time 97979030769 ps
CPU time 77.87 seconds
Started Jul 03 05:43:30 PM PDT 24
Finished Jul 03 05:44:48 PM PDT 24
Peak memory 199868 kb
Host smart-db2e0dba-9c3b-46b5-aba9-479552853d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344611289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1344611289
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.706173751
Short name T299
Test name
Test status
Simulation time 124698609783 ps
CPU time 233.56 seconds
Started Jul 03 05:43:44 PM PDT 24
Finished Jul 03 05:47:38 PM PDT 24
Peak memory 199916 kb
Host smart-924d5dad-582c-4eac-9311-785a9a442784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706173751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.706173751
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2101314885
Short name T799
Test name
Test status
Simulation time 47313181262 ps
CPU time 61.59 seconds
Started Jul 03 05:43:42 PM PDT 24
Finished Jul 03 05:44:44 PM PDT 24
Peak memory 199936 kb
Host smart-69269887-c0ef-4a1b-a960-76ec741f76dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101314885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2101314885
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2207980327
Short name T978
Test name
Test status
Simulation time 127674485397 ps
CPU time 26.09 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:43:56 PM PDT 24
Peak memory 196692 kb
Host smart-8fcc5342-6ab0-407c-947e-34015026092a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207980327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2207980327
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3064496588
Short name T784
Test name
Test status
Simulation time 342111562629 ps
CPU time 345.3 seconds
Started Jul 03 05:43:28 PM PDT 24
Finished Jul 03 05:49:14 PM PDT 24
Peak memory 199992 kb
Host smart-9105e9d1-74e4-4b2a-94ca-a59d9f57c2fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064496588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3064496588
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3286188167
Short name T874
Test name
Test status
Simulation time 11235022888 ps
CPU time 2.95 seconds
Started Jul 03 05:43:28 PM PDT 24
Finished Jul 03 05:43:31 PM PDT 24
Peak memory 199628 kb
Host smart-d19fff1d-2dfe-40e2-a55a-2e36cdfac760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286188167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3286188167
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.3063627458
Short name T251
Test name
Test status
Simulation time 28577554324 ps
CPU time 237.45 seconds
Started Jul 03 05:43:42 PM PDT 24
Finished Jul 03 05:47:40 PM PDT 24
Peak memory 199956 kb
Host smart-b0e2b067-f434-4cb6-80fd-59bfe307f3ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063627458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3063627458
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1815799800
Short name T430
Test name
Test status
Simulation time 6107903634 ps
CPU time 53.43 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:44:20 PM PDT 24
Peak memory 198376 kb
Host smart-8de62260-dc9e-46f3-bdd2-a50089d0e7ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815799800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1815799800
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3582210030
Short name T824
Test name
Test status
Simulation time 107818467410 ps
CPU time 171.68 seconds
Started Jul 03 05:43:27 PM PDT 24
Finished Jul 03 05:46:19 PM PDT 24
Peak memory 199656 kb
Host smart-e141c25e-2854-470a-a19f-a8e746fcadac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582210030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3582210030
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.573066485
Short name T277
Test name
Test status
Simulation time 3152967986 ps
CPU time 3.36 seconds
Started Jul 03 05:43:35 PM PDT 24
Finished Jul 03 05:43:39 PM PDT 24
Peak memory 196416 kb
Host smart-a235d9b2-5be2-4998-aea3-aac6499cdde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573066485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.573066485
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3318532484
Short name T1059
Test name
Test status
Simulation time 314678828 ps
CPU time 1.34 seconds
Started Jul 03 05:43:42 PM PDT 24
Finished Jul 03 05:43:44 PM PDT 24
Peak memory 198988 kb
Host smart-789ab4d0-6b57-4e7c-9595-ec09f1fb75f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318532484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3318532484
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1694338468
Short name T785
Test name
Test status
Simulation time 16109321881 ps
CPU time 16.49 seconds
Started Jul 03 05:43:39 PM PDT 24
Finished Jul 03 05:43:57 PM PDT 24
Peak memory 199964 kb
Host smart-37d2ccdf-660c-4804-8b9a-0182b4aafb94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694338468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1694338468
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1642863005
Short name T519
Test name
Test status
Simulation time 1206671297 ps
CPU time 1.77 seconds
Started Jul 03 05:43:26 PM PDT 24
Finished Jul 03 05:43:28 PM PDT 24
Peak memory 198812 kb
Host smart-1c31a4ac-54a9-4b20-95b2-26f958f6efdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642863005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1642863005
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2382327030
Short name T637
Test name
Test status
Simulation time 54575559407 ps
CPU time 78.17 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:44:48 PM PDT 24
Peak memory 199948 kb
Host smart-30680d5b-7041-4335-b894-31f71f3552e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382327030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2382327030
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1337912878
Short name T1083
Test name
Test status
Simulation time 12666760784 ps
CPU time 19.33 seconds
Started Jul 03 05:45:52 PM PDT 24
Finished Jul 03 05:46:11 PM PDT 24
Peak memory 199956 kb
Host smart-ee6da642-0049-4c73-a34f-8a059d1f879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337912878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1337912878
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1319570035
Short name T91
Test name
Test status
Simulation time 48662991252 ps
CPU time 21.65 seconds
Started Jul 03 05:45:57 PM PDT 24
Finished Jul 03 05:46:19 PM PDT 24
Peak memory 199972 kb
Host smart-bde33c40-4b02-48ee-aa84-ed84a68a171c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319570035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1319570035
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.701913589
Short name T836
Test name
Test status
Simulation time 211925091303 ps
CPU time 130.52 seconds
Started Jul 03 05:45:55 PM PDT 24
Finished Jul 03 05:48:06 PM PDT 24
Peak memory 199976 kb
Host smart-0117a8f5-9943-415b-8355-368215586890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701913589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.701913589
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3843160208
Short name T741
Test name
Test status
Simulation time 44623375639 ps
CPU time 31.54 seconds
Started Jul 03 05:45:58 PM PDT 24
Finished Jul 03 05:46:30 PM PDT 24
Peak memory 199712 kb
Host smart-7ac6bb4e-64db-4aa1-ac29-7864df1b8a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843160208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3843160208
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.8847372
Short name T279
Test name
Test status
Simulation time 12903840294 ps
CPU time 13.21 seconds
Started Jul 03 05:45:55 PM PDT 24
Finished Jul 03 05:46:08 PM PDT 24
Peak memory 199924 kb
Host smart-d2425132-ce01-4e8c-ae8a-6d134542b787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8847372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.8847372
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1815428620
Short name T191
Test name
Test status
Simulation time 171913498950 ps
CPU time 81.43 seconds
Started Jul 03 05:45:57 PM PDT 24
Finished Jul 03 05:47:19 PM PDT 24
Peak memory 199928 kb
Host smart-0587e385-e4d8-4da5-912b-ce089afcea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815428620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1815428620
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.686495497
Short name T982
Test name
Test status
Simulation time 14809614653 ps
CPU time 27.37 seconds
Started Jul 03 05:45:57 PM PDT 24
Finished Jul 03 05:46:25 PM PDT 24
Peak memory 199928 kb
Host smart-6aebed07-c047-480e-9fc0-cd22cc22cc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686495497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.686495497
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2676972851
Short name T162
Test name
Test status
Simulation time 93594292655 ps
CPU time 174.62 seconds
Started Jul 03 05:45:56 PM PDT 24
Finished Jul 03 05:48:50 PM PDT 24
Peak memory 199972 kb
Host smart-42bfef4a-5372-4691-803e-06da8c7769b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676972851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2676972851
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1815958433
Short name T742
Test name
Test status
Simulation time 52833524924 ps
CPU time 43.14 seconds
Started Jul 03 05:45:57 PM PDT 24
Finished Jul 03 05:46:41 PM PDT 24
Peak memory 199988 kb
Host smart-557319a2-f1e5-4283-8f2f-86c72b082b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815958433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1815958433
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3466733200
Short name T486
Test name
Test status
Simulation time 12132093 ps
CPU time 0.54 seconds
Started Jul 03 05:43:43 PM PDT 24
Finished Jul 03 05:43:44 PM PDT 24
Peak memory 194764 kb
Host smart-70a194ce-5821-4d83-bf93-e524bedd1b19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466733200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3466733200
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1411016637
Short name T1060
Test name
Test status
Simulation time 73433804126 ps
CPU time 111.52 seconds
Started Jul 03 05:43:27 PM PDT 24
Finished Jul 03 05:45:20 PM PDT 24
Peak memory 199812 kb
Host smart-e47bd6e9-ea76-4aad-b304-8bbc5fe7e1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411016637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1411016637
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.516232552
Short name T994
Test name
Test status
Simulation time 76867636076 ps
CPU time 24.66 seconds
Started Jul 03 05:43:46 PM PDT 24
Finished Jul 03 05:44:11 PM PDT 24
Peak memory 199852 kb
Host smart-e0aed362-c0c3-4c69-ac16-48222366aa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516232552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.516232552
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2299028773
Short name T890
Test name
Test status
Simulation time 209668644238 ps
CPU time 423.5 seconds
Started Jul 03 05:43:55 PM PDT 24
Finished Jul 03 05:50:59 PM PDT 24
Peak memory 200000 kb
Host smart-f46eb6c8-cbee-48b8-871f-48400ad49176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299028773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2299028773
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.729288448
Short name T93
Test name
Test status
Simulation time 63912400002 ps
CPU time 30.04 seconds
Started Jul 03 05:43:31 PM PDT 24
Finished Jul 03 05:44:01 PM PDT 24
Peak memory 199896 kb
Host smart-7ad1d389-b79f-4dd2-992d-738fdb3e8f46
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729288448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.729288448
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1758136170
Short name T752
Test name
Test status
Simulation time 66096489473 ps
CPU time 456.3 seconds
Started Jul 03 05:43:39 PM PDT 24
Finished Jul 03 05:51:16 PM PDT 24
Peak memory 199868 kb
Host smart-470b7367-3693-4cae-aff8-b1ba71d2f7b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1758136170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1758136170
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2575663278
Short name T950
Test name
Test status
Simulation time 8349317768 ps
CPU time 10.15 seconds
Started Jul 03 05:43:28 PM PDT 24
Finished Jul 03 05:43:39 PM PDT 24
Peak memory 199924 kb
Host smart-ec916ab3-3a06-43ba-ba6b-49ab4c0be020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575663278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2575663278
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.3861444620
Short name T770
Test name
Test status
Simulation time 5106390271 ps
CPU time 280.14 seconds
Started Jul 03 05:43:50 PM PDT 24
Finished Jul 03 05:48:31 PM PDT 24
Peak memory 199940 kb
Host smart-23a970ca-a228-40d1-b407-9d0c7eee9267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861444620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3861444620
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.642720684
Short name T961
Test name
Test status
Simulation time 6033742383 ps
CPU time 13.94 seconds
Started Jul 03 05:43:43 PM PDT 24
Finished Jul 03 05:43:57 PM PDT 24
Peak memory 199164 kb
Host smart-b8e80dd0-89bf-4f5d-aea1-affa1a555557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642720684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.642720684
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1841596024
Short name T1065
Test name
Test status
Simulation time 127116578576 ps
CPU time 42.23 seconds
Started Jul 03 05:43:47 PM PDT 24
Finished Jul 03 05:44:29 PM PDT 24
Peak memory 199812 kb
Host smart-ba455106-73c3-4a95-b12c-da0f66083c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841596024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1841596024
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2266370747
Short name T871
Test name
Test status
Simulation time 2567932597 ps
CPU time 4.7 seconds
Started Jul 03 05:43:28 PM PDT 24
Finished Jul 03 05:43:33 PM PDT 24
Peak memory 195884 kb
Host smart-98c55314-2a37-4c3e-8d8b-37b0b914be24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266370747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2266370747
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1606306117
Short name T979
Test name
Test status
Simulation time 775077918 ps
CPU time 1.92 seconds
Started Jul 03 05:43:27 PM PDT 24
Finished Jul 03 05:43:30 PM PDT 24
Peak memory 198908 kb
Host smart-326f79b0-4700-45db-bfe5-de39cc188b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606306117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1606306117
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2861764638
Short name T852
Test name
Test status
Simulation time 6590843980 ps
CPU time 19.74 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:43:49 PM PDT 24
Peak memory 199872 kb
Host smart-7a09d0ee-8f24-49d4-bddb-c842b2eb5256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861764638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2861764638
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1208595332
Short name T680
Test name
Test status
Simulation time 6545180018 ps
CPU time 11.02 seconds
Started Jul 03 05:43:38 PM PDT 24
Finished Jul 03 05:43:50 PM PDT 24
Peak memory 199656 kb
Host smart-ccc9c77b-ae7c-4e80-b974-3b467dd646d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208595332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1208595332
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1370136992
Short name T498
Test name
Test status
Simulation time 105534840937 ps
CPU time 143.74 seconds
Started Jul 03 05:45:55 PM PDT 24
Finished Jul 03 05:48:19 PM PDT 24
Peak memory 200004 kb
Host smart-b9df74b1-e0c8-4f88-b003-1c2710835a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370136992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1370136992
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.244715156
Short name T883
Test name
Test status
Simulation time 60727190822 ps
CPU time 19.54 seconds
Started Jul 03 05:45:55 PM PDT 24
Finished Jul 03 05:46:15 PM PDT 24
Peak memory 199864 kb
Host smart-7ddbd66b-1d12-48ab-95db-d8aff4017555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244715156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.244715156
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.663168937
Short name T783
Test name
Test status
Simulation time 11876566538 ps
CPU time 17.73 seconds
Started Jul 03 05:45:57 PM PDT 24
Finished Jul 03 05:46:15 PM PDT 24
Peak memory 199944 kb
Host smart-a2fc2f69-c150-489a-a077-be66f0516b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663168937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.663168937
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.765180976
Short name T686
Test name
Test status
Simulation time 89452293140 ps
CPU time 104.68 seconds
Started Jul 03 05:46:00 PM PDT 24
Finished Jul 03 05:47:45 PM PDT 24
Peak memory 199968 kb
Host smart-6ea76915-38c4-4d32-9b35-bfc1fbeabcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765180976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.765180976
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.901922558
Short name T106
Test name
Test status
Simulation time 57503450399 ps
CPU time 61.99 seconds
Started Jul 03 05:45:58 PM PDT 24
Finished Jul 03 05:47:00 PM PDT 24
Peak memory 199768 kb
Host smart-9211809c-9cf8-4bda-a2d5-ad0162b1be32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901922558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.901922558
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1767693582
Short name T924
Test name
Test status
Simulation time 6185680467 ps
CPU time 13.38 seconds
Started Jul 03 05:45:58 PM PDT 24
Finished Jul 03 05:46:12 PM PDT 24
Peak memory 200004 kb
Host smart-730d2ef9-470e-4b5f-b23e-8697c7d7a56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767693582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1767693582
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.612782665
Short name T484
Test name
Test status
Simulation time 26866764980 ps
CPU time 9.87 seconds
Started Jul 03 05:46:00 PM PDT 24
Finished Jul 03 05:46:10 PM PDT 24
Peak memory 199756 kb
Host smart-fce54226-7481-46d6-85e1-dfb28ae66d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612782665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.612782665
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1531900073
Short name T891
Test name
Test status
Simulation time 88100994998 ps
CPU time 35.73 seconds
Started Jul 03 05:46:01 PM PDT 24
Finished Jul 03 05:46:37 PM PDT 24
Peak memory 199916 kb
Host smart-3e149d4e-9b68-4491-92f1-739db06d949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531900073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1531900073
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3202415958
Short name T465
Test name
Test status
Simulation time 147307923170 ps
CPU time 54.24 seconds
Started Jul 03 05:45:58 PM PDT 24
Finished Jul 03 05:46:52 PM PDT 24
Peak memory 199984 kb
Host smart-19287e2d-4bf8-4720-92e0-02cfe71ca15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202415958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3202415958
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3457402827
Short name T587
Test name
Test status
Simulation time 14306594 ps
CPU time 0.57 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:43:59 PM PDT 24
Peak memory 195248 kb
Host smart-06882a8d-47f6-4bd8-95d9-0efcf5fb1c0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457402827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3457402827
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1746551129
Short name T889
Test name
Test status
Simulation time 57045667839 ps
CPU time 54.59 seconds
Started Jul 03 05:43:47 PM PDT 24
Finished Jul 03 05:44:42 PM PDT 24
Peak memory 199868 kb
Host smart-de52f41e-61d3-45c2-a973-e829c03145cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746551129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1746551129
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3939911916
Short name T155
Test name
Test status
Simulation time 75858359482 ps
CPU time 33.5 seconds
Started Jul 03 05:43:30 PM PDT 24
Finished Jul 03 05:44:04 PM PDT 24
Peak memory 199860 kb
Host smart-126ab2d1-08c7-4f20-8e5c-2045cf6bd775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939911916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3939911916
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2457221502
Short name T222
Test name
Test status
Simulation time 87342181190 ps
CPU time 52.33 seconds
Started Jul 03 05:43:46 PM PDT 24
Finished Jul 03 05:44:38 PM PDT 24
Peak memory 200012 kb
Host smart-9b6e8c3a-a8cd-4a07-88cf-c54222ae9b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457221502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2457221502
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3310834523
Short name T323
Test name
Test status
Simulation time 34137629671 ps
CPU time 17.28 seconds
Started Jul 03 05:43:32 PM PDT 24
Finished Jul 03 05:43:50 PM PDT 24
Peak memory 200000 kb
Host smart-30580549-e1c8-42ab-92d4-a2e5f1614ee4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310834523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3310834523
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1623592493
Short name T1084
Test name
Test status
Simulation time 112781353412 ps
CPU time 319.24 seconds
Started Jul 03 05:43:34 PM PDT 24
Finished Jul 03 05:48:54 PM PDT 24
Peak memory 199956 kb
Host smart-82724fcd-19c7-4aa3-b3fa-78a198ad15a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1623592493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1623592493
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.843353532
Short name T443
Test name
Test status
Simulation time 9540717356 ps
CPU time 24.92 seconds
Started Jul 03 05:43:50 PM PDT 24
Finished Jul 03 05:44:16 PM PDT 24
Peak memory 199896 kb
Host smart-6fee5318-e016-4be7-bb41-f3e65ba6e4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843353532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.843353532
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.251038931
Short name T233
Test name
Test status
Simulation time 16073513765 ps
CPU time 114.99 seconds
Started Jul 03 05:43:50 PM PDT 24
Finished Jul 03 05:45:46 PM PDT 24
Peak memory 200008 kb
Host smart-7277cd3d-1ecc-4f61-a85f-9401d4e7d8e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251038931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.251038931
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2411679842
Short name T365
Test name
Test status
Simulation time 4094334027 ps
CPU time 31.26 seconds
Started Jul 03 05:43:43 PM PDT 24
Finished Jul 03 05:44:14 PM PDT 24
Peak memory 199120 kb
Host smart-5591a460-f35f-423b-b213-4a4126a563a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2411679842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2411679842
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.276322016
Short name T943
Test name
Test status
Simulation time 42683546773 ps
CPU time 73.7 seconds
Started Jul 03 05:43:50 PM PDT 24
Finished Jul 03 05:45:05 PM PDT 24
Peak memory 199924 kb
Host smart-758caa1c-de10-4a1b-8394-4e28f6322c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276322016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.276322016
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2106328200
Short name T987
Test name
Test status
Simulation time 1576508109 ps
CPU time 1.83 seconds
Started Jul 03 05:43:53 PM PDT 24
Finished Jul 03 05:43:56 PM PDT 24
Peak memory 195376 kb
Host smart-378acf6f-430d-45e9-8662-4ffc82e7bc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106328200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2106328200
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3510332812
Short name T908
Test name
Test status
Simulation time 6299158307 ps
CPU time 6.06 seconds
Started Jul 03 05:43:36 PM PDT 24
Finished Jul 03 05:43:42 PM PDT 24
Peak memory 199396 kb
Host smart-886b613d-6331-47f6-8069-44ec453c162a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510332812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3510332812
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2881520918
Short name T863
Test name
Test status
Simulation time 251243352772 ps
CPU time 252.65 seconds
Started Jul 03 05:43:35 PM PDT 24
Finished Jul 03 05:47:48 PM PDT 24
Peak memory 199852 kb
Host smart-91a36165-3cb9-4a4e-b017-5c9c376992bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881520918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2881520918
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1950486248
Short name T231
Test name
Test status
Simulation time 150834935191 ps
CPU time 346.44 seconds
Started Jul 03 05:43:33 PM PDT 24
Finished Jul 03 05:49:20 PM PDT 24
Peak memory 216504 kb
Host smart-cdeee596-ff33-498f-8272-3f690227089e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950486248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1950486248
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3020685547
Short name T663
Test name
Test status
Simulation time 1016826472 ps
CPU time 2.1 seconds
Started Jul 03 05:43:44 PM PDT 24
Finished Jul 03 05:43:47 PM PDT 24
Peak memory 199664 kb
Host smart-9b2c18bd-5353-4e2e-91b8-c533d6b09df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020685547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3020685547
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.313196097
Short name T539
Test name
Test status
Simulation time 39773433756 ps
CPU time 51.58 seconds
Started Jul 03 05:43:46 PM PDT 24
Finished Jul 03 05:44:38 PM PDT 24
Peak memory 199992 kb
Host smart-49a1d76c-c14c-45dc-acb6-658b8dbccf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313196097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.313196097
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.889104234
Short name T697
Test name
Test status
Simulation time 183060378864 ps
CPU time 77.4 seconds
Started Jul 03 05:46:01 PM PDT 24
Finished Jul 03 05:47:18 PM PDT 24
Peak memory 200004 kb
Host smart-149a32a0-eb62-4cb2-b665-c047531baa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889104234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.889104234
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.871522454
Short name T989
Test name
Test status
Simulation time 169711578690 ps
CPU time 42.66 seconds
Started Jul 03 05:46:01 PM PDT 24
Finished Jul 03 05:46:44 PM PDT 24
Peak memory 199892 kb
Host smart-97c58c3a-a0fc-4d80-9719-b48359512ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871522454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.871522454
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3266692343
Short name T120
Test name
Test status
Simulation time 27174058136 ps
CPU time 20.63 seconds
Started Jul 03 05:46:01 PM PDT 24
Finished Jul 03 05:46:22 PM PDT 24
Peak memory 199980 kb
Host smart-78d8d6bd-a12a-40a0-8827-e137bf2f6120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266692343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3266692343
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.129686188
Short name T105
Test name
Test status
Simulation time 25998749127 ps
CPU time 22.47 seconds
Started Jul 03 05:46:07 PM PDT 24
Finished Jul 03 05:46:30 PM PDT 24
Peak memory 199968 kb
Host smart-4071472c-0286-4a66-b280-7c7477c982d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129686188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.129686188
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.375089143
Short name T236
Test name
Test status
Simulation time 43943577803 ps
CPU time 69.4 seconds
Started Jul 03 05:46:05 PM PDT 24
Finished Jul 03 05:47:15 PM PDT 24
Peak memory 199944 kb
Host smart-f5252c85-794d-48f4-abcf-ff25297232e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375089143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.375089143
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1479775733
Short name T490
Test name
Test status
Simulation time 77750752803 ps
CPU time 20.93 seconds
Started Jul 03 05:46:05 PM PDT 24
Finished Jul 03 05:46:26 PM PDT 24
Peak memory 198888 kb
Host smart-aaa32886-9989-4b38-a76a-8818733d680e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479775733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1479775733
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.4207881054
Short name T210
Test name
Test status
Simulation time 119775154625 ps
CPU time 90.62 seconds
Started Jul 03 05:46:04 PM PDT 24
Finished Jul 03 05:47:35 PM PDT 24
Peak memory 199952 kb
Host smart-efa0895e-a285-4961-8507-3d963ca1bff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207881054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4207881054
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.4242331067
Short name T182
Test name
Test status
Simulation time 21873158064 ps
CPU time 36.78 seconds
Started Jul 03 05:46:06 PM PDT 24
Finished Jul 03 05:46:43 PM PDT 24
Peak memory 199748 kb
Host smart-d192f9da-8ce3-4ec1-b4f5-3cc6e473b534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242331067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4242331067
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2614994386
Short name T187
Test name
Test status
Simulation time 168260484250 ps
CPU time 17.07 seconds
Started Jul 03 05:46:06 PM PDT 24
Finished Jul 03 05:46:23 PM PDT 24
Peak memory 199676 kb
Host smart-c4383468-0d63-4949-b65f-b781d95c464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614994386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2614994386
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3191523041
Short name T177
Test name
Test status
Simulation time 10588057040 ps
CPU time 27.38 seconds
Started Jul 03 05:46:07 PM PDT 24
Finished Jul 03 05:46:34 PM PDT 24
Peak memory 199940 kb
Host smart-96631f15-486a-4ec9-ba96-b0f1ecc09ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191523041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3191523041
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2777895733
Short name T450
Test name
Test status
Simulation time 39145116 ps
CPU time 0.53 seconds
Started Jul 03 05:43:48 PM PDT 24
Finished Jul 03 05:43:49 PM PDT 24
Peak memory 194776 kb
Host smart-233707db-2c75-499e-9d65-29652c02b088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777895733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2777895733
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1998935024
Short name T621
Test name
Test status
Simulation time 78704632631 ps
CPU time 38.86 seconds
Started Jul 03 05:43:35 PM PDT 24
Finished Jul 03 05:44:14 PM PDT 24
Peak memory 199896 kb
Host smart-23837c6b-b18f-412a-83d1-4a4322fdda74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998935024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1998935024
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2810872486
Short name T817
Test name
Test status
Simulation time 79185578273 ps
CPU time 20.47 seconds
Started Jul 03 05:43:36 PM PDT 24
Finished Jul 03 05:43:57 PM PDT 24
Peak memory 199484 kb
Host smart-33d593d9-9d03-4900-9b7b-df2faae949dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810872486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2810872486
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.32256201
Short name T121
Test name
Test status
Simulation time 222260911890 ps
CPU time 326.89 seconds
Started Jul 03 05:43:37 PM PDT 24
Finished Jul 03 05:49:04 PM PDT 24
Peak memory 200012 kb
Host smart-fa770a02-8638-4046-a1a1-30241c64cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32256201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.32256201
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3723877161
Short name T451
Test name
Test status
Simulation time 29695620401 ps
CPU time 7.61 seconds
Started Jul 03 05:43:44 PM PDT 24
Finished Jul 03 05:43:52 PM PDT 24
Peak memory 199936 kb
Host smart-2545e9f6-301a-47f7-a51b-4ce87c33a1c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723877161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3723877161
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2406889035
Short name T870
Test name
Test status
Simulation time 92372108659 ps
CPU time 788.32 seconds
Started Jul 03 05:43:42 PM PDT 24
Finished Jul 03 05:56:51 PM PDT 24
Peak memory 200004 kb
Host smart-af5f413a-7b61-4b50-b1cf-22cb4b778a1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2406889035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2406889035
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3976626464
Short name T455
Test name
Test status
Simulation time 3153597366 ps
CPU time 5.4 seconds
Started Jul 03 05:43:50 PM PDT 24
Finished Jul 03 05:43:57 PM PDT 24
Peak memory 199584 kb
Host smart-3620fb3c-5911-44c4-9358-972bf15a2f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976626464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3976626464
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.476048049
Short name T881
Test name
Test status
Simulation time 12257849053 ps
CPU time 180.01 seconds
Started Jul 03 05:43:52 PM PDT 24
Finished Jul 03 05:46:53 PM PDT 24
Peak memory 199988 kb
Host smart-c25215c0-723b-4f05-aad8-79555848a2e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476048049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.476048049
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2980340948
Short name T658
Test name
Test status
Simulation time 4671284105 ps
CPU time 34.26 seconds
Started Jul 03 05:43:32 PM PDT 24
Finished Jul 03 05:44:06 PM PDT 24
Peak memory 199196 kb
Host smart-f46a8ee2-1047-4306-b2ca-2977b61e3511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980340948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2980340948
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2931389806
Short name T142
Test name
Test status
Simulation time 30127251666 ps
CPU time 62.21 seconds
Started Jul 03 05:43:36 PM PDT 24
Finished Jul 03 05:44:39 PM PDT 24
Peak memory 199896 kb
Host smart-1ca24cff-4027-4c72-89fc-0bf639fe9b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931389806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2931389806
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.13738243
Short name T445
Test name
Test status
Simulation time 33488101931 ps
CPU time 48.17 seconds
Started Jul 03 05:43:44 PM PDT 24
Finished Jul 03 05:44:33 PM PDT 24
Peak memory 196704 kb
Host smart-3b8fff82-0058-4c68-b2ce-1d3b1309a5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13738243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.13738243
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.4039491782
Short name T813
Test name
Test status
Simulation time 5547504873 ps
CPU time 6.27 seconds
Started Jul 03 05:43:49 PM PDT 24
Finished Jul 03 05:43:56 PM PDT 24
Peak memory 199888 kb
Host smart-ea79207e-94e8-49da-921f-ba3904d4389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039491782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.4039491782
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1014731358
Short name T898
Test name
Test status
Simulation time 15072858530 ps
CPU time 6.58 seconds
Started Jul 03 05:43:44 PM PDT 24
Finished Jul 03 05:43:52 PM PDT 24
Peak memory 199864 kb
Host smart-ea6e9cb6-3211-40f8-ace6-af6737b55391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014731358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1014731358
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1627875152
Short name T620
Test name
Test status
Simulation time 117317622382 ps
CPU time 66.81 seconds
Started Jul 03 05:43:51 PM PDT 24
Finished Jul 03 05:44:59 PM PDT 24
Peak memory 199992 kb
Host smart-b1fa29d0-ca0c-4f38-b79f-030fe46603cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627875152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1627875152
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2138109094
Short name T135
Test name
Test status
Simulation time 112414902630 ps
CPU time 46.94 seconds
Started Jul 03 05:46:09 PM PDT 24
Finished Jul 03 05:46:56 PM PDT 24
Peak memory 199796 kb
Host smart-b03e42a2-f11b-4b79-886e-79c4a61de845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138109094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2138109094
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1053982658
Short name T861
Test name
Test status
Simulation time 151228180919 ps
CPU time 69.8 seconds
Started Jul 03 05:46:08 PM PDT 24
Finished Jul 03 05:47:19 PM PDT 24
Peak memory 200012 kb
Host smart-5d6c74cb-595b-4f1f-a8c7-e891ed323502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053982658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1053982658
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2850611111
Short name T344
Test name
Test status
Simulation time 48285904735 ps
CPU time 35.41 seconds
Started Jul 03 05:46:09 PM PDT 24
Finished Jul 03 05:46:44 PM PDT 24
Peak memory 199976 kb
Host smart-a1016f96-3308-47e2-93a1-85ab880a4601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850611111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2850611111
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2807989129
Short name T1024
Test name
Test status
Simulation time 98496119861 ps
CPU time 34.66 seconds
Started Jul 03 05:46:08 PM PDT 24
Finished Jul 03 05:46:43 PM PDT 24
Peak memory 199932 kb
Host smart-fccad42c-e7ee-4808-96a5-b412ccf30d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807989129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2807989129
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.963080891
Short name T624
Test name
Test status
Simulation time 129505126254 ps
CPU time 47.67 seconds
Started Jul 03 05:46:09 PM PDT 24
Finished Jul 03 05:46:57 PM PDT 24
Peak memory 199972 kb
Host smart-3ad074a8-dc6d-4066-a1f1-b049dba15f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963080891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.963080891
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2785169920
Short name T536
Test name
Test status
Simulation time 42923273285 ps
CPU time 89.13 seconds
Started Jul 03 05:46:11 PM PDT 24
Finished Jul 03 05:47:41 PM PDT 24
Peak memory 199996 kb
Host smart-17cf53a0-8c43-4e91-810e-12a3efd0828f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785169920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2785169920
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2744020856
Short name T974
Test name
Test status
Simulation time 264412095220 ps
CPU time 24.1 seconds
Started Jul 03 05:46:09 PM PDT 24
Finished Jul 03 05:46:33 PM PDT 24
Peak memory 199864 kb
Host smart-6036c38e-985c-4cdd-8c94-7c49f9321fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744020856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2744020856
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3682777783
Short name T981
Test name
Test status
Simulation time 81801545615 ps
CPU time 218.72 seconds
Started Jul 03 05:46:10 PM PDT 24
Finished Jul 03 05:49:50 PM PDT 24
Peak memory 199916 kb
Host smart-3d7beabc-0fa5-43e6-853a-0c58e4053dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682777783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3682777783
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1724716843
Short name T904
Test name
Test status
Simulation time 24002512977 ps
CPU time 10.79 seconds
Started Jul 03 05:46:09 PM PDT 24
Finished Jul 03 05:46:20 PM PDT 24
Peak memory 199908 kb
Host smart-977f862f-610e-4921-a721-820ba06d48f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724716843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1724716843
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1615834502
Short name T1043
Test name
Test status
Simulation time 20645712 ps
CPU time 0.54 seconds
Started Jul 03 05:43:44 PM PDT 24
Finished Jul 03 05:43:45 PM PDT 24
Peak memory 195256 kb
Host smart-562f410f-1f7d-4b34-b3f5-9926f65b891e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615834502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1615834502
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3929985265
Short name T993
Test name
Test status
Simulation time 356276740003 ps
CPU time 38.14 seconds
Started Jul 03 05:43:53 PM PDT 24
Finished Jul 03 05:44:32 PM PDT 24
Peak memory 199672 kb
Host smart-8c870d7b-346c-42df-9c7d-b94b00a42e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929985265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3929985265
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1108258208
Short name T568
Test name
Test status
Simulation time 106619581760 ps
CPU time 107.44 seconds
Started Jul 03 05:43:53 PM PDT 24
Finished Jul 03 05:45:41 PM PDT 24
Peak memory 199992 kb
Host smart-9b296bfb-d5fb-4aee-964d-10ab6797932c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108258208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1108258208
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3444880265
Short name T753
Test name
Test status
Simulation time 71054238311 ps
CPU time 122.97 seconds
Started Jul 03 05:43:52 PM PDT 24
Finished Jul 03 05:45:55 PM PDT 24
Peak memory 199924 kb
Host smart-8fd8c6f9-b16e-4917-b4b8-44518442d2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444880265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3444880265
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3688016967
Short name T921
Test name
Test status
Simulation time 13930181653 ps
CPU time 22.72 seconds
Started Jul 03 05:43:47 PM PDT 24
Finished Jul 03 05:44:11 PM PDT 24
Peak memory 199604 kb
Host smart-d3211e49-3e45-4185-85b1-f1875d362479
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688016967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3688016967
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3284855050
Short name T930
Test name
Test status
Simulation time 98145061776 ps
CPU time 566.69 seconds
Started Jul 03 05:43:50 PM PDT 24
Finished Jul 03 05:53:18 PM PDT 24
Peak memory 199944 kb
Host smart-178f2fde-8f0e-4866-bf64-fc9a06619ec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3284855050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3284855050
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3996964318
Short name T997
Test name
Test status
Simulation time 11765478137 ps
CPU time 19.91 seconds
Started Jul 03 05:43:48 PM PDT 24
Finished Jul 03 05:44:08 PM PDT 24
Peak memory 198676 kb
Host smart-496c406e-f75b-423d-8fbe-2ee2a746aae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996964318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3996964318
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.2064556348
Short name T885
Test name
Test status
Simulation time 8779999988 ps
CPU time 136.21 seconds
Started Jul 03 05:43:51 PM PDT 24
Finished Jul 03 05:46:08 PM PDT 24
Peak memory 200004 kb
Host smart-4f445b42-009b-4403-8184-3d3405036338
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064556348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2064556348
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2322206448
Short name T731
Test name
Test status
Simulation time 1402664002 ps
CPU time 1.95 seconds
Started Jul 03 05:43:59 PM PDT 24
Finished Jul 03 05:44:02 PM PDT 24
Peak memory 198252 kb
Host smart-e13386b2-6fba-48ba-b8da-efd4e024089a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322206448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2322206448
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2510210741
Short name T895
Test name
Test status
Simulation time 8189731326 ps
CPU time 14.04 seconds
Started Jul 03 05:43:53 PM PDT 24
Finished Jul 03 05:44:08 PM PDT 24
Peak memory 199952 kb
Host smart-23a1e9a2-9bfe-47ea-b11c-bcc31be0922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510210741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2510210741
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.4091365558
Short name T984
Test name
Test status
Simulation time 2773038302 ps
CPU time 4.77 seconds
Started Jul 03 05:43:52 PM PDT 24
Finished Jul 03 05:43:57 PM PDT 24
Peak memory 195968 kb
Host smart-6082b63d-7870-4d0e-be86-96d81dd07bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091365558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4091365558
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2627491247
Short name T464
Test name
Test status
Simulation time 736974415 ps
CPU time 1.26 seconds
Started Jul 03 05:43:45 PM PDT 24
Finished Jul 03 05:43:47 PM PDT 24
Peak memory 198364 kb
Host smart-09b40569-bdbf-4cfe-922e-5701671ee94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627491247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2627491247
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2802369727
Short name T157
Test name
Test status
Simulation time 916367591484 ps
CPU time 145.67 seconds
Started Jul 03 05:43:51 PM PDT 24
Finished Jul 03 05:46:18 PM PDT 24
Peak memory 199928 kb
Host smart-70ac51e4-004a-43d4-a0e2-4055656a64d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802369727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2802369727
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.612649125
Short name T840
Test name
Test status
Simulation time 294239484205 ps
CPU time 560.45 seconds
Started Jul 03 05:43:50 PM PDT 24
Finished Jul 03 05:53:12 PM PDT 24
Peak memory 216472 kb
Host smart-b249b3ae-5100-436b-b8b5-4b191b1e7046
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612649125 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.612649125
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1307638350
Short name T384
Test name
Test status
Simulation time 6082294050 ps
CPU time 9.42 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:44:08 PM PDT 24
Peak memory 199500 kb
Host smart-f1b85183-43cc-4332-9af1-a7e7aefd8248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307638350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1307638350
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2618489879
Short name T975
Test name
Test status
Simulation time 46053755848 ps
CPU time 70.4 seconds
Started Jul 03 05:43:49 PM PDT 24
Finished Jul 03 05:45:00 PM PDT 24
Peak memory 199892 kb
Host smart-c8a9dcda-9907-496d-bc8a-526d057e5bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618489879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2618489879
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.203267061
Short name T256
Test name
Test status
Simulation time 168555587275 ps
CPU time 82.55 seconds
Started Jul 03 05:46:12 PM PDT 24
Finished Jul 03 05:47:35 PM PDT 24
Peak memory 199944 kb
Host smart-b7cad692-17e5-45ba-bdbf-bfb5b6d29905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203267061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.203267061
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3597342251
Short name T203
Test name
Test status
Simulation time 51033487028 ps
CPU time 53.65 seconds
Started Jul 03 05:46:10 PM PDT 24
Finished Jul 03 05:47:04 PM PDT 24
Peak memory 199976 kb
Host smart-fcd18b6b-caee-4a49-90bb-c22e4ae3dd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597342251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3597342251
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.4212138753
Short name T432
Test name
Test status
Simulation time 5848488321 ps
CPU time 9.94 seconds
Started Jul 03 05:46:14 PM PDT 24
Finished Jul 03 05:46:24 PM PDT 24
Peak memory 198612 kb
Host smart-d9b3f779-de16-42f1-aa42-1c6cc079da0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212138753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.4212138753
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.941435737
Short name T199
Test name
Test status
Simulation time 115859263455 ps
CPU time 33.93 seconds
Started Jul 03 05:46:11 PM PDT 24
Finished Jul 03 05:46:46 PM PDT 24
Peak memory 199976 kb
Host smart-290c4457-107e-458a-a98a-e03e7f5f918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941435737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.941435737
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1160527077
Short name T127
Test name
Test status
Simulation time 121469316874 ps
CPU time 45.9 seconds
Started Jul 03 05:46:15 PM PDT 24
Finished Jul 03 05:47:01 PM PDT 24
Peak memory 199884 kb
Host smart-74c5aba7-d2a8-4800-8a39-b55b48dcb991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160527077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1160527077
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1839544060
Short name T473
Test name
Test status
Simulation time 143718206165 ps
CPU time 53.92 seconds
Started Jul 03 05:46:14 PM PDT 24
Finished Jul 03 05:47:08 PM PDT 24
Peak memory 199952 kb
Host smart-778c841a-40b9-456f-86bd-b0ee00513c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839544060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1839544060
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.955841060
Short name T711
Test name
Test status
Simulation time 87552639842 ps
CPU time 18.52 seconds
Started Jul 03 05:46:14 PM PDT 24
Finished Jul 03 05:46:32 PM PDT 24
Peak memory 199880 kb
Host smart-ddd005f7-fd35-4ef1-b839-07cf4068cc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955841060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.955841060
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1603921880
Short name T208
Test name
Test status
Simulation time 10310830484 ps
CPU time 21.2 seconds
Started Jul 03 05:46:14 PM PDT 24
Finished Jul 03 05:46:35 PM PDT 24
Peak memory 199988 kb
Host smart-be3064f5-736f-4064-955f-1a2593c046d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603921880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1603921880
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.115873564
Short name T849
Test name
Test status
Simulation time 14246412583 ps
CPU time 11.49 seconds
Started Jul 03 05:46:12 PM PDT 24
Finished Jul 03 05:46:24 PM PDT 24
Peak memory 199804 kb
Host smart-59c6af89-efeb-41d7-843e-d525641a7df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115873564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.115873564
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1764046185
Short name T286
Test name
Test status
Simulation time 51784895360 ps
CPU time 22.77 seconds
Started Jul 03 05:46:11 PM PDT 24
Finished Jul 03 05:46:34 PM PDT 24
Peak memory 199908 kb
Host smart-305d324e-cf07-41b5-90fd-ccef938029fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764046185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1764046185
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3070573616
Short name T357
Test name
Test status
Simulation time 23313256 ps
CPU time 0.56 seconds
Started Jul 03 05:43:57 PM PDT 24
Finished Jul 03 05:43:58 PM PDT 24
Peak memory 195328 kb
Host smart-f0214aa7-4173-4660-8e83-f1785b862889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070573616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3070573616
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3793720
Short name T627
Test name
Test status
Simulation time 64112889499 ps
CPU time 20.13 seconds
Started Jul 03 05:43:52 PM PDT 24
Finished Jul 03 05:44:13 PM PDT 24
Peak memory 200012 kb
Host smart-d38555c8-5cc2-496e-904d-dd64fc35ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3793720
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.340521404
Short name T538
Test name
Test status
Simulation time 120048080067 ps
CPU time 190.5 seconds
Started Jul 03 05:43:54 PM PDT 24
Finished Jul 03 05:47:05 PM PDT 24
Peak memory 199876 kb
Host smart-6d36afee-feef-4cb9-bebb-41dbc12b650f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340521404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.340521404
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2489336153
Short name T171
Test name
Test status
Simulation time 122361056016 ps
CPU time 170.97 seconds
Started Jul 03 05:43:57 PM PDT 24
Finished Jul 03 05:46:48 PM PDT 24
Peak memory 199864 kb
Host smart-90acdd1e-f5c6-47d8-bc16-876145ef907a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489336153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2489336153
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1906954112
Short name T554
Test name
Test status
Simulation time 113455093928 ps
CPU time 81.64 seconds
Started Jul 03 05:43:51 PM PDT 24
Finished Jul 03 05:45:13 PM PDT 24
Peak memory 195956 kb
Host smart-19539567-87b3-4f39-b841-db5f486c5fc2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906954112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1906954112
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1133023785
Short name T790
Test name
Test status
Simulation time 30977084659 ps
CPU time 274.75 seconds
Started Jul 03 05:43:49 PM PDT 24
Finished Jul 03 05:48:25 PM PDT 24
Peak memory 200008 kb
Host smart-8b7cdecc-f7c5-486c-a403-621b174461ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1133023785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1133023785
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1637615497
Short name T447
Test name
Test status
Simulation time 7851486063 ps
CPU time 13.86 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:14 PM PDT 24
Peak memory 199396 kb
Host smart-81a8cc4b-b31d-492b-8479-8c63995952c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637615497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1637615497
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3130403918
Short name T296
Test name
Test status
Simulation time 29518332595 ps
CPU time 42.53 seconds
Started Jul 03 05:44:03 PM PDT 24
Finished Jul 03 05:44:45 PM PDT 24
Peak memory 199996 kb
Host smart-ba2e9a89-18b2-4100-aa9e-0b3b4aa55f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130403918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3130403918
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3388396492
Short name T798
Test name
Test status
Simulation time 10473984419 ps
CPU time 588.69 seconds
Started Jul 03 05:43:47 PM PDT 24
Finished Jul 03 05:53:36 PM PDT 24
Peak memory 199972 kb
Host smart-619d3e5e-d5e4-4869-8dc9-b16148df348e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388396492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3388396492
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1401790249
Short name T378
Test name
Test status
Simulation time 2942679974 ps
CPU time 21.92 seconds
Started Jul 03 05:43:46 PM PDT 24
Finished Jul 03 05:44:08 PM PDT 24
Peak memory 199468 kb
Host smart-253bf245-12c3-4c7b-a012-16dc4d9ef4d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401790249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1401790249
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1519470846
Short name T138
Test name
Test status
Simulation time 94658573536 ps
CPU time 58.73 seconds
Started Jul 03 05:43:51 PM PDT 24
Finished Jul 03 05:44:50 PM PDT 24
Peak memory 199940 kb
Host smart-4fe702c7-0831-42a3-b606-972f3180b508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519470846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1519470846
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2322807294
Short name T397
Test name
Test status
Simulation time 2060441024 ps
CPU time 3.72 seconds
Started Jul 03 05:43:57 PM PDT 24
Finished Jul 03 05:44:02 PM PDT 24
Peak memory 195480 kb
Host smart-b53077c1-ae26-4161-9eba-0a8a5e35679b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322807294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2322807294
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3401545252
Short name T1005
Test name
Test status
Simulation time 5664080209 ps
CPU time 4.65 seconds
Started Jul 03 05:43:51 PM PDT 24
Finished Jul 03 05:43:56 PM PDT 24
Peak memory 199616 kb
Host smart-5c79bf6c-ed37-4e94-8400-35336c443bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401545252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3401545252
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1294017213
Short name T29
Test name
Test status
Simulation time 89084721642 ps
CPU time 596.38 seconds
Started Jul 03 05:43:47 PM PDT 24
Finished Jul 03 05:53:44 PM PDT 24
Peak memory 216456 kb
Host smart-44e2ff65-f0c7-4e15-a18e-c1be5af2835b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294017213 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1294017213
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.467098619
Short name T1002
Test name
Test status
Simulation time 7904335727 ps
CPU time 7.76 seconds
Started Jul 03 05:43:56 PM PDT 24
Finished Jul 03 05:44:04 PM PDT 24
Peak memory 199172 kb
Host smart-ca656431-3692-4c07-9722-a7bbc28c9b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467098619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.467098619
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1363477507
Short name T810
Test name
Test status
Simulation time 12658575136 ps
CPU time 12.24 seconds
Started Jul 03 05:43:50 PM PDT 24
Finished Jul 03 05:44:03 PM PDT 24
Peak memory 199996 kb
Host smart-4a00ce2f-1bf7-4cd3-8d35-c43a1e5e2e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363477507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1363477507
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2178360694
Short name T184
Test name
Test status
Simulation time 111615839100 ps
CPU time 47 seconds
Started Jul 03 05:46:12 PM PDT 24
Finished Jul 03 05:46:59 PM PDT 24
Peak memory 199988 kb
Host smart-9876aaac-83d8-48b5-aabb-0648176ee0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178360694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2178360694
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1669150018
Short name T202
Test name
Test status
Simulation time 19067243747 ps
CPU time 27.92 seconds
Started Jul 03 05:46:12 PM PDT 24
Finished Jul 03 05:46:40 PM PDT 24
Peak memory 199892 kb
Host smart-5d7ee9fe-1616-4463-a30c-f3fa29e1db41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669150018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1669150018
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.117424191
Short name T166
Test name
Test status
Simulation time 110873263477 ps
CPU time 40.38 seconds
Started Jul 03 05:46:17 PM PDT 24
Finished Jul 03 05:46:57 PM PDT 24
Peak memory 199968 kb
Host smart-a012e59d-fd84-492c-9192-2b21a73238a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117424191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.117424191
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2477361244
Short name T831
Test name
Test status
Simulation time 197852782620 ps
CPU time 284.52 seconds
Started Jul 03 05:46:16 PM PDT 24
Finished Jul 03 05:51:01 PM PDT 24
Peak memory 199992 kb
Host smart-be9d9c9b-1b16-48ca-b5ff-3cd37bcba008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477361244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2477361244
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1821006709
Short name T134
Test name
Test status
Simulation time 59328847988 ps
CPU time 22.37 seconds
Started Jul 03 05:46:16 PM PDT 24
Finished Jul 03 05:46:39 PM PDT 24
Peak memory 199804 kb
Host smart-d24a754f-991d-483d-a75b-1c66b4ea4f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821006709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1821006709
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1216387156
Short name T728
Test name
Test status
Simulation time 91572342835 ps
CPU time 36.7 seconds
Started Jul 03 05:46:15 PM PDT 24
Finished Jul 03 05:46:53 PM PDT 24
Peak memory 199980 kb
Host smart-256c62ae-8e98-4a25-9ce0-53fd298f2cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216387156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1216387156
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2664488897
Short name T902
Test name
Test status
Simulation time 159712064640 ps
CPU time 337.56 seconds
Started Jul 03 05:46:15 PM PDT 24
Finished Jul 03 05:51:52 PM PDT 24
Peak memory 199860 kb
Host smart-5a9808e1-c92c-4435-8bdd-dabbb9a451fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664488897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2664488897
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.315323395
Short name T348
Test name
Test status
Simulation time 36259744618 ps
CPU time 16.98 seconds
Started Jul 03 05:46:17 PM PDT 24
Finished Jul 03 05:46:35 PM PDT 24
Peak memory 199976 kb
Host smart-f537a7e9-a8d5-4e17-9a91-4e37de0c25cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315323395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.315323395
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.550902343
Short name T954
Test name
Test status
Simulation time 73335725783 ps
CPU time 73.43 seconds
Started Jul 03 05:46:17 PM PDT 24
Finished Jul 03 05:47:31 PM PDT 24
Peak memory 199920 kb
Host smart-2368f926-6751-4d10-8a21-0f5036fb2385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550902343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.550902343
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3727876739
Short name T920
Test name
Test status
Simulation time 25108260 ps
CPU time 0.56 seconds
Started Jul 03 05:42:57 PM PDT 24
Finished Jul 03 05:42:58 PM PDT 24
Peak memory 195548 kb
Host smart-62f2b6d9-0aa0-4da0-b2b8-d7152e886ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727876739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3727876739
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1515961024
Short name T119
Test name
Test status
Simulation time 139448551930 ps
CPU time 55.13 seconds
Started Jul 03 05:42:41 PM PDT 24
Finished Jul 03 05:43:38 PM PDT 24
Peak memory 199968 kb
Host smart-2a807096-f93d-46b0-96a5-9bdccda57242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515961024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1515961024
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3958280586
Short name T1081
Test name
Test status
Simulation time 242875075139 ps
CPU time 179.41 seconds
Started Jul 03 05:42:49 PM PDT 24
Finished Jul 03 05:45:49 PM PDT 24
Peak memory 199952 kb
Host smart-d549f0c3-b641-4e46-b1d9-9c58915fd954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958280586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3958280586
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1100195761
Short name T878
Test name
Test status
Simulation time 14886954538 ps
CPU time 24.64 seconds
Started Jul 03 05:42:39 PM PDT 24
Finished Jul 03 05:43:09 PM PDT 24
Peak memory 199856 kb
Host smart-c22b8c03-9ebc-439d-add1-7d0474abe578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100195761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1100195761
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1424460604
Short name T478
Test name
Test status
Simulation time 13246527889 ps
CPU time 6.81 seconds
Started Jul 03 05:42:40 PM PDT 24
Finished Jul 03 05:42:48 PM PDT 24
Peak memory 196956 kb
Host smart-b2eff087-42f2-49b0-9993-80a6b71bc3dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424460604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1424460604
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.758995895
Short name T677
Test name
Test status
Simulation time 68283373188 ps
CPU time 126.67 seconds
Started Jul 03 05:42:59 PM PDT 24
Finished Jul 03 05:45:06 PM PDT 24
Peak memory 199900 kb
Host smart-543d574d-6f31-45cd-90c0-f9b52d98f679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758995895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.758995895
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1258409728
Short name T10
Test name
Test status
Simulation time 9083847841 ps
CPU time 6.34 seconds
Started Jul 03 05:42:46 PM PDT 24
Finished Jul 03 05:42:52 PM PDT 24
Peak memory 199788 kb
Host smart-2850e74b-ddc6-4ce0-82bd-34470b156673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258409728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1258409728
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2224343856
Short name T565
Test name
Test status
Simulation time 3510087896 ps
CPU time 5.86 seconds
Started Jul 03 05:42:52 PM PDT 24
Finished Jul 03 05:42:58 PM PDT 24
Peak memory 199088 kb
Host smart-97414f6b-c7ec-4b3d-99b0-c6f32e51d1d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224343856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2224343856
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3209615585
Short name T766
Test name
Test status
Simulation time 159373833321 ps
CPU time 326 seconds
Started Jul 03 05:43:03 PM PDT 24
Finished Jul 03 05:48:30 PM PDT 24
Peak memory 199944 kb
Host smart-b731a00d-8253-4f57-92a8-630eed13752b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209615585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3209615585
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3308674679
Short name T37
Test name
Test status
Simulation time 3798111382 ps
CPU time 6.1 seconds
Started Jul 03 05:42:50 PM PDT 24
Finished Jul 03 05:42:57 PM PDT 24
Peak memory 196420 kb
Host smart-088570aa-e252-4fce-8f2e-b3fa3fb7b0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308674679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3308674679
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2669639376
Short name T26
Test name
Test status
Simulation time 131176557 ps
CPU time 0.74 seconds
Started Jul 03 05:43:00 PM PDT 24
Finished Jul 03 05:43:01 PM PDT 24
Peak memory 218328 kb
Host smart-c9b226c2-0a3e-4364-a76c-c64a80694103
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669639376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2669639376
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3319899548
Short name T916
Test name
Test status
Simulation time 6051524266 ps
CPU time 11.47 seconds
Started Jul 03 05:43:01 PM PDT 24
Finished Jul 03 05:43:13 PM PDT 24
Peak memory 199944 kb
Host smart-14917e3d-0b18-4d71-bf80-5c5dbaa40b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319899548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3319899548
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.301908978
Short name T549
Test name
Test status
Simulation time 54984511030 ps
CPU time 607.85 seconds
Started Jul 03 05:42:57 PM PDT 24
Finished Jul 03 05:53:05 PM PDT 24
Peak memory 216556 kb
Host smart-8d70b039-d993-44ef-bfe1-e742958758dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301908978 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.301908978
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1725457748
Short name T713
Test name
Test status
Simulation time 1216756773 ps
CPU time 3.2 seconds
Started Jul 03 05:42:44 PM PDT 24
Finished Jul 03 05:42:48 PM PDT 24
Peak memory 199816 kb
Host smart-959e7c13-0d7e-4ddc-a0db-470ea324fae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725457748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1725457748
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3833111276
Short name T446
Test name
Test status
Simulation time 102168694948 ps
CPU time 39.95 seconds
Started Jul 03 05:42:46 PM PDT 24
Finished Jul 03 05:43:26 PM PDT 24
Peak memory 199868 kb
Host smart-77a35801-2dfa-46cb-a1f4-7788b5eed25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833111276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3833111276
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1844584694
Short name T1019
Test name
Test status
Simulation time 11819531 ps
CPU time 0.55 seconds
Started Jul 03 05:43:56 PM PDT 24
Finished Jul 03 05:43:57 PM PDT 24
Peak memory 195264 kb
Host smart-63f6bcb9-97c2-441e-bf4b-832acfdc147d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844584694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1844584694
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3206264239
Short name T288
Test name
Test status
Simulation time 355902001552 ps
CPU time 40.42 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:44:40 PM PDT 24
Peak memory 199976 kb
Host smart-e7182ddc-dcc5-4553-bad0-8d13b74cd93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206264239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3206264239
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.4142212955
Short name T462
Test name
Test status
Simulation time 64288020578 ps
CPU time 49.16 seconds
Started Jul 03 05:43:48 PM PDT 24
Finished Jul 03 05:44:38 PM PDT 24
Peak memory 199944 kb
Host smart-71e3ed8f-038c-4ffe-9c15-02304e205454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142212955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4142212955
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1162847515
Short name T201
Test name
Test status
Simulation time 119007830101 ps
CPU time 183.61 seconds
Started Jul 03 05:43:56 PM PDT 24
Finished Jul 03 05:46:59 PM PDT 24
Peak memory 199892 kb
Host smart-f653dc34-0493-4c05-a96c-76d8857f40c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162847515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1162847515
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4058202559
Short name T569
Test name
Test status
Simulation time 51523974870 ps
CPU time 23.35 seconds
Started Jul 03 05:43:55 PM PDT 24
Finished Jul 03 05:44:18 PM PDT 24
Peak memory 199844 kb
Host smart-9a2b1430-2eda-436c-89f7-f98126f6ad17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058202559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4058202559
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.525789972
Short name T561
Test name
Test status
Simulation time 79916608265 ps
CPU time 446.47 seconds
Started Jul 03 05:43:54 PM PDT 24
Finished Jul 03 05:51:21 PM PDT 24
Peak memory 199912 kb
Host smart-418fd239-3aeb-4d13-bd44-b429b9ffba00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525789972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.525789972
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3560826170
Short name T1075
Test name
Test status
Simulation time 4495849480 ps
CPU time 9.35 seconds
Started Jul 03 05:43:59 PM PDT 24
Finished Jul 03 05:44:09 PM PDT 24
Peak memory 198372 kb
Host smart-6233add7-5ef5-4931-ba54-6615e41f8336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560826170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3560826170
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.1103467315
Short name T1042
Test name
Test status
Simulation time 14591980760 ps
CPU time 75.8 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:45:15 PM PDT 24
Peak memory 199976 kb
Host smart-42884541-c9d8-4fd3-baab-d8ff16820643
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103467315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1103467315
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2106120011
Short name T431
Test name
Test status
Simulation time 1899649199 ps
CPU time 6.2 seconds
Started Jul 03 05:43:59 PM PDT 24
Finished Jul 03 05:44:06 PM PDT 24
Peak memory 198136 kb
Host smart-abe4e399-479f-4632-ac06-55ed2ede22fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2106120011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2106120011
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1611247699
Short name T1030
Test name
Test status
Simulation time 165058510558 ps
CPU time 31.33 seconds
Started Jul 03 05:43:51 PM PDT 24
Finished Jul 03 05:44:23 PM PDT 24
Peak memory 199964 kb
Host smart-1c23dfd3-51c6-49ec-a074-134161b69c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611247699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1611247699
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.260623352
Short name T369
Test name
Test status
Simulation time 4870596853 ps
CPU time 2.57 seconds
Started Jul 03 05:43:51 PM PDT 24
Finished Jul 03 05:43:55 PM PDT 24
Peak memory 196052 kb
Host smart-b55e4fa1-f114-4b0a-8a89-1e1c4923dc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260623352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.260623352
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3265626890
Short name T364
Test name
Test status
Simulation time 506264350 ps
CPU time 1.56 seconds
Started Jul 03 05:43:52 PM PDT 24
Finished Jul 03 05:43:54 PM PDT 24
Peak memory 198212 kb
Host smart-064eea8d-5971-4f06-908e-c736373b6daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265626890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3265626890
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2458003410
Short name T693
Test name
Test status
Simulation time 111433186742 ps
CPU time 167.58 seconds
Started Jul 03 05:43:51 PM PDT 24
Finished Jul 03 05:46:39 PM PDT 24
Peak memory 199976 kb
Host smart-14d20bcd-538f-416d-82e4-ce5bc20849e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458003410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2458003410
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.4039638735
Short name T508
Test name
Test status
Simulation time 1336965890 ps
CPU time 1.72 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:44:01 PM PDT 24
Peak memory 199496 kb
Host smart-3f070835-f442-410a-8575-793e88979252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039638735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.4039638735
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.724637410
Short name T343
Test name
Test status
Simulation time 45410350543 ps
CPU time 21.36 seconds
Started Jul 03 05:43:51 PM PDT 24
Finished Jul 03 05:44:13 PM PDT 24
Peak memory 199948 kb
Host smart-39acdd87-e170-4421-9ae6-f5a13868d116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724637410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.724637410
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2840481225
Short name T623
Test name
Test status
Simulation time 45532292 ps
CPU time 0.58 seconds
Started Jul 03 05:43:57 PM PDT 24
Finished Jul 03 05:43:58 PM PDT 24
Peak memory 195568 kb
Host smart-21791d9e-b8ed-4bb6-a90c-a1e4e326d63d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840481225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2840481225
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2649583738
Short name T907
Test name
Test status
Simulation time 194490346906 ps
CPU time 92.19 seconds
Started Jul 03 05:43:52 PM PDT 24
Finished Jul 03 05:45:25 PM PDT 24
Peak memory 199932 kb
Host smart-c6cf942f-8a08-4920-b3df-a9bd9dbb64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649583738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2649583738
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2193833411
Short name T141
Test name
Test status
Simulation time 20030221760 ps
CPU time 32.31 seconds
Started Jul 03 05:43:57 PM PDT 24
Finished Jul 03 05:44:30 PM PDT 24
Peak memory 199936 kb
Host smart-863044f6-bd6d-4fb5-8a99-be3caff9a5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193833411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2193833411
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.823106766
Short name T609
Test name
Test status
Simulation time 90647322049 ps
CPU time 76.19 seconds
Started Jul 03 05:43:59 PM PDT 24
Finished Jul 03 05:45:16 PM PDT 24
Peak memory 199964 kb
Host smart-88efec47-06ee-4259-a721-a97901814281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823106766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.823106766
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.81712372
Short name T506
Test name
Test status
Simulation time 14639548891 ps
CPU time 10.89 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:44:10 PM PDT 24
Peak memory 199604 kb
Host smart-0a5646a5-fbc5-4f81-8b12-ad5019001a47
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81712372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.81712372
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.4239313779
Short name T389
Test name
Test status
Simulation time 126423082965 ps
CPU time 307.5 seconds
Started Jul 03 05:43:54 PM PDT 24
Finished Jul 03 05:49:02 PM PDT 24
Peak memory 200008 kb
Host smart-daef7927-5118-4654-b7dc-344bf462dbd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239313779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.4239313779
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1841276015
Short name T510
Test name
Test status
Simulation time 13433144943 ps
CPU time 5.99 seconds
Started Jul 03 05:43:54 PM PDT 24
Finished Jul 03 05:44:01 PM PDT 24
Peak memory 199944 kb
Host smart-c7bd1511-6a21-4cac-a6e3-bec2420f4fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841276015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1841276015
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.2940196111
Short name T571
Test name
Test status
Simulation time 5912566619 ps
CPU time 65.06 seconds
Started Jul 03 05:44:01 PM PDT 24
Finished Jul 03 05:45:07 PM PDT 24
Peak memory 199928 kb
Host smart-fe0be416-cb2b-4039-a1be-366d70905dc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2940196111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2940196111
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2777915788
Short name T390
Test name
Test status
Simulation time 1377694491 ps
CPU time 5.81 seconds
Started Jul 03 05:44:01 PM PDT 24
Finished Jul 03 05:44:07 PM PDT 24
Peak memory 197668 kb
Host smart-738f257e-d0c5-4c6c-8fef-c230dabbd78b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2777915788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2777915788
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1160976717
Short name T495
Test name
Test status
Simulation time 173205897207 ps
CPU time 77.62 seconds
Started Jul 03 05:44:01 PM PDT 24
Finished Jul 03 05:45:19 PM PDT 24
Peak memory 199768 kb
Host smart-bf82f7ab-8ae7-4ca6-a559-490fec169aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160976717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1160976717
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.256098728
Short name T958
Test name
Test status
Simulation time 5778147841 ps
CPU time 2.99 seconds
Started Jul 03 05:43:53 PM PDT 24
Finished Jul 03 05:43:56 PM PDT 24
Peak memory 196072 kb
Host smart-7b3c47ff-73fa-432e-b6b4-abf3c5e1c85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256098728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.256098728
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.500366074
Short name T1092
Test name
Test status
Simulation time 502630950 ps
CPU time 2.18 seconds
Started Jul 03 05:43:52 PM PDT 24
Finished Jul 03 05:43:55 PM PDT 24
Peak memory 198512 kb
Host smart-2d930777-7e58-49d8-92b9-8020bb7e69d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500366074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.500366074
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2625603244
Short name T274
Test name
Test status
Simulation time 6267123351 ps
CPU time 16.15 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:17 PM PDT 24
Peak memory 199820 kb
Host smart-ac7a1efe-3b88-47a6-8207-6ecadfab8a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625603244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2625603244
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2625230861
Short name T562
Test name
Test status
Simulation time 87912253755 ps
CPU time 48.17 seconds
Started Jul 03 05:44:02 PM PDT 24
Finished Jul 03 05:44:50 PM PDT 24
Peak memory 199940 kb
Host smart-2641b745-c287-4ccc-a98a-8e6aecb9e279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625230861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2625230861
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2646945496
Short name T520
Test name
Test status
Simulation time 16628147 ps
CPU time 0.56 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:01 PM PDT 24
Peak memory 194936 kb
Host smart-a4d15c2e-08e0-43e4-b3e4-2c458d7813ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646945496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2646945496
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1958885281
Short name T489
Test name
Test status
Simulation time 36727057344 ps
CPU time 30.99 seconds
Started Jul 03 05:43:59 PM PDT 24
Finished Jul 03 05:44:31 PM PDT 24
Peak memory 199948 kb
Host smart-0d250c85-c671-48ec-9112-4fa8d43c6748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958885281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1958885281
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3773663819
Short name T1088
Test name
Test status
Simulation time 102280297046 ps
CPU time 41.84 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:42 PM PDT 24
Peak memory 199912 kb
Host smart-862225dd-e4c1-40c4-9eee-7aaf8a85634a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773663819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3773663819
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.2933905461
Short name T263
Test name
Test status
Simulation time 6478845761 ps
CPU time 4.96 seconds
Started Jul 03 05:43:59 PM PDT 24
Finished Jul 03 05:44:05 PM PDT 24
Peak memory 199924 kb
Host smart-74dcc511-77aa-434b-b3e8-057ea58c5fd1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933905461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2933905461
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_loopback.727811793
Short name T1085
Test name
Test status
Simulation time 5967255897 ps
CPU time 11.62 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:12 PM PDT 24
Peak memory 199844 kb
Host smart-69c2b068-8a8a-4e44-b5fb-7bd0f0a4d0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727811793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.727811793
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.4076590961
Short name T258
Test name
Test status
Simulation time 30163043214 ps
CPU time 356.7 seconds
Started Jul 03 05:44:01 PM PDT 24
Finished Jul 03 05:49:59 PM PDT 24
Peak memory 200008 kb
Host smart-f110222c-4452-4718-91b8-1269a0299de9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4076590961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4076590961
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3197706920
Short name T405
Test name
Test status
Simulation time 3282432964 ps
CPU time 22.41 seconds
Started Jul 03 05:43:59 PM PDT 24
Finished Jul 03 05:44:22 PM PDT 24
Peak memory 198212 kb
Host smart-6170dcf5-f819-4d0d-a53b-cc2df44362b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3197706920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3197706920
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3739190533
Short name T511
Test name
Test status
Simulation time 110086577064 ps
CPU time 54.19 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:44:53 PM PDT 24
Peak memory 199952 kb
Host smart-e428f02a-f0fa-4017-a654-0db1c4bdaef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739190533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3739190533
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2504738172
Short name T636
Test name
Test status
Simulation time 3738892715 ps
CPU time 1.82 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:03 PM PDT 24
Peak memory 196272 kb
Host smart-2592217c-2ec1-46c5-98ef-17671ede2452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504738172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2504738172
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3706308002
Short name T800
Test name
Test status
Simulation time 716106964 ps
CPU time 2.02 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:44:00 PM PDT 24
Peak memory 198728 kb
Host smart-b367a619-cfc0-4e5c-b0aa-3a210f174403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706308002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3706308002
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2203757667
Short name T744
Test name
Test status
Simulation time 244257829102 ps
CPU time 657.11 seconds
Started Jul 03 05:44:03 PM PDT 24
Finished Jul 03 05:55:01 PM PDT 24
Peak memory 199980 kb
Host smart-51e36fa2-a354-4a5c-af82-15e308a5ae1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203757667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2203757667
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3201315274
Short name T1057
Test name
Test status
Simulation time 2868187374 ps
CPU time 2.18 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:03 PM PDT 24
Peak memory 199412 kb
Host smart-a62fdd6a-9c1f-4bc4-b720-718981d1a230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201315274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3201315274
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.215096159
Short name T242
Test name
Test status
Simulation time 46231679236 ps
CPU time 30.62 seconds
Started Jul 03 05:44:01 PM PDT 24
Finished Jul 03 05:44:32 PM PDT 24
Peak memory 199968 kb
Host smart-946ff979-549e-4455-8fa4-8895992999a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215096159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.215096159
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2084085937
Short name T648
Test name
Test status
Simulation time 23205976 ps
CPU time 0.55 seconds
Started Jul 03 05:44:02 PM PDT 24
Finished Jul 03 05:44:03 PM PDT 24
Peak memory 194740 kb
Host smart-274402f2-c68a-4e87-95b0-7e69b07667f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084085937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2084085937
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2226682753
Short name T965
Test name
Test status
Simulation time 105176718405 ps
CPU time 157.86 seconds
Started Jul 03 05:43:57 PM PDT 24
Finished Jul 03 05:46:35 PM PDT 24
Peak memory 199824 kb
Host smart-e6532c1a-2c0b-4689-809e-6072a82d4d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226682753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2226682753
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2560249158
Short name T976
Test name
Test status
Simulation time 51808728155 ps
CPU time 11.89 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:12 PM PDT 24
Peak memory 199904 kb
Host smart-60f601f7-1697-402e-81ec-cf7e6b45cd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560249158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2560249158
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2813120082
Short name T214
Test name
Test status
Simulation time 123745777175 ps
CPU time 49.69 seconds
Started Jul 03 05:43:57 PM PDT 24
Finished Jul 03 05:44:48 PM PDT 24
Peak memory 200028 kb
Host smart-42e37010-5a15-414b-863d-d5480dd44894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813120082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2813120082
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2993161339
Short name T329
Test name
Test status
Simulation time 102020909018 ps
CPU time 39.43 seconds
Started Jul 03 05:43:59 PM PDT 24
Finished Jul 03 05:44:39 PM PDT 24
Peak memory 196052 kb
Host smart-ca86ccb7-87b4-4374-8b9d-9eadcb8fb15a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993161339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2993161339
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.931830789
Short name T396
Test name
Test status
Simulation time 74019840038 ps
CPU time 296.77 seconds
Started Jul 03 05:43:59 PM PDT 24
Finished Jul 03 05:48:56 PM PDT 24
Peak memory 199872 kb
Host smart-e3dd6945-487f-4d74-8e3a-fe6f8e07b543
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931830789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.931830789
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.31573975
Short name T376
Test name
Test status
Simulation time 2660372235 ps
CPU time 2.67 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:03 PM PDT 24
Peak memory 198664 kb
Host smart-65828c73-f423-463f-9561-899e875e8f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31573975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.31573975
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.3020657274
Short name T463
Test name
Test status
Simulation time 11609677055 ps
CPU time 323.58 seconds
Started Jul 03 05:43:57 PM PDT 24
Finished Jul 03 05:49:21 PM PDT 24
Peak memory 199976 kb
Host smart-c38b7671-f9f4-4ded-bdcd-d3ff0177ba16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020657274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3020657274
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.277240612
Short name T427
Test name
Test status
Simulation time 7114458734 ps
CPU time 31.68 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:44:30 PM PDT 24
Peak memory 199268 kb
Host smart-e6732da4-dab0-43d5-ac60-4481dc8d1c25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=277240612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.277240612
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3762988748
Short name T297
Test name
Test status
Simulation time 127295345769 ps
CPU time 71.4 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:45:11 PM PDT 24
Peak memory 199884 kb
Host smart-6efde2de-a875-4aed-9c69-240de61141ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762988748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3762988748
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3282205442
Short name T545
Test name
Test status
Simulation time 37326472242 ps
CPU time 49 seconds
Started Jul 03 05:43:55 PM PDT 24
Finished Jul 03 05:44:44 PM PDT 24
Peak memory 195876 kb
Host smart-0636a36a-da3e-4c77-9557-2e70c562f4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282205442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3282205442
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2584892187
Short name T665
Test name
Test status
Simulation time 5629947859 ps
CPU time 20.43 seconds
Started Jul 03 05:43:58 PM PDT 24
Finished Jul 03 05:44:19 PM PDT 24
Peak memory 199204 kb
Host smart-17992d2b-0bfa-4cc7-ac3e-b58fd7406855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584892187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2584892187
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1803832500
Short name T638
Test name
Test status
Simulation time 1152818058815 ps
CPU time 173.61 seconds
Started Jul 03 05:43:57 PM PDT 24
Finished Jul 03 05:46:52 PM PDT 24
Peak memory 199984 kb
Host smart-81147ab3-3374-41d5-8ec5-9b26c439d6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803832500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1803832500
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.642533293
Short name T672
Test name
Test status
Simulation time 7153570903 ps
CPU time 8.67 seconds
Started Jul 03 05:43:59 PM PDT 24
Finished Jul 03 05:44:08 PM PDT 24
Peak memory 199832 kb
Host smart-bc4de62e-cf24-4a2a-bc72-d4dec5f59568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642533293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.642533293
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.748596547
Short name T726
Test name
Test status
Simulation time 95743447311 ps
CPU time 177.59 seconds
Started Jul 03 05:43:57 PM PDT 24
Finished Jul 03 05:46:55 PM PDT 24
Peak memory 199864 kb
Host smart-0d233637-ab69-411a-9f2c-10d4d95c1203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748596547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.748596547
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1353544525
Short name T1094
Test name
Test status
Simulation time 11023091 ps
CPU time 0.58 seconds
Started Jul 03 05:44:04 PM PDT 24
Finished Jul 03 05:44:05 PM PDT 24
Peak memory 195324 kb
Host smart-4a6bb292-8023-4d34-9dcf-e3bb4041ea38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353544525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1353544525
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1963362091
Short name T488
Test name
Test status
Simulation time 123619423444 ps
CPU time 248.85 seconds
Started Jul 03 05:44:02 PM PDT 24
Finished Jul 03 05:48:11 PM PDT 24
Peak memory 199752 kb
Host smart-148fcc19-ad4e-4943-84ba-2f68cfcf488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963362091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1963362091
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3511019241
Short name T241
Test name
Test status
Simulation time 31103180801 ps
CPU time 47.65 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:49 PM PDT 24
Peak memory 199924 kb
Host smart-310d482b-e977-48a3-ac0b-22113d40a58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511019241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3511019241
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.282951871
Short name T36
Test name
Test status
Simulation time 12929079855 ps
CPU time 10.05 seconds
Started Jul 03 05:44:01 PM PDT 24
Finished Jul 03 05:44:11 PM PDT 24
Peak memory 199672 kb
Host smart-f6c3955c-990c-464b-9af4-c35529e7776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282951871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.282951871
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.852956240
Short name T33
Test name
Test status
Simulation time 13382160937 ps
CPU time 18.54 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:19 PM PDT 24
Peak memory 197296 kb
Host smart-74d2e2be-edbb-4827-8ca2-87ef8469e913
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852956240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.852956240
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2469398360
Short name T547
Test name
Test status
Simulation time 131386767064 ps
CPU time 1201.62 seconds
Started Jul 03 05:44:04 PM PDT 24
Finished Jul 03 06:04:06 PM PDT 24
Peak memory 200028 kb
Host smart-2f429905-79f8-4415-aa13-6538616db86e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2469398360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2469398360
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4006096434
Short name T383
Test name
Test status
Simulation time 7810004252 ps
CPU time 15.83 seconds
Started Jul 03 05:44:05 PM PDT 24
Finished Jul 03 05:44:21 PM PDT 24
Peak memory 198472 kb
Host smart-136541f3-1087-4db9-9b0f-73ae78dd31f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006096434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4006096434
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.2117966314
Short name T666
Test name
Test status
Simulation time 10774604410 ps
CPU time 148.98 seconds
Started Jul 03 05:44:03 PM PDT 24
Finished Jul 03 05:46:32 PM PDT 24
Peak memory 199996 kb
Host smart-30b4914e-3a16-4344-8a07-227b96611874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117966314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2117966314
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.4122485408
Short name T373
Test name
Test status
Simulation time 4461716223 ps
CPU time 8.46 seconds
Started Jul 03 05:44:03 PM PDT 24
Finished Jul 03 05:44:12 PM PDT 24
Peak memory 198096 kb
Host smart-e65c2f7f-fd66-4a5c-880e-3c88cd0bb4c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122485408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.4122485408
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.232411392
Short name T940
Test name
Test status
Simulation time 98358059919 ps
CPU time 34.79 seconds
Started Jul 03 05:44:07 PM PDT 24
Finished Jul 03 05:44:43 PM PDT 24
Peak memory 199948 kb
Host smart-52c0612d-e3db-45b3-9cc6-29181fd8df54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232411392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.232411392
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1737074852
Short name T688
Test name
Test status
Simulation time 1634777377 ps
CPU time 1.78 seconds
Started Jul 03 05:44:02 PM PDT 24
Finished Jul 03 05:44:04 PM PDT 24
Peak memory 195580 kb
Host smart-13a94f19-f12c-46f2-a1f1-3ae2a92331e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737074852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1737074852
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1103087377
Short name T1064
Test name
Test status
Simulation time 6246361199 ps
CPU time 9.21 seconds
Started Jul 03 05:44:03 PM PDT 24
Finished Jul 03 05:44:12 PM PDT 24
Peak memory 199324 kb
Host smart-dd0baffb-ddd0-44f4-8a94-290b536b9292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103087377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1103087377
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1023757052
Short name T872
Test name
Test status
Simulation time 387133760017 ps
CPU time 204.59 seconds
Started Jul 03 05:44:03 PM PDT 24
Finished Jul 03 05:47:28 PM PDT 24
Peak memory 199936 kb
Host smart-b4067055-7d5c-4d1d-a9f6-1bf5fb038efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023757052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1023757052
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1560283192
Short name T95
Test name
Test status
Simulation time 83595648963 ps
CPU time 150.24 seconds
Started Jul 03 05:44:01 PM PDT 24
Finished Jul 03 05:46:32 PM PDT 24
Peak memory 216584 kb
Host smart-58f91cf1-9887-4624-b640-139fbcfe1d00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560283192 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1560283192
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3199679540
Short name T635
Test name
Test status
Simulation time 1511616924 ps
CPU time 2.68 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:44:03 PM PDT 24
Peak memory 198604 kb
Host smart-4de390b0-3708-4e33-aece-b22a1b497ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199679540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3199679540
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1299731825
Short name T39
Test name
Test status
Simulation time 40799198306 ps
CPU time 76.42 seconds
Started Jul 03 05:44:00 PM PDT 24
Finished Jul 03 05:45:18 PM PDT 24
Peak memory 199980 kb
Host smart-50f8a7d5-8883-4cf3-8eab-14ea26a6cb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299731825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1299731825
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2664889004
Short name T717
Test name
Test status
Simulation time 25769029 ps
CPU time 0.57 seconds
Started Jul 03 05:44:06 PM PDT 24
Finished Jul 03 05:44:07 PM PDT 24
Peak memory 195608 kb
Host smart-3733cb2d-a267-41c5-8635-ffee00883860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664889004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2664889004
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1078988153
Short name T634
Test name
Test status
Simulation time 82308517812 ps
CPU time 185.1 seconds
Started Jul 03 05:44:02 PM PDT 24
Finished Jul 03 05:47:07 PM PDT 24
Peak memory 199888 kb
Host smart-79dd4442-9844-49a1-9d59-0754f28bb575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078988153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1078988153
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.4122316824
Short name T712
Test name
Test status
Simulation time 118674312420 ps
CPU time 48.67 seconds
Started Jul 03 05:44:07 PM PDT 24
Finished Jul 03 05:44:56 PM PDT 24
Peak memory 199944 kb
Host smart-bbbb3c7f-e98a-4573-b209-43f9d028cb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122316824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.4122316824
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.3448773557
Short name T412
Test name
Test status
Simulation time 3322835891 ps
CPU time 4.54 seconds
Started Jul 03 05:44:01 PM PDT 24
Finished Jul 03 05:44:06 PM PDT 24
Peak memory 199096 kb
Host smart-204c9929-84c0-4232-b79f-d06bbfe3ddf4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448773557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3448773557
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3804144773
Short name T667
Test name
Test status
Simulation time 142114684844 ps
CPU time 157.29 seconds
Started Jul 03 05:44:06 PM PDT 24
Finished Jul 03 05:46:43 PM PDT 24
Peak memory 199900 kb
Host smart-8de61dda-0967-42bf-a7a9-19f3e02c91ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804144773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3804144773
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.10309991
Short name T670
Test name
Test status
Simulation time 4135834954 ps
CPU time 2.55 seconds
Started Jul 03 05:44:06 PM PDT 24
Finished Jul 03 05:44:08 PM PDT 24
Peak memory 198424 kb
Host smart-a5460f85-edd2-4be7-b742-16b273b79b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10309991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.10309991
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.2269001227
Short name T681
Test name
Test status
Simulation time 22892687039 ps
CPU time 351.05 seconds
Started Jul 03 05:44:05 PM PDT 24
Finished Jul 03 05:49:56 PM PDT 24
Peak memory 200020 kb
Host smart-c369498a-9231-4c5e-be7f-4ab8c5a30398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2269001227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2269001227
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3833235147
Short name T1074
Test name
Test status
Simulation time 6586339723 ps
CPU time 7.16 seconds
Started Jul 03 05:44:01 PM PDT 24
Finished Jul 03 05:44:09 PM PDT 24
Peak memory 198148 kb
Host smart-d822c498-3c9b-4c86-a1b4-d2b1d55c8f77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3833235147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3833235147
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1978106773
Short name T137
Test name
Test status
Simulation time 119011659567 ps
CPU time 71.19 seconds
Started Jul 03 05:44:07 PM PDT 24
Finished Jul 03 05:45:19 PM PDT 24
Peak memory 199976 kb
Host smart-4c68d329-6162-49b2-a964-71bcb2206e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978106773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1978106773
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.972405013
Short name T617
Test name
Test status
Simulation time 3508399756 ps
CPU time 5.51 seconds
Started Jul 03 05:44:08 PM PDT 24
Finished Jul 03 05:44:14 PM PDT 24
Peak memory 196832 kb
Host smart-0d0a1ba5-8636-4422-b615-e7696cb815e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972405013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.972405013
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1154583996
Short name T322
Test name
Test status
Simulation time 11067215273 ps
CPU time 15.29 seconds
Started Jul 03 05:44:03 PM PDT 24
Finished Jul 03 05:44:19 PM PDT 24
Peak memory 199872 kb
Host smart-c86572ac-afa0-412b-944f-f3b1c8ff2eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154583996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1154583996
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2396737104
Short name T570
Test name
Test status
Simulation time 155351409379 ps
CPU time 494.77 seconds
Started Jul 03 05:44:06 PM PDT 24
Finished Jul 03 05:52:21 PM PDT 24
Peak memory 215804 kb
Host smart-15b17041-ce75-43b0-acc8-a8d2f0d512fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396737104 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2396737104
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2517027468
Short name T245
Test name
Test status
Simulation time 1274359963 ps
CPU time 1.43 seconds
Started Jul 03 05:44:03 PM PDT 24
Finished Jul 03 05:44:05 PM PDT 24
Peak memory 198456 kb
Host smart-cb078a0b-71f9-4ec7-9d75-cbbebc915819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517027468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2517027468
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3270215344
Short name T307
Test name
Test status
Simulation time 63163263703 ps
CPU time 116.18 seconds
Started Jul 03 05:44:01 PM PDT 24
Finished Jul 03 05:45:58 PM PDT 24
Peak memory 199872 kb
Host smart-56bd77d1-6961-4c84-a865-c7f142aba289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270215344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3270215344
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2883561915
Short name T22
Test name
Test status
Simulation time 14160632 ps
CPU time 0.63 seconds
Started Jul 03 05:44:08 PM PDT 24
Finished Jul 03 05:44:09 PM PDT 24
Peak memory 195336 kb
Host smart-1d79908d-01d8-4b6d-a7aa-c87a64ff65e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883561915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2883561915
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3224267395
Short name T255
Test name
Test status
Simulation time 29581971393 ps
CPU time 42.78 seconds
Started Jul 03 05:44:02 PM PDT 24
Finished Jul 03 05:44:45 PM PDT 24
Peak memory 199944 kb
Host smart-22dd929b-4455-47bd-b3df-19550f1953ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224267395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3224267395
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3920975922
Short name T853
Test name
Test status
Simulation time 30012186498 ps
CPU time 49.32 seconds
Started Jul 03 05:44:06 PM PDT 24
Finished Jul 03 05:44:56 PM PDT 24
Peak memory 199888 kb
Host smart-b938d32c-0c9d-45e2-a6a5-1a760ba81e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920975922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3920975922
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1486008507
Short name T169
Test name
Test status
Simulation time 164935262919 ps
CPU time 256.23 seconds
Started Jul 03 05:44:07 PM PDT 24
Finished Jul 03 05:48:24 PM PDT 24
Peak memory 199972 kb
Host smart-7529f0eb-a63c-40f2-a083-773ac83c82e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486008507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1486008507
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3027694521
Short name T499
Test name
Test status
Simulation time 9161915910 ps
CPU time 7.09 seconds
Started Jul 03 05:44:04 PM PDT 24
Finished Jul 03 05:44:11 PM PDT 24
Peak memory 197448 kb
Host smart-fcb3dc26-cb62-4fc3-a755-c5200c85058c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027694521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3027694521
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.855779389
Short name T246
Test name
Test status
Simulation time 80713816228 ps
CPU time 279.58 seconds
Started Jul 03 05:44:06 PM PDT 24
Finished Jul 03 05:48:46 PM PDT 24
Peak memory 199936 kb
Host smart-c0e003df-f096-447f-ae81-7c8edac5fabc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855779389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.855779389
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.456643961
Short name T787
Test name
Test status
Simulation time 6480304842 ps
CPU time 3.91 seconds
Started Jul 03 05:44:06 PM PDT 24
Finished Jul 03 05:44:10 PM PDT 24
Peak memory 199476 kb
Host smart-c544df05-86f1-466b-9e03-6e6c3b38c72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456643961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.456643961
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3532333430
Short name T567
Test name
Test status
Simulation time 4686871759 ps
CPU time 7.72 seconds
Started Jul 03 05:44:05 PM PDT 24
Finished Jul 03 05:44:13 PM PDT 24
Peak memory 198596 kb
Host smart-6514b141-a4ae-4455-b533-42c269f9fe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532333430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3532333430
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.4288567319
Short name T777
Test name
Test status
Simulation time 10818937364 ps
CPU time 175.64 seconds
Started Jul 03 05:44:08 PM PDT 24
Finished Jul 03 05:47:04 PM PDT 24
Peak memory 199948 kb
Host smart-4a3f4871-6a83-4dc8-a0af-e528d0c1e75e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4288567319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4288567319
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.278587350
Short name T429
Test name
Test status
Simulation time 2212981141 ps
CPU time 10.8 seconds
Started Jul 03 05:44:04 PM PDT 24
Finished Jul 03 05:44:15 PM PDT 24
Peak memory 199516 kb
Host smart-d7a718ea-0189-4888-ac02-85d08b682085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278587350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.278587350
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1261428876
Short name T280
Test name
Test status
Simulation time 48980644294 ps
CPU time 102.82 seconds
Started Jul 03 05:44:07 PM PDT 24
Finished Jul 03 05:45:51 PM PDT 24
Peak memory 199936 kb
Host smart-9aaf78fe-d5c7-4182-ae41-40aea4ef366a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261428876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1261428876
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3883825954
Short name T388
Test name
Test status
Simulation time 548247445 ps
CPU time 1.4 seconds
Started Jul 03 05:44:03 PM PDT 24
Finished Jul 03 05:44:05 PM PDT 24
Peak memory 195384 kb
Host smart-b7c496ea-889c-44ae-84d7-2f1fa530ce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883825954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3883825954
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.620107591
Short name T315
Test name
Test status
Simulation time 6085868193 ps
CPU time 14.95 seconds
Started Jul 03 05:44:04 PM PDT 24
Finished Jul 03 05:44:20 PM PDT 24
Peak memory 199932 kb
Host smart-745eea1f-c3b6-47f5-8489-908ed67e9dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620107591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.620107591
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.695212386
Short name T778
Test name
Test status
Simulation time 75851633577 ps
CPU time 853.29 seconds
Started Jul 03 05:44:06 PM PDT 24
Finished Jul 03 05:58:20 PM PDT 24
Peak memory 224784 kb
Host smart-4231fcb6-043b-4d3a-8ce9-78156770a00c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695212386 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.695212386
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3666968136
Short name T986
Test name
Test status
Simulation time 1436443545 ps
CPU time 3.97 seconds
Started Jul 03 05:44:09 PM PDT 24
Finished Jul 03 05:44:13 PM PDT 24
Peak memory 198464 kb
Host smart-a0d44a86-a37c-4da3-a1a7-fbacc1d10df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666968136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3666968136
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1893482015
Short name T257
Test name
Test status
Simulation time 13368598823 ps
CPU time 12.09 seconds
Started Jul 03 05:44:06 PM PDT 24
Finished Jul 03 05:44:19 PM PDT 24
Peak memory 199960 kb
Host smart-20334a15-489f-4e25-aff0-4887665eb4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893482015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1893482015
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3912098284
Short name T23
Test name
Test status
Simulation time 52473649 ps
CPU time 0.54 seconds
Started Jul 03 05:44:08 PM PDT 24
Finished Jul 03 05:44:09 PM PDT 24
Peak memory 195288 kb
Host smart-6089c4b1-ebbe-441c-947d-65f1bee30947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912098284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3912098284
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.21805600
Short name T504
Test name
Test status
Simulation time 131185910987 ps
CPU time 168.68 seconds
Started Jul 03 05:44:11 PM PDT 24
Finished Jul 03 05:47:00 PM PDT 24
Peak memory 199880 kb
Host smart-fa3d5070-35c7-4b9a-9611-6372dcbbd92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21805600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.21805600
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2717060411
Short name T112
Test name
Test status
Simulation time 132446018575 ps
CPU time 52.79 seconds
Started Jul 03 05:44:10 PM PDT 24
Finished Jul 03 05:45:03 PM PDT 24
Peak memory 199900 kb
Host smart-6496fe16-5c18-4940-af8c-c5bebdef33ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717060411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2717060411
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4208206917
Short name T1000
Test name
Test status
Simulation time 289597212676 ps
CPU time 38.71 seconds
Started Jul 03 05:44:09 PM PDT 24
Finished Jul 03 05:44:48 PM PDT 24
Peak memory 199872 kb
Host smart-2ea81714-db47-4643-8d63-e1dfe51ebe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208206917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4208206917
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2407384611
Short name T879
Test name
Test status
Simulation time 33140710003 ps
CPU time 29.93 seconds
Started Jul 03 05:44:07 PM PDT 24
Finished Jul 03 05:44:37 PM PDT 24
Peak memory 199916 kb
Host smart-2496f163-1cd8-4466-a186-0e00caf3023e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407384611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2407384611
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2771251578
Short name T582
Test name
Test status
Simulation time 103215036690 ps
CPU time 293.53 seconds
Started Jul 03 05:44:08 PM PDT 24
Finished Jul 03 05:49:02 PM PDT 24
Peak memory 199908 kb
Host smart-63f25f45-1902-47eb-be79-f7c68fbf7bd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771251578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2771251578
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2567363680
Short name T470
Test name
Test status
Simulation time 9158094446 ps
CPU time 3.34 seconds
Started Jul 03 05:44:09 PM PDT 24
Finished Jul 03 05:44:13 PM PDT 24
Peak memory 198508 kb
Host smart-225dd03c-6d54-4ca4-a559-65d5179766c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567363680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2567363680
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.4290849516
Short name T937
Test name
Test status
Simulation time 13426334196 ps
CPU time 12.92 seconds
Started Jul 03 05:44:08 PM PDT 24
Finished Jul 03 05:44:21 PM PDT 24
Peak memory 198588 kb
Host smart-730a74da-176e-481b-926c-1ea731cf857e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290849516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4290849516
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.692611776
Short name T671
Test name
Test status
Simulation time 5320043034 ps
CPU time 72.67 seconds
Started Jul 03 05:44:08 PM PDT 24
Finished Jul 03 05:45:22 PM PDT 24
Peak memory 199968 kb
Host smart-105e1496-a9cc-4a2f-83f4-f4efdbdf58e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692611776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.692611776
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3337811220
Short name T1012
Test name
Test status
Simulation time 5765263255 ps
CPU time 12.44 seconds
Started Jul 03 05:44:11 PM PDT 24
Finished Jul 03 05:44:24 PM PDT 24
Peak memory 199120 kb
Host smart-89e023e5-8e96-4f27-830c-f0922b675b69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3337811220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3337811220
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.960041033
Short name T676
Test name
Test status
Simulation time 119580334379 ps
CPU time 42.58 seconds
Started Jul 03 05:44:09 PM PDT 24
Finished Jul 03 05:44:52 PM PDT 24
Peak memory 199632 kb
Host smart-270ab788-9337-480f-814d-ae2167318151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960041033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.960041033
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3472618096
Short name T550
Test name
Test status
Simulation time 4087306205 ps
CPU time 7.08 seconds
Started Jul 03 05:44:12 PM PDT 24
Finished Jul 03 05:44:19 PM PDT 24
Peak memory 196096 kb
Host smart-9c13f0c1-c752-4e55-9d53-6fda8a09fce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472618096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3472618096
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1593937504
Short name T311
Test name
Test status
Simulation time 871831999 ps
CPU time 2.26 seconds
Started Jul 03 05:44:07 PM PDT 24
Finished Jul 03 05:44:10 PM PDT 24
Peak memory 198432 kb
Host smart-2207a79f-8f26-433a-8061-f0391a3d77ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593937504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1593937504
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2463948909
Short name T845
Test name
Test status
Simulation time 16477213855 ps
CPU time 366.37 seconds
Started Jul 03 05:44:10 PM PDT 24
Finished Jul 03 05:50:17 PM PDT 24
Peak memory 208232 kb
Host smart-0bf5a487-9a61-418f-8cb3-4d4aa2827810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463948909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2463948909
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2125704650
Short name T371
Test name
Test status
Simulation time 663400881 ps
CPU time 2.23 seconds
Started Jul 03 05:44:09 PM PDT 24
Finished Jul 03 05:44:12 PM PDT 24
Peak memory 198408 kb
Host smart-5424e6d4-6d7a-4f35-8431-6c83176025df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125704650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2125704650
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.4234470851
Short name T537
Test name
Test status
Simulation time 90398559049 ps
CPU time 73.89 seconds
Started Jul 03 05:44:09 PM PDT 24
Finished Jul 03 05:45:23 PM PDT 24
Peak memory 199976 kb
Host smart-c4242df8-5460-4847-b75a-587b7dea032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234470851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.4234470851
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2949366501
Short name T1001
Test name
Test status
Simulation time 44476728 ps
CPU time 0.55 seconds
Started Jul 03 05:44:14 PM PDT 24
Finished Jul 03 05:44:15 PM PDT 24
Peak memory 195340 kb
Host smart-fbfea0e7-15d7-4f1f-b9b5-686111af5ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949366501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2949366501
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.4030663696
Short name T546
Test name
Test status
Simulation time 168310250636 ps
CPU time 419.31 seconds
Started Jul 03 05:44:11 PM PDT 24
Finished Jul 03 05:51:11 PM PDT 24
Peak memory 199944 kb
Host smart-b0e75870-32df-4365-887d-45cff9b6ca48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030663696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.4030663696
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2242113036
Short name T457
Test name
Test status
Simulation time 180186051367 ps
CPU time 330.89 seconds
Started Jul 03 05:44:14 PM PDT 24
Finished Jul 03 05:49:45 PM PDT 24
Peak memory 199964 kb
Host smart-eafef915-43a1-4246-a5f1-a184438b80cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242113036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2242113036
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2454403354
Short name T917
Test name
Test status
Simulation time 105875659373 ps
CPU time 168 seconds
Started Jul 03 05:44:17 PM PDT 24
Finished Jul 03 05:47:05 PM PDT 24
Peak memory 199992 kb
Host smart-23823e81-346e-4a2f-a747-f955805432fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454403354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2454403354
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3083594373
Short name T705
Test name
Test status
Simulation time 11898913613 ps
CPU time 16.14 seconds
Started Jul 03 05:44:13 PM PDT 24
Finished Jul 03 05:44:30 PM PDT 24
Peak memory 196652 kb
Host smart-b51e46b7-3fe3-4125-bf73-2528509564a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083594373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3083594373
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.802262414
Short name T715
Test name
Test status
Simulation time 135616452518 ps
CPU time 1075.99 seconds
Started Jul 03 05:44:14 PM PDT 24
Finished Jul 03 06:02:11 PM PDT 24
Peak memory 199932 kb
Host smart-73424fc2-e667-4099-8ccb-d3a1f791a16a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=802262414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.802262414
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.4268670256
Short name T792
Test name
Test status
Simulation time 7976502576 ps
CPU time 6.06 seconds
Started Jul 03 05:44:13 PM PDT 24
Finished Jul 03 05:44:20 PM PDT 24
Peak memory 199820 kb
Host smart-36540012-c9fe-4b08-b82b-ad2af12102c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268670256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4268670256
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.2416695460
Short name T1079
Test name
Test status
Simulation time 15634732003 ps
CPU time 364.12 seconds
Started Jul 03 05:44:14 PM PDT 24
Finished Jul 03 05:50:19 PM PDT 24
Peak memory 199984 kb
Host smart-9a91ccd6-988a-429b-bde1-db6e7fbe30f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416695460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2416695460
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1301031404
Short name T1021
Test name
Test status
Simulation time 2754004232 ps
CPU time 10.05 seconds
Started Jul 03 05:44:13 PM PDT 24
Finished Jul 03 05:44:24 PM PDT 24
Peak memory 199076 kb
Host smart-4d854f94-db5c-43a7-a1f3-c43ceda904b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301031404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1301031404
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3230243892
Short name T551
Test name
Test status
Simulation time 75636215481 ps
CPU time 123.1 seconds
Started Jul 03 05:44:13 PM PDT 24
Finished Jul 03 05:46:16 PM PDT 24
Peak memory 199892 kb
Host smart-856954fa-c354-4d4e-b25f-2d7dfc1ad0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230243892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3230243892
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3040658407
Short name T435
Test name
Test status
Simulation time 5548489243 ps
CPU time 2.6 seconds
Started Jul 03 05:44:14 PM PDT 24
Finished Jul 03 05:44:17 PM PDT 24
Peak memory 196240 kb
Host smart-cbcb0bbc-8583-441e-8a98-96c66653add9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040658407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3040658407
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3860387503
Short name T957
Test name
Test status
Simulation time 5527782487 ps
CPU time 8.26 seconds
Started Jul 03 05:44:12 PM PDT 24
Finished Jul 03 05:44:20 PM PDT 24
Peak memory 199692 kb
Host smart-7230fecb-39c8-454e-8561-8dbe70fac9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860387503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3860387503
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3807861737
Short name T1090
Test name
Test status
Simulation time 22596719357 ps
CPU time 253.03 seconds
Started Jul 03 05:44:13 PM PDT 24
Finished Jul 03 05:48:27 PM PDT 24
Peak memory 215952 kb
Host smart-25768098-5ef9-46ea-be87-996230611b96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807861737 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3807861737
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1115224915
Short name T283
Test name
Test status
Simulation time 1934192905 ps
CPU time 3.82 seconds
Started Jul 03 05:44:15 PM PDT 24
Finished Jul 03 05:44:19 PM PDT 24
Peak memory 198712 kb
Host smart-154dbc83-1dc1-4db8-a615-475c50df27f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115224915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1115224915
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.944735621
Short name T960
Test name
Test status
Simulation time 5791458305 ps
CPU time 9.09 seconds
Started Jul 03 05:44:09 PM PDT 24
Finished Jul 03 05:44:18 PM PDT 24
Peak memory 199428 kb
Host smart-ea981491-cddd-446a-b43c-63ea68df2c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944735621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.944735621
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1948763420
Short name T362
Test name
Test status
Simulation time 41982523 ps
CPU time 0.57 seconds
Started Jul 03 05:44:18 PM PDT 24
Finished Jul 03 05:44:19 PM PDT 24
Peak memory 195276 kb
Host smart-5827bc29-40f4-4c44-bc1c-70439f6e7221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948763420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1948763420
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.600240013
Short name T780
Test name
Test status
Simulation time 205731471038 ps
CPU time 35.8 seconds
Started Jul 03 05:44:14 PM PDT 24
Finished Jul 03 05:44:51 PM PDT 24
Peak memory 199936 kb
Host smart-f4666674-40a6-4620-b0d0-d66ee9ef4eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600240013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.600240013
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.745902742
Short name T526
Test name
Test status
Simulation time 8778712468 ps
CPU time 15.43 seconds
Started Jul 03 05:44:13 PM PDT 24
Finished Jul 03 05:44:29 PM PDT 24
Peak memory 199944 kb
Host smart-e4f42b10-57da-4fca-97b7-90c98553e08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745902742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.745902742
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2446343111
Short name T894
Test name
Test status
Simulation time 67519453077 ps
CPU time 82.54 seconds
Started Jul 03 05:44:18 PM PDT 24
Finished Jul 03 05:45:40 PM PDT 24
Peak memory 199988 kb
Host smart-6e6f1306-0e2d-40c4-92a3-a2517910ae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446343111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2446343111
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1246376403
Short name T772
Test name
Test status
Simulation time 11933121398 ps
CPU time 5.55 seconds
Started Jul 03 05:44:17 PM PDT 24
Finished Jul 03 05:44:23 PM PDT 24
Peak memory 196564 kb
Host smart-6b260871-6ea2-458a-936d-88b1bb5918e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246376403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1246376403
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.511700554
Short name T983
Test name
Test status
Simulation time 213831004308 ps
CPU time 519.04 seconds
Started Jul 03 05:44:18 PM PDT 24
Finished Jul 03 05:52:57 PM PDT 24
Peak memory 199948 kb
Host smart-18d56a67-899a-4e56-bac0-d5782323d3cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=511700554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.511700554
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.111271517
Short name T413
Test name
Test status
Simulation time 1603458571 ps
CPU time 2.24 seconds
Started Jul 03 05:44:16 PM PDT 24
Finished Jul 03 05:44:19 PM PDT 24
Peak memory 197920 kb
Host smart-5fd30011-2ab5-42da-9832-9e10935827de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111271517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.111271517
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.1407569204
Short name T306
Test name
Test status
Simulation time 14926970038 ps
CPU time 60.18 seconds
Started Jul 03 05:44:20 PM PDT 24
Finished Jul 03 05:45:21 PM PDT 24
Peak memory 199948 kb
Host smart-56d73b0d-93f3-42be-8461-4ecd8dbc1828
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1407569204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1407569204
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.921645749
Short name T968
Test name
Test status
Simulation time 1781547322 ps
CPU time 9.35 seconds
Started Jul 03 05:44:16 PM PDT 24
Finished Jul 03 05:44:26 PM PDT 24
Peak memory 198328 kb
Host smart-8fdb78e0-67b1-41d4-aae8-7d161f0c6f73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=921645749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.921645749
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2979917616
Short name T158
Test name
Test status
Simulation time 69455725556 ps
CPU time 23.92 seconds
Started Jul 03 05:44:16 PM PDT 24
Finished Jul 03 05:44:40 PM PDT 24
Peak memory 199640 kb
Host smart-ac292594-3087-452d-b6c1-caa053874dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979917616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2979917616
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.4204949990
Short name T1037
Test name
Test status
Simulation time 1762211938 ps
CPU time 1.94 seconds
Started Jul 03 05:44:18 PM PDT 24
Finished Jul 03 05:44:20 PM PDT 24
Peak memory 195492 kb
Host smart-ee43225e-6ea3-4794-94ec-5dd2e480fc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204949990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.4204949990
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.767179456
Short name T913
Test name
Test status
Simulation time 304636848 ps
CPU time 1.77 seconds
Started Jul 03 05:44:13 PM PDT 24
Finished Jul 03 05:44:16 PM PDT 24
Peak memory 199592 kb
Host smart-c72c0e0d-60f7-433f-b9ff-e9a06472b0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767179456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.767179456
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1566155448
Short name T234
Test name
Test status
Simulation time 13434174600 ps
CPU time 98.76 seconds
Started Jul 03 05:44:17 PM PDT 24
Finished Jul 03 05:45:56 PM PDT 24
Peak memory 199948 kb
Host smart-0198eaa0-8aba-4b43-8dd9-6cde7aa94c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566155448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1566155448
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1143155604
Short name T19
Test name
Test status
Simulation time 1224372264 ps
CPU time 2.74 seconds
Started Jul 03 05:44:20 PM PDT 24
Finished Jul 03 05:44:23 PM PDT 24
Peak memory 198340 kb
Host smart-65d2e8cf-95b5-426a-afda-5578a71b167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143155604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1143155604
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1110342507
Short name T714
Test name
Test status
Simulation time 60256448097 ps
CPU time 9.27 seconds
Started Jul 03 05:44:14 PM PDT 24
Finished Jul 03 05:44:24 PM PDT 24
Peak memory 199920 kb
Host smart-c4527cb1-3728-43c0-a7b8-4cfcea3d252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110342507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1110342507
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1729499166
Short name T948
Test name
Test status
Simulation time 104703682 ps
CPU time 0.58 seconds
Started Jul 03 05:42:58 PM PDT 24
Finished Jul 03 05:42:59 PM PDT 24
Peak memory 195564 kb
Host smart-09240814-797d-478b-9002-7e4856f0f595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729499166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1729499166
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2313462417
Short name T129
Test name
Test status
Simulation time 102303708558 ps
CPU time 36.15 seconds
Started Jul 03 05:42:50 PM PDT 24
Finished Jul 03 05:43:27 PM PDT 24
Peak memory 200024 kb
Host smart-83f7779c-ee98-4a4a-9d31-8d73a67aab33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313462417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2313462417
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4138391806
Short name T593
Test name
Test status
Simulation time 170239891739 ps
CPU time 256.16 seconds
Started Jul 03 05:43:09 PM PDT 24
Finished Jul 03 05:47:26 PM PDT 24
Peak memory 200020 kb
Host smart-b951bb8e-ab87-4fcf-aa58-76a76b39a1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138391806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4138391806
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1011098434
Short name T301
Test name
Test status
Simulation time 62665426565 ps
CPU time 175.88 seconds
Started Jul 03 05:43:10 PM PDT 24
Finished Jul 03 05:46:07 PM PDT 24
Peak memory 199976 kb
Host smart-9d9bbec0-b21a-4abb-a27f-e4455e6efbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011098434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1011098434
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1338688618
Short name T682
Test name
Test status
Simulation time 52665097499 ps
CPU time 27.74 seconds
Started Jul 03 05:42:58 PM PDT 24
Finished Jul 03 05:43:26 PM PDT 24
Peak memory 199824 kb
Host smart-4e506947-5967-475a-afe9-370fa1a2687a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338688618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1338688618
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2525586143
Short name T577
Test name
Test status
Simulation time 118953047922 ps
CPU time 373.46 seconds
Started Jul 03 05:42:56 PM PDT 24
Finished Jul 03 05:49:10 PM PDT 24
Peak memory 199912 kb
Host smart-354344c0-4b9a-4637-90b0-5bc21dc4ede7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525586143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2525586143
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4281871835
Short name T407
Test name
Test status
Simulation time 2262137978 ps
CPU time 5 seconds
Started Jul 03 05:42:54 PM PDT 24
Finished Jul 03 05:43:00 PM PDT 24
Peak memory 198748 kb
Host smart-d6f8211a-9acd-4896-93b3-15f331fc7832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281871835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4281871835
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.4079675926
Short name T844
Test name
Test status
Simulation time 7783246073 ps
CPU time 80.86 seconds
Started Jul 03 05:42:52 PM PDT 24
Finished Jul 03 05:44:13 PM PDT 24
Peak memory 199948 kb
Host smart-0362f420-9447-42df-9181-1732db959fad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079675926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4079675926
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3344790898
Short name T475
Test name
Test status
Simulation time 4222381164 ps
CPU time 33.92 seconds
Started Jul 03 05:42:51 PM PDT 24
Finished Jul 03 05:43:25 PM PDT 24
Peak memory 198956 kb
Host smart-f25f05a1-fa14-4d0e-b8b0-33b8847f6df7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3344790898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3344790898
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1453716653
Short name T275
Test name
Test status
Simulation time 117534073249 ps
CPU time 115.63 seconds
Started Jul 03 05:42:54 PM PDT 24
Finished Jul 03 05:44:50 PM PDT 24
Peak memory 199932 kb
Host smart-f97f1d21-41e0-4cdc-88db-f111cf79a046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453716653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1453716653
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2620543665
Short name T415
Test name
Test status
Simulation time 4438026321 ps
CPU time 7.13 seconds
Started Jul 03 05:42:58 PM PDT 24
Finished Jul 03 05:43:06 PM PDT 24
Peak memory 196224 kb
Host smart-999a510d-6902-488f-b14e-dde18e47983e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620543665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2620543665
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2264624561
Short name T25
Test name
Test status
Simulation time 147649085 ps
CPU time 0.77 seconds
Started Jul 03 05:43:08 PM PDT 24
Finished Jul 03 05:43:09 PM PDT 24
Peak memory 218336 kb
Host smart-afefd91a-3854-4437-beac-d0cb465a461c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264624561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2264624561
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1424317405
Short name T655
Test name
Test status
Simulation time 6048892774 ps
CPU time 7.78 seconds
Started Jul 03 05:43:11 PM PDT 24
Finished Jul 03 05:43:19 PM PDT 24
Peak memory 199628 kb
Host smart-3b6d6341-ca08-426a-b322-b4cd2c175979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424317405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1424317405
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1407093230
Short name T313
Test name
Test status
Simulation time 138865569788 ps
CPU time 279.82 seconds
Started Jul 03 05:43:00 PM PDT 24
Finished Jul 03 05:47:40 PM PDT 24
Peak memory 199952 kb
Host smart-e8630094-7c2a-491d-96f4-1daa6c48b6d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407093230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1407093230
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3781498966
Short name T87
Test name
Test status
Simulation time 74694856145 ps
CPU time 716.2 seconds
Started Jul 03 05:42:50 PM PDT 24
Finished Jul 03 05:54:46 PM PDT 24
Peak memory 214884 kb
Host smart-03e6c6cc-7509-4364-8f11-dc3a6fa455df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781498966 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3781498966
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1997807966
Short name T830
Test name
Test status
Simulation time 7951758367 ps
CPU time 16.23 seconds
Started Jul 03 05:43:03 PM PDT 24
Finished Jul 03 05:43:20 PM PDT 24
Peak memory 199704 kb
Host smart-3d4af00f-43ab-4ce2-be08-8904bd55da2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997807966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1997807966
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3082092525
Short name T695
Test name
Test status
Simulation time 51749696264 ps
CPU time 71.89 seconds
Started Jul 03 05:43:03 PM PDT 24
Finished Jul 03 05:44:16 PM PDT 24
Peak memory 199952 kb
Host smart-442bea1b-a2ae-426f-a688-58527ab7dd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082092525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3082092525
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.67587769
Short name T503
Test name
Test status
Simulation time 29625980 ps
CPU time 0.58 seconds
Started Jul 03 05:44:24 PM PDT 24
Finished Jul 03 05:44:25 PM PDT 24
Peak memory 195292 kb
Host smart-16a0d6fb-2062-4242-8b19-54cfd653e252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67587769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.67587769
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.494896642
Short name T496
Test name
Test status
Simulation time 118809487884 ps
CPU time 72.14 seconds
Started Jul 03 05:44:19 PM PDT 24
Finished Jul 03 05:45:32 PM PDT 24
Peak memory 200004 kb
Host smart-714b3388-a3fc-412d-aacf-0c29b2c11657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494896642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.494896642
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1490622070
Short name T576
Test name
Test status
Simulation time 71038193238 ps
CPU time 12.45 seconds
Started Jul 03 05:44:16 PM PDT 24
Finished Jul 03 05:44:29 PM PDT 24
Peak memory 199940 kb
Host smart-985c4820-db2a-408b-a60d-2421a4bd4d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490622070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1490622070
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2506477184
Short name T860
Test name
Test status
Simulation time 17291118082 ps
CPU time 13.11 seconds
Started Jul 03 05:44:15 PM PDT 24
Finished Jul 03 05:44:28 PM PDT 24
Peak memory 199956 kb
Host smart-fc1a587c-f96b-4aa9-96a7-11e71ef8a218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506477184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2506477184
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3780939576
Short name T540
Test name
Test status
Simulation time 300021436461 ps
CPU time 140.27 seconds
Started Jul 03 05:44:23 PM PDT 24
Finished Jul 03 05:46:43 PM PDT 24
Peak memory 199928 kb
Host smart-2dc26f4e-4612-497d-9b00-8cc916dccfd9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780939576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3780939576
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2137497615
Short name T1016
Test name
Test status
Simulation time 180688356833 ps
CPU time 1106.14 seconds
Started Jul 03 05:44:21 PM PDT 24
Finished Jul 03 06:02:48 PM PDT 24
Peak memory 199924 kb
Host smart-90589b51-26a8-4637-ab41-d27b5ec6516a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137497615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2137497615
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2036085401
Short name T973
Test name
Test status
Simulation time 403191182 ps
CPU time 1.66 seconds
Started Jul 03 05:44:20 PM PDT 24
Finished Jul 03 05:44:22 PM PDT 24
Peak memory 198608 kb
Host smart-62cf2b6a-f139-4f1b-a99b-741f250ff6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036085401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2036085401
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.1672199738
Short name T34
Test name
Test status
Simulation time 15255582947 ps
CPU time 242.61 seconds
Started Jul 03 05:44:21 PM PDT 24
Finished Jul 03 05:48:24 PM PDT 24
Peak memory 199904 kb
Host smart-8c097d1f-5e31-45ec-bd57-cad901e7d437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672199738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1672199738
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2808473453
Short name T759
Test name
Test status
Simulation time 2309307208 ps
CPU time 14.72 seconds
Started Jul 03 05:44:21 PM PDT 24
Finished Jul 03 05:44:36 PM PDT 24
Peak memory 198140 kb
Host smart-217a32a4-ff8e-4637-beeb-54640ab74f98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2808473453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2808473453
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2762361229
Short name T320
Test name
Test status
Simulation time 30181861909 ps
CPU time 14.19 seconds
Started Jul 03 05:44:22 PM PDT 24
Finished Jul 03 05:44:36 PM PDT 24
Peak memory 199868 kb
Host smart-cb485f8d-3e94-49b9-ab14-9fe66fdb5b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762361229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2762361229
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3369467269
Short name T650
Test name
Test status
Simulation time 2291463012 ps
CPU time 2.87 seconds
Started Jul 03 05:44:21 PM PDT 24
Finished Jul 03 05:44:24 PM PDT 24
Peak memory 195508 kb
Host smart-62549805-8c6c-4851-be9c-44f0b10fbfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369467269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3369467269
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.969749588
Short name T328
Test name
Test status
Simulation time 5370033330 ps
CPU time 16.02 seconds
Started Jul 03 05:44:20 PM PDT 24
Finished Jul 03 05:44:36 PM PDT 24
Peak memory 199908 kb
Host smart-68dae42d-663e-4f1f-af45-4f0eb6712001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969749588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.969749588
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3279269355
Short name T828
Test name
Test status
Simulation time 296593936286 ps
CPU time 302.88 seconds
Started Jul 03 05:44:23 PM PDT 24
Finished Jul 03 05:49:26 PM PDT 24
Peak memory 199956 kb
Host smart-ff5631d8-d348-438e-a913-b294cebf2642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279269355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3279269355
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1612576593
Short name T1022
Test name
Test status
Simulation time 1081999471 ps
CPU time 2.39 seconds
Started Jul 03 05:44:20 PM PDT 24
Finished Jul 03 05:44:23 PM PDT 24
Peak memory 198812 kb
Host smart-4378e1a6-a175-459b-a25d-4a895a0109b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612576593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1612576593
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3388976756
Short name T351
Test name
Test status
Simulation time 68828512541 ps
CPU time 93.76 seconds
Started Jul 03 05:44:18 PM PDT 24
Finished Jul 03 05:45:53 PM PDT 24
Peak memory 200004 kb
Host smart-4bb17ee7-f2a0-455f-931b-f7f89a6b4b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388976756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3388976756
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.4009850989
Short name T884
Test name
Test status
Simulation time 30289631 ps
CPU time 0.55 seconds
Started Jul 03 05:44:32 PM PDT 24
Finished Jul 03 05:44:33 PM PDT 24
Peak memory 195276 kb
Host smart-b7538e6d-e952-4123-8a29-861fc9e50db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009850989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4009850989
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3937055771
Short name T304
Test name
Test status
Simulation time 15579906251 ps
CPU time 25.44 seconds
Started Jul 03 05:44:25 PM PDT 24
Finished Jul 03 05:44:51 PM PDT 24
Peak memory 199920 kb
Host smart-e2355130-cfc0-46d0-b18c-9fe8792a0ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937055771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3937055771
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1090617651
Short name T123
Test name
Test status
Simulation time 151279174482 ps
CPU time 175.05 seconds
Started Jul 03 05:44:26 PM PDT 24
Finished Jul 03 05:47:21 PM PDT 24
Peak memory 199944 kb
Host smart-7166505c-52dc-4f44-b88b-78be969ce9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090617651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1090617651
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3855780695
Short name T102
Test name
Test status
Simulation time 69603011387 ps
CPU time 50.67 seconds
Started Jul 03 05:44:24 PM PDT 24
Finished Jul 03 05:45:15 PM PDT 24
Peak memory 199860 kb
Host smart-11ffa8c1-faeb-441f-b3bd-f857ae2e9ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855780695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3855780695
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2626472796
Short name T90
Test name
Test status
Simulation time 167937351191 ps
CPU time 33.08 seconds
Started Jul 03 05:44:23 PM PDT 24
Finished Jul 03 05:44:57 PM PDT 24
Peak memory 199964 kb
Host smart-3ac7a76b-2bf9-4e5f-b1a3-1070806c2da4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626472796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2626472796
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3985897481
Short name T273
Test name
Test status
Simulation time 74382947613 ps
CPU time 230.59 seconds
Started Jul 03 05:44:27 PM PDT 24
Finished Jul 03 05:48:18 PM PDT 24
Peak memory 199968 kb
Host smart-233d1755-d657-44fd-aed9-02e68b48beb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985897481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3985897481
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.227692718
Short name T964
Test name
Test status
Simulation time 3752034741 ps
CPU time 9.66 seconds
Started Jul 03 05:44:25 PM PDT 24
Finished Jul 03 05:44:35 PM PDT 24
Peak memory 199928 kb
Host smart-e29b398b-dfde-4476-b1e2-93d043c39700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227692718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.227692718
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.1201619140
Short name T440
Test name
Test status
Simulation time 17970281359 ps
CPU time 335.09 seconds
Started Jul 03 05:44:24 PM PDT 24
Finished Jul 03 05:49:59 PM PDT 24
Peak memory 199952 kb
Host smart-cf16aaff-fe47-4c01-a3fb-a1de450d9a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201619140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1201619140
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2885869488
Short name T370
Test name
Test status
Simulation time 4264522340 ps
CPU time 35.46 seconds
Started Jul 03 05:44:23 PM PDT 24
Finished Jul 03 05:44:59 PM PDT 24
Peak memory 198124 kb
Host smart-f5aa7da1-2fa0-4cf5-9e7c-da05fae3c81d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885869488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2885869488
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1327756536
Short name T1009
Test name
Test status
Simulation time 23836819423 ps
CPU time 34.58 seconds
Started Jul 03 05:44:25 PM PDT 24
Finished Jul 03 05:45:00 PM PDT 24
Peak memory 199888 kb
Host smart-4c8689d8-1369-42f1-ad28-8d8877ae2522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327756536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1327756536
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3246437909
Short name T40
Test name
Test status
Simulation time 4488000263 ps
CPU time 2.45 seconds
Started Jul 03 05:44:25 PM PDT 24
Finished Jul 03 05:44:27 PM PDT 24
Peak memory 196060 kb
Host smart-a6278741-7cca-427d-914b-c88753aeef83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246437909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3246437909
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3368231855
Short name T480
Test name
Test status
Simulation time 683261010 ps
CPU time 1.63 seconds
Started Jul 03 05:44:23 PM PDT 24
Finished Jul 03 05:44:25 PM PDT 24
Peak memory 199504 kb
Host smart-cab858dd-3eb3-4e85-a246-aad5769955e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368231855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3368231855
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3460758123
Short name T779
Test name
Test status
Simulation time 381985886603 ps
CPU time 138.16 seconds
Started Jul 03 05:44:29 PM PDT 24
Finished Jul 03 05:46:48 PM PDT 24
Peak memory 199920 kb
Host smart-22c88b1f-9a53-4b69-b225-dac602ec32d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460758123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3460758123
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.744684592
Short name T334
Test name
Test status
Simulation time 33736186211 ps
CPU time 743.21 seconds
Started Jul 03 05:44:28 PM PDT 24
Finished Jul 03 05:56:51 PM PDT 24
Peak memory 216428 kb
Host smart-383618a8-827e-4903-a49f-1a7e0d78aad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744684592 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.744684592
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3769991466
Short name T391
Test name
Test status
Simulation time 1937511808 ps
CPU time 2.18 seconds
Started Jul 03 05:44:23 PM PDT 24
Finished Jul 03 05:44:26 PM PDT 24
Peak memory 199864 kb
Host smart-23605f25-6654-41f9-9256-657bc7e35c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769991466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3769991466
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2804520242
Short name T991
Test name
Test status
Simulation time 119191128146 ps
CPU time 55.87 seconds
Started Jul 03 05:44:25 PM PDT 24
Finished Jul 03 05:45:21 PM PDT 24
Peak memory 199844 kb
Host smart-af1d12e9-ed13-46c6-acf0-bff71260e20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804520242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2804520242
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1034970325
Short name T436
Test name
Test status
Simulation time 55345839 ps
CPU time 0.57 seconds
Started Jul 03 05:44:37 PM PDT 24
Finished Jul 03 05:44:37 PM PDT 24
Peak memory 195528 kb
Host smart-8e502ffc-3c84-437f-9c6f-fc15b1762c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034970325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1034970325
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3610384051
Short name T897
Test name
Test status
Simulation time 44599682818 ps
CPU time 25.63 seconds
Started Jul 03 05:44:31 PM PDT 24
Finished Jul 03 05:44:57 PM PDT 24
Peak memory 199932 kb
Host smart-6c35c4f7-b3fa-484d-b5e2-224a80206824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610384051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3610384051
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2807317471
Short name T152
Test name
Test status
Simulation time 82752928552 ps
CPU time 112.99 seconds
Started Jul 03 05:44:28 PM PDT 24
Finished Jul 03 05:46:22 PM PDT 24
Peak memory 199932 kb
Host smart-e3d74e9f-f9a9-4383-ab4d-6f89673f4f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807317471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2807317471
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3495824810
Short name T896
Test name
Test status
Simulation time 85092144640 ps
CPU time 116.83 seconds
Started Jul 03 05:44:30 PM PDT 24
Finished Jul 03 05:46:27 PM PDT 24
Peak memory 199892 kb
Host smart-dd345f4c-4ae8-4567-b27c-525535332e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495824810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3495824810
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2679912395
Short name T403
Test name
Test status
Simulation time 253269204214 ps
CPU time 79.3 seconds
Started Jul 03 05:44:32 PM PDT 24
Finished Jul 03 05:45:52 PM PDT 24
Peak memory 196924 kb
Host smart-8252d18c-269e-484b-a601-1f2228ca4635
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679912395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2679912395
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.506958902
Short name T341
Test name
Test status
Simulation time 70990865647 ps
CPU time 256.91 seconds
Started Jul 03 05:44:33 PM PDT 24
Finished Jul 03 05:48:50 PM PDT 24
Peak memory 199876 kb
Host smart-3ae4a32f-ec78-4ab4-91b0-21b9fbd01ed5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=506958902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.506958902
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2388545726
Short name T580
Test name
Test status
Simulation time 2837008265 ps
CPU time 1.8 seconds
Started Jul 03 05:44:29 PM PDT 24
Finished Jul 03 05:44:31 PM PDT 24
Peak memory 195788 kb
Host smart-844ddc22-3f9a-4a58-a601-3f6903ef5608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388545726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2388545726
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.2687181058
Short name T472
Test name
Test status
Simulation time 21454413483 ps
CPU time 1216.89 seconds
Started Jul 03 05:44:36 PM PDT 24
Finished Jul 03 06:04:53 PM PDT 24
Peak memory 199848 kb
Host smart-19040fea-d456-4039-a806-3c120d0f43ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2687181058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2687181058
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.877581748
Short name T1027
Test name
Test status
Simulation time 6954100662 ps
CPU time 52.51 seconds
Started Jul 03 05:44:31 PM PDT 24
Finished Jul 03 05:45:23 PM PDT 24
Peak memory 198224 kb
Host smart-0f66b40d-82c8-484f-934f-38c59091d5a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877581748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.877581748
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2487307252
Short name T131
Test name
Test status
Simulation time 101478092077 ps
CPU time 37.59 seconds
Started Jul 03 05:44:28 PM PDT 24
Finished Jul 03 05:45:06 PM PDT 24
Peak memory 199612 kb
Host smart-cb207b21-99fe-41ee-a48a-97152b08d64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487307252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2487307252
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4247214680
Short name T324
Test name
Test status
Simulation time 6748098358 ps
CPU time 9.31 seconds
Started Jul 03 05:44:29 PM PDT 24
Finished Jul 03 05:44:39 PM PDT 24
Peak memory 196040 kb
Host smart-31bd8d77-79bb-45b1-934c-abe6b193a129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247214680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4247214680
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.295827810
Short name T928
Test name
Test status
Simulation time 647406114 ps
CPU time 2.61 seconds
Started Jul 03 05:44:31 PM PDT 24
Finished Jul 03 05:44:34 PM PDT 24
Peak memory 199648 kb
Host smart-c810577b-ccdd-4fa2-8f2c-540ccc9842cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295827810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.295827810
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3702185338
Short name T572
Test name
Test status
Simulation time 217421666831 ps
CPU time 172.47 seconds
Started Jul 03 05:44:36 PM PDT 24
Finished Jul 03 05:47:29 PM PDT 24
Peak memory 199844 kb
Host smart-d4d87a1b-035d-4276-aa71-d387b6c608a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702185338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3702185338
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2667394381
Short name T542
Test name
Test status
Simulation time 6347870890 ps
CPU time 6.27 seconds
Started Jul 03 05:44:34 PM PDT 24
Finished Jul 03 05:44:40 PM PDT 24
Peak memory 199940 kb
Host smart-f78690d5-e85d-47ab-a646-e565833b312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667394381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2667394381
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1500255970
Short name T309
Test name
Test status
Simulation time 15799329796 ps
CPU time 24.62 seconds
Started Jul 03 05:44:29 PM PDT 24
Finished Jul 03 05:44:54 PM PDT 24
Peak memory 199944 kb
Host smart-16848e09-4631-4c34-b62e-967539851a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500255970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1500255970
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1611617255
Short name T600
Test name
Test status
Simulation time 15044229 ps
CPU time 0.62 seconds
Started Jul 03 05:44:34 PM PDT 24
Finished Jul 03 05:44:35 PM PDT 24
Peak memory 195320 kb
Host smart-fecf35d4-6d6c-456e-be5a-22b82b79d4e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611617255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1611617255
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1685312407
Short name T483
Test name
Test status
Simulation time 12654377130 ps
CPU time 21.53 seconds
Started Jul 03 05:44:31 PM PDT 24
Finished Jul 03 05:44:53 PM PDT 24
Peak memory 199988 kb
Host smart-6c25f6f0-8845-43b2-96e6-1dd53d1543c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685312407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1685312407
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2306799294
Short name T747
Test name
Test status
Simulation time 35894149896 ps
CPU time 16.19 seconds
Started Jul 03 05:44:36 PM PDT 24
Finished Jul 03 05:44:53 PM PDT 24
Peak memory 199716 kb
Host smart-499f5166-9a7e-4d50-a17a-78b3084d90f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306799294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2306799294
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.291292411
Short name T128
Test name
Test status
Simulation time 106357054106 ps
CPU time 131.91 seconds
Started Jul 03 05:44:31 PM PDT 24
Finished Jul 03 05:46:43 PM PDT 24
Peak memory 199916 kb
Host smart-ac39d689-71f0-4ace-97ad-0b860e20e3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291292411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.291292411
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3083358537
Short name T809
Test name
Test status
Simulation time 108147924826 ps
CPU time 68.61 seconds
Started Jul 03 05:44:36 PM PDT 24
Finished Jul 03 05:45:45 PM PDT 24
Peak memory 195968 kb
Host smart-dccf2a91-972a-4ced-8ab8-3d541267b685
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083358537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3083358537
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2430184298
Short name T748
Test name
Test status
Simulation time 149130967056 ps
CPU time 543.53 seconds
Started Jul 03 05:44:34 PM PDT 24
Finished Jul 03 05:53:38 PM PDT 24
Peak memory 199948 kb
Host smart-ee2f7dd2-4602-472b-86f4-45119e0a4d59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430184298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2430184298
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.87317214
Short name T359
Test name
Test status
Simulation time 3343032613 ps
CPU time 2.39 seconds
Started Jul 03 05:44:32 PM PDT 24
Finished Jul 03 05:44:35 PM PDT 24
Peak memory 198412 kb
Host smart-3f9b6f7d-fbc3-4e8e-ba33-ed233fc70f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87317214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.87317214
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.244884613
Short name T822
Test name
Test status
Simulation time 29565890214 ps
CPU time 1577.2 seconds
Started Jul 03 05:44:34 PM PDT 24
Finished Jul 03 06:10:51 PM PDT 24
Peak memory 199972 kb
Host smart-61b988ae-cb4b-4168-b478-e1e1aaf0a16c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=244884613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.244884613
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1785503279
Short name T9
Test name
Test status
Simulation time 6047961014 ps
CPU time 13.66 seconds
Started Jul 03 05:44:32 PM PDT 24
Finished Jul 03 05:44:46 PM PDT 24
Peak memory 198144 kb
Host smart-065557e4-7584-4312-8eec-e08c12e62a3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785503279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1785503279
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2450414383
Short name T743
Test name
Test status
Simulation time 11199824705 ps
CPU time 14.67 seconds
Started Jul 03 05:44:31 PM PDT 24
Finished Jul 03 05:44:46 PM PDT 24
Peak memory 199724 kb
Host smart-50365ed8-2dcd-4f35-ac40-6789866bbf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450414383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2450414383
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3866160895
Short name T980
Test name
Test status
Simulation time 3394807970 ps
CPU time 5.61 seconds
Started Jul 03 05:44:31 PM PDT 24
Finished Jul 03 05:44:37 PM PDT 24
Peak memory 196300 kb
Host smart-e6d4e170-f997-49fb-9e3f-9ac99dafd802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866160895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3866160895
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2367768619
Short name T509
Test name
Test status
Simulation time 932611527 ps
CPU time 2.67 seconds
Started Jul 03 05:44:33 PM PDT 24
Finished Jul 03 05:44:36 PM PDT 24
Peak memory 198168 kb
Host smart-0c34bd15-352a-4269-8255-f609a75b9380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367768619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2367768619
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3265319075
Short name T619
Test name
Test status
Simulation time 142194521614 ps
CPU time 164.06 seconds
Started Jul 03 05:44:39 PM PDT 24
Finished Jul 03 05:47:24 PM PDT 24
Peak memory 199804 kb
Host smart-eb3732e1-5f41-40dc-ac44-e1ee0693184d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265319075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3265319075
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3910741488
Short name T336
Test name
Test status
Simulation time 94686334203 ps
CPU time 595.72 seconds
Started Jul 03 05:44:40 PM PDT 24
Finished Jul 03 05:54:36 PM PDT 24
Peak memory 216460 kb
Host smart-82a6bfc2-eaaf-4dc4-95fc-b4b6d546f571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910741488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3910741488
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3331714253
Short name T952
Test name
Test status
Simulation time 6453894006 ps
CPU time 7.26 seconds
Started Jul 03 05:44:31 PM PDT 24
Finished Jul 03 05:44:39 PM PDT 24
Peak memory 199864 kb
Host smart-67a4904c-4e83-4654-824e-83d5b3f97151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331714253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3331714253
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1596091457
Short name T493
Test name
Test status
Simulation time 82884397646 ps
CPU time 166.05 seconds
Started Jul 03 05:44:35 PM PDT 24
Finished Jul 03 05:47:21 PM PDT 24
Peak memory 199864 kb
Host smart-8b92622f-46e3-40e2-91bd-0baf9d730237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596091457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1596091457
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.67352472
Short name T358
Test name
Test status
Simulation time 13523050 ps
CPU time 0.56 seconds
Started Jul 03 05:44:40 PM PDT 24
Finished Jul 03 05:44:41 PM PDT 24
Peak memory 195248 kb
Host smart-d9870e28-51d5-4632-8971-0b02893ce763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67352472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.67352472
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1244333280
Short name T331
Test name
Test status
Simulation time 87938891948 ps
CPU time 138.95 seconds
Started Jul 03 05:44:34 PM PDT 24
Finished Jul 03 05:46:53 PM PDT 24
Peak memory 199884 kb
Host smart-bce32505-a5a8-4680-9782-e5312e13ba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244333280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1244333280
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1385287508
Short name T411
Test name
Test status
Simulation time 10935329124 ps
CPU time 18.5 seconds
Started Jul 03 05:44:36 PM PDT 24
Finished Jul 03 05:44:55 PM PDT 24
Peak memory 199968 kb
Host smart-d602ca91-c72a-4d9c-b023-6bb5be81215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385287508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1385287508
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1756380066
Short name T226
Test name
Test status
Simulation time 29497706916 ps
CPU time 12.14 seconds
Started Jul 03 05:44:37 PM PDT 24
Finished Jul 03 05:44:50 PM PDT 24
Peak memory 199972 kb
Host smart-cdd8c563-0646-4bc6-bff5-a385abc30423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756380066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1756380066
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2035075256
Short name T18
Test name
Test status
Simulation time 58294822739 ps
CPU time 112.28 seconds
Started Jul 03 05:44:36 PM PDT 24
Finished Jul 03 05:46:29 PM PDT 24
Peak memory 199912 kb
Host smart-129450fd-a696-4828-89ae-3c124233da76
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035075256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2035075256
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4178875591
Short name T814
Test name
Test status
Simulation time 86011654455 ps
CPU time 386.59 seconds
Started Jul 03 05:44:35 PM PDT 24
Finished Jul 03 05:51:02 PM PDT 24
Peak memory 199936 kb
Host smart-8b7c6b79-0bef-4030-a954-58d758269f08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178875591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4178875591
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.495517153
Short name T654
Test name
Test status
Simulation time 9094803014 ps
CPU time 6.02 seconds
Started Jul 03 05:44:37 PM PDT 24
Finished Jul 03 05:44:43 PM PDT 24
Peak memory 199888 kb
Host smart-dc883a84-ead2-4093-bdac-bc0dd3c9dba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495517153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.495517153
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.2359951940
Short name T694
Test name
Test status
Simulation time 20303708180 ps
CPU time 1207.87 seconds
Started Jul 03 05:44:39 PM PDT 24
Finished Jul 03 06:04:48 PM PDT 24
Peak memory 199884 kb
Host smart-dd33bb5c-0fe0-4640-9902-696a56bf2584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359951940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2359951940
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3277986453
Short name T1031
Test name
Test status
Simulation time 5045317633 ps
CPU time 10.5 seconds
Started Jul 03 05:44:35 PM PDT 24
Finished Jul 03 05:44:45 PM PDT 24
Peak memory 199484 kb
Host smart-7aa6c717-b570-41ba-86c4-cf8e8753c310
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277986453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3277986453
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2569606770
Short name T834
Test name
Test status
Simulation time 98726086943 ps
CPU time 36.04 seconds
Started Jul 03 05:44:36 PM PDT 24
Finished Jul 03 05:45:12 PM PDT 24
Peak memory 199764 kb
Host smart-d56a9731-0bd4-4d4b-a6d4-d3c3bc851f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569606770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2569606770
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3800213907
Short name T859
Test name
Test status
Simulation time 6025998596 ps
CPU time 4.64 seconds
Started Jul 03 05:44:37 PM PDT 24
Finished Jul 03 05:44:42 PM PDT 24
Peak memory 195960 kb
Host smart-4e03afc4-18d9-4aeb-9ab2-655206f47da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800213907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3800213907
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1317172523
Short name T804
Test name
Test status
Simulation time 6173048002 ps
CPU time 16.83 seconds
Started Jul 03 05:44:35 PM PDT 24
Finished Jul 03 05:44:52 PM PDT 24
Peak memory 199524 kb
Host smart-e9eaa189-e916-4bf3-8942-051a86e69cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317172523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1317172523
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2165645691
Short name T808
Test name
Test status
Simulation time 328458881905 ps
CPU time 2393.13 seconds
Started Jul 03 05:44:40 PM PDT 24
Finished Jul 03 06:24:34 PM PDT 24
Peak memory 199920 kb
Host smart-d0044dc4-ddfd-47a0-8552-f24287b7c5ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165645691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2165645691
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3613584152
Short name T626
Test name
Test status
Simulation time 7600915711 ps
CPU time 14.94 seconds
Started Jul 03 05:44:35 PM PDT 24
Finished Jul 03 05:44:50 PM PDT 24
Peak memory 199868 kb
Host smart-35251be6-54c2-4657-bd82-f7c291eda6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613584152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3613584152
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.380551783
Short name T643
Test name
Test status
Simulation time 89057938735 ps
CPU time 177.78 seconds
Started Jul 03 05:44:37 PM PDT 24
Finished Jul 03 05:47:35 PM PDT 24
Peak memory 199884 kb
Host smart-ac1d4a90-d7f6-47f3-94e8-59ea2e6941fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380551783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.380551783
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1412070394
Short name T449
Test name
Test status
Simulation time 50145591 ps
CPU time 0.54 seconds
Started Jul 03 05:44:44 PM PDT 24
Finished Jul 03 05:44:44 PM PDT 24
Peak memory 194732 kb
Host smart-7ff5b8f2-46bb-4628-bc6b-ab4579c5d165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412070394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1412070394
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.746807754
Short name T616
Test name
Test status
Simulation time 17911600838 ps
CPU time 29.6 seconds
Started Jul 03 05:44:39 PM PDT 24
Finished Jul 03 05:45:09 PM PDT 24
Peak memory 199952 kb
Host smart-c4f743ad-c6bd-42de-b762-9f83787bea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746807754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.746807754
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.352966908
Short name T1047
Test name
Test status
Simulation time 28001223089 ps
CPU time 11.25 seconds
Started Jul 03 05:44:39 PM PDT 24
Finished Jul 03 05:44:51 PM PDT 24
Peak memory 199872 kb
Host smart-97f2d779-4978-4500-8d2d-2a2ea95b93f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352966908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.352966908
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1441627241
Short name T164
Test name
Test status
Simulation time 128799340683 ps
CPU time 61.38 seconds
Started Jul 03 05:44:41 PM PDT 24
Finished Jul 03 05:45:42 PM PDT 24
Peak memory 199928 kb
Host smart-2f1fc3bf-e02e-41ec-8a38-741688a23770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441627241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1441627241
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.48710830
Short name T310
Test name
Test status
Simulation time 16586558991 ps
CPU time 28.94 seconds
Started Jul 03 05:44:40 PM PDT 24
Finished Jul 03 05:45:09 PM PDT 24
Peak memory 199656 kb
Host smart-d1b00479-2808-4529-b26c-d36302f8f187
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48710830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.48710830
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1870920512
Short name T862
Test name
Test status
Simulation time 108354390319 ps
CPU time 170.25 seconds
Started Jul 03 05:44:40 PM PDT 24
Finished Jul 03 05:47:31 PM PDT 24
Peak memory 199932 kb
Host smart-b113d432-bddd-44cf-a75f-d548f24a95f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870920512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1870920512
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2691364296
Short name T438
Test name
Test status
Simulation time 7275660346 ps
CPU time 4.38 seconds
Started Jul 03 05:44:38 PM PDT 24
Finished Jul 03 05:44:43 PM PDT 24
Peak memory 199584 kb
Host smart-0bbe9b8f-b791-4898-bb58-c6ca824f5d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691364296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2691364296
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.4277084213
Short name T701
Test name
Test status
Simulation time 5317196746 ps
CPU time 311.22 seconds
Started Jul 03 05:44:39 PM PDT 24
Finished Jul 03 05:49:50 PM PDT 24
Peak memory 199936 kb
Host smart-dfb4928f-33ec-4217-a21f-c308b9b4d207
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277084213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.4277084213
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1253115281
Short name T692
Test name
Test status
Simulation time 1801399418 ps
CPU time 7.96 seconds
Started Jul 03 05:44:40 PM PDT 24
Finished Jul 03 05:44:49 PM PDT 24
Peak memory 197964 kb
Host smart-98642e7b-8c62-4e1f-9c9c-165d1153f424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1253115281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1253115281
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1273083848
Short name T942
Test name
Test status
Simulation time 31122675527 ps
CPU time 16.88 seconds
Started Jul 03 05:44:40 PM PDT 24
Finished Jul 03 05:44:57 PM PDT 24
Peak memory 199964 kb
Host smart-63471c83-3409-4611-b064-f9c6e0aedf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273083848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1273083848
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.824261728
Short name T642
Test name
Test status
Simulation time 6300257419 ps
CPU time 1.53 seconds
Started Jul 03 05:44:37 PM PDT 24
Finished Jul 03 05:44:39 PM PDT 24
Peak memory 196172 kb
Host smart-4c473399-577d-41ed-9227-15067c11e4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824261728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.824261728
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1239781475
Short name T469
Test name
Test status
Simulation time 693226523 ps
CPU time 2.66 seconds
Started Jul 03 05:44:39 PM PDT 24
Finished Jul 03 05:44:42 PM PDT 24
Peak memory 199872 kb
Host smart-f4d9da35-ff7b-44d8-979b-03e284733211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239781475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1239781475
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3162232662
Short name T946
Test name
Test status
Simulation time 11741335173 ps
CPU time 36.66 seconds
Started Jul 03 05:44:41 PM PDT 24
Finished Jul 03 05:45:18 PM PDT 24
Peak memory 199964 kb
Host smart-3899cb6b-228d-4139-85bf-cfec898548a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162232662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3162232662
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2605409566
Short name T232
Test name
Test status
Simulation time 104335029284 ps
CPU time 30.58 seconds
Started Jul 03 05:44:39 PM PDT 24
Finished Jul 03 05:45:10 PM PDT 24
Peak memory 199940 kb
Host smart-a2781a77-bd27-4b59-b6ec-7eae7fb9e847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605409566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2605409566
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2733953675
Short name T719
Test name
Test status
Simulation time 93307033 ps
CPU time 0.57 seconds
Started Jul 03 05:44:42 PM PDT 24
Finished Jul 03 05:44:43 PM PDT 24
Peak memory 195280 kb
Host smart-b04571fc-dd9d-4485-a5f8-2e28e178c137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733953675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2733953675
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1410738244
Short name T905
Test name
Test status
Simulation time 188695648672 ps
CPU time 75.47 seconds
Started Jul 03 05:44:47 PM PDT 24
Finished Jul 03 05:46:03 PM PDT 24
Peak memory 199912 kb
Host smart-20f56be2-320f-498b-a6af-edc5fb9d4777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410738244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1410738244
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1066767809
Short name T262
Test name
Test status
Simulation time 24536091595 ps
CPU time 21.53 seconds
Started Jul 03 05:44:42 PM PDT 24
Finished Jul 03 05:45:04 PM PDT 24
Peak memory 199936 kb
Host smart-482edbce-ff08-4353-af91-8369c4bf845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066767809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1066767809
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.522043954
Short name T189
Test name
Test status
Simulation time 48593815493 ps
CPU time 89.44 seconds
Started Jul 03 05:44:41 PM PDT 24
Finished Jul 03 05:46:10 PM PDT 24
Peak memory 199940 kb
Host smart-291faea8-f17b-4adf-94e9-1bd4f581ac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522043954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.522043954
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.4158856611
Short name T1039
Test name
Test status
Simulation time 146906813598 ps
CPU time 55.76 seconds
Started Jul 03 05:44:44 PM PDT 24
Finished Jul 03 05:45:40 PM PDT 24
Peak memory 196196 kb
Host smart-076694ae-23cc-49c9-93e8-64c4e2f8023a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158856611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4158856611
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.158205411
Short name T398
Test name
Test status
Simulation time 114725282456 ps
CPU time 440.4 seconds
Started Jul 03 05:44:40 PM PDT 24
Finished Jul 03 05:52:01 PM PDT 24
Peak memory 199932 kb
Host smart-f53f692f-cc23-488d-bb80-8178d4e90c35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158205411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.158205411
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2487458630
Short name T353
Test name
Test status
Simulation time 9921379323 ps
CPU time 19.36 seconds
Started Jul 03 05:44:45 PM PDT 24
Finished Jul 03 05:45:05 PM PDT 24
Peak memory 198680 kb
Host smart-8fd6b0a8-49f0-4bb8-a8fb-cf4f1482ecc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487458630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2487458630
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3249534387
Short name T471
Test name
Test status
Simulation time 2979429124 ps
CPU time 5.01 seconds
Started Jul 03 05:44:43 PM PDT 24
Finished Jul 03 05:44:48 PM PDT 24
Peak memory 197284 kb
Host smart-133972f7-5290-47a6-ae66-51ba2b7212f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249534387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3249534387
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1933882730
Short name T931
Test name
Test status
Simulation time 20605724915 ps
CPU time 1056.6 seconds
Started Jul 03 05:44:42 PM PDT 24
Finished Jul 03 06:02:18 PM PDT 24
Peak memory 199920 kb
Host smart-396e3dd5-2921-4d5e-aac7-e20091a59045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933882730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1933882730
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.233143783
Short name T559
Test name
Test status
Simulation time 7465869725 ps
CPU time 63.69 seconds
Started Jul 03 05:44:45 PM PDT 24
Finished Jul 03 05:45:49 PM PDT 24
Peak memory 198208 kb
Host smart-b01f6052-9634-4cbe-b7cb-bc422005c2af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233143783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.233143783
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2304711586
Short name T316
Test name
Test status
Simulation time 81573442425 ps
CPU time 54.55 seconds
Started Jul 03 05:44:45 PM PDT 24
Finished Jul 03 05:45:39 PM PDT 24
Peak memory 199844 kb
Host smart-5d20aaed-cb49-4d9a-92e5-7a2524daf3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304711586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2304711586
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.654928607
Short name T880
Test name
Test status
Simulation time 4235947957 ps
CPU time 6.72 seconds
Started Jul 03 05:44:43 PM PDT 24
Finished Jul 03 05:44:50 PM PDT 24
Peak memory 196452 kb
Host smart-7bf1620f-87dd-4365-a335-78249cccc917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654928607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.654928607
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1210535598
Short name T479
Test name
Test status
Simulation time 5315807346 ps
CPU time 6.99 seconds
Started Jul 03 05:44:41 PM PDT 24
Finished Jul 03 05:44:48 PM PDT 24
Peak memory 199156 kb
Host smart-6736f6e8-e92d-4fdb-8e0d-779abb43632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210535598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1210535598
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.479937792
Short name T646
Test name
Test status
Simulation time 154719819182 ps
CPU time 333.48 seconds
Started Jul 03 05:44:46 PM PDT 24
Finished Jul 03 05:50:20 PM PDT 24
Peak memory 199904 kb
Host smart-fcfe9a9f-34fa-4cfb-92f1-0ac34107c8b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479937792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.479937792
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3995532515
Short name T394
Test name
Test status
Simulation time 6218909439 ps
CPU time 20.65 seconds
Started Jul 03 05:44:43 PM PDT 24
Finished Jul 03 05:45:04 PM PDT 24
Peak memory 199692 kb
Host smart-42317939-efdc-43a0-9a47-6330e41f8375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995532515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3995532515
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2163313006
Short name T969
Test name
Test status
Simulation time 138233827987 ps
CPU time 309.29 seconds
Started Jul 03 05:44:43 PM PDT 24
Finished Jul 03 05:49:53 PM PDT 24
Peak memory 199996 kb
Host smart-640fc3ed-7c8c-40df-b127-8b3acf487d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163313006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2163313006
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2245960614
Short name T476
Test name
Test status
Simulation time 14882462 ps
CPU time 0.55 seconds
Started Jul 03 05:44:47 PM PDT 24
Finished Jul 03 05:44:48 PM PDT 24
Peak memory 195572 kb
Host smart-8f3efbbf-ed11-4932-8167-8b8e45c56736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245960614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2245960614
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.256088799
Short name T330
Test name
Test status
Simulation time 65461834066 ps
CPU time 107.27 seconds
Started Jul 03 05:44:42 PM PDT 24
Finished Jul 03 05:46:30 PM PDT 24
Peak memory 199936 kb
Host smart-7b8a697b-464a-4993-a6bb-19f15881d586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256088799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.256088799
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.445829825
Short name T645
Test name
Test status
Simulation time 46689014300 ps
CPU time 33.53 seconds
Started Jul 03 05:44:43 PM PDT 24
Finished Jul 03 05:45:17 PM PDT 24
Peak memory 199908 kb
Host smart-5d4dc860-6fe8-409f-8630-ed7c52644d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445829825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.445829825
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2687337012
Short name T877
Test name
Test status
Simulation time 20392014342 ps
CPU time 30.93 seconds
Started Jul 03 05:44:43 PM PDT 24
Finished Jul 03 05:45:14 PM PDT 24
Peak memory 200008 kb
Host smart-69442b5c-ab4e-4dba-8fbb-02725db547c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687337012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2687337012
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2864066709
Short name T762
Test name
Test status
Simulation time 35270438240 ps
CPU time 32.45 seconds
Started Jul 03 05:44:47 PM PDT 24
Finished Jul 03 05:45:20 PM PDT 24
Peak memory 200004 kb
Host smart-0af922ce-4d3e-4c28-b2fe-34546f6bf576
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864066709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2864066709
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3456185804
Short name T661
Test name
Test status
Simulation time 89032579231 ps
CPU time 160.84 seconds
Started Jul 03 05:44:47 PM PDT 24
Finished Jul 03 05:47:28 PM PDT 24
Peak memory 199944 kb
Host smart-75923d59-8188-4ba4-9cbb-47e60473b564
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3456185804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3456185804
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2629939170
Short name T439
Test name
Test status
Simulation time 7537143754 ps
CPU time 6.96 seconds
Started Jul 03 05:44:46 PM PDT 24
Finished Jul 03 05:44:53 PM PDT 24
Peak memory 199444 kb
Host smart-25eae461-442c-4ab0-83c9-bd37720e78eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629939170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2629939170
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1688417404
Short name T530
Test name
Test status
Simulation time 10324552274 ps
CPU time 13.84 seconds
Started Jul 03 05:44:48 PM PDT 24
Finished Jul 03 05:45:02 PM PDT 24
Peak memory 197140 kb
Host smart-9ee2b243-32a5-4da1-bbe0-4088fea3d88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688417404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1688417404
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.4008263554
Short name T268
Test name
Test status
Simulation time 20905430314 ps
CPU time 1176.59 seconds
Started Jul 03 05:44:48 PM PDT 24
Finished Jul 03 06:04:25 PM PDT 24
Peak memory 199788 kb
Host smart-085d041e-c211-44c4-ac0d-b94842f34e42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4008263554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4008263554
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1656712961
Short name T507
Test name
Test status
Simulation time 2110321733 ps
CPU time 9.51 seconds
Started Jul 03 05:44:48 PM PDT 24
Finished Jul 03 05:44:58 PM PDT 24
Peak memory 198176 kb
Host smart-3d65c0b3-cf84-4fc5-a9ce-c4ceca1580d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656712961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1656712961
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.343921602
Short name T461
Test name
Test status
Simulation time 41139933326 ps
CPU time 16.03 seconds
Started Jul 03 05:44:47 PM PDT 24
Finished Jul 03 05:45:04 PM PDT 24
Peak memory 199924 kb
Host smart-7b0a8245-bfd3-4463-a758-65bf9e2a7155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343921602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.343921602
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1401412503
Short name T794
Test name
Test status
Simulation time 76985407603 ps
CPU time 114.62 seconds
Started Jul 03 05:44:47 PM PDT 24
Finished Jul 03 05:46:42 PM PDT 24
Peak memory 196184 kb
Host smart-4cf22ccf-d112-4535-b233-6ec1fd15f033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401412503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1401412503
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.880336293
Short name T709
Test name
Test status
Simulation time 6053952197 ps
CPU time 15.63 seconds
Started Jul 03 05:44:43 PM PDT 24
Finished Jul 03 05:44:59 PM PDT 24
Peak memory 199940 kb
Host smart-a9740a5e-d404-4e94-9a44-6616bc86b372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880336293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.880336293
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2060464063
Short name T139
Test name
Test status
Simulation time 228161439014 ps
CPU time 90.35 seconds
Started Jul 03 05:44:47 PM PDT 24
Finished Jul 03 05:46:17 PM PDT 24
Peak memory 199920 kb
Host smart-9b10a71b-645f-45aa-900a-a8fae017b3b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060464063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2060464063
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3732796518
Short name T285
Test name
Test status
Simulation time 7777216808 ps
CPU time 7.12 seconds
Started Jul 03 05:44:48 PM PDT 24
Finished Jul 03 05:44:55 PM PDT 24
Peak memory 199848 kb
Host smart-b6d936d0-5a25-455e-a0b7-64203f49aa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732796518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3732796518
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1351951257
Short name T608
Test name
Test status
Simulation time 52373159626 ps
CPU time 82.85 seconds
Started Jul 03 05:44:47 PM PDT 24
Finished Jul 03 05:46:10 PM PDT 24
Peak memory 199916 kb
Host smart-dfb63e6d-ce7c-457f-b07d-a639a020dd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351951257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1351951257
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1155990522
Short name T595
Test name
Test status
Simulation time 14991827 ps
CPU time 0.58 seconds
Started Jul 03 05:44:49 PM PDT 24
Finished Jul 03 05:44:50 PM PDT 24
Peak memory 195288 kb
Host smart-e4e420d4-06d9-41d2-9225-838f3ce7428f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155990522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1155990522
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3511549522
Short name T951
Test name
Test status
Simulation time 19545441283 ps
CPU time 20.45 seconds
Started Jul 03 05:44:48 PM PDT 24
Finished Jul 03 05:45:08 PM PDT 24
Peak memory 199828 kb
Host smart-bdd116c0-289a-4787-9c92-3af97e8e2ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511549522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3511549522
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1046292456
Short name T618
Test name
Test status
Simulation time 31196382207 ps
CPU time 25.03 seconds
Started Jul 03 05:44:45 PM PDT 24
Finished Jul 03 05:45:10 PM PDT 24
Peak memory 199836 kb
Host smart-fe4cec64-b5f5-4a1f-9835-8092791e4353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046292456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1046292456
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2137297288
Short name T183
Test name
Test status
Simulation time 89123517926 ps
CPU time 71.06 seconds
Started Jul 03 05:44:49 PM PDT 24
Finished Jul 03 05:46:00 PM PDT 24
Peak memory 199948 kb
Host smart-4e9fdf93-6810-454d-98dd-e000249eee6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137297288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2137297288
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.4019376269
Short name T284
Test name
Test status
Simulation time 30986586780 ps
CPU time 23.49 seconds
Started Jul 03 05:44:46 PM PDT 24
Finished Jul 03 05:45:10 PM PDT 24
Peak memory 199652 kb
Host smart-bd3af37c-fc25-401f-8b03-11a6765b2e69
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019376269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.4019376269
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.110274161
Short name T355
Test name
Test status
Simulation time 67176155795 ps
CPU time 96.14 seconds
Started Jul 03 05:44:50 PM PDT 24
Finished Jul 03 05:46:26 PM PDT 24
Peak memory 199992 kb
Host smart-5a65f0eb-b623-4573-b3f3-d155419f170a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110274161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.110274161
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3664546737
Short name T374
Test name
Test status
Simulation time 4207712691 ps
CPU time 2.93 seconds
Started Jul 03 05:44:45 PM PDT 24
Finished Jul 03 05:44:48 PM PDT 24
Peak memory 199676 kb
Host smart-46fd3c7a-b9a4-4346-ac8c-e9f2cef85147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664546737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3664546737
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.688130394
Short name T939
Test name
Test status
Simulation time 16141288668 ps
CPU time 235.03 seconds
Started Jul 03 05:44:50 PM PDT 24
Finished Jul 03 05:48:46 PM PDT 24
Peak memory 199844 kb
Host smart-484de655-31da-456c-963d-13205c4a7cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688130394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.688130394
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1030978380
Short name T556
Test name
Test status
Simulation time 5485245915 ps
CPU time 5.02 seconds
Started Jul 03 05:44:47 PM PDT 24
Finished Jul 03 05:44:53 PM PDT 24
Peak memory 198056 kb
Host smart-20adb1c7-9f31-4823-8c57-4a1508f4d65e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030978380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1030978380
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1458346724
Short name T923
Test name
Test status
Simulation time 90708154138 ps
CPU time 127.16 seconds
Started Jul 03 05:44:45 PM PDT 24
Finished Jul 03 05:46:53 PM PDT 24
Peak memory 199916 kb
Host smart-dd61944d-4503-4895-8759-1c9db8fcf548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458346724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1458346724
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1333964811
Short name T416
Test name
Test status
Simulation time 522077928 ps
CPU time 1.42 seconds
Started Jul 03 05:44:48 PM PDT 24
Finished Jul 03 05:44:50 PM PDT 24
Peak memory 195400 kb
Host smart-3746f299-ecd2-4a2b-b8db-c38258b8ee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333964811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1333964811
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1553749056
Short name T356
Test name
Test status
Simulation time 426496280 ps
CPU time 2.26 seconds
Started Jul 03 05:44:46 PM PDT 24
Finished Jul 03 05:44:48 PM PDT 24
Peak memory 198952 kb
Host smart-11569957-cb89-4b65-a37d-e0366f4cfd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553749056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1553749056
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2345413355
Short name T736
Test name
Test status
Simulation time 34667227787 ps
CPU time 136.88 seconds
Started Jul 03 05:44:49 PM PDT 24
Finished Jul 03 05:47:07 PM PDT 24
Peak memory 199984 kb
Host smart-abfcc400-097f-49b7-8c04-6249a8120c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345413355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2345413355
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.672217004
Short name T653
Test name
Test status
Simulation time 93448971726 ps
CPU time 485.03 seconds
Started Jul 03 05:44:54 PM PDT 24
Finished Jul 03 05:52:59 PM PDT 24
Peak memory 214668 kb
Host smart-1889889b-7597-4fea-b244-e061b3ea6614
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672217004 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.672217004
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1365988131
Short name T774
Test name
Test status
Simulation time 15544164585 ps
CPU time 17.51 seconds
Started Jul 03 05:44:49 PM PDT 24
Finished Jul 03 05:45:07 PM PDT 24
Peak memory 200004 kb
Host smart-7b4df17f-e0ec-4039-ad44-4ae5621355e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365988131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1365988131
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1600259805
Short name T444
Test name
Test status
Simulation time 14628116080 ps
CPU time 7.87 seconds
Started Jul 03 05:44:46 PM PDT 24
Finished Jul 03 05:44:54 PM PDT 24
Peak memory 199980 kb
Host smart-4e21ca9d-07b8-4db1-bacf-0bfd7c0c59ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600259805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1600259805
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.4009080018
Short name T925
Test name
Test status
Simulation time 14981664 ps
CPU time 0.57 seconds
Started Jul 03 05:44:57 PM PDT 24
Finished Jul 03 05:44:58 PM PDT 24
Peak memory 195336 kb
Host smart-8756de9f-d0c9-4bc0-8bbd-0a35e3c2a69f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009080018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.4009080018
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1972836832
Short name T657
Test name
Test status
Simulation time 12037203028 ps
CPU time 18.35 seconds
Started Jul 03 05:44:51 PM PDT 24
Finished Jul 03 05:45:09 PM PDT 24
Peak memory 199928 kb
Host smart-470d611b-06e9-4e21-841f-4a6cfcbf3326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972836832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1972836832
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.4078505950
Short name T698
Test name
Test status
Simulation time 32513931581 ps
CPU time 47.09 seconds
Started Jul 03 05:44:50 PM PDT 24
Finished Jul 03 05:45:37 PM PDT 24
Peak memory 199816 kb
Host smart-4dcfa495-237a-468d-943f-c148a0c61edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078505950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4078505950
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1061466599
Short name T1007
Test name
Test status
Simulation time 110016645908 ps
CPU time 324.6 seconds
Started Jul 03 05:44:49 PM PDT 24
Finished Jul 03 05:50:14 PM PDT 24
Peak memory 199972 kb
Host smart-52dafb34-5f85-45a6-9b9f-e2d4a10b040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061466599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1061466599
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3464167635
Short name T708
Test name
Test status
Simulation time 53323771343 ps
CPU time 35.47 seconds
Started Jul 03 05:44:50 PM PDT 24
Finished Jul 03 05:45:26 PM PDT 24
Peak memory 198840 kb
Host smart-3e466eda-7f99-47f8-9552-eab3e4fbcd3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464167635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3464167635
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1960749102
Short name T237
Test name
Test status
Simulation time 187170885265 ps
CPU time 333.43 seconds
Started Jul 03 05:44:55 PM PDT 24
Finished Jul 03 05:50:28 PM PDT 24
Peak memory 199916 kb
Host smart-9f94bcf6-0ddc-42c9-9a73-dc4840c0bc1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960749102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1960749102
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1404636561
Short name T807
Test name
Test status
Simulation time 5984780289 ps
CPU time 12.12 seconds
Started Jul 03 05:44:56 PM PDT 24
Finished Jul 03 05:45:08 PM PDT 24
Peak memory 199756 kb
Host smart-23117234-6801-4957-b4b7-3b004bc4631c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404636561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1404636561
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.4108676669
Short name T521
Test name
Test status
Simulation time 4114042024 ps
CPU time 242.54 seconds
Started Jul 03 05:44:56 PM PDT 24
Finished Jul 03 05:48:59 PM PDT 24
Peak memory 199920 kb
Host smart-2c450caa-6ec9-4a95-ad0f-0c10e902a83e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4108676669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.4108676669
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1125075739
Short name T581
Test name
Test status
Simulation time 7417566077 ps
CPU time 15.43 seconds
Started Jul 03 05:44:52 PM PDT 24
Finished Jul 03 05:45:07 PM PDT 24
Peak memory 199016 kb
Host smart-2ce90c6f-2bb5-4d8b-a5c0-aee2d809e112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125075739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1125075739
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2996845738
Short name T515
Test name
Test status
Simulation time 23837322468 ps
CPU time 36.34 seconds
Started Jul 03 05:44:49 PM PDT 24
Finished Jul 03 05:45:26 PM PDT 24
Peak memory 199576 kb
Host smart-893a96ab-ddfb-4f1f-9283-ced2f3a22b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996845738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2996845738
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.459807345
Short name T380
Test name
Test status
Simulation time 6706513816 ps
CPU time 1.78 seconds
Started Jul 03 05:44:51 PM PDT 24
Finished Jul 03 05:44:53 PM PDT 24
Peak memory 196016 kb
Host smart-1eec5b6f-11d2-48a6-874b-c6ac719cc383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459807345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.459807345
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.115745265
Short name T944
Test name
Test status
Simulation time 461999087 ps
CPU time 2.01 seconds
Started Jul 03 05:44:48 PM PDT 24
Finished Jul 03 05:44:50 PM PDT 24
Peak memory 199416 kb
Host smart-6ae391e1-ee36-4051-b885-054567b29fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115745265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.115745265
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2869344323
Short name T408
Test name
Test status
Simulation time 1031775590 ps
CPU time 1.38 seconds
Started Jul 03 05:44:50 PM PDT 24
Finished Jul 03 05:44:52 PM PDT 24
Peak memory 198372 kb
Host smart-cd2bb723-a4ef-4b6e-8da3-fe195088e956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869344323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2869344323
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1459044919
Short name T673
Test name
Test status
Simulation time 117518762081 ps
CPU time 48.78 seconds
Started Jul 03 05:44:50 PM PDT 24
Finished Jul 03 05:45:40 PM PDT 24
Peak memory 199904 kb
Host smart-1263f4f1-00f9-4461-8b37-13c1c7552a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459044919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1459044919
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1952737493
Short name T936
Test name
Test status
Simulation time 69875000 ps
CPU time 0.53 seconds
Started Jul 03 05:43:09 PM PDT 24
Finished Jul 03 05:43:10 PM PDT 24
Peak memory 195304 kb
Host smart-e1cf8121-5116-4a7b-bd8b-698e0f3406b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952737493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1952737493
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.4046860768
Short name T491
Test name
Test status
Simulation time 22562509787 ps
CPU time 31.23 seconds
Started Jul 03 05:43:08 PM PDT 24
Finished Jul 03 05:43:39 PM PDT 24
Peak memory 199884 kb
Host smart-e35ac15f-70ea-42b9-b124-7addaed80901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046860768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.4046860768
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.836672283
Short name T586
Test name
Test status
Simulation time 166649509234 ps
CPU time 318.97 seconds
Started Jul 03 05:43:07 PM PDT 24
Finished Jul 03 05:48:26 PM PDT 24
Peak memory 199856 kb
Host smart-380db220-a119-4e37-95e5-7795f3307095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836672283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.836672283
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1200116364
Short name T347
Test name
Test status
Simulation time 123155265633 ps
CPU time 54.24 seconds
Started Jul 03 05:43:07 PM PDT 24
Finished Jul 03 05:44:02 PM PDT 24
Peak memory 199852 kb
Host smart-ad78da0d-e7a1-449a-a5d1-b925e2e72003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200116364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1200116364
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1874567626
Short name T833
Test name
Test status
Simulation time 19137228667 ps
CPU time 8.56 seconds
Started Jul 03 05:43:08 PM PDT 24
Finished Jul 03 05:43:17 PM PDT 24
Peak memory 197536 kb
Host smart-39e43f50-ce72-4d3a-8f6d-0bf1680adfa6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874567626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1874567626
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1852238776
Short name T999
Test name
Test status
Simulation time 134693061493 ps
CPU time 581.52 seconds
Started Jul 03 05:43:03 PM PDT 24
Finished Jul 03 05:52:45 PM PDT 24
Peak memory 199944 kb
Host smart-e3df8b1f-6d1d-4df9-b719-43d2fbc72078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1852238776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1852238776
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1569271470
Short name T733
Test name
Test status
Simulation time 6291520549 ps
CPU time 4.55 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:43:17 PM PDT 24
Peak memory 198088 kb
Host smart-fb9fde1b-21ec-447b-9ada-a088d99b0b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569271470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1569271470
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.2137099501
Short name T723
Test name
Test status
Simulation time 15125457478 ps
CPU time 644.64 seconds
Started Jul 03 05:43:09 PM PDT 24
Finished Jul 03 05:53:54 PM PDT 24
Peak memory 200020 kb
Host smart-157851b6-6a1f-4084-b59d-467f16817dec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137099501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2137099501
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2855826899
Short name T382
Test name
Test status
Simulation time 4872541147 ps
CPU time 46.72 seconds
Started Jul 03 05:43:10 PM PDT 24
Finished Jul 03 05:43:57 PM PDT 24
Peak memory 199208 kb
Host smart-aa2e319a-03fa-4933-ab28-5f86dbe34a48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2855826899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2855826899
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.87995757
Short name T367
Test name
Test status
Simulation time 20596828241 ps
CPU time 7.83 seconds
Started Jul 03 05:43:03 PM PDT 24
Finished Jul 03 05:43:12 PM PDT 24
Peak memory 199796 kb
Host smart-3abc0d45-6423-424c-b110-92339335b156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87995757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.87995757
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3698583379
Short name T319
Test name
Test status
Simulation time 4412029900 ps
CPU time 2.27 seconds
Started Jul 03 05:43:08 PM PDT 24
Finished Jul 03 05:43:11 PM PDT 24
Peak memory 196260 kb
Host smart-a2357868-7a2d-4dcf-be91-ec398dd98973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698583379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3698583379
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1571978239
Short name T760
Test name
Test status
Simulation time 276931978 ps
CPU time 1.35 seconds
Started Jul 03 05:43:10 PM PDT 24
Finished Jul 03 05:43:11 PM PDT 24
Peak memory 199256 kb
Host smart-34e3583d-1f63-40b4-b0f0-93e16fc60995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571978239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1571978239
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2068965810
Short name T308
Test name
Test status
Simulation time 44720599350 ps
CPU time 117.96 seconds
Started Jul 03 05:43:06 PM PDT 24
Finished Jul 03 05:45:04 PM PDT 24
Peak memory 215772 kb
Host smart-67694ad7-9725-40ae-a877-1c9907bd3463
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068965810 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2068965810
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3124343959
Short name T434
Test name
Test status
Simulation time 730028929 ps
CPU time 1.65 seconds
Started Jul 03 05:43:04 PM PDT 24
Finished Jul 03 05:43:06 PM PDT 24
Peak memory 198568 kb
Host smart-0e81f4d7-8ea6-46b7-993d-65bd7746682e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124343959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3124343959
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1841756412
Short name T402
Test name
Test status
Simulation time 47266069562 ps
CPU time 102.49 seconds
Started Jul 03 05:42:58 PM PDT 24
Finished Jul 03 05:44:41 PM PDT 24
Peak memory 199892 kb
Host smart-6b1dc568-0c53-4b38-966d-08629edd4aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841756412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1841756412
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3475269674
Short name T314
Test name
Test status
Simulation time 28446823490 ps
CPU time 16.04 seconds
Started Jul 03 05:44:57 PM PDT 24
Finished Jul 03 05:45:14 PM PDT 24
Peak memory 199944 kb
Host smart-e569fa68-22fe-4434-a789-f8afb214ee00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475269674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3475269674
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2034340415
Short name T282
Test name
Test status
Simulation time 146348659483 ps
CPU time 105.39 seconds
Started Jul 03 05:44:56 PM PDT 24
Finished Jul 03 05:46:42 PM PDT 24
Peak memory 199980 kb
Host smart-036cbb67-a341-45d2-868c-6c03dcfe5d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034340415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2034340415
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1424969183
Short name T757
Test name
Test status
Simulation time 52356796978 ps
CPU time 299.6 seconds
Started Jul 03 05:44:56 PM PDT 24
Finished Jul 03 05:49:56 PM PDT 24
Peak memory 216432 kb
Host smart-db73a3f5-af30-46d8-9940-037f9d3092ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424969183 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1424969183
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3297732109
Short name T566
Test name
Test status
Simulation time 48319325594 ps
CPU time 71.54 seconds
Started Jul 03 05:44:54 PM PDT 24
Finished Jul 03 05:46:06 PM PDT 24
Peak memory 199932 kb
Host smart-946d3eaf-a006-4576-9fff-00bc0101c91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297732109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3297732109
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1511976310
Short name T758
Test name
Test status
Simulation time 40018702484 ps
CPU time 10.43 seconds
Started Jul 03 05:44:53 PM PDT 24
Finished Jul 03 05:45:04 PM PDT 24
Peak memory 199904 kb
Host smart-c25572b4-1a59-40c8-b388-5ba8e314c802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511976310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1511976310
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2666412055
Short name T49
Test name
Test status
Simulation time 51685375196 ps
CPU time 1078.3 seconds
Started Jul 03 05:44:55 PM PDT 24
Finished Jul 03 06:02:53 PM PDT 24
Peak memory 216544 kb
Host smart-de78b5f7-4aa5-4b66-8fe1-8449b0c63fa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666412055 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2666412055
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2718412858
Short name T558
Test name
Test status
Simulation time 29761909718 ps
CPU time 60.7 seconds
Started Jul 03 05:44:55 PM PDT 24
Finished Jul 03 05:45:56 PM PDT 24
Peak memory 199968 kb
Host smart-dd73b6c3-da81-4cce-ab66-45a9d28a4534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718412858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2718412858
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3312250
Short name T46
Test name
Test status
Simulation time 26184829826 ps
CPU time 314.39 seconds
Started Jul 03 05:44:56 PM PDT 24
Finished Jul 03 05:50:11 PM PDT 24
Peak memory 208400 kb
Host smart-c068f4ea-f66b-4a01-9865-140a545e2566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312250 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3312250
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2195483655
Short name T224
Test name
Test status
Simulation time 74119117145 ps
CPU time 16.92 seconds
Started Jul 03 05:44:57 PM PDT 24
Finished Jul 03 05:45:14 PM PDT 24
Peak memory 200036 kb
Host smart-510114a4-1dc5-4965-8f6c-8a198d62e164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195483655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2195483655
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.203836170
Short name T1071
Test name
Test status
Simulation time 31226862414 ps
CPU time 307.94 seconds
Started Jul 03 05:44:55 PM PDT 24
Finished Jul 03 05:50:03 PM PDT 24
Peak memory 215844 kb
Host smart-00175715-8eda-4c3b-91d3-95153cbaacc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203836170 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.203836170
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.334474233
Short name T1063
Test name
Test status
Simulation time 76684736700 ps
CPU time 138.22 seconds
Started Jul 03 05:44:56 PM PDT 24
Finished Jul 03 05:47:14 PM PDT 24
Peak memory 199928 kb
Host smart-9d430176-e9d0-48dd-a4f4-55cdf234d1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334474233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.334474233
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1825549958
Short name T60
Test name
Test status
Simulation time 41332502279 ps
CPU time 1183.99 seconds
Started Jul 03 05:44:59 PM PDT 24
Finished Jul 03 06:04:43 PM PDT 24
Peak memory 208280 kb
Host smart-f75f43ff-edfa-4a16-8127-0d6aca0dafb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825549958 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1825549958
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2265284825
Short name T122
Test name
Test status
Simulation time 98786479064 ps
CPU time 41.32 seconds
Started Jul 03 05:44:58 PM PDT 24
Finished Jul 03 05:45:39 PM PDT 24
Peak memory 199968 kb
Host smart-4b05156e-8f0e-4d03-86ac-ce2bb8843f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265284825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2265284825
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1302984975
Short name T477
Test name
Test status
Simulation time 92449038259 ps
CPU time 745.26 seconds
Started Jul 03 05:44:53 PM PDT 24
Finished Jul 03 05:57:19 PM PDT 24
Peak memory 216484 kb
Host smart-e849ca53-9e8c-47c6-8d91-f5fff11ae91d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302984975 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1302984975
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1512617480
Short name T910
Test name
Test status
Simulation time 35336882645 ps
CPU time 14.76 seconds
Started Jul 03 05:44:59 PM PDT 24
Finished Jul 03 05:45:14 PM PDT 24
Peak memory 199924 kb
Host smart-4f01b356-434c-4bb8-a754-2e2725edff7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512617480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1512617480
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1482125369
Short name T557
Test name
Test status
Simulation time 14873868 ps
CPU time 0.55 seconds
Started Jul 03 05:43:07 PM PDT 24
Finished Jul 03 05:43:08 PM PDT 24
Peak memory 195308 kb
Host smart-6471905c-0176-4887-b2c7-8b7e8c05196b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482125369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1482125369
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3502255948
Short name T1072
Test name
Test status
Simulation time 82556433285 ps
CPU time 54.57 seconds
Started Jul 03 05:43:10 PM PDT 24
Finished Jul 03 05:44:05 PM PDT 24
Peak memory 200008 kb
Host smart-7fa653d6-e0cb-444c-a6d9-83d78b72e9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502255948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3502255948
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2545872174
Short name T350
Test name
Test status
Simulation time 64704359768 ps
CPU time 26.79 seconds
Started Jul 03 05:43:04 PM PDT 24
Finished Jul 03 05:43:31 PM PDT 24
Peak memory 199952 kb
Host smart-2086c9c5-e9b5-477a-9ba2-7db893c52053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545872174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2545872174
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.382606495
Short name T92
Test name
Test status
Simulation time 58849154870 ps
CPU time 32.87 seconds
Started Jul 03 05:43:20 PM PDT 24
Finished Jul 03 05:43:53 PM PDT 24
Peak memory 199904 kb
Host smart-e677610a-9ff0-48c8-9cb7-91081fad9f5e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382606495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.382606495
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2936961038
Short name T611
Test name
Test status
Simulation time 38945158891 ps
CPU time 221.64 seconds
Started Jul 03 05:43:13 PM PDT 24
Finished Jul 03 05:46:55 PM PDT 24
Peak memory 199984 kb
Host smart-8909e3f8-02f2-4729-8048-72956b64b081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936961038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2936961038
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1210954224
Short name T829
Test name
Test status
Simulation time 4789712678 ps
CPU time 8.97 seconds
Started Jul 03 05:43:01 PM PDT 24
Finished Jul 03 05:43:10 PM PDT 24
Peak memory 197424 kb
Host smart-aa7b8f73-1038-4dca-b921-75b977ec2bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210954224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1210954224
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.2605805187
Short name T962
Test name
Test status
Simulation time 7910168264 ps
CPU time 406.47 seconds
Started Jul 03 05:43:11 PM PDT 24
Finished Jul 03 05:49:58 PM PDT 24
Peak memory 200024 kb
Host smart-1608c5ad-43c3-4966-8015-a5fccbffd12c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605805187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2605805187
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1853117648
Short name T735
Test name
Test status
Simulation time 1999299625 ps
CPU time 8.82 seconds
Started Jul 03 05:43:10 PM PDT 24
Finished Jul 03 05:43:20 PM PDT 24
Peak memory 198104 kb
Host smart-c960605d-c913-4d48-bda6-5dc9f60acef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853117648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1853117648
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1764187305
Short name T769
Test name
Test status
Simulation time 1853711263 ps
CPU time 3.62 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:18 PM PDT 24
Peak memory 195448 kb
Host smart-b152a8c5-db80-47bb-8571-8a342f9d62fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764187305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1764187305
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3787499641
Short name T419
Test name
Test status
Simulation time 266382537 ps
CPU time 1.47 seconds
Started Jul 03 05:42:55 PM PDT 24
Finished Jul 03 05:42:57 PM PDT 24
Peak memory 199576 kb
Host smart-f1cc62f3-22c2-4842-9476-026ad9679482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787499641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3787499641
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.4177310994
Short name T179
Test name
Test status
Simulation time 29235103682 ps
CPU time 261.47 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:47:34 PM PDT 24
Peak memory 199892 kb
Host smart-e731aeda-8f9e-43f7-8d98-51df7a5ac33c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177310994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.4177310994
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2624672686
Short name T1013
Test name
Test status
Simulation time 113133219731 ps
CPU time 449.27 seconds
Started Jul 03 05:42:51 PM PDT 24
Finished Jul 03 05:50:20 PM PDT 24
Peak memory 215724 kb
Host smart-936d4898-c633-4747-973a-4f79145b670f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624672686 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2624672686
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.887408660
Short name T414
Test name
Test status
Simulation time 912799380 ps
CPU time 2.61 seconds
Started Jul 03 05:43:01 PM PDT 24
Finished Jul 03 05:43:04 PM PDT 24
Peak memory 198320 kb
Host smart-7e8ac224-509c-418e-a5a3-eaeb67d0d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887408660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.887408660
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3869861263
Short name T909
Test name
Test status
Simulation time 24892350572 ps
CPU time 9 seconds
Started Jul 03 05:43:05 PM PDT 24
Finished Jul 03 05:43:15 PM PDT 24
Peak memory 199956 kb
Host smart-fcc6c9f5-2a48-41fc-82f7-70eaf35ce185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869861263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3869861263
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2871015499
Short name T1018
Test name
Test status
Simulation time 246315356604 ps
CPU time 47.07 seconds
Started Jul 03 05:44:59 PM PDT 24
Finished Jul 03 05:45:47 PM PDT 24
Peak memory 199980 kb
Host smart-8629dfa7-ad82-4a96-9916-c3c87e83355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871015499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2871015499
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2761413070
Short name T333
Test name
Test status
Simulation time 20631443944 ps
CPU time 265.55 seconds
Started Jul 03 05:44:59 PM PDT 24
Finished Jul 03 05:49:25 PM PDT 24
Peak memory 208200 kb
Host smart-de09d89c-6c64-4327-9eef-d0f854e04ac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761413070 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2761413070
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.919878286
Short name T459
Test name
Test status
Simulation time 31954980085 ps
CPU time 19.09 seconds
Started Jul 03 05:45:01 PM PDT 24
Finished Jul 03 05:45:20 PM PDT 24
Peak memory 199992 kb
Host smart-8fbe036b-ef86-4f1f-8f46-5ff46d08bb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919878286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.919878286
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3368058010
Short name T599
Test name
Test status
Simulation time 20195739024 ps
CPU time 227.54 seconds
Started Jul 03 05:45:01 PM PDT 24
Finished Jul 03 05:48:48 PM PDT 24
Peak memory 215556 kb
Host smart-4a10e84d-5a11-451f-9b41-ce3fe6ad16ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368058010 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3368058010
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.172220436
Short name T867
Test name
Test status
Simulation time 91962825141 ps
CPU time 143.61 seconds
Started Jul 03 05:44:55 PM PDT 24
Finished Jul 03 05:47:19 PM PDT 24
Peak memory 199940 kb
Host smart-4082abe1-5a9d-4f0d-a92c-13a43333e77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172220436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.172220436
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1535237375
Short name T207
Test name
Test status
Simulation time 66936570519 ps
CPU time 24.26 seconds
Started Jul 03 05:45:00 PM PDT 24
Finished Jul 03 05:45:25 PM PDT 24
Peak memory 199992 kb
Host smart-769f5cb9-2a0b-403c-9d40-4cc71f2457e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535237375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1535237375
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.872049819
Short name T217
Test name
Test status
Simulation time 16625689396 ps
CPU time 30.63 seconds
Started Jul 03 05:44:59 PM PDT 24
Finished Jul 03 05:45:30 PM PDT 24
Peak memory 199952 kb
Host smart-102c6a4a-f87f-42a7-ae60-a9bbfa2696f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872049819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.872049819
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3223854716
Short name T775
Test name
Test status
Simulation time 37079769443 ps
CPU time 479.76 seconds
Started Jul 03 05:44:59 PM PDT 24
Finished Jul 03 05:52:59 PM PDT 24
Peak memory 216384 kb
Host smart-c1b721ef-0f23-4fa1-ad11-9f3427ee30bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223854716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3223854716
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2142574865
Short name T903
Test name
Test status
Simulation time 74730339356 ps
CPU time 353.35 seconds
Started Jul 03 05:44:58 PM PDT 24
Finished Jul 03 05:50:52 PM PDT 24
Peak memory 216612 kb
Host smart-ac78465e-28ab-489c-ae8f-29aa4e692996
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142574865 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2142574865
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1536227341
Short name T927
Test name
Test status
Simulation time 8536662398 ps
CPU time 14.18 seconds
Started Jul 03 05:45:00 PM PDT 24
Finished Jul 03 05:45:14 PM PDT 24
Peak memory 199796 kb
Host smart-667c1ea1-58b2-4aab-ae8a-c6f86c5b9650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536227341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1536227341
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1615605394
Short name T1077
Test name
Test status
Simulation time 27213213573 ps
CPU time 21.95 seconds
Started Jul 03 05:44:59 PM PDT 24
Finished Jul 03 05:45:21 PM PDT 24
Peak memory 199972 kb
Host smart-09e8192d-d7f0-44ea-8e3a-66c2708fe85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615605394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1615605394
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3450091955
Short name T326
Test name
Test status
Simulation time 663213684289 ps
CPU time 432.08 seconds
Started Jul 03 05:45:00 PM PDT 24
Finished Jul 03 05:52:12 PM PDT 24
Peak memory 211216 kb
Host smart-311bf25f-092d-4b74-bb83-dd0c3d9874f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450091955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3450091955
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.4101237803
Short name T267
Test name
Test status
Simulation time 16308792228 ps
CPU time 25.02 seconds
Started Jul 03 05:44:57 PM PDT 24
Finished Jul 03 05:45:23 PM PDT 24
Peak memory 199988 kb
Host smart-3385ac6e-2658-4da3-845a-c843f10d9cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101237803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.4101237803
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2871406163
Short name T346
Test name
Test status
Simulation time 102149781086 ps
CPU time 145.02 seconds
Started Jul 03 05:45:02 PM PDT 24
Finished Jul 03 05:47:27 PM PDT 24
Peak memory 199956 kb
Host smart-6aabe336-fc78-493e-981b-61fdc9f903fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871406163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2871406163
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3221171631
Short name T630
Test name
Test status
Simulation time 11861187 ps
CPU time 0.55 seconds
Started Jul 03 05:43:05 PM PDT 24
Finished Jul 03 05:43:06 PM PDT 24
Peak memory 194736 kb
Host smart-01233e20-62ec-4c58-baec-a39d611c3161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221171631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3221171631
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3411270240
Short name T841
Test name
Test status
Simulation time 173799332113 ps
CPU time 132.08 seconds
Started Jul 03 05:43:03 PM PDT 24
Finished Jul 03 05:45:16 PM PDT 24
Peak memory 199932 kb
Host smart-2f030e9f-49e4-4f88-bc26-fe5c767be504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411270240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3411270240
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.476098001
Short name T887
Test name
Test status
Simulation time 94895421756 ps
CPU time 143.4 seconds
Started Jul 03 05:43:08 PM PDT 24
Finished Jul 03 05:45:32 PM PDT 24
Peak memory 199768 kb
Host smart-81f2c1e6-71fb-45d9-aaf8-db86b11fcd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476098001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.476098001
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2576083336
Short name T1076
Test name
Test status
Simulation time 411122700944 ps
CPU time 39.27 seconds
Started Jul 03 05:42:54 PM PDT 24
Finished Jul 03 05:43:34 PM PDT 24
Peak memory 199904 kb
Host smart-c9403591-61fb-4daf-8251-bae781776368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576083336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2576083336
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1135834676
Short name T584
Test name
Test status
Simulation time 90565907385 ps
CPU time 32.35 seconds
Started Jul 03 05:43:20 PM PDT 24
Finished Jul 03 05:43:52 PM PDT 24
Peak memory 195996 kb
Host smart-4879fe83-5058-4e70-8ea0-4b25d9845ad1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135834676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1135834676
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.995482163
Short name T801
Test name
Test status
Simulation time 63248136694 ps
CPU time 263.66 seconds
Started Jul 03 05:43:09 PM PDT 24
Finished Jul 03 05:47:33 PM PDT 24
Peak memory 199976 kb
Host smart-014d9800-00d1-4a33-adbf-fe4167a4b97d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995482163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.995482163
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2450633307
Short name T379
Test name
Test status
Simulation time 2713678645 ps
CPU time 4.73 seconds
Started Jul 03 05:43:24 PM PDT 24
Finished Jul 03 05:43:29 PM PDT 24
Peak memory 195776 kb
Host smart-f50c25ae-97e1-4c2f-aa59-e0f8507cc4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450633307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2450633307
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.2733247040
Short name T548
Test name
Test status
Simulation time 6484066689 ps
CPU time 92.23 seconds
Started Jul 03 05:43:00 PM PDT 24
Finished Jul 03 05:44:32 PM PDT 24
Peak memory 199988 kb
Host smart-9488103f-e89c-43d8-b247-108c3d1b7061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733247040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2733247040
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.901272269
Short name T1080
Test name
Test status
Simulation time 1398764340 ps
CPU time 1.83 seconds
Started Jul 03 05:43:11 PM PDT 24
Finished Jul 03 05:43:13 PM PDT 24
Peak memory 198428 kb
Host smart-d26d1d17-6e2c-46ad-b908-0167d7820952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901272269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.901272269
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.695827880
Short name T107
Test name
Test status
Simulation time 171435608065 ps
CPU time 68.62 seconds
Started Jul 03 05:43:16 PM PDT 24
Finished Jul 03 05:44:25 PM PDT 24
Peak memory 199904 kb
Host smart-74e64817-3a2e-4cc9-bdca-0179c4b0c154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695827880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.695827880
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2982524769
Short name T437
Test name
Test status
Simulation time 2518826578 ps
CPU time 2.59 seconds
Started Jul 03 05:43:03 PM PDT 24
Finished Jul 03 05:43:06 PM PDT 24
Peak memory 195944 kb
Host smart-2e7a40f5-5f99-4903-8c56-b034eaeb3673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982524769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2982524769
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.329698279
Short name T466
Test name
Test status
Simulation time 322079551 ps
CPU time 0.94 seconds
Started Jul 03 05:43:13 PM PDT 24
Finished Jul 03 05:43:15 PM PDT 24
Peak memory 198176 kb
Host smart-4cbd1f4c-dd31-4ace-ba2d-4864cd9964c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329698279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.329698279
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2906718246
Short name T606
Test name
Test status
Simulation time 8899476062 ps
CPU time 11.01 seconds
Started Jul 03 05:43:01 PM PDT 24
Finished Jul 03 05:43:13 PM PDT 24
Peak memory 199840 kb
Host smart-1d15ae7f-3aa1-4cf1-8e21-09fda7ff978d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906718246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2906718246
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2853540322
Short name T1055
Test name
Test status
Simulation time 10194071257 ps
CPU time 14.86 seconds
Started Jul 03 05:43:07 PM PDT 24
Finished Jul 03 05:43:22 PM PDT 24
Peak memory 196776 kb
Host smart-275fcc03-b6c8-4ee1-b349-c9b234a5215a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853540322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2853540322
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2157057303
Short name T212
Test name
Test status
Simulation time 76825378901 ps
CPU time 40.83 seconds
Started Jul 03 05:45:02 PM PDT 24
Finished Jul 03 05:45:43 PM PDT 24
Peak memory 199908 kb
Host smart-154e16be-1ef8-4f5b-897b-bb16ade859d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157057303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2157057303
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.11517447
Short name T30
Test name
Test status
Simulation time 30155201417 ps
CPU time 422.54 seconds
Started Jul 03 05:45:02 PM PDT 24
Finished Jul 03 05:52:05 PM PDT 24
Peak memory 208204 kb
Host smart-9f6b6288-cd23-4967-8eaf-1e1fcc026dde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11517447 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.11517447
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2948352796
Short name T124
Test name
Test status
Simulation time 34795807478 ps
CPU time 17.56 seconds
Started Jul 03 05:45:02 PM PDT 24
Finished Jul 03 05:45:20 PM PDT 24
Peak memory 199928 kb
Host smart-4a933d90-9f12-42aa-8091-0b351c4626d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948352796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2948352796
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2999502250
Short name T227
Test name
Test status
Simulation time 23110099160 ps
CPU time 9.66 seconds
Started Jul 03 05:45:04 PM PDT 24
Finished Jul 03 05:45:14 PM PDT 24
Peak memory 199904 kb
Host smart-1b4907bc-14e7-4cc0-899a-39b065624193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999502250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2999502250
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2419938232
Short name T195
Test name
Test status
Simulation time 51325285010 ps
CPU time 73.72 seconds
Started Jul 03 05:45:01 PM PDT 24
Finished Jul 03 05:46:15 PM PDT 24
Peak memory 199872 kb
Host smart-f4abb1f0-0e74-41a3-93bc-185f822b1015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419938232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2419938232
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.4373877
Short name T335
Test name
Test status
Simulation time 49447335353 ps
CPU time 572.84 seconds
Started Jul 03 05:45:06 PM PDT 24
Finished Jul 03 05:54:40 PM PDT 24
Peak memory 216000 kb
Host smart-7b900023-5a00-4d2c-9940-e1ddbaa5174d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4373877 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.4373877
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.368618557
Short name T266
Test name
Test status
Simulation time 53686422330 ps
CPU time 86.7 seconds
Started Jul 03 05:45:01 PM PDT 24
Finished Jul 03 05:46:28 PM PDT 24
Peak memory 199976 kb
Host smart-a9f2a730-fd22-47ee-a710-adcb9734f963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368618557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.368618557
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.4178767988
Short name T641
Test name
Test status
Simulation time 616454626616 ps
CPU time 602.49 seconds
Started Jul 03 05:45:08 PM PDT 24
Finished Jul 03 05:55:11 PM PDT 24
Peak memory 212576 kb
Host smart-d2b9b15c-c11e-4b62-bfed-3ddf6b0eaa4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178767988 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.4178767988
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.183170242
Short name T687
Test name
Test status
Simulation time 25439368572 ps
CPU time 29.39 seconds
Started Jul 03 05:45:05 PM PDT 24
Finished Jul 03 05:45:34 PM PDT 24
Peak memory 199864 kb
Host smart-d89a70fb-792c-44cc-85e2-87d021753520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183170242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.183170242
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.469884390
Short name T338
Test name
Test status
Simulation time 242347667928 ps
CPU time 1229.64 seconds
Started Jul 03 05:45:06 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 224628 kb
Host smart-0aea473a-8213-446c-a2ad-3c24387e3894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469884390 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.469884390
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.791521235
Short name T206
Test name
Test status
Simulation time 15680849397 ps
CPU time 9.96 seconds
Started Jul 03 05:45:05 PM PDT 24
Finished Jul 03 05:45:15 PM PDT 24
Peak memory 199928 kb
Host smart-7f4f3e58-6937-4eb6-96f8-d0c95332dbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791521235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.791521235
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.241464602
Short name T707
Test name
Test status
Simulation time 9685903473 ps
CPU time 15.77 seconds
Started Jul 03 05:45:06 PM PDT 24
Finished Jul 03 05:45:22 PM PDT 24
Peak memory 199972 kb
Host smart-53dee485-b9ef-4bc4-963d-88f3bc80487a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241464602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.241464602
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2264720513
Short name T317
Test name
Test status
Simulation time 58897076173 ps
CPU time 82.77 seconds
Started Jul 03 05:45:08 PM PDT 24
Finished Jul 03 05:46:31 PM PDT 24
Peak memory 199884 kb
Host smart-09f75658-0250-4819-af5d-0a376466d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264720513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2264720513
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2217921145
Short name T45
Test name
Test status
Simulation time 452721210045 ps
CPU time 377.4 seconds
Started Jul 03 05:45:09 PM PDT 24
Finished Jul 03 05:51:26 PM PDT 24
Peak memory 212892 kb
Host smart-5a2b2e09-5c95-4e64-9692-676aec1dff75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217921145 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2217921145
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3175691289
Short name T32
Test name
Test status
Simulation time 142861236976 ps
CPU time 254.95 seconds
Started Jul 03 05:45:09 PM PDT 24
Finished Jul 03 05:49:24 PM PDT 24
Peak memory 216484 kb
Host smart-9498cc14-f1c1-4b1c-8ca9-4771892c1f46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175691289 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3175691289
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1174239651
Short name T767
Test name
Test status
Simulation time 34848469 ps
CPU time 0.58 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:15 PM PDT 24
Peak memory 195324 kb
Host smart-b3b5e2ba-3206-426a-a3d4-b9766e1d4d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174239651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1174239651
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.902088561
Short name T737
Test name
Test status
Simulation time 45700121011 ps
CPU time 16.51 seconds
Started Jul 03 05:43:10 PM PDT 24
Finished Jul 03 05:43:27 PM PDT 24
Peak memory 199976 kb
Host smart-26a17ffb-70d0-4ebb-9725-1de87f85eb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902088561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.902088561
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1394707706
Short name T727
Test name
Test status
Simulation time 65038553685 ps
CPU time 30.95 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:43:55 PM PDT 24
Peak memory 199816 kb
Host smart-175c9e32-aac2-483f-a023-1e8c5996665a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394707706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1394707706
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.863872431
Short name T161
Test name
Test status
Simulation time 16879226387 ps
CPU time 8.39 seconds
Started Jul 03 05:43:27 PM PDT 24
Finished Jul 03 05:43:36 PM PDT 24
Peak memory 199956 kb
Host smart-d7225652-7e85-49e4-b3fd-44a320436b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863872431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.863872431
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1357497640
Short name T574
Test name
Test status
Simulation time 138535308072 ps
CPU time 1213.6 seconds
Started Jul 03 05:43:01 PM PDT 24
Finished Jul 03 06:03:15 PM PDT 24
Peak memory 199836 kb
Host smart-f8ebe731-807f-4e63-83d0-bcaae0a15e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357497640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1357497640
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2735517839
Short name T385
Test name
Test status
Simulation time 6513482577 ps
CPU time 5.42 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:20 PM PDT 24
Peak memory 198428 kb
Host smart-7d5f3c1e-3cbb-4316-b235-8e5a4a1c8cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735517839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2735517839
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.1282322042
Short name T375
Test name
Test status
Simulation time 17740144097 ps
CPU time 823.44 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:56:58 PM PDT 24
Peak memory 199872 kb
Host smart-c13c1aa5-d1d1-4fe1-960f-92519bd5e274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1282322042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1282322042
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.668149844
Short name T590
Test name
Test status
Simulation time 2597829894 ps
CPU time 16.6 seconds
Started Jul 03 05:43:00 PM PDT 24
Finished Jul 03 05:43:17 PM PDT 24
Peak memory 198396 kb
Host smart-0e85a783-9f71-45f4-b52f-deeda3e947c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668149844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.668149844
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1542409165
Short name T474
Test name
Test status
Simulation time 28072199892 ps
CPU time 43.68 seconds
Started Jul 03 05:43:09 PM PDT 24
Finished Jul 03 05:43:53 PM PDT 24
Peak memory 199868 kb
Host smart-d349b7c7-8194-454b-8750-f86299fb8248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542409165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1542409165
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3564658054
Short name T765
Test name
Test status
Simulation time 6005833607 ps
CPU time 2.29 seconds
Started Jul 03 05:43:11 PM PDT 24
Finished Jul 03 05:43:13 PM PDT 24
Peak memory 196256 kb
Host smart-d9434cb6-3321-428a-81cf-e4ee0acffb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564658054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3564658054
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3539691889
Short name T868
Test name
Test status
Simulation time 5749999903 ps
CPU time 6.28 seconds
Started Jul 03 05:43:29 PM PDT 24
Finished Jul 03 05:43:36 PM PDT 24
Peak memory 199928 kb
Host smart-41aec5ef-69a6-4ab4-b7e0-658631ade610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539691889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3539691889
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2402067178
Short name T1020
Test name
Test status
Simulation time 267879585026 ps
CPU time 913.56 seconds
Started Jul 03 05:43:05 PM PDT 24
Finished Jul 03 05:58:19 PM PDT 24
Peak memory 199812 kb
Host smart-08c7e009-9483-4fa8-a0d0-4ecddac181f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402067178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2402067178
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2501482233
Short name T300
Test name
Test status
Simulation time 7078380348 ps
CPU time 15.95 seconds
Started Jul 03 05:43:09 PM PDT 24
Finished Jul 03 05:43:25 PM PDT 24
Peak memory 200068 kb
Host smart-b1059d72-cab9-47b1-9c00-5dbd980ef409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501482233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2501482233
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3966443651
Short name T360
Test name
Test status
Simulation time 40067417699 ps
CPU time 17.38 seconds
Started Jul 03 05:43:22 PM PDT 24
Finished Jul 03 05:43:40 PM PDT 24
Peak memory 198300 kb
Host smart-92c1c000-e516-46ac-9a8b-691a5ae1c810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966443651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3966443651
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.860108716
Short name T239
Test name
Test status
Simulation time 71396937989 ps
CPU time 98.92 seconds
Started Jul 03 05:45:11 PM PDT 24
Finished Jul 03 05:46:50 PM PDT 24
Peak memory 199968 kb
Host smart-8b734e5a-78a2-41e2-b976-7c39825baef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860108716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.860108716
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2144118013
Short name T664
Test name
Test status
Simulation time 23521460065 ps
CPU time 597.09 seconds
Started Jul 03 05:45:10 PM PDT 24
Finished Jul 03 05:55:08 PM PDT 24
Peak memory 215492 kb
Host smart-96237eac-7ef7-44a9-8874-7b67643dbaf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144118013 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2144118013
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2646419166
Short name T372
Test name
Test status
Simulation time 7503395272 ps
CPU time 8.59 seconds
Started Jul 03 05:45:08 PM PDT 24
Finished Jul 03 05:45:17 PM PDT 24
Peak memory 199540 kb
Host smart-69fa5be0-3b2f-40a9-bde1-cfb419e62c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646419166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2646419166
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2801016883
Short name T1087
Test name
Test status
Simulation time 33637395575 ps
CPU time 117.93 seconds
Started Jul 03 05:45:09 PM PDT 24
Finished Jul 03 05:47:07 PM PDT 24
Peak memory 215748 kb
Host smart-1230cd62-28bf-4c45-b594-ee0594353c9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801016883 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2801016883
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3608607642
Short name T893
Test name
Test status
Simulation time 138496612375 ps
CPU time 80.24 seconds
Started Jul 03 05:45:13 PM PDT 24
Finished Jul 03 05:46:33 PM PDT 24
Peak memory 199920 kb
Host smart-9298d0d5-2280-451b-8972-0c64afc51c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608607642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3608607642
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.247953297
Short name T42
Test name
Test status
Simulation time 157130791864 ps
CPU time 451.51 seconds
Started Jul 03 05:45:10 PM PDT 24
Finished Jul 03 05:52:42 PM PDT 24
Peak memory 216524 kb
Host smart-79a60c18-777b-462e-b120-21d0c72d32f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247953297 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.247953297
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2149034734
Short name T959
Test name
Test status
Simulation time 83405687462 ps
CPU time 38.98 seconds
Started Jul 03 05:45:10 PM PDT 24
Finished Jul 03 05:45:49 PM PDT 24
Peak memory 199820 kb
Host smart-63d2b46f-c37e-41aa-97d3-3e274ae12ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149034734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2149034734
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1229587311
Short name T209
Test name
Test status
Simulation time 69011412257 ps
CPU time 61.27 seconds
Started Jul 03 05:45:11 PM PDT 24
Finished Jul 03 05:46:12 PM PDT 24
Peak memory 199884 kb
Host smart-bdc669a5-f8eb-4560-81a5-9aa508e64031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229587311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1229587311
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3558609051
Short name T332
Test name
Test status
Simulation time 60427936134 ps
CPU time 816.4 seconds
Started Jul 03 05:45:09 PM PDT 24
Finished Jul 03 05:58:46 PM PDT 24
Peak memory 216504 kb
Host smart-68e2157f-977c-4eff-b9ec-59fee93f8b1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558609051 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3558609051
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.791350011
Short name T1006
Test name
Test status
Simulation time 45378576171 ps
CPU time 8.43 seconds
Started Jul 03 05:45:12 PM PDT 24
Finished Jul 03 05:45:21 PM PDT 24
Peak memory 199892 kb
Host smart-c1a6f41a-7899-4c05-baab-8ef30fe08095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791350011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.791350011
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2723718360
Short name T86
Test name
Test status
Simulation time 77765337692 ps
CPU time 583.15 seconds
Started Jul 03 05:45:11 PM PDT 24
Finished Jul 03 05:54:54 PM PDT 24
Peak memory 208636 kb
Host smart-6cf46bc9-ce77-46af-a88e-ed337c7c2038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723718360 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2723718360
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1494710882
Short name T35
Test name
Test status
Simulation time 46257374275 ps
CPU time 125.69 seconds
Started Jul 03 05:45:10 PM PDT 24
Finished Jul 03 05:47:16 PM PDT 24
Peak memory 199916 kb
Host smart-d248f4dc-9782-4e24-9227-9592d423c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494710882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1494710882
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1708445342
Short name T83
Test name
Test status
Simulation time 14454068019 ps
CPU time 109.32 seconds
Started Jul 03 05:45:09 PM PDT 24
Finished Jul 03 05:46:59 PM PDT 24
Peak memory 216460 kb
Host smart-23da36c9-e68b-49dd-94c5-7becfbd98baf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708445342 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1708445342
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1940058748
Short name T165
Test name
Test status
Simulation time 264731244836 ps
CPU time 167.72 seconds
Started Jul 03 05:45:13 PM PDT 24
Finished Jul 03 05:48:02 PM PDT 24
Peak memory 199900 kb
Host smart-75e78056-3152-4830-9074-1e96117c5e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940058748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1940058748
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1863351681
Short name T995
Test name
Test status
Simulation time 47669573888 ps
CPU time 20.52 seconds
Started Jul 03 05:45:21 PM PDT 24
Finished Jul 03 05:45:41 PM PDT 24
Peak memory 200008 kb
Host smart-d1aa04c6-2468-4ce4-a911-6514c4703cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863351681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1863351681
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.656544957
Short name T956
Test name
Test status
Simulation time 27905742485 ps
CPU time 304.31 seconds
Started Jul 03 05:45:11 PM PDT 24
Finished Jul 03 05:50:16 PM PDT 24
Peak memory 216376 kb
Host smart-f0533f81-0486-492b-98d0-53593ef71c53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656544957 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.656544957
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3939322234
Short name T622
Test name
Test status
Simulation time 13694541 ps
CPU time 0.53 seconds
Started Jul 03 05:43:09 PM PDT 24
Finished Jul 03 05:43:16 PM PDT 24
Peak memory 195312 kb
Host smart-6a70cedb-39ac-4d2d-bc22-516b96965b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939322234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3939322234
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.38046775
Short name T513
Test name
Test status
Simulation time 107180257190 ps
CPU time 29.26 seconds
Started Jul 03 05:43:20 PM PDT 24
Finished Jul 03 05:43:50 PM PDT 24
Peak memory 199944 kb
Host smart-00daed0d-0c56-442d-ba10-618fe7c1d309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38046775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.38046775
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.881043798
Short name T869
Test name
Test status
Simulation time 8868851838 ps
CPU time 17.4 seconds
Started Jul 03 05:42:58 PM PDT 24
Finished Jul 03 05:43:15 PM PDT 24
Peak memory 199964 kb
Host smart-f06421f2-8c24-467a-93e5-828605f29133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881043798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.881043798
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2278041028
Short name T456
Test name
Test status
Simulation time 108300061536 ps
CPU time 163.07 seconds
Started Jul 03 05:43:07 PM PDT 24
Finished Jul 03 05:45:50 PM PDT 24
Peak memory 199960 kb
Host smart-abf83648-fa1d-4bea-aad3-64abaf0c3045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278041028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2278041028
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3746437674
Short name T541
Test name
Test status
Simulation time 26990661388 ps
CPU time 13.14 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:43:29 PM PDT 24
Peak memory 199932 kb
Host smart-4fb69246-2b24-4ffd-b8c3-5e67af770da2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746437674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3746437674
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3263264759
Short name T393
Test name
Test status
Simulation time 67945785937 ps
CPU time 141.75 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:45:38 PM PDT 24
Peak memory 199832 kb
Host smart-18d90367-0f5e-4aca-920f-0188d5b69288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263264759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3263264759
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1721004045
Short name T659
Test name
Test status
Simulation time 3574752487 ps
CPU time 14.03 seconds
Started Jul 03 05:43:15 PM PDT 24
Finished Jul 03 05:43:30 PM PDT 24
Peak memory 199268 kb
Host smart-6cd8f26e-95aa-4167-b035-d8e962778e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721004045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1721004045
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.3968100047
Short name T290
Test name
Test status
Simulation time 4806841928 ps
CPU time 136.75 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:45:32 PM PDT 24
Peak memory 199832 kb
Host smart-65500b26-c87f-4dfd-a8e8-7a95441b3bc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968100047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3968100047
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.726568349
Short name T377
Test name
Test status
Simulation time 5479221249 ps
CPU time 41.82 seconds
Started Jul 03 05:43:02 PM PDT 24
Finished Jul 03 05:43:44 PM PDT 24
Peak memory 199208 kb
Host smart-49baef6d-0d21-4d76-b024-f00c1e59b4e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726568349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.726568349
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3973031425
Short name T603
Test name
Test status
Simulation time 63258660154 ps
CPU time 13.35 seconds
Started Jul 03 05:43:20 PM PDT 24
Finished Jul 03 05:43:34 PM PDT 24
Peak memory 199932 kb
Host smart-249d0e6e-3800-47ff-b068-611c98f4873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973031425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3973031425
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.49176588
Short name T882
Test name
Test status
Simulation time 701681933 ps
CPU time 1.71 seconds
Started Jul 03 05:43:12 PM PDT 24
Finished Jul 03 05:43:14 PM PDT 24
Peak memory 195616 kb
Host smart-2c6a4189-b4e6-4eef-bf34-61263d006104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49176588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.49176588
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1275980380
Short name T261
Test name
Test status
Simulation time 5993739809 ps
CPU time 22.82 seconds
Started Jul 03 05:43:10 PM PDT 24
Finished Jul 03 05:43:33 PM PDT 24
Peak memory 199796 kb
Host smart-1a6e20a0-a705-461c-9a9f-88c3e58619e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275980380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1275980380
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3198463232
Short name T851
Test name
Test status
Simulation time 52621545222 ps
CPU time 583.96 seconds
Started Jul 03 05:43:23 PM PDT 24
Finished Jul 03 05:53:07 PM PDT 24
Peak memory 216516 kb
Host smart-97488cf4-1751-454a-bd54-93987c27d93c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198463232 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3198463232
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2098889191
Short name T751
Test name
Test status
Simulation time 6477605021 ps
CPU time 16.29 seconds
Started Jul 03 05:43:14 PM PDT 24
Finished Jul 03 05:43:32 PM PDT 24
Peak memory 200000 kb
Host smart-b795fbc6-48d3-4d89-b87d-3e1ae9994b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098889191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2098889191
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3684274528
Short name T1056
Test name
Test status
Simulation time 9654952838 ps
CPU time 14.5 seconds
Started Jul 03 05:43:04 PM PDT 24
Finished Jul 03 05:43:19 PM PDT 24
Peak memory 199784 kb
Host smart-d4077cee-a2f4-4080-b72b-9e34f83f783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684274528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3684274528
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.20249326
Short name T426
Test name
Test status
Simulation time 15032214374 ps
CPU time 14.85 seconds
Started Jul 03 05:45:21 PM PDT 24
Finished Jul 03 05:45:36 PM PDT 24
Peak memory 199936 kb
Host smart-7cb025ea-5ab2-43fe-b921-1919042762cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20249326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.20249326
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2738086788
Short name T1045
Test name
Test status
Simulation time 89012769936 ps
CPU time 78.55 seconds
Started Jul 03 05:45:14 PM PDT 24
Finished Jul 03 05:46:33 PM PDT 24
Peak memory 199952 kb
Host smart-f30ef4dc-0813-427e-8d76-9c5660392c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738086788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2738086788
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1944026301
Short name T971
Test name
Test status
Simulation time 276449875682 ps
CPU time 360.73 seconds
Started Jul 03 05:45:13 PM PDT 24
Finished Jul 03 05:51:14 PM PDT 24
Peak memory 216416 kb
Host smart-5a062d6d-286b-47b0-99b0-9245e73c0c02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944026301 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1944026301
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.935060360
Short name T532
Test name
Test status
Simulation time 27675644622 ps
CPU time 25.16 seconds
Started Jul 03 05:45:14 PM PDT 24
Finished Jul 03 05:45:39 PM PDT 24
Peak memory 199932 kb
Host smart-1ab4d8da-7af2-4cad-aa5c-67b10fa8c18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935060360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.935060360
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3465478284
Short name T424
Test name
Test status
Simulation time 9550781597 ps
CPU time 16.04 seconds
Started Jul 03 05:45:22 PM PDT 24
Finished Jul 03 05:45:38 PM PDT 24
Peak memory 199984 kb
Host smart-15dd291f-cd10-42e6-8cd4-f109f21e3b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465478284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3465478284
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.4221545689
Short name T699
Test name
Test status
Simulation time 23586659017 ps
CPU time 276.54 seconds
Started Jul 03 05:45:22 PM PDT 24
Finished Jul 03 05:49:59 PM PDT 24
Peak memory 209344 kb
Host smart-ed4fbf80-be52-410f-a704-18e25a22f0f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221545689 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.4221545689
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.926314641
Short name T716
Test name
Test status
Simulation time 19141082505 ps
CPU time 26.93 seconds
Started Jul 03 05:45:13 PM PDT 24
Finished Jul 03 05:45:41 PM PDT 24
Peak memory 199912 kb
Host smart-b45d7991-2a14-403e-9cd1-b9883abd9509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926314641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.926314641
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.347319945
Short name T84
Test name
Test status
Simulation time 51038940450 ps
CPU time 141.67 seconds
Started Jul 03 05:45:21 PM PDT 24
Finished Jul 03 05:47:43 PM PDT 24
Peak memory 216516 kb
Host smart-648dc129-b93c-4f4f-872a-703f731b32d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347319945 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.347319945
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1921354955
Short name T596
Test name
Test status
Simulation time 105949508715 ps
CPU time 165.26 seconds
Started Jul 03 05:45:12 PM PDT 24
Finished Jul 03 05:47:58 PM PDT 24
Peak memory 200004 kb
Host smart-b69dce42-2b3d-4176-89f2-e1f5fd31668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921354955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1921354955
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1950642794
Short name T826
Test name
Test status
Simulation time 45462617705 ps
CPU time 265.85 seconds
Started Jul 03 05:45:13 PM PDT 24
Finished Jul 03 05:49:39 PM PDT 24
Peak memory 216464 kb
Host smart-26490a6e-3a90-480d-94b0-0fec049ed962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950642794 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1950642794
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.235903217
Short name T633
Test name
Test status
Simulation time 29439067956 ps
CPU time 15.55 seconds
Started Jul 03 05:45:16 PM PDT 24
Finished Jul 03 05:45:32 PM PDT 24
Peak memory 199912 kb
Host smart-cf13b3b0-ac1d-4ae7-8be7-a8b652edf65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235903217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.235903217
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2475705691
Short name T553
Test name
Test status
Simulation time 54873133616 ps
CPU time 78.11 seconds
Started Jul 03 05:45:21 PM PDT 24
Finished Jul 03 05:46:40 PM PDT 24
Peak memory 199996 kb
Host smart-8449168b-6e4e-4e1c-9b2a-832e0116931d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475705691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2475705691
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1856856760
Short name T535
Test name
Test status
Simulation time 5578152825 ps
CPU time 9.55 seconds
Started Jul 03 05:45:17 PM PDT 24
Finished Jul 03 05:45:27 PM PDT 24
Peak memory 199952 kb
Host smart-4a9982c9-1f38-439e-912e-1a14a86b6009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856856760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1856856760
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.817100619
Short name T602
Test name
Test status
Simulation time 269646796043 ps
CPU time 1017.26 seconds
Started Jul 03 05:45:18 PM PDT 24
Finished Jul 03 06:02:16 PM PDT 24
Peak memory 216484 kb
Host smart-ee972346-574b-4964-bc84-e7e8c08d9dd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817100619 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.817100619
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2418648095
Short name T153
Test name
Test status
Simulation time 148926716826 ps
CPU time 60.34 seconds
Started Jul 03 05:45:18 PM PDT 24
Finished Jul 03 05:46:18 PM PDT 24
Peak memory 199932 kb
Host smart-cf86f0b4-619a-42bc-b3fa-35f3dde532e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418648095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2418648095
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3878022340
Short name T44
Test name
Test status
Simulation time 42357854663 ps
CPU time 336.88 seconds
Started Jul 03 05:45:16 PM PDT 24
Finished Jul 03 05:50:53 PM PDT 24
Peak memory 216572 kb
Host smart-0b3af07b-e4ac-4318-91c8-049a58f25b40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878022340 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3878022340
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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