Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	116667	1			T1	1		T2	41		T3	5
all_values[1]	116667	1			T1	1		T2	41		T3	5
all_values[2]	116667	1			T1	1		T2	41		T3	5
all_values[3]	116667	1			T1	1		T2	41		T3	5
all_values[4]	116667	1			T1	1		T2	41		T3	5
all_values[5]	116667	1			T1	1		T2	41		T3	5
all_values[6]	116667	1			T1	1		T2	41		T3	5
all_values[7]	116667	1			T1	1		T2	41		T3	5
all_values[8]	116667	1			T1	1		T2	41		T3	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

519785

1

T1

3

T2

203

T3

22

auto[1]

530218

1

T1

6

T2

166

T3

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

948655

1

T1

7

T2

341

T3

37

auto[1]

101348

1

T1

2

T2

28

T3

8

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	32902	1			T2	14		T3	1		T6	10
all_values[0]	auto[0]	auto[1]	24966	1			T2	13		T3	2		T5	32
all_values[0]	auto[1]	auto[0]	34242	1			T2	12		T3	1		T5	38
all_values[0]	auto[1]	auto[1]	24557	1			T1	1		T2	2		T3	1
all_values[1]	auto[0]	auto[0]	60527	1			T1	1		T2	21		T5	67
all_values[1]	auto[0]	auto[1]	1548	1			T8	8		T9	1		T11	1
all_values[1]	auto[1]	auto[0]	52897	1			T2	20		T3	5		T5	21
all_values[1]	auto[1]	auto[1]	1695	1			T5	5		T8	2		T34	9
all_values[2]	auto[0]	auto[0]	55467	1			T2	10		T3	2		T5	15
all_values[2]	auto[0]	auto[1]	2891	1			T2	2		T5	8		T6	11
all_values[2]	auto[1]	auto[0]	55800	1			T1	1		T2	26		T3	1
all_values[2]	auto[1]	auto[1]	2509	1			T2	3		T3	2		T5	10
all_values[3]	auto[0]	auto[0]	53982	1			T1	1		T2	6		T3	2
all_values[3]	auto[0]	auto[1]	327	1			T5	1		T11	4		T15	1
all_values[3]	auto[1]	auto[0]	62017	1			T2	35		T3	3		T5	20
all_values[3]	auto[1]	auto[1]	341	1			T5	1		T15	1		T19	2
all_values[4]	auto[0]	auto[0]	56911	1			T1	1		T2	29		T3	3
all_values[4]	auto[0]	auto[1]	538	1			T15	2		T16	1		T19	6
all_values[4]	auto[1]	auto[0]	58699	1			T2	12		T3	2		T5	19
all_values[4]	auto[1]	auto[1]	519	1			T18	7		T19	4		T20	6
all_values[5]	auto[0]	auto[0]	59268	1			T2	18		T3	3		T5	77
all_values[5]	auto[0]	auto[1]	216	1			T11	2		T19	2		T20	1
all_values[5]	auto[1]	auto[0]	56965	1			T1	1		T2	23		T3	2
all_values[5]	auto[1]	auto[1]	218	1			T8	2		T15	2		T35	2
all_values[6]	auto[0]	auto[0]	54614	1			T2	20		T3	3		T5	77
all_values[6]	auto[0]	auto[1]	176	1			T11	1		T15	2		T16	1
all_values[6]	auto[1]	auto[0]	61692	1			T1	1		T2	21		T3	2
all_values[6]	auto[1]	auto[1]	185	1			T8	2		T35	1		T19	2
all_values[7]	auto[0]	auto[0]	59600	1			T2	41		T3	3		T5	82
all_values[7]	auto[0]	auto[1]	380	1			T8	1		T11	2		T35	1
all_values[7]	auto[1]	auto[0]	56292	1			T1	1		T3	2		T5	11
all_values[7]	auto[1]	auto[1]	395	1			T8	4		T15	2		T35	3
all_values[8]	auto[0]	auto[0]	36264	1			T2	21		T3	1		T5	51
all_values[8]	auto[0]	auto[1]	19208	1			T2	8		T3	2		T5	32
all_values[8]	auto[1]	auto[0]	40516	1			T2	12		T3	1		T8	694
all_values[8]	auto[1]	auto[1]	20679	1			T1	1		T3	1		T5	10