Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2244	1			T1	2		T2	2		T5	2
auto[BaudRate115200]	1962	1			T2	2		T5	2		T6	1
auto[BaudRate230400]	1923	1			T2	1		T3	1		T8	8
auto[BaudRate128Kbps]	1890	1			T2	1		T3	1		T5	1
auto[BaudRate256Kbps]	2110	1			T3	1		T6	2		T8	11
auto[BaudRate1Mbps]	1826	1			T2	1		T3	2		T5	1
auto[BaudRate1p5Mbps]	1418	1			T2	1		T5	4		T6	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1597	1			T11	20		T33	1		T105	6
freqs[25]	1294	1			T31	9		T104	9		T16	95
freqs[48]	768	1			T32	10		T103	6		T38	2
freqs[50]	616	1			T109	6		T279	2		T306	6
freqs[100]	1177	1			T10	5		T158	10		T14	34

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	273	1			T11	1		T35	3		T249	1
auto[BaudRate9600]	freqs[25]	203	1			T104	2		T16	10		T22	2
auto[BaudRate9600]	freqs[48]	111	1			T154	2		T148	2		T40	15
auto[BaudRate9600]	freqs[50]	90	1			T109	2		T279	1		T306	6
auto[BaudRate9600]	freqs[100]	191	1			T14	1		T220	3		T19	5
auto[BaudRate115200]	freqs[24]	255	1			T11	2		T33	1		T105	3
auto[BaudRate115200]	freqs[25]	193	1			T31	1		T104	1		T16	12
auto[BaudRate115200]	freqs[48]	110	1			T32	2		T103	2		T247	5
auto[BaudRate115200]	freqs[50]	78	1			T109	1		T80	1		T112	1
auto[BaudRate115200]	freqs[100]	142	1			T158	2		T14	3		T220	1
auto[BaudRate230400]	freqs[24]	242	1			T11	5		T105	1		T35	2
auto[BaudRate230400]	freqs[25]	197	1			T31	4		T104	1		T16	13
auto[BaudRate230400]	freqs[48]	94	1			T32	2		T103	1		T247	6
auto[BaudRate230400]	freqs[50]	79	1			T80	1		T112	2		T298	2
auto[BaudRate230400]	freqs[100]	158	1			T158	2		T14	4		T220	1
auto[BaudRate128Kbps]	freqs[24]	256	1			T11	3		T35	4		T36	3
auto[BaudRate128Kbps]	freqs[25]	186	1			T31	1		T104	1		T16	4
auto[BaudRate128Kbps]	freqs[48]	113	1			T32	1		T103	2		T247	12
auto[BaudRate128Kbps]	freqs[50]	52	1			T112	2		T298	2		T278	1
auto[BaudRate128Kbps]	freqs[100]	159	1			T158	2		T14	7		T19	13
auto[BaudRate256Kbps]	freqs[24]	219	1			T11	7		T105	1		T35	8
auto[BaudRate256Kbps]	freqs[25]	211	1			T31	2		T104	3		T16	25
auto[BaudRate256Kbps]	freqs[48]	104	1			T32	1		T103	1		T247	6
auto[BaudRate256Kbps]	freqs[50]	99	1			T80	3		T231	4		T301	1
auto[BaudRate256Kbps]	freqs[100]	169	1			T10	1		T158	1		T14	5
auto[BaudRate1Mbps]	freqs[24]	237	1			T11	1		T105	1		T35	2
auto[BaudRate1Mbps]	freqs[25]	196	1			T31	1		T104	1		T16	23
auto[BaudRate1Mbps]	freqs[48]	118	1			T32	2		T38	1		T247	5
auto[BaudRate1Mbps]	freqs[50]	100	1			T109	2		T80	2		T112	2
auto[BaudRate1Mbps]	freqs[100]	168	1			T10	3		T158	1		T14	3
auto[BaudRate1p5Mbps]	freqs[25]	108	1			T16	8		T153	1		T116	7
auto[BaudRate1p5Mbps]	freqs[48]	118	1			T32	2		T38	1		T247	9
auto[BaudRate1p5Mbps]	freqs[50]	118	1			T109	1		T279	1		T80	2
auto[BaudRate1p5Mbps]	freqs[100]	190	1			T10	1		T158	2		T14	11

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded