Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	34552549	1			T1	1		T2	44		T3	24
all_levels[1]	194447	1			T2	1		T8	200		T9	693
all_levels[2]	2556	1			T2	1		T5	1		T8	12
all_levels[3]	1091	1			T2	1		T8	6		T11	2
all_levels[4]	707	1			T6	1		T8	4		T15	6
all_levels[5]	498	1			T2	2		T3	1		T5	2
all_levels[6]	452	1			T8	1		T15	2		T32	1
all_levels[7]	363	1			T8	2		T15	4		T32	1
all_levels[8]	279	1			T2	1		T3	2		T6	1
all_levels[9]	245	1			T2	2		T8	1		T15	2
all_levels[10]	221	1			T2	1		T8	1		T103	1
all_levels[11]	180	1			T2	1		T35	1		T104	1
all_levels[12]	175	1			T15	1		T32	2		T52	1
all_levels[13]	144	1			T105	2		T104	1		T52	1
all_levels[14]	146	1			T11	1		T16	1		T106	1
all_levels[15]	120	1			T2	3		T32	1		T16	1
all_levels[16]	91	1			T8	1		T104	3		T107	1
all_levels[17]	89	1			T8	1		T52	1		T108	1
all_levels[18]	85	1			T16	1		T93	1		T19	2
all_levels[19]	81	1			T32	2		T104	2		T16	1
all_levels[20]	79	1			T15	1		T105	1		T52	1
all_levels[21]	83	1			T104	1		T108	1		T83	2
all_levels[22]	70	1			T8	1		T109	1		T52	1
all_levels[23]	73	1			T106	1		T80	1		T110	1
all_levels[24]	58	1			T32	1		T13	2		T14	1
all_levels[25]	49	1			T103	1		T14	1		T93	1
all_levels[26]	50	1			T5	1		T6	1		T8	1
all_levels[27]	51	1			T109	1		T104	2		T16	1
all_levels[28]	38	1			T104	1		T16	1		T111	1
all_levels[29]	38	1			T53	1		T112	1		T113	1
all_levels[30]	37	1			T6	1		T16	2		T53	1
all_levels[31]	46	1			T108	1		T114	4		T115	1
all_levels[32]	33	1			T5	1		T16	1		T114	1
all_levels[33]	26	1			T32	1		T19	2		T116	1
all_levels[34]	26	1			T93	2		T19	2		T117	1
all_levels[35]	20	1			T15	1		T29	2		T113	3
all_levels[36]	24	1			T118	2		T119	1		T120	1
all_levels[37]	14	1			T93	1		T115	1		T121	1
all_levels[38]	26	1			T106	1		T20	1		T116	2
all_levels[39]	18	1			T105	1		T122	1		T123	1
all_levels[40]	22	1			T5	1		T20	1		T124	4
all_levels[41]	23	1			T52	2		T90	1		T125	4
all_levels[42]	12	1			T8	1		T32	1		T16	1
all_levels[43]	19	1			T93	1		T83	1		T126	1
all_levels[44]	10	1			T127	1		T128	1		T129	1
all_levels[45]	18	1			T14	1		T126	1		T130	1
all_levels[46]	13	1			T35	1		T14	2		T83	1
all_levels[47]	17	1			T14	1		T131	1		T132	1
all_levels[48]	16	1			T131	4		T132	1		T133	1
all_levels[49]	13	1			T134	1		T135	2		T136	1
all_levels[50]	13	1			T93	1		T20	1		T116	1
all_levels[51]	15	1			T32	1		T137	1		T138	1
all_levels[52]	15	1			T116	1		T139	1		T127	1
all_levels[53]	15	1			T16	1		T140	1		T133	3
all_levels[54]	6	1			T141	1		T142	1		T143	1
all_levels[55]	6	1			T123	1		T144	1		T145	1
all_levels[56]	6	1			T14	1		T29	1		T120	1
all_levels[57]	5	1			T146	1		T59	1		T147	2
all_levels[58]	10	1			T148	1		T149	1		T150	1
all_levels[59]	10	1			T132	1		T151	1		T152	1
all_levels[60]	10	1			T94	1		T153	1		T154	1
all_levels[61]	7	1			T15	1		T35	1		T112	1
all_levels[62]	6	1			T36	1		T89	1		T155	3
all_levels[63]	5	1			T16	1		T126	1		T156	1
all_levels[64]	103	1			T14	1		T19	1		T157	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34751129

1

T2

51

T3

27

T5

175

auto[1]

4644

1

T1

1

T2

6

T5

9

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[42]]	[auto[1]]	0	1	1
[all_levels[44] , all_levels[45]]	[auto[1]]	--	--	2
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58] , all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	4
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	34548333	1			T2	40		T3	24		T5	170
all_levels[0]	auto[1]	4216	1			T1	1		T2	4		T5	8
all_levels[1]	auto[0]	194356	1			T2	1		T8	200		T9	693
all_levels[1]	auto[1]	91	1			T158	1		T80	2		T85	2
all_levels[2]	auto[0]	2536	1			T2	1		T5	1		T8	12
all_levels[2]	auto[1]	20	1			T131	2		T159	2		T160	1
all_levels[3]	auto[0]	1081	1			T2	1		T8	6		T11	2
all_levels[3]	auto[1]	10	1			T125	1		T161	1		T162	1
all_levels[4]	auto[0]	691	1			T6	1		T8	4		T15	6
all_levels[4]	auto[1]	16	1			T108	1		T163	1		T164	1
all_levels[5]	auto[0]	478	1			T2	2		T3	1		T5	1
all_levels[5]	auto[1]	20	1			T5	1		T165	3		T166	1
all_levels[6]	auto[0]	436	1			T8	1		T15	2		T32	1
all_levels[6]	auto[1]	16	1			T134	1		T151	2		T167	1
all_levels[7]	auto[0]	351	1			T8	2		T15	4		T32	1
all_levels[7]	auto[1]	12	1			T168	1		T169	1		T170	4
all_levels[8]	auto[0]	269	1			T2	1		T3	2		T6	1
all_levels[8]	auto[1]	10	1			T85	1		T168	1		T171	5
all_levels[9]	auto[0]	234	1			T2	2		T8	1		T15	2
all_levels[9]	auto[1]	11	1			T172	1		T173	1		T174	1
all_levels[10]	auto[0]	208	1			T2	1		T8	1		T103	1
all_levels[10]	auto[1]	13	1			T164	1		T175	1		T176	2
all_levels[11]	auto[0]	168	1			T2	1		T35	1		T104	1
all_levels[11]	auto[1]	12	1			T52	2		T177	1		T178	1
all_levels[12]	auto[0]	160	1			T15	1		T32	2		T52	1
all_levels[12]	auto[1]	15	1			T133	1		T172	1		T139	1
all_levels[13]	auto[0]	131	1			T105	1		T104	1		T52	1
all_levels[13]	auto[1]	13	1			T105	1		T172	1		T179	1
all_levels[14]	auto[0]	140	1			T11	1		T16	1		T106	1
all_levels[14]	auto[1]	6	1			T148	1		T180	1		T181	1
all_levels[15]	auto[0]	106	1			T2	1		T32	1		T16	1
all_levels[15]	auto[1]	14	1			T2	2		T182	2		T172	1
all_levels[16]	auto[0]	88	1			T8	1		T104	2		T107	1
all_levels[16]	auto[1]	3	1			T104	1		T183	1		T184	1
all_levels[17]	auto[0]	84	1			T8	1		T52	1		T108	1
all_levels[17]	auto[1]	5	1			T118	1		T185	4		-	-
all_levels[18]	auto[0]	79	1			T16	1		T93	1		T19	2
all_levels[18]	auto[1]	6	1			T186	1		T164	1		T187	1
all_levels[19]	auto[0]	76	1			T32	2		T104	2		T16	1
all_levels[19]	auto[1]	5	1			T158	1		T188	1		T189	2
all_levels[20]	auto[0]	69	1			T15	1		T105	1		T52	1
all_levels[20]	auto[1]	10	1			T176	1		T190	1		T191	1
all_levels[21]	auto[0]	72	1			T104	1		T108	1		T83	2
all_levels[21]	auto[1]	11	1			T130	1		T122	3		T169	1
all_levels[22]	auto[0]	65	1			T8	1		T109	1		T52	1
all_levels[22]	auto[1]	5	1			T173	2		T125	1		T156	1
all_levels[23]	auto[0]	69	1			T106	1		T80	1		T110	1
all_levels[23]	auto[1]	4	1			T191	1		T192	1		T193	1
all_levels[24]	auto[0]	55	1			T32	1		T13	1		T14	1
all_levels[24]	auto[1]	3	1			T13	1		T194	2		-	-
all_levels[25]	auto[0]	45	1			T103	1		T14	1		T93	1
all_levels[25]	auto[1]	4	1			T178	2		T195	1		T196	1
all_levels[26]	auto[0]	43	1			T5	1		T6	1		T8	1
all_levels[26]	auto[1]	7	1			T138	3		T197	1		T198	2
all_levels[27]	auto[0]	49	1			T109	1		T104	2		T16	1
all_levels[27]	auto[1]	2	1			T179	1		T199	1		-	-
all_levels[28]	auto[0]	34	1			T104	1		T16	1		T111	1
all_levels[28]	auto[1]	4	1			T200	3		T201	1		-	-
all_levels[29]	auto[0]	37	1			T53	1		T112	1		T113	1
all_levels[29]	auto[1]	1	1			T202	1		-	-		-	-
all_levels[30]	auto[0]	35	1			T6	1		T16	2		T53	1
all_levels[30]	auto[1]	2	1			T167	1		T189	1		-	-
all_levels[31]	auto[0]	37	1			T108	1		T114	3		T115	1
all_levels[31]	auto[1]	9	1			T114	1		T203	1		T172	1
all_levels[32]	auto[0]	32	1			T5	1		T16	1		T114	1
all_levels[32]	auto[1]	1	1			T204	1		-	-		-	-
all_levels[33]	auto[0]	26	1			T32	1		T19	2		T116	1
all_levels[34]	auto[0]	24	1			T93	2		T19	2		T117	1
all_levels[34]	auto[1]	2	1			T90	1		T205	1		-	-
all_levels[35]	auto[0]	17	1			T15	1		T29	2		T113	1
all_levels[35]	auto[1]	3	1			T113	2		T180	1		-	-
all_levels[36]	auto[0]	20	1			T118	1		T119	1		T120	1
all_levels[36]	auto[1]	4	1			T118	1		T206	2		T207	1
all_levels[37]	auto[0]	13	1			T93	1		T115	1		T121	1
all_levels[37]	auto[1]	1	1			T208	1		-	-		-	-
all_levels[38]	auto[0]	23	1			T106	1		T20	1		T116	2
all_levels[38]	auto[1]	3	1			T209	2		T210	1		-	-
all_levels[39]	auto[0]	16	1			T105	1		T122	1		T123	1
all_levels[39]	auto[1]	2	1			T119	2		-	-		-	-
all_levels[40]	auto[0]	17	1			T5	1		T20	1		T124	1
all_levels[40]	auto[1]	5	1			T124	3		T159	1		T211	1
all_levels[41]	auto[0]	17	1			T52	1		T90	1		T125	1
all_levels[41]	auto[1]	6	1			T52	1		T125	3		T179	2
all_levels[42]	auto[0]	12	1			T8	1		T32	1		T16	1
all_levels[43]	auto[0]	17	1			T93	1		T83	1		T126	1
all_levels[43]	auto[1]	2	1			T146	1		T212	1		-	-
all_levels[44]	auto[0]	10	1			T127	1		T128	1		T129	1
all_levels[45]	auto[0]	18	1			T14	1		T126	1		T130	1
all_levels[46]	auto[0]	12	1			T35	1		T14	2		T83	1
all_levels[46]	auto[1]	1	1			T213	1		-	-		-	-
all_levels[47]	auto[0]	15	1			T14	1		T131	1		T132	1
all_levels[47]	auto[1]	2	1			T151	1		T214	1		-	-
all_levels[48]	auto[0]	13	1			T131	1		T132	1		T133	1
all_levels[48]	auto[1]	3	1			T131	3		-	-		-	-
all_levels[49]	auto[0]	10	1			T134	1		T135	1		T136	1
all_levels[49]	auto[1]	3	1			T135	1		T215	2		-	-
all_levels[50]	auto[0]	12	1			T93	1		T20	1		T116	1
all_levels[50]	auto[1]	1	1			T216	1		-	-		-	-
all_levels[51]	auto[0]	13	1			T32	1		T137	1		T138	1
all_levels[51]	auto[1]	2	1			T217	2		-	-		-	-
all_levels[52]	auto[0]	11	1			T116	1		T139	1		T127	1
all_levels[52]	auto[1]	4	1			T218	4		-	-		-	-
all_levels[53]	auto[0]	13	1			T16	1		T140	1		T133	1
all_levels[53]	auto[1]	2	1			T133	2		-	-		-	-
all_levels[54]	auto[0]	6	1			T141	1		T142	1		T143	1
all_levels[55]	auto[0]	5	1			T123	1		T144	1		T145	1
all_levels[55]	auto[1]	1	1			T219	1		-	-		-	-
all_levels[56]	auto[0]	6	1			T14	1		T29	1		T120	1
all_levels[57]	auto[0]	4	1			T146	1		T59	1		T147	1
all_levels[57]	auto[1]	1	1			T147	1		-	-		-	-
all_levels[58]	auto[0]	10	1			T148	1		T149	1		T150	1
all_levels[59]	auto[0]	10	1			T132	1		T151	1		T152	1
all_levels[60]	auto[0]	10	1			T94	1		T153	1		T154	1
all_levels[61]	auto[0]	7	1			T15	1		T35	1		T112	1
all_levels[62]	auto[0]	4	1			T36	1		T89	1		T155	1
all_levels[62]	auto[1]	2	1			T155	2		-	-		-	-
all_levels[63]	auto[0]	5	1			T16	1		T126	1		T156	1
all_levels[64]	auto[0]	86	1			T14	1		T19	1		T157	1
all_levels[64]	auto[1]	17	1			T138	1		T165	1		T150	1