Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	116667	1			T1	1		T2	41		T3	5
all_pins[1]	116667	1			T1	1		T2	41		T3	5
all_pins[2]	116667	1			T1	1		T2	41		T3	5
all_pins[3]	116667	1			T1	1		T2	41		T3	5
all_pins[4]	116667	1			T1	1		T2	41		T3	5
all_pins[5]	116667	1			T1	1		T2	41		T3	5
all_pins[6]	116667	1			T1	1		T2	41		T3	5
all_pins[7]	116667	1			T1	1		T2	41		T3	5
all_pins[8]	116667	1			T1	1		T2	41		T3	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	997945	1			T1	7		T2	364		T3	41
values[0x1]	52058	1			T1	2		T2	5		T3	4
transitions[0x0=>0x1]	40474	1			T1	1		T2	5		T3	3
transitions[0x1=>0x0]	40270	1			T1	1		T2	4		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	92015	1			T2	39		T3	4		T5	70
all_pins[0]	values[0x1]	24652	1			T1	1		T2	2		T3	1
all_pins[0]	transitions[0x0=>0x1]	24117	1			T1	1		T2	2		T3	1
all_pins[0]	transitions[0x1=>0x0]	1161	1			T5	5		T8	2		T34	9
all_pins[1]	values[0x0]	114971	1			T1	1		T2	41		T3	5
all_pins[1]	values[0x1]	1696	1			T5	5		T8	2		T34	9
all_pins[1]	transitions[0x0=>0x1]	1593	1			T5	5		T8	2		T34	6
all_pins[1]	transitions[0x1=>0x0]	2465	1			T2	3		T3	2		T5	10
all_pins[2]	values[0x0]	114099	1			T1	1		T2	38		T3	3
all_pins[2]	values[0x1]	2568	1			T2	3		T3	2		T5	10
all_pins[2]	transitions[0x0=>0x1]	2495	1			T2	3		T3	2		T5	10
all_pins[2]	transitions[0x1=>0x0]	268	1			T5	1		T15	1		T19	1
all_pins[3]	values[0x0]	116326	1			T1	1		T2	41		T3	5
all_pins[3]	values[0x1]	341	1			T5	1		T15	1		T19	2
all_pins[3]	transitions[0x0=>0x1]	280	1			T5	1		T15	1		T19	1
all_pins[3]	transitions[0x1=>0x0]	458	1			T18	7		T19	3		T20	5
all_pins[4]	values[0x0]	116148	1			T1	1		T2	41		T3	5
all_pins[4]	values[0x1]	519	1			T18	7		T19	4		T20	6
all_pins[4]	transitions[0x0=>0x1]	417	1			T18	6		T19	1		T20	1
all_pins[4]	transitions[0x1=>0x0]	179	1			T8	2		T15	2		T35	2
all_pins[5]	values[0x0]	116386	1			T1	1		T2	41		T3	5
all_pins[5]	values[0x1]	281	1			T8	2		T15	2		T18	1
all_pins[5]	transitions[0x0=>0x1]	230	1			T15	2		T18	1		T35	2
all_pins[5]	transitions[0x1=>0x0]	808	1			T5	2		T8	12		T11	1
all_pins[6]	values[0x0]	115808	1			T1	1		T2	41		T3	5
all_pins[6]	values[0x1]	859	1			T5	2		T8	14		T11	1
all_pins[6]	transitions[0x0=>0x1]	799	1			T5	2		T8	12		T11	1
all_pins[6]	transitions[0x1=>0x0]	335	1			T8	2		T15	2		T35	3
all_pins[7]	values[0x0]	116272	1			T1	1		T2	41		T3	5
all_pins[7]	values[0x1]	395	1			T8	4		T15	2		T35	3
all_pins[7]	transitions[0x0=>0x1]	253	1			T8	2		T15	2		T14	2
all_pins[7]	transitions[0x1=>0x0]	20605	1			T1	1		T3	1		T5	10
all_pins[8]	values[0x0]	95920	1			T2	41		T3	4		T5	83
all_pins[8]	values[0x1]	20747	1			T1	1		T3	1		T5	10
all_pins[8]	transitions[0x0=>0x1]	10290	1			T5	8		T6	1		T8	17
all_pins[8]	transitions[0x1=>0x0]	13991	1			T2	1		T3	1		T5	21