Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	9588455	1			T2	2		T3	9		T5	79
all_levels[1]	1916560	1			T3	1		T5	17		T8	35955
all_levels[2]	372251	1			T3	2		T5	8		T8	22558
all_levels[3]	517963	1			T2	1		T3	1		T5	6
all_levels[4]	271669	1			T3	2		T5	3		T8	994
all_levels[5]	497777	1			T2	2		T3	1		T5	12
all_levels[6]	250444	1			T3	2		T5	5		T8	16466
all_levels[7]	395144	1			T3	2		T5	5		T8	571
all_levels[8]	398615	1			T2	1		T3	2		T5	9
all_levels[9]	255239	1			T5	4		T8	645		T9	14
all_levels[10]	581585	1			T2	1		T5	2		T8	561
all_levels[11]	219496	1			T2	1		T5	1		T6	1
all_levels[12]	222008	1			T5	1		T8	636		T9	15
all_levels[13]	406716	1			T2	1		T5	6		T6	3
all_levels[14]	353211	1			T5	7		T6	1		T8	615
all_levels[15]	288982	1			T5	1		T6	2		T8	460
all_levels[16]	343783	1			T2	1		T8	696		T9	23
all_levels[17]	342530	1			T2	1		T5	5		T8	518
all_levels[18]	434530	1			T2	1		T5	2		T8	574
all_levels[19]	200371	1			T5	1		T8	638		T9	15
all_levels[20]	617593	1			T2	1		T5	3		T8	533
all_levels[21]	233329	1			T8	473		T9	15		T10	63
all_levels[22]	423882	1			T2	6		T5	2		T8	725
all_levels[23]	415725	1			T8	648		T9	10		T10	53
all_levels[24]	765974	1			T2	2		T5	3		T6	2
all_levels[25]	237015	1			T8	660		T9	21		T10	49
all_levels[26]	230450	1			T8	374		T9	14		T10	50
all_levels[27]	165662	1			T8	373		T9	19		T10	45
all_levels[28]	207844	1			T5	1		T8	5087		T9	16
all_levels[29]	191670	1			T8	368		T9	16		T10	47
all_levels[30]	574153	1			T8	392		T9	17		T10	61
all_levels[31]	522446	1			T8	696		T9	118		T10	2007
all_levels[32]	12312401	1			T2	35		T3	6		T6	8

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34751129

1

T2

51

T3

27

T5

175

auto[1]

4344

1

T2

5

T3

1

T5

8

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	9585967	1			T2	2		T3	9		T5	73
all_levels[0]	auto[1]	2488	1			T5	6		T34	4		T103	1
all_levels[1]	auto[0]	1916235	1			T3	1		T5	16		T8	35954
all_levels[1]	auto[1]	325	1			T5	1		T8	1		T52	2
all_levels[2]	auto[0]	372188	1			T3	2		T5	8		T8	22558
all_levels[2]	auto[1]	63	1			T36	2		T28	1		T130	2
all_levels[3]	auto[0]	517839	1			T2	1		T3	1		T5	6
all_levels[3]	auto[1]	124	1			T104	1		T108	2		T14	1
all_levels[4]	auto[0]	271636	1			T3	2		T5	3		T8	994
all_levels[4]	auto[1]	33	1			T36	2		T158	2		T308	1
all_levels[5]	auto[0]	497732	1			T2	2		T3	1		T5	11
all_levels[5]	auto[1]	45	1			T5	1		T105	1		T309	2
all_levels[6]	auto[0]	250426	1			T3	2		T5	5		T8	16466
all_levels[6]	auto[1]	18	1			T158	1		T169	1		T148	1
all_levels[7]	auto[0]	395057	1			T3	2		T5	5		T8	570
all_levels[7]	auto[1]	87	1			T8	1		T95	2		T183	1
all_levels[8]	auto[0]	398586	1			T2	1		T3	2		T5	9
all_levels[8]	auto[1]	29	1			T103	1		T268	1		T113	1
all_levels[9]	auto[0]	255212	1			T5	4		T8	645		T9	14
all_levels[9]	auto[1]	27	1			T153	1		T169	1		T310	1
all_levels[10]	auto[0]	581563	1			T2	1		T5	2		T8	561
all_levels[10]	auto[1]	22	1			T286	2		T275	1		T303	2
all_levels[11]	auto[0]	219467	1			T2	1		T5	1		T6	1
all_levels[11]	auto[1]	29	1			T237	1		T301	1		T134	1
all_levels[12]	auto[0]	221983	1			T5	1		T8	636		T9	15
all_levels[12]	auto[1]	25	1			T80	2		T311	2		T312	2
all_levels[13]	auto[0]	406693	1			T2	1		T5	6		T6	3
all_levels[13]	auto[1]	23	1			T8	1		T249	1		T234	1
all_levels[14]	auto[0]	353186	1			T5	7		T6	1		T8	615
all_levels[14]	auto[1]	25	1			T105	3		T87	1		T113	1
all_levels[15]	auto[0]	288854	1			T5	1		T6	2		T8	460
all_levels[15]	auto[1]	128	1			T235	5		T116	4		T292	6
all_levels[16]	auto[0]	343759	1			T2	1		T8	696		T9	23
all_levels[16]	auto[1]	24	1			T14	3		T300	1		T313	1
all_levels[17]	auto[0]	342514	1			T2	1		T5	5		T8	518
all_levels[17]	auto[1]	16	1			T158	1		T236	1		T314	1
all_levels[18]	auto[0]	434512	1			T2	1		T5	2		T8	574
all_levels[18]	auto[1]	18	1			T315	1		T251	1		T148	2
all_levels[19]	auto[0]	200360	1			T5	1		T8	638		T9	15
all_levels[19]	auto[1]	11	1			T316	1		T317	1		T318	1
all_levels[20]	auto[0]	617570	1			T2	1		T5	3		T8	533
all_levels[20]	auto[1]	23	1			T110	1		T183	3		T319	1
all_levels[21]	auto[0]	233312	1			T8	473		T9	15		T10	63
all_levels[21]	auto[1]	17	1			T81	1		T168	1		T317	1
all_levels[22]	auto[0]	423850	1			T2	3		T5	2		T8	725
all_levels[22]	auto[1]	32	1			T2	3		T111	1		T148	1
all_levels[23]	auto[0]	415706	1			T8	648		T9	10		T10	53
all_levels[23]	auto[1]	19	1			T320	1		T310	1		T172	1
all_levels[24]	auto[0]	765954	1			T2	2		T5	3		T6	2
all_levels[24]	auto[1]	20	1			T297	1		T220	2		T111	1
all_levels[25]	auto[0]	236992	1			T8	660		T9	21		T10	49
all_levels[25]	auto[1]	23	1			T86	1		T30	1		T164	1
all_levels[26]	auto[0]	230431	1			T8	374		T9	14		T10	50
all_levels[26]	auto[1]	19	1			T104	2		T321	2		T210	1
all_levels[27]	auto[0]	165648	1			T8	373		T9	19		T10	45
all_levels[27]	auto[1]	14	1			T80	1		T130	1		T134	1
all_levels[28]	auto[0]	207826	1			T5	1		T8	5086		T9	16
all_levels[28]	auto[1]	18	1			T8	1		T51	2		T322	1
all_levels[29]	auto[0]	191647	1			T8	368		T9	16		T10	47
all_levels[29]	auto[1]	23	1			T209	1		T269	1		T323	1
all_levels[30]	auto[0]	574144	1			T8	392		T9	17		T10	61
all_levels[30]	auto[1]	9	1			T39	1		T174	1		T324	1
all_levels[31]	auto[0]	522433	1			T8	696		T9	118		T10	2007
all_levels[31]	auto[1]	13	1			T325	1		T181	1		T166	2
all_levels[32]	auto[0]	12311847	1			T2	33		T3	5		T6	8
all_levels[32]	auto[1]	554	1			T2	2		T3	1		T9	1