Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	855	1			T8	4		T11	4		T15	4
all_values[1]	855	1			T8	4		T11	4		T15	4
all_values[2]	855	1			T8	4		T11	4		T15	4
all_values[3]	855	1			T8	4		T11	4		T15	4
all_values[4]	855	1			T8	4		T11	4		T15	4
all_values[5]	855	1			T8	4		T11	4		T15	4
all_values[6]	855	1			T8	4		T11	4		T15	4
all_values[7]	855	1			T8	4		T11	4		T15	4
all_values[8]	855	1			T8	4		T11	4		T15	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4198

1

T8

22

T11

25

T15

21

auto[1]

3497

1

T8

14

T11

11

T15

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2521

1

T8

16

T11

13

T15

10

auto[1]

5174

1

T8

20

T11

23

T15

26

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4593

1

T8

23

T11

20

T15

19

auto[1]

3102

1

T8

13

T11

16

T15

17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	288	1			T8	3		T11	1		T15	1
all_values[0]	auto[0]	auto[1]	auto[1]	228	1			T11	1		T15	1		T35	1
all_values[0]	auto[1]	auto[0]	auto[1]	190	1			T8	1		T11	1		T15	1
all_values[0]	auto[1]	auto[1]	auto[1]	149	1			T11	1		T15	1		T19	3
all_values[1]	auto[0]	auto[0]	auto[0]	280	1			T8	3		T11	3		T15	2
all_values[1]	auto[0]	auto[1]	auto[0]	236	1			T8	1		T15	1		T35	2
all_values[1]	auto[1]	auto[0]	auto[1]	184	1			T11	1		T15	1		T19	3
all_values[1]	auto[1]	auto[1]	auto[1]	155	1			T16	1		T19	2		T20	2
all_values[2]	auto[0]	auto[0]	auto[0]	193	1			T8	1		T11	2		T15	1
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T35	1		T30	1		T98	2
all_values[2]	auto[0]	auto[1]	auto[0]	141	1			T8	2		T15	2		T35	1
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T11	1		T16	1		T20	3
all_values[2]	auto[1]	auto[0]	auto[1]	192	1			T8	1		T35	1		T16	1
all_values[2]	auto[1]	auto[1]	auto[1]	156	1			T11	1		T15	1		T19	3
all_values[3]	auto[0]	auto[0]	auto[0]	178	1			T8	2		T35	1		T16	1
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T11	1		T35	1		T16	2
all_values[3]	auto[0]	auto[1]	auto[0]	167	1			T8	1		T15	2		T19	2
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T19	1		T20	2		T30	1
all_values[3]	auto[1]	auto[0]	auto[1]	195	1			T11	3		T15	2		T16	1
all_values[3]	auto[1]	auto[1]	auto[1]	153	1			T8	1		T35	2		T19	2
all_values[4]	auto[0]	auto[0]	auto[0]	179	1			T8	1		T35	4		T16	1
all_values[4]	auto[0]	auto[0]	auto[1]	98	1			T15	1		T16	1		T88	2
all_values[4]	auto[0]	auto[1]	auto[0]	118	1			T8	1		T11	3		T16	1
all_values[4]	auto[0]	auto[1]	auto[1]	91	1			T19	2		T20	4		T30	1
all_values[4]	auto[1]	auto[0]	auto[1]	206	1			T8	1		T11	1		T15	2
all_values[4]	auto[1]	auto[1]	auto[1]	163	1			T8	1		T15	1		T16	1
all_values[5]	auto[0]	auto[0]	auto[0]	173	1			T8	1		T11	1		T35	1
all_values[5]	auto[0]	auto[0]	auto[1]	113	1			T11	1		T19	1		T20	1
all_values[5]	auto[0]	auto[1]	auto[0]	134	1			T35	1		T20	1		T30	2
all_values[5]	auto[0]	auto[1]	auto[1]	90	1			T8	1		T15	1		T35	1
all_values[5]	auto[1]	auto[0]	auto[1]	176	1			T11	2		T15	1		T35	1
all_values[5]	auto[1]	auto[1]	auto[1]	169	1			T8	2		T15	2		T16	2
all_values[6]	auto[0]	auto[0]	auto[0]	199	1			T8	1		T11	1		T35	1
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T15	1		T19	1		T30	2
all_values[6]	auto[0]	auto[1]	auto[0]	167	1			T11	2		T35	1		T20	2
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T8	1		T20	1		T98	1
all_values[6]	auto[1]	auto[0]	auto[1]	179	1			T8	2		T11	1		T15	3
all_values[6]	auto[1]	auto[1]	auto[1]	161	1			T35	2		T19	2		T20	2
all_values[7]	auto[0]	auto[0]	auto[0]	206	1			T8	1		T11	1		T15	2
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T11	1		T35	1		T16	1
all_values[7]	auto[0]	auto[1]	auto[0]	150	1			T8	1		T19	2		T20	4
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T15	1		T35	2		T30	1
all_values[7]	auto[1]	auto[0]	auto[1]	175	1			T8	2		T11	2		T35	1
all_values[7]	auto[1]	auto[1]	auto[1]	156	1			T15	1		T19	1		T20	2
all_values[8]	auto[0]	auto[0]	auto[1]	290	1			T15	2		T16	3		T19	7
all_values[8]	auto[0]	auto[1]	auto[1]	222	1			T8	2		T11	1		T15	1
all_values[8]	auto[1]	auto[0]	auto[1]	183	1			T8	2		T11	2		T15	1
all_values[8]	auto[1]	auto[1]	auto[1]	160	1			T11	1		T35	1		T19	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal