Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1314
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T1253 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1017164176 Jul 04 04:48:01 PM PDT 24 Jul 04 04:48:02 PM PDT 24 19113533 ps
T1254 /workspace/coverage/cover_reg_top/5.uart_intr_test.1862630548 Jul 04 04:47:54 PM PDT 24 Jul 04 04:47:54 PM PDT 24 42416313 ps
T1255 /workspace/coverage/cover_reg_top/25.uart_intr_test.3471057496 Jul 04 04:48:13 PM PDT 24 Jul 04 04:48:14 PM PDT 24 13951992 ps
T1256 /workspace/coverage/cover_reg_top/20.uart_intr_test.20490045 Jul 04 04:48:16 PM PDT 24 Jul 04 04:48:17 PM PDT 24 39361502 ps
T1257 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2879383378 Jul 04 04:47:57 PM PDT 24 Jul 04 04:47:58 PM PDT 24 32536908 ps
T1258 /workspace/coverage/cover_reg_top/42.uart_intr_test.1149363498 Jul 04 04:48:02 PM PDT 24 Jul 04 04:48:03 PM PDT 24 26082234 ps
T1259 /workspace/coverage/cover_reg_top/19.uart_tl_errors.3505054326 Jul 04 04:48:06 PM PDT 24 Jul 04 04:48:08 PM PDT 24 27314943 ps
T1260 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2172203499 Jul 04 04:48:13 PM PDT 24 Jul 04 04:48:15 PM PDT 24 18816112 ps
T1261 /workspace/coverage/cover_reg_top/27.uart_intr_test.575318107 Jul 04 04:48:11 PM PDT 24 Jul 04 04:48:12 PM PDT 24 15809239 ps
T1262 /workspace/coverage/cover_reg_top/33.uart_intr_test.3626677616 Jul 04 04:48:09 PM PDT 24 Jul 04 04:48:10 PM PDT 24 61392435 ps
T1263 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1300147644 Jul 04 04:47:57 PM PDT 24 Jul 04 04:47:58 PM PDT 24 67920017 ps
T1264 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3789994183 Jul 04 04:47:59 PM PDT 24 Jul 04 04:48:00 PM PDT 24 29890811 ps
T1265 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3854488136 Jul 04 04:47:46 PM PDT 24 Jul 04 04:47:47 PM PDT 24 206683694 ps
T1266 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2725052625 Jul 04 04:48:02 PM PDT 24 Jul 04 04:48:04 PM PDT 24 72965183 ps
T1267 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3418666239 Jul 04 04:47:55 PM PDT 24 Jul 04 04:47:56 PM PDT 24 51037907 ps
T1268 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.4226435517 Jul 04 04:48:05 PM PDT 24 Jul 04 04:48:06 PM PDT 24 38189102 ps
T1269 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1400760491 Jul 04 04:48:06 PM PDT 24 Jul 04 04:48:08 PM PDT 24 264607776 ps
T1270 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2857437570 Jul 04 04:47:54 PM PDT 24 Jul 04 04:47:56 PM PDT 24 272656869 ps
T1271 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3678315968 Jul 04 04:47:56 PM PDT 24 Jul 04 04:47:57 PM PDT 24 13436504 ps
T1272 /workspace/coverage/cover_reg_top/34.uart_intr_test.186098996 Jul 04 04:48:16 PM PDT 24 Jul 04 04:48:17 PM PDT 24 93810029 ps
T1273 /workspace/coverage/cover_reg_top/12.uart_intr_test.3751267029 Jul 04 04:48:07 PM PDT 24 Jul 04 04:48:08 PM PDT 24 44395397 ps
T1274 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1480393087 Jul 04 04:48:04 PM PDT 24 Jul 04 04:48:06 PM PDT 24 28176617 ps
T1275 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.162843541 Jul 04 04:48:02 PM PDT 24 Jul 04 04:48:03 PM PDT 24 1041969109 ps
T77 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1012579319 Jul 04 04:47:51 PM PDT 24 Jul 04 04:47:52 PM PDT 24 192454432 ps
T1276 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2372389695 Jul 04 04:47:58 PM PDT 24 Jul 04 04:48:00 PM PDT 24 287573541 ps
T1277 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.572081482 Jul 04 04:48:10 PM PDT 24 Jul 04 04:48:11 PM PDT 24 28237743 ps
T1278 /workspace/coverage/cover_reg_top/18.uart_intr_test.568214120 Jul 04 04:48:09 PM PDT 24 Jul 04 04:48:09 PM PDT 24 49604149 ps
T1279 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.239705730 Jul 04 04:48:00 PM PDT 24 Jul 04 04:48:01 PM PDT 24 27608198 ps
T1280 /workspace/coverage/cover_reg_top/19.uart_intr_test.2051636764 Jul 04 04:48:04 PM PDT 24 Jul 04 04:48:05 PM PDT 24 16114769 ps
T1281 /workspace/coverage/cover_reg_top/15.uart_intr_test.160104059 Jul 04 04:48:04 PM PDT 24 Jul 04 04:48:05 PM PDT 24 15659335 ps
T1282 /workspace/coverage/cover_reg_top/32.uart_intr_test.2355898520 Jul 04 04:48:07 PM PDT 24 Jul 04 04:48:08 PM PDT 24 12805322 ps
T1283 /workspace/coverage/cover_reg_top/6.uart_intr_test.926299841 Jul 04 04:48:09 PM PDT 24 Jul 04 04:48:09 PM PDT 24 31600735 ps
T1284 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2340926811 Jul 04 04:48:13 PM PDT 24 Jul 04 04:48:15 PM PDT 24 103453668 ps
T1285 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.493618669 Jul 04 04:48:05 PM PDT 24 Jul 04 04:48:06 PM PDT 24 42974934 ps
T1286 /workspace/coverage/cover_reg_top/0.uart_intr_test.3138927831 Jul 04 04:47:54 PM PDT 24 Jul 04 04:47:55 PM PDT 24 20170889 ps
T1287 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.240933446 Jul 04 04:47:57 PM PDT 24 Jul 04 04:47:59 PM PDT 24 114841462 ps
T1288 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2282227583 Jul 04 04:47:58 PM PDT 24 Jul 04 04:47:59 PM PDT 24 40595963 ps
T1289 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.320783897 Jul 04 04:48:15 PM PDT 24 Jul 04 04:48:19 PM PDT 24 51499807 ps
T1290 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2568095038 Jul 04 04:48:02 PM PDT 24 Jul 04 04:48:03 PM PDT 24 77090960 ps
T1291 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1409701566 Jul 04 04:47:47 PM PDT 24 Jul 04 04:47:49 PM PDT 24 163923852 ps
T1292 /workspace/coverage/cover_reg_top/30.uart_intr_test.1902044378 Jul 04 04:48:17 PM PDT 24 Jul 04 04:48:18 PM PDT 24 12084336 ps
T1293 /workspace/coverage/cover_reg_top/11.uart_intr_test.1290763634 Jul 04 04:48:07 PM PDT 24 Jul 04 04:48:07 PM PDT 24 47728557 ps
T1294 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3752596483 Jul 04 04:48:03 PM PDT 24 Jul 04 04:48:04 PM PDT 24 26030565 ps
T1295 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1709231050 Jul 04 04:48:14 PM PDT 24 Jul 04 04:48:15 PM PDT 24 16206289 ps
T1296 /workspace/coverage/cover_reg_top/22.uart_intr_test.3559602724 Jul 04 04:48:11 PM PDT 24 Jul 04 04:48:12 PM PDT 24 14153422 ps
T1297 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.198171453 Jul 04 04:48:03 PM PDT 24 Jul 04 04:48:04 PM PDT 24 65715813 ps
T1298 /workspace/coverage/cover_reg_top/7.uart_tl_errors.3878988784 Jul 04 04:47:51 PM PDT 24 Jul 04 04:47:52 PM PDT 24 69722022 ps
T1299 /workspace/coverage/cover_reg_top/24.uart_intr_test.853663910 Jul 04 04:48:15 PM PDT 24 Jul 04 04:48:16 PM PDT 24 39171728 ps
T1300 /workspace/coverage/cover_reg_top/13.uart_tl_errors.483577349 Jul 04 04:47:55 PM PDT 24 Jul 04 04:47:57 PM PDT 24 24507551 ps
T1301 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3176911356 Jul 04 04:48:14 PM PDT 24 Jul 04 04:48:16 PM PDT 24 89850330 ps
T1302 /workspace/coverage/cover_reg_top/10.uart_intr_test.3333630152 Jul 04 04:48:00 PM PDT 24 Jul 04 04:48:01 PM PDT 24 14537464 ps
T1303 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2754365025 Jul 04 04:47:56 PM PDT 24 Jul 04 04:47:57 PM PDT 24 23440351 ps
T1304 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3482844122 Jul 04 04:48:09 PM PDT 24 Jul 04 04:48:10 PM PDT 24 63945986 ps
T1305 /workspace/coverage/cover_reg_top/13.uart_intr_test.1380985422 Jul 04 04:47:56 PM PDT 24 Jul 04 04:47:57 PM PDT 24 60706539 ps
T1306 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2709098518 Jul 04 04:47:56 PM PDT 24 Jul 04 04:47:57 PM PDT 24 52981346 ps
T74 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2915184053 Jul 04 04:48:07 PM PDT 24 Jul 04 04:48:08 PM PDT 24 141093845 ps
T1307 /workspace/coverage/cover_reg_top/46.uart_intr_test.3534493793 Jul 04 04:48:10 PM PDT 24 Jul 04 04:48:10 PM PDT 24 13790690 ps
T1308 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1925796118 Jul 04 04:48:03 PM PDT 24 Jul 04 04:48:04 PM PDT 24 19978879 ps
T1309 /workspace/coverage/cover_reg_top/14.uart_tl_errors.179889623 Jul 04 04:47:56 PM PDT 24 Jul 04 04:47:58 PM PDT 24 68782847 ps
T1310 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1063229490 Jul 04 04:48:10 PM PDT 24 Jul 04 04:48:11 PM PDT 24 31140501 ps
T1311 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2158582531 Jul 04 04:48:02 PM PDT 24 Jul 04 04:48:03 PM PDT 24 53695192 ps
T1312 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3150864957 Jul 04 04:48:01 PM PDT 24 Jul 04 04:48:03 PM PDT 24 29868786 ps
T1313 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4160317076 Jul 04 04:47:49 PM PDT 24 Jul 04 04:47:49 PM PDT 24 46540893 ps
T1314 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2574343977 Jul 04 04:48:06 PM PDT 24 Jul 04 04:48:08 PM PDT 24 40793192 ps

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3454558103
Short name T8
Test name
Test status
Simulation time 112565361502 ps
CPU time 928.36 seconds
Started Jul 04 05:38:30 PM PDT 24
Finished Jul 04 05:53:59 PM PDT 24
Peak memory 229852 kb
Host smart-637ef1ba-6fbc-4e80-8b44-7fbb73317a5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454558103 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3454558103
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1740627458
Short name T15
Test name
Test status
Simulation time 134043476707 ps
CPU time 487.16 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:49:07 PM PDT 24
Peak memory 216612 kb
Host smart-d27579d2-3d47-423a-9c1c-03fe78d9e193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740627458 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1740627458
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2794896939
Short name T30
Test name
Test status
Simulation time 182963864805 ps
CPU time 840.4 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:52:14 PM PDT 24
Peak memory 224900 kb
Host smart-63c67257-af54-4649-909a-387fbebaf588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794896939 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2794896939
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1064854322
Short name T19
Test name
Test status
Simulation time 116981665522 ps
CPU time 1445.58 seconds
Started Jul 04 05:42:38 PM PDT 24
Finished Jul 04 06:06:45 PM PDT 24
Peak memory 224924 kb
Host smart-ebc44150-2560-4d2a-8d56-463cef45fb39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064854322 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1064854322
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.303704903
Short name T111
Test name
Test status
Simulation time 1552384627635 ps
CPU time 410.15 seconds
Started Jul 04 05:38:50 PM PDT 24
Finished Jul 04 05:45:41 PM PDT 24
Peak memory 200188 kb
Host smart-ab5c847c-b042-4aed-8a97-96cb3d2fbdb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303704903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.303704903
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3563551184
Short name T16
Test name
Test status
Simulation time 253920250953 ps
CPU time 427.95 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:46:28 PM PDT 24
Peak memory 216432 kb
Host smart-66e7492b-0824-45e9-9638-c496ab6dd4dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563551184 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3563551184
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2541941059
Short name T25
Test name
Test status
Simulation time 34480244 ps
CPU time 0.77 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:38:14 PM PDT 24
Peak memory 218308 kb
Host smart-06de55c0-5f62-445d-b60e-1b5053ac5bf9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541941059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2541941059
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/42.uart_stress_all.2468566015
Short name T210
Test name
Test status
Simulation time 1184478055220 ps
CPU time 235.96 seconds
Started Jul 04 05:41:21 PM PDT 24
Finished Jul 04 05:45:17 PM PDT 24
Peak memory 208336 kb
Host smart-36766a49-a828-48f0-b723-506f8a3ad8a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468566015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2468566015
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2032994595
Short name T116
Test name
Test status
Simulation time 187101755857 ps
CPU time 696.1 seconds
Started Jul 04 05:42:04 PM PDT 24
Finished Jul 04 05:53:40 PM PDT 24
Peak memory 216516 kb
Host smart-4e175b9a-6508-4bed-9780-108aa1bfb268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032994595 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2032994595
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all.3180851144
Short name T14
Test name
Test status
Simulation time 129464624078 ps
CPU time 626.31 seconds
Started Jul 04 05:41:56 PM PDT 24
Finished Jul 04 05:52:23 PM PDT 24
Peak memory 199976 kb
Host smart-96ad1bee-2949-469c-a1df-551f7bf4393a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180851144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3180851144
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2228132016
Short name T123
Test name
Test status
Simulation time 207099819278 ps
CPU time 782.47 seconds
Started Jul 04 05:42:04 PM PDT 24
Finished Jul 04 05:55:07 PM PDT 24
Peak memory 216484 kb
Host smart-4e7b07ef-f00f-415b-a9a2-58a1cdd9d18f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228132016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2228132016
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2680852833
Short name T168
Test name
Test status
Simulation time 185837065887 ps
CPU time 334.33 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:44:22 PM PDT 24
Peak memory 199872 kb
Host smart-10056f40-f66e-418f-9241-5427888b450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680852833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2680852833
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.1056255221
Short name T35
Test name
Test status
Simulation time 240296051683 ps
CPU time 437.31 seconds
Started Jul 04 05:41:30 PM PDT 24
Finished Jul 04 05:48:48 PM PDT 24
Peak memory 208440 kb
Host smart-a69daf23-e152-4bb7-b470-379a7a680f42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056255221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1056255221
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2449236612
Short name T71
Test name
Test status
Simulation time 53199816 ps
CPU time 0.94 seconds
Started Jul 04 04:47:59 PM PDT 24
Finished Jul 04 04:48:00 PM PDT 24
Peak memory 199724 kb
Host smart-b8a0d58e-4468-49ab-830a-6c746b1e7983
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449236612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2449236612
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.547744117
Short name T39
Test name
Test status
Simulation time 219869411804 ps
CPU time 562.47 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:52:00 PM PDT 24
Peak memory 216716 kb
Host smart-b64c3a42-6763-4d5b-a290-5651f8972c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547744117 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.547744117
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2566138974
Short name T164
Test name
Test status
Simulation time 115157140206 ps
CPU time 180.3 seconds
Started Jul 04 05:42:51 PM PDT 24
Finished Jul 04 05:45:51 PM PDT 24
Peak memory 199904 kb
Host smart-778180d1-62d9-436e-b958-ac98a2ce4f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566138974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2566138974
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.790107061
Short name T110
Test name
Test status
Simulation time 133426676502 ps
CPU time 225.9 seconds
Started Jul 04 05:42:49 PM PDT 24
Finished Jul 04 05:46:35 PM PDT 24
Peak memory 200016 kb
Host smart-56214529-5890-45df-acbc-fb31a282e026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790107061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.790107061
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_alert_test.2459298375
Short name T4
Test name
Test status
Simulation time 18510232 ps
CPU time 0.55 seconds
Started Jul 04 05:39:20 PM PDT 24
Finished Jul 04 05:39:21 PM PDT 24
Peak memory 195624 kb
Host smart-0ed8ca57-f37a-41d6-ae47-723e002f8da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459298375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2459298375
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1972541293
Short name T112
Test name
Test status
Simulation time 62166379149 ps
CPU time 48.17 seconds
Started Jul 04 05:40:20 PM PDT 24
Finished Jul 04 05:41:08 PM PDT 24
Peak memory 200036 kb
Host smart-842e691a-a234-41ac-aba1-a28c94989a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972541293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1972541293
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2145127407
Short name T106
Test name
Test status
Simulation time 133304362782 ps
CPU time 164.24 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:42:08 PM PDT 24
Peak memory 199924 kb
Host smart-dfa0cfb0-39dc-440c-9c9a-54b9ab56d6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145127407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2145127407
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.4149022903
Short name T89
Test name
Test status
Simulation time 63562324392 ps
CPU time 317.81 seconds
Started Jul 04 05:41:58 PM PDT 24
Finished Jul 04 05:47:16 PM PDT 24
Peak memory 216640 kb
Host smart-bdde9945-2230-4d94-93ea-3f4c73226822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149022903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.4149022903
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_noise_filter.685198124
Short name T226
Test name
Test status
Simulation time 133873872650 ps
CPU time 175.98 seconds
Started Jul 04 05:39:53 PM PDT 24
Finished Jul 04 05:42:50 PM PDT 24
Peak memory 200140 kb
Host smart-d5bbc0ed-72a5-4d59-a9c0-1f27eea21418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685198124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.685198124
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.198348412
Short name T49
Test name
Test status
Simulation time 14925797 ps
CPU time 0.64 seconds
Started Jul 04 04:47:52 PM PDT 24
Finished Jul 04 04:47:52 PM PDT 24
Peak memory 196124 kb
Host smart-ba870b73-6476-40e7-84f0-23d7c9c47f8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198348412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.198348412
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2669391322
Short name T66
Test name
Test status
Simulation time 58238255 ps
CPU time 0.72 seconds
Started Jul 04 04:47:39 PM PDT 24
Finished Jul 04 04:47:40 PM PDT 24
Peak memory 197552 kb
Host smart-3f06e932-51bc-42ba-af88-2cc3554c58c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669391322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2669391322
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1412669644
Short name T148
Test name
Test status
Simulation time 83025385472 ps
CPU time 66.07 seconds
Started Jul 04 05:43:57 PM PDT 24
Finished Jul 04 05:45:03 PM PDT 24
Peak memory 199996 kb
Host smart-d12a0f1c-6af0-479c-8575-b9868401b2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412669644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1412669644
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all.20926194
Short name T97
Test name
Test status
Simulation time 812207938774 ps
CPU time 241.15 seconds
Started Jul 04 05:39:18 PM PDT 24
Finished Jul 04 05:43:19 PM PDT 24
Peak memory 208244 kb
Host smart-25bf2f41-5248-45e8-b122-bf51e3d1edfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20926194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.20926194
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3926183877
Short name T150
Test name
Test status
Simulation time 350256794756 ps
CPU time 1273 seconds
Started Jul 04 05:38:40 PM PDT 24
Finished Jul 04 05:59:54 PM PDT 24
Peak memory 218736 kb
Host smart-bd202cbc-60e3-4f33-9c6f-27af3313ae52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926183877 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3926183877
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2734285088
Short name T93
Test name
Test status
Simulation time 41950224958 ps
CPU time 21.16 seconds
Started Jul 04 05:41:28 PM PDT 24
Finished Jul 04 05:41:49 PM PDT 24
Peak memory 200012 kb
Host smart-5194729e-4a2a-450a-933c-f895cb73ef5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734285088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2734285088
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.320138073
Short name T80
Test name
Test status
Simulation time 78857951034 ps
CPU time 85.29 seconds
Started Jul 04 05:43:34 PM PDT 24
Finished Jul 04 05:44:59 PM PDT 24
Peak memory 199956 kb
Host smart-2e53187f-edfb-4013-9bb0-ee0cbb3a443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320138073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.320138073
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.683580207
Short name T172
Test name
Test status
Simulation time 171150580890 ps
CPU time 314.87 seconds
Started Jul 04 05:42:14 PM PDT 24
Finished Jul 04 05:47:29 PM PDT 24
Peak memory 200016 kb
Host smart-223a0336-5d0d-4094-a4cc-1f19cec16d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683580207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.683580207
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.67188483
Short name T52
Test name
Test status
Simulation time 30910674969 ps
CPU time 48.95 seconds
Started Jul 04 05:43:48 PM PDT 24
Finished Jul 04 05:44:37 PM PDT 24
Peak memory 199924 kb
Host smart-92ae0744-fca7-4b66-871d-fbab4fc5220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67188483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.67188483
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2792972389
Short name T72
Test name
Test status
Simulation time 195812408 ps
CPU time 1.24 seconds
Started Jul 04 04:47:51 PM PDT 24
Finished Jul 04 04:47:53 PM PDT 24
Peak memory 199988 kb
Host smart-ba9d6c34-28af-4d5b-8935-0039ab780132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792972389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2792972389
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.903475077
Short name T131
Test name
Test status
Simulation time 59943283738 ps
CPU time 80.02 seconds
Started Jul 04 05:42:58 PM PDT 24
Finished Jul 04 05:44:18 PM PDT 24
Peak memory 199888 kb
Host smart-5283373e-86f7-40e0-b35b-7d8112dea807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903475077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.903475077
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.987803115
Short name T153
Test name
Test status
Simulation time 83697722361 ps
CPU time 37.28 seconds
Started Jul 04 05:42:08 PM PDT 24
Finished Jul 04 05:42:45 PM PDT 24
Peak memory 200000 kb
Host smart-c5ae62d9-8dd7-4c82-ae80-d3021d8de22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987803115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.987803115
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.3621845834
Short name T151
Test name
Test status
Simulation time 177320338769 ps
CPU time 417.04 seconds
Started Jul 04 05:38:43 PM PDT 24
Finished Jul 04 05:45:40 PM PDT 24
Peak memory 199856 kb
Host smart-a18d128f-3b4e-4b25-9828-1f2bc40f4910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621845834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3621845834
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.178541419
Short name T118
Test name
Test status
Simulation time 52643380449 ps
CPU time 15.47 seconds
Started Jul 04 05:43:02 PM PDT 24
Finished Jul 04 05:43:17 PM PDT 24
Peak memory 199884 kb
Host smart-43830190-e4dd-4eea-811d-7db718fad89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178541419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.178541419
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.658204354
Short name T136
Test name
Test status
Simulation time 135312210448 ps
CPU time 70.53 seconds
Started Jul 04 05:40:20 PM PDT 24
Finished Jul 04 05:41:31 PM PDT 24
Peak memory 199940 kb
Host smart-583e869f-0409-4244-a537-1854a61ed017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658204354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.658204354
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1118920184
Short name T5
Test name
Test status
Simulation time 124892941136 ps
CPU time 143.77 seconds
Started Jul 04 05:38:50 PM PDT 24
Finished Jul 04 05:41:14 PM PDT 24
Peak memory 199860 kb
Host smart-8f58366c-477e-43c3-8194-039cc92efa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118920184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1118920184
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3955873198
Short name T147
Test name
Test status
Simulation time 10649888357 ps
CPU time 16.19 seconds
Started Jul 04 05:42:48 PM PDT 24
Finished Jul 04 05:43:04 PM PDT 24
Peak memory 199988 kb
Host smart-fa055554-46df-4eb9-a5eb-e0397d825b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955873198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3955873198
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2350360779
Short name T130
Test name
Test status
Simulation time 11526541715 ps
CPU time 28.63 seconds
Started Jul 04 05:43:10 PM PDT 24
Finished Jul 04 05:43:38 PM PDT 24
Peak memory 199924 kb
Host smart-89fc40c6-aa38-4cd5-81c6-8acad558e28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350360779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2350360779
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.844388080
Short name T602
Test name
Test status
Simulation time 153326765626 ps
CPU time 88.84 seconds
Started Jul 04 05:40:28 PM PDT 24
Finished Jul 04 05:41:57 PM PDT 24
Peak memory 199920 kb
Host smart-e1a0f89d-0f98-49f3-944e-d64d0e1fd2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844388080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.844388080
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1028893134
Short name T40
Test name
Test status
Simulation time 33763732543 ps
CPU time 109.85 seconds
Started Jul 04 05:41:37 PM PDT 24
Finished Jul 04 05:43:27 PM PDT 24
Peak memory 215832 kb
Host smart-7d84581c-d94e-4a59-9747-0a45d912ac8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028893134 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1028893134
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3531631305
Short name T113
Test name
Test status
Simulation time 15831303057 ps
CPU time 25.81 seconds
Started Jul 04 05:43:47 PM PDT 24
Finished Jul 04 05:44:13 PM PDT 24
Peak memory 199912 kb
Host smart-3ffbbb54-9f55-4dc6-8008-b813de87c1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531631305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3531631305
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.579640947
Short name T1073
Test name
Test status
Simulation time 353851940385 ps
CPU time 896.82 seconds
Started Jul 04 05:42:11 PM PDT 24
Finished Jul 04 05:57:08 PM PDT 24
Peak memory 226404 kb
Host smart-5aae93cc-4e90-4b45-bd52-5a940a23209b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579640947 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.579640947
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3216712831
Short name T90
Test name
Test status
Simulation time 136381785568 ps
CPU time 762.29 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:55:19 PM PDT 24
Peak memory 216336 kb
Host smart-10022983-2827-4fda-bff9-108231f05b87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216712831 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3216712831
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3474053730
Short name T125
Test name
Test status
Simulation time 62711512752 ps
CPU time 24.8 seconds
Started Jul 04 05:38:14 PM PDT 24
Finished Jul 04 05:38:39 PM PDT 24
Peak memory 199956 kb
Host smart-97f30651-f148-4043-9f49-992e4ac0d5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474053730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3474053730
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1471804463
Short name T216
Test name
Test status
Simulation time 64296705208 ps
CPU time 18.44 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:42:56 PM PDT 24
Peak memory 199816 kb
Host smart-17927d15-d0aa-4a96-930c-1d0926386ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471804463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1471804463
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2386625118
Short name T191
Test name
Test status
Simulation time 76579755212 ps
CPU time 25.65 seconds
Started Jul 04 05:43:41 PM PDT 24
Finished Jul 04 05:44:06 PM PDT 24
Peak memory 199864 kb
Host smart-eab0a0b7-02f2-4429-8174-b5d408a4b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386625118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2386625118
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.4111068692
Short name T286
Test name
Test status
Simulation time 69626396129 ps
CPU time 673.54 seconds
Started Jul 04 05:40:35 PM PDT 24
Finished Jul 04 05:51:48 PM PDT 24
Peak memory 228912 kb
Host smart-2cdc381a-bb2d-447d-88ce-1100a32fe003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111068692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.4111068692
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.2877713509
Short name T815
Test name
Test status
Simulation time 165757810812 ps
CPU time 278.54 seconds
Started Jul 04 05:38:15 PM PDT 24
Finished Jul 04 05:42:54 PM PDT 24
Peak memory 199896 kb
Host smart-fe7deab9-0345-4227-bcfc-16e1665de5b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877713509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2877713509
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_noise_filter.725890161
Short name T241
Test name
Test status
Simulation time 89401910126 ps
CPU time 38.62 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:39:14 PM PDT 24
Peak memory 199280 kb
Host smart-f462639e-ae51-4177-9340-ecc363a0e61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725890161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.725890161
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2500703525
Short name T209
Test name
Test status
Simulation time 153394016503 ps
CPU time 56.71 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:43:34 PM PDT 24
Peak memory 199856 kb
Host smart-b63880e8-f5af-4e66-b835-6b2f0d6bb65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500703525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2500703525
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2310552446
Short name T104
Test name
Test status
Simulation time 41658022886 ps
CPU time 47.42 seconds
Started Jul 04 05:42:42 PM PDT 24
Finished Jul 04 05:43:29 PM PDT 24
Peak memory 199864 kb
Host smart-1d09383b-9d1c-442a-a47a-217f421479d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310552446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2310552446
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1401535479
Short name T146
Test name
Test status
Simulation time 125388332055 ps
CPU time 214.71 seconds
Started Jul 04 05:42:48 PM PDT 24
Finished Jul 04 05:46:23 PM PDT 24
Peak memory 199944 kb
Host smart-8ab0370c-b924-4e60-a38a-0abc263f0db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401535479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1401535479
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1406661604
Short name T124
Test name
Test status
Simulation time 39421280168 ps
CPU time 34.21 seconds
Started Jul 04 05:42:42 PM PDT 24
Finished Jul 04 05:43:16 PM PDT 24
Peak memory 199956 kb
Host smart-79e29351-59ac-4436-8e57-55dc7c1cb1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406661604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1406661604
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.4187248763
Short name T13
Test name
Test status
Simulation time 87353434740 ps
CPU time 61.43 seconds
Started Jul 04 05:42:49 PM PDT 24
Finished Jul 04 05:43:51 PM PDT 24
Peak memory 199960 kb
Host smart-f1f13da1-917f-435d-bb26-2f8601205328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187248763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4187248763
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.3603844836
Short name T119
Test name
Test status
Simulation time 104581749043 ps
CPU time 128.95 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:41:06 PM PDT 24
Peak memory 199924 kb
Host smart-9ba446b1-3433-4fbf-b0b1-a54f8da9e5ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603844836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3603844836
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2601430565
Short name T195
Test name
Test status
Simulation time 189564530335 ps
CPU time 107.55 seconds
Started Jul 04 05:42:54 PM PDT 24
Finished Jul 04 05:44:42 PM PDT 24
Peak memory 199960 kb
Host smart-33d6571b-d6ac-4cd6-a410-568ec2084754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601430565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2601430565
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2427842144
Short name T138
Test name
Test status
Simulation time 190182710093 ps
CPU time 58.41 seconds
Started Jul 04 05:43:03 PM PDT 24
Finished Jul 04 05:44:02 PM PDT 24
Peak memory 199872 kb
Host smart-b4a54c49-b18d-40fc-a95f-109bda62761b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427842144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2427842144
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2081271533
Short name T217
Test name
Test status
Simulation time 67109605865 ps
CPU time 54.79 seconds
Started Jul 04 05:43:03 PM PDT 24
Finished Jul 04 05:43:58 PM PDT 24
Peak memory 199896 kb
Host smart-9df762b8-3f07-4d1a-9912-c63c2b11dbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081271533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2081271533
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2481146194
Short name T463
Test name
Test status
Simulation time 75528535289 ps
CPU time 257.66 seconds
Started Jul 04 05:43:11 PM PDT 24
Finished Jul 04 05:47:29 PM PDT 24
Peak memory 199988 kb
Host smart-394720f0-c83d-44c0-a35c-750f9ee3cbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481146194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2481146194
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3856973004
Short name T135
Test name
Test status
Simulation time 53172114377 ps
CPU time 25.21 seconds
Started Jul 04 05:43:11 PM PDT 24
Finished Jul 04 05:43:36 PM PDT 24
Peak memory 199948 kb
Host smart-6c047b55-14a8-42e9-8f5f-bbe5a22fe1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856973004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3856973004
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.4037615779
Short name T133
Test name
Test status
Simulation time 79101044683 ps
CPU time 127.26 seconds
Started Jul 04 05:43:11 PM PDT 24
Finished Jul 04 05:45:19 PM PDT 24
Peak memory 199884 kb
Host smart-71bae48a-45d3-4f96-aea2-594ca2eb871e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037615779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4037615779
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.890287621
Short name T201
Test name
Test status
Simulation time 68239010453 ps
CPU time 16.85 seconds
Started Jul 04 05:43:19 PM PDT 24
Finished Jul 04 05:43:36 PM PDT 24
Peak memory 199912 kb
Host smart-d7fa53eb-735e-45b8-8b66-82a99744fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890287621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.890287621
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2662039448
Short name T218
Test name
Test status
Simulation time 61119096820 ps
CPU time 30.36 seconds
Started Jul 04 05:43:27 PM PDT 24
Finished Jul 04 05:43:58 PM PDT 24
Peak memory 199948 kb
Host smart-f018ef10-afb6-4f6e-b9da-78781ed0efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662039448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2662039448
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2499770403
Short name T167
Test name
Test status
Simulation time 19303043111 ps
CPU time 33.97 seconds
Started Jul 04 05:43:26 PM PDT 24
Finished Jul 04 05:44:00 PM PDT 24
Peak memory 199996 kb
Host smart-0fd27339-fc40-4307-98a5-3311da404a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499770403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2499770403
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2530994932
Short name T208
Test name
Test status
Simulation time 23399007333 ps
CPU time 22.06 seconds
Started Jul 04 05:43:26 PM PDT 24
Finished Jul 04 05:43:48 PM PDT 24
Peak memory 199932 kb
Host smart-af7627ed-8e88-496a-8863-f7c9618b0179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530994932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2530994932
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2972280601
Short name T219
Test name
Test status
Simulation time 39683796941 ps
CPU time 14.26 seconds
Started Jul 04 05:43:33 PM PDT 24
Finished Jul 04 05:43:47 PM PDT 24
Peak memory 199956 kb
Host smart-4b81e5f2-d604-468a-b7c6-6591dd98a66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972280601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2972280601
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.3131791971
Short name T213
Test name
Test status
Simulation time 241659692999 ps
CPU time 380.23 seconds
Started Jul 04 05:39:36 PM PDT 24
Finished Jul 04 05:45:56 PM PDT 24
Peak memory 199936 kb
Host smart-ba7efc6b-3eee-41f9-853e-4220fe08fb18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131791971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3131791971
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1382901231
Short name T202
Test name
Test status
Simulation time 299521045928 ps
CPU time 41.99 seconds
Started Jul 04 05:43:56 PM PDT 24
Finished Jul 04 05:44:38 PM PDT 24
Peak memory 200004 kb
Host smart-91bbe87d-9ffa-4c93-b4eb-227931d5d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382901231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1382901231
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.637662440
Short name T199
Test name
Test status
Simulation time 20094034534 ps
CPU time 32.43 seconds
Started Jul 04 05:40:34 PM PDT 24
Finished Jul 04 05:41:06 PM PDT 24
Peak memory 199940 kb
Host smart-fd2730c8-8c08-4c5e-83d2-4b14940d568d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637662440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.637662440
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3864790362
Short name T155
Test name
Test status
Simulation time 19730866067 ps
CPU time 30 seconds
Started Jul 04 05:42:03 PM PDT 24
Finished Jul 04 05:42:34 PM PDT 24
Peak memory 199928 kb
Host smart-8d87015c-feef-4149-8585-52279c974dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864790362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3864790362
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.4233577474
Short name T204
Test name
Test status
Simulation time 36656168911 ps
CPU time 15.48 seconds
Started Jul 04 05:42:05 PM PDT 24
Finished Jul 04 05:42:21 PM PDT 24
Peak memory 199964 kb
Host smart-054885d3-0a25-47e6-9299-88fc673f42fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233577474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.4233577474
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1314929382
Short name T1203
Test name
Test status
Simulation time 669041174 ps
CPU time 2.52 seconds
Started Jul 04 04:47:46 PM PDT 24
Finished Jul 04 04:47:49 PM PDT 24
Peak memory 198356 kb
Host smart-f8e36151-27d1-4c30-814a-2264fb523457
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314929382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1314929382
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4160317076
Short name T1313
Test name
Test status
Simulation time 46540893 ps
CPU time 0.6 seconds
Started Jul 04 04:47:49 PM PDT 24
Finished Jul 04 04:47:49 PM PDT 24
Peak memory 196104 kb
Host smart-85fc5d7f-e85f-403b-807b-87918884dd87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160317076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4160317076
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2694017576
Short name T1235
Test name
Test status
Simulation time 19493956 ps
CPU time 0.67 seconds
Started Jul 04 04:47:39 PM PDT 24
Finished Jul 04 04:47:40 PM PDT 24
Peak memory 198492 kb
Host smart-30620c62-1b08-448b-8b76-5abe89677d71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694017576 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2694017576
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1472686122
Short name T1210
Test name
Test status
Simulation time 32074368 ps
CPU time 0.65 seconds
Started Jul 04 04:48:03 PM PDT 24
Finished Jul 04 04:48:04 PM PDT 24
Peak memory 196080 kb
Host smart-69ac5390-c56e-4aed-9388-81eb56afa48c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472686122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1472686122
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3138927831
Short name T1286
Test name
Test status
Simulation time 20170889 ps
CPU time 0.56 seconds
Started Jul 04 04:47:54 PM PDT 24
Finished Jul 04 04:47:55 PM PDT 24
Peak memory 195040 kb
Host smart-b8b46ddd-a4de-4f3a-b2b8-d4658212ec76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138927831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3138927831
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1757761021
Short name T1252
Test name
Test status
Simulation time 633770494 ps
CPU time 1.34 seconds
Started Jul 04 04:47:37 PM PDT 24
Finished Jul 04 04:47:39 PM PDT 24
Peak memory 200660 kb
Host smart-7ffb3761-ac41-4109-bd6a-59cb682febbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757761021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1757761021
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4250547114
Short name T101
Test name
Test status
Simulation time 182593530 ps
CPU time 0.99 seconds
Started Jul 04 04:47:59 PM PDT 24
Finished Jul 04 04:48:00 PM PDT 24
Peak memory 199700 kb
Host smart-887e15a8-2bf4-460d-a657-75352d1aad9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250547114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.4250547114
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2299935304
Short name T48
Test name
Test status
Simulation time 61072425 ps
CPU time 0.64 seconds
Started Jul 04 04:47:54 PM PDT 24
Finished Jul 04 04:47:55 PM PDT 24
Peak memory 196024 kb
Host smart-ddcb10b8-908d-43d7-a0aa-c0a18204be7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299935304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2299935304
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2629406469
Short name T1186
Test name
Test status
Simulation time 34789275 ps
CPU time 1.47 seconds
Started Jul 04 04:47:59 PM PDT 24
Finished Jul 04 04:48:01 PM PDT 24
Peak memory 198408 kb
Host smart-176b022f-c49a-4f26-be51-dbcbedd10422
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629406469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2629406469
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1069413452
Short name T1206
Test name
Test status
Simulation time 101454044 ps
CPU time 0.61 seconds
Started Jul 04 04:47:58 PM PDT 24
Finished Jul 04 04:47:59 PM PDT 24
Peak memory 196004 kb
Host smart-72083f33-694f-4373-8073-f453b42ad798
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069413452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1069413452
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1044966791
Short name T1217
Test name
Test status
Simulation time 60047307 ps
CPU time 0.82 seconds
Started Jul 04 04:47:54 PM PDT 24
Finished Jul 04 04:47:54 PM PDT 24
Peak memory 200436 kb
Host smart-d18dc8ed-815a-4ec6-8368-3f3090c71081
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044966791 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1044966791
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1138850855
Short name T50
Test name
Test status
Simulation time 79846591 ps
CPU time 0.59 seconds
Started Jul 04 04:47:58 PM PDT 24
Finished Jul 04 04:47:59 PM PDT 24
Peak memory 196184 kb
Host smart-1aeff414-fe63-404f-b3da-147643d1b1f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138850855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1138850855
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2229717644
Short name T1237
Test name
Test status
Simulation time 16839581 ps
CPU time 0.6 seconds
Started Jul 04 04:48:02 PM PDT 24
Finished Jul 04 04:48:03 PM PDT 24
Peak memory 195000 kb
Host smart-feb3fb7b-a356-4698-a912-1621426f0299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229717644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2229717644
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.302265401
Short name T1244
Test name
Test status
Simulation time 78074134 ps
CPU time 0.63 seconds
Started Jul 04 04:47:54 PM PDT 24
Finished Jul 04 04:47:55 PM PDT 24
Peak memory 195300 kb
Host smart-a7db141e-02f1-44ea-afba-8b81effd3a04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302265401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.302265401
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.677205346
Short name T1188
Test name
Test status
Simulation time 51651817 ps
CPU time 1.33 seconds
Started Jul 04 04:47:47 PM PDT 24
Finished Jul 04 04:47:48 PM PDT 24
Peak memory 200724 kb
Host smart-32e704c9-0b0d-4db0-84b5-d65b0a0cfb93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677205346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.677205346
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3854488136
Short name T1265
Test name
Test status
Simulation time 206683694 ps
CPU time 0.96 seconds
Started Jul 04 04:47:46 PM PDT 24
Finished Jul 04 04:47:47 PM PDT 24
Peak memory 199776 kb
Host smart-a978cb95-5d91-4b36-b702-d7b275c4ab46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854488136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3854488136
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1119579345
Short name T1224
Test name
Test status
Simulation time 39377926 ps
CPU time 0.92 seconds
Started Jul 04 04:48:01 PM PDT 24
Finished Jul 04 04:48:02 PM PDT 24
Peak memory 200480 kb
Host smart-f0ea097d-e4d4-48a8-83b9-66f909f9a9cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119579345 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1119579345
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3678315968
Short name T1271
Test name
Test status
Simulation time 13436504 ps
CPU time 0.57 seconds
Started Jul 04 04:47:56 PM PDT 24
Finished Jul 04 04:47:57 PM PDT 24
Peak memory 196100 kb
Host smart-c953ee97-3437-4efc-a961-97c255327ff5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678315968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3678315968
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3333630152
Short name T1302
Test name
Test status
Simulation time 14537464 ps
CPU time 0.58 seconds
Started Jul 04 04:48:00 PM PDT 24
Finished Jul 04 04:48:01 PM PDT 24
Peak memory 195028 kb
Host smart-18c6653a-ef06-4ead-b280-a0416d8469cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333630152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3333630152
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1102787880
Short name T61
Test name
Test status
Simulation time 108028543 ps
CPU time 0.64 seconds
Started Jul 04 04:48:01 PM PDT 24
Finished Jul 04 04:48:02 PM PDT 24
Peak memory 195276 kb
Host smart-8a5b51f5-a5b1-4c62-9c5d-3ac54f6ef2dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102787880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1102787880
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1835316070
Short name T1180
Test name
Test status
Simulation time 131859240 ps
CPU time 1.67 seconds
Started Jul 04 04:48:00 PM PDT 24
Finished Jul 04 04:48:02 PM PDT 24
Peak memory 200724 kb
Host smart-f6d9d03a-f258-48b2-a08f-9734eab310f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835316070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1835316070
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3786086989
Short name T102
Test name
Test status
Simulation time 181871721 ps
CPU time 1.31 seconds
Started Jul 04 04:48:02 PM PDT 24
Finished Jul 04 04:48:04 PM PDT 24
Peak memory 199840 kb
Host smart-a3ff09b7-4f7b-4392-88f9-3f8cc85bf7b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786086989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3786086989
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2340926811
Short name T1284
Test name
Test status
Simulation time 103453668 ps
CPU time 1.29 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:15 PM PDT 24
Peak memory 200720 kb
Host smart-ee068284-0956-4721-8d64-ec1000f85a71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340926811 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2340926811
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2158582531
Short name T1311
Test name
Test status
Simulation time 53695192 ps
CPU time 0.57 seconds
Started Jul 04 04:48:02 PM PDT 24
Finished Jul 04 04:48:03 PM PDT 24
Peak memory 196044 kb
Host smart-17703e86-aa26-463d-98c3-b01bb2018c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158582531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2158582531
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1290763634
Short name T1293
Test name
Test status
Simulation time 47728557 ps
CPU time 0.61 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:07 PM PDT 24
Peak memory 195056 kb
Host smart-c13c282e-320d-4ba1-8dad-ff6ac3e5702e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290763634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1290763634
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3752596483
Short name T1294
Test name
Test status
Simulation time 26030565 ps
CPU time 0.75 seconds
Started Jul 04 04:48:03 PM PDT 24
Finished Jul 04 04:48:04 PM PDT 24
Peak memory 197728 kb
Host smart-3d573160-f24d-404f-a1c1-32ff77cba7b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752596483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3752596483
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3514202678
Short name T1175
Test name
Test status
Simulation time 930533037 ps
CPU time 1.4 seconds
Started Jul 04 04:47:52 PM PDT 24
Finished Jul 04 04:47:53 PM PDT 24
Peak memory 200668 kb
Host smart-7dd597e2-594b-4faa-82c5-fd3f3f73f5c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514202678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3514202678
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4129419251
Short name T1223
Test name
Test status
Simulation time 218302794 ps
CPU time 1.12 seconds
Started Jul 04 04:48:05 PM PDT 24
Finished Jul 04 04:48:07 PM PDT 24
Peak memory 200448 kb
Host smart-c870d6fe-1256-474e-a823-97e21f6b56a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129419251 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.4129419251
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2086307961
Short name T62
Test name
Test status
Simulation time 25604476 ps
CPU time 0.59 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 196064 kb
Host smart-8fcd7447-bb66-457b-9935-e54d733a3897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086307961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2086307961
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3751267029
Short name T1273
Test name
Test status
Simulation time 44395397 ps
CPU time 0.59 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 195064 kb
Host smart-5d61cea6-b4c0-47d3-a20e-13dbc3061c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751267029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3751267029
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2709098518
Short name T1306
Test name
Test status
Simulation time 52981346 ps
CPU time 0.64 seconds
Started Jul 04 04:47:56 PM PDT 24
Finished Jul 04 04:47:57 PM PDT 24
Peak memory 196128 kb
Host smart-04d63e11-560d-453d-8446-0b642115dd89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709098518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2709098518
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1432340577
Short name T1213
Test name
Test status
Simulation time 963589770 ps
CPU time 2.05 seconds
Started Jul 04 04:47:51 PM PDT 24
Finished Jul 04 04:47:54 PM PDT 24
Peak memory 200720 kb
Host smart-bf9bbda9-1ae5-4dc9-b238-712ca126cce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432340577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1432340577
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1012579319
Short name T77
Test name
Test status
Simulation time 192454432 ps
CPU time 1.34 seconds
Started Jul 04 04:47:51 PM PDT 24
Finished Jul 04 04:47:52 PM PDT 24
Peak memory 200032 kb
Host smart-a08938c8-5e75-4f89-80fe-bd113870c765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012579319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1012579319
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1063229490
Short name T1310
Test name
Test status
Simulation time 31140501 ps
CPU time 0.84 seconds
Started Jul 04 04:48:10 PM PDT 24
Finished Jul 04 04:48:11 PM PDT 24
Peak memory 200468 kb
Host smart-19b8b330-9d09-4075-b754-355338fa80a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063229490 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1063229490
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3030187929
Short name T1182
Test name
Test status
Simulation time 16050466 ps
CPU time 0.58 seconds
Started Jul 04 04:47:55 PM PDT 24
Finished Jul 04 04:47:56 PM PDT 24
Peak memory 196032 kb
Host smart-b961e73e-00ff-4ff3-a2b0-332af4af59fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030187929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3030187929
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1380985422
Short name T1305
Test name
Test status
Simulation time 60706539 ps
CPU time 0.55 seconds
Started Jul 04 04:47:56 PM PDT 24
Finished Jul 04 04:47:57 PM PDT 24
Peak memory 195064 kb
Host smart-0a0f49eb-2a8c-4f43-b7d0-9565d5f5398d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380985422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1380985422
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3041737718
Short name T64
Test name
Test status
Simulation time 115331258 ps
CPU time 0.76 seconds
Started Jul 04 04:47:59 PM PDT 24
Finished Jul 04 04:48:00 PM PDT 24
Peak memory 196672 kb
Host smart-092a1c8b-13ac-4957-b58b-375e8edbbf4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041737718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3041737718
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.483577349
Short name T1300
Test name
Test status
Simulation time 24507551 ps
CPU time 1.13 seconds
Started Jul 04 04:47:55 PM PDT 24
Finished Jul 04 04:47:57 PM PDT 24
Peak memory 200676 kb
Host smart-4ce691cb-bbed-4050-9d01-8b664ca65a0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483577349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.483577349
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1119600020
Short name T1215
Test name
Test status
Simulation time 116383123 ps
CPU time 0.86 seconds
Started Jul 04 04:48:00 PM PDT 24
Finished Jul 04 04:48:02 PM PDT 24
Peak memory 200412 kb
Host smart-03723620-a6b5-4e1d-ba39-9d7851fe875e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119600020 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1119600020
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2282227583
Short name T1288
Test name
Test status
Simulation time 40595963 ps
CPU time 0.57 seconds
Started Jul 04 04:47:58 PM PDT 24
Finished Jul 04 04:47:59 PM PDT 24
Peak memory 196068 kb
Host smart-a2103fd4-1644-4da8-9e91-8b4d5913c3eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282227583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2282227583
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1543055742
Short name T1196
Test name
Test status
Simulation time 29936973 ps
CPU time 0.56 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:07 PM PDT 24
Peak memory 195084 kb
Host smart-340558e1-024c-43a7-b97f-dffee996c8ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543055742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1543055742
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2026935647
Short name T1205
Test name
Test status
Simulation time 34799922 ps
CPU time 0.81 seconds
Started Jul 04 04:48:04 PM PDT 24
Finished Jul 04 04:48:05 PM PDT 24
Peak memory 196744 kb
Host smart-a1153e73-d0cc-48b0-bc29-80b97ca72adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026935647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2026935647
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.179889623
Short name T1309
Test name
Test status
Simulation time 68782847 ps
CPU time 1.6 seconds
Started Jul 04 04:47:56 PM PDT 24
Finished Jul 04 04:47:58 PM PDT 24
Peak memory 200664 kb
Host smart-28841d71-bbf6-420a-ba49-68ab9dc7ba2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179889623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.179889623
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.175560178
Short name T1231
Test name
Test status
Simulation time 170970766 ps
CPU time 0.97 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 199648 kb
Host smart-fe913ae0-4067-47c5-9826-a9276351e8e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175560178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.175560178
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.100231721
Short name T1197
Test name
Test status
Simulation time 79669449 ps
CPU time 0.76 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:13 PM PDT 24
Peak memory 199560 kb
Host smart-92edf85c-6d88-46ba-a611-9c3d51f00c7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100231721 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.100231721
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.322454851
Short name T1225
Test name
Test status
Simulation time 12888981 ps
CPU time 0.6 seconds
Started Jul 04 04:48:14 PM PDT 24
Finished Jul 04 04:48:15 PM PDT 24
Peak memory 196048 kb
Host smart-5e3f0761-8181-403b-8dbc-5f2660aaddb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322454851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.322454851
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.160104059
Short name T1281
Test name
Test status
Simulation time 15659335 ps
CPU time 0.59 seconds
Started Jul 04 04:48:04 PM PDT 24
Finished Jul 04 04:48:05 PM PDT 24
Peak memory 195080 kb
Host smart-9faaecb0-1e3f-456c-a3a8-3aa4b32482e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160104059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.160104059
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3094172212
Short name T67
Test name
Test status
Simulation time 53207302 ps
CPU time 0.67 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:18 PM PDT 24
Peak memory 196100 kb
Host smart-74ddca51-8c33-467a-b466-6f9c49c912bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094172212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3094172212
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3150864957
Short name T1312
Test name
Test status
Simulation time 29868786 ps
CPU time 1.64 seconds
Started Jul 04 04:48:01 PM PDT 24
Finished Jul 04 04:48:03 PM PDT 24
Peak memory 200688 kb
Host smart-83f4dce3-4820-4188-8a96-f1a23fd351f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150864957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3150864957
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3325196763
Short name T73
Test name
Test status
Simulation time 391874648 ps
CPU time 1.34 seconds
Started Jul 04 04:47:58 PM PDT 24
Finished Jul 04 04:48:00 PM PDT 24
Peak memory 199972 kb
Host smart-c41c79ca-fd7f-4dad-8a60-5238cafb093f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325196763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3325196763
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2172203499
Short name T1260
Test name
Test status
Simulation time 18816112 ps
CPU time 0.86 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:15 PM PDT 24
Peak memory 200112 kb
Host smart-a57e00f1-1e42-412b-9760-459fe4d78be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172203499 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2172203499
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2794968394
Short name T1208
Test name
Test status
Simulation time 24468204 ps
CPU time 0.61 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 196124 kb
Host smart-5a978cb5-3895-44a5-a89f-e54557fce95d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794968394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2794968394
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2050252462
Short name T1211
Test name
Test status
Simulation time 37692833 ps
CPU time 0.56 seconds
Started Jul 04 04:48:09 PM PDT 24
Finished Jul 04 04:48:10 PM PDT 24
Peak memory 194988 kb
Host smart-79a6bf3a-cf9b-4ddd-ad63-b53bd6f55cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050252462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2050252462
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1409423387
Short name T1228
Test name
Test status
Simulation time 60830273 ps
CPU time 0.7 seconds
Started Jul 04 04:48:04 PM PDT 24
Finished Jul 04 04:48:05 PM PDT 24
Peak memory 197372 kb
Host smart-733bdb42-dc3c-4c16-82c2-41989f365540
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409423387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1409423387
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1729504379
Short name T1221
Test name
Test status
Simulation time 44449075 ps
CPU time 1.28 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:17 PM PDT 24
Peak memory 200700 kb
Host smart-9f183b5b-747e-4679-94b0-04c28b8be8e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729504379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1729504379
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2915184053
Short name T74
Test name
Test status
Simulation time 141093845 ps
CPU time 0.93 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 199472 kb
Host smart-8a2fa710-dbf5-46cd-945b-4fe5693f987f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915184053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2915184053
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.64104874
Short name T1236
Test name
Test status
Simulation time 22207393 ps
CPU time 0.97 seconds
Started Jul 04 04:48:08 PM PDT 24
Finished Jul 04 04:48:09 PM PDT 24
Peak memory 200476 kb
Host smart-309b7de3-17bd-4e4f-8d60-0ce310e5c892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64104874 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.64104874
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1709231050
Short name T1295
Test name
Test status
Simulation time 16206289 ps
CPU time 0.57 seconds
Started Jul 04 04:48:14 PM PDT 24
Finished Jul 04 04:48:15 PM PDT 24
Peak memory 196076 kb
Host smart-b21f7064-484a-4707-8ef9-96d93b278315
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709231050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1709231050
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.139736789
Short name T1209
Test name
Test status
Simulation time 19512928 ps
CPU time 0.58 seconds
Started Jul 04 04:48:14 PM PDT 24
Finished Jul 04 04:48:15 PM PDT 24
Peak memory 194964 kb
Host smart-cd016d4c-f98f-49ad-bf54-54857e9e00a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139736789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.139736789
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1925796118
Short name T1308
Test name
Test status
Simulation time 19978879 ps
CPU time 0.72 seconds
Started Jul 04 04:48:03 PM PDT 24
Finished Jul 04 04:48:04 PM PDT 24
Peak memory 196372 kb
Host smart-a12fbf4a-6417-47b3-b269-47e0dd7428e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925796118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1925796118
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1853482599
Short name T1222
Test name
Test status
Simulation time 26917570 ps
CPU time 0.84 seconds
Started Jul 04 04:48:12 PM PDT 24
Finished Jul 04 04:48:13 PM PDT 24
Peak memory 200408 kb
Host smart-8dff0dd4-d1e2-486f-85ec-100d1e986738
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853482599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1853482599
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3222959903
Short name T1247
Test name
Test status
Simulation time 265598131 ps
CPU time 1.28 seconds
Started Jul 04 04:48:18 PM PDT 24
Finished Jul 04 04:48:20 PM PDT 24
Peak memory 199992 kb
Host smart-20f09a2f-a2de-4938-a2f5-8a822c03580e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222959903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3222959903
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.564929625
Short name T1239
Test name
Test status
Simulation time 32077491 ps
CPU time 0.81 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:15 PM PDT 24
Peak memory 200456 kb
Host smart-e72b8da9-8fe4-4f06-bdee-8fcd369c56db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564929625 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.564929625
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.221613100
Short name T1179
Test name
Test status
Simulation time 44270638 ps
CPU time 0.6 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:48:18 PM PDT 24
Peak memory 196016 kb
Host smart-20f1bf08-a2fd-4ce0-b94a-74e1179452e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221613100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.221613100
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.568214120
Short name T1278
Test name
Test status
Simulation time 49604149 ps
CPU time 0.58 seconds
Started Jul 04 04:48:09 PM PDT 24
Finished Jul 04 04:48:09 PM PDT 24
Peak memory 195032 kb
Host smart-d7359fe1-5b77-417f-9459-10cad1adc82a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568214120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.568214120
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.572081482
Short name T1277
Test name
Test status
Simulation time 28237743 ps
CPU time 0.63 seconds
Started Jul 04 04:48:10 PM PDT 24
Finished Jul 04 04:48:11 PM PDT 24
Peak memory 195284 kb
Host smart-480be273-b1ea-412e-affa-04c6c2edf71e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572081482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.572081482
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2288278294
Short name T1214
Test name
Test status
Simulation time 28760248 ps
CPU time 1.41 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:09 PM PDT 24
Peak memory 200708 kb
Host smart-a2c4afa5-aaa4-4f1b-99e8-4b0d659927d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288278294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2288278294
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3176911356
Short name T1301
Test name
Test status
Simulation time 89850330 ps
CPU time 1.3 seconds
Started Jul 04 04:48:14 PM PDT 24
Finished Jul 04 04:48:16 PM PDT 24
Peak memory 200004 kb
Host smart-dbca4061-5333-459e-a69b-ea6403787c54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176911356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3176911356
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.320783897
Short name T1289
Test name
Test status
Simulation time 51499807 ps
CPU time 0.71 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:19 PM PDT 24
Peak memory 199384 kb
Host smart-5523348b-1dda-4c97-8696-4a5155930b3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320783897 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.320783897
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1872689302
Short name T63
Test name
Test status
Simulation time 111660574 ps
CPU time 0.56 seconds
Started Jul 04 04:48:12 PM PDT 24
Finished Jul 04 04:48:13 PM PDT 24
Peak memory 196064 kb
Host smart-020320b0-564a-47bf-b494-427025018913
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872689302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1872689302
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2051636764
Short name T1280
Test name
Test status
Simulation time 16114769 ps
CPU time 0.59 seconds
Started Jul 04 04:48:04 PM PDT 24
Finished Jul 04 04:48:05 PM PDT 24
Peak memory 195072 kb
Host smart-3cbef831-faf1-434e-9593-5d869f1daf5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051636764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2051636764
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.337989211
Short name T1234
Test name
Test status
Simulation time 60731118 ps
CPU time 0.69 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:09 PM PDT 24
Peak memory 196500 kb
Host smart-95c1a8e8-6f8d-4ce5-b3ae-156185efb436
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337989211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.337989211
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3505054326
Short name T1259
Test name
Test status
Simulation time 27314943 ps
CPU time 1.37 seconds
Started Jul 04 04:48:06 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 200664 kb
Host smart-cd47a63c-5d5d-4c88-8af8-766b801c95e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505054326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3505054326
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2640154868
Short name T76
Test name
Test status
Simulation time 109275658 ps
CPU time 1.31 seconds
Started Jul 04 04:48:08 PM PDT 24
Finished Jul 04 04:48:10 PM PDT 24
Peak memory 199804 kb
Host smart-59066e1a-fc96-42c2-a023-e6af369e6cc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640154868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2640154868
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2999750179
Short name T47
Test name
Test status
Simulation time 532656990 ps
CPU time 0.76 seconds
Started Jul 04 04:47:42 PM PDT 24
Finished Jul 04 04:47:43 PM PDT 24
Peak memory 197504 kb
Host smart-edd6d70d-d9f5-4f36-9517-c248234f58b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999750179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2999750179
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4023343598
Short name T1189
Test name
Test status
Simulation time 106236772 ps
CPU time 2.23 seconds
Started Jul 04 04:48:10 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 198296 kb
Host smart-a22da791-708b-48c6-8fc9-1b19c0a4e8a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023343598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4023343598
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3482844122
Short name T1304
Test name
Test status
Simulation time 63945986 ps
CPU time 0.59 seconds
Started Jul 04 04:48:09 PM PDT 24
Finished Jul 04 04:48:10 PM PDT 24
Peak memory 196020 kb
Host smart-4e8587b7-3061-4eb3-b402-93c91778ccc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482844122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3482844122
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4063084543
Short name T1192
Test name
Test status
Simulation time 34479172 ps
CPU time 0.73 seconds
Started Jul 04 04:47:55 PM PDT 24
Finished Jul 04 04:47:56 PM PDT 24
Peak memory 199456 kb
Host smart-292710d5-e562-4b5f-b94e-af2989228f48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063084543 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.4063084543
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.656266452
Short name T1250
Test name
Test status
Simulation time 123266591 ps
CPU time 0.63 seconds
Started Jul 04 04:47:45 PM PDT 24
Finished Jul 04 04:47:46 PM PDT 24
Peak memory 196140 kb
Host smart-dc8d3750-d8e8-4b33-b6d5-7179f5c46879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656266452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.656266452
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2475068030
Short name T1201
Test name
Test status
Simulation time 28915669 ps
CPU time 0.59 seconds
Started Jul 04 04:47:50 PM PDT 24
Finished Jul 04 04:47:50 PM PDT 24
Peak memory 195092 kb
Host smart-b179299f-42d5-4bff-b1c1-09de6cd2f757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475068030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2475068030
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3418666239
Short name T1267
Test name
Test status
Simulation time 51037907 ps
CPU time 0.71 seconds
Started Jul 04 04:47:55 PM PDT 24
Finished Jul 04 04:47:56 PM PDT 24
Peak memory 196332 kb
Host smart-62f27fc8-0aeb-4a8c-842b-13fee9ccb027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418666239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3418666239
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2407625877
Short name T1218
Test name
Test status
Simulation time 116661036 ps
CPU time 1.29 seconds
Started Jul 04 04:47:46 PM PDT 24
Finished Jul 04 04:47:47 PM PDT 24
Peak memory 200684 kb
Host smart-16d7a6cd-1953-40c2-8cef-0a6493a09454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407625877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2407625877
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.74581792
Short name T100
Test name
Test status
Simulation time 213167958 ps
CPU time 0.96 seconds
Started Jul 04 04:47:48 PM PDT 24
Finished Jul 04 04:47:49 PM PDT 24
Peak memory 199504 kb
Host smart-e302e998-7c8e-4c2b-acc4-d70068f8f96c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74581792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.74581792
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.20490045
Short name T1256
Test name
Test status
Simulation time 39361502 ps
CPU time 0.56 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:17 PM PDT 24
Peak memory 195036 kb
Host smart-41358a81-38de-49fa-b405-b2fa91020151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20490045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.20490045
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.654412914
Short name T1177
Test name
Test status
Simulation time 12420160 ps
CPU time 0.56 seconds
Started Jul 04 04:48:19 PM PDT 24
Finished Jul 04 04:48:20 PM PDT 24
Peak memory 194948 kb
Host smart-743bd022-d940-4ba2-a27d-e5633694e12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654412914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.654412914
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3559602724
Short name T1296
Test name
Test status
Simulation time 14153422 ps
CPU time 0.58 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 195064 kb
Host smart-c3b6436a-f45e-4a87-a301-ded26836bbdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559602724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3559602724
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1001548412
Short name T1181
Test name
Test status
Simulation time 13698122 ps
CPU time 0.57 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 194928 kb
Host smart-b55cf9db-039d-4faf-80ce-662ab07b7a8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001548412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1001548412
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.853663910
Short name T1299
Test name
Test status
Simulation time 39171728 ps
CPU time 0.58 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:16 PM PDT 24
Peak memory 195064 kb
Host smart-24255f85-fa26-45a7-8e10-a11ec46d5035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853663910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.853663910
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3471057496
Short name T1255
Test name
Test status
Simulation time 13951992 ps
CPU time 0.56 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:14 PM PDT 24
Peak memory 194960 kb
Host smart-e13cd056-ebbc-46d1-bd59-594b77fb91a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471057496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3471057496
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.4960318
Short name T1246
Test name
Test status
Simulation time 21054823 ps
CPU time 0.58 seconds
Started Jul 04 04:48:18 PM PDT 24
Finished Jul 04 04:48:19 PM PDT 24
Peak memory 195072 kb
Host smart-0502b282-bc2c-4c1f-9220-0e1a24c800f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4960318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4960318
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.575318107
Short name T1261
Test name
Test status
Simulation time 15809239 ps
CPU time 0.56 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 195080 kb
Host smart-ccb069d8-f133-4691-aa91-7db942efa3d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575318107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.575318107
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.973708957
Short name T1200
Test name
Test status
Simulation time 53912265 ps
CPU time 0.57 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:14 PM PDT 24
Peak memory 195064 kb
Host smart-4b917fd2-1a8a-4cee-a612-2300d4c556cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973708957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.973708957
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3475396877
Short name T1202
Test name
Test status
Simulation time 49525827 ps
CPU time 0.55 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 194928 kb
Host smart-710ad458-3deb-4b7b-af2a-65a7b9c8fefa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475396877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3475396877
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.4226435517
Short name T1268
Test name
Test status
Simulation time 38189102 ps
CPU time 0.79 seconds
Started Jul 04 04:48:05 PM PDT 24
Finished Jul 04 04:48:06 PM PDT 24
Peak memory 196944 kb
Host smart-100f08cf-4683-41ce-b5de-fe75808c2748
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226435517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.4226435517
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.240933446
Short name T1287
Test name
Test status
Simulation time 114841462 ps
CPU time 2.28 seconds
Started Jul 04 04:47:57 PM PDT 24
Finished Jul 04 04:47:59 PM PDT 24
Peak memory 198312 kb
Host smart-7f00a7a6-1c20-486a-8027-6c3a0b1018d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240933446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.240933446
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.162843541
Short name T1275
Test name
Test status
Simulation time 1041969109 ps
CPU time 1.56 seconds
Started Jul 04 04:48:02 PM PDT 24
Finished Jul 04 04:48:03 PM PDT 24
Peak memory 196060 kb
Host smart-aa7de815-3efd-4396-9488-22442038a12c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162843541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.162843541
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2754365025
Short name T1303
Test name
Test status
Simulation time 23440351 ps
CPU time 1.01 seconds
Started Jul 04 04:47:56 PM PDT 24
Finished Jul 04 04:47:57 PM PDT 24
Peak memory 200432 kb
Host smart-1ab34096-3438-4b0e-b271-9e9f8f7303a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754365025 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2754365025
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1729675772
Short name T1248
Test name
Test status
Simulation time 14572845 ps
CPU time 0.66 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:13 PM PDT 24
Peak memory 196056 kb
Host smart-1744f9aa-25ff-4c6d-bc70-d353f2625440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729675772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1729675772
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.791925064
Short name T1245
Test name
Test status
Simulation time 12604982 ps
CPU time 0.56 seconds
Started Jul 04 04:47:55 PM PDT 24
Finished Jul 04 04:47:56 PM PDT 24
Peak memory 195064 kb
Host smart-09568f47-4b8e-4e55-ad5a-d92e59adf600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791925064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.791925064
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.493618669
Short name T1285
Test name
Test status
Simulation time 42974934 ps
CPU time 0.62 seconds
Started Jul 04 04:48:05 PM PDT 24
Finished Jul 04 04:48:06 PM PDT 24
Peak memory 196496 kb
Host smart-6ddf7493-812f-4f58-93f4-72f8cddb721e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493618669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.493618669
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2857437570
Short name T1270
Test name
Test status
Simulation time 272656869 ps
CPU time 1.63 seconds
Started Jul 04 04:47:54 PM PDT 24
Finished Jul 04 04:47:56 PM PDT 24
Peak memory 200732 kb
Host smart-58841851-aef9-4fb4-8b67-f0bf6e984b42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857437570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2857437570
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3249786936
Short name T99
Test name
Test status
Simulation time 134124397 ps
CPU time 1.39 seconds
Started Jul 04 04:47:58 PM PDT 24
Finished Jul 04 04:48:00 PM PDT 24
Peak memory 200052 kb
Host smart-2f1f1073-4606-4149-87b0-11bb04d64d87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249786936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3249786936
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1902044378
Short name T1292
Test name
Test status
Simulation time 12084336 ps
CPU time 0.57 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:48:18 PM PDT 24
Peak memory 195068 kb
Host smart-481b408d-98ae-48bd-9522-dc2f7378f150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902044378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1902044378
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3595797657
Short name T1198
Test name
Test status
Simulation time 21130947 ps
CPU time 0.58 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 195072 kb
Host smart-1ede534e-4a9d-4d9f-ba2a-b9e4330a3e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595797657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3595797657
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2355898520
Short name T1282
Test name
Test status
Simulation time 12805322 ps
CPU time 0.57 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 195004 kb
Host smart-cebc4d51-36d8-488d-9fae-776d4fb0a88a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355898520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2355898520
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3626677616
Short name T1262
Test name
Test status
Simulation time 61392435 ps
CPU time 0.59 seconds
Started Jul 04 04:48:09 PM PDT 24
Finished Jul 04 04:48:10 PM PDT 24
Peak memory 195072 kb
Host smart-84686a47-1bee-40d6-9f88-d2458ebc6cab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626677616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3626677616
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.186098996
Short name T1272
Test name
Test status
Simulation time 93810029 ps
CPU time 0.62 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:17 PM PDT 24
Peak memory 195080 kb
Host smart-7cf8dea8-ea9e-4f3a-852a-5419c84cd982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186098996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.186098996
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3361091580
Short name T1238
Test name
Test status
Simulation time 48920963 ps
CPU time 0.56 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 195012 kb
Host smart-083f5cfe-a7ef-4d21-b126-90155473b1e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361091580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3361091580
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3846339869
Short name T1193
Test name
Test status
Simulation time 13456258 ps
CPU time 0.58 seconds
Started Jul 04 04:48:14 PM PDT 24
Finished Jul 04 04:48:15 PM PDT 24
Peak memory 195096 kb
Host smart-557d71f7-7650-46ff-8377-790b60956923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846339869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3846339869
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.137110626
Short name T1226
Test name
Test status
Simulation time 12750061 ps
CPU time 0.58 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:16 PM PDT 24
Peak memory 195028 kb
Host smart-e825da30-10d7-4b71-82b6-2b6116264e03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137110626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.137110626
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3536114948
Short name T1207
Test name
Test status
Simulation time 47907325 ps
CPU time 0.55 seconds
Started Jul 04 04:48:18 PM PDT 24
Finished Jul 04 04:48:19 PM PDT 24
Peak memory 195084 kb
Host smart-286dd3f5-be65-41df-aa8c-b728677b5549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536114948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3536114948
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.549901430
Short name T1195
Test name
Test status
Simulation time 18736777 ps
CPU time 0.59 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:14 PM PDT 24
Peak memory 195064 kb
Host smart-28b8b43a-358e-4347-8248-ccf0995df540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549901430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.549901430
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.239705730
Short name T1279
Test name
Test status
Simulation time 27608198 ps
CPU time 0.76 seconds
Started Jul 04 04:48:00 PM PDT 24
Finished Jul 04 04:48:01 PM PDT 24
Peak memory 196788 kb
Host smart-53f717e9-5692-46ec-9a25-7eab3a0f1390
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239705730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.239705730
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.820532739
Short name T1190
Test name
Test status
Simulation time 1027712556 ps
CPU time 2.74 seconds
Started Jul 04 04:48:04 PM PDT 24
Finished Jul 04 04:48:07 PM PDT 24
Peak memory 198304 kb
Host smart-1c2f1c28-80ab-4343-87a1-6d40b2a01984
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820532739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.820532739
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.528986004
Short name T1216
Test name
Test status
Simulation time 118411356 ps
CPU time 0.64 seconds
Started Jul 04 04:47:47 PM PDT 24
Finished Jul 04 04:47:48 PM PDT 24
Peak memory 196064 kb
Host smart-2176cf96-9cb1-4607-aa10-cf815306f9d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528986004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.528986004
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.475759972
Short name T1183
Test name
Test status
Simulation time 26510220 ps
CPU time 1.05 seconds
Started Jul 04 04:47:46 PM PDT 24
Finished Jul 04 04:47:47 PM PDT 24
Peak memory 201064 kb
Host smart-4fc338a3-7ef7-4bf0-823d-b89e88318eeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475759972 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.475759972
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1017164176
Short name T1253
Test name
Test status
Simulation time 19113533 ps
CPU time 0.64 seconds
Started Jul 04 04:48:01 PM PDT 24
Finished Jul 04 04:48:02 PM PDT 24
Peak memory 196184 kb
Host smart-a898c52e-2ee4-40ff-9121-749f8219c3ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017164176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1017164176
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1211392307
Short name T1241
Test name
Test status
Simulation time 12670122 ps
CPU time 0.55 seconds
Started Jul 04 04:48:03 PM PDT 24
Finished Jul 04 04:48:04 PM PDT 24
Peak memory 195000 kb
Host smart-a92335a0-e2be-42e7-b989-adb505570bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211392307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1211392307
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2825268684
Short name T69
Test name
Test status
Simulation time 220644562 ps
CPU time 0.72 seconds
Started Jul 04 04:48:01 PM PDT 24
Finished Jul 04 04:48:02 PM PDT 24
Peak memory 197620 kb
Host smart-057da28f-5dbe-4166-adaf-ac5b393555e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825268684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2825268684
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3474107489
Short name T1191
Test name
Test status
Simulation time 95976510 ps
CPU time 1.02 seconds
Started Jul 04 04:47:58 PM PDT 24
Finished Jul 04 04:47:59 PM PDT 24
Peak memory 200620 kb
Host smart-b671c07a-8982-4fee-a5cd-c247c8d92bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474107489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3474107489
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2372389695
Short name T1276
Test name
Test status
Simulation time 287573541 ps
CPU time 1.35 seconds
Started Jul 04 04:47:58 PM PDT 24
Finished Jul 04 04:48:00 PM PDT 24
Peak memory 200056 kb
Host smart-cb64500a-f32d-490f-b2b5-475372cf623a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372389695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2372389695
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3345693602
Short name T1199
Test name
Test status
Simulation time 16391434 ps
CPU time 0.56 seconds
Started Jul 04 04:48:19 PM PDT 24
Finished Jul 04 04:48:19 PM PDT 24
Peak memory 194996 kb
Host smart-5dd5d241-33bd-4505-b679-04cfb6492d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345693602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3345693602
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2001001620
Short name T1178
Test name
Test status
Simulation time 13785941 ps
CPU time 0.56 seconds
Started Jul 04 04:48:03 PM PDT 24
Finished Jul 04 04:48:03 PM PDT 24
Peak memory 194992 kb
Host smart-d15493fa-8c9b-450f-aebd-0c744c1e5d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001001620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2001001620
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1149363498
Short name T1258
Test name
Test status
Simulation time 26082234 ps
CPU time 0.6 seconds
Started Jul 04 04:48:02 PM PDT 24
Finished Jul 04 04:48:03 PM PDT 24
Peak memory 195064 kb
Host smart-57cde95e-7c53-4c31-a1ae-4213d7544aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149363498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1149363498
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2924593923
Short name T1229
Test name
Test status
Simulation time 24373380 ps
CPU time 0.58 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 195080 kb
Host smart-de9e65bc-0762-4e66-8db1-aed3d2f05841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924593923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2924593923
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.454852864
Short name T1242
Test name
Test status
Simulation time 31676141 ps
CPU time 0.56 seconds
Started Jul 04 04:48:06 PM PDT 24
Finished Jul 04 04:48:06 PM PDT 24
Peak memory 195060 kb
Host smart-8477370e-7591-4499-9404-2ac032844a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454852864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.454852864
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3120870212
Short name T1185
Test name
Test status
Simulation time 24850836 ps
CPU time 0.59 seconds
Started Jul 04 04:48:14 PM PDT 24
Finished Jul 04 04:48:15 PM PDT 24
Peak memory 195100 kb
Host smart-6ded016b-71b6-40f0-816c-1bacd677145f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120870212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3120870212
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3534493793
Short name T1307
Test name
Test status
Simulation time 13790690 ps
CPU time 0.54 seconds
Started Jul 04 04:48:10 PM PDT 24
Finished Jul 04 04:48:10 PM PDT 24
Peak memory 194964 kb
Host smart-b86c92a6-e335-4a0e-abb5-2bc9fbfd19b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534493793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3534493793
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.680614959
Short name T1204
Test name
Test status
Simulation time 13916854 ps
CPU time 0.57 seconds
Started Jul 04 04:48:08 PM PDT 24
Finished Jul 04 04:48:09 PM PDT 24
Peak memory 194932 kb
Host smart-4b7de8af-c7b2-42c3-8826-3cbdf7a9f442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680614959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.680614959
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.909440884
Short name T1176
Test name
Test status
Simulation time 55286801 ps
CPU time 0.57 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:12 PM PDT 24
Peak memory 195064 kb
Host smart-b3023d7c-85df-45e0-82d1-787c26debf5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909440884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.909440884
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2075172570
Short name T1184
Test name
Test status
Simulation time 20914555 ps
CPU time 0.52 seconds
Started Jul 04 04:48:08 PM PDT 24
Finished Jul 04 04:48:09 PM PDT 24
Peak memory 194948 kb
Host smart-a0a3653f-9602-4c11-b6e8-ab5fa7cea99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075172570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2075172570
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3789994183
Short name T1264
Test name
Test status
Simulation time 29890811 ps
CPU time 0.65 seconds
Started Jul 04 04:47:59 PM PDT 24
Finished Jul 04 04:48:00 PM PDT 24
Peak memory 198224 kb
Host smart-c64af029-3e53-4d79-81fb-a374fdb852bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789994183 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3789994183
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.4132294617
Short name T68
Test name
Test status
Simulation time 71336928 ps
CPU time 0.58 seconds
Started Jul 04 04:48:01 PM PDT 24
Finished Jul 04 04:48:02 PM PDT 24
Peak memory 196456 kb
Host smart-13bbecfa-414a-4891-b07e-2b9398ad30ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132294617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.4132294617
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1862630548
Short name T1254
Test name
Test status
Simulation time 42416313 ps
CPU time 0.59 seconds
Started Jul 04 04:47:54 PM PDT 24
Finished Jul 04 04:47:54 PM PDT 24
Peak memory 195028 kb
Host smart-5d562180-78a7-4f27-88d2-0b0f169fb5f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862630548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1862630548
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2625587216
Short name T70
Test name
Test status
Simulation time 18303218 ps
CPU time 0.63 seconds
Started Jul 04 04:47:52 PM PDT 24
Finished Jul 04 04:47:53 PM PDT 24
Peak memory 196396 kb
Host smart-9da72cfb-d3ae-4cc0-ba75-8a0a432bd09d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625587216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2625587216
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1400760491
Short name T1269
Test name
Test status
Simulation time 264607776 ps
CPU time 1.54 seconds
Started Jul 04 04:48:06 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 200668 kb
Host smart-ec6ceff8-3a24-4f55-ac0f-37ff389ffb3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400760491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1400760491
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2574343977
Short name T1314
Test name
Test status
Simulation time 40793192 ps
CPU time 0.98 seconds
Started Jul 04 04:48:06 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 199788 kb
Host smart-2d12ac4c-f82e-4470-99d1-3b501bd28a41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574343977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2574343977
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3418058779
Short name T1212
Test name
Test status
Simulation time 63667241 ps
CPU time 0.7 seconds
Started Jul 04 04:48:00 PM PDT 24
Finished Jul 04 04:48:01 PM PDT 24
Peak memory 198504 kb
Host smart-c3c7ffad-e307-4b1a-8add-9a4c9333619d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418058779 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3418058779
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1203699748
Short name T1251
Test name
Test status
Simulation time 47706005 ps
CPU time 0.62 seconds
Started Jul 04 04:47:57 PM PDT 24
Finished Jul 04 04:47:58 PM PDT 24
Peak memory 196084 kb
Host smart-c7a8490c-fb04-4c05-9647-e85bf034999f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203699748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1203699748
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.926299841
Short name T1283
Test name
Test status
Simulation time 31600735 ps
CPU time 0.58 seconds
Started Jul 04 04:48:09 PM PDT 24
Finished Jul 04 04:48:09 PM PDT 24
Peak memory 195024 kb
Host smart-56c3ed6c-914a-42e5-bc58-24c528caeaf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926299841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.926299841
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.111383099
Short name T1249
Test name
Test status
Simulation time 100964826 ps
CPU time 0.74 seconds
Started Jul 04 04:47:48 PM PDT 24
Finished Jul 04 04:47:49 PM PDT 24
Peak memory 197456 kb
Host smart-4fd43c5b-b8a4-458c-9a16-fb2ab5fb1878
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111383099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.111383099
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1300147644
Short name T1263
Test name
Test status
Simulation time 67920017 ps
CPU time 1.03 seconds
Started Jul 04 04:47:57 PM PDT 24
Finished Jul 04 04:47:58 PM PDT 24
Peak memory 200436 kb
Host smart-eac26407-9128-4602-9588-ac12bb58b420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300147644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1300147644
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3493853481
Short name T1240
Test name
Test status
Simulation time 66275319 ps
CPU time 1.29 seconds
Started Jul 04 04:47:49 PM PDT 24
Finished Jul 04 04:47:51 PM PDT 24
Peak memory 199920 kb
Host smart-b3f8d8be-fc66-46fe-a50c-f0d8af8e27a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493853481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3493853481
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.531231829
Short name T1233
Test name
Test status
Simulation time 28291168 ps
CPU time 0.8 seconds
Started Jul 04 04:47:51 PM PDT 24
Finished Jul 04 04:47:52 PM PDT 24
Peak memory 200436 kb
Host smart-5b813c5a-4134-45a3-b864-f64a1f8d902b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531231829 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.531231829
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1127068292
Short name T1230
Test name
Test status
Simulation time 21345960 ps
CPU time 0.56 seconds
Started Jul 04 04:48:07 PM PDT 24
Finished Jul 04 04:48:08 PM PDT 24
Peak memory 196044 kb
Host smart-096fb2a8-eb71-4690-9c81-cffd7fbe7eef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127068292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1127068292
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2261611609
Short name T1227
Test name
Test status
Simulation time 11822373 ps
CPU time 0.57 seconds
Started Jul 04 04:47:55 PM PDT 24
Finished Jul 04 04:47:56 PM PDT 24
Peak memory 195016 kb
Host smart-c7cbc752-4e55-48db-9cf2-8020976e10ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261611609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2261611609
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2879383378
Short name T1257
Test name
Test status
Simulation time 32536908 ps
CPU time 0.77 seconds
Started Jul 04 04:47:57 PM PDT 24
Finished Jul 04 04:47:58 PM PDT 24
Peak memory 196656 kb
Host smart-0ea1b3d7-c5e9-4bf3-b2cd-a7abc7efa9bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879383378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2879383378
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3878988784
Short name T1298
Test name
Test status
Simulation time 69722022 ps
CPU time 1.37 seconds
Started Jul 04 04:47:51 PM PDT 24
Finished Jul 04 04:47:52 PM PDT 24
Peak memory 200680 kb
Host smart-c09de2e3-c2f8-441f-bcd0-949a74e28ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878988784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3878988784
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2194499104
Short name T1220
Test name
Test status
Simulation time 136228540 ps
CPU time 0.98 seconds
Started Jul 04 04:48:11 PM PDT 24
Finished Jul 04 04:48:13 PM PDT 24
Peak memory 199372 kb
Host smart-6d87eb48-7fe2-4260-bb1c-1c02b2105b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194499104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2194499104
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1480393087
Short name T1274
Test name
Test status
Simulation time 28176617 ps
CPU time 1.42 seconds
Started Jul 04 04:48:04 PM PDT 24
Finished Jul 04 04:48:06 PM PDT 24
Peak memory 200760 kb
Host smart-926a3e2d-8546-4055-b152-83265811acbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480393087 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1480393087
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.578056378
Short name T65
Test name
Test status
Simulation time 15513016 ps
CPU time 0.62 seconds
Started Jul 04 04:47:57 PM PDT 24
Finished Jul 04 04:47:58 PM PDT 24
Peak memory 196096 kb
Host smart-f1f7d6b2-8322-4903-9801-067360af43fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578056378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.578056378
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3469894256
Short name T1243
Test name
Test status
Simulation time 48861109 ps
CPU time 0.58 seconds
Started Jul 04 04:48:02 PM PDT 24
Finished Jul 04 04:48:03 PM PDT 24
Peak memory 195072 kb
Host smart-a1d69db7-4bc4-40eb-96e7-952fc84e6962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469894256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3469894256
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2376429627
Short name T1219
Test name
Test status
Simulation time 241685589 ps
CPU time 0.65 seconds
Started Jul 04 04:48:06 PM PDT 24
Finished Jul 04 04:48:07 PM PDT 24
Peak memory 196236 kb
Host smart-65ef3de9-08b0-40f5-85a1-a73d87c9a888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376429627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2376429627
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.34359456
Short name T1194
Test name
Test status
Simulation time 103975697 ps
CPU time 2.21 seconds
Started Jul 04 04:47:46 PM PDT 24
Finished Jul 04 04:47:48 PM PDT 24
Peak memory 200684 kb
Host smart-0646d2e9-59ea-4f53-805b-9f733bfb55eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34359456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.34359456
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1409701566
Short name T1291
Test name
Test status
Simulation time 163923852 ps
CPU time 1.33 seconds
Started Jul 04 04:47:47 PM PDT 24
Finished Jul 04 04:47:49 PM PDT 24
Peak memory 199936 kb
Host smart-f0baa263-2839-4698-95a3-420dd69f0258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409701566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1409701566
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.198171453
Short name T1297
Test name
Test status
Simulation time 65715813 ps
CPU time 0.93 seconds
Started Jul 04 04:48:03 PM PDT 24
Finished Jul 04 04:48:04 PM PDT 24
Peak memory 200496 kb
Host smart-d05cb186-a009-4174-9446-0dc4c0cd2f2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198171453 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.198171453
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2248361965
Short name T1232
Test name
Test status
Simulation time 138227517 ps
CPU time 0.57 seconds
Started Jul 04 04:47:55 PM PDT 24
Finished Jul 04 04:47:56 PM PDT 24
Peak memory 196012 kb
Host smart-294cf766-0141-4399-b27b-87ef0945604a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248361965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2248361965
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1581237747
Short name T1187
Test name
Test status
Simulation time 15372457 ps
CPU time 0.61 seconds
Started Jul 04 04:48:01 PM PDT 24
Finished Jul 04 04:48:02 PM PDT 24
Peak memory 194992 kb
Host smart-f4b5487d-5c78-4db6-bb6b-57adb9e11f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581237747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1581237747
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2568095038
Short name T1290
Test name
Test status
Simulation time 77090960 ps
CPU time 0.66 seconds
Started Jul 04 04:48:02 PM PDT 24
Finished Jul 04 04:48:03 PM PDT 24
Peak memory 196244 kb
Host smart-bfd0238d-badc-457a-bd2c-4d6b71a06f7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568095038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2568095038
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2725052625
Short name T1266
Test name
Test status
Simulation time 72965183 ps
CPU time 1.51 seconds
Started Jul 04 04:48:02 PM PDT 24
Finished Jul 04 04:48:04 PM PDT 24
Peak memory 200644 kb
Host smart-bd1e8436-54eb-4029-908e-5067407c1e38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725052625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2725052625
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3086776832
Short name T75
Test name
Test status
Simulation time 55293192 ps
CPU time 0.93 seconds
Started Jul 04 04:47:59 PM PDT 24
Finished Jul 04 04:48:01 PM PDT 24
Peak memory 199356 kb
Host smart-04696f44-87a4-414b-9e58-893a05241771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086776832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3086776832
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.94221182
Short name T954
Test name
Test status
Simulation time 13397045 ps
CPU time 0.59 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:38:14 PM PDT 24
Peak memory 194752 kb
Host smart-ec85444e-a132-49be-8dd4-9f3ae3acfd4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94221182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.94221182
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3905886429
Short name T733
Test name
Test status
Simulation time 67025110442 ps
CPU time 29.12 seconds
Started Jul 04 05:38:11 PM PDT 24
Finished Jul 04 05:38:40 PM PDT 24
Peak memory 199996 kb
Host smart-d78a62bd-8dcb-4c6d-b7aa-a828378e0995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905886429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3905886429
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2495732478
Short name T425
Test name
Test status
Simulation time 39976444806 ps
CPU time 29.3 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:38:43 PM PDT 24
Peak memory 200008 kb
Host smart-aa061d83-1248-44fe-a43f-83618f08b5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495732478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2495732478
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.4193731051
Short name T989
Test name
Test status
Simulation time 22700976060 ps
CPU time 16.85 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:38:30 PM PDT 24
Peak memory 199980 kb
Host smart-eb1a38bd-f4ac-4f75-b2a4-81c6ffdd5b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193731051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4193731051
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.322659296
Short name T376
Test name
Test status
Simulation time 55955684561 ps
CPU time 25.35 seconds
Started Jul 04 05:38:11 PM PDT 24
Finished Jul 04 05:38:37 PM PDT 24
Peak memory 198060 kb
Host smart-128dc350-2ec2-431d-b20a-8dbf560a6295
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322659296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.322659296
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2942413435
Short name T601
Test name
Test status
Simulation time 125145134756 ps
CPU time 255.4 seconds
Started Jul 04 05:38:14 PM PDT 24
Finished Jul 04 05:42:30 PM PDT 24
Peak memory 199932 kb
Host smart-a9188579-f445-465a-9d60-ff821d189451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942413435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2942413435
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.142542559
Short name T472
Test name
Test status
Simulation time 555726438 ps
CPU time 1.54 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:38:15 PM PDT 24
Peak memory 195904 kb
Host smart-bbf75eb9-3a1d-4885-a20b-8cafb925c6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142542559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.142542559
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1249105091
Short name T666
Test name
Test status
Simulation time 102988276762 ps
CPU time 171.51 seconds
Started Jul 04 05:38:11 PM PDT 24
Finished Jul 04 05:41:03 PM PDT 24
Peak memory 200120 kb
Host smart-5f60853b-5b37-42be-9324-7e504f1fcbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249105091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1249105091
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2268165437
Short name T1020
Test name
Test status
Simulation time 11976928869 ps
CPU time 139.79 seconds
Started Jul 04 05:38:17 PM PDT 24
Finished Jul 04 05:40:37 PM PDT 24
Peak memory 199936 kb
Host smart-bd6808f7-c723-42f1-9817-3bac487163ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2268165437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2268165437
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.343833043
Short name T457
Test name
Test status
Simulation time 3774495557 ps
CPU time 31.34 seconds
Started Jul 04 05:38:18 PM PDT 24
Finished Jul 04 05:38:49 PM PDT 24
Peak memory 199036 kb
Host smart-fe2f3b32-fa46-44a8-8020-8b0e970ec27e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343833043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.343833043
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3450611282
Short name T629
Test name
Test status
Simulation time 32735820921 ps
CPU time 67.84 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:39:21 PM PDT 24
Peak memory 200000 kb
Host smart-1c1c6bf3-aea8-4386-b983-03d034e8e7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450611282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3450611282
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1760858211
Short name T1004
Test name
Test status
Simulation time 2972708113 ps
CPU time 4.49 seconds
Started Jul 04 05:38:18 PM PDT 24
Finished Jul 04 05:38:23 PM PDT 24
Peak memory 195816 kb
Host smart-9f7ac1cb-e0e2-4302-866b-cfbe2653ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760858211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1760858211
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3748226549
Short name T78
Test name
Test status
Simulation time 227928274 ps
CPU time 0.84 seconds
Started Jul 04 05:38:14 PM PDT 24
Finished Jul 04 05:38:15 PM PDT 24
Peak memory 218280 kb
Host smart-c7adc2df-29dd-47a3-921b-96b86399c3fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748226549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3748226549
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.996097352
Short name T1144
Test name
Test status
Simulation time 292023715 ps
CPU time 1.26 seconds
Started Jul 04 05:38:12 PM PDT 24
Finished Jul 04 05:38:13 PM PDT 24
Peak memory 199412 kb
Host smart-482c4492-b386-48a9-bf9e-f83c908c3be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996097352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.996097352
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.4222885568
Short name T11
Test name
Test status
Simulation time 69790380299 ps
CPU time 230.15 seconds
Started Jul 04 05:38:14 PM PDT 24
Finished Jul 04 05:42:04 PM PDT 24
Peak memory 199972 kb
Host smart-b8596ee5-d5b0-4a6a-b278-5ec5f182b1d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222885568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.4222885568
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1906389135
Short name T304
Test name
Test status
Simulation time 13601531838 ps
CPU time 143.63 seconds
Started Jul 04 05:38:15 PM PDT 24
Finished Jul 04 05:40:39 PM PDT 24
Peak memory 216704 kb
Host smart-f5130cb0-67e7-42d3-97bc-2d4e49a5e9b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906389135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1906389135
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.435619694
Short name T1069
Test name
Test status
Simulation time 1302166366 ps
CPU time 1.86 seconds
Started Jul 04 05:38:15 PM PDT 24
Finished Jul 04 05:38:17 PM PDT 24
Peak memory 198492 kb
Host smart-9521ade5-0274-4ffe-a05a-de51d6f54b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435619694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.435619694
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2071760226
Short name T373
Test name
Test status
Simulation time 34939177499 ps
CPU time 14.11 seconds
Started Jul 04 05:38:19 PM PDT 24
Finished Jul 04 05:38:34 PM PDT 24
Peak memory 199920 kb
Host smart-6645539e-e438-469a-a1bc-d1782e8beb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071760226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2071760226
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1328482875
Short name T361
Test name
Test status
Simulation time 37191705 ps
CPU time 0.58 seconds
Started Jul 04 05:38:11 PM PDT 24
Finished Jul 04 05:38:12 PM PDT 24
Peak memory 194976 kb
Host smart-0a2df37d-ca9d-49f8-8aea-3dd09758de12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328482875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1328482875
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3862501515
Short name T805
Test name
Test status
Simulation time 151063290171 ps
CPU time 213.69 seconds
Started Jul 04 05:38:14 PM PDT 24
Finished Jul 04 05:41:48 PM PDT 24
Peak memory 199932 kb
Host smart-63561be4-03a6-4f3c-8d66-70d3bf824756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862501515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3862501515
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.4230076959
Short name T979
Test name
Test status
Simulation time 26152553768 ps
CPU time 4.25 seconds
Started Jul 04 05:38:14 PM PDT 24
Finished Jul 04 05:38:18 PM PDT 24
Peak memory 198240 kb
Host smart-5bb0e5b8-00a1-4166-84e0-50cabdc7763e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230076959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4230076959
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.1448213298
Short name T414
Test name
Test status
Simulation time 37367114509 ps
CPU time 55.45 seconds
Started Jul 04 05:38:17 PM PDT 24
Finished Jul 04 05:39:13 PM PDT 24
Peak memory 199888 kb
Host smart-a450c7c1-a398-47dc-b308-6d45d893fff4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448213298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1448213298
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2190457909
Short name T359
Test name
Test status
Simulation time 98337139287 ps
CPU time 230.61 seconds
Started Jul 04 05:38:15 PM PDT 24
Finished Jul 04 05:42:06 PM PDT 24
Peak memory 199980 kb
Host smart-17eabca4-f916-49fa-83d8-5f4f38de284b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190457909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2190457909
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1383716322
Short name T898
Test name
Test status
Simulation time 6019276947 ps
CPU time 7.41 seconds
Started Jul 04 05:38:14 PM PDT 24
Finished Jul 04 05:38:22 PM PDT 24
Peak memory 199932 kb
Host smart-53ce837d-146a-424d-8344-358c075bb600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383716322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1383716322
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1437796032
Short name T428
Test name
Test status
Simulation time 30739812918 ps
CPU time 53.25 seconds
Started Jul 04 05:38:14 PM PDT 24
Finished Jul 04 05:39:07 PM PDT 24
Peak memory 208240 kb
Host smart-de8ee669-de11-4053-ade8-227e17e2d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437796032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1437796032
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2955138485
Short name T913
Test name
Test status
Simulation time 22516280758 ps
CPU time 303.5 seconds
Started Jul 04 05:38:15 PM PDT 24
Finished Jul 04 05:43:19 PM PDT 24
Peak memory 199944 kb
Host smart-2c5af143-7317-4962-9f7d-4b58956f004a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955138485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2955138485
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.949392393
Short name T475
Test name
Test status
Simulation time 4041292996 ps
CPU time 7.89 seconds
Started Jul 04 05:38:17 PM PDT 24
Finished Jul 04 05:38:25 PM PDT 24
Peak memory 199000 kb
Host smart-54af1de2-83e9-4ffb-abe7-54c47d8e4f7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949392393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.949392393
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2108867011
Short name T875
Test name
Test status
Simulation time 31035394488 ps
CPU time 43.26 seconds
Started Jul 04 05:38:18 PM PDT 24
Finished Jul 04 05:39:01 PM PDT 24
Peak memory 199908 kb
Host smart-b887326b-57ff-4630-be4c-fe6117b2fb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108867011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2108867011
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.980404445
Short name T450
Test name
Test status
Simulation time 4700777447 ps
CPU time 7.81 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:38:21 PM PDT 24
Peak memory 196248 kb
Host smart-268d06b3-f109-4e85-a6a9-116555415edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980404445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.980404445
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.4096167987
Short name T710
Test name
Test status
Simulation time 5533731936 ps
CPU time 15.52 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:38:29 PM PDT 24
Peak memory 199208 kb
Host smart-268f340a-8de0-4758-81ec-fbb0130c0cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096167987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4096167987
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2580913682
Short name T395
Test name
Test status
Simulation time 8083456568 ps
CPU time 14.82 seconds
Started Jul 04 05:38:17 PM PDT 24
Finished Jul 04 05:38:32 PM PDT 24
Peak memory 199472 kb
Host smart-2da96f50-a136-45f9-902e-585c63cc7612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580913682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2580913682
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2808292052
Short name T882
Test name
Test status
Simulation time 25711408706 ps
CPU time 14.31 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:38:27 PM PDT 24
Peak memory 199696 kb
Host smart-57407e20-6eb1-4fa5-9c68-e03364fef5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808292052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2808292052
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.738797543
Short name T1107
Test name
Test status
Simulation time 21317102 ps
CPU time 0.57 seconds
Started Jul 04 05:38:42 PM PDT 24
Finished Jul 04 05:38:43 PM PDT 24
Peak memory 195580 kb
Host smart-56011471-0065-4b8b-aaa2-e08086b8c941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738797543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.738797543
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2316075066
Short name T499
Test name
Test status
Simulation time 331182269031 ps
CPU time 98.78 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:40:14 PM PDT 24
Peak memory 199972 kb
Host smart-641ab196-f7d8-41bb-99df-9081b4c808f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316075066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2316075066
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3724957594
Short name T565
Test name
Test status
Simulation time 52898474292 ps
CPU time 17.02 seconds
Started Jul 04 05:38:38 PM PDT 24
Finished Jul 04 05:38:56 PM PDT 24
Peak memory 199896 kb
Host smart-566e081b-4c32-4f81-b1c5-6cb0863fd4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724957594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3724957594
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2485889542
Short name T81
Test name
Test status
Simulation time 29489089433 ps
CPU time 51.12 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:39:33 PM PDT 24
Peak memory 199868 kb
Host smart-56430ca7-a26f-4e16-a165-f4f1f76409eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485889542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2485889542
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1828459339
Short name T834
Test name
Test status
Simulation time 67499771022 ps
CPU time 31.3 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:39:07 PM PDT 24
Peak memory 199868 kb
Host smart-faaac209-6c76-41da-88be-963cae77409a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828459339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1828459339
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.4045861747
Short name T697
Test name
Test status
Simulation time 117818365358 ps
CPU time 169.84 seconds
Started Jul 04 05:38:38 PM PDT 24
Finished Jul 04 05:41:28 PM PDT 24
Peak memory 199952 kb
Host smart-136a5097-4ed1-4a38-9b06-c5e32d7e0de7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045861747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4045861747
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3405722098
Short name T763
Test name
Test status
Simulation time 95453768 ps
CPU time 0.87 seconds
Started Jul 04 05:38:40 PM PDT 24
Finished Jul 04 05:38:41 PM PDT 24
Peak memory 196916 kb
Host smart-cf92f104-666a-4983-8ed5-634f6552d147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405722098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3405722098
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.274497312
Short name T296
Test name
Test status
Simulation time 8586586804 ps
CPU time 431.06 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:45:59 PM PDT 24
Peak memory 199880 kb
Host smart-2eb7905d-05ec-4374-aa0d-6eac70ec7c80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=274497312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.274497312
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2655225464
Short name T341
Test name
Test status
Simulation time 7454816818 ps
CPU time 6.32 seconds
Started Jul 04 05:38:39 PM PDT 24
Finished Jul 04 05:38:45 PM PDT 24
Peak memory 198272 kb
Host smart-bcb9a6b1-2834-473d-aa82-c09eb71d6262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2655225464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2655225464
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2167276034
Short name T255
Test name
Test status
Simulation time 23984514501 ps
CPU time 40.04 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:39:21 PM PDT 24
Peak memory 199980 kb
Host smart-438738ef-70db-47f1-a0a3-72c4b2fb09df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167276034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2167276034
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3068501
Short name T854
Test name
Test status
Simulation time 3062870659 ps
CPU time 5.41 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:38:40 PM PDT 24
Peak memory 196804 kb
Host smart-87c0aab1-2cc3-4071-bf67-536ea04063d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3068501
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.503050650
Short name T631
Test name
Test status
Simulation time 109271567 ps
CPU time 1.02 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:38:42 PM PDT 24
Peak memory 198664 kb
Host smart-97d7f70b-fa83-44dd-858d-abdbcb04bbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503050650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.503050650
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3642727758
Short name T1146
Test name
Test status
Simulation time 273919499748 ps
CPU time 460.49 seconds
Started Jul 04 05:38:42 PM PDT 24
Finished Jul 04 05:46:22 PM PDT 24
Peak memory 199916 kb
Host smart-4b742ad7-142b-4004-bd0c-e28fdb53c15c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642727758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3642727758
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2312017765
Short name T667
Test name
Test status
Simulation time 76494026882 ps
CPU time 290.73 seconds
Started Jul 04 05:38:42 PM PDT 24
Finished Jul 04 05:43:33 PM PDT 24
Peak memory 216476 kb
Host smart-9645ee81-c3fd-4fdf-b39b-4c62152c860a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312017765 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2312017765
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1467951066
Short name T1163
Test name
Test status
Simulation time 1469953759 ps
CPU time 2.38 seconds
Started Jul 04 05:38:42 PM PDT 24
Finished Jul 04 05:38:44 PM PDT 24
Peak memory 199880 kb
Host smart-b89af6c0-43c6-4ee3-8b19-b2b5dbb6f88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467951066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1467951066
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.4084659456
Short name T237
Test name
Test status
Simulation time 10648140923 ps
CPU time 19.44 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:38:55 PM PDT 24
Peak memory 199760 kb
Host smart-8e57d265-5c78-4b5e-8e08-6304468c37b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084659456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.4084659456
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3288807417
Short name T885
Test name
Test status
Simulation time 101763252249 ps
CPU time 145.36 seconds
Started Jul 04 05:42:35 PM PDT 24
Finished Jul 04 05:45:00 PM PDT 24
Peak memory 199904 kb
Host smart-e47f99d4-3631-4f69-bff7-b1e5ffbe64b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288807417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3288807417
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.377487850
Short name T520
Test name
Test status
Simulation time 17720475661 ps
CPU time 38.17 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:43:15 PM PDT 24
Peak memory 199920 kb
Host smart-959267b1-73fa-4fa3-a8fa-a16df62c4ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377487850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.377487850
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3508735884
Short name T454
Test name
Test status
Simulation time 36826784419 ps
CPU time 55.41 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:43:32 PM PDT 24
Peak memory 199912 kb
Host smart-0c799f2a-bb8b-4d2f-8407-a6b5e0634652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508735884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3508735884
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.4282955910
Short name T214
Test name
Test status
Simulation time 119527192855 ps
CPU time 170.31 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:45:26 PM PDT 24
Peak memory 199912 kb
Host smart-94679400-43e8-410d-a3bd-906f05f94ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282955910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.4282955910
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2762669824
Short name T398
Test name
Test status
Simulation time 43372278519 ps
CPU time 83.45 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:44:01 PM PDT 24
Peak memory 199924 kb
Host smart-dcbb2568-c338-4120-ac82-8d1b54d21518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762669824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2762669824
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1115495861
Short name T618
Test name
Test status
Simulation time 34974828569 ps
CPU time 62.61 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:43:39 PM PDT 24
Peak memory 199980 kb
Host smart-5263b408-0963-48a6-879a-9810a2a52eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115495861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1115495861
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.588424677
Short name T848
Test name
Test status
Simulation time 71225112424 ps
CPU time 23.52 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:43:01 PM PDT 24
Peak memory 200004 kb
Host smart-2ffbceee-1768-4124-930f-d91fd38f3302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588424677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.588424677
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3801988021
Short name T513
Test name
Test status
Simulation time 56691574827 ps
CPU time 30.74 seconds
Started Jul 04 05:42:35 PM PDT 24
Finished Jul 04 05:43:06 PM PDT 24
Peak memory 199928 kb
Host smart-7cb448c3-2efa-4da5-ac98-9e2ad5c548f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801988021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3801988021
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.4201807687
Short name T1001
Test name
Test status
Simulation time 138598766298 ps
CPU time 107.41 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:44:25 PM PDT 24
Peak memory 200020 kb
Host smart-c19d6b70-d9d2-462c-8092-68c4eaade7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201807687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4201807687
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2533042232
Short name T374
Test name
Test status
Simulation time 22420195 ps
CPU time 0.55 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:38:42 PM PDT 24
Peak memory 195264 kb
Host smart-93160557-3818-4da4-bf94-4fd63e3a7dd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533042232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2533042232
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2903449180
Short name T992
Test name
Test status
Simulation time 99101329275 ps
CPU time 120.33 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:40:48 PM PDT 24
Peak memory 199988 kb
Host smart-6f237917-5b4d-4b7e-be74-6af9b5b8bf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903449180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2903449180
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3306709888
Short name T157
Test name
Test status
Simulation time 82385194066 ps
CPU time 30.58 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:39:12 PM PDT 24
Peak memory 199500 kb
Host smart-0531d437-0cd3-4251-a004-acb0eec8f97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306709888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3306709888
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1961941237
Short name T826
Test name
Test status
Simulation time 15603879755 ps
CPU time 11.9 seconds
Started Jul 04 05:38:38 PM PDT 24
Finished Jul 04 05:38:51 PM PDT 24
Peak memory 199628 kb
Host smart-082d4320-c319-45dd-8523-90778b51bf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961941237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1961941237
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3276872191
Short name T1016
Test name
Test status
Simulation time 59990672717 ps
CPU time 8.59 seconds
Started Jul 04 05:38:40 PM PDT 24
Finished Jul 04 05:38:49 PM PDT 24
Peak memory 199932 kb
Host smart-2c08a483-2f1c-43e9-b344-062341bdd341
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276872191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3276872191
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1855204634
Short name T798
Test name
Test status
Simulation time 171099710425 ps
CPU time 230.95 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:42:32 PM PDT 24
Peak memory 199916 kb
Host smart-9fe39242-5c9a-47ea-8ee9-eba5c4897f87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855204634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1855204634
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2233557748
Short name T1028
Test name
Test status
Simulation time 1350225729 ps
CPU time 1.05 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:38:49 PM PDT 24
Peak memory 195420 kb
Host smart-2a5cbdeb-8b89-4307-bb0b-d72f4ecb8975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233557748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2233557748
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2908163919
Short name T493
Test name
Test status
Simulation time 78854390782 ps
CPU time 69.07 seconds
Started Jul 04 05:38:43 PM PDT 24
Finished Jul 04 05:39:52 PM PDT 24
Peak memory 200048 kb
Host smart-68bf2239-e8bb-42ea-8369-e0dc9b552084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908163919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2908163919
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3664496180
Short name T712
Test name
Test status
Simulation time 24961243766 ps
CPU time 733.08 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:50:54 PM PDT 24
Peak memory 200008 kb
Host smart-bfa0ad88-8140-44f3-8be4-621bc2942df6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3664496180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3664496180
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1034552192
Short name T920
Test name
Test status
Simulation time 7454073166 ps
CPU time 29.86 seconds
Started Jul 04 05:38:40 PM PDT 24
Finished Jul 04 05:39:11 PM PDT 24
Peak memory 199296 kb
Host smart-7fcce6e6-1a22-4ebc-af39-fb21c218da9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034552192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1034552192
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1888984469
Short name T993
Test name
Test status
Simulation time 68380697906 ps
CPU time 8.22 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:38:49 PM PDT 24
Peak memory 199860 kb
Host smart-47240249-9512-446d-8774-28c1be015b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888984469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1888984469
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.879300958
Short name T444
Test name
Test status
Simulation time 706622430 ps
CPU time 0.96 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:38:49 PM PDT 24
Peak memory 195412 kb
Host smart-5aea604b-8564-4af3-bdc3-222d2d80abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879300958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.879300958
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.295998387
Short name T33
Test name
Test status
Simulation time 1002017030 ps
CPU time 1.86 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:38:43 PM PDT 24
Peak memory 198320 kb
Host smart-2d3b779c-4ad2-4d24-9567-66fdcdead716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295998387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.295998387
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.357728482
Short name T769
Test name
Test status
Simulation time 6933006932 ps
CPU time 9.2 seconds
Started Jul 04 05:38:39 PM PDT 24
Finished Jul 04 05:38:48 PM PDT 24
Peak memory 199544 kb
Host smart-3fca1f5e-6d64-4843-929e-6a8e5a25a86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357728482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.357728482
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3729908702
Short name T688
Test name
Test status
Simulation time 53676488354 ps
CPU time 22.32 seconds
Started Jul 04 05:38:40 PM PDT 24
Finished Jul 04 05:39:03 PM PDT 24
Peak memory 199912 kb
Host smart-029c04c1-6b9d-400c-b0db-436ff0b010b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729908702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3729908702
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2942620310
Short name T139
Test name
Test status
Simulation time 357773424965 ps
CPU time 45.22 seconds
Started Jul 04 05:42:39 PM PDT 24
Finished Jul 04 05:43:24 PM PDT 24
Peak memory 199884 kb
Host smart-038c8c12-4b40-4f88-a43a-70d02c1991b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942620310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2942620310
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2916283081
Short name T1031
Test name
Test status
Simulation time 13199844156 ps
CPU time 12.54 seconds
Started Jul 04 05:42:38 PM PDT 24
Finished Jul 04 05:42:51 PM PDT 24
Peak memory 199988 kb
Host smart-95cc03fa-cdb1-4b53-8bd9-3d07b37b9778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916283081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2916283081
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.4203404579
Short name T804
Test name
Test status
Simulation time 120943767604 ps
CPU time 12.54 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:42:50 PM PDT 24
Peak memory 199712 kb
Host smart-47f67d1a-3a2c-4820-83e4-2aa62314e85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203404579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.4203404579
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.4128963754
Short name T620
Test name
Test status
Simulation time 42821671843 ps
CPU time 62.33 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:43:39 PM PDT 24
Peak memory 199908 kb
Host smart-66c9f594-8fe9-4a6e-bb63-e5a49b852e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128963754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4128963754
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.161801684
Short name T1027
Test name
Test status
Simulation time 65155355709 ps
CPU time 34.36 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:43:12 PM PDT 24
Peak memory 199964 kb
Host smart-c4a5af10-c30e-45ae-b1b8-10d5cd5ef1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161801684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.161801684
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1312255347
Short name T1122
Test name
Test status
Simulation time 186002987747 ps
CPU time 46.01 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:43:24 PM PDT 24
Peak memory 199792 kb
Host smart-062b682a-b68a-4a6b-8ddc-90eb20e30e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312255347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1312255347
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3360299539
Short name T236
Test name
Test status
Simulation time 99603462237 ps
CPU time 117.15 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:44:35 PM PDT 24
Peak memory 199840 kb
Host smart-ce825c6b-60cc-4c05-adec-f292b34f7d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360299539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3360299539
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.4023666760
Short name T797
Test name
Test status
Simulation time 27107238093 ps
CPU time 45.95 seconds
Started Jul 04 05:42:38 PM PDT 24
Finished Jul 04 05:43:25 PM PDT 24
Peak memory 199996 kb
Host smart-a30f413f-5b74-4709-aa5a-ad2fe40c089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023666760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4023666760
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3449951774
Short name T309
Test name
Test status
Simulation time 24757383985 ps
CPU time 6.99 seconds
Started Jul 04 05:42:39 PM PDT 24
Finished Jul 04 05:42:47 PM PDT 24
Peak memory 199848 kb
Host smart-aa41d067-6982-48b2-ac6c-6430ffe44705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449951774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3449951774
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.432253787
Short name T1121
Test name
Test status
Simulation time 42936834 ps
CPU time 0.58 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:38:48 PM PDT 24
Peak memory 195248 kb
Host smart-1f0687dd-9140-4097-99e5-1f39706678d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432253787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.432253787
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2277263738
Short name T567
Test name
Test status
Simulation time 111177499052 ps
CPU time 185.28 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:41:47 PM PDT 24
Peak memory 199988 kb
Host smart-78ac3b3a-6049-4315-a668-2f417d1bc5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277263738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2277263738
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1328631742
Short name T546
Test name
Test status
Simulation time 12448045418 ps
CPU time 20.95 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:39:09 PM PDT 24
Peak memory 199056 kb
Host smart-ee5aba68-7d6c-4e05-8027-bb6fd2ee403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328631742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1328631742
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.4038596783
Short name T776
Test name
Test status
Simulation time 18611559582 ps
CPU time 14.96 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:39:02 PM PDT 24
Peak memory 200036 kb
Host smart-fdd31f0d-1b05-45cd-9b01-4b2582b65ed2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038596783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.4038596783
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1408721704
Short name T695
Test name
Test status
Simulation time 150133016561 ps
CPU time 166.86 seconds
Started Jul 04 05:38:52 PM PDT 24
Finished Jul 04 05:41:39 PM PDT 24
Peak memory 199856 kb
Host smart-1d59fb3f-ea62-41e7-8946-0cb95b907201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408721704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1408721704
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2541993174
Short name T327
Test name
Test status
Simulation time 1187582815 ps
CPU time 2.31 seconds
Started Jul 04 05:38:49 PM PDT 24
Finished Jul 04 05:38:51 PM PDT 24
Peak memory 195560 kb
Host smart-7ca83244-94fa-4d5d-99a0-b290812a0249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541993174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2541993174
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3460655845
Short name T483
Test name
Test status
Simulation time 40457604583 ps
CPU time 10.76 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:38:59 PM PDT 24
Peak memory 199460 kb
Host smart-7d965951-0d3b-4aef-b72e-73afcc7b7d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460655845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3460655845
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.4116719162
Short name T519
Test name
Test status
Simulation time 7457786208 ps
CPU time 88.72 seconds
Started Jul 04 05:38:49 PM PDT 24
Finished Jul 04 05:40:18 PM PDT 24
Peak memory 199904 kb
Host smart-9c31d21b-e484-486d-9c1a-7a355544f828
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116719162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.4116719162
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4256149426
Short name T331
Test name
Test status
Simulation time 5965766105 ps
CPU time 3.46 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:38:51 PM PDT 24
Peak memory 199284 kb
Host smart-91219483-10ef-4514-90c2-c10b1e3aaab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256149426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4256149426
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2872110160
Short name T269
Test name
Test status
Simulation time 88681127616 ps
CPU time 28.51 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:39:16 PM PDT 24
Peak memory 199748 kb
Host smart-8a05f0ce-c674-4bc6-8678-6819f3b70cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872110160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2872110160
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2990212405
Short name T743
Test name
Test status
Simulation time 5440837002 ps
CPU time 3 seconds
Started Jul 04 05:38:50 PM PDT 24
Finished Jul 04 05:38:53 PM PDT 24
Peak memory 196416 kb
Host smart-cdf203a7-19a6-411b-82d6-9c86ae8f0a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990212405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2990212405
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3933299837
Short name T916
Test name
Test status
Simulation time 5650626272 ps
CPU time 25.41 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:39:07 PM PDT 24
Peak memory 199664 kb
Host smart-6ec09c9e-1b9e-4f1b-b6ca-9e88e35d0c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933299837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3933299837
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2305258861
Short name T996
Test name
Test status
Simulation time 185098279627 ps
CPU time 271.45 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:43:19 PM PDT 24
Peak memory 200416 kb
Host smart-cea809cf-4ca4-414e-b65f-759d4af91c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305258861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2305258861
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2750565829
Short name T12
Test name
Test status
Simulation time 20593452524 ps
CPU time 247.92 seconds
Started Jul 04 05:38:53 PM PDT 24
Finished Jul 04 05:43:01 PM PDT 24
Peak memory 216564 kb
Host smart-80ccc615-6a52-464c-9070-866ff6424bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750565829 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2750565829
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3698380495
Short name T576
Test name
Test status
Simulation time 755370099 ps
CPU time 3.22 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:38:52 PM PDT 24
Peak memory 199812 kb
Host smart-1fc04646-3242-4a9b-be42-d55022ab9848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698380495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3698380495
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2971249438
Short name T895
Test name
Test status
Simulation time 106997016936 ps
CPU time 235.28 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:42:43 PM PDT 24
Peak memory 199916 kb
Host smart-994e4521-1a3c-4751-933c-f6b5353f0186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971249438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2971249438
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2468330573
Short name T741
Test name
Test status
Simulation time 115451466138 ps
CPU time 28.24 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:43:06 PM PDT 24
Peak memory 199876 kb
Host smart-a2bb081b-db46-4b20-b660-4ddd6f444325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468330573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2468330573
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4049666915
Short name T578
Test name
Test status
Simulation time 150836967744 ps
CPU time 208.63 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:46:06 PM PDT 24
Peak memory 199984 kb
Host smart-c4d7f7a8-246b-4f50-9fe8-2d4a65c6a4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049666915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4049666915
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2668089090
Short name T313
Test name
Test status
Simulation time 131526368231 ps
CPU time 69.17 seconds
Started Jul 04 05:42:41 PM PDT 24
Finished Jul 04 05:43:50 PM PDT 24
Peak memory 199916 kb
Host smart-81cdb22f-dc5e-479c-9b9a-fdc3bf46aeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668089090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2668089090
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3613941578
Short name T442
Test name
Test status
Simulation time 32370064986 ps
CPU time 26.76 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:43:03 PM PDT 24
Peak memory 199220 kb
Host smart-1f8b701b-97e8-4a33-888a-b65a10b10fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613941578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3613941578
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2412755634
Short name T275
Test name
Test status
Simulation time 83513036552 ps
CPU time 46.42 seconds
Started Jul 04 05:42:38 PM PDT 24
Finished Jul 04 05:43:25 PM PDT 24
Peak memory 199976 kb
Host smart-c96b359c-097d-46d5-854f-506c5db07e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412755634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2412755634
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.368819666
Short name T207
Test name
Test status
Simulation time 148145929722 ps
CPU time 60.6 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:43:37 PM PDT 24
Peak memory 199928 kb
Host smart-6c925ea1-9d16-42e9-9cbd-1a093f51cb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368819666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.368819666
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3719249451
Short name T160
Test name
Test status
Simulation time 53643462043 ps
CPU time 75.94 seconds
Started Jul 04 05:42:34 PM PDT 24
Finished Jul 04 05:43:50 PM PDT 24
Peak memory 199924 kb
Host smart-a9e0de1e-c05d-4deb-a5de-3d27dbf10d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719249451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3719249451
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.7364184
Short name T991
Test name
Test status
Simulation time 134119412947 ps
CPU time 181.27 seconds
Started Jul 04 05:42:43 PM PDT 24
Finished Jul 04 05:45:44 PM PDT 24
Peak memory 199988 kb
Host smart-ab106a6e-d412-4ede-8d75-37bd55905050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7364184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.7364184
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1469098068
Short name T440
Test name
Test status
Simulation time 16686422496 ps
CPU time 27.33 seconds
Started Jul 04 05:42:49 PM PDT 24
Finished Jul 04 05:43:16 PM PDT 24
Peak memory 199960 kb
Host smart-e9cec140-174d-484b-81e8-9600b3c8dac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469098068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1469098068
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2539176320
Short name T1118
Test name
Test status
Simulation time 16960335779 ps
CPU time 25.04 seconds
Started Jul 04 05:42:41 PM PDT 24
Finished Jul 04 05:43:07 PM PDT 24
Peak memory 199912 kb
Host smart-b23d1ea4-516b-4259-9cca-67e61420c1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539176320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2539176320
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2787386343
Short name T757
Test name
Test status
Simulation time 12832633 ps
CPU time 0.54 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:38:47 PM PDT 24
Peak memory 194548 kb
Host smart-d5db3bd6-025c-446e-aa3e-e06aaa8abff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787386343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2787386343
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.257082717
Short name T606
Test name
Test status
Simulation time 72548032511 ps
CPU time 27.87 seconds
Started Jul 04 05:38:49 PM PDT 24
Finished Jul 04 05:39:18 PM PDT 24
Peak memory 199872 kb
Host smart-4816753e-e99b-4e40-aaaf-27cd108a168a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257082717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.257082717
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2219448158
Short name T390
Test name
Test status
Simulation time 18731030234 ps
CPU time 15.23 seconds
Started Jul 04 05:38:51 PM PDT 24
Finished Jul 04 05:39:06 PM PDT 24
Peak memory 199196 kb
Host smart-1fcda982-8368-49b9-88c9-4a04c9f36da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219448158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2219448158
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.2597254874
Short name T1088
Test name
Test status
Simulation time 17965059757 ps
CPU time 28.52 seconds
Started Jul 04 05:38:51 PM PDT 24
Finished Jul 04 05:39:20 PM PDT 24
Peak memory 199936 kb
Host smart-5365fee4-2656-4cd9-a9b8-3e1ffeb2f277
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597254874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2597254874
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2385688447
Short name T334
Test name
Test status
Simulation time 89896608542 ps
CPU time 308.9 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:43:57 PM PDT 24
Peak memory 199924 kb
Host smart-27ec6791-028e-4d46-b1ed-1a924bf79c8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385688447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2385688447
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.4037849125
Short name T908
Test name
Test status
Simulation time 8147116491 ps
CPU time 4.65 seconds
Started Jul 04 05:38:51 PM PDT 24
Finished Jul 04 05:38:56 PM PDT 24
Peak memory 199608 kb
Host smart-5f3c6f6d-0c85-47f9-9d67-86221ac08914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037849125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.4037849125
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2566360437
Short name T752
Test name
Test status
Simulation time 167893906286 ps
CPU time 24.2 seconds
Started Jul 04 05:38:50 PM PDT 24
Finished Jul 04 05:39:14 PM PDT 24
Peak memory 200248 kb
Host smart-5f6b1d5f-ab45-4d36-9405-d71852656b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566360437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2566360437
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3682844015
Short name T434
Test name
Test status
Simulation time 23433846329 ps
CPU time 259.76 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:43:08 PM PDT 24
Peak memory 199912 kb
Host smart-169e22cc-c967-43a7-b833-5cea4e719d61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682844015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3682844015
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.848966700
Short name T984
Test name
Test status
Simulation time 3877737922 ps
CPU time 31.88 seconds
Started Jul 04 05:38:49 PM PDT 24
Finished Jul 04 05:39:22 PM PDT 24
Peak memory 199092 kb
Host smart-3faf0142-c3b2-493d-a889-142d183f76b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=848966700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.848966700
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.963048912
Short name T120
Test name
Test status
Simulation time 11986103992 ps
CPU time 17.24 seconds
Started Jul 04 05:38:49 PM PDT 24
Finished Jul 04 05:39:06 PM PDT 24
Peak memory 199944 kb
Host smart-ee408861-a98d-4444-b7f9-dd7d11aa17b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963048912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.963048912
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1726807143
Short name T267
Test name
Test status
Simulation time 3096734302 ps
CPU time 1.78 seconds
Started Jul 04 05:38:49 PM PDT 24
Finished Jul 04 05:38:51 PM PDT 24
Peak memory 196224 kb
Host smart-4d49335f-1d27-46aa-9f7d-629505053a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726807143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1726807143
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3891689306
Short name T1111
Test name
Test status
Simulation time 5902080973 ps
CPU time 7.62 seconds
Started Jul 04 05:38:50 PM PDT 24
Finished Jul 04 05:38:58 PM PDT 24
Peak memory 199792 kb
Host smart-aca3936f-e0c2-4eb9-979b-3cfbb480f0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891689306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3891689306
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2340877654
Short name T464
Test name
Test status
Simulation time 141171143991 ps
CPU time 594.61 seconds
Started Jul 04 05:38:49 PM PDT 24
Finished Jul 04 05:48:44 PM PDT 24
Peak memory 200140 kb
Host smart-330f7495-c82d-4ab3-a2b4-ac5b8d0dafc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340877654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2340877654
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3138135716
Short name T45
Test name
Test status
Simulation time 32123134133 ps
CPU time 237.71 seconds
Started Jul 04 05:38:49 PM PDT 24
Finished Jul 04 05:42:47 PM PDT 24
Peak memory 211504 kb
Host smart-f2d246cd-8bc9-4472-9863-66dd77faedb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138135716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3138135716
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3624985796
Short name T873
Test name
Test status
Simulation time 818303447 ps
CPU time 2.82 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:38:51 PM PDT 24
Peak memory 198456 kb
Host smart-0fea9847-71d1-4aa2-88ce-dc39da8d394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624985796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3624985796
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.497837375
Short name T1114
Test name
Test status
Simulation time 63395820583 ps
CPU time 33.72 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:39:21 PM PDT 24
Peak memory 199984 kb
Host smart-21b11c4f-3da7-4049-9560-775d1b47102a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497837375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.497837375
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3792724268
Short name T1056
Test name
Test status
Simulation time 183628403503 ps
CPU time 238.02 seconds
Started Jul 04 05:42:43 PM PDT 24
Finished Jul 04 05:46:41 PM PDT 24
Peak memory 199944 kb
Host smart-6af323fc-14b0-4688-9c0f-b0d2d9072ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792724268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3792724268
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.342748395
Short name T782
Test name
Test status
Simulation time 17270087786 ps
CPU time 7.51 seconds
Started Jul 04 05:42:43 PM PDT 24
Finished Jul 04 05:42:50 PM PDT 24
Peak memory 199928 kb
Host smart-556e3681-8d7c-4b69-aff3-6ac449c5eb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342748395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.342748395
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.659561616
Short name T1091
Test name
Test status
Simulation time 15818746367 ps
CPU time 27.54 seconds
Started Jul 04 05:42:40 PM PDT 24
Finished Jul 04 05:43:08 PM PDT 24
Peak memory 199932 kb
Host smart-85a784da-8f12-4280-8591-f20815602903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659561616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.659561616
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3013755241
Short name T1123
Test name
Test status
Simulation time 268808627974 ps
CPU time 99.89 seconds
Started Jul 04 05:42:42 PM PDT 24
Finished Jul 04 05:44:22 PM PDT 24
Peak memory 199888 kb
Host smart-0f898945-0140-465d-a3e6-aafd06617f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013755241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3013755241
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4227628165
Short name T1169
Test name
Test status
Simulation time 40271859945 ps
CPU time 56.13 seconds
Started Jul 04 05:42:46 PM PDT 24
Finished Jul 04 05:43:43 PM PDT 24
Peak memory 199908 kb
Host smart-dc0156df-879e-443e-beb3-acde47fb79f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227628165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4227628165
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2296708731
Short name T85
Test name
Test status
Simulation time 146539536121 ps
CPU time 48.14 seconds
Started Jul 04 05:42:47 PM PDT 24
Finished Jul 04 05:43:35 PM PDT 24
Peak memory 199916 kb
Host smart-ead34402-b3a9-4a8e-92a8-2933c4d1729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296708731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2296708731
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4235297683
Short name T1006
Test name
Test status
Simulation time 186911198939 ps
CPU time 286.61 seconds
Started Jul 04 05:42:42 PM PDT 24
Finished Jul 04 05:47:29 PM PDT 24
Peak memory 199972 kb
Host smart-20f6c880-c28a-4c16-ac19-c6bcf8fcdcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235297683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4235297683
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3033852586
Short name T764
Test name
Test status
Simulation time 12264001 ps
CPU time 0.56 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:38:58 PM PDT 24
Peak memory 195516 kb
Host smart-f688b5e2-336d-4f9c-a0a2-7fe3cf306f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033852586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3033852586
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.698378587
Short name T647
Test name
Test status
Simulation time 205526115307 ps
CPU time 302.57 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:44:00 PM PDT 24
Peak memory 199852 kb
Host smart-5a86d31f-04e6-43d8-8740-65359c89c051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698378587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.698378587
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1054975309
Short name T774
Test name
Test status
Simulation time 98029632955 ps
CPU time 148.8 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:41:17 PM PDT 24
Peak memory 199936 kb
Host smart-88bbadc9-ed3e-4773-81c5-d64b6173cbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054975309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1054975309
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2248659271
Short name T626
Test name
Test status
Simulation time 162484801838 ps
CPU time 26.59 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:39:15 PM PDT 24
Peak memory 199768 kb
Host smart-115280df-d209-4ce4-a0c6-977bceae0105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248659271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2248659271
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2497721538
Short name T1037
Test name
Test status
Simulation time 104969448959 ps
CPU time 631.84 seconds
Started Jul 04 05:38:50 PM PDT 24
Finished Jul 04 05:49:22 PM PDT 24
Peak memory 199872 kb
Host smart-149f533a-59e3-434a-8787-d75d9fac8eaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497721538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2497721538
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2265599754
Short name T435
Test name
Test status
Simulation time 9109085404 ps
CPU time 30.07 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:39:19 PM PDT 24
Peak memory 199428 kb
Host smart-cdd78262-86f2-4f67-9406-8c860cf95279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265599754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2265599754
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2153661110
Short name T446
Test name
Test status
Simulation time 10009571870 ps
CPU time 17.05 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:39:14 PM PDT 24
Peak memory 200032 kb
Host smart-e9bd47b7-bfad-4c84-81de-c34326b5d216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153661110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2153661110
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1479304304
Short name T729
Test name
Test status
Simulation time 10628255854 ps
CPU time 151.91 seconds
Started Jul 04 05:38:49 PM PDT 24
Finished Jul 04 05:41:21 PM PDT 24
Peak memory 199872 kb
Host smart-9015db79-1c51-4922-a7c7-8da2c1a9a6fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479304304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1479304304
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2945037832
Short name T928
Test name
Test status
Simulation time 5558140009 ps
CPU time 28.69 seconds
Started Jul 04 05:38:50 PM PDT 24
Finished Jul 04 05:39:19 PM PDT 24
Peak memory 199936 kb
Host smart-f4e1fb35-aba8-4f31-88a2-9258cd899cbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2945037832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2945037832
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.4007296675
Short name T682
Test name
Test status
Simulation time 103852945661 ps
CPU time 35.19 seconds
Started Jul 04 05:38:53 PM PDT 24
Finished Jul 04 05:39:28 PM PDT 24
Peak memory 199876 kb
Host smart-305ca31f-b0a3-4211-b7a0-3f54005da65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007296675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.4007296675
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1136164171
Short name T624
Test name
Test status
Simulation time 4780285440 ps
CPU time 8.13 seconds
Started Jul 04 05:38:50 PM PDT 24
Finished Jul 04 05:38:59 PM PDT 24
Peak memory 196468 kb
Host smart-f4ff4ed3-0ca1-4d3f-be8a-97c2cc8e359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136164171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1136164171
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2350563597
Short name T969
Test name
Test status
Simulation time 449562212 ps
CPU time 1.95 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:38:50 PM PDT 24
Peak memory 199732 kb
Host smart-93a8b1e9-74b9-47d9-961e-aee80b687408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350563597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2350563597
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2256445460
Short name T1047
Test name
Test status
Simulation time 18372648555 ps
CPU time 289.91 seconds
Started Jul 04 05:38:49 PM PDT 24
Finished Jul 04 05:43:40 PM PDT 24
Peak memory 210984 kb
Host smart-ac1468cd-b059-4f56-8ef6-3b258812bfc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256445460 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2256445460
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1377909136
Short name T794
Test name
Test status
Simulation time 1118436034 ps
CPU time 3.65 seconds
Started Jul 04 05:38:50 PM PDT 24
Finished Jul 04 05:38:54 PM PDT 24
Peak memory 198732 kb
Host smart-80ef166d-c0ff-4fcc-9e41-7a9cee11cea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377909136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1377909136
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.387330022
Short name T918
Test name
Test status
Simulation time 30492167230 ps
CPU time 28.63 seconds
Started Jul 04 05:38:48 PM PDT 24
Finished Jul 04 05:39:17 PM PDT 24
Peak memory 199988 kb
Host smart-e49b5ca7-a845-402b-8e64-203de41cc545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387330022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.387330022
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.4121545296
Short name T791
Test name
Test status
Simulation time 47797264625 ps
CPU time 18.35 seconds
Started Jul 04 05:42:50 PM PDT 24
Finished Jul 04 05:43:09 PM PDT 24
Peak memory 199884 kb
Host smart-ad5593ec-32e2-4e24-be87-58e3d2952bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121545296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.4121545296
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1128583939
Short name T187
Test name
Test status
Simulation time 24290779227 ps
CPU time 22.41 seconds
Started Jul 04 05:42:51 PM PDT 24
Finished Jul 04 05:43:13 PM PDT 24
Peak memory 199924 kb
Host smart-6ad85d24-3a57-4044-897d-084d5cd4b737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128583939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1128583939
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3071882452
Short name T182
Test name
Test status
Simulation time 332476562639 ps
CPU time 82.74 seconds
Started Jul 04 05:42:49 PM PDT 24
Finished Jul 04 05:44:12 PM PDT 24
Peak memory 199936 kb
Host smart-0cb178cf-753b-40a4-be49-f56113ebaaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071882452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3071882452
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2521698177
Short name T945
Test name
Test status
Simulation time 27957749151 ps
CPU time 49.79 seconds
Started Jul 04 05:42:49 PM PDT 24
Finished Jul 04 05:43:39 PM PDT 24
Peak memory 199948 kb
Host smart-65f8cfdb-ab27-407a-bd8f-8e9be5140b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521698177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2521698177
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2632790226
Short name T184
Test name
Test status
Simulation time 83322927404 ps
CPU time 51.52 seconds
Started Jul 04 05:42:50 PM PDT 24
Finished Jul 04 05:43:42 PM PDT 24
Peak memory 199924 kb
Host smart-af55c8fe-071a-432f-bcca-5e85096af678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632790226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2632790226
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3608296022
Short name T1090
Test name
Test status
Simulation time 22204661637 ps
CPU time 39.67 seconds
Started Jul 04 05:42:49 PM PDT 24
Finished Jul 04 05:43:29 PM PDT 24
Peak memory 199924 kb
Host smart-2d3c6be4-73ff-4470-b24e-e71c3c5cc979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608296022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3608296022
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3483862556
Short name T322
Test name
Test status
Simulation time 206042104616 ps
CPU time 83.14 seconds
Started Jul 04 05:42:50 PM PDT 24
Finished Jul 04 05:44:13 PM PDT 24
Peak memory 199920 kb
Host smart-f956022d-a5f6-423c-a321-7ab912d3ee24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483862556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3483862556
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.967366652
Short name T352
Test name
Test status
Simulation time 19926722 ps
CPU time 0.54 seconds
Started Jul 04 05:38:58 PM PDT 24
Finished Jul 04 05:38:59 PM PDT 24
Peak memory 194468 kb
Host smart-d18da854-f77e-4269-9218-5ece4fe40e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967366652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.967366652
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1174080406
Short name T287
Test name
Test status
Simulation time 31428333392 ps
CPU time 51.29 seconds
Started Jul 04 05:38:51 PM PDT 24
Finished Jul 04 05:39:42 PM PDT 24
Peak memory 199924 kb
Host smart-6d26f41f-a7e2-452f-9951-db0b25d7b38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174080406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1174080406
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.979667872
Short name T615
Test name
Test status
Simulation time 8284284975 ps
CPU time 14.34 seconds
Started Jul 04 05:38:51 PM PDT 24
Finished Jul 04 05:39:06 PM PDT 24
Peak memory 198100 kb
Host smart-c07f623f-ccbb-4b13-a87a-0292f5ad8d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979667872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.979667872
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3939637929
Short name T1029
Test name
Test status
Simulation time 247854121371 ps
CPU time 93.02 seconds
Started Jul 04 05:38:56 PM PDT 24
Finished Jul 04 05:40:30 PM PDT 24
Peak memory 199988 kb
Host smart-424c7e1f-6ecf-4e77-80d4-6da2d40df377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939637929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3939637929
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.159043844
Short name T292
Test name
Test status
Simulation time 22452803274 ps
CPU time 10.02 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:39:07 PM PDT 24
Peak memory 199960 kb
Host smart-db6dc97e-3f75-4c46-b910-87212b89e003
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159043844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.159043844
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.464960813
Short name T1132
Test name
Test status
Simulation time 33982644740 ps
CPU time 120.13 seconds
Started Jul 04 05:38:56 PM PDT 24
Finished Jul 04 05:40:57 PM PDT 24
Peak memory 200000 kb
Host smart-3158433c-7682-413b-84c1-3d7ebc1c00f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464960813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.464960813
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3426147871
Short name T357
Test name
Test status
Simulation time 4102467416 ps
CPU time 3.56 seconds
Started Jul 04 05:38:56 PM PDT 24
Finished Jul 04 05:39:00 PM PDT 24
Peak memory 199608 kb
Host smart-1115c125-db14-4d4c-82bb-59455e11c2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426147871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3426147871
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1640354962
Short name T891
Test name
Test status
Simulation time 18220915262 ps
CPU time 26.97 seconds
Started Jul 04 05:39:02 PM PDT 24
Finished Jul 04 05:39:29 PM PDT 24
Peak memory 198568 kb
Host smart-cb92961d-69f1-465e-9c52-adc1eaf9811f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640354962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1640354962
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2809533693
Short name T290
Test name
Test status
Simulation time 28457587506 ps
CPU time 1545.71 seconds
Started Jul 04 05:38:56 PM PDT 24
Finished Jul 04 06:04:42 PM PDT 24
Peak memory 199940 kb
Host smart-03cfcb27-d15b-429a-953c-70faffb929cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809533693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2809533693
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2202235744
Short name T1098
Test name
Test status
Simulation time 3351612407 ps
CPU time 9.83 seconds
Started Jul 04 05:38:59 PM PDT 24
Finished Jul 04 05:39:09 PM PDT 24
Peak memory 198136 kb
Host smart-be236178-d2a0-42da-ab4c-33c636ab0a75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202235744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2202235744
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3121004620
Short name T1128
Test name
Test status
Simulation time 113579182819 ps
CPU time 58.83 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:39:56 PM PDT 24
Peak memory 199924 kb
Host smart-34a0d604-3b72-4885-b596-f300c088a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121004620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3121004620
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3785442047
Short name T1022
Test name
Test status
Simulation time 40719598906 ps
CPU time 59.27 seconds
Started Jul 04 05:38:58 PM PDT 24
Finished Jul 04 05:39:57 PM PDT 24
Peak memory 196156 kb
Host smart-64dd7882-6870-40be-b18f-4f3245d05dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785442047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3785442047
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2750313117
Short name T433
Test name
Test status
Simulation time 889550818 ps
CPU time 3.31 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:39:01 PM PDT 24
Peak memory 198796 kb
Host smart-23fdd7fe-d76f-4dac-912f-4bd21a50b84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750313117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2750313117
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3784554528
Short name T1117
Test name
Test status
Simulation time 505884555621 ps
CPU time 62.18 seconds
Started Jul 04 05:39:00 PM PDT 24
Finished Jul 04 05:40:02 PM PDT 24
Peak memory 208388 kb
Host smart-fc8c6941-9c67-4e90-9e2c-38041ae7498c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784554528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3784554528
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3565052777
Short name T611
Test name
Test status
Simulation time 73531612073 ps
CPU time 1297.57 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 06:00:35 PM PDT 24
Peak memory 227916 kb
Host smart-eddfec72-d9fa-494e-ab95-e0a3ae780c1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565052777 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3565052777
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1106037760
Short name T453
Test name
Test status
Simulation time 2500993101 ps
CPU time 2.64 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:39:00 PM PDT 24
Peak memory 199876 kb
Host smart-fe08dbc1-43e8-4c90-88d6-94d1bb41d5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106037760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1106037760
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.247887838
Short name T702
Test name
Test status
Simulation time 73039640947 ps
CPU time 68.88 seconds
Started Jul 04 05:38:47 PM PDT 24
Finished Jul 04 05:39:57 PM PDT 24
Peak memory 199932 kb
Host smart-0b5f56b4-a1c0-4667-9cbd-3335fa634ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247887838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.247887838
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3827196646
Short name T779
Test name
Test status
Simulation time 9398054547 ps
CPU time 22.54 seconds
Started Jul 04 05:42:52 PM PDT 24
Finished Jul 04 05:43:16 PM PDT 24
Peak memory 199948 kb
Host smart-75bd35b9-5c5f-4dfc-acf1-8a892652a906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827196646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3827196646
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3203961876
Short name T1157
Test name
Test status
Simulation time 23994749824 ps
CPU time 20.25 seconds
Started Jul 04 05:42:50 PM PDT 24
Finished Jul 04 05:43:11 PM PDT 24
Peak memory 199872 kb
Host smart-16c04f94-e600-407f-ae4f-1de014fc49a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203961876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3203961876
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3078372639
Short name T1030
Test name
Test status
Simulation time 23673205186 ps
CPU time 12.25 seconds
Started Jul 04 05:42:50 PM PDT 24
Finished Jul 04 05:43:03 PM PDT 24
Peak memory 200004 kb
Host smart-60ed6000-a31e-432c-8166-91a6b303e176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078372639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3078372639
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1837523287
Short name T907
Test name
Test status
Simulation time 68196425721 ps
CPU time 107.63 seconds
Started Jul 04 05:42:47 PM PDT 24
Finished Jul 04 05:44:35 PM PDT 24
Peak memory 200020 kb
Host smart-bda970e4-a213-4c4f-bf0f-01fb87165663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837523287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1837523287
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2043839463
Short name T964
Test name
Test status
Simulation time 17358593280 ps
CPU time 32.97 seconds
Started Jul 04 05:42:50 PM PDT 24
Finished Jul 04 05:43:23 PM PDT 24
Peak memory 199932 kb
Host smart-046810b7-9a64-4d97-92ab-1de8f490f000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043839463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2043839463
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3506333575
Short name T612
Test name
Test status
Simulation time 67515264558 ps
CPU time 31.76 seconds
Started Jul 04 05:42:49 PM PDT 24
Finished Jul 04 05:43:21 PM PDT 24
Peak memory 199940 kb
Host smart-90603630-cb33-4f48-bde2-908135136011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506333575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3506333575
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3510902239
Short name T1127
Test name
Test status
Simulation time 67380258846 ps
CPU time 66.07 seconds
Started Jul 04 05:42:54 PM PDT 24
Finished Jul 04 05:44:00 PM PDT 24
Peak memory 199996 kb
Host smart-dadb13fd-fecd-4b15-8be7-a9b137399e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510902239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3510902239
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1683352177
Short name T812
Test name
Test status
Simulation time 41853119740 ps
CPU time 18.45 seconds
Started Jul 04 05:42:58 PM PDT 24
Finished Jul 04 05:43:17 PM PDT 24
Peak memory 199696 kb
Host smart-968dd7ee-85ca-42b4-bf2f-4defeacfc998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683352177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1683352177
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.4113548812
Short name T458
Test name
Test status
Simulation time 36447348322 ps
CPU time 16.88 seconds
Started Jul 04 05:42:59 PM PDT 24
Finished Jul 04 05:43:16 PM PDT 24
Peak memory 199908 kb
Host smart-394365da-d870-4e42-88d8-30a67693aef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113548812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.4113548812
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.45018583
Short name T573
Test name
Test status
Simulation time 24544419 ps
CPU time 0.55 seconds
Started Jul 04 05:38:58 PM PDT 24
Finished Jul 04 05:38:59 PM PDT 24
Peak memory 195300 kb
Host smart-5e003751-1a37-46e2-bcce-ca0f94924240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45018583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.45018583
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.860829843
Short name T929
Test name
Test status
Simulation time 142867469601 ps
CPU time 19.93 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:39:18 PM PDT 24
Peak memory 199892 kb
Host smart-d575dc07-879b-4b94-bd54-287c5e75e3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860829843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.860829843
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2988081030
Short name T953
Test name
Test status
Simulation time 309674392209 ps
CPU time 147.21 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:41:25 PM PDT 24
Peak memory 199844 kb
Host smart-876b48fc-ff62-4b7f-aed5-2af47e2fdfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988081030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2988081030
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1493841784
Short name T449
Test name
Test status
Simulation time 17656855427 ps
CPU time 9.22 seconds
Started Jul 04 05:39:02 PM PDT 24
Finished Jul 04 05:39:11 PM PDT 24
Peak memory 199924 kb
Host smart-caf461b4-9553-428d-b0aa-3ae147438652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493841784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1493841784
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2446138669
Short name T417
Test name
Test status
Simulation time 15220862503 ps
CPU time 2.99 seconds
Started Jul 04 05:38:55 PM PDT 24
Finished Jul 04 05:38:59 PM PDT 24
Peak memory 196640 kb
Host smart-2578d9e8-33ac-47fd-8df7-8dddfe0d4c23
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446138669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2446138669
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2413712339
Short name T980
Test name
Test status
Simulation time 148003833126 ps
CPU time 1165.49 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:58:23 PM PDT 24
Peak memory 199852 kb
Host smart-8b0adf06-385f-44cd-a3f0-f9d06d8dd3a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413712339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2413712339
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.975815536
Short name T686
Test name
Test status
Simulation time 4431994423 ps
CPU time 10.53 seconds
Started Jul 04 05:39:00 PM PDT 24
Finished Jul 04 05:39:11 PM PDT 24
Peak memory 199928 kb
Host smart-ba75a643-6c27-45eb-a406-eb89d0df50e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975815536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.975815536
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.4220717516
Short name T244
Test name
Test status
Simulation time 54816330807 ps
CPU time 22.87 seconds
Started Jul 04 05:38:59 PM PDT 24
Finished Jul 04 05:39:22 PM PDT 24
Peak memory 197448 kb
Host smart-457cc91c-d073-4d4c-a49a-c1fbe19ced6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220717516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.4220717516
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.747049255
Short name T355
Test name
Test status
Simulation time 4694266746 ps
CPU time 269.71 seconds
Started Jul 04 05:38:56 PM PDT 24
Finished Jul 04 05:43:26 PM PDT 24
Peak memory 199992 kb
Host smart-57c899d9-d80d-4a03-95ed-500cdec81c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747049255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.747049255
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.362277289
Short name T759
Test name
Test status
Simulation time 4162484036 ps
CPU time 31.66 seconds
Started Jul 04 05:38:55 PM PDT 24
Finished Jul 04 05:39:27 PM PDT 24
Peak memory 198112 kb
Host smart-d176200d-72d7-4082-86dc-645f66e6c57f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362277289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.362277289
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1501987974
Short name T266
Test name
Test status
Simulation time 150770836148 ps
CPU time 524.73 seconds
Started Jul 04 05:38:56 PM PDT 24
Finished Jul 04 05:47:41 PM PDT 24
Peak memory 199912 kb
Host smart-85e7746f-212f-40a8-a4f0-883e0ad1f283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501987974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1501987974
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3419283499
Short name T901
Test name
Test status
Simulation time 1980342012 ps
CPU time 3.75 seconds
Started Jul 04 05:38:56 PM PDT 24
Finished Jul 04 05:39:00 PM PDT 24
Peak memory 195568 kb
Host smart-b18a8edd-e7c6-4133-8fca-262971bf82ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419283499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3419283499
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1916109372
Short name T614
Test name
Test status
Simulation time 278120949 ps
CPU time 0.96 seconds
Started Jul 04 05:38:58 PM PDT 24
Finished Jul 04 05:38:59 PM PDT 24
Peak memory 198408 kb
Host smart-0e4c0f94-a14b-48bc-9984-7edf29edf93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916109372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1916109372
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3214052968
Short name T905
Test name
Test status
Simulation time 17571103619 ps
CPU time 87.2 seconds
Started Jul 04 05:38:57 PM PDT 24
Finished Jul 04 05:40:25 PM PDT 24
Peak memory 215460 kb
Host smart-400b642a-5091-4c15-a602-9d9c94158e1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214052968 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3214052968
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3812261521
Short name T1129
Test name
Test status
Simulation time 429391663 ps
CPU time 1.07 seconds
Started Jul 04 05:38:56 PM PDT 24
Finished Jul 04 05:38:58 PM PDT 24
Peak memory 196952 kb
Host smart-f4446e6a-586d-4032-a122-ab33d3c5f8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812261521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3812261521
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.379937674
Short name T481
Test name
Test status
Simulation time 9504227710 ps
CPU time 17.63 seconds
Started Jul 04 05:38:58 PM PDT 24
Finished Jul 04 05:39:16 PM PDT 24
Peak memory 199988 kb
Host smart-33b232da-0402-4f04-a9fd-1dc96b7100d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379937674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.379937674
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.10425694
Short name T159
Test name
Test status
Simulation time 155283533125 ps
CPU time 76.22 seconds
Started Jul 04 05:42:53 PM PDT 24
Finished Jul 04 05:44:10 PM PDT 24
Peak memory 199900 kb
Host smart-6fa34e73-c0d7-414f-ac0b-566e15c54b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10425694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.10425694
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.158804912
Short name T206
Test name
Test status
Simulation time 120683900211 ps
CPU time 105.43 seconds
Started Jul 04 05:42:56 PM PDT 24
Finished Jul 04 05:44:42 PM PDT 24
Peak memory 199964 kb
Host smart-ae377656-041e-4ab3-93cd-2b5f4dc69e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158804912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.158804912
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1768731418
Short name T1010
Test name
Test status
Simulation time 257037774055 ps
CPU time 41 seconds
Started Jul 04 05:42:58 PM PDT 24
Finished Jul 04 05:43:39 PM PDT 24
Peak memory 199976 kb
Host smart-1e7b27d7-d4a9-4344-b6cd-f3d10f48517d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768731418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1768731418
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.305320768
Short name T1062
Test name
Test status
Simulation time 156842518202 ps
CPU time 297.54 seconds
Started Jul 04 05:42:56 PM PDT 24
Finished Jul 04 05:47:54 PM PDT 24
Peak memory 199896 kb
Host smart-6ad8f1d7-5a65-45f1-85db-758d6fd5e2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305320768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.305320768
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.321036080
Short name T192
Test name
Test status
Simulation time 14146090727 ps
CPU time 31.53 seconds
Started Jul 04 05:42:58 PM PDT 24
Finished Jul 04 05:43:30 PM PDT 24
Peak memory 199912 kb
Host smart-bc917260-4518-499a-8035-4ba36964cf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321036080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.321036080
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1504998110
Short name T174
Test name
Test status
Simulation time 86282881345 ps
CPU time 56.21 seconds
Started Jul 04 05:42:57 PM PDT 24
Finished Jul 04 05:43:53 PM PDT 24
Peak memory 199956 kb
Host smart-fdb7992d-ca26-47b9-8b97-fc79db88aab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504998110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1504998110
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3597405250
Short name T288
Test name
Test status
Simulation time 81110180443 ps
CPU time 34.03 seconds
Started Jul 04 05:42:56 PM PDT 24
Finished Jul 04 05:43:30 PM PDT 24
Peak memory 199872 kb
Host smart-2fa52a78-6808-40d1-99c0-a06f518f2a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597405250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3597405250
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3205122586
Short name T141
Test name
Test status
Simulation time 72178641969 ps
CPU time 98.69 seconds
Started Jul 04 05:42:55 PM PDT 24
Finished Jul 04 05:44:34 PM PDT 24
Peak memory 199888 kb
Host smart-3cea7c43-a37c-4227-8bbb-4730dc300165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205122586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3205122586
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.971385606
Short name T345
Test name
Test status
Simulation time 11005714 ps
CPU time 0.54 seconds
Started Jul 04 05:39:00 PM PDT 24
Finished Jul 04 05:39:01 PM PDT 24
Peak memory 194500 kb
Host smart-42f90d45-b7eb-4f86-9ab8-9861360ba987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971385606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.971385606
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3197087305
Short name T943
Test name
Test status
Simulation time 74390668427 ps
CPU time 64.31 seconds
Started Jul 04 05:39:03 PM PDT 24
Finished Jul 04 05:40:07 PM PDT 24
Peak memory 199952 kb
Host smart-550c25fe-dfca-4816-8f67-e915377fdd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197087305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3197087305
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2673035574
Short name T566
Test name
Test status
Simulation time 31988910968 ps
CPU time 21.95 seconds
Started Jul 04 05:39:03 PM PDT 24
Finished Jul 04 05:39:25 PM PDT 24
Peak memory 199932 kb
Host smart-0f097cad-a68c-4950-8ab7-7ae38584a409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673035574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2673035574
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.910256518
Short name T1109
Test name
Test status
Simulation time 72614225647 ps
CPU time 167.95 seconds
Started Jul 04 05:39:06 PM PDT 24
Finished Jul 04 05:41:55 PM PDT 24
Peak memory 199948 kb
Host smart-7c52e0c5-e2b1-4c36-869b-36d04cd8d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910256518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.910256518
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3465170156
Short name T985
Test name
Test status
Simulation time 14282444919 ps
CPU time 6.81 seconds
Started Jul 04 05:39:05 PM PDT 24
Finished Jul 04 05:39:12 PM PDT 24
Peak memory 199900 kb
Host smart-e3b4dc2d-b2b6-4705-a87f-d15700a34b19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465170156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3465170156
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2170912211
Short name T37
Test name
Test status
Simulation time 101510378329 ps
CPU time 299.32 seconds
Started Jul 04 05:39:05 PM PDT 24
Finished Jul 04 05:44:04 PM PDT 24
Peak memory 199956 kb
Host smart-ef647810-32e7-486f-8bb2-9c3fd88dd363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170912211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2170912211
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.428096687
Short name T364
Test name
Test status
Simulation time 4961419482 ps
CPU time 4.51 seconds
Started Jul 04 05:39:02 PM PDT 24
Finished Jul 04 05:39:07 PM PDT 24
Peak memory 198492 kb
Host smart-586a9cdb-0432-4450-b94f-af0cb49df3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428096687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.428096687
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2733248106
Short name T616
Test name
Test status
Simulation time 71098652796 ps
CPU time 115.63 seconds
Started Jul 04 05:39:04 PM PDT 24
Finished Jul 04 05:41:00 PM PDT 24
Peak memory 199940 kb
Host smart-b24e6ceb-94ef-41ab-85b2-3018e1f22c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733248106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2733248106
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1722377226
Short name T1140
Test name
Test status
Simulation time 32172288245 ps
CPU time 218.94 seconds
Started Jul 04 05:39:04 PM PDT 24
Finished Jul 04 05:42:44 PM PDT 24
Peak memory 199952 kb
Host smart-984b6265-65ee-484d-a932-2c62646d3caa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722377226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1722377226
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.596682428
Short name T671
Test name
Test status
Simulation time 3668474084 ps
CPU time 15.51 seconds
Started Jul 04 05:39:01 PM PDT 24
Finished Jul 04 05:39:17 PM PDT 24
Peak memory 198112 kb
Host smart-3b2bbafa-0b48-461a-8acc-4de0eb76a8fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596682428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.596682428
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.4078760428
Short name T995
Test name
Test status
Simulation time 278225121510 ps
CPU time 45.44 seconds
Started Jul 04 05:39:02 PM PDT 24
Finished Jul 04 05:39:48 PM PDT 24
Peak memory 199812 kb
Host smart-52b5f5c7-778e-4281-9ce2-041137a8289a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078760428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4078760428
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2108080937
Short name T745
Test name
Test status
Simulation time 76288021132 ps
CPU time 53.16 seconds
Started Jul 04 05:39:02 PM PDT 24
Finished Jul 04 05:39:56 PM PDT 24
Peak memory 195692 kb
Host smart-1ba6fcfe-87a4-4d95-9b5c-d6c6502238a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108080937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2108080937
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2271014276
Short name T447
Test name
Test status
Simulation time 116973881 ps
CPU time 0.73 seconds
Started Jul 04 05:38:55 PM PDT 24
Finished Jul 04 05:38:56 PM PDT 24
Peak memory 196812 kb
Host smart-7b95c8dc-e928-40ae-bfd0-50cdeb6be0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271014276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2271014276
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3251300837
Short name T747
Test name
Test status
Simulation time 106282679567 ps
CPU time 1145.23 seconds
Started Jul 04 05:39:03 PM PDT 24
Finished Jul 04 05:58:09 PM PDT 24
Peak memory 199968 kb
Host smart-896ce250-49c0-42a7-82d6-1c132f199836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251300837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3251300837
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1430773426
Short name T975
Test name
Test status
Simulation time 231744277490 ps
CPU time 629.43 seconds
Started Jul 04 05:39:05 PM PDT 24
Finished Jul 04 05:49:35 PM PDT 24
Peak memory 224904 kb
Host smart-f714307a-7213-42a8-a759-53f928437a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430773426 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1430773426
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.37743217
Short name T1167
Test name
Test status
Simulation time 1036925299 ps
CPU time 2.33 seconds
Started Jul 04 05:39:02 PM PDT 24
Finished Jul 04 05:39:04 PM PDT 24
Peak memory 199580 kb
Host smart-7d4f58b1-197f-4d40-ad22-c7f8a04ac32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37743217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.37743217
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2931570184
Short name T490
Test name
Test status
Simulation time 53932651749 ps
CPU time 18.63 seconds
Started Jul 04 05:39:02 PM PDT 24
Finished Jul 04 05:39:20 PM PDT 24
Peak memory 199916 kb
Host smart-f376004e-86af-41b9-abdd-472d63ebec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931570184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2931570184
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.4120527053
Short name T999
Test name
Test status
Simulation time 129390535575 ps
CPU time 182.67 seconds
Started Jul 04 05:42:57 PM PDT 24
Finished Jul 04 05:46:00 PM PDT 24
Peak memory 199984 kb
Host smart-caf6de35-f191-48a0-bb8a-6922544f0b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120527053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.4120527053
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.924201496
Short name T914
Test name
Test status
Simulation time 124916027708 ps
CPU time 47.46 seconds
Started Jul 04 05:42:58 PM PDT 24
Finished Jul 04 05:43:46 PM PDT 24
Peak memory 199952 kb
Host smart-83dbd879-998b-4f75-8b7b-10b37e12f8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924201496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.924201496
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.32990169
Short name T1126
Test name
Test status
Simulation time 43182346208 ps
CPU time 66.76 seconds
Started Jul 04 05:42:54 PM PDT 24
Finished Jul 04 05:44:01 PM PDT 24
Peak memory 199976 kb
Host smart-764cbd16-c21b-4d9f-b76d-2a99a36bbe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32990169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.32990169
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.633827477
Short name T1061
Test name
Test status
Simulation time 35580812437 ps
CPU time 94.89 seconds
Started Jul 04 05:43:03 PM PDT 24
Finished Jul 04 05:44:38 PM PDT 24
Peak memory 199992 kb
Host smart-334184ce-cf35-48f2-8c2c-1c023584a207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633827477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.633827477
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.734221545
Short name T211
Test name
Test status
Simulation time 51788261249 ps
CPU time 22.77 seconds
Started Jul 04 05:43:05 PM PDT 24
Finished Jul 04 05:43:28 PM PDT 24
Peak memory 199980 kb
Host smart-8279a54b-35f0-4f9f-be69-196f0fb0ca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734221545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.734221545
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2013279663
Short name T716
Test name
Test status
Simulation time 25232180725 ps
CPU time 14.34 seconds
Started Jul 04 05:43:05 PM PDT 24
Finished Jul 04 05:43:19 PM PDT 24
Peak memory 199984 kb
Host smart-4d87f6f7-a7f9-4a00-922e-607c6f0115fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013279663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2013279663
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2686447747
Short name T2
Test name
Test status
Simulation time 39577705424 ps
CPU time 62.77 seconds
Started Jul 04 05:43:01 PM PDT 24
Finished Jul 04 05:44:04 PM PDT 24
Peak memory 199960 kb
Host smart-9443c5fd-409f-4b7b-a4b0-00401d1d0793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686447747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2686447747
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.340315262
Short name T1164
Test name
Test status
Simulation time 74000349 ps
CPU time 0.57 seconds
Started Jul 04 05:39:10 PM PDT 24
Finished Jul 04 05:39:11 PM PDT 24
Peak memory 195208 kb
Host smart-cde6eee2-dca1-458a-82ad-ded7e8934fc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340315262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.340315262
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1216887257
Short name T1100
Test name
Test status
Simulation time 94551720303 ps
CPU time 30.92 seconds
Started Jul 04 05:39:03 PM PDT 24
Finished Jul 04 05:39:35 PM PDT 24
Peak memory 199936 kb
Host smart-c88459ab-99b9-46a3-934e-b9f51549cda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216887257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1216887257
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2604647693
Short name T420
Test name
Test status
Simulation time 254025945512 ps
CPU time 65.09 seconds
Started Jul 04 05:39:02 PM PDT 24
Finished Jul 04 05:40:08 PM PDT 24
Peak memory 199860 kb
Host smart-066ff7a3-1079-447a-b69d-cad3b5fec270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604647693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2604647693
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1933369206
Short name T1130
Test name
Test status
Simulation time 155081689265 ps
CPU time 124.55 seconds
Started Jul 04 05:39:04 PM PDT 24
Finished Jul 04 05:41:09 PM PDT 24
Peak memory 199964 kb
Host smart-90139d93-4686-41d8-adb3-783cb86c5e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933369206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1933369206
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2354295357
Short name T927
Test name
Test status
Simulation time 26445307411 ps
CPU time 5.02 seconds
Started Jul 04 05:39:06 PM PDT 24
Finished Jul 04 05:39:11 PM PDT 24
Peak memory 199988 kb
Host smart-58470e37-ed54-4754-8566-4efa7b199f14
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354295357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2354295357
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4285076495
Short name T589
Test name
Test status
Simulation time 87308868148 ps
CPU time 233.83 seconds
Started Jul 04 05:39:10 PM PDT 24
Finished Jul 04 05:43:04 PM PDT 24
Peak memory 199912 kb
Host smart-0255b81d-80aa-427d-b9ae-73e4e8e6fd13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285076495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4285076495
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2463985563
Short name T1005
Test name
Test status
Simulation time 1425244739 ps
CPU time 2.88 seconds
Started Jul 04 05:39:04 PM PDT 24
Finished Jul 04 05:39:07 PM PDT 24
Peak memory 197388 kb
Host smart-234cbaf2-8475-46ab-83b7-5246bdb9201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463985563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2463985563
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.171573338
Short name T354
Test name
Test status
Simulation time 32309607365 ps
CPU time 12.64 seconds
Started Jul 04 05:39:05 PM PDT 24
Finished Jul 04 05:39:18 PM PDT 24
Peak memory 198496 kb
Host smart-46ea3f39-4716-4db1-94d4-79ada6129c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171573338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.171573338
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2184102929
Short name T715
Test name
Test status
Simulation time 21469179910 ps
CPU time 267.45 seconds
Started Jul 04 05:39:13 PM PDT 24
Finished Jul 04 05:43:41 PM PDT 24
Peak memory 199912 kb
Host smart-ee2e8269-1643-4a18-82a0-16f40eee30cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184102929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2184102929
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2557366793
Short name T583
Test name
Test status
Simulation time 3066016509 ps
CPU time 3.96 seconds
Started Jul 04 05:39:06 PM PDT 24
Finished Jul 04 05:39:11 PM PDT 24
Peak memory 198120 kb
Host smart-033a751e-2f10-4750-b7b0-a8f253ba8903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557366793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2557366793
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1456807118
Short name T680
Test name
Test status
Simulation time 109163931378 ps
CPU time 290.05 seconds
Started Jul 04 05:39:06 PM PDT 24
Finished Jul 04 05:43:57 PM PDT 24
Peak memory 199960 kb
Host smart-cc606039-4b82-4251-9a9d-5eeb86a3e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456807118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1456807118
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2313650122
Short name T492
Test name
Test status
Simulation time 45084342978 ps
CPU time 61.41 seconds
Started Jul 04 05:39:02 PM PDT 24
Finished Jul 04 05:40:03 PM PDT 24
Peak memory 196412 kb
Host smart-24ede7b8-e1e2-4379-9192-87e189f09bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313650122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2313650122
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1932917073
Short name T506
Test name
Test status
Simulation time 989035042 ps
CPU time 1.49 seconds
Started Jul 04 05:39:07 PM PDT 24
Finished Jul 04 05:39:09 PM PDT 24
Peak memory 198808 kb
Host smart-29df397a-d930-43df-a5f4-3e1dffe66907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932917073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1932917073
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.923510925
Short name T777
Test name
Test status
Simulation time 461583121881 ps
CPU time 248.8 seconds
Started Jul 04 05:39:10 PM PDT 24
Finished Jul 04 05:43:19 PM PDT 24
Peak memory 199872 kb
Host smart-92b3ce09-799e-4d6c-967a-260d4dee8f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923510925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.923510925
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2910860673
Short name T303
Test name
Test status
Simulation time 115616912419 ps
CPU time 340.42 seconds
Started Jul 04 05:39:08 PM PDT 24
Finished Jul 04 05:44:49 PM PDT 24
Peak memory 216496 kb
Host smart-c9d4c764-f1e2-42d4-b9c9-a110499cef8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910860673 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2910860673
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2287651972
Short name T424
Test name
Test status
Simulation time 649049076 ps
CPU time 2.38 seconds
Started Jul 04 05:39:04 PM PDT 24
Finished Jul 04 05:39:06 PM PDT 24
Peak memory 199644 kb
Host smart-1c1c74b1-b332-4364-9561-293f8218bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287651972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2287651972
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.4090375107
Short name T238
Test name
Test status
Simulation time 62974501694 ps
CPU time 164.57 seconds
Started Jul 04 05:39:03 PM PDT 24
Finished Jul 04 05:41:47 PM PDT 24
Peak memory 199984 kb
Host smart-04acb08e-fad6-41e0-99d7-75f0c22f06cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090375107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.4090375107
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1789240284
Short name T849
Test name
Test status
Simulation time 86398125200 ps
CPU time 23.5 seconds
Started Jul 04 05:43:06 PM PDT 24
Finished Jul 04 05:43:30 PM PDT 24
Peak memory 199980 kb
Host smart-6cb6ead1-1f0c-4e31-85fe-129500442efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789240284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1789240284
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1686804756
Short name T597
Test name
Test status
Simulation time 52634076805 ps
CPU time 60.41 seconds
Started Jul 04 05:43:04 PM PDT 24
Finished Jul 04 05:44:05 PM PDT 24
Peak memory 199944 kb
Host smart-76870806-88cd-439b-bc94-99d1de2456d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686804756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1686804756
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1693795254
Short name T930
Test name
Test status
Simulation time 107709568138 ps
CPU time 41.96 seconds
Started Jul 04 05:43:04 PM PDT 24
Finished Jul 04 05:43:46 PM PDT 24
Peak memory 199908 kb
Host smart-3d1450a0-9075-44cf-b76c-efaac66c6a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693795254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1693795254
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3790971092
Short name T795
Test name
Test status
Simulation time 39473734814 ps
CPU time 61.52 seconds
Started Jul 04 05:43:02 PM PDT 24
Finished Jul 04 05:44:04 PM PDT 24
Peak memory 199988 kb
Host smart-762b092c-205c-4d34-819c-9a78c72d6b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790971092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3790971092
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3869635393
Short name T1026
Test name
Test status
Simulation time 20209176333 ps
CPU time 32.31 seconds
Started Jul 04 05:43:02 PM PDT 24
Finished Jul 04 05:43:35 PM PDT 24
Peak memory 199908 kb
Host smart-0daa7df8-d31c-4ce1-9044-1c486830ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869635393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3869635393
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.995757189
Short name T489
Test name
Test status
Simulation time 99845688037 ps
CPU time 222.97 seconds
Started Jul 04 05:43:11 PM PDT 24
Finished Jul 04 05:46:55 PM PDT 24
Peak memory 199936 kb
Host smart-be38fa3f-b04f-4f68-b864-797838b59440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995757189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.995757189
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3920400401
Short name T592
Test name
Test status
Simulation time 23518514678 ps
CPU time 19.29 seconds
Started Jul 04 05:43:11 PM PDT 24
Finished Jul 04 05:43:30 PM PDT 24
Peak memory 199920 kb
Host smart-359c9332-f3bd-4c81-9623-1f2d5562e1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920400401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3920400401
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1335823671
Short name T955
Test name
Test status
Simulation time 18655577 ps
CPU time 0.55 seconds
Started Jul 04 05:39:22 PM PDT 24
Finished Jul 04 05:39:23 PM PDT 24
Peak memory 195304 kb
Host smart-2a889c1c-eb4c-46b8-89ce-ca70e453e823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335823671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1335823671
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2794448343
Short name T1101
Test name
Test status
Simulation time 64878794733 ps
CPU time 83.8 seconds
Started Jul 04 05:39:10 PM PDT 24
Finished Jul 04 05:40:34 PM PDT 24
Peak memory 199912 kb
Host smart-75adfe25-4162-4cb7-8eff-b0a11a80d0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794448343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2794448343
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3687474509
Short name T126
Test name
Test status
Simulation time 164982009408 ps
CPU time 35.16 seconds
Started Jul 04 05:39:10 PM PDT 24
Finished Jul 04 05:39:46 PM PDT 24
Peak memory 199952 kb
Host smart-ceed60a2-c33a-4570-8916-18ff7d923f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687474509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3687474509
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.575032684
Short name T186
Test name
Test status
Simulation time 71256921976 ps
CPU time 14.74 seconds
Started Jul 04 05:39:11 PM PDT 24
Finished Jul 04 05:39:26 PM PDT 24
Peak memory 199896 kb
Host smart-2ebbd747-29bf-4133-9e2f-f89da3d70de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575032684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.575032684
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2592405090
Short name T235
Test name
Test status
Simulation time 24632826386 ps
CPU time 11.52 seconds
Started Jul 04 05:39:10 PM PDT 24
Finished Jul 04 05:39:22 PM PDT 24
Peak memory 199964 kb
Host smart-e803a822-4cd9-4596-bfc9-a6d15f55737a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592405090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2592405090
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.98468835
Short name T939
Test name
Test status
Simulation time 98256110139 ps
CPU time 149.94 seconds
Started Jul 04 05:39:10 PM PDT 24
Finished Jul 04 05:41:40 PM PDT 24
Peak memory 199888 kb
Host smart-5255142a-f200-412d-a4a4-dda53df6eef9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98468835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.98468835
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.774358927
Short name T517
Test name
Test status
Simulation time 3553745562 ps
CPU time 20.35 seconds
Started Jul 04 05:39:10 PM PDT 24
Finished Jul 04 05:39:31 PM PDT 24
Peak memory 198668 kb
Host smart-e4442ec8-b85d-4796-a9d1-8774aa2687af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774358927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.774358927
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.141215228
Short name T661
Test name
Test status
Simulation time 50695561450 ps
CPU time 56.55 seconds
Started Jul 04 05:39:09 PM PDT 24
Finished Jul 04 05:40:06 PM PDT 24
Peak memory 200116 kb
Host smart-e001fe23-8608-4752-a687-b150aa421f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141215228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.141215228
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.844579935
Short name T693
Test name
Test status
Simulation time 25701113136 ps
CPU time 1544.29 seconds
Started Jul 04 05:39:11 PM PDT 24
Finished Jul 04 06:04:56 PM PDT 24
Peak memory 199976 kb
Host smart-10baa338-d1f0-4308-9c02-933c944b7f09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=844579935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.844579935
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1086942734
Short name T956
Test name
Test status
Simulation time 3287239421 ps
CPU time 17.16 seconds
Started Jul 04 05:39:12 PM PDT 24
Finished Jul 04 05:39:30 PM PDT 24
Peak memory 199148 kb
Host smart-357be9f6-d278-4892-ad73-3fb3b4a0e0f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086942734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1086942734
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.271872780
Short name T412
Test name
Test status
Simulation time 87199022663 ps
CPU time 71.07 seconds
Started Jul 04 05:39:10 PM PDT 24
Finished Jul 04 05:40:21 PM PDT 24
Peak memory 199936 kb
Host smart-d9cacfdb-20d1-4b4d-acfb-4b14f44fefdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271872780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.271872780
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1372662181
Short name T282
Test name
Test status
Simulation time 38172077117 ps
CPU time 54.26 seconds
Started Jul 04 05:39:11 PM PDT 24
Finished Jul 04 05:40:05 PM PDT 24
Peak memory 196356 kb
Host smart-90de4608-83d5-4c53-b0e3-979a7219402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372662181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1372662181
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2817398838
Short name T439
Test name
Test status
Simulation time 489709414 ps
CPU time 1.85 seconds
Started Jul 04 05:39:11 PM PDT 24
Finished Jul 04 05:39:13 PM PDT 24
Peak memory 198248 kb
Host smart-f67db521-78e4-4ea9-95a1-85eb14355c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817398838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2817398838
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.150864024
Short name T676
Test name
Test status
Simulation time 6231572947 ps
CPU time 32.92 seconds
Started Jul 04 05:39:10 PM PDT 24
Finished Jul 04 05:39:44 PM PDT 24
Peak memory 199248 kb
Host smart-ed724256-213d-4e65-9df0-f49548f1e45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150864024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.150864024
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1712267350
Short name T731
Test name
Test status
Simulation time 149530499351 ps
CPU time 246.6 seconds
Started Jul 04 05:39:08 PM PDT 24
Finished Jul 04 05:43:15 PM PDT 24
Peak memory 199924 kb
Host smart-73bbad7c-ed4a-46f3-97da-3ad00e63aa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712267350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1712267350
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.928375593
Short name T1058
Test name
Test status
Simulation time 58832120506 ps
CPU time 19.53 seconds
Started Jul 04 05:43:12 PM PDT 24
Finished Jul 04 05:43:31 PM PDT 24
Peak memory 199984 kb
Host smart-b4adab0f-5d64-40a4-a21a-6994c391e00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928375593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.928375593
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2839684164
Short name T1115
Test name
Test status
Simulation time 52671123629 ps
CPU time 41.71 seconds
Started Jul 04 05:43:12 PM PDT 24
Finished Jul 04 05:43:54 PM PDT 24
Peak memory 199984 kb
Host smart-33b911f9-d34e-4c5c-b40c-736752b261e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839684164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2839684164
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1125934991
Short name T92
Test name
Test status
Simulation time 85248226904 ps
CPU time 28.12 seconds
Started Jul 04 05:43:10 PM PDT 24
Finished Jul 04 05:43:38 PM PDT 24
Peak memory 199860 kb
Host smart-35fd8c10-f30c-4764-b3f2-b543451d8f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125934991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1125934991
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3340293333
Short name T527
Test name
Test status
Simulation time 71089961920 ps
CPU time 33.15 seconds
Started Jul 04 05:43:20 PM PDT 24
Finished Jul 04 05:43:53 PM PDT 24
Peak memory 199984 kb
Host smart-7454a1ef-fbef-4da2-a7bf-213b7b11e388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340293333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3340293333
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1125181067
Short name T600
Test name
Test status
Simulation time 253513884583 ps
CPU time 88.46 seconds
Started Jul 04 05:43:19 PM PDT 24
Finished Jul 04 05:44:48 PM PDT 24
Peak memory 199968 kb
Host smart-ad3fc10d-a022-44ec-b868-61fed2d1720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125181067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1125181067
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3592290752
Short name T829
Test name
Test status
Simulation time 26321182843 ps
CPU time 16.8 seconds
Started Jul 04 05:43:19 PM PDT 24
Finished Jul 04 05:43:35 PM PDT 24
Peak memory 199928 kb
Host smart-2f850d8c-f2c9-4356-ab2f-1a0be3a6ae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592290752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3592290752
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3961847197
Short name T796
Test name
Test status
Simulation time 113692051872 ps
CPU time 112.55 seconds
Started Jul 04 05:43:19 PM PDT 24
Finished Jul 04 05:45:12 PM PDT 24
Peak memory 199956 kb
Host smart-2e0c04d1-786a-472b-a460-c3414c4373d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961847197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3961847197
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3233145898
Short name T1057
Test name
Test status
Simulation time 114909327078 ps
CPU time 141.55 seconds
Started Jul 04 05:43:20 PM PDT 24
Finished Jul 04 05:45:42 PM PDT 24
Peak memory 199956 kb
Host smart-5d562b9e-c71f-4069-a382-a5548e6d21fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233145898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3233145898
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.4174308075
Short name T378
Test name
Test status
Simulation time 11129814 ps
CPU time 0.58 seconds
Started Jul 04 05:38:15 PM PDT 24
Finished Jul 04 05:38:16 PM PDT 24
Peak memory 195296 kb
Host smart-462f7725-1d08-4151-bcce-de1256af6dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174308075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.4174308075
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.369941171
Short name T128
Test name
Test status
Simulation time 40406937451 ps
CPU time 61.59 seconds
Started Jul 04 05:38:15 PM PDT 24
Finished Jul 04 05:39:17 PM PDT 24
Peak memory 199916 kb
Host smart-01ccf300-4705-45f0-82d4-a2f34ef147ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369941171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.369941171
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3093143339
Short name T1034
Test name
Test status
Simulation time 85993325713 ps
CPU time 134.62 seconds
Started Jul 04 05:38:17 PM PDT 24
Finished Jul 04 05:40:32 PM PDT 24
Peak memory 199880 kb
Host smart-f3c4f7bb-86d9-4b7f-90a5-4eacd261d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093143339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3093143339
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.4096436522
Short name T564
Test name
Test status
Simulation time 29261529674 ps
CPU time 13.88 seconds
Started Jul 04 05:38:16 PM PDT 24
Finished Jul 04 05:38:30 PM PDT 24
Peak memory 199940 kb
Host smart-27f6ee6f-9338-4e81-85c4-4539c670a4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096436522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4096436522
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2129104860
Short name T273
Test name
Test status
Simulation time 37940297084 ps
CPU time 18.7 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:38:32 PM PDT 24
Peak memory 199996 kb
Host smart-4aa8d436-f0db-4412-a782-ae0cb53400b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129104860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2129104860
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1270777464
Short name T1133
Test name
Test status
Simulation time 101721314627 ps
CPU time 370.27 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:44:24 PM PDT 24
Peak memory 199992 kb
Host smart-eec78c9e-1f87-4185-b82d-f6867cbbfa1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1270777464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1270777464
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2542575739
Short name T1002
Test name
Test status
Simulation time 6275687240 ps
CPU time 10.7 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:38:24 PM PDT 24
Peak memory 198604 kb
Host smart-5378bebf-6be6-4536-ab21-9579873ff399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542575739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2542575739
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.803045291
Short name T703
Test name
Test status
Simulation time 81312607842 ps
CPU time 171.73 seconds
Started Jul 04 05:38:17 PM PDT 24
Finished Jul 04 05:41:09 PM PDT 24
Peak memory 200108 kb
Host smart-ffe86017-c9ce-424a-848d-6ef90903f499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803045291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.803045291
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3881685579
Short name T562
Test name
Test status
Simulation time 17749175944 ps
CPU time 98.16 seconds
Started Jul 04 05:38:12 PM PDT 24
Finished Jul 04 05:39:50 PM PDT 24
Peak memory 199996 kb
Host smart-463c17d3-3949-46c8-808b-7f7f37924619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881685579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3881685579
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.851664418
Short name T21
Test name
Test status
Simulation time 6793255218 ps
CPU time 29.15 seconds
Started Jul 04 05:38:20 PM PDT 24
Finished Jul 04 05:38:50 PM PDT 24
Peak memory 198576 kb
Host smart-15390c5a-fba9-4b24-bf9a-823d2c902095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=851664418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.851664418
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1376727943
Short name T545
Test name
Test status
Simulation time 94371678261 ps
CPU time 144.56 seconds
Started Jul 04 05:38:13 PM PDT 24
Finished Jul 04 05:40:38 PM PDT 24
Peak memory 199888 kb
Host smart-bc0950d5-f8a6-4bdb-9614-a07f30347335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376727943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1376727943
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2251833954
Short name T648
Test name
Test status
Simulation time 5721638636 ps
CPU time 2.75 seconds
Started Jul 04 05:38:18 PM PDT 24
Finished Jul 04 05:38:21 PM PDT 24
Peak memory 196076 kb
Host smart-95772437-1253-459d-a2bf-03a6c57d8c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251833954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2251833954
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3514324563
Short name T26
Test name
Test status
Simulation time 72823325 ps
CPU time 0.75 seconds
Started Jul 04 05:38:14 PM PDT 24
Finished Jul 04 05:38:15 PM PDT 24
Peak memory 218156 kb
Host smart-2e19dd73-a0f9-41b1-963d-85594b2f5eaf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514324563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3514324563
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2085536814
Short name T291
Test name
Test status
Simulation time 689535108 ps
CPU time 2.92 seconds
Started Jul 04 05:38:10 PM PDT 24
Finished Jul 04 05:38:13 PM PDT 24
Peak memory 198752 kb
Host smart-d5666b57-9a79-4e86-a648-c016fdfd652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085536814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2085536814
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.4016516447
Short name T127
Test name
Test status
Simulation time 277930656687 ps
CPU time 110.02 seconds
Started Jul 04 05:38:12 PM PDT 24
Finished Jul 04 05:40:02 PM PDT 24
Peak memory 210816 kb
Host smart-ca60246a-35fc-4682-aff5-2971ccaa8d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016516447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4016516447
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.824418620
Short name T1151
Test name
Test status
Simulation time 157073486648 ps
CPU time 572.07 seconds
Started Jul 04 05:38:15 PM PDT 24
Finished Jul 04 05:47:47 PM PDT 24
Peak memory 216472 kb
Host smart-3e42b5a8-5769-4ffa-aa74-d5fb6db0a729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824418620 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.824418620
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.4256451292
Short name T471
Test name
Test status
Simulation time 1405570983 ps
CPU time 1.88 seconds
Started Jul 04 05:38:15 PM PDT 24
Finished Jul 04 05:38:17 PM PDT 24
Peak memory 198528 kb
Host smart-a2ef211f-8a80-4d89-871d-dc7c65e2a0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256451292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.4256451292
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3020201116
Short name T946
Test name
Test status
Simulation time 11885712251 ps
CPU time 10.89 seconds
Started Jul 04 05:38:20 PM PDT 24
Finished Jul 04 05:38:31 PM PDT 24
Peak memory 199896 kb
Host smart-0b363b3f-a0d8-4d2b-a27f-9801e1bcb34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020201116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3020201116
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_fifo_full.870224336
Short name T778
Test name
Test status
Simulation time 156591965092 ps
CPU time 148.41 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:41:47 PM PDT 24
Peak memory 199996 kb
Host smart-f5332469-b271-45c2-be60-6fe1c53d2cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870224336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.870224336
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3539937434
Short name T1142
Test name
Test status
Simulation time 19610192358 ps
CPU time 30.92 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:39:50 PM PDT 24
Peak memory 199976 kb
Host smart-a88c5a8b-bfa3-4a08-accb-40f339e5de32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539937434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3539937434
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1842746817
Short name T846
Test name
Test status
Simulation time 52966852899 ps
CPU time 28.24 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:39:51 PM PDT 24
Peak memory 199916 kb
Host smart-f7d51649-f19c-46c6-805b-84327f4f9f6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842746817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1842746817
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1501943509
Short name T1077
Test name
Test status
Simulation time 59872422945 ps
CPU time 441.38 seconds
Started Jul 04 05:39:21 PM PDT 24
Finished Jul 04 05:46:43 PM PDT 24
Peak memory 199964 kb
Host smart-582e438b-1dbe-48a8-b83d-45564aeff73b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501943509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1501943509
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1997536594
Short name T645
Test name
Test status
Simulation time 2573835153 ps
CPU time 4.11 seconds
Started Jul 04 05:39:21 PM PDT 24
Finished Jul 04 05:39:25 PM PDT 24
Peak memory 196168 kb
Host smart-815353f4-0100-43f6-b2b1-417c5dd44a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997536594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1997536594
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2604890403
Short name T701
Test name
Test status
Simulation time 30484460934 ps
CPU time 20.23 seconds
Started Jul 04 05:39:20 PM PDT 24
Finished Jul 04 05:39:41 PM PDT 24
Peak memory 199224 kb
Host smart-63fedeaf-56d6-4c87-a0e3-0e9f2d378c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604890403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2604890403
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.4231118574
Short name T498
Test name
Test status
Simulation time 12766216192 ps
CPU time 740.37 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:51:40 PM PDT 24
Peak memory 199960 kb
Host smart-023007fd-6afd-4368-8890-c34b3eb19e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231118574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4231118574
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1610200434
Short name T399
Test name
Test status
Simulation time 3975804834 ps
CPU time 32.16 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:39:51 PM PDT 24
Peak memory 199016 kb
Host smart-c9681209-5484-4ee1-85a4-8f068b7968ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610200434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1610200434
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.451853564
Short name T872
Test name
Test status
Simulation time 83200477736 ps
CPU time 56.87 seconds
Started Jul 04 05:39:22 PM PDT 24
Finished Jul 04 05:40:19 PM PDT 24
Peak memory 199836 kb
Host smart-b3f3e528-86a4-4156-ad74-10a9a197a77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451853564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.451853564
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.489327358
Short name T604
Test name
Test status
Simulation time 614650839 ps
CPU time 0.95 seconds
Started Jul 04 05:39:20 PM PDT 24
Finished Jul 04 05:39:21 PM PDT 24
Peak memory 195428 kb
Host smart-bf76f817-2bfd-4312-af0f-72ace51b8cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489327358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.489327358
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3319792403
Short name T768
Test name
Test status
Simulation time 530669142 ps
CPU time 3.99 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:39:23 PM PDT 24
Peak memory 199024 kb
Host smart-c48861f5-417f-40e7-9e52-6c986aeed933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319792403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3319792403
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1190257221
Short name T830
Test name
Test status
Simulation time 170528621253 ps
CPU time 274.44 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:43:54 PM PDT 24
Peak memory 199980 kb
Host smart-0cac7aaf-3d43-436e-95d2-32d12811dbe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190257221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1190257221
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2772597032
Short name T971
Test name
Test status
Simulation time 1606991604 ps
CPU time 2.19 seconds
Started Jul 04 05:39:21 PM PDT 24
Finished Jul 04 05:39:23 PM PDT 24
Peak memory 199856 kb
Host smart-f44d86d2-88f1-4878-bc81-041ac416a466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772597032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2772597032
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.4144263804
Short name T751
Test name
Test status
Simulation time 41117316370 ps
CPU time 10.95 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:39:30 PM PDT 24
Peak memory 200004 kb
Host smart-4f3d8499-844f-40f5-aeda-7d4d3f536206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144263804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.4144263804
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2753070723
Short name T311
Test name
Test status
Simulation time 132473926647 ps
CPU time 52.22 seconds
Started Jul 04 05:43:19 PM PDT 24
Finished Jul 04 05:44:11 PM PDT 24
Peak memory 199808 kb
Host smart-154d0b5c-6a34-49e3-8d2f-c767402dcc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753070723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2753070723
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3415060717
Short name T197
Test name
Test status
Simulation time 65926800203 ps
CPU time 27.52 seconds
Started Jul 04 05:43:19 PM PDT 24
Finished Jul 04 05:43:47 PM PDT 24
Peak memory 199980 kb
Host smart-454a59bf-bd47-4fef-b1c7-63bf392b692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415060717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3415060717
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2389813033
Short name T652
Test name
Test status
Simulation time 25611757954 ps
CPU time 20.01 seconds
Started Jul 04 05:43:29 PM PDT 24
Finished Jul 04 05:43:50 PM PDT 24
Peak memory 199884 kb
Host smart-818edfb1-2fce-46e7-b144-2d912e35858b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389813033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2389813033
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.4234678424
Short name T1051
Test name
Test status
Simulation time 74903749087 ps
CPU time 24.95 seconds
Started Jul 04 05:43:25 PM PDT 24
Finished Jul 04 05:43:51 PM PDT 24
Peak memory 199816 kb
Host smart-ab33a0c7-34a2-4710-8174-c2b745374cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234678424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.4234678424
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2211079162
Short name T1041
Test name
Test status
Simulation time 95300477000 ps
CPU time 63.2 seconds
Started Jul 04 05:43:25 PM PDT 24
Finished Jul 04 05:44:28 PM PDT 24
Peak memory 199916 kb
Host smart-8953882f-3df5-43d7-8d59-da6adfdf02a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211079162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2211079162
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1933761185
Short name T215
Test name
Test status
Simulation time 76086624691 ps
CPU time 29.83 seconds
Started Jul 04 05:43:26 PM PDT 24
Finished Jul 04 05:43:56 PM PDT 24
Peak memory 199896 kb
Host smart-fbbf105e-c57c-44dc-8ba7-b82b6e4ec18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933761185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1933761185
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.947351551
Short name T596
Test name
Test status
Simulation time 29442625996 ps
CPU time 22.17 seconds
Started Jul 04 05:43:25 PM PDT 24
Finished Jul 04 05:43:47 PM PDT 24
Peak memory 199876 kb
Host smart-78e45131-17b2-4b8a-8e75-f5b92724f36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947351551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.947351551
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1556752634
Short name T105
Test name
Test status
Simulation time 13832678028 ps
CPU time 6.85 seconds
Started Jul 04 05:43:27 PM PDT 24
Finished Jul 04 05:43:34 PM PDT 24
Peak memory 199856 kb
Host smart-8fbccdd6-697c-4cf8-9166-5c14f5bd2e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556752634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1556752634
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2679744594
Short name T1170
Test name
Test status
Simulation time 33351494 ps
CPU time 0.61 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:39:24 PM PDT 24
Peak memory 195304 kb
Host smart-64790c9b-59e4-4d5a-a73e-df3d8a065477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679744594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2679744594
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2205877112
Short name T1074
Test name
Test status
Simulation time 113612059358 ps
CPU time 79.96 seconds
Started Jul 04 05:39:18 PM PDT 24
Finished Jul 04 05:40:38 PM PDT 24
Peak memory 199976 kb
Host smart-84b5d3e7-09f0-4262-a98c-722e1dfeb9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205877112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2205877112
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1547677969
Short name T965
Test name
Test status
Simulation time 77165403311 ps
CPU time 20.17 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:39:39 PM PDT 24
Peak memory 199992 kb
Host smart-27197f18-816f-4efc-8e90-3e44cfbd32b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547677969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1547677969
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2318644245
Short name T809
Test name
Test status
Simulation time 9640038737 ps
CPU time 17.72 seconds
Started Jul 04 05:39:20 PM PDT 24
Finished Jul 04 05:39:38 PM PDT 24
Peak memory 199836 kb
Host smart-e9bd8fc9-3e34-4d8b-b12d-bc8f6ab3f6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318644245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2318644245
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1459397327
Short name T18
Test name
Test status
Simulation time 10174154716 ps
CPU time 5.76 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:39:25 PM PDT 24
Peak memory 199560 kb
Host smart-7d6aaba0-ee3d-4774-9491-c210af3eee56
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459397327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1459397327
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.4026961795
Short name T990
Test name
Test status
Simulation time 49297853924 ps
CPU time 64.32 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:40:27 PM PDT 24
Peak memory 199868 kb
Host smart-2946b8b1-446a-4e74-9c39-4a9e42d9cad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026961795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.4026961795
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1019877691
Short name T590
Test name
Test status
Simulation time 5587420946 ps
CPU time 7.85 seconds
Started Jul 04 05:39:25 PM PDT 24
Finished Jul 04 05:39:33 PM PDT 24
Peak memory 199864 kb
Host smart-1a54d4ee-1d5a-4d64-baec-e28d8016250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019877691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1019877691
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3822914358
Short name T669
Test name
Test status
Simulation time 81865610202 ps
CPU time 57.94 seconds
Started Jul 04 05:39:19 PM PDT 24
Finished Jul 04 05:40:17 PM PDT 24
Peak memory 200036 kb
Host smart-8aa256ec-cf6d-47b5-b597-7eff779172ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822914358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3822914358
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2403087840
Short name T915
Test name
Test status
Simulation time 10313313795 ps
CPU time 281.42 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:44:05 PM PDT 24
Peak memory 199940 kb
Host smart-06ec5cb5-39d5-4378-b019-012d86d40dbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403087840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2403087840
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2348834652
Short name T329
Test name
Test status
Simulation time 4013555578 ps
CPU time 17.49 seconds
Started Jul 04 05:39:17 PM PDT 24
Finished Jul 04 05:39:35 PM PDT 24
Peak memory 198048 kb
Host smart-22182392-4d59-42ea-81e6-bd8d3289898a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348834652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2348834652
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2405359451
Short name T960
Test name
Test status
Simulation time 278742168655 ps
CPU time 57.13 seconds
Started Jul 04 05:39:22 PM PDT 24
Finished Jul 04 05:40:20 PM PDT 24
Peak memory 200000 kb
Host smart-fe9e2565-43a8-4afd-b80e-e91d50186d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405359451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2405359451
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1827857433
Short name T470
Test name
Test status
Simulation time 3420174166 ps
CPU time 2.89 seconds
Started Jul 04 05:39:22 PM PDT 24
Finished Jul 04 05:39:25 PM PDT 24
Peak memory 196212 kb
Host smart-f48a1360-09c5-4edb-b18e-3d0b6826e90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827857433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1827857433
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.625740434
Short name T477
Test name
Test status
Simulation time 447852770 ps
CPU time 1.88 seconds
Started Jul 04 05:39:18 PM PDT 24
Finished Jul 04 05:39:20 PM PDT 24
Peak memory 198348 kb
Host smart-8320a71f-c928-40c6-80b8-26dfc377d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625740434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.625740434
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2464482410
Short name T1096
Test name
Test status
Simulation time 108324026043 ps
CPU time 1482.23 seconds
Started Jul 04 05:39:28 PM PDT 24
Finished Jul 04 06:04:10 PM PDT 24
Peak memory 199952 kb
Host smart-b8899946-121b-489d-97ad-f4c61227764f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464482410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2464482410
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3838471027
Short name T41
Test name
Test status
Simulation time 105968854522 ps
CPU time 847.76 seconds
Started Jul 04 05:39:28 PM PDT 24
Finished Jul 04 05:53:36 PM PDT 24
Peak memory 232516 kb
Host smart-8e18292c-1799-47cf-b23f-d87ed90316ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838471027 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3838471027
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3171202723
Short name T582
Test name
Test status
Simulation time 708524023 ps
CPU time 2.69 seconds
Started Jul 04 05:39:18 PM PDT 24
Finished Jul 04 05:39:21 PM PDT 24
Peak memory 198404 kb
Host smart-9bc18a66-e9b9-4326-a3f6-454e44e7fc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171202723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3171202723
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.318088806
Short name T864
Test name
Test status
Simulation time 33689226989 ps
CPU time 51.84 seconds
Started Jul 04 05:39:21 PM PDT 24
Finished Jul 04 05:40:13 PM PDT 24
Peak memory 199988 kb
Host smart-a6d6c116-e2b9-4699-90f2-aacfc603c34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318088806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.318088806
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1341987465
Short name T212
Test name
Test status
Simulation time 22485107677 ps
CPU time 10.2 seconds
Started Jul 04 05:43:25 PM PDT 24
Finished Jul 04 05:43:35 PM PDT 24
Peak memory 199908 kb
Host smart-eeb5a244-f399-41eb-8b66-5a244a0a9f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341987465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1341987465
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2640451996
Short name T1143
Test name
Test status
Simulation time 90395772723 ps
CPU time 38.32 seconds
Started Jul 04 05:43:26 PM PDT 24
Finished Jul 04 05:44:04 PM PDT 24
Peak memory 199920 kb
Host smart-a4800140-8c6a-4900-ac4d-77f40dcfc38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640451996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2640451996
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2098263791
Short name T321
Test name
Test status
Simulation time 26056825455 ps
CPU time 47.44 seconds
Started Jul 04 05:43:26 PM PDT 24
Finished Jul 04 05:44:14 PM PDT 24
Peak memory 199976 kb
Host smart-561ded01-3681-49bd-bd77-e58174ad166d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098263791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2098263791
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3182722244
Short name T34
Test name
Test status
Simulation time 45529951996 ps
CPU time 24.04 seconds
Started Jul 04 05:43:27 PM PDT 24
Finished Jul 04 05:43:51 PM PDT 24
Peak memory 199904 kb
Host smart-36ef1378-40a6-4e6d-8ae5-26fbab9740cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182722244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3182722244
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1294331804
Short name T1131
Test name
Test status
Simulation time 27755824516 ps
CPU time 42.63 seconds
Started Jul 04 05:43:27 PM PDT 24
Finished Jul 04 05:44:10 PM PDT 24
Peak memory 199860 kb
Host smart-659336e3-5bb9-465b-af09-52576b4fb0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294331804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1294331804
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1932242464
Short name T613
Test name
Test status
Simulation time 5834094801 ps
CPU time 5.38 seconds
Started Jul 04 05:43:27 PM PDT 24
Finished Jul 04 05:43:32 PM PDT 24
Peak memory 199944 kb
Host smart-591a6715-8e4c-47e5-b911-6f1f82fdf593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932242464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1932242464
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2963295671
Short name T1165
Test name
Test status
Simulation time 163555867486 ps
CPU time 94.84 seconds
Started Jul 04 05:43:27 PM PDT 24
Finished Jul 04 05:45:02 PM PDT 24
Peak memory 199924 kb
Host smart-fde15e40-d82e-463f-aa9d-4cc99d0a1002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963295671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2963295671
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4067737058
Short name T474
Test name
Test status
Simulation time 46081052429 ps
CPU time 10.56 seconds
Started Jul 04 05:43:29 PM PDT 24
Finished Jul 04 05:43:40 PM PDT 24
Peak memory 199848 kb
Host smart-5f27ffa4-3a31-417b-8a52-952e3648f61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067737058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4067737058
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3709742595
Short name T166
Test name
Test status
Simulation time 41992905839 ps
CPU time 20.99 seconds
Started Jul 04 05:43:29 PM PDT 24
Finished Jul 04 05:43:50 PM PDT 24
Peak memory 199852 kb
Host smart-fd7e23eb-fe57-4008-9713-8e2443825219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709742595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3709742595
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3794540955
Short name T594
Test name
Test status
Simulation time 13654572 ps
CPU time 0.62 seconds
Started Jul 04 05:39:28 PM PDT 24
Finished Jul 04 05:39:28 PM PDT 24
Peak memory 195300 kb
Host smart-33bf5058-6a59-4013-8d72-18f4e299c0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794540955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3794540955
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2349019701
Short name T94
Test name
Test status
Simulation time 62270552104 ps
CPU time 53.97 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:40:17 PM PDT 24
Peak memory 199968 kb
Host smart-d98a8b02-753f-4b73-8db1-629702bcd702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349019701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2349019701
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.506863278
Short name T103
Test name
Test status
Simulation time 21041896820 ps
CPU time 18.84 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:39:42 PM PDT 24
Peak memory 199880 kb
Host smart-119b8005-1042-42cf-885d-63f935733af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506863278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.506863278
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2525446516
Short name T368
Test name
Test status
Simulation time 18758865578 ps
CPU time 26.37 seconds
Started Jul 04 05:39:28 PM PDT 24
Finished Jul 04 05:39:54 PM PDT 24
Peak memory 198420 kb
Host smart-40e6d4df-88b7-43ab-b0d0-cd3a0077ba78
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525446516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2525446516
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.4235184356
Short name T1066
Test name
Test status
Simulation time 113329287905 ps
CPU time 135.98 seconds
Started Jul 04 05:39:24 PM PDT 24
Finished Jul 04 05:41:40 PM PDT 24
Peak memory 199948 kb
Host smart-a4d65666-8aad-4a51-a6fd-2db7e9ae5c91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235184356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.4235184356
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3565941093
Short name T958
Test name
Test status
Simulation time 923769106 ps
CPU time 1.38 seconds
Started Jul 04 05:39:26 PM PDT 24
Finished Jul 04 05:39:27 PM PDT 24
Peak memory 197240 kb
Host smart-befb844b-3c47-4985-94f2-c3487323a5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565941093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3565941093
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3565585109
Short name T504
Test name
Test status
Simulation time 58834367140 ps
CPU time 85.06 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:40:49 PM PDT 24
Peak memory 200128 kb
Host smart-6cd13576-b77d-43f8-858c-ccdc0d37c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565585109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3565585109
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.213923382
Short name T430
Test name
Test status
Simulation time 14783654523 ps
CPU time 200.7 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:42:44 PM PDT 24
Peak memory 199984 kb
Host smart-027b9c36-d377-4e68-85c9-701735f5ab88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213923382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.213923382
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2210529865
Short name T401
Test name
Test status
Simulation time 6060423043 ps
CPU time 13.86 seconds
Started Jul 04 05:39:25 PM PDT 24
Finished Jul 04 05:39:39 PM PDT 24
Peak memory 199164 kb
Host smart-ed3cea31-1fdf-4584-a7e5-62e238297e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210529865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2210529865
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1962057425
Short name T902
Test name
Test status
Simulation time 180918690306 ps
CPU time 168.26 seconds
Started Jul 04 05:39:26 PM PDT 24
Finished Jul 04 05:42:14 PM PDT 24
Peak memory 199708 kb
Host smart-3e57a83e-e2e7-407f-a3f0-4b1d5b860c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962057425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1962057425
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3077777870
Short name T534
Test name
Test status
Simulation time 2212100649 ps
CPU time 2.27 seconds
Started Jul 04 05:39:24 PM PDT 24
Finished Jul 04 05:39:27 PM PDT 24
Peak memory 195520 kb
Host smart-962428c3-e6e4-4cdc-b336-b58f9e400da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077777870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3077777870
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1217805859
Short name T358
Test name
Test status
Simulation time 487018213 ps
CPU time 1.84 seconds
Started Jul 04 05:39:24 PM PDT 24
Finished Jul 04 05:39:26 PM PDT 24
Peak memory 198724 kb
Host smart-d3ee3d3d-7203-4472-925a-01afcc2bee9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217805859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1217805859
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.4284218405
Short name T921
Test name
Test status
Simulation time 134530600143 ps
CPU time 401.74 seconds
Started Jul 04 05:39:22 PM PDT 24
Finished Jul 04 05:46:04 PM PDT 24
Peak memory 200116 kb
Host smart-84ae3e7d-ed7f-4d46-8cf0-b310b805849a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284218405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4284218405
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3119418529
Short name T789
Test name
Test status
Simulation time 2088451495 ps
CPU time 2.7 seconds
Started Jul 04 05:39:24 PM PDT 24
Finished Jul 04 05:39:27 PM PDT 24
Peak memory 198576 kb
Host smart-69c5794b-4aa2-47fa-82e3-bca7b69afccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119418529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3119418529
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3799867614
Short name T755
Test name
Test status
Simulation time 55813779411 ps
CPU time 105.67 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:41:09 PM PDT 24
Peak memory 199948 kb
Host smart-c4f8c8ee-b2ec-491e-a9d2-24a4d8852b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799867614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3799867614
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.236951380
Short name T484
Test name
Test status
Simulation time 92815650229 ps
CPU time 13.65 seconds
Started Jul 04 05:43:26 PM PDT 24
Finished Jul 04 05:43:40 PM PDT 24
Peak memory 199872 kb
Host smart-d0c50700-c385-4c77-b262-bce867ed387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236951380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.236951380
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1223214110
Short name T265
Test name
Test status
Simulation time 99508493801 ps
CPU time 15.92 seconds
Started Jul 04 05:43:26 PM PDT 24
Finished Jul 04 05:43:42 PM PDT 24
Peak memory 199984 kb
Host smart-5ecaa85d-42c2-498a-96cb-d14bc2d4b98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223214110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1223214110
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2267419178
Short name T897
Test name
Test status
Simulation time 11092575394 ps
CPU time 18.61 seconds
Started Jul 04 05:43:33 PM PDT 24
Finished Jul 04 05:43:52 PM PDT 24
Peak memory 199992 kb
Host smart-231a5f01-759c-483c-87f2-2c5249e16cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267419178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2267419178
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1589491690
Short name T563
Test name
Test status
Simulation time 37215632367 ps
CPU time 52.06 seconds
Started Jul 04 05:43:33 PM PDT 24
Finished Jul 04 05:44:25 PM PDT 24
Peak memory 199908 kb
Host smart-02c10630-a3d0-4faf-9ded-1c5e3b040691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589491690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1589491690
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2380668139
Short name T193
Test name
Test status
Simulation time 56855724233 ps
CPU time 49.44 seconds
Started Jul 04 05:43:34 PM PDT 24
Finished Jul 04 05:44:24 PM PDT 24
Peak memory 199984 kb
Host smart-42b3f978-265a-4bd5-86a9-a48465ec8923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380668139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2380668139
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.793522051
Short name T176
Test name
Test status
Simulation time 15342846830 ps
CPU time 20.94 seconds
Started Jul 04 05:43:35 PM PDT 24
Finished Jul 04 05:43:56 PM PDT 24
Peak memory 199660 kb
Host smart-88ef52e4-36a5-4b76-9271-491fd40d58fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793522051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.793522051
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1181424048
Short name T156
Test name
Test status
Simulation time 38240115857 ps
CPU time 32.96 seconds
Started Jul 04 05:43:36 PM PDT 24
Finished Jul 04 05:44:09 PM PDT 24
Peak memory 199916 kb
Host smart-99b20da3-f2dd-4ab6-a937-19e7d9fe2f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181424048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1181424048
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2766973518
Short name T840
Test name
Test status
Simulation time 57738123372 ps
CPU time 68.46 seconds
Started Jul 04 05:43:35 PM PDT 24
Finished Jul 04 05:44:44 PM PDT 24
Peak memory 199968 kb
Host smart-34beb25d-11f8-4fa4-9f88-b4bfca84e6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766973518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2766973518
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2232778754
Short name T177
Test name
Test status
Simulation time 30084585462 ps
CPU time 39.83 seconds
Started Jul 04 05:43:34 PM PDT 24
Finished Jul 04 05:44:14 PM PDT 24
Peak memory 199864 kb
Host smart-daca83ef-985b-4255-93c8-876de86082bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232778754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2232778754
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1915366086
Short name T1063
Test name
Test status
Simulation time 30025660 ps
CPU time 0.57 seconds
Started Jul 04 05:39:31 PM PDT 24
Finished Jul 04 05:39:32 PM PDT 24
Peak memory 195576 kb
Host smart-1e5df33f-37b8-4900-bb07-6bd17b76c5b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915366086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1915366086
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3974559404
Short name T443
Test name
Test status
Simulation time 24261961998 ps
CPU time 5.68 seconds
Started Jul 04 05:39:32 PM PDT 24
Finished Jul 04 05:39:38 PM PDT 24
Peak memory 200000 kb
Host smart-228616ad-c09c-4ead-b4a0-b221f105ac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974559404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3974559404
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3128942055
Short name T271
Test name
Test status
Simulation time 23598878192 ps
CPU time 54.91 seconds
Started Jul 04 05:39:35 PM PDT 24
Finished Jul 04 05:40:30 PM PDT 24
Peak memory 199980 kb
Host smart-0c7e769d-1d88-42dc-8325-08c5ac23cd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128942055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3128942055
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2644002562
Short name T949
Test name
Test status
Simulation time 71918963679 ps
CPU time 42.48 seconds
Started Jul 04 05:39:31 PM PDT 24
Finished Jul 04 05:40:14 PM PDT 24
Peak memory 199960 kb
Host smart-b88a98f1-01e1-4973-b505-eb0100de8d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644002562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2644002562
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.4277982317
Short name T396
Test name
Test status
Simulation time 71004280930 ps
CPU time 29.52 seconds
Started Jul 04 05:39:31 PM PDT 24
Finished Jul 04 05:40:01 PM PDT 24
Peak memory 200016 kb
Host smart-3e41ef2d-35c4-4678-985e-c7b39f6a8a20
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277982317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4277982317
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1101592352
Short name T223
Test name
Test status
Simulation time 140908695470 ps
CPU time 1302.49 seconds
Started Jul 04 05:39:33 PM PDT 24
Finished Jul 04 06:01:16 PM PDT 24
Peak memory 199984 kb
Host smart-1be16992-0054-46c4-b2a8-1eea207662eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101592352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1101592352
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.527497087
Short name T748
Test name
Test status
Simulation time 8822152853 ps
CPU time 4.51 seconds
Started Jul 04 05:39:31 PM PDT 24
Finished Jul 04 05:39:36 PM PDT 24
Peak memory 199304 kb
Host smart-cdfc3a52-bf3c-4a31-9793-9b48e072d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527497087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.527497087
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.84038427
Short name T315
Test name
Test status
Simulation time 37097277068 ps
CPU time 14.83 seconds
Started Jul 04 05:39:32 PM PDT 24
Finished Jul 04 05:39:47 PM PDT 24
Peak memory 194936 kb
Host smart-602799c5-a17d-423b-97a5-9776a73ac03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84038427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.84038427
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.668209413
Short name T299
Test name
Test status
Simulation time 8764642260 ps
CPU time 515.76 seconds
Started Jul 04 05:39:31 PM PDT 24
Finished Jul 04 05:48:07 PM PDT 24
Peak memory 200000 kb
Host smart-274e29c8-0478-4bd4-afb8-f159cbc5e154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668209413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.668209413
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.4242538381
Short name T365
Test name
Test status
Simulation time 4830773457 ps
CPU time 10.94 seconds
Started Jul 04 05:39:30 PM PDT 24
Finished Jul 04 05:39:41 PM PDT 24
Peak memory 197784 kb
Host smart-33a9d05e-5938-460f-bc72-603b2a323d84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4242538381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.4242538381
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3079507914
Short name T603
Test name
Test status
Simulation time 44052999690 ps
CPU time 18.43 seconds
Started Jul 04 05:39:36 PM PDT 24
Finished Jul 04 05:39:55 PM PDT 24
Peak memory 199640 kb
Host smart-c57f3312-5e0f-4575-8a8e-d419c81dac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079507914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3079507914
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3696364135
Short name T1168
Test name
Test status
Simulation time 1824362922 ps
CPU time 3.38 seconds
Started Jul 04 05:39:31 PM PDT 24
Finished Jul 04 05:39:34 PM PDT 24
Peak memory 195340 kb
Host smart-128141fb-26fe-46e7-96f4-92711f3b0c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696364135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3696364135
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1462278299
Short name T366
Test name
Test status
Simulation time 288061737 ps
CPU time 1.34 seconds
Started Jul 04 05:39:23 PM PDT 24
Finished Jul 04 05:39:25 PM PDT 24
Peak memory 198564 kb
Host smart-04fc901b-4927-4f63-b8a8-7b9cc7cbad45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462278299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1462278299
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3710120751
Short name T832
Test name
Test status
Simulation time 463574692010 ps
CPU time 2678.32 seconds
Started Jul 04 05:39:32 PM PDT 24
Finished Jul 04 06:24:11 PM PDT 24
Peak memory 199948 kb
Host smart-a769bb87-c0ab-43d2-90f3-efd5cf78479c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710120751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3710120751
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3329205490
Short name T1141
Test name
Test status
Simulation time 52363984566 ps
CPU time 652.81 seconds
Started Jul 04 05:39:33 PM PDT 24
Finished Jul 04 05:50:26 PM PDT 24
Peak memory 216636 kb
Host smart-686aceed-3a5e-4cb1-86a5-645cf1796c58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329205490 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3329205490
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3551759363
Short name T708
Test name
Test status
Simulation time 6632890784 ps
CPU time 16.23 seconds
Started Jul 04 05:39:31 PM PDT 24
Finished Jul 04 05:39:47 PM PDT 24
Peak memory 199900 kb
Host smart-4dcfbe91-9f97-4741-a83d-57fadf723bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551759363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3551759363
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3405292462
Short name T1159
Test name
Test status
Simulation time 23672266662 ps
CPU time 21.51 seconds
Started Jul 04 05:39:31 PM PDT 24
Finished Jul 04 05:39:53 PM PDT 24
Peak memory 199984 kb
Host smart-f5f53f06-8fa1-4216-ae54-563184ed207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405292462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3405292462
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3622546118
Short name T696
Test name
Test status
Simulation time 17833984279 ps
CPU time 13.01 seconds
Started Jul 04 05:43:32 PM PDT 24
Finished Jul 04 05:43:45 PM PDT 24
Peak memory 199748 kb
Host smart-1e446164-ebbe-4739-81fa-3f7c951444a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622546118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3622546118
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.4114239319
Short name T756
Test name
Test status
Simulation time 42166779087 ps
CPU time 41.45 seconds
Started Jul 04 05:43:31 PM PDT 24
Finished Jul 04 05:44:13 PM PDT 24
Peak memory 199864 kb
Host smart-4d6de4bb-3497-4a1a-b818-a3d44c33e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114239319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.4114239319
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.446024802
Short name T938
Test name
Test status
Simulation time 65074403920 ps
CPU time 101.87 seconds
Started Jul 04 05:43:36 PM PDT 24
Finished Jul 04 05:45:18 PM PDT 24
Peak memory 199844 kb
Host smart-696c3282-788f-41fa-ab79-b482c3a05cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446024802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.446024802
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2789010759
Short name T468
Test name
Test status
Simulation time 112766416958 ps
CPU time 177.48 seconds
Started Jul 04 05:43:34 PM PDT 24
Finished Jul 04 05:46:32 PM PDT 24
Peak memory 199920 kb
Host smart-f82750b4-6f5d-4460-b4fd-ce03f2607610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789010759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2789010759
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1834667120
Short name T814
Test name
Test status
Simulation time 83607725217 ps
CPU time 67.52 seconds
Started Jul 04 05:43:36 PM PDT 24
Finished Jul 04 05:44:44 PM PDT 24
Peak memory 199856 kb
Host smart-325efccb-67be-473a-9032-e038881f60df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834667120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1834667120
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1129524442
Short name T36
Test name
Test status
Simulation time 80326066262 ps
CPU time 44.5 seconds
Started Jul 04 05:43:35 PM PDT 24
Finished Jul 04 05:44:20 PM PDT 24
Peak memory 199972 kb
Host smart-3f289f66-dd93-4511-9414-3cd01958cd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129524442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1129524442
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2745640039
Short name T108
Test name
Test status
Simulation time 40021831563 ps
CPU time 43.38 seconds
Started Jul 04 05:43:44 PM PDT 24
Finished Jul 04 05:44:27 PM PDT 24
Peak memory 199896 kb
Host smart-2cdcef8a-0fb4-4f32-96c6-8d08f52a0faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745640039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2745640039
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2337600590
Short name T1173
Test name
Test status
Simulation time 132212336075 ps
CPU time 252.79 seconds
Started Jul 04 05:43:44 PM PDT 24
Finished Jul 04 05:47:57 PM PDT 24
Peak memory 199944 kb
Host smart-7b4a8257-7119-4570-8791-bf5fe3572f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337600590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2337600590
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.820652711
Short name T1161
Test name
Test status
Simulation time 62683923254 ps
CPU time 47.22 seconds
Started Jul 04 05:43:50 PM PDT 24
Finished Jul 04 05:44:37 PM PDT 24
Peak memory 200016 kb
Host smart-0adb6cdf-46ca-4ac3-a85d-f3ceab8bf944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820652711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.820652711
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.433558782
Short name T344
Test name
Test status
Simulation time 12239684 ps
CPU time 0.6 seconds
Started Jul 04 05:39:36 PM PDT 24
Finished Jul 04 05:39:37 PM PDT 24
Peak memory 195604 kb
Host smart-20ead358-0886-407e-b8e0-4b5b170d026d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433558782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.433558782
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1079051276
Short name T878
Test name
Test status
Simulation time 341861125467 ps
CPU time 212.34 seconds
Started Jul 04 05:39:31 PM PDT 24
Finished Jul 04 05:43:04 PM PDT 24
Peak memory 199964 kb
Host smart-ccea4c7b-6ed9-4e90-8782-77c6d251c034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079051276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1079051276
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1847222523
Short name T298
Test name
Test status
Simulation time 96663975254 ps
CPU time 75.45 seconds
Started Jul 04 05:39:37 PM PDT 24
Finished Jul 04 05:40:53 PM PDT 24
Peak memory 199824 kb
Host smart-713bc5dc-dbef-4644-94c0-dc3902e76074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847222523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1847222523
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2359499400
Short name T1153
Test name
Test status
Simulation time 125892243480 ps
CPU time 49.17 seconds
Started Jul 04 05:39:37 PM PDT 24
Finished Jul 04 05:40:26 PM PDT 24
Peak memory 199964 kb
Host smart-9653d0df-59b0-47f1-9b85-c27044e5075e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359499400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2359499400
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3755966100
Short name T1162
Test name
Test status
Simulation time 14031426177 ps
CPU time 5.66 seconds
Started Jul 04 05:39:37 PM PDT 24
Finished Jul 04 05:39:43 PM PDT 24
Peak memory 196904 kb
Host smart-3e570b0f-7084-4897-8d1c-10bdd7e63423
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755966100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3755966100
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3961403435
Short name T1067
Test name
Test status
Simulation time 112173093652 ps
CPU time 362.24 seconds
Started Jul 04 05:39:40 PM PDT 24
Finished Jul 04 05:45:42 PM PDT 24
Peak memory 199900 kb
Host smart-8b6a64bd-ef24-4cc2-9059-4f40bff05d53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3961403435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3961403435
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1302570398
Short name T532
Test name
Test status
Simulation time 8018135894 ps
CPU time 16.46 seconds
Started Jul 04 05:39:44 PM PDT 24
Finished Jul 04 05:40:00 PM PDT 24
Peak memory 199864 kb
Host smart-73a3ced8-7974-48de-aa6f-2b8bb3c54ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302570398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1302570398
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.937714423
Short name T295
Test name
Test status
Simulation time 51036025968 ps
CPU time 84.92 seconds
Started Jul 04 05:39:36 PM PDT 24
Finished Jul 04 05:41:02 PM PDT 24
Peak memory 200132 kb
Host smart-4c3938df-2610-450b-80c5-9336c88cf003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937714423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.937714423
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1750149548
Short name T31
Test name
Test status
Simulation time 10756407313 ps
CPU time 150.47 seconds
Started Jul 04 05:39:37 PM PDT 24
Finished Jul 04 05:42:08 PM PDT 24
Peak memory 199964 kb
Host smart-6508d88d-d43b-4aa5-bdb2-108d7e03f956
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750149548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1750149548
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3682468327
Short name T883
Test name
Test status
Simulation time 3553828330 ps
CPU time 12.67 seconds
Started Jul 04 05:39:35 PM PDT 24
Finished Jul 04 05:39:48 PM PDT 24
Peak memory 198996 kb
Host smart-2f131ebc-38b3-4f5a-8be1-712d02fbb011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682468327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3682468327
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.600369698
Short name T537
Test name
Test status
Simulation time 30599108580 ps
CPU time 9.53 seconds
Started Jul 04 05:39:38 PM PDT 24
Finished Jul 04 05:39:48 PM PDT 24
Peak memory 199972 kb
Host smart-adc72d8e-f443-49c8-9682-95b905c3e885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600369698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.600369698
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2975938134
Short name T7
Test name
Test status
Simulation time 36854427986 ps
CPU time 29.18 seconds
Started Jul 04 05:39:37 PM PDT 24
Finished Jul 04 05:40:07 PM PDT 24
Peak memory 195956 kb
Host smart-13d3f026-894d-466f-aac8-96305785f676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975938134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2975938134
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3232817612
Short name T1108
Test name
Test status
Simulation time 5551115150 ps
CPU time 6.59 seconds
Started Jul 04 05:39:32 PM PDT 24
Finished Jul 04 05:39:39 PM PDT 24
Peak memory 199936 kb
Host smart-a9fdf26c-ebb5-482a-8be6-301f0fbe122d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232817612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3232817612
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.939250138
Short name T144
Test name
Test status
Simulation time 103756521366 ps
CPU time 1274.92 seconds
Started Jul 04 05:39:37 PM PDT 24
Finished Jul 04 06:00:53 PM PDT 24
Peak memory 216464 kb
Host smart-4930ee45-03e8-45f0-92ff-ac76195254f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939250138 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.939250138
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3236509354
Short name T17
Test name
Test status
Simulation time 1434914186 ps
CPU time 4.35 seconds
Started Jul 04 05:39:39 PM PDT 24
Finished Jul 04 05:39:44 PM PDT 24
Peak memory 199324 kb
Host smart-85f38ee0-7d6c-4034-80bf-0e4653cf93a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236509354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3236509354
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.4068592342
Short name T871
Test name
Test status
Simulation time 26766461803 ps
CPU time 42.43 seconds
Started Jul 04 05:39:36 PM PDT 24
Finished Jul 04 05:40:19 PM PDT 24
Peak memory 199972 kb
Host smart-1b7fd4aa-12ac-4e99-8643-e10a54f44cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068592342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4068592342
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2502073459
Short name T775
Test name
Test status
Simulation time 61198937796 ps
CPU time 24.76 seconds
Started Jul 04 05:43:42 PM PDT 24
Finished Jul 04 05:44:07 PM PDT 24
Peak memory 199884 kb
Host smart-f8539429-b0ed-4334-bf75-a5e5a31a010c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502073459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2502073459
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1745424444
Short name T810
Test name
Test status
Simulation time 6909465999 ps
CPU time 12.42 seconds
Started Jul 04 05:43:44 PM PDT 24
Finished Jul 04 05:43:56 PM PDT 24
Peak memory 199944 kb
Host smart-fac0a3dd-d940-47d5-a30f-80b46a29d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745424444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1745424444
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.364198846
Short name T526
Test name
Test status
Simulation time 16337755706 ps
CPU time 22.8 seconds
Started Jul 04 05:43:40 PM PDT 24
Finished Jul 04 05:44:03 PM PDT 24
Peak memory 199848 kb
Host smart-72a9fa55-48ea-449f-ae06-d11468708c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364198846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.364198846
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.274370695
Short name T1024
Test name
Test status
Simulation time 21626563171 ps
CPU time 24.14 seconds
Started Jul 04 05:43:44 PM PDT 24
Finished Jul 04 05:44:08 PM PDT 24
Peak memory 199964 kb
Host smart-3bf3bea7-118f-4e3a-a53f-5bba9608585d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274370695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.274370695
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.4167607898
Short name T709
Test name
Test status
Simulation time 23443347555 ps
CPU time 48.21 seconds
Started Jul 04 05:43:42 PM PDT 24
Finished Jul 04 05:44:31 PM PDT 24
Peak memory 199988 kb
Host smart-f301dbd7-95cc-445a-b15e-e3c64cf2454b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167607898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4167607898
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.824783214
Short name T923
Test name
Test status
Simulation time 47685419140 ps
CPU time 106.25 seconds
Started Jul 04 05:43:50 PM PDT 24
Finished Jul 04 05:45:36 PM PDT 24
Peak memory 199956 kb
Host smart-bca68d8b-4b98-4137-be58-e582cf730919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824783214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.824783214
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1051943029
Short name T1009
Test name
Test status
Simulation time 50485548296 ps
CPU time 48.84 seconds
Started Jul 04 05:43:49 PM PDT 24
Finished Jul 04 05:44:39 PM PDT 24
Peak memory 199996 kb
Host smart-3f8f5828-01d8-479e-95e6-bf88d1a7cffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051943029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1051943029
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.853193685
Short name T1064
Test name
Test status
Simulation time 174039924395 ps
CPU time 239.42 seconds
Started Jul 04 05:43:45 PM PDT 24
Finished Jul 04 05:47:45 PM PDT 24
Peak memory 199864 kb
Host smart-f0897b1a-9c76-40a5-b8d5-9d349e44ba24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853193685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.853193685
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2121066589
Short name T619
Test name
Test status
Simulation time 88251361327 ps
CPU time 141.55 seconds
Started Jul 04 05:43:42 PM PDT 24
Finished Jul 04 05:46:04 PM PDT 24
Peak memory 199992 kb
Host smart-1e6314b3-9e06-4247-a077-3b35a7b44a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121066589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2121066589
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.638914169
Short name T328
Test name
Test status
Simulation time 24513708 ps
CPU time 0.55 seconds
Started Jul 04 05:39:43 PM PDT 24
Finished Jul 04 05:39:43 PM PDT 24
Peak memory 195624 kb
Host smart-3c8dfd52-d140-48a7-866e-d51bd0f0178f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638914169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.638914169
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.4128210749
Short name T950
Test name
Test status
Simulation time 34249290226 ps
CPU time 25.33 seconds
Started Jul 04 05:39:36 PM PDT 24
Finished Jul 04 05:40:01 PM PDT 24
Peak memory 199888 kb
Host smart-7a2c1a26-4f06-480e-9cf3-c29c52e6c2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128210749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.4128210749
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2734008871
Short name T1070
Test name
Test status
Simulation time 19564306181 ps
CPU time 17.12 seconds
Started Jul 04 05:39:38 PM PDT 24
Finished Jul 04 05:39:55 PM PDT 24
Peak memory 199908 kb
Host smart-45bde5c1-fc28-4077-ad26-67c82e6f5ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734008871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2734008871
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2718493319
Short name T572
Test name
Test status
Simulation time 91629462143 ps
CPU time 78.35 seconds
Started Jul 04 05:39:45 PM PDT 24
Finished Jul 04 05:41:04 PM PDT 24
Peak memory 199996 kb
Host smart-0cf494cd-5c3e-4ae8-99e4-14d09a92f168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718493319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2718493319
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1142717531
Short name T1021
Test name
Test status
Simulation time 58101905036 ps
CPU time 46.06 seconds
Started Jul 04 05:39:38 PM PDT 24
Finished Jul 04 05:40:24 PM PDT 24
Peak memory 199928 kb
Host smart-239590df-eb96-4dd1-aba1-34aae04fa076
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142717531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1142717531
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.231544187
Short name T841
Test name
Test status
Simulation time 106135269028 ps
CPU time 617.26 seconds
Started Jul 04 05:39:45 PM PDT 24
Finished Jul 04 05:50:02 PM PDT 24
Peak memory 199884 kb
Host smart-53aaf559-ef78-44c9-93db-746764ce1b61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231544187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.231544187
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3414590604
Short name T571
Test name
Test status
Simulation time 1301127963 ps
CPU time 2.25 seconds
Started Jul 04 05:39:41 PM PDT 24
Finished Jul 04 05:39:43 PM PDT 24
Peak memory 195396 kb
Host smart-a87f3680-d344-4ae5-8ea5-34077bc169e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414590604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3414590604
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3198036971
Short name T1097
Test name
Test status
Simulation time 31669636668 ps
CPU time 47.97 seconds
Started Jul 04 05:39:39 PM PDT 24
Finished Jul 04 05:40:27 PM PDT 24
Peak memory 200128 kb
Host smart-92124cd7-448b-4f46-bc67-a7ce2a099715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198036971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3198036971
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3203444982
Short name T257
Test name
Test status
Simulation time 20522033731 ps
CPU time 210.24 seconds
Started Jul 04 05:39:45 PM PDT 24
Finished Jul 04 05:43:15 PM PDT 24
Peak memory 200000 kb
Host smart-ffc9498b-ab40-4e10-a405-e138b473b6af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203444982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3203444982
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1883434010
Short name T622
Test name
Test status
Simulation time 2047948346 ps
CPU time 1.89 seconds
Started Jul 04 05:39:38 PM PDT 24
Finished Jul 04 05:39:40 PM PDT 24
Peak memory 198004 kb
Host smart-386bd329-29a9-4b67-88b8-70800b2d667a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883434010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1883434010
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1832992312
Short name T587
Test name
Test status
Simulation time 150903564606 ps
CPU time 189.55 seconds
Started Jul 04 05:39:37 PM PDT 24
Finished Jul 04 05:42:47 PM PDT 24
Peak memory 200008 kb
Host smart-b2a70e9c-28b5-4a74-b829-1b868bdc21d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832992312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1832992312
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3284512480
Short name T941
Test name
Test status
Simulation time 1610270806 ps
CPU time 2.19 seconds
Started Jul 04 05:39:37 PM PDT 24
Finished Jul 04 05:39:40 PM PDT 24
Peak memory 195436 kb
Host smart-ba989037-83d0-453e-a165-11987f1bc46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284512480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3284512480
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3632784296
Short name T909
Test name
Test status
Simulation time 5311570163 ps
CPU time 8.03 seconds
Started Jul 04 05:39:37 PM PDT 24
Finished Jul 04 05:39:45 PM PDT 24
Peak memory 199732 kb
Host smart-8d28a6bd-4eaa-4e91-84c1-f2b479ec7725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632784296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3632784296
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2802708080
Short name T181
Test name
Test status
Simulation time 162506275138 ps
CPU time 63.84 seconds
Started Jul 04 05:39:49 PM PDT 24
Finished Jul 04 05:40:53 PM PDT 24
Peak memory 199956 kb
Host smart-680a1f1b-694f-42b5-9470-8294333f4468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802708080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2802708080
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3165187654
Short name T932
Test name
Test status
Simulation time 13292166046 ps
CPU time 146.41 seconds
Started Jul 04 05:39:44 PM PDT 24
Finished Jul 04 05:42:11 PM PDT 24
Peak memory 215524 kb
Host smart-065d4f5d-1133-4c90-b498-d81259e8a3bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165187654 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3165187654
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2996217270
Short name T658
Test name
Test status
Simulation time 6493234036 ps
CPU time 29.99 seconds
Started Jul 04 05:39:37 PM PDT 24
Finished Jul 04 05:40:08 PM PDT 24
Peak memory 200000 kb
Host smart-53985fb2-522c-472f-b704-36a6c79d9ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996217270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2996217270
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.364350398
Short name T828
Test name
Test status
Simulation time 111795575597 ps
CPU time 97.09 seconds
Started Jul 04 05:39:35 PM PDT 24
Finished Jul 04 05:41:13 PM PDT 24
Peak memory 199904 kb
Host smart-6a42938d-8f45-477c-ac8e-e465b9d8f23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364350398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.364350398
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2567947764
Short name T134
Test name
Test status
Simulation time 170321661576 ps
CPU time 167.26 seconds
Started Jul 04 05:43:49 PM PDT 24
Finished Jul 04 05:46:37 PM PDT 24
Peak memory 199964 kb
Host smart-34343a6f-fe7d-4228-81a0-7193b55361a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567947764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2567947764
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1860756863
Short name T122
Test name
Test status
Simulation time 33771284288 ps
CPU time 16.04 seconds
Started Jul 04 05:43:44 PM PDT 24
Finished Jul 04 05:44:00 PM PDT 24
Peak memory 199996 kb
Host smart-17592cc6-47b5-4165-88d1-e8841ea9660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860756863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1860756863
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4114546289
Short name T185
Test name
Test status
Simulation time 6168026716 ps
CPU time 10.56 seconds
Started Jul 04 05:43:49 PM PDT 24
Finished Jul 04 05:44:00 PM PDT 24
Peak memory 199732 kb
Host smart-4648b841-934c-4c43-806a-0ac7e0e30a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114546289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4114546289
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3918424909
Short name T944
Test name
Test status
Simulation time 61759730325 ps
CPU time 24.87 seconds
Started Jul 04 05:43:45 PM PDT 24
Finished Jul 04 05:44:10 PM PDT 24
Peak memory 199888 kb
Host smart-2f678108-16b3-42ac-a631-8b70eee0d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918424909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3918424909
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3045122373
Short name T577
Test name
Test status
Simulation time 64207290020 ps
CPU time 36.37 seconds
Started Jul 04 05:43:41 PM PDT 24
Finished Jul 04 05:44:18 PM PDT 24
Peak memory 199924 kb
Host smart-3e384ba7-caa6-4d17-bd1e-fc3a89c7a02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045122373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3045122373
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2103290854
Short name T162
Test name
Test status
Simulation time 17515947632 ps
CPU time 29.15 seconds
Started Jul 04 05:43:49 PM PDT 24
Finished Jul 04 05:44:18 PM PDT 24
Peak memory 199980 kb
Host smart-a7fdb8f1-a2cf-4c45-a167-1941ca74e8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103290854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2103290854
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.564313092
Short name T698
Test name
Test status
Simulation time 98245055685 ps
CPU time 70.54 seconds
Started Jul 04 05:43:50 PM PDT 24
Finished Jul 04 05:45:00 PM PDT 24
Peak memory 199940 kb
Host smart-2d210064-a4d0-4bb5-bd3b-e605f0ebc325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564313092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.564313092
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3875182414
Short name T419
Test name
Test status
Simulation time 180892667541 ps
CPU time 42.13 seconds
Started Jul 04 05:43:49 PM PDT 24
Finished Jul 04 05:44:32 PM PDT 24
Peak memory 199928 kb
Host smart-29201d31-b4f9-48af-9324-4dce1ead87cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875182414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3875182414
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3361022108
Short name T1106
Test name
Test status
Simulation time 89805900465 ps
CPU time 31.44 seconds
Started Jul 04 05:43:50 PM PDT 24
Finished Jul 04 05:44:22 PM PDT 24
Peak memory 199964 kb
Host smart-10f9037f-341a-4407-90e6-903b54b06e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361022108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3361022108
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3768200592
Short name T655
Test name
Test status
Simulation time 12709941 ps
CPU time 0.55 seconds
Started Jul 04 05:39:50 PM PDT 24
Finished Jul 04 05:39:50 PM PDT 24
Peak memory 194564 kb
Host smart-56b9db9a-1ec3-4ef3-965a-ef23724a415c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768200592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3768200592
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3560544295
Short name T1105
Test name
Test status
Simulation time 48717722945 ps
CPU time 105.3 seconds
Started Jul 04 05:39:44 PM PDT 24
Finished Jul 04 05:41:30 PM PDT 24
Peak memory 199972 kb
Host smart-4baf4186-8d45-4fe2-8619-489b63c75ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560544295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3560544295
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.417476160
Short name T870
Test name
Test status
Simulation time 115431935231 ps
CPU time 152.06 seconds
Started Jul 04 05:39:44 PM PDT 24
Finished Jul 04 05:42:16 PM PDT 24
Peak memory 199900 kb
Host smart-3660fe0a-9c24-40a8-b18d-56bc986e5d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417476160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.417476160
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3971100033
Short name T685
Test name
Test status
Simulation time 357479496847 ps
CPU time 28.69 seconds
Started Jul 04 05:39:44 PM PDT 24
Finished Jul 04 05:40:13 PM PDT 24
Peak memory 199928 kb
Host smart-4ce7bebc-c326-4836-90a5-c3197c3071e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971100033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3971100033
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3795715367
Short name T653
Test name
Test status
Simulation time 7364297367 ps
CPU time 7.12 seconds
Started Jul 04 05:39:44 PM PDT 24
Finished Jul 04 05:39:52 PM PDT 24
Peak memory 199936 kb
Host smart-d90c68e0-a33e-46f9-8189-50232dd34a2a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795715367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3795715367
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3751375319
Short name T525
Test name
Test status
Simulation time 75821997106 ps
CPU time 348.3 seconds
Started Jul 04 05:39:43 PM PDT 24
Finished Jul 04 05:45:31 PM PDT 24
Peak memory 199904 kb
Host smart-4db8e38b-1472-4d7d-9454-b51448c351c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751375319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3751375319
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.4135227287
Short name T326
Test name
Test status
Simulation time 7283504622 ps
CPU time 9.95 seconds
Started Jul 04 05:39:48 PM PDT 24
Finished Jul 04 05:39:58 PM PDT 24
Peak memory 199528 kb
Host smart-51bbb09a-d40f-48ee-9afa-ae481f74a8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135227287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4135227287
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1408185762
Short name T438
Test name
Test status
Simulation time 36501927062 ps
CPU time 14.53 seconds
Started Jul 04 05:39:42 PM PDT 24
Finished Jul 04 05:39:57 PM PDT 24
Peak memory 194572 kb
Host smart-0e4b5bf6-1540-4fdc-aaf0-076eea942f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408185762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1408185762
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1176289762
Short name T397
Test name
Test status
Simulation time 4781310676 ps
CPU time 140.06 seconds
Started Jul 04 05:39:44 PM PDT 24
Finished Jul 04 05:42:04 PM PDT 24
Peak memory 199996 kb
Host smart-6dec0c1a-d942-411e-bd17-b7cfa071ed84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176289762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1176289762
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3644278636
Short name T356
Test name
Test status
Simulation time 5467935697 ps
CPU time 21.27 seconds
Started Jul 04 05:39:47 PM PDT 24
Finished Jul 04 05:40:09 PM PDT 24
Peak memory 199300 kb
Host smart-05adb481-554b-4ac4-98d7-89af03082128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3644278636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3644278636
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3381234660
Short name T551
Test name
Test status
Simulation time 32126498774 ps
CPU time 13.2 seconds
Started Jul 04 05:39:45 PM PDT 24
Finished Jul 04 05:39:58 PM PDT 24
Peak memory 199788 kb
Host smart-b0a456da-6fa0-4107-ad00-80333fdd4a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381234660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3381234660
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1293030933
Short name T660
Test name
Test status
Simulation time 3314449693 ps
CPU time 5 seconds
Started Jul 04 05:39:44 PM PDT 24
Finished Jul 04 05:39:50 PM PDT 24
Peak memory 195988 kb
Host smart-444ea831-5422-490f-82d6-6f22720a3eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293030933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1293030933
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.4178491723
Short name T1139
Test name
Test status
Simulation time 560983684 ps
CPU time 2.26 seconds
Started Jul 04 05:39:48 PM PDT 24
Finished Jul 04 05:39:50 PM PDT 24
Peak memory 198672 kb
Host smart-3d25476d-09b3-4cea-950e-8e0d5c455993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178491723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4178491723
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.718216470
Short name T970
Test name
Test status
Simulation time 147097588313 ps
CPU time 344.91 seconds
Started Jul 04 05:39:51 PM PDT 24
Finished Jul 04 05:45:36 PM PDT 24
Peak memory 215928 kb
Host smart-2d1b6b89-9670-439c-a8a4-3b6383ec66c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718216470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.718216470
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3509634751
Short name T692
Test name
Test status
Simulation time 262639190329 ps
CPU time 995 seconds
Started Jul 04 05:39:48 PM PDT 24
Finished Jul 04 05:56:23 PM PDT 24
Peak memory 225584 kb
Host smart-7cc8ebaf-d389-40c0-9f46-c7d410d132f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509634751 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3509634751
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1242833574
Short name T1116
Test name
Test status
Simulation time 1903353923 ps
CPU time 1.5 seconds
Started Jul 04 05:39:44 PM PDT 24
Finished Jul 04 05:39:46 PM PDT 24
Peak memory 199080 kb
Host smart-25e0e8c1-175e-428f-9c74-51e504e8da7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242833574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1242833574
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2395300473
Short name T1072
Test name
Test status
Simulation time 60486087672 ps
CPU time 24.83 seconds
Started Jul 04 05:39:44 PM PDT 24
Finished Jul 04 05:40:09 PM PDT 24
Peak memory 199912 kb
Host smart-55235b28-72f9-4752-b1bf-3c25d30bd7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395300473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2395300473
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.267720321
Short name T1158
Test name
Test status
Simulation time 39080751366 ps
CPU time 16.2 seconds
Started Jul 04 05:43:48 PM PDT 24
Finished Jul 04 05:44:05 PM PDT 24
Peak memory 199964 kb
Host smart-869ff414-181c-4b69-a2e3-cc3b74976505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267720321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.267720321
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3422430111
Short name T1044
Test name
Test status
Simulation time 37935209336 ps
CPU time 17.62 seconds
Started Jul 04 05:43:50 PM PDT 24
Finished Jul 04 05:44:08 PM PDT 24
Peak memory 199876 kb
Host smart-8427e996-458c-442f-ab4a-f84c87a94c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422430111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3422430111
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.798326352
Short name T145
Test name
Test status
Simulation time 132568777903 ps
CPU time 154.58 seconds
Started Jul 04 05:43:50 PM PDT 24
Finished Jul 04 05:46:25 PM PDT 24
Peak memory 199892 kb
Host smart-78e3f124-6f6f-49ac-bc1b-a7148dabdc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798326352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.798326352
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1689412450
Short name T978
Test name
Test status
Simulation time 101291042488 ps
CPU time 18.81 seconds
Started Jul 04 05:43:48 PM PDT 24
Finished Jul 04 05:44:07 PM PDT 24
Peak memory 199948 kb
Host smart-7e52b76e-bebd-4b3a-8093-9e6a7de843c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689412450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1689412450
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.697959717
Short name T973
Test name
Test status
Simulation time 139539629434 ps
CPU time 117.22 seconds
Started Jul 04 05:43:50 PM PDT 24
Finished Jul 04 05:45:47 PM PDT 24
Peak memory 199976 kb
Host smart-2b42b9c4-881d-49f1-a7b3-4d8f4b5175e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697959717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.697959717
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1201572436
Short name T1092
Test name
Test status
Simulation time 41669551975 ps
CPU time 64.03 seconds
Started Jul 04 05:43:50 PM PDT 24
Finished Jul 04 05:44:54 PM PDT 24
Peak memory 199924 kb
Host smart-a5e999ec-b991-435e-87e0-59bde74ac81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201572436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1201572436
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.4008559839
Short name T561
Test name
Test status
Simulation time 99140209121 ps
CPU time 52.93 seconds
Started Jul 04 05:43:48 PM PDT 24
Finished Jul 04 05:44:41 PM PDT 24
Peak memory 199964 kb
Host smart-902c4b69-d793-4c94-9e45-e8cdbb182a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008559839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.4008559839
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2315056994
Short name T705
Test name
Test status
Simulation time 114144049731 ps
CPU time 44.45 seconds
Started Jul 04 05:43:48 PM PDT 24
Finished Jul 04 05:44:33 PM PDT 24
Peak memory 199988 kb
Host smart-df7cb429-8966-45a7-af7a-14005829da58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315056994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2315056994
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4164967348
Short name T977
Test name
Test status
Simulation time 13950832 ps
CPU time 0.55 seconds
Started Jul 04 05:39:52 PM PDT 24
Finished Jul 04 05:39:53 PM PDT 24
Peak memory 194584 kb
Host smart-9d63da37-2d91-489c-ac70-e0d61128dd75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164967348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4164967348
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.136910738
Short name T689
Test name
Test status
Simulation time 9725016391 ps
CPU time 3.63 seconds
Started Jul 04 05:39:51 PM PDT 24
Finished Jul 04 05:39:55 PM PDT 24
Peak memory 199832 kb
Host smart-2a135c03-5179-4e23-838a-665450e6183e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136910738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.136910738
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.471966218
Short name T6
Test name
Test status
Simulation time 131663443560 ps
CPU time 103.35 seconds
Started Jul 04 05:39:51 PM PDT 24
Finished Jul 04 05:41:35 PM PDT 24
Peak memory 199984 kb
Host smart-83500387-d343-4284-84e2-691bb9895a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471966218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.471966218
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2589234417
Short name T1076
Test name
Test status
Simulation time 77016792833 ps
CPU time 279.1 seconds
Started Jul 04 05:39:51 PM PDT 24
Finished Jul 04 05:44:31 PM PDT 24
Peak memory 199876 kb
Host smart-bccc5680-321c-4578-b9cd-0f3bc37bacc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589234417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2589234417
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2139876486
Short name T95
Test name
Test status
Simulation time 36482138032 ps
CPU time 19.93 seconds
Started Jul 04 05:39:52 PM PDT 24
Finished Jul 04 05:40:12 PM PDT 24
Peak memory 199996 kb
Host smart-5706d15d-b140-4d9d-bb02-23503ae31e67
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139876486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2139876486
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.834643486
Short name T772
Test name
Test status
Simulation time 77108130566 ps
CPU time 114.6 seconds
Started Jul 04 05:39:52 PM PDT 24
Finished Jul 04 05:41:47 PM PDT 24
Peak memory 199940 kb
Host smart-016d343d-a1f2-4e33-b499-370deff62ab9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834643486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.834643486
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3222119786
Short name T754
Test name
Test status
Simulation time 4879265452 ps
CPU time 8.99 seconds
Started Jul 04 05:39:50 PM PDT 24
Finished Jul 04 05:39:59 PM PDT 24
Peak memory 199652 kb
Host smart-ed0dc92f-2fc6-4cad-b645-8bd94695b117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222119786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3222119786
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.421509966
Short name T381
Test name
Test status
Simulation time 20170184823 ps
CPU time 259.51 seconds
Started Jul 04 05:39:52 PM PDT 24
Finished Jul 04 05:44:11 PM PDT 24
Peak memory 199976 kb
Host smart-b3383651-acfe-4758-a1a3-4f7c99059c98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421509966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.421509966
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.88586937
Short name T335
Test name
Test status
Simulation time 2125135917 ps
CPU time 3.41 seconds
Started Jul 04 05:39:51 PM PDT 24
Finished Jul 04 05:39:55 PM PDT 24
Peak memory 198328 kb
Host smart-9124fc56-1540-4cc4-ae8d-15c19e11333f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88586937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.88586937
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.572911406
Short name T851
Test name
Test status
Simulation time 58455559269 ps
CPU time 92.99 seconds
Started Jul 04 05:39:53 PM PDT 24
Finished Jul 04 05:41:26 PM PDT 24
Peak memory 199996 kb
Host smart-c79ba86d-f2e2-4d9e-9254-bfc47294ed1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572911406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.572911406
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.697676807
Short name T1135
Test name
Test status
Simulation time 37184730828 ps
CPU time 14.42 seconds
Started Jul 04 05:39:50 PM PDT 24
Finished Jul 04 05:40:05 PM PDT 24
Peak memory 196084 kb
Host smart-9498a33e-aa63-4a9d-93a2-4f49052d6eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697676807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.697676807
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1042747549
Short name T855
Test name
Test status
Simulation time 769261158 ps
CPU time 1.62 seconds
Started Jul 04 05:39:50 PM PDT 24
Finished Jul 04 05:39:52 PM PDT 24
Peak memory 198416 kb
Host smart-0b513c4f-b8ae-41bb-91f2-9ce3d16daccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042747549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1042747549
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3706444276
Short name T845
Test name
Test status
Simulation time 152993713206 ps
CPU time 91.26 seconds
Started Jul 04 05:39:52 PM PDT 24
Finished Jul 04 05:41:23 PM PDT 24
Peak memory 199848 kb
Host smart-c598ad10-f018-49f2-89a5-2ceca21d2902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706444276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3706444276
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2243075921
Short name T437
Test name
Test status
Simulation time 132280439029 ps
CPU time 295.23 seconds
Started Jul 04 05:39:51 PM PDT 24
Finished Jul 04 05:44:47 PM PDT 24
Peak memory 214772 kb
Host smart-e4db5849-9adc-48de-b007-7bd51896a6f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243075921 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2243075921
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.433143304
Short name T280
Test name
Test status
Simulation time 7237088892 ps
CPU time 10.45 seconds
Started Jul 04 05:39:53 PM PDT 24
Finished Jul 04 05:40:04 PM PDT 24
Peak memory 199940 kb
Host smart-493d3e25-1a02-490b-b947-48bdd6c94e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433143304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.433143304
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4263830349
Short name T558
Test name
Test status
Simulation time 90153300910 ps
CPU time 77.21 seconds
Started Jul 04 05:39:51 PM PDT 24
Finished Jul 04 05:41:08 PM PDT 24
Peak memory 199980 kb
Host smart-765b7de0-927e-411b-af86-6ed2f6163959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263830349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4263830349
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2589927755
Short name T641
Test name
Test status
Simulation time 128318414302 ps
CPU time 142.94 seconds
Started Jul 04 05:43:48 PM PDT 24
Finished Jul 04 05:46:11 PM PDT 24
Peak memory 200008 kb
Host smart-2a0279ea-cfd3-4532-98a9-6c6e226b44e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589927755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2589927755
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2832946267
Short name T263
Test name
Test status
Simulation time 119684846070 ps
CPU time 42.42 seconds
Started Jul 04 05:43:47 PM PDT 24
Finished Jul 04 05:44:30 PM PDT 24
Peak memory 199824 kb
Host smart-d783de57-3b76-4abc-941c-458b64c3bda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832946267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2832946267
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2874727667
Short name T1036
Test name
Test status
Simulation time 74291607205 ps
CPU time 109.94 seconds
Started Jul 04 05:43:50 PM PDT 24
Finished Jul 04 05:45:40 PM PDT 24
Peak memory 199904 kb
Host smart-3d442e21-d305-443b-920a-cded793c1436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874727667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2874727667
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1699550909
Short name T952
Test name
Test status
Simulation time 145638936706 ps
CPU time 190.9 seconds
Started Jul 04 05:43:57 PM PDT 24
Finished Jul 04 05:47:08 PM PDT 24
Peak memory 199920 kb
Host smart-deff9938-61e5-4d8a-a473-1d4ecb53be28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699550909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1699550909
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1482871574
Short name T161
Test name
Test status
Simulation time 171732357403 ps
CPU time 40.51 seconds
Started Jul 04 05:43:56 PM PDT 24
Finished Jul 04 05:44:37 PM PDT 24
Peak memory 199980 kb
Host smart-49aca67e-9fcf-4aee-8ccc-81611e7cb070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482871574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1482871574
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1539253261
Short name T189
Test name
Test status
Simulation time 14735899324 ps
CPU time 14.61 seconds
Started Jul 04 05:43:57 PM PDT 24
Finished Jul 04 05:44:12 PM PDT 24
Peak memory 199992 kb
Host smart-cd83574a-8e50-461a-9145-3631ff0b5aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539253261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1539253261
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.773604338
Short name T773
Test name
Test status
Simulation time 105208261032 ps
CPU time 26.68 seconds
Started Jul 04 05:43:58 PM PDT 24
Finished Jul 04 05:44:25 PM PDT 24
Peak memory 199896 kb
Host smart-26fdfdd7-a6fb-40d4-aca8-fec820878ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773604338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.773604338
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1284406160
Short name T630
Test name
Test status
Simulation time 6475272272 ps
CPU time 14.82 seconds
Started Jul 04 05:43:57 PM PDT 24
Finished Jul 04 05:44:12 PM PDT 24
Peak memory 199920 kb
Host smart-04b2323d-5fe1-4d38-bda4-13f501ef0702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284406160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1284406160
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.4375925
Short name T200
Test name
Test status
Simulation time 222465475619 ps
CPU time 138.51 seconds
Started Jul 04 05:44:05 PM PDT 24
Finished Jul 04 05:46:24 PM PDT 24
Peak memory 199584 kb
Host smart-d236b64f-98cf-4f53-a5c5-b074ab047cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4375925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.4375925
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.7131297
Short name T636
Test name
Test status
Simulation time 23765893339 ps
CPU time 36.77 seconds
Started Jul 04 05:44:05 PM PDT 24
Finished Jul 04 05:44:42 PM PDT 24
Peak memory 199684 kb
Host smart-fb09593f-8bf6-4cdc-a17b-f42d7ecb154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7131297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.7131297
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1106740203
Short name T761
Test name
Test status
Simulation time 35158563 ps
CPU time 0.55 seconds
Started Jul 04 05:39:59 PM PDT 24
Finished Jul 04 05:39:59 PM PDT 24
Peak memory 194260 kb
Host smart-9d034ca0-b458-40ba-bf56-3a9f2d1d455b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106740203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1106740203
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1028289732
Short name T836
Test name
Test status
Simulation time 36976995200 ps
CPU time 26.16 seconds
Started Jul 04 05:39:51 PM PDT 24
Finished Jul 04 05:40:18 PM PDT 24
Peak memory 199912 kb
Host smart-d2e14719-aad4-4e88-8ae5-a194734ad32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028289732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1028289732
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.514443579
Short name T1065
Test name
Test status
Simulation time 13422320330 ps
CPU time 18.57 seconds
Started Jul 04 05:39:51 PM PDT 24
Finished Jul 04 05:40:10 PM PDT 24
Peak memory 199612 kb
Host smart-93e1a78f-7764-4ed4-a70f-4a8511265e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514443579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.514443579
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.453343593
Short name T541
Test name
Test status
Simulation time 206422000173 ps
CPU time 41.3 seconds
Started Jul 04 05:39:49 PM PDT 24
Finished Jul 04 05:40:31 PM PDT 24
Peak memory 199804 kb
Host smart-4f55ed8a-ca8d-4174-aab4-b344735235de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453343593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.453343593
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.396982441
Short name T856
Test name
Test status
Simulation time 241232843000 ps
CPU time 508.73 seconds
Started Jul 04 05:40:01 PM PDT 24
Finished Jul 04 05:48:30 PM PDT 24
Peak memory 199604 kb
Host smart-68300d9b-2947-4984-b5a4-2e9971d5548f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396982441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.396982441
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3156904992
Short name T926
Test name
Test status
Simulation time 96184718170 ps
CPU time 192.59 seconds
Started Jul 04 05:40:00 PM PDT 24
Finished Jul 04 05:43:13 PM PDT 24
Peak memory 199776 kb
Host smart-0d1ddf5e-5796-4fee-b48e-297d2c80e111
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156904992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3156904992
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.600015780
Short name T890
Test name
Test status
Simulation time 13161689992 ps
CPU time 5.57 seconds
Started Jul 04 05:40:01 PM PDT 24
Finished Jul 04 05:40:07 PM PDT 24
Peak memory 198836 kb
Host smart-dbeb1026-7ff5-4b88-be25-0eec3129b629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600015780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.600015780
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2535484659
Short name T659
Test name
Test status
Simulation time 302924647299 ps
CPU time 65.98 seconds
Started Jul 04 05:39:59 PM PDT 24
Finished Jul 04 05:41:05 PM PDT 24
Peak memory 200196 kb
Host smart-9373f290-dcb1-49a7-825c-f65945d3d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535484659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2535484659
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1284914182
Short name T740
Test name
Test status
Simulation time 8787950629 ps
CPU time 523.14 seconds
Started Jul 04 05:39:59 PM PDT 24
Finished Jul 04 05:48:43 PM PDT 24
Peak memory 199948 kb
Host smart-b31619ca-693e-45b3-8263-cb88e2af7b0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1284914182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1284914182
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2331333334
Short name T531
Test name
Test status
Simulation time 2428961804 ps
CPU time 1.49 seconds
Started Jul 04 05:39:59 PM PDT 24
Finished Jul 04 05:40:01 PM PDT 24
Peak memory 199144 kb
Host smart-067a1ddb-7af5-4281-9f77-e5210131f566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331333334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2331333334
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3538085363
Short name T727
Test name
Test status
Simulation time 165319849916 ps
CPU time 52.52 seconds
Started Jul 04 05:40:01 PM PDT 24
Finished Jul 04 05:40:53 PM PDT 24
Peak memory 199908 kb
Host smart-8cc92a58-1e4b-40c1-a3fe-fe3c6dd94ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538085363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3538085363
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1921934263
Short name T426
Test name
Test status
Simulation time 2100804701 ps
CPU time 1.61 seconds
Started Jul 04 05:40:01 PM PDT 24
Finished Jul 04 05:40:03 PM PDT 24
Peak memory 195396 kb
Host smart-5e2a5c96-24d3-4cce-86a5-4289ecb12d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921934263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1921934263
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.4162659372
Short name T488
Test name
Test status
Simulation time 5992969641 ps
CPU time 21.52 seconds
Started Jul 04 05:39:50 PM PDT 24
Finished Jul 04 05:40:12 PM PDT 24
Peak memory 199936 kb
Host smart-c10be88d-10b7-48d3-88a7-331bce644428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162659372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4162659372
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.71885967
Short name T1055
Test name
Test status
Simulation time 490126446997 ps
CPU time 45.2 seconds
Started Jul 04 05:40:00 PM PDT 24
Finished Jul 04 05:40:45 PM PDT 24
Peak memory 199960 kb
Host smart-e142f754-10c2-4e35-9ac8-e7b957350c16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71885967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.71885967
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.4057941001
Short name T690
Test name
Test status
Simulation time 100217351392 ps
CPU time 566.94 seconds
Started Jul 04 05:40:00 PM PDT 24
Finished Jul 04 05:49:28 PM PDT 24
Peak memory 216456 kb
Host smart-2fdc01db-d22f-4f9e-8b88-c00e4a7b30c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057941001 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.4057941001
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3605045417
Short name T264
Test name
Test status
Simulation time 722038932 ps
CPU time 1.67 seconds
Started Jul 04 05:40:02 PM PDT 24
Finished Jul 04 05:40:04 PM PDT 24
Peak memory 199684 kb
Host smart-dac12e72-2840-4c06-b298-f9cb54285559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605045417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3605045417
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3951426844
Short name T859
Test name
Test status
Simulation time 10123590846 ps
CPU time 16 seconds
Started Jul 04 05:39:52 PM PDT 24
Finished Jul 04 05:40:08 PM PDT 24
Peak memory 199656 kb
Host smart-c9a7942d-3c6e-4b62-ad26-356c55936da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951426844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3951426844
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2606150345
Short name T843
Test name
Test status
Simulation time 63996575328 ps
CPU time 52.9 seconds
Started Jul 04 05:43:57 PM PDT 24
Finished Jul 04 05:44:50 PM PDT 24
Peak memory 199888 kb
Host smart-4f8e5dca-c269-4f20-9af4-2f666c1f3188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606150345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2606150345
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2221854289
Short name T726
Test name
Test status
Simulation time 22631100965 ps
CPU time 36.64 seconds
Started Jul 04 05:43:58 PM PDT 24
Finished Jul 04 05:44:34 PM PDT 24
Peak memory 199936 kb
Host smart-0faa4b90-c761-4750-9412-299ea033b297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221854289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2221854289
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.248567770
Short name T310
Test name
Test status
Simulation time 41575406759 ps
CPU time 30.33 seconds
Started Jul 04 05:43:57 PM PDT 24
Finished Jul 04 05:44:28 PM PDT 24
Peak memory 199924 kb
Host smart-ff56bd3e-327d-4ae1-928d-9373d64b678c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248567770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.248567770
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1097516147
Short name T149
Test name
Test status
Simulation time 25829411732 ps
CPU time 45.39 seconds
Started Jul 04 05:44:00 PM PDT 24
Finished Jul 04 05:44:45 PM PDT 24
Peak memory 199860 kb
Host smart-bef54961-b80a-4a12-8d77-65b28f992ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097516147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1097516147
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2710942553
Short name T194
Test name
Test status
Simulation time 30140607211 ps
CPU time 15.21 seconds
Started Jul 04 05:44:05 PM PDT 24
Finished Jul 04 05:44:21 PM PDT 24
Peak memory 199760 kb
Host smart-8da9fae8-6446-42c8-8263-af005aef52d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710942553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2710942553
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2394991664
Short name T760
Test name
Test status
Simulation time 29233814452 ps
CPU time 55.26 seconds
Started Jul 04 05:43:57 PM PDT 24
Finished Jul 04 05:44:52 PM PDT 24
Peak memory 199948 kb
Host smart-8ba63486-a2d8-4360-b0d8-40a5aba40bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394991664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2394991664
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2994201314
Short name T500
Test name
Test status
Simulation time 14456466100 ps
CPU time 14.21 seconds
Started Jul 04 05:43:59 PM PDT 24
Finished Jul 04 05:44:13 PM PDT 24
Peak memory 199944 kb
Host smart-b2d51766-2e38-4972-809a-c84ea26907a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994201314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2994201314
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2845032976
Short name T552
Test name
Test status
Simulation time 8764220924 ps
CPU time 13.11 seconds
Started Jul 04 05:43:57 PM PDT 24
Finished Jul 04 05:44:10 PM PDT 24
Peak memory 199804 kb
Host smart-995a4328-f7e7-4e0c-9666-644fa2185549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845032976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2845032976
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.731725691
Short name T1174
Test name
Test status
Simulation time 108938209610 ps
CPU time 82.18 seconds
Started Jul 04 05:43:56 PM PDT 24
Finished Jul 04 05:45:18 PM PDT 24
Peak memory 199908 kb
Host smart-cfe6dee3-abf3-4441-85a5-178f809513f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731725691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.731725691
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3284866505
Short name T623
Test name
Test status
Simulation time 11211887 ps
CPU time 0.56 seconds
Started Jul 04 05:40:00 PM PDT 24
Finished Jul 04 05:40:01 PM PDT 24
Peak memory 195292 kb
Host smart-328320c1-8dd5-4032-8773-f0d6aabb825b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284866505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3284866505
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.852058932
Short name T867
Test name
Test status
Simulation time 337761543237 ps
CPU time 122.84 seconds
Started Jul 04 05:40:01 PM PDT 24
Finished Jul 04 05:42:05 PM PDT 24
Peak memory 199900 kb
Host smart-2bd0e11c-268d-4800-ad54-51f3603b224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852058932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.852058932
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3376795345
Short name T893
Test name
Test status
Simulation time 27036554753 ps
CPU time 42.39 seconds
Started Jul 04 05:40:00 PM PDT 24
Finished Jul 04 05:40:43 PM PDT 24
Peak memory 199908 kb
Host smart-69de0362-b904-44a7-8d43-04935cd468a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376795345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3376795345
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3870228700
Short name T203
Test name
Test status
Simulation time 53363919079 ps
CPU time 22.91 seconds
Started Jul 04 05:39:59 PM PDT 24
Finished Jul 04 05:40:22 PM PDT 24
Peak memory 200000 kb
Host smart-c0b2cffb-cb33-49b8-bf55-cdb9bc9afa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870228700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3870228700
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.4285652956
Short name T1000
Test name
Test status
Simulation time 67068236867 ps
CPU time 34.85 seconds
Started Jul 04 05:39:59 PM PDT 24
Finished Jul 04 05:40:34 PM PDT 24
Peak memory 199876 kb
Host smart-8b0fb43c-acdb-4ac7-9cfb-140ed6cce05a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285652956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.4285652956
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1853420339
Short name T421
Test name
Test status
Simulation time 57627992585 ps
CPU time 572.68 seconds
Started Jul 04 05:40:00 PM PDT 24
Finished Jul 04 05:49:33 PM PDT 24
Peak memory 199872 kb
Host smart-08d12ffc-8668-4332-8b4b-2f71a10ad156
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853420339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1853420339
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2621524657
Short name T362
Test name
Test status
Simulation time 2324905740 ps
CPU time 2.69 seconds
Started Jul 04 05:39:59 PM PDT 24
Finished Jul 04 05:40:02 PM PDT 24
Peak memory 197468 kb
Host smart-c51193da-3094-498e-a2c8-628163d58e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621524657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2621524657
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.882785821
Short name T222
Test name
Test status
Simulation time 117208318367 ps
CPU time 193.96 seconds
Started Jul 04 05:40:00 PM PDT 24
Finished Jul 04 05:43:15 PM PDT 24
Peak memory 199700 kb
Host smart-8298f9cc-4af4-4fe5-9549-782c129201b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882785821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.882785821
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3325871411
Short name T1145
Test name
Test status
Simulation time 1954514985 ps
CPU time 32.68 seconds
Started Jul 04 05:40:01 PM PDT 24
Finished Jul 04 05:40:34 PM PDT 24
Peak memory 199872 kb
Host smart-1b238181-6122-4ccf-86d8-1dd13f38cd9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325871411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3325871411
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.685294571
Short name T835
Test name
Test status
Simulation time 2872114971 ps
CPU time 5.35 seconds
Started Jul 04 05:40:01 PM PDT 24
Finished Jul 04 05:40:06 PM PDT 24
Peak memory 198368 kb
Host smart-30b478f6-d0e1-40b0-ab24-82eda1869db3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685294571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.685294571
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1982207315
Short name T911
Test name
Test status
Simulation time 230982835153 ps
CPU time 58.78 seconds
Started Jul 04 05:40:01 PM PDT 24
Finished Jul 04 05:41:00 PM PDT 24
Peak memory 199868 kb
Host smart-5877e542-5d74-4cb9-a291-595b1aef9a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982207315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1982207315
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2148402443
Short name T250
Test name
Test status
Simulation time 1666042320 ps
CPU time 3.18 seconds
Started Jul 04 05:40:02 PM PDT 24
Finished Jul 04 05:40:05 PM PDT 24
Peak memory 195456 kb
Host smart-7306d822-841e-4cc3-9bff-49e27cb970ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148402443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2148402443
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2346297532
Short name T762
Test name
Test status
Simulation time 6073438394 ps
CPU time 5 seconds
Started Jul 04 05:40:01 PM PDT 24
Finished Jul 04 05:40:07 PM PDT 24
Peak memory 199924 kb
Host smart-d5969d72-72cb-43d4-bb5e-a27214d6e16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346297532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2346297532
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.297564489
Short name T415
Test name
Test status
Simulation time 470945737714 ps
CPU time 1363.31 seconds
Started Jul 04 05:40:02 PM PDT 24
Finished Jul 04 06:02:45 PM PDT 24
Peak memory 199952 kb
Host smart-bef6d7dd-e766-44c3-94f5-b09df0577a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297564489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.297564489
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2355479550
Short name T1054
Test name
Test status
Simulation time 60633219155 ps
CPU time 363.8 seconds
Started Jul 04 05:40:00 PM PDT 24
Finished Jul 04 05:46:04 PM PDT 24
Peak memory 215880 kb
Host smart-6014ca33-6051-4dfe-b70d-d608040857a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355479550 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2355479550
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.869980683
Short name T974
Test name
Test status
Simulation time 6291508136 ps
CPU time 20.44 seconds
Started Jul 04 05:40:01 PM PDT 24
Finished Jul 04 05:40:22 PM PDT 24
Peak memory 199028 kb
Host smart-22d40292-be95-40dd-a399-b79b6c576b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869980683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.869980683
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.4201284885
Short name T300
Test name
Test status
Simulation time 88224612457 ps
CPU time 14.77 seconds
Started Jul 04 05:40:00 PM PDT 24
Finished Jul 04 05:40:15 PM PDT 24
Peak memory 198212 kb
Host smart-476fd3ab-6e9d-4ea5-b1e1-f3a0d4ce3fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201284885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4201284885
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.927515226
Short name T143
Test name
Test status
Simulation time 108341457482 ps
CPU time 87.62 seconds
Started Jul 04 05:44:04 PM PDT 24
Finished Jul 04 05:45:31 PM PDT 24
Peak memory 199924 kb
Host smart-541e82de-7194-42bf-be88-ceeebd5f8390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927515226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.927515226
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1366094216
Short name T679
Test name
Test status
Simulation time 12640967268 ps
CPU time 10.1 seconds
Started Jul 04 05:44:05 PM PDT 24
Finished Jul 04 05:44:16 PM PDT 24
Peak memory 199992 kb
Host smart-689fc805-ef0d-4256-8821-6d08e618c9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366094216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1366094216
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.492549967
Short name T51
Test name
Test status
Simulation time 14376203680 ps
CPU time 18.7 seconds
Started Jul 04 05:44:05 PM PDT 24
Finished Jul 04 05:44:24 PM PDT 24
Peak memory 198580 kb
Host smart-f5e4baca-59fe-49e7-a2df-8813d1881b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492549967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.492549967
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3359932061
Short name T699
Test name
Test status
Simulation time 118719371851 ps
CPU time 82.35 seconds
Started Jul 04 05:44:03 PM PDT 24
Finished Jul 04 05:45:26 PM PDT 24
Peak memory 199932 kb
Host smart-b079ac2b-f2f1-4247-a34b-8a2bb07b2ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359932061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3359932061
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2398257557
Short name T432
Test name
Test status
Simulation time 16451634555 ps
CPU time 17.35 seconds
Started Jul 04 05:44:05 PM PDT 24
Finished Jul 04 05:44:22 PM PDT 24
Peak memory 199944 kb
Host smart-55f610ac-02db-4bf3-ade5-bcfee27463fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398257557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2398257557
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2264455399
Short name T220
Test name
Test status
Simulation time 124934677279 ps
CPU time 220.42 seconds
Started Jul 04 05:44:05 PM PDT 24
Finished Jul 04 05:47:46 PM PDT 24
Peak memory 199864 kb
Host smart-e8653cc4-177e-4dc7-bc77-cab4b0bf534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264455399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2264455399
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3053747213
Short name T1040
Test name
Test status
Simulation time 102271398618 ps
CPU time 38.6 seconds
Started Jul 04 05:44:05 PM PDT 24
Finished Jul 04 05:44:43 PM PDT 24
Peak memory 199872 kb
Host smart-4aed7c2f-44e9-428c-83f9-b64371f3acc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053747213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3053747213
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.4250799429
Short name T736
Test name
Test status
Simulation time 423694190669 ps
CPU time 58.33 seconds
Started Jul 04 05:44:04 PM PDT 24
Finished Jul 04 05:45:02 PM PDT 24
Peak memory 199828 kb
Host smart-4d1194ad-d7a5-4799-a490-8202ac0e331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250799429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.4250799429
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2626982451
Short name T1083
Test name
Test status
Simulation time 55511898091 ps
CPU time 35.16 seconds
Started Jul 04 05:44:05 PM PDT 24
Finished Jul 04 05:44:40 PM PDT 24
Peak memory 199976 kb
Host smart-54fbf0ec-0d8c-4e96-8161-3816734d9399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626982451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2626982451
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1818594367
Short name T336
Test name
Test status
Simulation time 36781125 ps
CPU time 0.61 seconds
Started Jul 04 05:38:18 PM PDT 24
Finished Jul 04 05:38:19 PM PDT 24
Peak memory 195292 kb
Host smart-38616f17-1909-4ec1-ba99-b656cdd91e6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818594367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1818594367
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2232260711
Short name T423
Test name
Test status
Simulation time 25997843436 ps
CPU time 43.53 seconds
Started Jul 04 05:38:19 PM PDT 24
Finished Jul 04 05:39:03 PM PDT 24
Peak memory 199920 kb
Host smart-08ede492-3199-4e2d-b988-f8617d1bf54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232260711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2232260711
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3356838946
Short name T665
Test name
Test status
Simulation time 188511737857 ps
CPU time 114.68 seconds
Started Jul 04 05:38:20 PM PDT 24
Finished Jul 04 05:40:15 PM PDT 24
Peak memory 199844 kb
Host smart-8c0e3da4-cf1b-4d11-afd4-05c97fefb324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356838946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3356838946
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1756275339
Short name T142
Test name
Test status
Simulation time 66513489699 ps
CPU time 25.77 seconds
Started Jul 04 05:38:12 PM PDT 24
Finished Jul 04 05:38:38 PM PDT 24
Peak memory 199984 kb
Host smart-c4b37255-2cfc-494b-af77-1fe67f74aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756275339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1756275339
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2258572707
Short name T732
Test name
Test status
Simulation time 26734291874 ps
CPU time 22.1 seconds
Started Jul 04 05:38:21 PM PDT 24
Finished Jul 04 05:38:43 PM PDT 24
Peak memory 198144 kb
Host smart-00d05b3f-80d5-4b41-a230-a4eda1614586
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258572707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2258572707
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2570871851
Short name T388
Test name
Test status
Simulation time 126413299339 ps
CPU time 228.64 seconds
Started Jul 04 05:38:24 PM PDT 24
Finished Jul 04 05:42:13 PM PDT 24
Peak memory 199888 kb
Host smart-3db14ba7-8f70-431d-9b20-899370fc395d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2570871851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2570871851
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2581898769
Short name T632
Test name
Test status
Simulation time 3195930417 ps
CPU time 4.87 seconds
Started Jul 04 05:38:23 PM PDT 24
Finished Jul 04 05:38:28 PM PDT 24
Peak memory 199884 kb
Host smart-865feaef-155b-4e02-b7d8-a9943df1de45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581898769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2581898769
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3533807708
Short name T1042
Test name
Test status
Simulation time 4785849377 ps
CPU time 4.42 seconds
Started Jul 04 05:38:20 PM PDT 24
Finished Jul 04 05:38:25 PM PDT 24
Peak memory 199836 kb
Host smart-171519db-5757-4f40-9af1-df64b12c91aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533807708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3533807708
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2785719792
Short name T853
Test name
Test status
Simulation time 15047870513 ps
CPU time 390.08 seconds
Started Jul 04 05:38:17 PM PDT 24
Finished Jul 04 05:44:47 PM PDT 24
Peak memory 199876 kb
Host smart-d98b567f-76c1-4bf2-9abb-8935c09bd01e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785719792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2785719792
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1223917994
Short name T508
Test name
Test status
Simulation time 1797384009 ps
CPU time 9.55 seconds
Started Jul 04 05:38:19 PM PDT 24
Finished Jul 04 05:38:29 PM PDT 24
Peak memory 197932 kb
Host smart-95c6d71a-26eb-49b5-a19f-d1613166809d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223917994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1223917994
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1297021020
Short name T393
Test name
Test status
Simulation time 171240364872 ps
CPU time 33.55 seconds
Started Jul 04 05:38:15 PM PDT 24
Finished Jul 04 05:38:49 PM PDT 24
Peak memory 199924 kb
Host smart-3db5943b-3254-4e6a-ad44-22a8393843d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297021020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1297021020
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.879649581
Short name T877
Test name
Test status
Simulation time 1320091011 ps
CPU time 2.48 seconds
Started Jul 04 05:38:21 PM PDT 24
Finished Jul 04 05:38:24 PM PDT 24
Peak memory 195356 kb
Host smart-0ab44dbe-03d4-4bfd-839a-bb96f0db8917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879649581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.879649581
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3366134282
Short name T27
Test name
Test status
Simulation time 107701501 ps
CPU time 0.82 seconds
Started Jul 04 05:38:21 PM PDT 24
Finished Jul 04 05:38:22 PM PDT 24
Peak memory 218384 kb
Host smart-e60a13da-9f5d-4d0b-86a2-4882b5cd575f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366134282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3366134282
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2857395709
Short name T976
Test name
Test status
Simulation time 505477885 ps
CPU time 1.97 seconds
Started Jul 04 05:38:20 PM PDT 24
Finished Jul 04 05:38:23 PM PDT 24
Peak memory 199388 kb
Host smart-967de14c-7b3c-44c8-a5b7-7cbf15559f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857395709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2857395709
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.362461708
Short name T1075
Test name
Test status
Simulation time 48848081550 ps
CPU time 118.36 seconds
Started Jul 04 05:38:24 PM PDT 24
Finished Jul 04 05:40:23 PM PDT 24
Peak memory 199920 kb
Host smart-0b2549ca-5d19-47a3-ae95-d491a04aab97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362461708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.362461708
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3055593463
Short name T651
Test name
Test status
Simulation time 260850962594 ps
CPU time 762.78 seconds
Started Jul 04 05:38:22 PM PDT 24
Finished Jul 04 05:51:05 PM PDT 24
Peak memory 224840 kb
Host smart-5a66ee20-1441-4da9-9ff1-f4a56729a567
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055593463 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3055593463
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2728358127
Short name T962
Test name
Test status
Simulation time 685790339 ps
CPU time 1.97 seconds
Started Jul 04 05:38:22 PM PDT 24
Finished Jul 04 05:38:25 PM PDT 24
Peak memory 198676 kb
Host smart-dcf45d90-ed2f-4699-a54a-17c2a8462514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728358127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2728358127
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3368290801
Short name T670
Test name
Test status
Simulation time 58314955384 ps
CPU time 117.31 seconds
Started Jul 04 05:38:23 PM PDT 24
Finished Jul 04 05:40:20 PM PDT 24
Peak memory 200024 kb
Host smart-21d83998-833e-464a-841c-d82dc8b1cab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368290801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3368290801
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3731396403
Short name T788
Test name
Test status
Simulation time 12666191 ps
CPU time 0.59 seconds
Started Jul 04 05:40:11 PM PDT 24
Finished Jul 04 05:40:12 PM PDT 24
Peak memory 194944 kb
Host smart-d16235b5-0bc8-4fbf-8e33-2b0e5eb0e9ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731396403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3731396403
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.47824604
Short name T132
Test name
Test status
Simulation time 19950751709 ps
CPU time 16.67 seconds
Started Jul 04 05:40:11 PM PDT 24
Finished Jul 04 05:40:28 PM PDT 24
Peak memory 199960 kb
Host smart-17747e27-bf40-40fc-a5d0-c8bb04f4c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47824604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.47824604
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.624544432
Short name T947
Test name
Test status
Simulation time 84372916240 ps
CPU time 114.55 seconds
Started Jul 04 05:40:10 PM PDT 24
Finished Jul 04 05:42:05 PM PDT 24
Peak memory 199700 kb
Host smart-43e098c7-776b-4137-84d7-65a2c562dd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624544432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.624544432
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2607531481
Short name T869
Test name
Test status
Simulation time 20265588717 ps
CPU time 26.72 seconds
Started Jul 04 05:40:14 PM PDT 24
Finished Jul 04 05:40:41 PM PDT 24
Peak memory 199876 kb
Host smart-2c75e9ae-d2dd-4c78-94b7-febb1eac546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607531481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2607531481
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3092354201
Short name T270
Test name
Test status
Simulation time 168691780072 ps
CPU time 143.47 seconds
Started Jul 04 05:40:12 PM PDT 24
Finished Jul 04 05:42:36 PM PDT 24
Peak memory 199960 kb
Host smart-ab882f09-cd28-45ae-be6a-4eaaeb4e2aca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092354201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3092354201
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2034583190
Short name T967
Test name
Test status
Simulation time 93930395293 ps
CPU time 139.74 seconds
Started Jul 04 05:40:12 PM PDT 24
Finished Jul 04 05:42:32 PM PDT 24
Peak memory 199960 kb
Host smart-bf4afdaa-1fc4-4147-8f4d-13df5d9163ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2034583190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2034583190
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2853289105
Short name T1007
Test name
Test status
Simulation time 5878293710 ps
CPU time 10.59 seconds
Started Jul 04 05:40:11 PM PDT 24
Finished Jul 04 05:40:21 PM PDT 24
Peak memory 198612 kb
Host smart-d3a4996b-170e-4652-90ee-b15bed500193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853289105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2853289105
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3270944871
Short name T781
Test name
Test status
Simulation time 64339192789 ps
CPU time 29.92 seconds
Started Jul 04 05:40:14 PM PDT 24
Finished Jul 04 05:40:44 PM PDT 24
Peak memory 198968 kb
Host smart-1363bf2f-5abb-4c17-9211-71b52c840727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270944871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3270944871
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.410961188
Short name T476
Test name
Test status
Simulation time 9549886304 ps
CPU time 558.71 seconds
Started Jul 04 05:40:12 PM PDT 24
Finished Jul 04 05:49:31 PM PDT 24
Peak memory 199892 kb
Host smart-0c6378fb-27f5-4883-9c86-66517eb968d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410961188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.410961188
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.892231487
Short name T886
Test name
Test status
Simulation time 1907008938 ps
CPU time 5.37 seconds
Started Jul 04 05:40:11 PM PDT 24
Finished Jul 04 05:40:17 PM PDT 24
Peak memory 198056 kb
Host smart-7cb53af8-f307-4775-b2e8-f42cdb567400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=892231487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.892231487
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1306359106
Short name T418
Test name
Test status
Simulation time 35290742123 ps
CPU time 29.24 seconds
Started Jul 04 05:40:11 PM PDT 24
Finished Jul 04 05:40:40 PM PDT 24
Peak memory 199968 kb
Host smart-285edd23-7e19-4773-94a0-cd2403498526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306359106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1306359106
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3294750579
Short name T253
Test name
Test status
Simulation time 4649478598 ps
CPU time 3.88 seconds
Started Jul 04 05:40:12 PM PDT 24
Finished Jul 04 05:40:16 PM PDT 24
Peak memory 196424 kb
Host smart-b6edb72b-0e4f-4ae0-9c20-11fa66e18c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294750579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3294750579
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1328900306
Short name T242
Test name
Test status
Simulation time 884043077 ps
CPU time 3.39 seconds
Started Jul 04 05:40:02 PM PDT 24
Finished Jul 04 05:40:05 PM PDT 24
Peak memory 198180 kb
Host smart-0344a4d8-2c63-4756-a157-e9ff1d7935d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328900306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1328900306
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2142974823
Short name T171
Test name
Test status
Simulation time 42354296923 ps
CPU time 1341.42 seconds
Started Jul 04 05:40:10 PM PDT 24
Finished Jul 04 06:02:32 PM PDT 24
Peak memory 199904 kb
Host smart-2b89092e-85fd-4783-bf7a-010f9a058cb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142974823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2142974823
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.427696670
Short name T588
Test name
Test status
Simulation time 85604662284 ps
CPU time 898.96 seconds
Started Jul 04 05:40:11 PM PDT 24
Finished Jul 04 05:55:10 PM PDT 24
Peak memory 224752 kb
Host smart-b239a88f-af38-4aea-b208-a3520789b090
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427696670 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.427696670
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2215398296
Short name T1148
Test name
Test status
Simulation time 707267641 ps
CPU time 3.05 seconds
Started Jul 04 05:40:12 PM PDT 24
Finished Jul 04 05:40:15 PM PDT 24
Peak memory 198500 kb
Host smart-52fa5a13-ac77-4f94-9885-8b4bb161d4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215398296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2215398296
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3950667053
Short name T892
Test name
Test status
Simulation time 60733237287 ps
CPU time 10.07 seconds
Started Jul 04 05:40:10 PM PDT 24
Finished Jul 04 05:40:20 PM PDT 24
Peak memory 199652 kb
Host smart-82dd0c03-1f94-4fcf-b5cf-dc0535f00e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950667053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3950667053
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2920265846
Short name T801
Test name
Test status
Simulation time 24867045 ps
CPU time 0.58 seconds
Started Jul 04 05:40:19 PM PDT 24
Finished Jul 04 05:40:19 PM PDT 24
Peak memory 195224 kb
Host smart-791697cd-4027-4863-bde6-a3dc241fb677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920265846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2920265846
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3667073534
Short name T628
Test name
Test status
Simulation time 101300524239 ps
CPU time 29.65 seconds
Started Jul 04 05:40:12 PM PDT 24
Finished Jul 04 05:40:42 PM PDT 24
Peak memory 199984 kb
Host smart-b3a63ee3-a3e6-4100-a51b-af67485103ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667073534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3667073534
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3063895799
Short name T831
Test name
Test status
Simulation time 139333399080 ps
CPU time 118.84 seconds
Started Jul 04 05:40:11 PM PDT 24
Finished Jul 04 05:42:10 PM PDT 24
Peak memory 199988 kb
Host smart-6dc43a92-6078-40e8-800b-153ee9623632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063895799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3063895799
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2236389045
Short name T608
Test name
Test status
Simulation time 160005103226 ps
CPU time 60.79 seconds
Started Jul 04 05:40:12 PM PDT 24
Finished Jul 04 05:41:13 PM PDT 24
Peak memory 199920 kb
Host smart-fdbadcc2-e3db-450c-a27a-426edb44651a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236389045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2236389045
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2789476878
Short name T96
Test name
Test status
Simulation time 60282082045 ps
CPU time 17.07 seconds
Started Jul 04 05:40:12 PM PDT 24
Finished Jul 04 05:40:30 PM PDT 24
Peak memory 199968 kb
Host smart-76f6710c-036a-40cf-b168-f42216fe9a69
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789476878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2789476878
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1429905176
Short name T10
Test name
Test status
Simulation time 65926716465 ps
CPU time 363.53 seconds
Started Jul 04 05:40:18 PM PDT 24
Finished Jul 04 05:46:22 PM PDT 24
Peak memory 199984 kb
Host smart-3adc9d23-90b4-4496-b27c-f5007e74f354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429905176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1429905176
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3876640437
Short name T633
Test name
Test status
Simulation time 10077997280 ps
CPU time 10.63 seconds
Started Jul 04 05:40:21 PM PDT 24
Finished Jul 04 05:40:32 PM PDT 24
Peak memory 199688 kb
Host smart-3b865757-1bed-4a79-8d54-39d57eadaff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876640437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3876640437
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3970256950
Short name T528
Test name
Test status
Simulation time 36746930375 ps
CPU time 69.58 seconds
Started Jul 04 05:40:12 PM PDT 24
Finished Jul 04 05:41:22 PM PDT 24
Peak memory 200164 kb
Host smart-20166d34-fb80-4770-9db9-a4a567510277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970256950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3970256950
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.774272151
Short name T413
Test name
Test status
Simulation time 9998184584 ps
CPU time 439.18 seconds
Started Jul 04 05:40:23 PM PDT 24
Finished Jul 04 05:47:43 PM PDT 24
Peak memory 199892 kb
Host smart-2f9fe831-f797-47a3-ad81-9cbb84a56e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774272151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.774272151
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1932449041
Short name T448
Test name
Test status
Simulation time 3164248447 ps
CPU time 10.66 seconds
Started Jul 04 05:40:14 PM PDT 24
Finished Jul 04 05:40:25 PM PDT 24
Peak memory 197744 kb
Host smart-48e4c159-cb6e-489e-bd38-300d83827be8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932449041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1932449041
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3737179361
Short name T1033
Test name
Test status
Simulation time 239352260828 ps
CPU time 440.48 seconds
Started Jul 04 05:40:18 PM PDT 24
Finished Jul 04 05:47:38 PM PDT 24
Peak memory 199976 kb
Host smart-f35d9476-0272-4c70-975b-21a235513012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737179361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3737179361
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4139048558
Short name T904
Test name
Test status
Simulation time 3225816116 ps
CPU time 3.34 seconds
Started Jul 04 05:40:11 PM PDT 24
Finished Jul 04 05:40:14 PM PDT 24
Peak memory 195956 kb
Host smart-f006b59a-68d5-4822-8b2f-7b1f36a12ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139048558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4139048558
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2933137581
Short name T465
Test name
Test status
Simulation time 5686146134 ps
CPU time 9.62 seconds
Started Jul 04 05:40:08 PM PDT 24
Finished Jul 04 05:40:18 PM PDT 24
Peak memory 199860 kb
Host smart-bb08ae79-5891-4fcd-a9c0-af2fe9c955fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933137581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2933137581
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.997057363
Short name T170
Test name
Test status
Simulation time 67301500014 ps
CPU time 102.07 seconds
Started Jul 04 05:40:23 PM PDT 24
Finished Jul 04 05:42:05 PM PDT 24
Peak memory 199988 kb
Host smart-372cae4b-a183-43ff-ac1e-a412de248cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997057363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.997057363
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3654058780
Short name T784
Test name
Test status
Simulation time 13228767728 ps
CPU time 121.85 seconds
Started Jul 04 05:40:18 PM PDT 24
Finished Jul 04 05:42:21 PM PDT 24
Peak memory 216628 kb
Host smart-300f7e69-1a41-491b-947d-7cf62cea2dac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654058780 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3654058780
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2883549257
Short name T1156
Test name
Test status
Simulation time 6629700758 ps
CPU time 14.03 seconds
Started Jul 04 05:40:23 PM PDT 24
Finished Jul 04 05:40:37 PM PDT 24
Peak memory 199932 kb
Host smart-8323bec4-d2c5-4846-89a9-4f6239e33805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883549257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2883549257
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2260080911
Short name T240
Test name
Test status
Simulation time 1804341316 ps
CPU time 3.16 seconds
Started Jul 04 05:40:11 PM PDT 24
Finished Jul 04 05:40:14 PM PDT 24
Peak memory 198952 kb
Host smart-97719d62-58b4-4f8d-8081-ba8d30fcc36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260080911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2260080911
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1552097194
Short name T803
Test name
Test status
Simulation time 11809334 ps
CPU time 0.56 seconds
Started Jul 04 05:40:18 PM PDT 24
Finished Jul 04 05:40:19 PM PDT 24
Peak memory 195300 kb
Host smart-7b0f4961-4138-497b-ab3c-788b20942c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552097194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1552097194
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2997763296
Short name T569
Test name
Test status
Simulation time 18223436627 ps
CPU time 24 seconds
Started Jul 04 05:40:19 PM PDT 24
Finished Jul 04 05:40:43 PM PDT 24
Peak memory 199624 kb
Host smart-94db137f-9e08-4c21-8f6f-ac314ac0fad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997763296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2997763296
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3969954144
Short name T959
Test name
Test status
Simulation time 117111469976 ps
CPU time 85.11 seconds
Started Jul 04 05:40:21 PM PDT 24
Finished Jul 04 05:41:46 PM PDT 24
Peak memory 200000 kb
Host smart-12f8b4c4-e7a3-4bce-adeb-9ed3b97b68ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969954144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3969954144
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.689042287
Short name T994
Test name
Test status
Simulation time 47835099740 ps
CPU time 18.96 seconds
Started Jul 04 05:40:17 PM PDT 24
Finished Jul 04 05:40:36 PM PDT 24
Peak memory 199780 kb
Host smart-871370d9-8b23-4385-b10d-663228e19469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689042287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.689042287
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1604044770
Short name T643
Test name
Test status
Simulation time 63814820261 ps
CPU time 26.74 seconds
Started Jul 04 05:40:24 PM PDT 24
Finished Jul 04 05:40:51 PM PDT 24
Peak memory 199688 kb
Host smart-63bae317-50fa-4314-bb89-75596f57ab26
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604044770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1604044770
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.267448430
Short name T461
Test name
Test status
Simulation time 90814347611 ps
CPU time 235.22 seconds
Started Jul 04 05:40:20 PM PDT 24
Finished Jul 04 05:44:16 PM PDT 24
Peak memory 199928 kb
Host smart-2a079ab8-00f0-43b5-acf6-992de8376594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267448430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.267448430
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1511962239
Short name T556
Test name
Test status
Simulation time 5732076327 ps
CPU time 3.54 seconds
Started Jul 04 05:40:18 PM PDT 24
Finished Jul 04 05:40:22 PM PDT 24
Peak memory 197404 kb
Host smart-15fed6ce-1f4f-4379-af13-da91758f57d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511962239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1511962239
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.622090668
Short name T557
Test name
Test status
Simulation time 16977072579 ps
CPU time 29.2 seconds
Started Jul 04 05:40:24 PM PDT 24
Finished Jul 04 05:40:53 PM PDT 24
Peak memory 198672 kb
Host smart-248cf3c1-bd84-412b-87a9-e2f639d74500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622090668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.622090668
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2978816832
Short name T903
Test name
Test status
Simulation time 9634952525 ps
CPU time 504.02 seconds
Started Jul 04 05:40:18 PM PDT 24
Finished Jul 04 05:48:42 PM PDT 24
Peak memory 199936 kb
Host smart-e8f4a5aa-58f2-41a9-b0af-f7be7538534b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978816832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2978816832
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.459296335
Short name T813
Test name
Test status
Simulation time 7383521816 ps
CPU time 7.18 seconds
Started Jul 04 05:40:20 PM PDT 24
Finished Jul 04 05:40:27 PM PDT 24
Peak memory 198784 kb
Host smart-58b256ef-d6d3-4675-8cbb-63f6d54e8699
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=459296335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.459296335
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3124101713
Short name T427
Test name
Test status
Simulation time 1937350971 ps
CPU time 1.34 seconds
Started Jul 04 05:40:18 PM PDT 24
Finished Jul 04 05:40:20 PM PDT 24
Peak memory 195360 kb
Host smart-372b4473-60fc-4b88-b6e5-7330c6088a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124101713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3124101713
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1978320043
Short name T285
Test name
Test status
Simulation time 11103109451 ps
CPU time 13.57 seconds
Started Jul 04 05:40:20 PM PDT 24
Finished Jul 04 05:40:34 PM PDT 24
Peak memory 199920 kb
Host smart-3a071852-46c2-4ca0-abb8-487336a79c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978320043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1978320043
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2038547814
Short name T317
Test name
Test status
Simulation time 122104126413 ps
CPU time 210.1 seconds
Started Jul 04 05:40:19 PM PDT 24
Finished Jul 04 05:43:50 PM PDT 24
Peak memory 200016 kb
Host smart-74c8cec7-cc7d-457b-9723-a52607aa37fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038547814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2038547814
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2074804047
Short name T487
Test name
Test status
Simulation time 61380085958 ps
CPU time 289.87 seconds
Started Jul 04 05:40:17 PM PDT 24
Finished Jul 04 05:45:07 PM PDT 24
Peak memory 200068 kb
Host smart-b5593669-11af-4645-80f8-b4b4146a083f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074804047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2074804047
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2235156789
Short name T639
Test name
Test status
Simulation time 1061549955 ps
CPU time 3.24 seconds
Started Jul 04 05:40:21 PM PDT 24
Finished Jul 04 05:40:25 PM PDT 24
Peak memory 198160 kb
Host smart-13316cc6-b6ef-40ab-8003-16b5adb2bc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235156789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2235156789
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1547645016
Short name T370
Test name
Test status
Simulation time 30574160699 ps
CPU time 12.93 seconds
Started Jul 04 05:40:24 PM PDT 24
Finished Jul 04 05:40:37 PM PDT 24
Peak memory 200004 kb
Host smart-4784fa1e-e396-4024-9005-1c8534092ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547645016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1547645016
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3274563566
Short name T833
Test name
Test status
Simulation time 38867954 ps
CPU time 0.55 seconds
Started Jul 04 05:40:28 PM PDT 24
Finished Jul 04 05:40:29 PM PDT 24
Peak memory 194776 kb
Host smart-1edb6a5e-d4d7-4935-b505-4b210ae02c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274563566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3274563566
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2843665120
Short name T1052
Test name
Test status
Simulation time 81178919697 ps
CPU time 97.42 seconds
Started Jul 04 05:40:18 PM PDT 24
Finished Jul 04 05:41:56 PM PDT 24
Peak memory 199984 kb
Host smart-0357aa15-f8ea-44b6-a183-c4e776d8410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843665120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2843665120
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.4119805159
Short name T580
Test name
Test status
Simulation time 50537838508 ps
CPU time 22.71 seconds
Started Jul 04 05:40:18 PM PDT 24
Finished Jul 04 05:40:41 PM PDT 24
Peak memory 200016 kb
Host smart-509d2603-79c7-4c13-874c-24375ecccb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119805159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.4119805159
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3831528867
Short name T910
Test name
Test status
Simulation time 4816895357 ps
CPU time 13.64 seconds
Started Jul 04 05:40:21 PM PDT 24
Finished Jul 04 05:40:35 PM PDT 24
Peak memory 199848 kb
Host smart-fb1e92e4-778f-44f9-a847-5b992d6c7fed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831528867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3831528867
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.517383863
Short name T486
Test name
Test status
Simulation time 92651197547 ps
CPU time 830.24 seconds
Started Jul 04 05:40:26 PM PDT 24
Finished Jul 04 05:54:17 PM PDT 24
Peak memory 199912 kb
Host smart-3102ef4e-3da7-4dff-8344-a631f6dba76f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=517383863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.517383863
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2483914324
Short name T429
Test name
Test status
Simulation time 2612906202 ps
CPU time 10.18 seconds
Started Jul 04 05:40:27 PM PDT 24
Finished Jul 04 05:40:38 PM PDT 24
Peak memory 198636 kb
Host smart-19cfcafd-5d0a-432a-9174-d67bc010a3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483914324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2483914324
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3426983939
Short name T874
Test name
Test status
Simulation time 57503012972 ps
CPU time 97.89 seconds
Started Jul 04 05:40:26 PM PDT 24
Finished Jul 04 05:42:04 PM PDT 24
Peak memory 200124 kb
Host smart-2080e128-c5f8-4e3b-baa4-ebe281b643fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426983939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3426983939
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.203427448
Short name T649
Test name
Test status
Simulation time 24170015852 ps
CPU time 62.37 seconds
Started Jul 04 05:40:27 PM PDT 24
Finished Jul 04 05:41:29 PM PDT 24
Peak memory 199976 kb
Host smart-027d809f-236a-4673-8aa8-068ebebbccd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203427448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.203427448
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.128672254
Short name T906
Test name
Test status
Simulation time 6951183486 ps
CPU time 11.26 seconds
Started Jul 04 05:40:18 PM PDT 24
Finished Jul 04 05:40:30 PM PDT 24
Peak memory 198160 kb
Host smart-aecc8a84-66e6-4b6c-9c07-938411c16d73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128672254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.128672254
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1966251433
Short name T674
Test name
Test status
Simulation time 87018665780 ps
CPU time 286.7 seconds
Started Jul 04 05:40:27 PM PDT 24
Finished Jul 04 05:45:14 PM PDT 24
Peak memory 199960 kb
Host smart-426434ef-24cd-4300-86c6-3661c9a9d5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966251433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1966251433
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.565734689
Short name T555
Test name
Test status
Simulation time 4283047522 ps
CPU time 1.19 seconds
Started Jul 04 05:40:27 PM PDT 24
Finished Jul 04 05:40:28 PM PDT 24
Peak memory 196056 kb
Host smart-3c94c680-c142-47da-a7f2-cf1aeb61e98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565734689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.565734689
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2731541738
Short name T884
Test name
Test status
Simulation time 6169704022 ps
CPU time 19.23 seconds
Started Jul 04 05:40:24 PM PDT 24
Finished Jul 04 05:40:43 PM PDT 24
Peak memory 199944 kb
Host smart-abef5bfa-fb66-48f8-b334-a29da53ad0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731541738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2731541738
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2204492844
Short name T595
Test name
Test status
Simulation time 143910331730 ps
CPU time 57.6 seconds
Started Jul 04 05:40:26 PM PDT 24
Finished Jul 04 05:41:24 PM PDT 24
Peak memory 199900 kb
Host smart-14046c24-780e-402e-a660-92255eb24c0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204492844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2204492844
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2525678375
Short name T844
Test name
Test status
Simulation time 57678783261 ps
CPU time 411.06 seconds
Started Jul 04 05:40:27 PM PDT 24
Finished Jul 04 05:47:18 PM PDT 24
Peak memory 212620 kb
Host smart-a61a5b7c-b8f8-4a92-a5ca-55807bc567df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525678375 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2525678375
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.569994671
Short name T963
Test name
Test status
Simulation time 7071261264 ps
CPU time 25.3 seconds
Started Jul 04 05:40:26 PM PDT 24
Finished Jul 04 05:40:51 PM PDT 24
Peak memory 199404 kb
Host smart-42cf2d9f-6436-4ff7-b8a0-9e664956df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569994671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.569994671
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2787541409
Short name T1147
Test name
Test status
Simulation time 57234340086 ps
CPU time 26.99 seconds
Started Jul 04 05:40:16 PM PDT 24
Finished Jul 04 05:40:43 PM PDT 24
Peak memory 199940 kb
Host smart-08c11fcd-cd65-4f00-8787-9de75c04e842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787541409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2787541409
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3669418300
Short name T339
Test name
Test status
Simulation time 45214236 ps
CPU time 0.6 seconds
Started Jul 04 05:40:33 PM PDT 24
Finished Jul 04 05:40:34 PM PDT 24
Peak memory 195272 kb
Host smart-b8fe5c41-48d6-4004-9b62-a8f53db3ebb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669418300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3669418300
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3199689333
Short name T707
Test name
Test status
Simulation time 45533109050 ps
CPU time 24.1 seconds
Started Jul 04 05:40:27 PM PDT 24
Finished Jul 04 05:40:51 PM PDT 24
Peak memory 199976 kb
Host smart-4802c5a7-71ab-4ecb-bf39-5cbaf69c5336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199689333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3199689333
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1762144483
Short name T109
Test name
Test status
Simulation time 99476676534 ps
CPU time 80.22 seconds
Started Jul 04 05:40:27 PM PDT 24
Finished Jul 04 05:41:47 PM PDT 24
Peak memory 199696 kb
Host smart-e383e6e6-4ac1-459f-9fdc-03cc52677e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762144483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1762144483
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_intr.4239717136
Short name T496
Test name
Test status
Simulation time 22281388349 ps
CPU time 35.58 seconds
Started Jul 04 05:40:35 PM PDT 24
Finished Jul 04 05:41:11 PM PDT 24
Peak memory 198448 kb
Host smart-246c7f2e-f989-4fa9-b7b2-234aa20183ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239717136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4239717136
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2509012105
Short name T986
Test name
Test status
Simulation time 105423832550 ps
CPU time 1018.41 seconds
Started Jul 04 05:40:33 PM PDT 24
Finished Jul 04 05:57:31 PM PDT 24
Peak memory 199972 kb
Host smart-58f10513-8c63-4707-80ce-41717a4abd60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509012105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2509012105
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.463984560
Short name T799
Test name
Test status
Simulation time 1341529010 ps
CPU time 2.02 seconds
Started Jul 04 05:40:35 PM PDT 24
Finished Jul 04 05:40:38 PM PDT 24
Peak memory 198324 kb
Host smart-d0c50af7-39d8-4587-b262-528cfc6466e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463984560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.463984560
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3115048762
Short name T261
Test name
Test status
Simulation time 93115191229 ps
CPU time 89.86 seconds
Started Jul 04 05:40:33 PM PDT 24
Finished Jul 04 05:42:03 PM PDT 24
Peak memory 208032 kb
Host smart-6be4e743-bfe2-4dba-bee3-bb408d6a11b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115048762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3115048762
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.848301067
Short name T348
Test name
Test status
Simulation time 3817879516 ps
CPU time 235.64 seconds
Started Jul 04 05:40:34 PM PDT 24
Finished Jul 04 05:44:30 PM PDT 24
Peak memory 199880 kb
Host smart-04d0fe76-abd8-4f4a-b1bf-5eeecddf9c3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=848301067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.848301067
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.80151314
Short name T598
Test name
Test status
Simulation time 5270297101 ps
CPU time 49.87 seconds
Started Jul 04 05:40:27 PM PDT 24
Finished Jul 04 05:41:18 PM PDT 24
Peak memory 198344 kb
Host smart-48aa3719-686c-4619-9b21-aaa29b92e978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80151314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.80151314
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4019039945
Short name T140
Test name
Test status
Simulation time 78087376384 ps
CPU time 13.91 seconds
Started Jul 04 05:40:37 PM PDT 24
Finished Jul 04 05:40:51 PM PDT 24
Peak memory 199732 kb
Host smart-56ca70e3-544e-49a9-b10f-5c5b8021fe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019039945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4019039945
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2796403953
Short name T850
Test name
Test status
Simulation time 5077281239 ps
CPU time 7.42 seconds
Started Jul 04 05:40:36 PM PDT 24
Finished Jul 04 05:40:43 PM PDT 24
Peak memory 196428 kb
Host smart-56ccbbef-26c6-4efc-b56e-ad1f2b608edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796403953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2796403953
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2947929653
Short name T394
Test name
Test status
Simulation time 462560525 ps
CPU time 1.64 seconds
Started Jul 04 05:40:29 PM PDT 24
Finished Jul 04 05:40:30 PM PDT 24
Peak memory 199844 kb
Host smart-d05dfc01-c5f7-4778-9692-a0e9c03aa384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947929653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2947929653
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.4153136945
Short name T544
Test name
Test status
Simulation time 321526389635 ps
CPU time 240.07 seconds
Started Jul 04 05:40:34 PM PDT 24
Finished Jul 04 05:44:34 PM PDT 24
Peak memory 199916 kb
Host smart-381ca41c-4ae7-401d-afc8-807ade33be1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153136945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4153136945
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1532641357
Short name T1023
Test name
Test status
Simulation time 803279125 ps
CPU time 3.01 seconds
Started Jul 04 05:40:35 PM PDT 24
Finished Jul 04 05:40:38 PM PDT 24
Peak memory 198308 kb
Host smart-e721f8b7-d340-4325-9923-0559f95c7b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532641357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1532641357
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.4027074839
Short name T91
Test name
Test status
Simulation time 68933881126 ps
CPU time 47.52 seconds
Started Jul 04 05:40:27 PM PDT 24
Finished Jul 04 05:41:15 PM PDT 24
Peak memory 199808 kb
Host smart-32700de4-b17a-48ec-a94c-ffcfabba3955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027074839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.4027074839
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3507034377
Short name T23
Test name
Test status
Simulation time 57317062 ps
CPU time 0.55 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:40:42 PM PDT 24
Peak memory 195292 kb
Host smart-31df47e5-a016-4c1d-afb7-2d18b59feb9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507034377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3507034377
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3470191521
Short name T912
Test name
Test status
Simulation time 137647322909 ps
CPU time 55.88 seconds
Started Jul 04 05:40:32 PM PDT 24
Finished Jul 04 05:41:28 PM PDT 24
Peak memory 199884 kb
Host smart-1a924fe7-8b97-421c-b2f1-19cac885fdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470191521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3470191521
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3964492079
Short name T894
Test name
Test status
Simulation time 93690370479 ps
CPU time 67.16 seconds
Started Jul 04 05:40:34 PM PDT 24
Finished Jul 04 05:41:41 PM PDT 24
Peak memory 198488 kb
Host smart-6fbbaaca-917e-4114-8bd8-98c0a7586688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964492079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3964492079
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.2669887989
Short name T1032
Test name
Test status
Simulation time 10800978247 ps
CPU time 14.47 seconds
Started Jul 04 05:40:34 PM PDT 24
Finished Jul 04 05:40:49 PM PDT 24
Peak memory 197472 kb
Host smart-199ce6c1-dcc8-4719-be97-a6e33df72979
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669887989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2669887989
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1246877487
Short name T1136
Test name
Test status
Simulation time 97022990974 ps
CPU time 372.15 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:46:54 PM PDT 24
Peak memory 199884 kb
Host smart-70a5b2d1-a32c-4d72-b139-eaa0a19bd39a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246877487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1246877487
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1274183418
Short name T919
Test name
Test status
Simulation time 11067105846 ps
CPU time 21.19 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:41:03 PM PDT 24
Peak memory 199880 kb
Host smart-e564c91e-6377-4dbe-87c2-593c1d89661e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274183418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1274183418
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2753838849
Short name T524
Test name
Test status
Simulation time 13153790708 ps
CPU time 20.55 seconds
Started Jul 04 05:40:33 PM PDT 24
Finished Jul 04 05:40:54 PM PDT 24
Peak memory 198708 kb
Host smart-4acc81ee-f045-4c77-912a-0cbcd3c4bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753838849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2753838849
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3435557556
Short name T730
Test name
Test status
Simulation time 21870310804 ps
CPU time 110.89 seconds
Started Jul 04 05:40:40 PM PDT 24
Finished Jul 04 05:42:31 PM PDT 24
Peak memory 200000 kb
Host smart-053c19d4-f73e-4fdd-92d4-201088583b40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435557556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3435557556
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1619006617
Short name T533
Test name
Test status
Simulation time 7077609258 ps
CPU time 68.14 seconds
Started Jul 04 05:40:33 PM PDT 24
Finished Jul 04 05:41:41 PM PDT 24
Peak memory 198380 kb
Host smart-7cd3de7d-e054-47ae-a6e5-cd00ff868caa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619006617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1619006617
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3235988941
Short name T1119
Test name
Test status
Simulation time 146293391794 ps
CPU time 96.13 seconds
Started Jul 04 05:40:34 PM PDT 24
Finished Jul 04 05:42:11 PM PDT 24
Peak memory 199860 kb
Host smart-319ad507-3617-4ec3-b4a9-f3ce821731f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235988941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3235988941
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2140630493
Short name T507
Test name
Test status
Simulation time 2957580154 ps
CPU time 1.39 seconds
Started Jul 04 05:40:35 PM PDT 24
Finished Jul 04 05:40:37 PM PDT 24
Peak memory 195792 kb
Host smart-2c7997af-e0b9-4ce5-a82e-15b834edaa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140630493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2140630493
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2777157198
Short name T758
Test name
Test status
Simulation time 646182378 ps
CPU time 2.85 seconds
Started Jul 04 05:40:34 PM PDT 24
Finished Jul 04 05:40:37 PM PDT 24
Peak memory 199616 kb
Host smart-5da56941-db61-4ba9-b44c-0ab73cc6e158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777157198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2777157198
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1758925191
Short name T1172
Test name
Test status
Simulation time 424947142559 ps
CPU time 217.43 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:44:19 PM PDT 24
Peak memory 199928 kb
Host smart-039426eb-c30e-4fa6-b86c-05f258ab895c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758925191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1758925191
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3844803549
Short name T1017
Test name
Test status
Simulation time 208544396977 ps
CPU time 231.7 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:44:33 PM PDT 24
Peak memory 216464 kb
Host smart-046193fe-d6b6-4ae6-8037-72b0d280c3c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844803549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3844803549
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.120183635
Short name T640
Test name
Test status
Simulation time 2468537093 ps
CPU time 2.08 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:40:43 PM PDT 24
Peak memory 199564 kb
Host smart-8eaf1d0c-5e29-4efb-9789-63ab205ea221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120183635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.120183635
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.315250925
Short name T319
Test name
Test status
Simulation time 39045753672 ps
CPU time 12.07 seconds
Started Jul 04 05:40:35 PM PDT 24
Finished Jul 04 05:40:47 PM PDT 24
Peak memory 199988 kb
Host smart-9afd994b-7a73-43a4-8781-c98869ef7ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315250925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.315250925
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1520982817
Short name T694
Test name
Test status
Simulation time 198524120 ps
CPU time 0.53 seconds
Started Jul 04 05:40:48 PM PDT 24
Finished Jul 04 05:40:49 PM PDT 24
Peak memory 195260 kb
Host smart-35ea2211-cc03-4376-9d43-996e7de1ae89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520982817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1520982817
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.695763708
Short name T609
Test name
Test status
Simulation time 99404715132 ps
CPU time 25.96 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:41:07 PM PDT 24
Peak memory 199900 kb
Host smart-9167ee69-298b-4246-8d96-f124af47c199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695763708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.695763708
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2001295048
Short name T713
Test name
Test status
Simulation time 174821996006 ps
CPU time 42.37 seconds
Started Jul 04 05:40:39 PM PDT 24
Finished Jul 04 05:41:22 PM PDT 24
Peak memory 199968 kb
Host smart-b87a2382-fef7-40b1-8ac4-b6168f08cafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001295048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2001295048
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4122912220
Short name T876
Test name
Test status
Simulation time 83901178705 ps
CPU time 22.85 seconds
Started Jul 04 05:40:40 PM PDT 24
Finished Jul 04 05:41:03 PM PDT 24
Peak memory 199852 kb
Host smart-fbc93ac3-beba-4875-ba30-e8d7ecdc7afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122912220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4122912220
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.867754367
Short name T462
Test name
Test status
Simulation time 13251397627 ps
CPU time 5.38 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:40:47 PM PDT 24
Peak memory 197752 kb
Host smart-74cf5120-441b-42f5-a274-d0a0c752f5b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867754367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.867754367
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3808263306
Short name T1014
Test name
Test status
Simulation time 104892939572 ps
CPU time 562.17 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:50:03 PM PDT 24
Peak memory 199896 kb
Host smart-170f563d-d783-4ebc-b44f-409aaf1066ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808263306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3808263306
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3864275604
Short name T389
Test name
Test status
Simulation time 9661370564 ps
CPU time 4.85 seconds
Started Jul 04 05:40:38 PM PDT 24
Finished Jul 04 05:40:43 PM PDT 24
Peak memory 199964 kb
Host smart-dc5e2d3a-91c3-4ad0-9c8f-4ee71bdfe0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864275604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3864275604
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2682702149
Short name T1103
Test name
Test status
Simulation time 47472915401 ps
CPU time 39.05 seconds
Started Jul 04 05:40:42 PM PDT 24
Finished Jul 04 05:41:22 PM PDT 24
Peak memory 200008 kb
Host smart-622c3c0c-7e0f-446e-b0c3-781ff47aedf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682702149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2682702149
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3335696477
Short name T823
Test name
Test status
Simulation time 4756088403 ps
CPU time 133.46 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:42:54 PM PDT 24
Peak memory 199928 kb
Host smart-5381f086-8829-4a7f-8b0d-20738455959a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3335696477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3335696477
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3808933308
Short name T780
Test name
Test status
Simulation time 6332103819 ps
CPU time 52.35 seconds
Started Jul 04 05:40:44 PM PDT 24
Finished Jul 04 05:41:36 PM PDT 24
Peak memory 198840 kb
Host smart-a14c6513-fcc7-4595-be18-e3dbd30c23b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808933308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3808933308
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2225660638
Short name T363
Test name
Test status
Simulation time 54302974043 ps
CPU time 21.67 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:41:03 PM PDT 24
Peak memory 199708 kb
Host smart-4c7ae243-4848-4f77-aec7-06e67ddb68ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225660638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2225660638
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3032812831
Short name T243
Test name
Test status
Simulation time 4366697616 ps
CPU time 1.19 seconds
Started Jul 04 05:40:42 PM PDT 24
Finished Jul 04 05:40:44 PM PDT 24
Peak memory 196776 kb
Host smart-9f614d6b-1514-43c6-ad90-6a11cf40c381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032812831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3032812831
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2074739791
Short name T951
Test name
Test status
Simulation time 6335870463 ps
CPU time 10.01 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:40:51 PM PDT 24
Peak memory 199956 kb
Host smart-acff2fdc-7256-4269-bfea-fefe9b372472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074739791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2074739791
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.622700418
Short name T997
Test name
Test status
Simulation time 463318349631 ps
CPU time 321.71 seconds
Started Jul 04 05:40:47 PM PDT 24
Finished Jul 04 05:46:09 PM PDT 24
Peak memory 215704 kb
Host smart-99d99196-2d6a-493c-bc23-76f49db4246c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622700418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.622700418
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.4233011172
Short name T664
Test name
Test status
Simulation time 479752531236 ps
CPU time 463.33 seconds
Started Jul 04 05:40:46 PM PDT 24
Finished Jul 04 05:48:29 PM PDT 24
Peak memory 216448 kb
Host smart-19af7cea-b714-4d8f-bd26-c070448de4bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233011172 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.4233011172
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3926557364
Short name T793
Test name
Test status
Simulation time 7060937936 ps
CPU time 8.37 seconds
Started Jul 04 05:40:41 PM PDT 24
Finished Jul 04 05:40:50 PM PDT 24
Peak memory 199736 kb
Host smart-2232ee31-f6e0-49ed-be34-77007707b241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926557364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3926557364
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.899961291
Short name T862
Test name
Test status
Simulation time 45415570495 ps
CPU time 72.48 seconds
Started Jul 04 05:40:42 PM PDT 24
Finished Jul 04 05:41:55 PM PDT 24
Peak memory 199748 kb
Host smart-66b2d884-580b-4496-9f9d-d76765f0d37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899961291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.899961291
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.379653622
Short name T360
Test name
Test status
Simulation time 65488904 ps
CPU time 0.56 seconds
Started Jul 04 05:40:48 PM PDT 24
Finished Jul 04 05:40:48 PM PDT 24
Peak memory 195292 kb
Host smart-7b231326-874a-4392-ab75-9cc8ab93d34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379653622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.379653622
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2251558907
Short name T225
Test name
Test status
Simulation time 90408945634 ps
CPU time 166.43 seconds
Started Jul 04 05:40:46 PM PDT 24
Finished Jul 04 05:43:33 PM PDT 24
Peak memory 199908 kb
Host smart-c10ecf23-7642-43cb-91c5-ecde49695531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251558907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2251558907
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3025721319
Short name T657
Test name
Test status
Simulation time 138044193416 ps
CPU time 205.4 seconds
Started Jul 04 05:40:48 PM PDT 24
Finished Jul 04 05:44:14 PM PDT 24
Peak memory 199996 kb
Host smart-4330b360-85b3-46de-86ad-47559a1d3ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025721319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3025721319
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1607180294
Short name T1019
Test name
Test status
Simulation time 93941566647 ps
CPU time 19.58 seconds
Started Jul 04 05:40:53 PM PDT 24
Finished Jul 04 05:41:13 PM PDT 24
Peak memory 199472 kb
Host smart-7c49b01e-898d-44b8-a7f4-dfadd0c675d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607180294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1607180294
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3837688348
Short name T1080
Test name
Test status
Simulation time 48593144192 ps
CPU time 72.16 seconds
Started Jul 04 05:40:47 PM PDT 24
Finished Jul 04 05:42:00 PM PDT 24
Peak memory 199908 kb
Host smart-5f7f1e20-23dd-4f6c-8ef3-15b8e221f4c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837688348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3837688348
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3705223190
Short name T9
Test name
Test status
Simulation time 84809611537 ps
CPU time 245.64 seconds
Started Jul 04 05:40:47 PM PDT 24
Finished Jul 04 05:44:53 PM PDT 24
Peak memory 199880 kb
Host smart-e8dae814-3342-4ad5-97b6-0c17736b9bb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705223190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3705223190
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.401331938
Short name T771
Test name
Test status
Simulation time 9104297321 ps
CPU time 5.81 seconds
Started Jul 04 05:40:47 PM PDT 24
Finished Jul 04 05:40:53 PM PDT 24
Peak memory 198492 kb
Host smart-df47fb8f-6a91-4c30-98ff-d3e12ab28665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401331938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.401331938
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2264380149
Short name T57
Test name
Test status
Simulation time 60029332668 ps
CPU time 62.67 seconds
Started Jul 04 05:40:48 PM PDT 24
Finished Jul 04 05:41:51 PM PDT 24
Peak memory 198688 kb
Host smart-b0cf5cfa-f492-4e7b-8777-e212f25eafa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264380149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2264380149
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2594763562
Short name T1012
Test name
Test status
Simulation time 11131866982 ps
CPU time 111.67 seconds
Started Jul 04 05:40:47 PM PDT 24
Finished Jul 04 05:42:39 PM PDT 24
Peak memory 199944 kb
Host smart-78032486-cf16-441b-8e88-fe674b57e709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594763562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2594763562
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3624949616
Short name T333
Test name
Test status
Simulation time 7386164971 ps
CPU time 9.29 seconds
Started Jul 04 05:40:47 PM PDT 24
Finished Jul 04 05:40:57 PM PDT 24
Peak memory 197964 kb
Host smart-8596f1f6-b3ac-4a6b-8d95-d6ac36605bcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624949616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3624949616
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1473729112
Short name T535
Test name
Test status
Simulation time 70429688260 ps
CPU time 26.75 seconds
Started Jul 04 05:40:47 PM PDT 24
Finished Jul 04 05:41:14 PM PDT 24
Peak memory 199744 kb
Host smart-deff5053-0e99-459c-92b5-1850a383595c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473729112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1473729112
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3116717645
Short name T725
Test name
Test status
Simulation time 2157221865 ps
CPU time 4.1 seconds
Started Jul 04 05:40:47 PM PDT 24
Finished Jul 04 05:40:51 PM PDT 24
Peak memory 195516 kb
Host smart-7978c555-e17b-40ad-aa08-75b6361d5a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116717645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3116717645
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2938677537
Short name T494
Test name
Test status
Simulation time 268215013 ps
CPU time 1.32 seconds
Started Jul 04 05:40:53 PM PDT 24
Finished Jul 04 05:40:55 PM PDT 24
Peak memory 198088 kb
Host smart-5531ac46-5516-4e06-b31b-fd4c903c86f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938677537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2938677537
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2180198211
Short name T738
Test name
Test status
Simulation time 527671578256 ps
CPU time 590.25 seconds
Started Jul 04 05:40:47 PM PDT 24
Finished Jul 04 05:50:38 PM PDT 24
Peak memory 208400 kb
Host smart-c4b87959-361d-400d-8271-915a9f0e223e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180198211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2180198211
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2917357000
Short name T88
Test name
Test status
Simulation time 74006758534 ps
CPU time 602.95 seconds
Started Jul 04 05:40:47 PM PDT 24
Finished Jul 04 05:50:50 PM PDT 24
Peak memory 228884 kb
Host smart-083ab5ae-32e1-4a10-9eab-07053e1a33b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917357000 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2917357000
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1569132885
Short name T627
Test name
Test status
Simulation time 1650794911 ps
CPU time 1.93 seconds
Started Jul 04 05:40:52 PM PDT 24
Finished Jul 04 05:40:54 PM PDT 24
Peak memory 198284 kb
Host smart-e4a768db-d0b8-4eb8-b0a5-e8bc6227e110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569132885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1569132885
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3376924705
Short name T1008
Test name
Test status
Simulation time 129637920027 ps
CPU time 54.58 seconds
Started Jul 04 05:40:46 PM PDT 24
Finished Jul 04 05:41:41 PM PDT 24
Peak memory 199904 kb
Host smart-92108246-1ef5-4135-9766-205467621e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376924705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3376924705
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.764675751
Short name T1087
Test name
Test status
Simulation time 43737323 ps
CPU time 0.58 seconds
Started Jul 04 05:40:54 PM PDT 24
Finished Jul 04 05:40:54 PM PDT 24
Peak memory 194764 kb
Host smart-ec9b043e-1834-4280-bfac-fa85c9fe9d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764675751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.764675751
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.708474137
Short name T379
Test name
Test status
Simulation time 69903428491 ps
CPU time 28.37 seconds
Started Jul 04 05:40:54 PM PDT 24
Finished Jul 04 05:41:22 PM PDT 24
Peak memory 199884 kb
Host smart-07836b8b-c826-4ae3-8efc-0f8f300476be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708474137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.708474137
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1517831942
Short name T817
Test name
Test status
Simulation time 72759936745 ps
CPU time 60.24 seconds
Started Jul 04 05:40:59 PM PDT 24
Finished Jul 04 05:41:59 PM PDT 24
Peak memory 199912 kb
Host smart-192bc935-6fb5-4f4e-b15d-41aafcab0a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517831942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1517831942
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1768772441
Short name T584
Test name
Test status
Simulation time 35486629070 ps
CPU time 28.42 seconds
Started Jul 04 05:40:53 PM PDT 24
Finished Jul 04 05:41:22 PM PDT 24
Peak memory 199860 kb
Host smart-d4ae2a3e-9207-4a61-9973-7a88beeb1cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768772441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1768772441
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1832176965
Short name T1043
Test name
Test status
Simulation time 59561118901 ps
CPU time 54.5 seconds
Started Jul 04 05:40:52 PM PDT 24
Finished Jul 04 05:41:48 PM PDT 24
Peak memory 199892 kb
Host smart-34a48f14-5177-46d1-83b4-f8c80c72b415
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832176965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1832176965
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3481388379
Short name T340
Test name
Test status
Simulation time 128120570550 ps
CPU time 523.13 seconds
Started Jul 04 05:40:54 PM PDT 24
Finished Jul 04 05:49:38 PM PDT 24
Peak memory 199936 kb
Host smart-a175e209-203f-4d33-8919-e82278ad995b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481388379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3481388379
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.715655772
Short name T338
Test name
Test status
Simulation time 8529732933 ps
CPU time 5.92 seconds
Started Jul 04 05:40:55 PM PDT 24
Finished Jul 04 05:41:01 PM PDT 24
Peak memory 199816 kb
Host smart-633eafed-c82c-4d1d-97c7-6deb6e8f5035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715655772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.715655772
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3792248881
Short name T251
Test name
Test status
Simulation time 180380591187 ps
CPU time 78.84 seconds
Started Jul 04 05:40:53 PM PDT 24
Finished Jul 04 05:42:12 PM PDT 24
Peak memory 200160 kb
Host smart-ee79c353-7dd3-4e01-9aba-782181e2d8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792248881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3792248881
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3754148577
Short name T491
Test name
Test status
Simulation time 23846042896 ps
CPU time 1468.6 seconds
Started Jul 04 05:40:53 PM PDT 24
Finished Jul 04 06:05:22 PM PDT 24
Peak memory 200004 kb
Host smart-5bbb8894-8872-472a-bc99-d0ce2ea27f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754148577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3754148577
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2698312417
Short name T369
Test name
Test status
Simulation time 1699471653 ps
CPU time 9.13 seconds
Started Jul 04 05:40:53 PM PDT 24
Finished Jul 04 05:41:02 PM PDT 24
Peak memory 199040 kb
Host smart-2d242d87-3b1a-4315-8618-ff1b9d61870f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2698312417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2698312417
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2747972038
Short name T83
Test name
Test status
Simulation time 45429883122 ps
CPU time 17.15 seconds
Started Jul 04 05:40:54 PM PDT 24
Finished Jul 04 05:41:11 PM PDT 24
Peak memory 199928 kb
Host smart-d2177422-fc39-4a73-9d92-aa8339d3baba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747972038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2747972038
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3488976118
Short name T1045
Test name
Test status
Simulation time 736867523 ps
CPU time 1.14 seconds
Started Jul 04 05:40:53 PM PDT 24
Finished Jul 04 05:40:55 PM PDT 24
Peak memory 195568 kb
Host smart-686fb82e-28fe-4b95-9867-7613ff23f497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488976118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3488976118
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2524561873
Short name T825
Test name
Test status
Simulation time 249180012 ps
CPU time 1.54 seconds
Started Jul 04 05:40:48 PM PDT 24
Finished Jul 04 05:40:49 PM PDT 24
Peak memory 198944 kb
Host smart-fa12cf0c-5dd9-4ef6-b224-c1d6abc7ae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524561873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2524561873
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.444392072
Short name T591
Test name
Test status
Simulation time 178514817773 ps
CPU time 1182.63 seconds
Started Jul 04 05:40:54 PM PDT 24
Finished Jul 04 06:00:37 PM PDT 24
Peak memory 208776 kb
Host smart-152e2442-20c9-456f-886d-2556971f755e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444392072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.444392072
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1787931717
Short name T1060
Test name
Test status
Simulation time 34029823557 ps
CPU time 455.35 seconds
Started Jul 04 05:40:53 PM PDT 24
Finished Jul 04 05:48:29 PM PDT 24
Peak memory 214792 kb
Host smart-5065c8b9-2787-419f-aec9-96ef753e00d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787931717 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1787931717
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3386736235
Short name T509
Test name
Test status
Simulation time 7413404890 ps
CPU time 8.89 seconds
Started Jul 04 05:40:53 PM PDT 24
Finished Jul 04 05:41:02 PM PDT 24
Peak memory 199848 kb
Host smart-70cfc667-02a2-4ccd-97cc-5b519eb4abfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386736235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3386736235
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.326954877
Short name T542
Test name
Test status
Simulation time 26889816191 ps
CPU time 11.35 seconds
Started Jul 04 05:40:54 PM PDT 24
Finished Jul 04 05:41:05 PM PDT 24
Peak memory 197348 kb
Host smart-52a24522-912a-4725-8c8e-3b996965a474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326954877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.326954877
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2570326682
Short name T510
Test name
Test status
Simulation time 17829345 ps
CPU time 0.58 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:41:01 PM PDT 24
Peak memory 194736 kb
Host smart-b25c16e5-9d06-43ad-a617-f0561457b3a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570326682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2570326682
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1102771286
Short name T605
Test name
Test status
Simulation time 19486764304 ps
CPU time 24.8 seconds
Started Jul 04 05:40:54 PM PDT 24
Finished Jul 04 05:41:19 PM PDT 24
Peak memory 199660 kb
Host smart-851d5cc2-253c-4022-a718-bce1b15c6c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102771286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1102771286
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2180770045
Short name T646
Test name
Test status
Simulation time 52043567954 ps
CPU time 48.92 seconds
Started Jul 04 05:40:52 PM PDT 24
Finished Jul 04 05:41:41 PM PDT 24
Peak memory 200024 kb
Host smart-05467446-5d66-44c4-a43b-37880dabacea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180770045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2180770045
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3068354070
Short name T117
Test name
Test status
Simulation time 77900145444 ps
CPU time 110.29 seconds
Started Jul 04 05:40:54 PM PDT 24
Finished Jul 04 05:42:45 PM PDT 24
Peak memory 199920 kb
Host smart-d9f72032-f481-41d8-af23-dfe8913f2881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068354070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3068354070
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1151452845
Short name T673
Test name
Test status
Simulation time 68439840869 ps
CPU time 77.46 seconds
Started Jul 04 05:40:53 PM PDT 24
Finished Jul 04 05:42:11 PM PDT 24
Peak memory 199724 kb
Host smart-e90316c1-4080-4ccb-a4d4-e60bf5094530
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151452845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1151452845
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2360220012
Short name T391
Test name
Test status
Simulation time 42423815061 ps
CPU time 83.32 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:42:24 PM PDT 24
Peak memory 199864 kb
Host smart-7ca1a56c-fb53-4bdf-9f0b-305fc9e646e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360220012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2360220012
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.339734651
Short name T637
Test name
Test status
Simulation time 3624847841 ps
CPU time 7.01 seconds
Started Jul 04 05:40:59 PM PDT 24
Finished Jul 04 05:41:06 PM PDT 24
Peak memory 199976 kb
Host smart-f6bbbdea-8da2-402b-9af9-bd83dcec3376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339734651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.339734651
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2160905606
Short name T1093
Test name
Test status
Simulation time 100049924063 ps
CPU time 196.49 seconds
Started Jul 04 05:40:54 PM PDT 24
Finished Jul 04 05:44:11 PM PDT 24
Peak memory 208160 kb
Host smart-7287c12d-0e28-4b5d-b85f-1a46d459f44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160905606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2160905606
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1946951016
Short name T819
Test name
Test status
Simulation time 23246971514 ps
CPU time 965.99 seconds
Started Jul 04 05:41:01 PM PDT 24
Finished Jul 04 05:57:08 PM PDT 24
Peak memory 199984 kb
Host smart-ee13c727-2852-4653-801b-492864b57eb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946951016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1946951016
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.791699804
Short name T459
Test name
Test status
Simulation time 2553662022 ps
CPU time 3.75 seconds
Started Jul 04 05:40:54 PM PDT 24
Finished Jul 04 05:40:58 PM PDT 24
Peak memory 198192 kb
Host smart-49819824-9346-4114-9022-932e90d407ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791699804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.791699804
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.4059861293
Short name T445
Test name
Test status
Simulation time 22929261510 ps
CPU time 60.06 seconds
Started Jul 04 05:40:59 PM PDT 24
Finished Jul 04 05:41:59 PM PDT 24
Peak memory 199820 kb
Host smart-252fac09-ed27-4bf6-94d4-5ecb4dd00ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059861293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.4059861293
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1323514407
Short name T1039
Test name
Test status
Simulation time 3275628895 ps
CPU time 5.71 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:41:06 PM PDT 24
Peak memory 196376 kb
Host smart-6a454c5e-3a6b-4ff4-966e-31853a61d0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323514407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1323514407
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3961098456
Short name T38
Test name
Test status
Simulation time 120582612 ps
CPU time 0.84 seconds
Started Jul 04 05:40:52 PM PDT 24
Finished Jul 04 05:40:54 PM PDT 24
Peak memory 197012 kb
Host smart-68611b56-3f0d-4b04-8bfa-4449975300cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961098456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3961098456
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1235396888
Short name T852
Test name
Test status
Simulation time 206566423948 ps
CPU time 503.94 seconds
Started Jul 04 05:41:02 PM PDT 24
Finished Jul 04 05:49:26 PM PDT 24
Peak memory 199856 kb
Host smart-31aadb1e-f23b-4179-9f2c-5b390d8f7955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235396888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1235396888
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1393356092
Short name T521
Test name
Test status
Simulation time 6524271602 ps
CPU time 18.69 seconds
Started Jul 04 05:40:59 PM PDT 24
Finished Jul 04 05:41:18 PM PDT 24
Peak memory 199960 kb
Host smart-8a86bda2-e262-414f-b1da-367febad4a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393356092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1393356092
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.777062053
Short name T297
Test name
Test status
Simulation time 1998221638 ps
CPU time 2.64 seconds
Started Jul 04 05:40:59 PM PDT 24
Finished Jul 04 05:41:02 PM PDT 24
Peak memory 197192 kb
Host smart-64e060f6-b32f-482d-9cf6-efba967e389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777062053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.777062053
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1778436589
Short name T24
Test name
Test status
Simulation time 14337289 ps
CPU time 0.54 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:38:27 PM PDT 24
Peak memory 195252 kb
Host smart-6a5d9873-5bc1-481c-93d3-6c2fac15d2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778436589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1778436589
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3129131293
Short name T32
Test name
Test status
Simulation time 47291605104 ps
CPU time 56.85 seconds
Started Jul 04 05:38:24 PM PDT 24
Finished Jul 04 05:39:21 PM PDT 24
Peak memory 200012 kb
Host smart-35ccb6ab-bc40-4a8f-b5e9-51bb7c8eb9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129131293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3129131293
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1686418482
Short name T152
Test name
Test status
Simulation time 15111003400 ps
CPU time 19.98 seconds
Started Jul 04 05:38:23 PM PDT 24
Finished Jul 04 05:38:44 PM PDT 24
Peak memory 199884 kb
Host smart-823fd4e4-3c2a-42fc-9348-baa704d01d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686418482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1686418482
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2207857831
Short name T560
Test name
Test status
Simulation time 30754513904 ps
CPU time 15.87 seconds
Started Jul 04 05:38:20 PM PDT 24
Finished Jul 04 05:38:36 PM PDT 24
Peak memory 199964 kb
Host smart-625c70b7-7625-4ca3-a021-5a21c556437f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207857831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2207857831
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2792403848
Short name T1059
Test name
Test status
Simulation time 15945714921 ps
CPU time 7.61 seconds
Started Jul 04 05:38:23 PM PDT 24
Finished Jul 04 05:38:31 PM PDT 24
Peak memory 199876 kb
Host smart-5f7135f3-6990-40c6-bb78-418fa5bb58c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792403848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2792403848
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3640374858
Short name T372
Test name
Test status
Simulation time 95398728999 ps
CPU time 1018.9 seconds
Started Jul 04 05:38:24 PM PDT 24
Finished Jul 04 05:55:23 PM PDT 24
Peak memory 199980 kb
Host smart-477cb005-1ea3-4cb7-ab41-77ebba7180cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640374858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3640374858
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.317803372
Short name T593
Test name
Test status
Simulation time 4581459225 ps
CPU time 7.04 seconds
Started Jul 04 05:38:23 PM PDT 24
Finished Jul 04 05:38:30 PM PDT 24
Peak memory 198252 kb
Host smart-93e40e0c-c26a-43c5-8942-d454a5fbb698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317803372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.317803372
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3338733922
Short name T753
Test name
Test status
Simulation time 146803555762 ps
CPU time 62.83 seconds
Started Jul 04 05:38:17 PM PDT 24
Finished Jul 04 05:39:20 PM PDT 24
Peak memory 199992 kb
Host smart-fe741b8e-5688-4c6f-a3f8-00500c89b047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338733922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3338733922
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3100613563
Short name T568
Test name
Test status
Simulation time 14970387699 ps
CPU time 126.6 seconds
Started Jul 04 05:38:23 PM PDT 24
Finished Jul 04 05:40:30 PM PDT 24
Peak memory 199952 kb
Host smart-08c343ee-5e58-4081-809a-3d69f9d70592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100613563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3100613563
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.80955863
Short name T543
Test name
Test status
Simulation time 4917528166 ps
CPU time 39.82 seconds
Started Jul 04 05:38:20 PM PDT 24
Finished Jul 04 05:39:00 PM PDT 24
Peak memory 198088 kb
Host smart-21137802-f6a8-4c44-b705-3c461443da06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80955863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.80955863
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1783590970
Short name T451
Test name
Test status
Simulation time 102147829400 ps
CPU time 185.91 seconds
Started Jul 04 05:38:26 PM PDT 24
Finished Jul 04 05:41:32 PM PDT 24
Peak memory 199892 kb
Host smart-df955ad9-bcf3-405b-a6ad-1c60e88f8884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783590970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1783590970
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1326976570
Short name T786
Test name
Test status
Simulation time 45691648428 ps
CPU time 11.92 seconds
Started Jul 04 05:38:23 PM PDT 24
Finished Jul 04 05:38:35 PM PDT 24
Peak memory 195792 kb
Host smart-740f64a0-8c75-4666-9638-850fede890e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326976570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1326976570
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2735846289
Short name T79
Test name
Test status
Simulation time 221210392 ps
CPU time 0.84 seconds
Started Jul 04 05:38:22 PM PDT 24
Finished Jul 04 05:38:23 PM PDT 24
Peak memory 218324 kb
Host smart-5a2ce899-967a-4c11-b9a3-ebe0af6894f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735846289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2735846289
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1409537897
Short name T838
Test name
Test status
Simulation time 648715730 ps
CPU time 1.44 seconds
Started Jul 04 05:38:20 PM PDT 24
Finished Jul 04 05:38:22 PM PDT 24
Peak memory 198580 kb
Host smart-27526e11-07aa-4a3a-b486-683b4359f35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409537897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1409537897
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1357787628
Short name T165
Test name
Test status
Simulation time 856543948023 ps
CPU time 207.67 seconds
Started Jul 04 05:38:26 PM PDT 24
Finished Jul 04 05:41:54 PM PDT 24
Peak memory 199868 kb
Host smart-98ecd24a-6682-465b-b367-4039c12833c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357787628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1357787628
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1350635294
Short name T495
Test name
Test status
Simulation time 11608543918 ps
CPU time 196.71 seconds
Started Jul 04 05:38:18 PM PDT 24
Finished Jul 04 05:41:35 PM PDT 24
Peak memory 216464 kb
Host smart-36c8cf4f-342a-4af9-bc25-27d9691ac86f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350635294 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1350635294
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2999091071
Short name T1079
Test name
Test status
Simulation time 1594667023 ps
CPU time 2.3 seconds
Started Jul 04 05:38:22 PM PDT 24
Finished Jul 04 05:38:25 PM PDT 24
Peak memory 199148 kb
Host smart-e92d0bca-d639-4208-82b2-aa4ba989f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999091071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2999091071
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1329235137
Short name T899
Test name
Test status
Simulation time 129118702914 ps
CPU time 50.95 seconds
Started Jul 04 05:38:18 PM PDT 24
Finished Jul 04 05:39:09 PM PDT 24
Peak memory 199876 kb
Host smart-fcef1b28-090d-4a7e-aec8-0458432bbac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329235137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1329235137
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1750686191
Short name T387
Test name
Test status
Simulation time 34772483 ps
CPU time 0.56 seconds
Started Jul 04 05:41:07 PM PDT 24
Finished Jul 04 05:41:08 PM PDT 24
Peak memory 195304 kb
Host smart-950a36b5-0d68-4219-bd2d-7be6c73a2416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750686191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1750686191
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2683685855
Short name T821
Test name
Test status
Simulation time 26073883353 ps
CPU time 38.74 seconds
Started Jul 04 05:41:01 PM PDT 24
Finished Jul 04 05:41:40 PM PDT 24
Peak memory 199960 kb
Host smart-9130aeac-90ac-4290-80d3-efef4e0108cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683685855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2683685855
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.819099946
Short name T402
Test name
Test status
Simulation time 71183681748 ps
CPU time 110.18 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:42:50 PM PDT 24
Peak memory 199868 kb
Host smart-f3cb206c-dd83-4ce9-927b-50deee6b8a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819099946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.819099946
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3105797203
Short name T530
Test name
Test status
Simulation time 30941256024 ps
CPU time 16.02 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:41:17 PM PDT 24
Peak memory 198428 kb
Host smart-18406067-d661-4c03-9598-5f0b7b7a02f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105797203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3105797203
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3824068398
Short name T857
Test name
Test status
Simulation time 222228589 ps
CPU time 0.66 seconds
Started Jul 04 05:41:02 PM PDT 24
Finished Jul 04 05:41:03 PM PDT 24
Peak memory 195504 kb
Host smart-e16cf3da-8ea4-43b4-91f1-1565d399cc09
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824068398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3824068398
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1772793009
Short name T559
Test name
Test status
Simulation time 89406630320 ps
CPU time 311.31 seconds
Started Jul 04 05:41:14 PM PDT 24
Finished Jul 04 05:46:26 PM PDT 24
Peak memory 199852 kb
Host smart-fdb0c40a-1f42-40c2-9f30-d356e54ffee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772793009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1772793009
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1265223544
Short name T734
Test name
Test status
Simulation time 7522469865 ps
CPU time 17.78 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:41:18 PM PDT 24
Peak memory 199736 kb
Host smart-194530bf-b209-4196-95a8-463e92fec10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265223544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1265223544
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2746670529
Short name T308
Test name
Test status
Simulation time 1420496897 ps
CPU time 2.88 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:41:03 PM PDT 24
Peak memory 194512 kb
Host smart-a865a9b8-e10f-4767-bea4-d659e995a771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746670529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2746670529
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2018121239
Short name T258
Test name
Test status
Simulation time 20741970487 ps
CPU time 639.91 seconds
Started Jul 04 05:41:15 PM PDT 24
Finished Jul 04 05:51:56 PM PDT 24
Peak memory 199912 kb
Host smart-4134bdc7-1cb8-4022-a9e9-5225daaf5f33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018121239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2018121239
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.737779515
Short name T480
Test name
Test status
Simulation time 4976675575 ps
CPU time 11.45 seconds
Started Jul 04 05:41:01 PM PDT 24
Finished Jul 04 05:41:13 PM PDT 24
Peak memory 198628 kb
Host smart-9d402b29-5003-467b-aeaf-b1ad25b0e280
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=737779515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.737779515
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.271208180
Short name T511
Test name
Test status
Simulation time 123527984513 ps
CPU time 58.24 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:41:59 PM PDT 24
Peak memory 199888 kb
Host smart-21b5b7ec-1208-4d42-9b63-cadb307b00e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271208180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.271208180
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.276486182
Short name T518
Test name
Test status
Simulation time 740477412 ps
CPU time 1.82 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:41:02 PM PDT 24
Peak memory 195632 kb
Host smart-0029edd5-ed42-45b3-903e-6eeab03ac5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276486182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.276486182
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3904620220
Short name T82
Test name
Test status
Simulation time 5720094475 ps
CPU time 27.96 seconds
Started Jul 04 05:41:00 PM PDT 24
Finished Jul 04 05:41:28 PM PDT 24
Peak memory 199908 kb
Host smart-8a6e32e7-dc16-49a3-b5a0-91990a0460fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904620220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3904620220
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3082499373
Short name T1150
Test name
Test status
Simulation time 234299277641 ps
CPU time 253.48 seconds
Started Jul 04 05:41:09 PM PDT 24
Finished Jul 04 05:45:23 PM PDT 24
Peak memory 199928 kb
Host smart-f4a54b62-f720-4642-87a9-f05ff8d15a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082499373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3082499373
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3852793830
Short name T925
Test name
Test status
Simulation time 183944284595 ps
CPU time 1596.03 seconds
Started Jul 04 05:41:09 PM PDT 24
Finished Jul 04 06:07:45 PM PDT 24
Peak memory 216588 kb
Host smart-cb3a1c58-442d-42fa-8b9b-7982b7c4c26d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852793830 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3852793830
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2846112401
Short name T522
Test name
Test status
Simulation time 1051093609 ps
CPU time 2.07 seconds
Started Jul 04 05:40:59 PM PDT 24
Finished Jul 04 05:41:01 PM PDT 24
Peak memory 198228 kb
Host smart-6db083b5-d95e-48e5-9a04-5cbb4336c7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846112401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2846112401
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.723832136
Short name T460
Test name
Test status
Simulation time 43757710906 ps
CPU time 22.73 seconds
Started Jul 04 05:41:02 PM PDT 24
Finished Jul 04 05:41:25 PM PDT 24
Peak memory 199996 kb
Host smart-af1e73d2-782c-40be-890c-75b8febebcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723832136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.723832136
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2978393613
Short name T337
Test name
Test status
Simulation time 15357927 ps
CPU time 0.58 seconds
Started Jul 04 05:41:17 PM PDT 24
Finished Jul 04 05:41:17 PM PDT 24
Peak memory 195272 kb
Host smart-b412fba7-7bb3-4b56-8f64-d0d1b7c63910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978393613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2978393613
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3439715795
Short name T497
Test name
Test status
Simulation time 75965283100 ps
CPU time 61.61 seconds
Started Jul 04 05:41:07 PM PDT 24
Finished Jul 04 05:42:09 PM PDT 24
Peak memory 199956 kb
Host smart-a0d0f75f-1c78-4d43-b6c1-356e400a8d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439715795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3439715795
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.4127244275
Short name T896
Test name
Test status
Simulation time 109814141874 ps
CPU time 183.17 seconds
Started Jul 04 05:41:07 PM PDT 24
Finished Jul 04 05:44:10 PM PDT 24
Peak memory 199884 kb
Host smart-f282016f-e598-4845-8469-fab8917e3c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127244275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.4127244275
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1641277651
Short name T824
Test name
Test status
Simulation time 109987072791 ps
CPU time 250.57 seconds
Started Jul 04 05:41:09 PM PDT 24
Finished Jul 04 05:45:20 PM PDT 24
Peak memory 199876 kb
Host smart-4f465e0a-8af7-481d-92cc-af5908330e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641277651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1641277651
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3502320499
Short name T668
Test name
Test status
Simulation time 739735591343 ps
CPU time 139.28 seconds
Started Jul 04 05:41:15 PM PDT 24
Finished Jul 04 05:43:35 PM PDT 24
Peak memory 199856 kb
Host smart-1f2e94c1-2991-4c81-af06-f8c84ed3b22c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502320499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3502320499
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.445425661
Short name T294
Test name
Test status
Simulation time 321547992174 ps
CPU time 221.91 seconds
Started Jul 04 05:41:16 PM PDT 24
Finished Jul 04 05:44:58 PM PDT 24
Peak memory 199928 kb
Host smart-ce2c3164-b296-4b58-8784-6273e4ab3e27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=445425661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.445425661
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3278411300
Short name T349
Test name
Test status
Simulation time 3004211902 ps
CPU time 6.67 seconds
Started Jul 04 05:41:08 PM PDT 24
Finished Jul 04 05:41:15 PM PDT 24
Peak memory 199624 kb
Host smart-944d88eb-340f-417a-9b79-e87592f8aeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278411300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3278411300
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3383493408
Short name T934
Test name
Test status
Simulation time 53687103367 ps
CPU time 46.07 seconds
Started Jul 04 05:41:07 PM PDT 24
Finished Jul 04 05:41:53 PM PDT 24
Peak memory 199788 kb
Host smart-b8bb0ebf-4e48-4b81-8c27-1fd3b5c722e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383493408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3383493408
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2263088056
Short name T972
Test name
Test status
Simulation time 20972352599 ps
CPU time 536.55 seconds
Started Jul 04 05:41:16 PM PDT 24
Finished Jul 04 05:50:13 PM PDT 24
Peak memory 199932 kb
Host smart-f5eecc11-6f8e-46a4-a0de-10897b699b2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263088056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2263088056
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3541594258
Short name T407
Test name
Test status
Simulation time 2444122979 ps
CPU time 15.09 seconds
Started Jul 04 05:41:15 PM PDT 24
Finished Jul 04 05:41:31 PM PDT 24
Peak memory 197752 kb
Host smart-55eb1cab-3542-4c31-b64e-3feee4c6b5da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3541594258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3541594258
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1010680786
Short name T154
Test name
Test status
Simulation time 110320677750 ps
CPU time 77.01 seconds
Started Jul 04 05:41:15 PM PDT 24
Finished Jul 04 05:42:33 PM PDT 24
Peak memory 199852 kb
Host smart-459216b0-df33-4996-80e7-b16eaadd05fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010680786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1010680786
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2552366291
Short name T681
Test name
Test status
Simulation time 43526524786 ps
CPU time 4.71 seconds
Started Jul 04 05:41:06 PM PDT 24
Finished Jul 04 05:41:11 PM PDT 24
Peak memory 195776 kb
Host smart-150a0025-fd0e-46b1-9883-329ce9c1c948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552366291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2552366291
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.677682548
Short name T880
Test name
Test status
Simulation time 117545861 ps
CPU time 0.83 seconds
Started Jul 04 05:41:15 PM PDT 24
Finished Jul 04 05:41:17 PM PDT 24
Peak memory 196860 kb
Host smart-c91cf35d-61e0-4d53-b081-10bd0940d207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677682548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.677682548
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2572386535
Short name T644
Test name
Test status
Simulation time 376823176588 ps
CPU time 533.52 seconds
Started Jul 04 05:41:14 PM PDT 24
Finished Jul 04 05:50:08 PM PDT 24
Peak memory 208376 kb
Host smart-0ed74258-9834-4e6b-ae5f-db0ce69a2581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572386535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2572386535
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1641665784
Short name T406
Test name
Test status
Simulation time 372595395128 ps
CPU time 1284.37 seconds
Started Jul 04 05:41:16 PM PDT 24
Finished Jul 04 06:02:41 PM PDT 24
Peak memory 224912 kb
Host smart-d3d930f2-2ac2-4078-82db-04d84c9c42a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641665784 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1641665784
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1764153468
Short name T746
Test name
Test status
Simulation time 7241534492 ps
CPU time 22.87 seconds
Started Jul 04 05:41:07 PM PDT 24
Finished Jul 04 05:41:30 PM PDT 24
Peak memory 199456 kb
Host smart-6522c1dd-d2b9-4f64-adbc-8d64b2410816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764153468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1764153468
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.190342925
Short name T744
Test name
Test status
Simulation time 95747358802 ps
CPU time 43.55 seconds
Started Jul 04 05:41:06 PM PDT 24
Finished Jul 04 05:41:50 PM PDT 24
Peak memory 199952 kb
Host smart-b69020a8-f66b-4331-a6d6-793b7eae1637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190342925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.190342925
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1041251410
Short name T1152
Test name
Test status
Simulation time 53251335 ps
CPU time 0.6 seconds
Started Jul 04 05:41:17 PM PDT 24
Finished Jul 04 05:41:18 PM PDT 24
Peak memory 195240 kb
Host smart-43ccdd35-d70a-4417-9e60-cba302eda863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041251410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1041251410
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3460058237
Short name T53
Test name
Test status
Simulation time 37563180010 ps
CPU time 65.54 seconds
Started Jul 04 05:41:17 PM PDT 24
Finished Jul 04 05:42:22 PM PDT 24
Peak memory 199964 kb
Host smart-78ea5bb8-b6c1-41ca-8d7f-8ace35653fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460058237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3460058237
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1109510499
Short name T501
Test name
Test status
Simulation time 108555148801 ps
CPU time 19.96 seconds
Started Jul 04 05:41:16 PM PDT 24
Finished Jul 04 05:41:36 PM PDT 24
Peak memory 199924 kb
Host smart-95bbee12-9f70-4690-b438-01fb0be96c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109510499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1109510499
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1242936665
Short name T811
Test name
Test status
Simulation time 257381378935 ps
CPU time 27.36 seconds
Started Jul 04 05:41:15 PM PDT 24
Finished Jul 04 05:41:42 PM PDT 24
Peak memory 199980 kb
Host smart-947c5c6c-6bae-4223-9609-6e3d1d40f42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242936665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1242936665
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3280895480
Short name T1015
Test name
Test status
Simulation time 31988970640 ps
CPU time 32.34 seconds
Started Jul 04 05:41:17 PM PDT 24
Finished Jul 04 05:41:49 PM PDT 24
Peak memory 199820 kb
Host smart-1cf2bccd-b688-42d7-bd88-e3a633dca7e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280895480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3280895480
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4010310636
Short name T1038
Test name
Test status
Simulation time 63599307954 ps
CPU time 165.01 seconds
Started Jul 04 05:41:16 PM PDT 24
Finished Jul 04 05:44:01 PM PDT 24
Peak memory 199952 kb
Host smart-97f5a99b-a481-4382-9337-e6f46205e00b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010310636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4010310636
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2688435899
Short name T330
Test name
Test status
Simulation time 1925856146 ps
CPU time 4.6 seconds
Started Jul 04 05:41:16 PM PDT 24
Finished Jul 04 05:41:21 PM PDT 24
Peak memory 199928 kb
Host smart-600a5e3a-4379-4165-9fd0-31c6a1b6a61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688435899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2688435899
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1089699928
Short name T687
Test name
Test status
Simulation time 110911681661 ps
CPU time 43.78 seconds
Started Jul 04 05:41:16 PM PDT 24
Finished Jul 04 05:42:00 PM PDT 24
Peak memory 198960 kb
Host smart-6df8296b-e52b-4cd1-9894-c8f9f9db2457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089699928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1089699928
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.134092713
Short name T721
Test name
Test status
Simulation time 1490622043 ps
CPU time 63.24 seconds
Started Jul 04 05:41:16 PM PDT 24
Finished Jul 04 05:42:19 PM PDT 24
Peak memory 199848 kb
Host smart-ddc4f384-7e37-4964-b32d-0f775b8b1e70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134092713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.134092713
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.462868080
Short name T469
Test name
Test status
Simulation time 1696970116 ps
CPU time 9.38 seconds
Started Jul 04 05:41:15 PM PDT 24
Finished Jul 04 05:41:25 PM PDT 24
Peak memory 198096 kb
Host smart-7a8b53fb-e4a6-4ef8-b706-86450ad14a11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462868080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.462868080
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.604393688
Short name T404
Test name
Test status
Simulation time 160002315246 ps
CPU time 132.86 seconds
Started Jul 04 05:41:21 PM PDT 24
Finished Jul 04 05:43:34 PM PDT 24
Peak memory 199932 kb
Host smart-678098c0-973a-4259-9318-d79b54114201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604393688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.604393688
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3541847605
Short name T505
Test name
Test status
Simulation time 6041011835 ps
CPU time 3.29 seconds
Started Jul 04 05:41:17 PM PDT 24
Finished Jul 04 05:41:20 PM PDT 24
Peak memory 195940 kb
Host smart-71dc5037-2e7d-4794-b426-f81201660f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541847605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3541847605
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2733874413
Short name T347
Test name
Test status
Simulation time 977809728 ps
CPU time 3.4 seconds
Started Jul 04 05:41:15 PM PDT 24
Finished Jul 04 05:41:19 PM PDT 24
Peak memory 198760 kb
Host smart-e0390949-427b-4322-abc6-69a990752050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733874413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2733874413
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2349317276
Short name T60
Test name
Test status
Simulation time 85165518145 ps
CPU time 815.17 seconds
Started Jul 04 05:41:17 PM PDT 24
Finished Jul 04 05:54:52 PM PDT 24
Peak memory 216508 kb
Host smart-b87264d5-8ec1-462d-9891-3c9e882d03fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349317276 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2349317276
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.4212822904
Short name T574
Test name
Test status
Simulation time 1246056168 ps
CPU time 2.28 seconds
Started Jul 04 05:41:16 PM PDT 24
Finished Jul 04 05:41:19 PM PDT 24
Peak memory 199884 kb
Host smart-eb881b61-ac9b-4d29-b3c8-6ef6de4edbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212822904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.4212822904
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3114372018
Short name T678
Test name
Test status
Simulation time 55836692783 ps
CPU time 20.05 seconds
Started Jul 04 05:41:15 PM PDT 24
Finished Jul 04 05:41:36 PM PDT 24
Peak memory 199892 kb
Host smart-c0f839de-6e29-4dd4-9875-4cd28cbea92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114372018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3114372018
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2069860351
Short name T431
Test name
Test status
Simulation time 58500386 ps
CPU time 0.54 seconds
Started Jul 04 05:41:23 PM PDT 24
Finished Jul 04 05:41:24 PM PDT 24
Peak memory 194764 kb
Host smart-92594902-7d0c-41fd-8cc7-ed87bf4cf8dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069860351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2069860351
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.4188127941
Short name T917
Test name
Test status
Simulation time 138151334662 ps
CPU time 421.99 seconds
Started Jul 04 05:41:22 PM PDT 24
Finished Jul 04 05:48:24 PM PDT 24
Peak memory 199892 kb
Host smart-3b1203da-e465-4ddc-b779-6269f81865a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188127941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.4188127941
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1753731619
Short name T516
Test name
Test status
Simulation time 63208171131 ps
CPU time 96.21 seconds
Started Jul 04 05:41:22 PM PDT 24
Finished Jul 04 05:42:58 PM PDT 24
Peak memory 199888 kb
Host smart-dac6b5de-1507-40cc-acd8-94c771472899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753731619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1753731619
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2405258787
Short name T1124
Test name
Test status
Simulation time 131939282203 ps
CPU time 195.95 seconds
Started Jul 04 05:41:23 PM PDT 24
Finished Jul 04 05:44:39 PM PDT 24
Peak memory 200012 kb
Host smart-58299969-1b4e-4da1-8f38-237bcd5cef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405258787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2405258787
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.4255771176
Short name T307
Test name
Test status
Simulation time 414325522415 ps
CPU time 297.72 seconds
Started Jul 04 05:41:25 PM PDT 24
Finished Jul 04 05:46:23 PM PDT 24
Peak memory 199552 kb
Host smart-8d2e75c1-fbe1-45dc-9d45-011822ad9602
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255771176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4255771176
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3936559373
Short name T1099
Test name
Test status
Simulation time 224381068562 ps
CPU time 369.04 seconds
Started Jul 04 05:41:25 PM PDT 24
Finished Jul 04 05:47:35 PM PDT 24
Peak memory 199944 kb
Host smart-f42372de-70b4-4962-95bc-64b24c191968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936559373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3936559373
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2397351820
Short name T1018
Test name
Test status
Simulation time 7334124223 ps
CPU time 3.42 seconds
Started Jul 04 05:41:22 PM PDT 24
Finished Jul 04 05:41:25 PM PDT 24
Peak memory 198872 kb
Host smart-73173475-3bdd-4776-90e2-3b3bbcc0a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397351820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2397351820
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1979900408
Short name T249
Test name
Test status
Simulation time 106770206743 ps
CPU time 48.15 seconds
Started Jul 04 05:41:28 PM PDT 24
Finished Jul 04 05:42:17 PM PDT 24
Peak memory 199648 kb
Host smart-d41463d0-0cb5-4665-8d2a-f1ed10b9aeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979900408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1979900408
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2979103330
Short name T536
Test name
Test status
Simulation time 2932693423 ps
CPU time 142.26 seconds
Started Jul 04 05:41:27 PM PDT 24
Finished Jul 04 05:43:49 PM PDT 24
Peak memory 199900 kb
Host smart-79f38dd8-8e78-42a1-89b2-294ef199a7cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979103330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2979103330
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.130362644
Short name T1171
Test name
Test status
Simulation time 2132450612 ps
CPU time 6.38 seconds
Started Jul 04 05:41:27 PM PDT 24
Finished Jul 04 05:41:33 PM PDT 24
Peak memory 198592 kb
Host smart-925380ac-f285-4e0f-a162-e629dcd9a496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130362644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.130362644
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3850476699
Short name T739
Test name
Test status
Simulation time 105416028115 ps
CPU time 45.14 seconds
Started Jul 04 05:41:22 PM PDT 24
Finished Jul 04 05:42:07 PM PDT 24
Peak memory 199892 kb
Host smart-b203dada-d57a-4bee-8262-6d0afd16c0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850476699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3850476699
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.517164700
Short name T607
Test name
Test status
Simulation time 1928199968 ps
CPU time 3.69 seconds
Started Jul 04 05:41:22 PM PDT 24
Finished Jul 04 05:41:26 PM PDT 24
Peak memory 195392 kb
Host smart-5eab8ca6-681b-4df5-ac55-91683ef4dd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517164700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.517164700
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.430965985
Short name T467
Test name
Test status
Simulation time 629068907 ps
CPU time 4.09 seconds
Started Jul 04 05:41:15 PM PDT 24
Finished Jul 04 05:41:19 PM PDT 24
Peak memory 198896 kb
Host smart-33b7c0c7-4a60-424c-b7cd-622facf70726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430965985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.430965985
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1606042961
Short name T247
Test name
Test status
Simulation time 50476348628 ps
CPU time 625.88 seconds
Started Jul 04 05:41:26 PM PDT 24
Finished Jul 04 05:51:52 PM PDT 24
Peak memory 199900 kb
Host smart-cc40b9eb-b576-48d2-a4b5-bbbf5257758c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606042961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1606042961
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1369489817
Short name T28
Test name
Test status
Simulation time 66868925413 ps
CPU time 173.01 seconds
Started Jul 04 05:41:27 PM PDT 24
Finished Jul 04 05:44:20 PM PDT 24
Peak memory 216668 kb
Host smart-e68123fb-7573-4aae-a41f-a8dfd7ec87a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369489817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1369489817
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1143348017
Short name T1050
Test name
Test status
Simulation time 12833482327 ps
CPU time 17.25 seconds
Started Jul 04 05:41:22 PM PDT 24
Finished Jul 04 05:41:39 PM PDT 24
Peak memory 199884 kb
Host smart-e533ef7f-8885-4345-952b-1e54997cf7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143348017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1143348017
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1727268330
Short name T400
Test name
Test status
Simulation time 96253440809 ps
CPU time 95.03 seconds
Started Jul 04 05:41:16 PM PDT 24
Finished Jul 04 05:42:52 PM PDT 24
Peak memory 199856 kb
Host smart-a6ece999-e9e6-46b0-bb82-68a89af905ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727268330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1727268330
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1057679057
Short name T889
Test name
Test status
Simulation time 42133903 ps
CPU time 0.53 seconds
Started Jul 04 05:41:30 PM PDT 24
Finished Jul 04 05:41:30 PM PDT 24
Peak memory 194240 kb
Host smart-8b815b29-7634-4aa3-8c7e-7a0f9351d0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057679057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1057679057
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2315631823
Short name T121
Test name
Test status
Simulation time 157198105987 ps
CPU time 134.14 seconds
Started Jul 04 05:41:22 PM PDT 24
Finished Jul 04 05:43:37 PM PDT 24
Peak memory 200012 kb
Host smart-1b275000-5fba-4fe6-a81b-3a6b9b31f5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315631823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2315631823
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3587700495
Short name T350
Test name
Test status
Simulation time 64869432531 ps
CPU time 29.17 seconds
Started Jul 04 05:41:23 PM PDT 24
Finished Jul 04 05:41:52 PM PDT 24
Peak memory 199940 kb
Host smart-516a316a-24de-4b60-aba1-7e4b65eb4a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587700495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3587700495
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2771916539
Short name T183
Test name
Test status
Simulation time 196146089923 ps
CPU time 144.94 seconds
Started Jul 04 05:41:20 PM PDT 24
Finished Jul 04 05:43:45 PM PDT 24
Peak memory 199924 kb
Host smart-f31c6773-853b-4dea-b30e-021e34a91c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771916539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2771916539
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2321442424
Short name T452
Test name
Test status
Simulation time 61867933243 ps
CPU time 16.83 seconds
Started Jul 04 05:41:24 PM PDT 24
Finished Jul 04 05:41:41 PM PDT 24
Peak memory 199736 kb
Host smart-755cea74-030e-426e-af6a-d6c1c3d64f22
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321442424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2321442424
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.371253700
Short name T231
Test name
Test status
Simulation time 134091064502 ps
CPU time 345.59 seconds
Started Jul 04 05:41:28 PM PDT 24
Finished Jul 04 05:47:14 PM PDT 24
Peak memory 199968 kb
Host smart-49c617ba-cc0d-4c42-9696-83aaa859beaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371253700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.371253700
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1882179694
Short name T808
Test name
Test status
Simulation time 540512279 ps
CPU time 1.87 seconds
Started Jul 04 05:41:30 PM PDT 24
Finished Jul 04 05:41:32 PM PDT 24
Peak memory 198448 kb
Host smart-ae775b25-cc9c-4fb2-a7c5-607618c3178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882179694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1882179694
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.4281376765
Short name T278
Test name
Test status
Simulation time 20780115972 ps
CPU time 18.32 seconds
Started Jul 04 05:41:26 PM PDT 24
Finished Jul 04 05:41:45 PM PDT 24
Peak memory 199752 kb
Host smart-410b6403-df56-431a-8b6e-af9a5d65eef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281376765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.4281376765
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3447629765
Short name T1086
Test name
Test status
Simulation time 8106980894 ps
CPU time 194.24 seconds
Started Jul 04 05:41:30 PM PDT 24
Finished Jul 04 05:44:45 PM PDT 24
Peak memory 199984 kb
Host smart-fc1a66fd-fef0-4ab7-a83c-7c89a71dd6bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447629765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3447629765
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1719667707
Short name T416
Test name
Test status
Simulation time 7755964159 ps
CPU time 33.58 seconds
Started Jul 04 05:41:23 PM PDT 24
Finished Jul 04 05:41:57 PM PDT 24
Peak memory 198072 kb
Host smart-3fb7102f-0925-4e3e-98c1-2e50385ff782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719667707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1719667707
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2867924426
Short name T549
Test name
Test status
Simulation time 82874943996 ps
CPU time 28.68 seconds
Started Jul 04 05:41:22 PM PDT 24
Finished Jul 04 05:41:51 PM PDT 24
Peak memory 198956 kb
Host smart-945f9dc4-76d1-4b1c-ae43-4655b1487fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867924426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2867924426
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.760687981
Short name T55
Test name
Test status
Simulation time 845492140 ps
CPU time 1.82 seconds
Started Jul 04 05:41:26 PM PDT 24
Finished Jul 04 05:41:28 PM PDT 24
Peak memory 195572 kb
Host smart-dfa01634-712c-4197-913d-64524df21315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760687981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.760687981
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.527947327
Short name T392
Test name
Test status
Simulation time 472509799 ps
CPU time 2.1 seconds
Started Jul 04 05:41:22 PM PDT 24
Finished Jul 04 05:41:24 PM PDT 24
Peak memory 198800 kb
Host smart-d3318a24-c2b1-4f58-b366-d45288234245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527947327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.527947327
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1548936444
Short name T230
Test name
Test status
Simulation time 130771404333 ps
CPU time 425.51 seconds
Started Jul 04 05:41:28 PM PDT 24
Finished Jul 04 05:48:34 PM PDT 24
Peak memory 199980 kb
Host smart-356808cd-0d48-4a48-b3c0-19c1098589b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548936444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1548936444
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2097706272
Short name T1013
Test name
Test status
Simulation time 77641131954 ps
CPU time 748.81 seconds
Started Jul 04 05:41:30 PM PDT 24
Finished Jul 04 05:53:59 PM PDT 24
Peak memory 216520 kb
Host smart-c50dae6b-03e4-4aa5-871c-05c355ee1918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097706272 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2097706272
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1776432274
Short name T1166
Test name
Test status
Simulation time 1135826980 ps
CPU time 1.88 seconds
Started Jul 04 05:41:22 PM PDT 24
Finished Jul 04 05:41:24 PM PDT 24
Peak memory 198828 kb
Host smart-444e6545-95b8-4967-bcf6-3e588a27c47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776432274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1776432274
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.872037091
Short name T860
Test name
Test status
Simulation time 55107505614 ps
CPU time 90.49 seconds
Started Jul 04 05:41:23 PM PDT 24
Finished Jul 04 05:42:53 PM PDT 24
Peak memory 199916 kb
Host smart-1ffe3f41-dea5-493c-8afc-beac5786d34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872037091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.872037091
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2280884324
Short name T523
Test name
Test status
Simulation time 48752324 ps
CPU time 0.56 seconds
Started Jul 04 05:41:28 PM PDT 24
Finished Jul 04 05:41:29 PM PDT 24
Peak memory 195340 kb
Host smart-75fc68ca-a51e-4746-960a-cd5661bccad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280884324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2280884324
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1997778488
Short name T787
Test name
Test status
Simulation time 60824190093 ps
CPU time 98.97 seconds
Started Jul 04 05:41:37 PM PDT 24
Finished Jul 04 05:43:16 PM PDT 24
Peak memory 199996 kb
Host smart-6e773d78-7379-4a75-88bc-5ba12241d356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997778488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1997778488
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.723113123
Short name T158
Test name
Test status
Simulation time 38902469999 ps
CPU time 57.84 seconds
Started Jul 04 05:41:28 PM PDT 24
Finished Jul 04 05:42:26 PM PDT 24
Peak memory 199964 kb
Host smart-e895d26e-2eab-4a77-8b84-8f42da2a1ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723113123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.723113123
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.985638014
Short name T837
Test name
Test status
Simulation time 142933019315 ps
CPU time 178.22 seconds
Started Jul 04 05:41:29 PM PDT 24
Finished Jul 04 05:44:28 PM PDT 24
Peak memory 199968 kb
Host smart-52de5777-1ba5-4ffc-8dfb-58dab4efc75a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985638014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.985638014
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2691868191
Short name T792
Test name
Test status
Simulation time 129626252138 ps
CPU time 624.78 seconds
Started Jul 04 05:41:30 PM PDT 24
Finished Jul 04 05:51:55 PM PDT 24
Peak memory 199840 kb
Host smart-9f1c7549-85ec-4481-95e7-f95b7910be10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691868191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2691868191
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2101570454
Short name T942
Test name
Test status
Simulation time 2018663853 ps
CPU time 1.43 seconds
Started Jul 04 05:41:30 PM PDT 24
Finished Jul 04 05:41:32 PM PDT 24
Peak memory 196184 kb
Host smart-74676d6a-a155-4a68-b7b7-619dfd8bd4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101570454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2101570454
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.184405760
Short name T847
Test name
Test status
Simulation time 94960588174 ps
CPU time 189.14 seconds
Started Jul 04 05:41:29 PM PDT 24
Finished Jul 04 05:44:38 PM PDT 24
Peak memory 200156 kb
Host smart-06fe95dc-4d9c-4dfe-8091-8e97827db9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184405760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.184405760
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3939880083
Short name T1085
Test name
Test status
Simulation time 10550792865 ps
CPU time 249.52 seconds
Started Jul 04 05:41:36 PM PDT 24
Finished Jul 04 05:45:46 PM PDT 24
Peak memory 200028 kb
Host smart-501e0e22-6da8-4826-943a-8145069b1956
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939880083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3939880083
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.680207282
Short name T933
Test name
Test status
Simulation time 4012295867 ps
CPU time 29.43 seconds
Started Jul 04 05:41:27 PM PDT 24
Finished Jul 04 05:41:57 PM PDT 24
Peak memory 198472 kb
Host smart-f6dc4e68-0067-49a4-9cba-301c4369755c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=680207282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.680207282
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1185832044
Short name T548
Test name
Test status
Simulation time 78443655345 ps
CPU time 92.29 seconds
Started Jul 04 05:41:29 PM PDT 24
Finished Jul 04 05:43:02 PM PDT 24
Peak memory 200184 kb
Host smart-097d2959-e45b-4152-ab96-fae7eb2de23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185832044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1185832044
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1146526040
Short name T1078
Test name
Test status
Simulation time 37598036890 ps
CPU time 13.98 seconds
Started Jul 04 05:41:29 PM PDT 24
Finished Jul 04 05:41:43 PM PDT 24
Peak memory 195752 kb
Host smart-ad5fd76f-50c8-4ed2-bc5b-f506db433f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146526040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1146526040
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.499927678
Short name T473
Test name
Test status
Simulation time 701097361 ps
CPU time 2.44 seconds
Started Jul 04 05:41:28 PM PDT 24
Finished Jul 04 05:41:31 PM PDT 24
Peak memory 199464 kb
Host smart-b7deecbf-3113-41ae-835b-68e08fb3a3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499927678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.499927678
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3993358136
Short name T1125
Test name
Test status
Simulation time 2553110083 ps
CPU time 2.72 seconds
Started Jul 04 05:41:28 PM PDT 24
Finished Jul 04 05:41:31 PM PDT 24
Peak memory 199092 kb
Host smart-c4e5e835-2830-48e8-8224-f9f8a3e200a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993358136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3993358136
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.288225284
Short name T466
Test name
Test status
Simulation time 14491948572 ps
CPU time 21.22 seconds
Started Jul 04 05:41:37 PM PDT 24
Finished Jul 04 05:41:58 PM PDT 24
Peak memory 199900 kb
Host smart-42cab55b-cc3a-490f-9761-2b55a4df655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288225284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.288225284
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.806848952
Short name T617
Test name
Test status
Simulation time 22453076 ps
CPU time 0.54 seconds
Started Jul 04 05:41:43 PM PDT 24
Finished Jul 04 05:41:44 PM PDT 24
Peak memory 195604 kb
Host smart-8e091d28-b4c9-4d0b-93b2-3c22e4acfb42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806848952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.806848952
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1363072499
Short name T227
Test name
Test status
Simulation time 127222750587 ps
CPU time 239.39 seconds
Started Jul 04 05:41:37 PM PDT 24
Finished Jul 04 05:45:36 PM PDT 24
Peak memory 199984 kb
Host smart-9b89679c-ab30-455a-853a-2e4001b2fe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363072499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1363072499
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2615316939
Short name T529
Test name
Test status
Simulation time 68920416240 ps
CPU time 100.68 seconds
Started Jul 04 05:41:30 PM PDT 24
Finished Jul 04 05:43:11 PM PDT 24
Peak memory 199916 kb
Host smart-dac212a8-2e33-4a57-a75e-15f983669fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615316939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2615316939
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3894010932
Short name T163
Test name
Test status
Simulation time 31374086116 ps
CPU time 49.43 seconds
Started Jul 04 05:41:37 PM PDT 24
Finished Jul 04 05:42:27 PM PDT 24
Peak memory 199932 kb
Host smart-7996736f-5d04-4334-b6d6-3e0879f72c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894010932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3894010932
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1787075096
Short name T634
Test name
Test status
Simulation time 49002248285 ps
CPU time 44.5 seconds
Started Jul 04 05:41:38 PM PDT 24
Finished Jul 04 05:42:23 PM PDT 24
Peak memory 199984 kb
Host smart-a59b5f57-098b-4345-811b-f44f6639ca30
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787075096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1787075096
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.639397458
Short name T343
Test name
Test status
Simulation time 175248268461 ps
CPU time 1210.46 seconds
Started Jul 04 05:41:37 PM PDT 24
Finished Jul 04 06:01:47 PM PDT 24
Peak memory 199956 kb
Host smart-d20d7c25-ab8b-4f81-a559-b89f10478262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639397458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.639397458
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2694855949
Short name T785
Test name
Test status
Simulation time 1979495940 ps
CPU time 5.98 seconds
Started Jul 04 05:41:35 PM PDT 24
Finished Jul 04 05:41:42 PM PDT 24
Peak memory 198968 kb
Host smart-5b459e3f-be8b-427c-8750-7d0c93fe7f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694855949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2694855949
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2071167017
Short name T324
Test name
Test status
Simulation time 41802333112 ps
CPU time 69.31 seconds
Started Jul 04 05:41:36 PM PDT 24
Finished Jul 04 05:42:46 PM PDT 24
Peak memory 200080 kb
Host smart-74f540b2-a463-497a-bf7e-e05544e55db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071167017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2071167017
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2602944408
Short name T684
Test name
Test status
Simulation time 17528875267 ps
CPU time 438.67 seconds
Started Jul 04 05:41:36 PM PDT 24
Finished Jul 04 05:48:54 PM PDT 24
Peak memory 200004 kb
Host smart-93c54bed-8b41-41a6-8eeb-f3bca1fc4bb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602944408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2602944408
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1854706264
Short name T503
Test name
Test status
Simulation time 5553822146 ps
CPU time 4.56 seconds
Started Jul 04 05:41:36 PM PDT 24
Finished Jul 04 05:41:41 PM PDT 24
Peak memory 199088 kb
Host smart-f5eadfaf-dc9b-4407-9621-7fc34b57a2fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1854706264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1854706264
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3514722088
Short name T377
Test name
Test status
Simulation time 41529763053 ps
CPU time 17.6 seconds
Started Jul 04 05:41:35 PM PDT 24
Finished Jul 04 05:41:53 PM PDT 24
Peak memory 199576 kb
Host smart-a3bc40be-d64b-42f9-b8a3-c88efaacbd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514722088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3514722088
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.736691688
Short name T806
Test name
Test status
Simulation time 5215405521 ps
CPU time 1.43 seconds
Started Jul 04 05:41:36 PM PDT 24
Finished Jul 04 05:41:38 PM PDT 24
Peak memory 196048 kb
Host smart-7676ef14-8065-4fe6-b07a-d7195f922d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736691688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.736691688
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1254465128
Short name T410
Test name
Test status
Simulation time 5436452990 ps
CPU time 19.08 seconds
Started Jul 04 05:41:29 PM PDT 24
Finished Jul 04 05:41:48 PM PDT 24
Peak memory 199332 kb
Host smart-3466fdbb-a2b6-4e52-aa5f-cd07cdcc4e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254465128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1254465128
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3766141644
Short name T765
Test name
Test status
Simulation time 76857389163 ps
CPU time 178.33 seconds
Started Jul 04 05:41:42 PM PDT 24
Finished Jul 04 05:44:41 PM PDT 24
Peak memory 199960 kb
Host smart-8de873bf-2c6d-4fa3-92e5-9ae7b84ec6a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766141644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3766141644
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.511254770
Short name T485
Test name
Test status
Simulation time 177044965675 ps
CPU time 707.63 seconds
Started Jul 04 05:41:36 PM PDT 24
Finished Jul 04 05:53:24 PM PDT 24
Peak memory 224784 kb
Host smart-5156ca60-13e3-499a-90cd-8c46002304e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511254770 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.511254770
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2327885395
Short name T293
Test name
Test status
Simulation time 7627287760 ps
CPU time 11.91 seconds
Started Jul 04 05:41:37 PM PDT 24
Finished Jul 04 05:41:49 PM PDT 24
Peak memory 199852 kb
Host smart-9d316f7b-5e1d-4bbe-8835-503452fa05eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327885395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2327885395
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3954658793
Short name T706
Test name
Test status
Simulation time 26603197162 ps
CPU time 29.42 seconds
Started Jul 04 05:41:36 PM PDT 24
Finished Jul 04 05:42:06 PM PDT 24
Peak memory 199940 kb
Host smart-9f36879c-7beb-4cbd-876a-7f8ac83ce730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954658793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3954658793
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1241158705
Short name T940
Test name
Test status
Simulation time 34575642 ps
CPU time 0.56 seconds
Started Jul 04 05:41:42 PM PDT 24
Finished Jul 04 05:41:43 PM PDT 24
Peak memory 195608 kb
Host smart-27560ddf-a748-41dc-8ca5-66319ea5906b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241158705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1241158705
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1691521765
Short name T405
Test name
Test status
Simulation time 206452391569 ps
CPU time 483.58 seconds
Started Jul 04 05:41:41 PM PDT 24
Finished Jul 04 05:49:45 PM PDT 24
Peak memory 199940 kb
Host smart-0fceca17-0050-4320-9b4c-fc9e08c46dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691521765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1691521765
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3596589998
Short name T3
Test name
Test status
Simulation time 12428886117 ps
CPU time 24.7 seconds
Started Jul 04 05:41:50 PM PDT 24
Finished Jul 04 05:42:15 PM PDT 24
Peak memory 199996 kb
Host smart-fbad104a-298b-496f-9e78-1869ecd500f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596589998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3596589998
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1576488680
Short name T325
Test name
Test status
Simulation time 30142421384 ps
CPU time 14.48 seconds
Started Jul 04 05:41:43 PM PDT 24
Finished Jul 04 05:41:58 PM PDT 24
Peak memory 199880 kb
Host smart-cb059f1f-3aba-4068-89fb-a5f4174fc1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576488680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1576488680
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.571122958
Short name T1082
Test name
Test status
Simulation time 24532189931 ps
CPU time 12.77 seconds
Started Jul 04 05:41:48 PM PDT 24
Finished Jul 04 05:42:01 PM PDT 24
Peak memory 199944 kb
Host smart-42cacb6b-bb4b-4ef6-9691-5d1fad49e54a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571122958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.571122958
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3537890704
Short name T766
Test name
Test status
Simulation time 172841527025 ps
CPU time 332.98 seconds
Started Jul 04 05:41:42 PM PDT 24
Finished Jul 04 05:47:16 PM PDT 24
Peak memory 199996 kb
Host smart-8b3846dd-28e1-4ce0-b127-909ba0e9c97b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537890704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3537890704
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1756024888
Short name T585
Test name
Test status
Simulation time 2601335189 ps
CPU time 1.38 seconds
Started Jul 04 05:41:45 PM PDT 24
Finished Jul 04 05:41:46 PM PDT 24
Peak memory 196296 kb
Host smart-656f9e8e-663c-4fb9-9898-04a61defc14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756024888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1756024888
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3098818338
Short name T683
Test name
Test status
Simulation time 149887752803 ps
CPU time 104.57 seconds
Started Jul 04 05:41:43 PM PDT 24
Finished Jul 04 05:43:27 PM PDT 24
Peak memory 208320 kb
Host smart-5bc71812-cd56-413b-87cf-eaf3545db5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098818338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3098818338
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.4191743550
Short name T422
Test name
Test status
Simulation time 15867697942 ps
CPU time 110.34 seconds
Started Jul 04 05:41:42 PM PDT 24
Finished Jul 04 05:43:33 PM PDT 24
Peak memory 199984 kb
Host smart-3aee5d24-949a-4cac-8f1c-b6550daff926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191743550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4191743550
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3135233176
Short name T961
Test name
Test status
Simulation time 4524946792 ps
CPU time 16.93 seconds
Started Jul 04 05:41:44 PM PDT 24
Finished Jul 04 05:42:01 PM PDT 24
Peak memory 199296 kb
Host smart-b79562d3-ab66-4202-a966-bba8f27ca48e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135233176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3135233176
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1252623465
Short name T115
Test name
Test status
Simulation time 53528254330 ps
CPU time 84.29 seconds
Started Jul 04 05:41:43 PM PDT 24
Finished Jul 04 05:43:08 PM PDT 24
Peak memory 199872 kb
Host smart-98114e7b-c4ba-48a1-b244-58ddf391e6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252623465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1252623465
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4173907769
Short name T888
Test name
Test status
Simulation time 552105359 ps
CPU time 1.06 seconds
Started Jul 04 05:41:42 PM PDT 24
Finished Jul 04 05:41:44 PM PDT 24
Peak memory 195592 kb
Host smart-f508dcdc-49aa-411c-a2c5-bf2b1a6cee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173907769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4173907769
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3708955181
Short name T54
Test name
Test status
Simulation time 524063077 ps
CPU time 1.37 seconds
Started Jul 04 05:41:43 PM PDT 24
Finished Jul 04 05:41:45 PM PDT 24
Peak memory 198732 kb
Host smart-ab3e0e3a-6ef9-48d8-82f9-0ac3388f6269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708955181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3708955181
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1956730574
Short name T550
Test name
Test status
Simulation time 77634796678 ps
CPU time 34.02 seconds
Started Jul 04 05:41:41 PM PDT 24
Finished Jul 04 05:42:15 PM PDT 24
Peak memory 199984 kb
Host smart-2f8eabd6-4e15-4398-8b6a-a6a58c6d4c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956730574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1956730574
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.50977608
Short name T46
Test name
Test status
Simulation time 168885298880 ps
CPU time 869.84 seconds
Started Jul 04 05:41:43 PM PDT 24
Finished Jul 04 05:56:14 PM PDT 24
Peak memory 225624 kb
Host smart-092c02eb-3b7b-41e1-9f86-4fc5633daaff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50977608 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.50977608
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1672885378
Short name T579
Test name
Test status
Simulation time 2187798365 ps
CPU time 2.36 seconds
Started Jul 04 05:41:42 PM PDT 24
Finished Jul 04 05:41:45 PM PDT 24
Peak memory 198772 kb
Host smart-19e8d966-bcf0-415d-b388-1f81220a8841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672885378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1672885378
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.141414602
Short name T983
Test name
Test status
Simulation time 88270731052 ps
CPU time 46.85 seconds
Started Jul 04 05:41:42 PM PDT 24
Finished Jul 04 05:42:29 PM PDT 24
Peak memory 199992 kb
Host smart-c46787ca-d6d3-46b7-b9dd-824b393db5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141414602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.141414602
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1608183009
Short name T384
Test name
Test status
Simulation time 13720403 ps
CPU time 0.56 seconds
Started Jul 04 05:41:50 PM PDT 24
Finished Jul 04 05:41:51 PM PDT 24
Peak memory 194708 kb
Host smart-dd3e76e1-7972-4000-aa83-d0a9aad6c558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608183009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1608183009
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3708433176
Short name T998
Test name
Test status
Simulation time 113931803467 ps
CPU time 169.14 seconds
Started Jul 04 05:41:45 PM PDT 24
Finished Jul 04 05:44:34 PM PDT 24
Peak memory 199992 kb
Host smart-147d7e66-1e31-44fb-b837-8feb81f32fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708433176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3708433176
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2162664839
Short name T539
Test name
Test status
Simulation time 15537031814 ps
CPU time 25.25 seconds
Started Jul 04 05:41:44 PM PDT 24
Finished Jul 04 05:42:10 PM PDT 24
Peak memory 199948 kb
Host smart-afafddee-8132-4e7f-99f7-567bb4a34a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162664839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2162664839
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1266926048
Short name T190
Test name
Test status
Simulation time 88267677396 ps
CPU time 154.62 seconds
Started Jul 04 05:41:41 PM PDT 24
Finished Jul 04 05:44:16 PM PDT 24
Peak memory 199872 kb
Host smart-e9e82716-024b-4e5b-a781-bcf1109d9ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266926048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1266926048
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3863380832
Short name T827
Test name
Test status
Simulation time 41754933948 ps
CPU time 21.56 seconds
Started Jul 04 05:41:50 PM PDT 24
Finished Jul 04 05:42:12 PM PDT 24
Peak memory 197212 kb
Host smart-3ebba95b-34ef-4dc6-a69d-4f4b3088ec4f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863380832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3863380832
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1051849016
Short name T861
Test name
Test status
Simulation time 214399375239 ps
CPU time 935.75 seconds
Started Jul 04 05:41:48 PM PDT 24
Finished Jul 04 05:57:24 PM PDT 24
Peak memory 199924 kb
Host smart-55d8fae4-d860-4f2b-896e-8d3e9997c593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051849016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1051849016
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.4182110275
Short name T346
Test name
Test status
Simulation time 8370923005 ps
CPU time 2.9 seconds
Started Jul 04 05:41:47 PM PDT 24
Finished Jul 04 05:41:50 PM PDT 24
Peak memory 199448 kb
Host smart-3f5ba532-f9b2-4fbf-b15c-800563e3a3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182110275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4182110275
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.352256783
Short name T610
Test name
Test status
Simulation time 163444769655 ps
CPU time 73.06 seconds
Started Jul 04 05:41:50 PM PDT 24
Finished Jul 04 05:43:03 PM PDT 24
Peak memory 208272 kb
Host smart-f38175a9-4f8f-4801-81c5-94fa36dfd343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352256783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.352256783
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.867599599
Short name T1068
Test name
Test status
Simulation time 27951488774 ps
CPU time 244.18 seconds
Started Jul 04 05:41:48 PM PDT 24
Finished Jul 04 05:45:53 PM PDT 24
Peak memory 199992 kb
Host smart-c3c17f6f-008a-4440-a82a-7fd8ba37bc16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867599599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.867599599
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1125996368
Short name T1
Test name
Test status
Simulation time 1672053521 ps
CPU time 5.2 seconds
Started Jul 04 05:41:44 PM PDT 24
Finished Jul 04 05:41:49 PM PDT 24
Peak memory 198992 kb
Host smart-44e1b58e-f258-4deb-bebb-50b814e425f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125996368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1125996368
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3961831205
Short name T246
Test name
Test status
Simulation time 44460318037 ps
CPU time 84.74 seconds
Started Jul 04 05:41:48 PM PDT 24
Finished Jul 04 05:43:13 PM PDT 24
Peak memory 200012 kb
Host smart-b6bd1710-972b-4ee4-890f-3e301a82619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961831205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3961831205
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1453470716
Short name T351
Test name
Test status
Simulation time 4117151384 ps
CPU time 1.65 seconds
Started Jul 04 05:41:50 PM PDT 24
Finished Jul 04 05:41:52 PM PDT 24
Peak memory 196692 kb
Host smart-937346ae-cb1b-414c-840f-fe3f05031ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453470716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1453470716
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2723312922
Short name T279
Test name
Test status
Simulation time 5281374243 ps
CPU time 12.41 seconds
Started Jul 04 05:41:43 PM PDT 24
Finished Jul 04 05:41:55 PM PDT 24
Peak memory 199744 kb
Host smart-8e026d4c-a462-4c8f-85d8-aaa381002bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723312922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2723312922
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1292871806
Short name T1155
Test name
Test status
Simulation time 271599388526 ps
CPU time 394.83 seconds
Started Jul 04 05:41:50 PM PDT 24
Finished Jul 04 05:48:25 PM PDT 24
Peak memory 199920 kb
Host smart-b4541d8d-c518-41f3-a0e5-818af356f114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292871806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1292871806
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1234386834
Short name T1154
Test name
Test status
Simulation time 435176777596 ps
CPU time 1671.75 seconds
Started Jul 04 05:41:49 PM PDT 24
Finished Jul 04 06:09:41 PM PDT 24
Peak memory 216512 kb
Host smart-1e72da95-8a9b-4a30-b058-3dda458ca537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234386834 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1234386834
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1301576676
Short name T256
Test name
Test status
Simulation time 1078154786 ps
CPU time 2.11 seconds
Started Jul 04 05:41:49 PM PDT 24
Finished Jul 04 05:41:51 PM PDT 24
Peak memory 199636 kb
Host smart-5612822d-5389-4213-b89a-d4ddefe319cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301576676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1301576676
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.706884939
Short name T86
Test name
Test status
Simulation time 45195921157 ps
CPU time 296.52 seconds
Started Jul 04 05:41:41 PM PDT 24
Finished Jul 04 05:46:38 PM PDT 24
Peak memory 199952 kb
Host smart-f53cb64d-df2f-4c8f-8d07-a3d2ec45bbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706884939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.706884939
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1235828126
Short name T84
Test name
Test status
Simulation time 42080667 ps
CPU time 0.62 seconds
Started Jul 04 05:41:58 PM PDT 24
Finished Jul 04 05:41:59 PM PDT 24
Peak memory 194588 kb
Host smart-d86cab5d-accb-400a-a8dd-84599ceaef5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235828126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1235828126
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3967503561
Short name T642
Test name
Test status
Simulation time 37941018821 ps
CPU time 28.2 seconds
Started Jul 04 05:41:50 PM PDT 24
Finished Jul 04 05:42:18 PM PDT 24
Peak memory 199924 kb
Host smart-2f644cb9-e7ca-4b4d-ba3a-2667bfef8f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967503561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3967503561
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.876595701
Short name T107
Test name
Test status
Simulation time 16892798968 ps
CPU time 24.05 seconds
Started Jul 04 05:41:50 PM PDT 24
Finished Jul 04 05:42:14 PM PDT 24
Peak memory 199740 kb
Host smart-8f538c06-1fda-440a-afc3-e85357d9f82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876595701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.876595701
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.4233628240
Short name T169
Test name
Test status
Simulation time 8643036656 ps
CPU time 12.73 seconds
Started Jul 04 05:41:57 PM PDT 24
Finished Jul 04 05:42:10 PM PDT 24
Peak memory 200008 kb
Host smart-71240bb4-2685-4190-8d41-bf2ee874a89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233628240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.4233628240
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3634693021
Short name T704
Test name
Test status
Simulation time 137513636870 ps
CPU time 192.17 seconds
Started Jul 04 05:41:57 PM PDT 24
Finished Jul 04 05:45:09 PM PDT 24
Peak memory 196084 kb
Host smart-d1345515-91ce-4b19-b11e-fc21241433a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634693021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3634693021
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2607614452
Short name T717
Test name
Test status
Simulation time 118278588039 ps
CPU time 407.47 seconds
Started Jul 04 05:41:56 PM PDT 24
Finished Jul 04 05:48:44 PM PDT 24
Peak memory 199956 kb
Host smart-23710195-b8fe-48dc-b099-fbb1191ba495
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607614452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2607614452
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.976978716
Short name T375
Test name
Test status
Simulation time 1530778915 ps
CPU time 1.25 seconds
Started Jul 04 05:41:58 PM PDT 24
Finished Jul 04 05:42:00 PM PDT 24
Peak memory 195768 kb
Host smart-6db87e35-5bf4-4566-9ac4-997b9fbb0fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976978716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.976978716
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2155889805
Short name T233
Test name
Test status
Simulation time 41715458904 ps
CPU time 73.32 seconds
Started Jul 04 05:41:56 PM PDT 24
Finished Jul 04 05:43:09 PM PDT 24
Peak memory 199520 kb
Host smart-6c76f25f-1590-4688-abec-597541e59fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155889805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2155889805
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2429618277
Short name T239
Test name
Test status
Simulation time 8825114511 ps
CPU time 202.24 seconds
Started Jul 04 05:41:58 PM PDT 24
Finished Jul 04 05:45:20 PM PDT 24
Peak memory 199936 kb
Host smart-26fe3f49-6d06-46e8-9bb3-d3ff90853206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429618277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2429618277
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3227946051
Short name T599
Test name
Test status
Simulation time 3561437984 ps
CPU time 27.44 seconds
Started Jul 04 05:41:56 PM PDT 24
Finished Jul 04 05:42:24 PM PDT 24
Peak memory 198128 kb
Host smart-70f4e595-b68f-4beb-aefb-909d74785de6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227946051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3227946051
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3008471450
Short name T248
Test name
Test status
Simulation time 70053453769 ps
CPU time 29.43 seconds
Started Jul 04 05:41:56 PM PDT 24
Finished Jul 04 05:42:26 PM PDT 24
Peak memory 199256 kb
Host smart-2bae7dac-c47b-4e39-91e5-c464eb67c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008471450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3008471450
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3320592829
Short name T382
Test name
Test status
Simulation time 3751958973 ps
CPU time 3.41 seconds
Started Jul 04 05:41:57 PM PDT 24
Finished Jul 04 05:42:01 PM PDT 24
Peak memory 196540 kb
Host smart-ccb74f69-71ea-4176-b377-2cf227aa62a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320592829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3320592829
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.298111009
Short name T1120
Test name
Test status
Simulation time 929102098 ps
CPU time 2.97 seconds
Started Jul 04 05:41:49 PM PDT 24
Finished Jul 04 05:41:52 PM PDT 24
Peak memory 198484 kb
Host smart-cea52f7c-63e9-4f9b-a8e0-555d8f948cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298111009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.298111009
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4007327793
Short name T456
Test name
Test status
Simulation time 6635974720 ps
CPU time 21.61 seconds
Started Jul 04 05:41:57 PM PDT 24
Finished Jul 04 05:42:19 PM PDT 24
Peak memory 199304 kb
Host smart-70c7cf1d-6f7b-4e57-85ec-f4391cf133f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007327793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4007327793
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.254359112
Short name T735
Test name
Test status
Simulation time 93676599908 ps
CPU time 141.25 seconds
Started Jul 04 05:41:49 PM PDT 24
Finished Jul 04 05:44:11 PM PDT 24
Peak memory 199860 kb
Host smart-0a9c9bfc-f519-473b-915e-0650ad8d69e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254359112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.254359112
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2553288546
Short name T553
Test name
Test status
Simulation time 76038382 ps
CPU time 0.58 seconds
Started Jul 04 05:38:24 PM PDT 24
Finished Jul 04 05:38:25 PM PDT 24
Peak memory 195288 kb
Host smart-e1f53ce4-e0b0-4565-9032-1cc3f82b68bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553288546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2553288546
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.13320262
Short name T1112
Test name
Test status
Simulation time 160180608526 ps
CPU time 99.75 seconds
Started Jul 04 05:38:25 PM PDT 24
Finished Jul 04 05:40:05 PM PDT 24
Peak memory 199988 kb
Host smart-76c4c841-36b2-4538-ab50-c4cda487c878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13320262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.13320262
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2269880438
Short name T259
Test name
Test status
Simulation time 123376522442 ps
CPU time 25.86 seconds
Started Jul 04 05:38:24 PM PDT 24
Finished Jul 04 05:38:50 PM PDT 24
Peak memory 199908 kb
Host smart-0583a28a-623b-4c93-89d3-83bf5518bdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269880438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2269880438
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.490571125
Short name T922
Test name
Test status
Simulation time 89954540202 ps
CPU time 56.31 seconds
Started Jul 04 05:38:21 PM PDT 24
Finished Jul 04 05:39:17 PM PDT 24
Peak memory 199948 kb
Host smart-8e95ee36-612b-4058-8e78-f3f331139e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490571125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.490571125
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3021731948
Short name T900
Test name
Test status
Simulation time 26447271870 ps
CPU time 23.91 seconds
Started Jul 04 05:38:19 PM PDT 24
Finished Jul 04 05:38:44 PM PDT 24
Peak memory 197516 kb
Host smart-daa06557-8ba8-4509-94d9-1c5420817693
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021731948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3021731948
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2801533755
Short name T865
Test name
Test status
Simulation time 70221381862 ps
CPU time 529.56 seconds
Started Jul 04 05:38:19 PM PDT 24
Finished Jul 04 05:47:09 PM PDT 24
Peak memory 199884 kb
Host smart-291b197d-21ea-4df0-ab26-2dacdd6cbab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2801533755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2801533755
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.4027113580
Short name T306
Test name
Test status
Simulation time 1590344696 ps
CPU time 2.49 seconds
Started Jul 04 05:38:25 PM PDT 24
Finished Jul 04 05:38:28 PM PDT 24
Peak memory 198320 kb
Host smart-7d08776f-87d4-48b6-9810-5b5c4f0cf4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027113580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.4027113580
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3648269397
Short name T957
Test name
Test status
Simulation time 38486620710 ps
CPU time 16.22 seconds
Started Jul 04 05:38:20 PM PDT 24
Finished Jul 04 05:38:37 PM PDT 24
Peak memory 196140 kb
Host smart-eae44305-1215-44d7-ac1a-de2e09471f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648269397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3648269397
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.4286821260
Short name T252
Test name
Test status
Simulation time 28367337553 ps
CPU time 1555.78 seconds
Started Jul 04 05:38:19 PM PDT 24
Finished Jul 04 06:04:15 PM PDT 24
Peak memory 199888 kb
Host smart-09e967e7-a346-460c-b255-c48e945240e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4286821260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.4286821260
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1532905315
Short name T386
Test name
Test status
Simulation time 4701864384 ps
CPU time 10.56 seconds
Started Jul 04 05:38:25 PM PDT 24
Finished Jul 04 05:38:36 PM PDT 24
Peak memory 197812 kb
Host smart-42570355-298e-429f-a58b-37e9ff669e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1532905315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1532905315
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.248570235
Short name T228
Test name
Test status
Simulation time 118612228098 ps
CPU time 50.21 seconds
Started Jul 04 05:38:19 PM PDT 24
Finished Jul 04 05:39:10 PM PDT 24
Peak memory 199924 kb
Host smart-3b684b2a-b5e2-47b9-908d-8c80a96a88a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248570235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.248570235
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.217664709
Short name T371
Test name
Test status
Simulation time 3251246942 ps
CPU time 1.71 seconds
Started Jul 04 05:38:23 PM PDT 24
Finished Jul 04 05:38:25 PM PDT 24
Peak memory 195836 kb
Host smart-5a266dc5-e141-4498-9553-16102e78c708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217664709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.217664709
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.114450697
Short name T383
Test name
Test status
Simulation time 856862642 ps
CPU time 1.87 seconds
Started Jul 04 05:38:24 PM PDT 24
Finished Jul 04 05:38:26 PM PDT 24
Peak memory 199428 kb
Host smart-6b2c3073-eceb-4a08-bef4-0817472604b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114450697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.114450697
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.567577380
Short name T1003
Test name
Test status
Simulation time 516212338733 ps
CPU time 137.45 seconds
Started Jul 04 05:38:22 PM PDT 24
Finished Jul 04 05:40:39 PM PDT 24
Peak memory 199980 kb
Host smart-b6c805e7-efe8-4485-b475-b96f48d17dcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567577380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.567577380
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2650359987
Short name T1110
Test name
Test status
Simulation time 42537041792 ps
CPU time 221.07 seconds
Started Jul 04 05:38:26 PM PDT 24
Finished Jul 04 05:42:08 PM PDT 24
Peak memory 216356 kb
Host smart-274753ec-945a-42f0-b056-380749c26a1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650359987 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2650359987
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.785495047
Short name T1084
Test name
Test status
Simulation time 6891288597 ps
CPU time 22.58 seconds
Started Jul 04 05:38:23 PM PDT 24
Finished Jul 04 05:38:46 PM PDT 24
Peak memory 199528 kb
Host smart-ed57a25e-deb3-4204-b28d-13f2bb974069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785495047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.785495047
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1693475363
Short name T318
Test name
Test status
Simulation time 190078726539 ps
CPU time 119.29 seconds
Started Jul 04 05:38:21 PM PDT 24
Finished Jul 04 05:40:20 PM PDT 24
Peak memory 199532 kb
Host smart-8cf1a8a5-f50d-46a6-b859-2e622d862679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693475363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1693475363
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.985130467
Short name T656
Test name
Test status
Simulation time 53720697799 ps
CPU time 72.67 seconds
Started Jul 04 05:41:58 PM PDT 24
Finished Jul 04 05:43:11 PM PDT 24
Peak memory 199848 kb
Host smart-e0244f0b-3d7e-4f7d-a1f5-c3f6bcc5b2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985130467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.985130467
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.557839254
Short name T1049
Test name
Test status
Simulation time 447376078649 ps
CPU time 1151.17 seconds
Started Jul 04 05:41:57 PM PDT 24
Finished Jul 04 06:01:08 PM PDT 24
Peak memory 233012 kb
Host smart-bf05efe2-12c2-4c4c-8437-4c6dfd1d9aa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557839254 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.557839254
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.24216698
Short name T312
Test name
Test status
Simulation time 48831961592 ps
CPU time 27.26 seconds
Started Jul 04 05:42:00 PM PDT 24
Finished Jul 04 05:42:28 PM PDT 24
Peak memory 199988 kb
Host smart-dc129c98-407c-4da0-9517-8b863e0de236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24216698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.24216698
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.355688717
Short name T44
Test name
Test status
Simulation time 50953998066 ps
CPU time 605.3 seconds
Started Jul 04 05:41:55 PM PDT 24
Finished Jul 04 05:52:01 PM PDT 24
Peak memory 224840 kb
Host smart-ec2b89e9-a1bf-43b8-9660-34d4f6a8e057
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355688717 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.355688717
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2471733155
Short name T924
Test name
Test status
Simulation time 124943543523 ps
CPU time 348.73 seconds
Started Jul 04 05:41:57 PM PDT 24
Finished Jul 04 05:47:46 PM PDT 24
Peak memory 199976 kb
Host smart-b695f6b1-379e-439d-82c3-cb8923013e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471733155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2471733155
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.688642950
Short name T514
Test name
Test status
Simulation time 99838316943 ps
CPU time 553.07 seconds
Started Jul 04 05:41:58 PM PDT 24
Finished Jul 04 05:51:11 PM PDT 24
Peak memory 216444 kb
Host smart-4779d72a-bad5-4de3-b9fe-7a2a64fad2cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688642950 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.688642950
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2251399603
Short name T262
Test name
Test status
Simulation time 131114038667 ps
CPU time 254.32 seconds
Started Jul 04 05:41:57 PM PDT 24
Finished Jul 04 05:46:12 PM PDT 24
Peak memory 199812 kb
Host smart-20026ed7-d655-4293-9e75-70a224889fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251399603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2251399603
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1502221939
Short name T43
Test name
Test status
Simulation time 124097408353 ps
CPU time 638.06 seconds
Started Jul 04 05:41:58 PM PDT 24
Finished Jul 04 05:52:36 PM PDT 24
Peak memory 209288 kb
Host smart-a248487b-7ee0-4eec-a5ff-aa42406b6655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502221939 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1502221939
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3950404649
Short name T188
Test name
Test status
Simulation time 111593820760 ps
CPU time 94.54 seconds
Started Jul 04 05:42:03 PM PDT 24
Finished Jul 04 05:43:38 PM PDT 24
Peak memory 199964 kb
Host smart-f09c745d-2708-480d-a7ce-ec103acadc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950404649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3950404649
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1676016376
Short name T936
Test name
Test status
Simulation time 14433879641 ps
CPU time 13.72 seconds
Started Jul 04 05:42:08 PM PDT 24
Finished Jul 04 05:42:22 PM PDT 24
Peak memory 199828 kb
Host smart-b1fdacc8-d02d-4c7a-b706-b05f1dac7cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676016376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1676016376
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2008046629
Short name T59
Test name
Test status
Simulation time 144017858348 ps
CPU time 517.52 seconds
Started Jul 04 05:42:03 PM PDT 24
Finished Jul 04 05:50:41 PM PDT 24
Peak memory 216504 kb
Host smart-7b1035bf-e21d-4eca-bf6b-30b3116b2f7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008046629 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2008046629
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2413197672
Short name T770
Test name
Test status
Simulation time 39250457022 ps
CPU time 26.01 seconds
Started Jul 04 05:42:04 PM PDT 24
Finished Jul 04 05:42:31 PM PDT 24
Peak memory 200004 kb
Host smart-267aa223-0f27-4439-9742-d53813acef1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413197672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2413197672
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1495942049
Short name T29
Test name
Test status
Simulation time 151684641965 ps
CPU time 308.13 seconds
Started Jul 04 05:42:06 PM PDT 24
Finished Jul 04 05:47:14 PM PDT 24
Peak memory 215904 kb
Host smart-21690e38-d3bb-4fbb-ab56-c01329c50af5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495942049 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1495942049
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1029938127
Short name T802
Test name
Test status
Simulation time 37465962261 ps
CPU time 739.19 seconds
Started Jul 04 05:42:04 PM PDT 24
Finished Jul 04 05:54:23 PM PDT 24
Peak memory 216716 kb
Host smart-3e1a9603-2321-4175-9bbf-f966ad495e4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029938127 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1029938127
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3893491926
Short name T1095
Test name
Test status
Simulation time 18606494715 ps
CPU time 24.63 seconds
Started Jul 04 05:42:04 PM PDT 24
Finished Jul 04 05:42:29 PM PDT 24
Peak memory 199944 kb
Host smart-0ef155e4-c9aa-44cb-849f-6f0e1a468be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893491926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3893491926
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.722752984
Short name T807
Test name
Test status
Simulation time 116650791850 ps
CPU time 668.84 seconds
Started Jul 04 05:42:06 PM PDT 24
Finished Jul 04 05:53:15 PM PDT 24
Peak memory 216448 kb
Host smart-aadd9271-15ae-4ae7-97f3-8cb8c0cf3ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722752984 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.722752984
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3876608017
Short name T323
Test name
Test status
Simulation time 13501926554 ps
CPU time 17.51 seconds
Started Jul 04 05:42:05 PM PDT 24
Finished Jul 04 05:42:22 PM PDT 24
Peak memory 199724 kb
Host smart-67eec6e9-0926-4523-bfe2-94acf699e5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876608017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3876608017
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3896389284
Short name T581
Test name
Test status
Simulation time 75895128493 ps
CPU time 727.52 seconds
Started Jul 04 05:42:09 PM PDT 24
Finished Jul 04 05:54:17 PM PDT 24
Peak memory 224924 kb
Host smart-6cb68c32-0d7d-4d4a-9168-79af4fc26abc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896389284 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3896389284
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.4048664873
Short name T342
Test name
Test status
Simulation time 13195762 ps
CPU time 0.56 seconds
Started Jul 04 05:38:26 PM PDT 24
Finished Jul 04 05:38:26 PM PDT 24
Peak memory 195308 kb
Host smart-f0a5d654-470a-4e7b-9b70-8040ddf76157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048664873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.4048664873
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1539347062
Short name T129
Test name
Test status
Simulation time 156330642765 ps
CPU time 57.5 seconds
Started Jul 04 05:38:24 PM PDT 24
Finished Jul 04 05:39:22 PM PDT 24
Peak memory 199948 kb
Host smart-cec00032-895d-42a6-9fec-1f7abc7619a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539347062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1539347062
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2271526168
Short name T234
Test name
Test status
Simulation time 179675211085 ps
CPU time 83.93 seconds
Started Jul 04 05:38:24 PM PDT 24
Finished Jul 04 05:39:48 PM PDT 24
Peak memory 199972 kb
Host smart-fd84908d-48fb-4118-aef0-373f691255c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271526168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2271526168
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.178605466
Short name T1081
Test name
Test status
Simulation time 49788830041 ps
CPU time 30.53 seconds
Started Jul 04 05:38:23 PM PDT 24
Finished Jul 04 05:38:54 PM PDT 24
Peak memory 199928 kb
Host smart-3fefe5b3-6658-46f1-8346-6c3b73e2dd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178605466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.178605466
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.363101322
Short name T332
Test name
Test status
Simulation time 15123776807 ps
CPU time 6.72 seconds
Started Jul 04 05:38:26 PM PDT 24
Finished Jul 04 05:38:33 PM PDT 24
Peak memory 196792 kb
Host smart-15cb6819-9543-45c3-ac6a-a61278a79788
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363101322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.363101322
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1832456316
Short name T720
Test name
Test status
Simulation time 125197096135 ps
CPU time 211.53 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:41:58 PM PDT 24
Peak memory 199968 kb
Host smart-fd504160-2f52-4109-b953-775ca71bd44b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832456316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1832456316
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.177962756
Short name T353
Test name
Test status
Simulation time 261693658 ps
CPU time 0.81 seconds
Started Jul 04 05:38:28 PM PDT 24
Finished Jul 04 05:38:29 PM PDT 24
Peak memory 195828 kb
Host smart-75c04b46-a112-462c-8914-019941d92573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177962756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.177962756
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.97325883
Short name T274
Test name
Test status
Simulation time 94291761978 ps
CPU time 66.94 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:39:34 PM PDT 24
Peak memory 200180 kb
Host smart-024f608d-1e58-4c97-bd6a-560216dbc974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97325883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.97325883
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1900503378
Short name T1149
Test name
Test status
Simulation time 12112093099 ps
CPU time 116.12 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:40:24 PM PDT 24
Peak memory 199948 kb
Host smart-20c01fc8-b8f0-48f8-926b-a2605235cfa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900503378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1900503378
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.850177528
Short name T455
Test name
Test status
Simulation time 2778680564 ps
CPU time 5.17 seconds
Started Jul 04 05:38:31 PM PDT 24
Finished Jul 04 05:38:37 PM PDT 24
Peak memory 198052 kb
Host smart-cb6737fa-dba8-4578-bbba-46c92e246694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850177528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.850177528
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2364782380
Short name T137
Test name
Test status
Simulation time 37626719283 ps
CPU time 14.67 seconds
Started Jul 04 05:38:25 PM PDT 24
Finished Jul 04 05:38:40 PM PDT 24
Peak memory 199928 kb
Host smart-6c93bb43-a3db-495c-9b48-1e352182e002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364782380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2364782380
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1464460631
Short name T232
Test name
Test status
Simulation time 35026520053 ps
CPU time 30.87 seconds
Started Jul 04 05:38:31 PM PDT 24
Finished Jul 04 05:39:02 PM PDT 24
Peak memory 196052 kb
Host smart-4c72f8bb-997a-4777-a4e9-b654c20091a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464460631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1464460631
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3692403216
Short name T245
Test name
Test status
Simulation time 6306086359 ps
CPU time 10.66 seconds
Started Jul 04 05:38:18 PM PDT 24
Finished Jul 04 05:38:29 PM PDT 24
Peak memory 199908 kb
Host smart-ae344956-4337-408a-9e21-63d3fb66523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692403216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3692403216
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.162313851
Short name T672
Test name
Test status
Simulation time 284129156758 ps
CPU time 476.84 seconds
Started Jul 04 05:38:31 PM PDT 24
Finished Jul 04 05:46:28 PM PDT 24
Peak memory 208340 kb
Host smart-f870c8dd-8258-4b14-903e-c0e5123ac551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162313851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.162313851
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1719052427
Short name T409
Test name
Test status
Simulation time 176911742261 ps
CPU time 480.99 seconds
Started Jul 04 05:38:28 PM PDT 24
Finished Jul 04 05:46:29 PM PDT 24
Peak memory 216656 kb
Host smart-b8d23e16-53cc-4ad8-afe2-fc532c79c757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719052427 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1719052427
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2034334791
Short name T367
Test name
Test status
Simulation time 6535925599 ps
CPU time 14.54 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:38:42 PM PDT 24
Peak memory 199240 kb
Host smart-099b408f-81fe-42e5-a392-3835a9b26597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034334791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2034334791
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2461516526
Short name T1071
Test name
Test status
Simulation time 31117058529 ps
CPU time 53.53 seconds
Started Jul 04 05:38:25 PM PDT 24
Finished Jul 04 05:39:19 PM PDT 24
Peak memory 199928 kb
Host smart-3ae3a779-1f58-495d-9f01-cb0f8a23c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461516526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2461516526
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1666016192
Short name T638
Test name
Test status
Simulation time 105965422206 ps
CPU time 239.35 seconds
Started Jul 04 05:42:05 PM PDT 24
Finished Jul 04 05:46:04 PM PDT 24
Peak memory 216332 kb
Host smart-b8b8f8f3-0673-4660-af8b-749af5b0700a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666016192 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1666016192
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2181889381
Short name T621
Test name
Test status
Simulation time 79559976299 ps
CPU time 160.22 seconds
Started Jul 04 05:42:06 PM PDT 24
Finished Jul 04 05:44:46 PM PDT 24
Peak memory 199920 kb
Host smart-af635524-17a3-4a89-9918-c5f465367556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181889381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2181889381
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1309391151
Short name T1137
Test name
Test status
Simulation time 26935813064 ps
CPU time 287.05 seconds
Started Jul 04 05:42:05 PM PDT 24
Finished Jul 04 05:46:52 PM PDT 24
Peak memory 216520 kb
Host smart-e9bf10ca-5b21-4485-a001-2e54b12bd031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309391151 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1309391151
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.871580035
Short name T1048
Test name
Test status
Simulation time 118487871216 ps
CPU time 46.38 seconds
Started Jul 04 05:42:04 PM PDT 24
Finished Jul 04 05:42:50 PM PDT 24
Peak memory 199956 kb
Host smart-0152ddd1-ca72-4244-be90-18d9af29ce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871580035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.871580035
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.178818147
Short name T1046
Test name
Test status
Simulation time 303205925743 ps
CPU time 424.43 seconds
Started Jul 04 05:42:08 PM PDT 24
Finished Jul 04 05:49:12 PM PDT 24
Peak memory 216560 kb
Host smart-fa9e3960-a42d-4f2b-a0c6-e1a2e2589d5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178818147 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.178818147
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.555836708
Short name T570
Test name
Test status
Simulation time 109085303472 ps
CPU time 171.62 seconds
Started Jul 04 05:42:03 PM PDT 24
Finished Jul 04 05:44:55 PM PDT 24
Peak memory 199940 kb
Host smart-3e21e9db-9508-4774-ae3f-54ef68bf516c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555836708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.555836708
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1818455425
Short name T981
Test name
Test status
Simulation time 61387119495 ps
CPU time 725.76 seconds
Started Jul 04 05:42:04 PM PDT 24
Finished Jul 04 05:54:10 PM PDT 24
Peak memory 216612 kb
Host smart-2e132f3d-17b1-48ae-9740-44da3a209585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818455425 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1818455425
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.212110314
Short name T767
Test name
Test status
Simulation time 60822976145 ps
CPU time 14.85 seconds
Started Jul 04 05:42:04 PM PDT 24
Finished Jul 04 05:42:19 PM PDT 24
Peak memory 199912 kb
Host smart-581f7ceb-5938-44c6-83f3-97cdc1934b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212110314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.212110314
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.4276962191
Short name T866
Test name
Test status
Simulation time 211020426224 ps
CPU time 697.69 seconds
Started Jul 04 05:42:14 PM PDT 24
Finished Jul 04 05:53:52 PM PDT 24
Peak memory 226432 kb
Host smart-5093e790-416e-44c8-ae8c-daa6df324ee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276962191 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.4276962191
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.30385966
Short name T822
Test name
Test status
Simulation time 61034282914 ps
CPU time 29.31 seconds
Started Jul 04 05:42:11 PM PDT 24
Finished Jul 04 05:42:41 PM PDT 24
Peak memory 199908 kb
Host smart-f94f8866-658e-4bb7-bff1-0f1e26a51db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30385966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.30385966
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3899784435
Short name T1035
Test name
Test status
Simulation time 89027574740 ps
CPU time 509.04 seconds
Started Jul 04 05:42:14 PM PDT 24
Finished Jul 04 05:50:44 PM PDT 24
Peak memory 224852 kb
Host smart-f855bda1-fdf9-480a-92a2-8ec88f03b713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899784435 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3899784435
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1101520312
Short name T1094
Test name
Test status
Simulation time 92662320774 ps
CPU time 108.1 seconds
Started Jul 04 05:42:13 PM PDT 24
Finished Jul 04 05:44:01 PM PDT 24
Peak memory 199796 kb
Host smart-d7d28ca1-29e0-4960-aaea-444d72744e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101520312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1101520312
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2478477816
Short name T301
Test name
Test status
Simulation time 58991630682 ps
CPU time 48.42 seconds
Started Jul 04 05:42:14 PM PDT 24
Finished Jul 04 05:43:03 PM PDT 24
Peak memory 199660 kb
Host smart-798425ba-85d7-43d1-ae5c-aa89d5004ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478477816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2478477816
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3716481818
Short name T868
Test name
Test status
Simulation time 28935416662 ps
CPU time 1275.22 seconds
Started Jul 04 05:42:12 PM PDT 24
Finished Jul 04 06:03:27 PM PDT 24
Peak memory 216516 kb
Host smart-0e29ac22-b672-47f7-9d0a-a539c6b0a1c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716481818 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3716481818
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2620411158
Short name T547
Test name
Test status
Simulation time 117653356266 ps
CPU time 47.56 seconds
Started Jul 04 05:42:13 PM PDT 24
Finished Jul 04 05:43:01 PM PDT 24
Peak memory 199924 kb
Host smart-ed355c25-7e30-4485-af40-804a561041e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620411158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2620411158
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1146679808
Short name T987
Test name
Test status
Simulation time 80110930745 ps
CPU time 764.61 seconds
Started Jul 04 05:42:12 PM PDT 24
Finished Jul 04 05:54:57 PM PDT 24
Peak memory 224900 kb
Host smart-0329b978-630c-40b1-b240-2b265747a628
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146679808 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1146679808
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3174506362
Short name T700
Test name
Test status
Simulation time 13257316 ps
CPU time 0.55 seconds
Started Jul 04 05:38:28 PM PDT 24
Finished Jul 04 05:38:29 PM PDT 24
Peak memory 195592 kb
Host smart-a0cfd5ad-b0c6-494a-b356-f3f6cd2394d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174506362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3174506362
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.324493940
Short name T948
Test name
Test status
Simulation time 30250293745 ps
CPU time 17.86 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:38:45 PM PDT 24
Peak memory 199940 kb
Host smart-249bba4f-76ef-4d67-b046-f7642e69ed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324493940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.324493940
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3710197156
Short name T575
Test name
Test status
Simulation time 152541718736 ps
CPU time 69.81 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:39:37 PM PDT 24
Peak memory 199980 kb
Host smart-df36d177-8c41-4b02-a65c-4f44e710790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710197156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3710197156
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1964109854
Short name T654
Test name
Test status
Simulation time 106864558839 ps
CPU time 172.04 seconds
Started Jul 04 05:38:30 PM PDT 24
Finished Jul 04 05:41:22 PM PDT 24
Peak memory 199944 kb
Host smart-2a914ae5-9281-4001-ae6c-e254aba5432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964109854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1964109854
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1772973483
Short name T56
Test name
Test status
Simulation time 20258677085 ps
CPU time 6.19 seconds
Started Jul 04 05:38:26 PM PDT 24
Finished Jul 04 05:38:33 PM PDT 24
Peak memory 196936 kb
Host smart-af9d3fef-cffe-4152-97f0-7d4e774ea942
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772973483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1772973483
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1669049457
Short name T224
Test name
Test status
Simulation time 172687967839 ps
CPU time 223.8 seconds
Started Jul 04 05:38:32 PM PDT 24
Finished Jul 04 05:42:16 PM PDT 24
Peak memory 199928 kb
Host smart-82bef40a-dfde-47d6-bbf5-549a9e767357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669049457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1669049457
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2425056076
Short name T411
Test name
Test status
Simulation time 3504094816 ps
CPU time 8.05 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:38:36 PM PDT 24
Peak memory 199948 kb
Host smart-20e51626-49ea-4c02-a35a-377a56010d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425056076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2425056076
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3010079288
Short name T268
Test name
Test status
Simulation time 106773687569 ps
CPU time 40.96 seconds
Started Jul 04 05:38:30 PM PDT 24
Finished Jul 04 05:39:11 PM PDT 24
Peak memory 199404 kb
Host smart-18c8ba82-022d-4ee1-8646-f0e7eb2d8d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010079288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3010079288
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3815881984
Short name T403
Test name
Test status
Simulation time 21883624642 ps
CPU time 1179.83 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:58:07 PM PDT 24
Peak memory 199984 kb
Host smart-8c868d4a-068f-4761-9890-5207e7adb3d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3815881984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3815881984
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1959638630
Short name T820
Test name
Test status
Simulation time 7055389577 ps
CPU time 35.2 seconds
Started Jul 04 05:38:28 PM PDT 24
Finished Jul 04 05:39:03 PM PDT 24
Peak memory 197872 kb
Host smart-52cb5ab3-bd89-4dbc-af6c-b057c3cc44f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1959638630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1959638630
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3156795138
Short name T316
Test name
Test status
Simulation time 91452110416 ps
CPU time 137.08 seconds
Started Jul 04 05:38:28 PM PDT 24
Finished Jul 04 05:40:45 PM PDT 24
Peak memory 199884 kb
Host smart-0be1a408-5ece-46a5-9317-f2ae816e43a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156795138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3156795138
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3545529022
Short name T719
Test name
Test status
Simulation time 46034052066 ps
CPU time 72.29 seconds
Started Jul 04 05:38:26 PM PDT 24
Finished Jul 04 05:39:38 PM PDT 24
Peak memory 195792 kb
Host smart-34ba4257-f05c-442b-9637-d32bf0d412eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545529022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3545529022
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3883653631
Short name T635
Test name
Test status
Simulation time 6047712544 ps
CPU time 19.3 seconds
Started Jul 04 05:38:28 PM PDT 24
Finished Jul 04 05:38:48 PM PDT 24
Peak memory 199868 kb
Host smart-193444de-1710-4401-a2c6-6373273af0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883653631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3883653631
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.715642567
Short name T1113
Test name
Test status
Simulation time 35909194108 ps
CPU time 23.56 seconds
Started Jul 04 05:38:30 PM PDT 24
Finished Jul 04 05:38:54 PM PDT 24
Peak memory 199956 kb
Host smart-b31b6304-3a9b-4c15-9d60-4528bfb8c045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715642567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.715642567
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.4110859478
Short name T691
Test name
Test status
Simulation time 1205912785 ps
CPU time 1.96 seconds
Started Jul 04 05:38:30 PM PDT 24
Finished Jul 04 05:38:32 PM PDT 24
Peak memory 198640 kb
Host smart-8bfa283b-a94a-4efc-91e0-4c0f943d3a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110859478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.4110859478
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1461121029
Short name T935
Test name
Test status
Simulation time 42346690732 ps
CPU time 35.14 seconds
Started Jul 04 05:38:26 PM PDT 24
Finished Jul 04 05:39:01 PM PDT 24
Peak memory 199856 kb
Host smart-c9a2dd8b-db5e-45a2-9763-86b2ba6759ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461121029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1461121029
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1129650648
Short name T839
Test name
Test status
Simulation time 31476404111 ps
CPU time 154.01 seconds
Started Jul 04 05:42:14 PM PDT 24
Finished Jul 04 05:44:48 PM PDT 24
Peak memory 216680 kb
Host smart-9b8454df-0ee5-4707-9579-34a2b9626707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129650648 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1129650648
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.926233579
Short name T1053
Test name
Test status
Simulation time 128483311615 ps
CPU time 182.17 seconds
Started Jul 04 05:42:12 PM PDT 24
Finished Jul 04 05:45:14 PM PDT 24
Peak memory 200000 kb
Host smart-0ebf221c-2e7d-4cf1-a9a0-af32752c6cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926233579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.926233579
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2219604631
Short name T512
Test name
Test status
Simulation time 176829863434 ps
CPU time 643.82 seconds
Started Jul 04 05:42:11 PM PDT 24
Finished Jul 04 05:52:55 PM PDT 24
Peak memory 212960 kb
Host smart-6e53ed27-cce9-4825-aab6-6db333732eb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219604631 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2219604631
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3757316555
Short name T289
Test name
Test status
Simulation time 125675952520 ps
CPU time 35.19 seconds
Started Jul 04 05:42:13 PM PDT 24
Finished Jul 04 05:42:48 PM PDT 24
Peak memory 199864 kb
Host smart-99fea2c3-fb1d-404e-bc79-480434808b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757316555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3757316555
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.4103910642
Short name T737
Test name
Test status
Simulation time 122846081438 ps
CPU time 591.31 seconds
Started Jul 04 05:42:12 PM PDT 24
Finished Jul 04 05:52:03 PM PDT 24
Peak memory 224932 kb
Host smart-bb5634ba-7795-4d43-9dcc-6e803f226496
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103910642 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.4103910642
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3395115901
Short name T1104
Test name
Test status
Simulation time 59083163755 ps
CPU time 13.71 seconds
Started Jul 04 05:42:12 PM PDT 24
Finished Jul 04 05:42:26 PM PDT 24
Peak memory 198208 kb
Host smart-835930ce-bb1e-496e-98b7-ccbd49db4237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395115901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3395115901
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1847029520
Short name T114
Test name
Test status
Simulation time 61062002266 ps
CPU time 30.38 seconds
Started Jul 04 05:42:14 PM PDT 24
Finished Jul 04 05:42:44 PM PDT 24
Peak memory 199944 kb
Host smart-397f7907-ff78-48ca-8b88-e55d094ed136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847029520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1847029520
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3073333133
Short name T198
Test name
Test status
Simulation time 149892437256 ps
CPU time 718.37 seconds
Started Jul 04 05:42:12 PM PDT 24
Finished Jul 04 05:54:11 PM PDT 24
Peak memory 224832 kb
Host smart-76404fb4-363f-4b29-8673-d3d89b280b57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073333133 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3073333133
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3135478744
Short name T816
Test name
Test status
Simulation time 172530319996 ps
CPU time 45.07 seconds
Started Jul 04 05:42:12 PM PDT 24
Finished Jul 04 05:42:58 PM PDT 24
Peak memory 199924 kb
Host smart-5e4c70af-f057-4f0b-b0ce-14429f422a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135478744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3135478744
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.990756180
Short name T276
Test name
Test status
Simulation time 63840442662 ps
CPU time 344.26 seconds
Started Jul 04 05:42:25 PM PDT 24
Finished Jul 04 05:48:10 PM PDT 24
Peak memory 216672 kb
Host smart-b981b404-ce42-4a6d-9e95-3f04aa42dda3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990756180 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.990756180
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3043115599
Short name T175
Test name
Test status
Simulation time 12255275833 ps
CPU time 19.15 seconds
Started Jul 04 05:42:26 PM PDT 24
Finished Jul 04 05:42:46 PM PDT 24
Peak memory 199988 kb
Host smart-698507bf-85fc-4980-8034-e4e954c9d2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043115599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3043115599
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.4195819732
Short name T22
Test name
Test status
Simulation time 80703592406 ps
CPU time 289.8 seconds
Started Jul 04 05:42:24 PM PDT 24
Finished Jul 04 05:47:14 PM PDT 24
Peak memory 215864 kb
Host smart-12668a76-7746-4650-bf21-8bdca64adbdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195819732 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.4195819732
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.596674225
Short name T818
Test name
Test status
Simulation time 39465924608 ps
CPU time 15.19 seconds
Started Jul 04 05:42:24 PM PDT 24
Finished Jul 04 05:42:39 PM PDT 24
Peak memory 199948 kb
Host smart-3b0de889-022f-4ab9-b29a-e3f9fc401d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596674225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.596674225
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2365322309
Short name T20
Test name
Test status
Simulation time 89704201119 ps
CPU time 531.45 seconds
Started Jul 04 05:42:24 PM PDT 24
Finished Jul 04 05:51:16 PM PDT 24
Peak memory 216488 kb
Host smart-fb6d5c0d-6a9c-46b9-aeea-3fb8bff55346
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365322309 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2365322309
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.483393619
Short name T982
Test name
Test status
Simulation time 127525465354 ps
CPU time 90.98 seconds
Started Jul 04 05:42:24 PM PDT 24
Finished Jul 04 05:43:55 PM PDT 24
Peak memory 199940 kb
Host smart-30b7db4d-2c6c-4522-83fd-159e996e3c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483393619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.483393619
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2789736531
Short name T728
Test name
Test status
Simulation time 249391097668 ps
CPU time 622.93 seconds
Started Jul 04 05:42:25 PM PDT 24
Finished Jul 04 05:52:48 PM PDT 24
Peak memory 228392 kb
Host smart-afde21ec-f9fe-4b46-a9c9-a50d1eec1290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789736531 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2789736531
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1567481285
Short name T173
Test name
Test status
Simulation time 38262093704 ps
CPU time 15.18 seconds
Started Jul 04 05:42:24 PM PDT 24
Finished Jul 04 05:42:40 PM PDT 24
Peak memory 199940 kb
Host smart-3d103c0a-6e93-4649-9f32-28c0edb6881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567481285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1567481285
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1993553494
Short name T1134
Test name
Test status
Simulation time 158363244929 ps
CPU time 262.45 seconds
Started Jul 04 05:42:24 PM PDT 24
Finished Jul 04 05:46:47 PM PDT 24
Peak memory 214376 kb
Host smart-4a622581-609e-4ace-9dcf-6619a5edd3c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993553494 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1993553494
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2876557493
Short name T931
Test name
Test status
Simulation time 14179419 ps
CPU time 0.57 seconds
Started Jul 04 05:38:41 PM PDT 24
Finished Jul 04 05:38:42 PM PDT 24
Peak memory 195204 kb
Host smart-9e0f581a-2fcd-4dad-9ce5-e7c56bb2444e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876557493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2876557493
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.937108902
Short name T320
Test name
Test status
Simulation time 34115739015 ps
CPU time 55.17 seconds
Started Jul 04 05:38:30 PM PDT 24
Finished Jul 04 05:39:26 PM PDT 24
Peak memory 199928 kb
Host smart-f8b335b1-2bd3-4e51-8d7c-476f0b58c1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937108902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.937108902
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3952546810
Short name T1138
Test name
Test status
Simulation time 25631374618 ps
CPU time 14.62 seconds
Started Jul 04 05:38:30 PM PDT 24
Finished Jul 04 05:38:45 PM PDT 24
Peak memory 199876 kb
Host smart-2904966b-f7a0-4d7a-b3d9-9cf0f4ea69d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952546810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3952546810
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1207586847
Short name T196
Test name
Test status
Simulation time 24398049033 ps
CPU time 18.83 seconds
Started Jul 04 05:38:29 PM PDT 24
Finished Jul 04 05:38:48 PM PDT 24
Peak memory 199932 kb
Host smart-d7316031-d739-42f3-a0e9-2948063833ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207586847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1207586847
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3897810566
Short name T515
Test name
Test status
Simulation time 20353505297 ps
CPU time 32.62 seconds
Started Jul 04 05:38:34 PM PDT 24
Finished Jul 04 05:39:06 PM PDT 24
Peak memory 199940 kb
Host smart-b60ff07d-85a2-49cf-a6d2-8cafbec97dce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897810566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3897810566
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.612854307
Short name T221
Test name
Test status
Simulation time 74314189835 ps
CPU time 91.8 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:40:07 PM PDT 24
Peak memory 200000 kb
Host smart-5717082a-677f-4086-bd48-43e5e415fd4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612854307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.612854307
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2316717176
Short name T750
Test name
Test status
Simulation time 9137207684 ps
CPU time 15.04 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:38:50 PM PDT 24
Peak memory 198824 kb
Host smart-ac19b351-4f57-4064-a3cb-bed546a78936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316717176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2316717176
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3681024546
Short name T1089
Test name
Test status
Simulation time 45071177153 ps
CPU time 41.35 seconds
Started Jul 04 05:38:33 PM PDT 24
Finished Jul 04 05:39:15 PM PDT 24
Peak memory 208204 kb
Host smart-9c544471-9499-4e49-a39b-2be21345e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681024546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3681024546
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.4249754218
Short name T663
Test name
Test status
Simulation time 5530627020 ps
CPU time 135.78 seconds
Started Jul 04 05:38:33 PM PDT 24
Finished Jul 04 05:40:49 PM PDT 24
Peak memory 199968 kb
Host smart-956c7bcb-af52-4d2f-b4cb-14c445acb81f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249754218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.4249754218
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3533969860
Short name T479
Test name
Test status
Simulation time 3519834619 ps
CPU time 6.92 seconds
Started Jul 04 05:38:33 PM PDT 24
Finished Jul 04 05:38:40 PM PDT 24
Peak memory 197256 kb
Host smart-82b228bb-ffb5-43ac-a877-e730701547ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533969860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3533969860
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.4187399444
Short name T1160
Test name
Test status
Simulation time 23039333836 ps
CPU time 37.6 seconds
Started Jul 04 05:38:36 PM PDT 24
Finished Jul 04 05:39:14 PM PDT 24
Peak memory 199912 kb
Host smart-91e36dc7-1a56-41f9-80fb-4b6a649be079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187399444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4187399444
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.522892800
Short name T385
Test name
Test status
Simulation time 5790066023 ps
CPU time 2.59 seconds
Started Jul 04 05:38:39 PM PDT 24
Finished Jul 04 05:38:42 PM PDT 24
Peak memory 196152 kb
Host smart-2450933f-0d4e-4539-8e63-d97431949f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522892800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.522892800
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.4227683307
Short name T881
Test name
Test status
Simulation time 1003190667 ps
CPU time 1.15 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:38:28 PM PDT 24
Peak memory 198440 kb
Host smart-119769d0-c56c-4e47-bd75-59635ee09604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227683307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4227683307
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.58559647
Short name T749
Test name
Test status
Simulation time 207478058959 ps
CPU time 841.32 seconds
Started Jul 04 05:38:36 PM PDT 24
Finished Jul 04 05:52:38 PM PDT 24
Peak memory 199936 kb
Host smart-5eca8b2e-42a8-468a-875f-5f657e1ac1fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58559647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.58559647
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.4175452231
Short name T1011
Test name
Test status
Simulation time 72284464292 ps
CPU time 429.41 seconds
Started Jul 04 05:38:36 PM PDT 24
Finished Jul 04 05:45:45 PM PDT 24
Peak memory 216564 kb
Host smart-828165e4-0262-4583-8566-c5f9a548441a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175452231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.4175452231
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.185046250
Short name T650
Test name
Test status
Simulation time 1110998295 ps
CPU time 3.24 seconds
Started Jul 04 05:38:39 PM PDT 24
Finished Jul 04 05:38:42 PM PDT 24
Peak memory 198376 kb
Host smart-4104b6b3-e688-4b99-a5ce-61cd2a0a5a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185046250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.185046250
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.78410708
Short name T482
Test name
Test status
Simulation time 77081509438 ps
CPU time 114.06 seconds
Started Jul 04 05:38:27 PM PDT 24
Finished Jul 04 05:40:22 PM PDT 24
Peak memory 199928 kb
Host smart-6e8e275d-459a-42bd-8940-6abc4adac810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78410708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.78410708
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2666172329
Short name T800
Test name
Test status
Simulation time 96655447288 ps
CPU time 989.46 seconds
Started Jul 04 05:42:26 PM PDT 24
Finished Jul 04 05:58:55 PM PDT 24
Peak memory 199964 kb
Host smart-60a22e4e-d475-4577-b173-f71d1f6e8ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666172329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2666172329
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2843309420
Short name T1102
Test name
Test status
Simulation time 213875545988 ps
CPU time 2316.97 seconds
Started Jul 04 05:42:24 PM PDT 24
Finished Jul 04 06:21:01 PM PDT 24
Peak memory 224216 kb
Host smart-dfb5681b-2d75-4d5d-bd93-c99c7be0a2fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843309420 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2843309420
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1566578063
Short name T790
Test name
Test status
Simulation time 27680030079 ps
CPU time 37.02 seconds
Started Jul 04 05:42:24 PM PDT 24
Finished Jul 04 05:43:02 PM PDT 24
Peak memory 200004 kb
Host smart-c3910d8a-7949-4e6f-be89-0d6fc2a22586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566578063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1566578063
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1932168735
Short name T858
Test name
Test status
Simulation time 19893867248 ps
CPU time 299.55 seconds
Started Jul 04 05:42:23 PM PDT 24
Finished Jul 04 05:47:22 PM PDT 24
Peak memory 216696 kb
Host smart-22c77273-8487-4856-a588-b54875ff8a2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932168735 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1932168735
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3529571027
Short name T179
Test name
Test status
Simulation time 30015411267 ps
CPU time 24.33 seconds
Started Jul 04 05:42:25 PM PDT 24
Finished Jul 04 05:42:50 PM PDT 24
Peak memory 199924 kb
Host smart-61d2073d-7246-40ad-8003-510eccf8c5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529571027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3529571027
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1288958534
Short name T42
Test name
Test status
Simulation time 553412176888 ps
CPU time 1379 seconds
Started Jul 04 05:42:27 PM PDT 24
Finished Jul 04 06:05:26 PM PDT 24
Peak memory 228168 kb
Host smart-2a3d2c41-bf38-43f6-b52e-20d28468ee97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288958534 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1288958534
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3115539459
Short name T723
Test name
Test status
Simulation time 73741673401 ps
CPU time 163.99 seconds
Started Jul 04 05:42:24 PM PDT 24
Finished Jul 04 05:45:08 PM PDT 24
Peak memory 199972 kb
Host smart-29dfa9d3-d2a3-417f-9b78-bea4de69062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115539459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3115539459
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1796870574
Short name T254
Test name
Test status
Simulation time 18437076901 ps
CPU time 237.25 seconds
Started Jul 04 05:42:25 PM PDT 24
Finished Jul 04 05:46:22 PM PDT 24
Peak memory 210472 kb
Host smart-b252c4f3-0091-4781-a784-240c4e0421e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796870574 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1796870574
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2001381217
Short name T277
Test name
Test status
Simulation time 194903622407 ps
CPU time 85.95 seconds
Started Jul 04 05:42:25 PM PDT 24
Finished Jul 04 05:43:51 PM PDT 24
Peak memory 199920 kb
Host smart-b5ea75d5-1b2a-4591-b6b8-f280f598cd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001381217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2001381217
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1581236950
Short name T677
Test name
Test status
Simulation time 100722594449 ps
CPU time 284.35 seconds
Started Jul 04 05:42:25 PM PDT 24
Finished Jul 04 05:47:10 PM PDT 24
Peak memory 216624 kb
Host smart-df406441-525f-4d22-b1bc-79c598072382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581236950 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1581236950
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1575020920
Short name T283
Test name
Test status
Simulation time 51633053653 ps
CPU time 45.85 seconds
Started Jul 04 05:42:24 PM PDT 24
Finished Jul 04 05:43:11 PM PDT 24
Peak memory 199980 kb
Host smart-407f1801-291a-4365-937e-a365a5fe8800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575020920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1575020920
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2434791633
Short name T229
Test name
Test status
Simulation time 26617358793 ps
CPU time 294.46 seconds
Started Jul 04 05:42:25 PM PDT 24
Finished Jul 04 05:47:20 PM PDT 24
Peak memory 216684 kb
Host smart-87a2eb92-9f46-4837-8a6c-ea3b3b6eae4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434791633 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2434791633
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3666335226
Short name T968
Test name
Test status
Simulation time 128334257469 ps
CPU time 29.44 seconds
Started Jul 04 05:42:25 PM PDT 24
Finished Jul 04 05:42:55 PM PDT 24
Peak memory 199928 kb
Host smart-d2b37758-4e60-4258-ae97-17efadcf55e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666335226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3666335226
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3997360258
Short name T408
Test name
Test status
Simulation time 53920430735 ps
CPU time 686.3 seconds
Started Jul 04 05:42:38 PM PDT 24
Finished Jul 04 05:54:04 PM PDT 24
Peak memory 216648 kb
Host smart-fac98b78-2cf1-4df6-a06a-210495c711be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997360258 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3997360258
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2275702936
Short name T314
Test name
Test status
Simulation time 17646093763 ps
CPU time 28.01 seconds
Started Jul 04 05:42:28 PM PDT 24
Finished Jul 04 05:42:56 PM PDT 24
Peak memory 199824 kb
Host smart-0e122597-ef25-40ac-9961-7b4d849ef838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275702936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2275702936
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2690986994
Short name T284
Test name
Test status
Simulation time 146668122987 ps
CPU time 32.31 seconds
Started Jul 04 05:42:38 PM PDT 24
Finished Jul 04 05:43:10 PM PDT 24
Peak memory 199944 kb
Host smart-995879b9-79ba-4b37-93e8-f2b87c8632eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690986994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2690986994
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.601283875
Short name T586
Test name
Test status
Simulation time 73821944558 ps
CPU time 783.18 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:55:41 PM PDT 24
Peak memory 224880 kb
Host smart-edb56e5f-a42c-4b97-9cc5-dec9280a0a10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601283875 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.601283875
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2198399613
Short name T178
Test name
Test status
Simulation time 97738425858 ps
CPU time 113.06 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:44:29 PM PDT 24
Peak memory 199928 kb
Host smart-98df77c2-a583-4ea0-8ce2-57f15e7ba138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198399613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2198399613
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.734642549
Short name T305
Test name
Test status
Simulation time 41348363726 ps
CPU time 1007.84 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:59:24 PM PDT 24
Peak memory 224680 kb
Host smart-feaa8689-c885-413c-bfb6-e8efc4f77459
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734642549 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.734642549
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.648866903
Short name T1025
Test name
Test status
Simulation time 16992190 ps
CPU time 0.57 seconds
Started Jul 04 05:38:37 PM PDT 24
Finished Jul 04 05:38:37 PM PDT 24
Peak memory 194296 kb
Host smart-a83ce201-9c35-4c52-b102-f8aacb420163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648866903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.648866903
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.523756571
Short name T879
Test name
Test status
Simulation time 178195838066 ps
CPU time 162.07 seconds
Started Jul 04 05:38:36 PM PDT 24
Finished Jul 04 05:41:18 PM PDT 24
Peak memory 199880 kb
Host smart-f7d19bee-b14a-4799-9dfa-bfa716fe0b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523756571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.523756571
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2855776462
Short name T714
Test name
Test status
Simulation time 57129233229 ps
CPU time 48.38 seconds
Started Jul 04 05:38:36 PM PDT 24
Finished Jul 04 05:39:25 PM PDT 24
Peak memory 199936 kb
Host smart-5fd1bb3c-06fc-4278-b7b7-6e122a8356c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855776462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2855776462
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.4166007103
Short name T180
Test name
Test status
Simulation time 39115195108 ps
CPU time 35.18 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:39:11 PM PDT 24
Peak memory 199948 kb
Host smart-fd5d782e-b3de-49bc-aa50-c5d643f28640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166007103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4166007103
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2281102416
Short name T937
Test name
Test status
Simulation time 152411105969 ps
CPU time 203 seconds
Started Jul 04 05:38:34 PM PDT 24
Finished Jul 04 05:41:57 PM PDT 24
Peak memory 196000 kb
Host smart-8bc8b821-bcc5-4916-8777-48c6c4a6948c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281102416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2281102416
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1113871837
Short name T842
Test name
Test status
Simulation time 122349373260 ps
CPU time 426.06 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:45:42 PM PDT 24
Peak memory 200012 kb
Host smart-ba2c6ac9-a02f-4d3a-911d-e267f9e68257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113871837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1113871837
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1774568073
Short name T742
Test name
Test status
Simulation time 4326922153 ps
CPU time 6.74 seconds
Started Jul 04 05:38:37 PM PDT 24
Finished Jul 04 05:38:44 PM PDT 24
Peak memory 199268 kb
Host smart-12400089-3268-49ed-b8df-ecf9d5dbd09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774568073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1774568073
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1799069733
Short name T441
Test name
Test status
Simulation time 8030015976 ps
CPU time 13.72 seconds
Started Jul 04 05:38:33 PM PDT 24
Finished Jul 04 05:38:47 PM PDT 24
Peak memory 197636 kb
Host smart-ea010900-4eba-494e-8ddc-348aafd0d65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799069733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1799069733
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.478281336
Short name T502
Test name
Test status
Simulation time 17990036131 ps
CPU time 552.02 seconds
Started Jul 04 05:38:34 PM PDT 24
Finished Jul 04 05:47:46 PM PDT 24
Peak memory 199908 kb
Host smart-c76599f1-2fa4-499b-a14d-09f9e86769bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=478281336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.478281336
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2251641001
Short name T625
Test name
Test status
Simulation time 5748608565 ps
CPU time 49.52 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:39:25 PM PDT 24
Peak memory 198824 kb
Host smart-a627c362-57e7-4563-9c90-2d587170d8b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251641001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2251641001
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2485583381
Short name T722
Test name
Test status
Simulation time 120237081157 ps
CPU time 218.72 seconds
Started Jul 04 05:38:32 PM PDT 24
Finished Jul 04 05:42:11 PM PDT 24
Peak memory 199936 kb
Host smart-c918dc08-e3e5-46d1-b51b-e0dba119af90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485583381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2485583381
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1160946594
Short name T281
Test name
Test status
Simulation time 4987565792 ps
CPU time 6.98 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:38:42 PM PDT 24
Peak memory 196240 kb
Host smart-6e2459c1-86a4-4a18-8dc1-fb39d4075169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160946594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1160946594
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3817682615
Short name T887
Test name
Test status
Simulation time 518545475 ps
CPU time 1.3 seconds
Started Jul 04 05:38:39 PM PDT 24
Finished Jul 04 05:38:40 PM PDT 24
Peak memory 198384 kb
Host smart-0ef7b003-a78d-45e2-81e2-f3bf9a0ac81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817682615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3817682615
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3037946407
Short name T724
Test name
Test status
Simulation time 728951866865 ps
CPU time 648.69 seconds
Started Jul 04 05:38:36 PM PDT 24
Finished Jul 04 05:49:25 PM PDT 24
Peak memory 199964 kb
Host smart-8b0e65b9-c409-4689-a05c-4901e3fa2ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037946407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3037946407
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.606463841
Short name T98
Test name
Test status
Simulation time 9138243647 ps
CPU time 99.45 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:40:15 PM PDT 24
Peak memory 215880 kb
Host smart-82cc40a1-6f25-436e-a28f-3e0935f16e61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606463841 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.606463841
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3282472654
Short name T260
Test name
Test status
Simulation time 7361432731 ps
CPU time 9.48 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:38:45 PM PDT 24
Peak memory 199304 kb
Host smart-7b9e0c4a-e5de-4626-a754-bb520a073bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282472654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3282472654
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3779153410
Short name T783
Test name
Test status
Simulation time 107419789798 ps
CPU time 12.66 seconds
Started Jul 04 05:38:35 PM PDT 24
Finished Jul 04 05:38:47 PM PDT 24
Peak memory 199928 kb
Host smart-e9c56a56-2936-47b9-95d0-659b1fe5eb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779153410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3779153410
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3526586462
Short name T436
Test name
Test status
Simulation time 79832230165 ps
CPU time 20.06 seconds
Started Jul 04 05:42:35 PM PDT 24
Finished Jul 04 05:42:55 PM PDT 24
Peak memory 200032 kb
Host smart-6fcddd07-6b97-4be4-ae50-f617f114b4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526586462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3526586462
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1733193770
Short name T58
Test name
Test status
Simulation time 76420611525 ps
CPU time 676.41 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:53:53 PM PDT 24
Peak memory 216688 kb
Host smart-f06ce23d-15a1-4ac4-95c7-7887e1275c40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733193770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1733193770
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.135198090
Short name T272
Test name
Test status
Simulation time 90607219358 ps
CPU time 35.19 seconds
Started Jul 04 05:42:35 PM PDT 24
Finished Jul 04 05:43:10 PM PDT 24
Peak memory 199720 kb
Host smart-c3aaf332-b852-4efd-afde-a0dfac3d4f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135198090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.135198090
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2885035829
Short name T863
Test name
Test status
Simulation time 265648391060 ps
CPU time 434.81 seconds
Started Jul 04 05:42:28 PM PDT 24
Finished Jul 04 05:49:43 PM PDT 24
Peak memory 199932 kb
Host smart-3d5d0ac7-e679-4aa6-bd3c-7f16d9d1e9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885035829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2885035829
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3367072947
Short name T302
Test name
Test status
Simulation time 66831977679 ps
CPU time 387.45 seconds
Started Jul 04 05:42:38 PM PDT 24
Finished Jul 04 05:49:06 PM PDT 24
Peak memory 216400 kb
Host smart-38fc24cd-4252-4a75-82a4-0e13f1bf7295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367072947 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3367072947
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.454570221
Short name T554
Test name
Test status
Simulation time 35266221156 ps
CPU time 16.15 seconds
Started Jul 04 05:42:38 PM PDT 24
Finished Jul 04 05:42:55 PM PDT 24
Peak memory 199892 kb
Host smart-138a13a2-a99d-4a1f-a0f2-db06e970e99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454570221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.454570221
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1672307349
Short name T540
Test name
Test status
Simulation time 19513746667 ps
CPU time 114.72 seconds
Started Jul 04 05:42:38 PM PDT 24
Finished Jul 04 05:44:33 PM PDT 24
Peak memory 216708 kb
Host smart-99118a57-6d31-4175-a542-737b0d3359e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672307349 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1672307349
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3681120867
Short name T711
Test name
Test status
Simulation time 20644968602 ps
CPU time 9.38 seconds
Started Jul 04 05:42:35 PM PDT 24
Finished Jul 04 05:42:45 PM PDT 24
Peak memory 199792 kb
Host smart-5883477b-6977-4cdc-8409-f3bb7358135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681120867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3681120867
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3499455823
Short name T538
Test name
Test status
Simulation time 238653553206 ps
CPU time 312.77 seconds
Started Jul 04 05:42:35 PM PDT 24
Finished Jul 04 05:47:48 PM PDT 24
Peak memory 215888 kb
Host smart-25b5d4e7-3795-4d4b-a708-bfab72596722
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499455823 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3499455823
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.736956818
Short name T478
Test name
Test status
Simulation time 26862451944 ps
CPU time 26.09 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:43:04 PM PDT 24
Peak memory 199980 kb
Host smart-818c27fb-38c0-47a5-80a3-2e5370a169f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736956818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.736956818
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.496245600
Short name T988
Test name
Test status
Simulation time 134332946842 ps
CPU time 825.21 seconds
Started Jul 04 05:42:33 PM PDT 24
Finished Jul 04 05:56:19 PM PDT 24
Peak memory 224848 kb
Host smart-68c5c4f9-cda0-47f2-a12f-fc4dd53223de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496245600 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.496245600
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1400742927
Short name T966
Test name
Test status
Simulation time 70613822831 ps
CPU time 18.18 seconds
Started Jul 04 05:42:36 PM PDT 24
Finished Jul 04 05:42:54 PM PDT 24
Peak memory 199924 kb
Host smart-1aff0d9c-8942-47bc-be5a-ed89f2480dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400742927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1400742927
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3518028896
Short name T87
Test name
Test status
Simulation time 73927943480 ps
CPU time 324.75 seconds
Started Jul 04 05:42:37 PM PDT 24
Finished Jul 04 05:48:02 PM PDT 24
Peak memory 216708 kb
Host smart-d164e2e9-15c7-4533-9037-1a9042c7dbae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518028896 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3518028896
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.65158148
Short name T718
Test name
Test status
Simulation time 154663248211 ps
CPU time 246.52 seconds
Started Jul 04 05:42:35 PM PDT 24
Finished Jul 04 05:46:42 PM PDT 24
Peak memory 199968 kb
Host smart-77ad2e6f-3cbb-4c68-96cc-ea31d7cfa7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65158148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.65158148
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2726686806
Short name T380
Test name
Test status
Simulation time 18169807293 ps
CPU time 28.39 seconds
Started Jul 04 05:42:26 PM PDT 24
Finished Jul 04 05:42:55 PM PDT 24
Peak memory 199900 kb
Host smart-51aa37fa-1f91-4385-9968-e9b9dd33eb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726686806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2726686806
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1540499302
Short name T675
Test name
Test status
Simulation time 74001433875 ps
CPU time 791.76 seconds
Started Jul 04 05:42:38 PM PDT 24
Finished Jul 04 05:55:50 PM PDT 24
Peak memory 216648 kb
Host smart-1b905cf7-03e6-47d9-85d9-892fb36f0a01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540499302 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1540499302
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2711734297
Short name T205
Test name
Test status
Simulation time 43225636121 ps
CPU time 62.4 seconds
Started Jul 04 05:42:27 PM PDT 24
Finished Jul 04 05:43:30 PM PDT 24
Peak memory 199860 kb
Host smart-1717e98f-e3eb-4bba-a575-6f1c0285210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711734297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2711734297
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.283819049
Short name T662
Test name
Test status
Simulation time 53700261092 ps
CPU time 1353.85 seconds
Started Jul 04 05:42:35 PM PDT 24
Finished Jul 04 06:05:09 PM PDT 24
Peak memory 216656 kb
Host smart-7db57872-cde8-490b-aa2c-73a59d15c1f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283819049 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.283819049
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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