Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	108513	1			T1	2		T2	67		T3	20
all_values[1]	108513	1			T1	2		T2	67		T3	20
all_values[2]	108513	1			T1	2		T2	67		T3	20
all_values[3]	108513	1			T1	2		T2	67		T3	20
all_values[4]	108513	1			T1	2		T2	67		T3	20
all_values[5]	108513	1			T1	2		T2	67		T3	20
all_values[6]	108513	1			T1	2		T2	67		T3	20
all_values[7]	108513	1			T1	2		T2	67		T3	20
all_values[8]	108513	1			T1	2		T2	67		T3	20

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

497189

1

T1

18

T2

300

T3

84

auto[1]

479428

1

T2

303

T3

96

T5

747

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

887683

1

T1

13

T2

524

T3

161

auto[1]

88934

1

T1

5

T2

79

T3

19

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	31346	1			T2	22		T5	69		T8	122
all_values[0]	auto[0]	auto[1]	22055	1			T1	2		T2	10		T3	8
all_values[0]	auto[1]	auto[0]	33501	1			T2	13		T3	12		T5	4
all_values[0]	auto[1]	auto[1]	21611	1			T2	22		T5	27		T7	1
all_values[1]	auto[0]	auto[0]	51054	1			T1	2		T2	33		T3	20
all_values[1]	auto[0]	auto[1]	1724	1			T2	1		T5	14		T76	3
all_values[1]	auto[1]	auto[0]	54072	1			T2	30		T5	94		T7	1
all_values[1]	auto[1]	auto[1]	1663	1			T2	3		T8	39		T9	8
all_values[2]	auto[0]	auto[0]	52774	1			T1	1		T2	13		T3	3
all_values[2]	auto[0]	auto[1]	2670	1			T1	1		T2	5		T4	1
all_values[2]	auto[1]	auto[0]	50626	1			T2	44		T3	12		T5	68
all_values[2]	auto[1]	auto[1]	2443	1			T2	5		T3	5		T5	8
all_values[3]	auto[0]	auto[0]	54562	1			T1	2		T2	37		T3	8
all_values[3]	auto[0]	auto[1]	332	1			T8	1		T11	2		T78	1
all_values[3]	auto[1]	auto[0]	53301	1			T2	29		T3	12		T5	63
all_values[3]	auto[1]	auto[1]	318	1			T2	1		T12	1		T14	3
all_values[4]	auto[0]	auto[0]	53596	1			T1	2		T2	45		T3	8
all_values[4]	auto[0]	auto[1]	446	1			T13	1		T14	3		T16	22
all_values[4]	auto[1]	auto[0]	54067	1			T2	22		T3	12		T5	89
all_values[4]	auto[1]	auto[1]	404	1			T13	1		T14	5		T28	1
all_values[5]	auto[0]	auto[0]	57585	1			T1	2		T2	55		T3	3
all_values[5]	auto[0]	auto[1]	206	1			T2	2		T13	1		T14	4
all_values[5]	auto[1]	auto[0]	50509	1			T2	10		T3	17		T5	50
all_values[5]	auto[1]	auto[1]	213	1			T14	6		T32	1		T33	2
all_values[6]	auto[0]	auto[0]	57748	1			T1	2		T2	10		T3	13
all_values[6]	auto[0]	auto[1]	172	1			T13	1		T14	4		T19	3
all_values[6]	auto[1]	auto[0]	50399	1			T2	57		T3	7		T5	76
all_values[6]	auto[1]	auto[1]	194	1			T13	2		T14	6		T19	5
all_values[7]	auto[0]	auto[0]	53277	1			T1	2		T2	57		T3	20
all_values[7]	auto[0]	auto[1]	401	1			T2	3		T12	5		T13	2
all_values[7]	auto[1]	auto[0]	54450	1			T2	6		T5	136		T8	153
all_values[7]	auto[1]	auto[1]	385	1			T2	1		T5	5		T13	2
all_values[8]	auto[0]	auto[0]	38722	1			T2	1		T5	13		T8	57
all_values[8]	auto[0]	auto[1]	18519	1			T1	2		T2	6		T3	1
all_values[8]	auto[1]	auto[0]	36094	1			T2	40		T3	14		T5	91
all_values[8]	auto[1]	auto[1]	15178	1			T2	20		T3	5		T5	36