Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2247	1			T2	6		T3	3		T5	2
auto[BaudRate115200]	1953	1			T1	1		T2	4		T3	3
auto[BaudRate230400]	1911	1			T2	2		T3	2		T4	1
auto[BaudRate128Kbps]	1926	1			T2	5		T3	1		T5	1
auto[BaudRate256Kbps]	2064	1			T2	2		T3	1		T5	2
auto[BaudRate1Mbps]	1928	1			T2	4		T5	2		T7	6
auto[BaudRate1p5Mbps]	1334	1			T1	1		T2	3		T7	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1327	1			T1	2		T9	9		T12	5
freqs[25]	1103	1			T11	71		T115	1		T249	10
freqs[48]	429	1			T4	2		T247	5		T28	63
freqs[50]	444	1			T21	53		T311	33		T177	7
freqs[100]	1230	1			T7	30		T76	6		T120	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	187	1			T12	1		T14	2		T272	1
auto[BaudRate9600]	freqs[25]	207	1			T11	10		T249	2		T296	2
auto[BaudRate9600]	freqs[48]	40	1			T247	1		T28	4		T119	1
auto[BaudRate9600]	freqs[50]	74	1			T21	7		T177	1		T239	1
auto[BaudRate9600]	freqs[100]	247	1			T76	1		T312	3		T116	1
auto[BaudRate115200]	freqs[24]	175	1			T1	1		T9	2		T12	1
auto[BaudRate115200]	freqs[25]	148	1			T11	9		T249	3		T238	1
auto[BaudRate115200]	freqs[48]	87	1			T4	1		T247	1		T28	15
auto[BaudRate115200]	freqs[50]	51	1			T21	4		T177	1		T206	5
auto[BaudRate115200]	freqs[100]	168	1			T7	12		T76	1		T120	2
auto[BaudRate230400]	freqs[24]	216	1			T9	1		T12	1		T243	2
auto[BaudRate230400]	freqs[25]	151	1			T11	13		T296	1		T238	2
auto[BaudRate230400]	freqs[48]	57	1			T4	1		T247	1		T28	5
auto[BaudRate230400]	freqs[50]	57	1			T21	5		T311	3		T177	2
auto[BaudRate230400]	freqs[100]	155	1			T7	3		T76	1		T120	2
auto[BaudRate128Kbps]	freqs[24]	194	1			T9	3		T14	1		T243	3
auto[BaudRate128Kbps]	freqs[25]	158	1			T11	15		T249	1		T64	1
auto[BaudRate128Kbps]	freqs[48]	57	1			T247	1		T28	6		T123	6
auto[BaudRate128Kbps]	freqs[50]	55	1			T21	13		T311	3		T206	1
auto[BaudRate128Kbps]	freqs[100]	185	1			T7	6		T312	6		T116	1
auto[BaudRate256Kbps]	freqs[24]	229	1			T14	1		T243	1		T19	13
auto[BaudRate256Kbps]	freqs[25]	169	1			T11	10		T249	1		T64	1
auto[BaudRate256Kbps]	freqs[48]	60	1			T28	15		T123	5		T313	1
auto[BaudRate256Kbps]	freqs[50]	72	1			T21	12		T311	18		T177	1
auto[BaudRate256Kbps]	freqs[100]	143	1			T120	1		T312	3		T116	1
auto[BaudRate1Mbps]	freqs[24]	220	1			T9	2		T12	1		T14	4
auto[BaudRate1Mbps]	freqs[25]	179	1			T11	11		T115	1		T249	2
auto[BaudRate1Mbps]	freqs[48]	67	1			T247	1		T28	10		T123	9
auto[BaudRate1Mbps]	freqs[50]	75	1			T21	10		T311	6		T177	1
auto[BaudRate1Mbps]	freqs[100]	190	1			T7	6		T120	3		T312	6
auto[BaudRate1p5Mbps]	freqs[25]	91	1			T11	3		T249	1		T91	1
auto[BaudRate1p5Mbps]	freqs[48]	61	1			T28	8		T123	8		T313	1
auto[BaudRate1p5Mbps]	freqs[50]	60	1			T21	2		T311	3		T177	1
auto[BaudRate1p5Mbps]	freqs[100]	142	1			T7	3		T76	3		T120	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded