Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.91	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	12	118	90.77

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	12	118	90.77	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29629198	1			T2	269		T3	60		T5	262
all_levels[1]	179701	1			T2	20		T5	12		T8	152
all_levels[2]	2331	1			T2	9		T5	6		T8	15
all_levels[3]	1006	1			T2	8		T5	5		T8	4
all_levels[4]	684	1			T2	2		T5	5		T8	13
all_levels[5]	550	1			T2	4		T5	1		T8	3
all_levels[6]	446	1			T2	1		T3	3		T5	6
all_levels[7]	349	1			T5	3		T8	3		T10	2
all_levels[8]	256	1			T5	1		T8	1		T11	2
all_levels[9]	244	1			T2	1		T3	1		T5	2
all_levels[10]	214	1			T3	1		T5	4		T8	2
all_levels[11]	185	1			T5	2		T8	1		T11	1
all_levels[12]	174	1			T10	1		T77	3		T115	1
all_levels[13]	137	1			T2	1		T8	1		T10	1
all_levels[14]	147	1			T5	1		T77	1		T13	1
all_levels[15]	123	1			T10	1		T76	2		T77	3
all_levels[16]	111	1			T8	1		T11	2		T77	1
all_levels[17]	103	1			T5	1		T76	1		T77	1
all_levels[18]	89	1			T77	2		T116	1		T117	1
all_levels[19]	76	1			T13	1		T35	2		T118	1
all_levels[20]	84	1			T8	3		T11	1		T77	1
all_levels[21]	95	1			T5	2		T10	2		T77	1
all_levels[22]	62	1			T3	1		T10	1		T119	1
all_levels[23]	59	1			T10	1		T77	1		T120	1
all_levels[24]	54	1			T10	1		T117	1		T121	1
all_levels[25]	55	1			T76	1		T19	2		T122	1
all_levels[26]	45	1			T5	1		T8	1		T123	1
all_levels[27]	60	1			T117	1		T124	1		T32	1
all_levels[28]	47	1			T117	1		T125	1		T126	1
all_levels[29]	51	1			T11	2		T127	1		T128	1
all_levels[30]	35	1			T8	1		T117	1		T19	2
all_levels[31]	39	1			T5	1		T123	1		T129	1
all_levels[32]	45	1			T14	1		T130	2		T111	1
all_levels[33]	28	1			T121	1		T111	1		T122	1
all_levels[34]	24	1			T121	1		T131	1		T127	1
all_levels[35]	24	1			T111	1		T132	2		T99	1
all_levels[36]	24	1			T76	1		T32	1		T111	1
all_levels[37]	22	1			T3	1		T123	1		T127	1
all_levels[38]	19	1			T133	1		T129	1		T134	1
all_levels[39]	12	1			T129	1		T135	1		T100	1
all_levels[40]	19	1			T31	1		T129	1		T136	1
all_levels[41]	22	1			T129	1		T137	1		T138	3
all_levels[42]	24	1			T139	1		T127	1		T140	1
all_levels[43]	18	1			T32	1		T141	2		T136	1
all_levels[44]	14	1			T129	2		T135	1		T142	1
all_levels[45]	10	1			T111	1		T123	1		T143	1
all_levels[46]	12	1			T12	1		T36	1		T19	1
all_levels[47]	13	1			T35	1		T144	1		T145	1
all_levels[48]	8	1			T146	1		T147	1		T148	1
all_levels[49]	9	1			T149	2		T129	1		T150	1
all_levels[50]	18	1			T28	1		T137	1		T151	3
all_levels[51]	4	1			T152	1		T153	1		T154	1
all_levels[52]	10	1			T155	1		T40	1		T156	1
all_levels[53]	12	1			T58	1		T155	1		T157	2
all_levels[54]	7	1			T36	1		T58	1		T101	1
all_levels[55]	9	1			T158	1		T159	1		T44	1
all_levels[56]	7	1			T19	2		T160	1		T161	1
all_levels[57]	9	1			T162	1		T134	1		T163	1
all_levels[58]	4	1			T164	1		T165	1		T166	1
all_levels[59]	7	1			T167	1		T168	1		T169	1
all_levels[60]	9	1			T58	2		T170	2		T165	1
all_levels[61]	11	1			T12	1		T171	1		T136	1
all_levels[62]	3	1			T172	1		T173	1		T174	1
all_levels[63]	7	1			T12	1		T36	1		T175	1
all_levels[64]	125	1			T12	1		T78	2		T13	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29812561

1

T2

315

T3

62

T5

315

auto[1]

4838

1

T3

5

T7

3

T8

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	12	118	90.77	12

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[44] , all_levels[45] , all_levels[46]]	[auto[1]]	--	--	3
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[54] , all_levels[55]]	[auto[1]]	--	--	2
[all_levels[58] , all_levels[59]]	[auto[1]]	--	--	2
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29624798	1			T2	269		T3	55		T5	262
all_levels[0]	auto[1]	4400	1			T3	5		T7	3		T8	3
all_levels[1]	auto[0]	179651	1			T2	20		T5	12		T8	152
all_levels[1]	auto[1]	50	1			T116	2		T117	1		T176	1
all_levels[2]	auto[0]	2296	1			T2	9		T5	6		T8	15
all_levels[2]	auto[1]	35	1			T171	2		T177	1		T178	1
all_levels[3]	auto[0]	987	1			T2	8		T5	5		T8	4
all_levels[3]	auto[1]	19	1			T179	4		T95	1		T180	1
all_levels[4]	auto[0]	671	1			T2	2		T5	5		T8	13
all_levels[4]	auto[1]	13	1			T129	1		T135	1		T181	1
all_levels[5]	auto[0]	533	1			T2	4		T5	1		T8	3
all_levels[5]	auto[1]	17	1			T117	2		T182	2		T183	1
all_levels[6]	auto[0]	435	1			T2	1		T3	3		T5	6
all_levels[6]	auto[1]	11	1			T184	1		T185	1		T186	2
all_levels[7]	auto[0]	325	1			T5	3		T8	3		T10	2
all_levels[7]	auto[1]	24	1			T130	1		T133	1		T187	1
all_levels[8]	auto[0]	245	1			T5	1		T8	1		T11	2
all_levels[8]	auto[1]	11	1			T57	1		T178	1		T180	1
all_levels[9]	auto[0]	235	1			T2	1		T3	1		T5	2
all_levels[9]	auto[1]	9	1			T188	3		T189	3		T190	1
all_levels[10]	auto[0]	199	1			T3	1		T5	4		T8	2
all_levels[10]	auto[1]	15	1			T119	1		T191	1		T192	3
all_levels[11]	auto[0]	170	1			T5	2		T8	1		T11	1
all_levels[11]	auto[1]	15	1			T146	1		T135	1		T193	2
all_levels[12]	auto[0]	163	1			T10	1		T77	3		T115	1
all_levels[12]	auto[1]	11	1			T108	1		T183	2		T158	1
all_levels[13]	auto[0]	130	1			T2	1		T8	1		T10	1
all_levels[13]	auto[1]	7	1			T189	1		T194	1		T195	1
all_levels[14]	auto[0]	132	1			T5	1		T77	1		T13	1
all_levels[14]	auto[1]	15	1			T196	1		T197	1		T198	2
all_levels[15]	auto[0]	113	1			T10	1		T76	1		T77	3
all_levels[15]	auto[1]	10	1			T76	1		T179	1		T199	2
all_levels[16]	auto[0]	105	1			T8	1		T11	1		T77	1
all_levels[16]	auto[1]	6	1			T11	1		T200	2		T201	1
all_levels[17]	auto[0]	95	1			T5	1		T76	1		T77	1
all_levels[17]	auto[1]	8	1			T100	1		T202	1		T203	1
all_levels[18]	auto[0]	77	1			T77	2		T116	1		T117	1
all_levels[18]	auto[1]	12	1			T204	2		T193	1		T205	2
all_levels[19]	auto[0]	75	1			T13	1		T35	2		T118	1
all_levels[19]	auto[1]	1	1			T40	1		-	-		-	-
all_levels[20]	auto[0]	72	1			T8	1		T11	1		T77	1
all_levels[20]	auto[1]	12	1			T8	2		T206	2		T127	2
all_levels[21]	auto[0]	82	1			T5	2		T10	1		T77	1
all_levels[21]	auto[1]	13	1			T10	1		T207	1		T208	3
all_levels[22]	auto[0]	58	1			T3	1		T10	1		T119	1
all_levels[22]	auto[1]	4	1			T184	1		T209	3		-	-
all_levels[23]	auto[0]	57	1			T10	1		T77	1		T120	1
all_levels[23]	auto[1]	2	1			T210	2		-	-		-	-
all_levels[24]	auto[0]	50	1			T10	1		T117	1		T121	1
all_levels[24]	auto[1]	4	1			T211	1		T212	3		-	-
all_levels[25]	auto[0]	46	1			T76	1		T19	1		T122	1
all_levels[25]	auto[1]	9	1			T19	1		T208	2		T136	1
all_levels[26]	auto[0]	42	1			T5	1		T8	1		T123	1
all_levels[26]	auto[1]	3	1			T213	1		T214	1		T215	1
all_levels[27]	auto[0]	51	1			T117	1		T124	1		T32	1
all_levels[27]	auto[1]	9	1			T216	1		T169	2		T217	1
all_levels[28]	auto[0]	39	1			T117	1		T125	1		T126	1
all_levels[28]	auto[1]	8	1			T218	1		T219	2		T203	1
all_levels[29]	auto[0]	42	1			T11	1		T127	1		T128	1
all_levels[29]	auto[1]	9	1			T11	1		T220	2		T221	3
all_levels[30]	auto[0]	33	1			T8	1		T117	1		T19	2
all_levels[30]	auto[1]	2	1			T129	1		T222	1		-	-
all_levels[31]	auto[0]	32	1			T5	1		T123	1		T129	1
all_levels[31]	auto[1]	7	1			T187	1		T147	1		T152	1
all_levels[32]	auto[0]	40	1			T14	1		T130	1		T111	1
all_levels[32]	auto[1]	5	1			T130	1		T39	1		T223	1
all_levels[33]	auto[0]	24	1			T121	1		T111	1		T122	1
all_levels[33]	auto[1]	4	1			T158	1		T54	2		T224	1
all_levels[34]	auto[0]	20	1			T121	1		T131	1		T127	1
all_levels[34]	auto[1]	4	1			T136	2		T225	1		T226	1
all_levels[35]	auto[0]	22	1			T111	1		T132	2		T99	1
all_levels[35]	auto[1]	2	1			T227	1		T228	1		-	-
all_levels[36]	auto[0]	22	1			T76	1		T32	1		T111	1
all_levels[36]	auto[1]	2	1			T229	2		-	-		-	-
all_levels[37]	auto[0]	21	1			T3	1		T123	1		T127	1
all_levels[37]	auto[1]	1	1			T157	1		-	-		-	-
all_levels[38]	auto[0]	17	1			T133	1		T129	1		T134	1
all_levels[38]	auto[1]	2	1			T164	2		-	-		-	-
all_levels[39]	auto[0]	11	1			T129	1		T135	1		T100	1
all_levels[39]	auto[1]	1	1			T189	1		-	-		-	-
all_levels[40]	auto[0]	18	1			T31	1		T129	1		T136	1
all_levels[40]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[41]	auto[0]	17	1			T129	1		T137	1		T138	1
all_levels[41]	auto[1]	5	1			T138	2		T231	3		-	-
all_levels[42]	auto[0]	20	1			T139	1		T127	1		T140	1
all_levels[42]	auto[1]	4	1			T138	1		T232	3		-	-
all_levels[43]	auto[0]	17	1			T32	1		T141	1		T136	1
all_levels[43]	auto[1]	1	1			T141	1		-	-		-	-
all_levels[44]	auto[0]	14	1			T129	2		T135	1		T142	1
all_levels[45]	auto[0]	10	1			T111	1		T123	1		T143	1
all_levels[46]	auto[0]	12	1			T12	1		T36	1		T19	1
all_levels[47]	auto[0]	12	1			T35	1		T144	1		T145	1
all_levels[47]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[48]	auto[0]	8	1			T146	1		T147	1		T148	1
all_levels[49]	auto[0]	8	1			T149	1		T129	1		T150	1
all_levels[49]	auto[1]	1	1			T149	1		-	-		-	-
all_levels[50]	auto[0]	15	1			T28	1		T137	1		T151	1
all_levels[50]	auto[1]	3	1			T151	2		T185	1		-	-
all_levels[51]	auto[0]	4	1			T152	1		T153	1		T154	1
all_levels[52]	auto[0]	10	1			T155	1		T40	1		T156	1
all_levels[53]	auto[0]	11	1			T58	1		T155	1		T157	2
all_levels[53]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[54]	auto[0]	7	1			T36	1		T58	1		T101	1
all_levels[55]	auto[0]	9	1			T158	1		T159	1		T44	1
all_levels[56]	auto[0]	6	1			T19	1		T160	1		T161	1
all_levels[56]	auto[1]	1	1			T19	1		-	-		-	-
all_levels[57]	auto[0]	7	1			T162	1		T134	1		T163	1
all_levels[57]	auto[1]	2	1			T235	1		T236	1		-	-
all_levels[58]	auto[0]	4	1			T164	1		T165	1		T166	1
all_levels[59]	auto[0]	7	1			T167	1		T168	1		T169	1
all_levels[60]	auto[0]	8	1			T58	1		T170	2		T165	1
all_levels[60]	auto[1]	1	1			T58	1		-	-		-	-
all_levels[61]	auto[0]	10	1			T12	1		T171	1		T136	1
all_levels[61]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[62]	auto[0]	3	1			T172	1		T173	1		T174	1
all_levels[63]	auto[0]	7	1			T12	1		T36	1		T175	1
all_levels[64]	auto[0]	101	1			T12	1		T78	1		T13	1
all_levels[64]	auto[1]	24	1			T78	1		T171	1		T229	3