Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 1 7 87.50 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 1 7 87.50


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1317 1 T2 4 T8 30 T9 8
all_levels[1] 788 1 T76 3 T77 1 T35 3
all_levels[2] 554 1 T8 9 T11 2 T12 2
all_levels[3] 318 1 T5 1 T11 8 T12 2
all_levels[4] 244 1 T5 13 T17 4 T107 11
all_levels[5] 119 1 T35 1 T19 5 T108 7
all_levels[6] 46 1 T18 5 T109 3 T110 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%