Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	108513	1			T1	2		T2	67		T3	20
all_pins[1]	108513	1			T1	2		T2	67		T3	20
all_pins[2]	108513	1			T1	2		T2	67		T3	20
all_pins[3]	108513	1			T1	2		T2	67		T3	20
all_pins[4]	108513	1			T1	2		T2	67		T3	20
all_pins[5]	108513	1			T1	2		T2	67		T3	20
all_pins[6]	108513	1			T1	2		T2	67		T3	20
all_pins[7]	108513	1			T1	2		T2	67		T3	20
all_pins[8]	108513	1			T1	2		T2	67		T3	20

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	933259	1			T1	18		T2	548		T3	168
values[0x1]	43358	1			T2	55		T3	12		T5	76
transitions[0x0=>0x1]	34478	1			T2	39		T3	12		T5	45
transitions[0x1=>0x0]	34265	1			T2	39		T3	12		T5	45

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	86818	1			T1	2		T2	44		T3	20
all_pins[0]	values[0x1]	21695	1			T2	23		T5	27		T7	1
all_pins[0]	transitions[0x0=>0x1]	21134	1			T2	21		T5	27		T7	1
all_pins[0]	transitions[0x1=>0x0]	1108	1			T2	1		T8	39		T9	8
all_pins[1]	values[0x0]	106844	1			T1	2		T2	64		T3	20
all_pins[1]	values[0x1]	1669	1			T2	3		T8	39		T9	8
all_pins[1]	transitions[0x0=>0x1]	1547	1			T2	3		T8	39		T9	8
all_pins[1]	transitions[0x1=>0x0]	2386	1			T2	5		T3	5		T5	8
all_pins[2]	values[0x0]	106005	1			T1	2		T2	62		T3	15
all_pins[2]	values[0x1]	2508	1			T2	5		T3	5		T5	8
all_pins[2]	transitions[0x0=>0x1]	2424	1			T2	5		T3	5		T5	8
all_pins[2]	transitions[0x1=>0x0]	234	1			T2	1		T14	3		T19	5
all_pins[3]	values[0x0]	108195	1			T1	2		T2	66		T3	20
all_pins[3]	values[0x1]	318	1			T2	1		T12	1		T14	3
all_pins[3]	transitions[0x0=>0x1]	276	1			T2	1		T12	1		T14	2
all_pins[3]	transitions[0x1=>0x0]	362	1			T13	1		T14	4		T28	1
all_pins[4]	values[0x0]	108109	1			T1	2		T2	67		T3	20
all_pins[4]	values[0x1]	404	1			T13	1		T14	5		T28	1
all_pins[4]	transitions[0x0=>0x1]	340	1			T13	1		T14	3		T28	1
all_pins[4]	transitions[0x1=>0x0]	190	1			T14	4		T17	1		T32	1
all_pins[5]	values[0x0]	108259	1			T1	2		T2	67		T3	20
all_pins[5]	values[0x1]	254	1			T14	6		T17	2		T32	1
all_pins[5]	transitions[0x0=>0x1]	199	1			T14	4		T17	2		T18	3
all_pins[5]	transitions[0x1=>0x0]	814	1			T2	2		T3	2		T8	6
all_pins[6]	values[0x0]	107644	1			T1	2		T2	65		T3	18
all_pins[6]	values[0x1]	869	1			T2	2		T3	2		T8	6
all_pins[6]	transitions[0x0=>0x1]	801	1			T2	2		T3	2		T8	6
all_pins[6]	transitions[0x1=>0x0]	313	1			T2	1		T5	5		T13	2
all_pins[7]	values[0x0]	108132	1			T1	2		T2	66		T3	20
all_pins[7]	values[0x1]	381	1			T2	1		T5	5		T13	2
all_pins[7]	transitions[0x0=>0x1]	204	1			T14	3		T35	2		T36	2
all_pins[7]	transitions[0x1=>0x0]	15083	1			T2	19		T3	5		T5	31
all_pins[8]	values[0x0]	93253	1			T1	2		T2	47		T3	15
all_pins[8]	values[0x1]	15260	1			T2	20		T3	5		T5	36
all_pins[8]	transitions[0x0=>0x1]	7553	1			T2	7		T3	5		T5	10
all_pins[8]	transitions[0x1=>0x0]	13775	1			T2	10		T5	1		T8	25