Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7270006	1			T2	87		T3	15		T5	86
all_levels[1]	1619517	1			T2	53		T3	1		T5	139
all_levels[2]	317426	1			T2	21		T8	746		T9	2202
all_levels[3]	286489	1			T2	2		T3	3		T5	4
all_levels[4]	606269	1			T2	110		T5	1		T8	1009
all_levels[5]	240376	1			T2	6		T5	6		T8	717
all_levels[6]	193291	1			T3	1		T5	7		T8	742
all_levels[7]	315660	1			T2	4		T3	4		T8	744
all_levels[8]	212817	1			T3	1		T8	727		T9	2211
all_levels[9]	241953	1			T2	2		T8	747		T9	2210
all_levels[10]	205087	1			T8	750		T9	2212		T11	5
all_levels[11]	247431	1			T3	7		T8	722		T9	2211
all_levels[12]	275020	1			T5	13		T8	734		T9	57332
all_levels[13]	178891	1			T2	2		T5	11		T8	745
all_levels[14]	199365	1			T2	9		T8	753		T9	1664
all_levels[15]	166630	1			T2	8		T8	724		T9	1649
all_levels[16]	191798	1			T8	750		T9	1586		T10	1
all_levels[17]	319656	1			T2	3		T8	735		T9	637
all_levels[18]	264143	1			T2	2		T8	737		T9	639
all_levels[19]	467383	1			T2	1		T5	11		T8	712
all_levels[20]	173086	1			T5	4		T8	754		T9	625
all_levels[21]	193855	1			T5	1		T8	751		T9	631
all_levels[22]	210286	1			T5	1		T8	764		T9	630
all_levels[23]	217191	1			T5	1		T8	716		T9	625
all_levels[24]	185293	1			T5	3		T8	728		T9	636
all_levels[25]	311003	1			T3	37		T5	2		T8	733
all_levels[26]	203865	1			T5	6		T8	738		T9	628
all_levels[27]	418791	1			T2	2		T5	4		T8	772
all_levels[28]	194123	1			T2	3		T5	3		T8	742
all_levels[29]	333493	1			T5	2		T8	737		T9	625
all_levels[30]	201213	1			T5	7		T8	738		T9	631
all_levels[31]	487336	1			T8	974		T9	3043		T11	6
all_levels[32]	12868256	1			T3	3		T5	4		T8	10448

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29812561

1

T2

315

T3

62

T5

315

auto[1]

4438

1

T3

10

T5

1

T8

10

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7267466	1			T2	87		T3	11		T5	86
all_levels[0]	auto[1]	2540	1			T3	4		T8	3		T10	3
all_levels[1]	auto[0]	1619123	1			T2	53		T3	1		T5	138
all_levels[1]	auto[1]	394	1			T5	1		T11	3		T115	1
all_levels[2]	auto[0]	317386	1			T2	21		T8	746		T9	2202
all_levels[2]	auto[1]	40	1			T252	3		T108	2		T255	1
all_levels[3]	auto[0]	286355	1			T2	2		T3	2		T5	4
all_levels[3]	auto[1]	134	1			T3	1		T16	4		T29	1
all_levels[4]	auto[0]	606245	1			T2	110		T5	1		T8	1008
all_levels[4]	auto[1]	24	1			T8	1		T279	1		T146	1
all_levels[5]	auto[0]	240356	1			T2	6		T5	6		T8	717
all_levels[5]	auto[1]	20	1			T19	3		T149	3		T180	2
all_levels[6]	auto[0]	193259	1			T3	1		T5	7		T8	742
all_levels[6]	auto[1]	32	1			T11	2		T139	2		T58	2
all_levels[7]	auto[0]	315489	1			T2	4		T3	3		T8	744
all_levels[7]	auto[1]	171	1			T3	1		T13	4		T17	20
all_levels[8]	auto[0]	212792	1			T3	1		T8	727		T9	2211
all_levels[8]	auto[1]	25	1			T208	1		T314	1		T315	1
all_levels[9]	auto[0]	241930	1			T2	2		T8	747		T9	2210
all_levels[9]	auto[1]	23	1			T207	4		T146	1		T184	1
all_levels[10]	auto[0]	205066	1			T8	750		T9	2212		T11	5
all_levels[10]	auto[1]	21	1			T108	2		T245	1		T164	2
all_levels[11]	auto[0]	247407	1			T3	6		T8	722		T9	2211
all_levels[11]	auto[1]	24	1			T3	1		T139	1		T264	1
all_levels[12]	auto[0]	274992	1			T5	13		T8	734		T9	57332
all_levels[12]	auto[1]	28	1			T297	1		T295	1		T188	1
all_levels[13]	auto[0]	178865	1			T2	2		T5	11		T8	745
all_levels[13]	auto[1]	26	1			T76	2		T95	1		T33	1
all_levels[14]	auto[0]	199355	1			T2	9		T8	753		T9	1664
all_levels[14]	auto[1]	10	1			T133	1		T151	1		T186	1
all_levels[15]	auto[0]	166542	1			T2	8		T8	721		T9	1649
all_levels[15]	auto[1]	88	1			T8	3		T10	1		T11	2
all_levels[16]	auto[0]	191780	1			T8	750		T9	1586		T10	1
all_levels[16]	auto[1]	18	1			T247	1		T241	2		T313	1
all_levels[17]	auto[0]	319632	1			T2	3		T8	735		T9	637
all_levels[17]	auto[1]	24	1			T58	2		T196	3		T208	1
all_levels[18]	auto[0]	264123	1			T2	2		T8	737		T9	639
all_levels[18]	auto[1]	20	1			T267	1		T273	1		T307	1
all_levels[19]	auto[0]	467356	1			T2	1		T5	11		T8	712
all_levels[19]	auto[1]	27	1			T316	1		T141	2		T176	1
all_levels[20]	auto[0]	173065	1			T5	4		T8	753		T9	625
all_levels[20]	auto[1]	21	1			T8	1		T10	1		T317	2
all_levels[21]	auto[0]	193841	1			T5	1		T8	751		T9	631
all_levels[21]	auto[1]	14	1			T58	1		T179	1		T132	2
all_levels[22]	auto[0]	210271	1			T5	1		T8	764		T9	630
all_levels[22]	auto[1]	15	1			T116	2		T318	1		T290	1
all_levels[23]	auto[0]	217172	1			T5	1		T8	716		T9	625
all_levels[23]	auto[1]	19	1			T108	2		T163	1		T319	1
all_levels[24]	auto[0]	185270	1			T5	3		T8	728		T9	636
all_levels[24]	auto[1]	23	1			T296	1		T19	1		T140	1
all_levels[25]	auto[0]	310983	1			T3	35		T5	2		T8	733
all_levels[25]	auto[1]	20	1			T3	2		T255	1		T208	2
all_levels[26]	auto[0]	203852	1			T5	6		T8	737		T9	628
all_levels[26]	auto[1]	13	1			T8	1		T185	1		T183	2
all_levels[27]	auto[0]	418769	1			T2	2		T5	4		T8	772
all_levels[27]	auto[1]	22	1			T78	1		T241	1		T320	1
all_levels[28]	auto[0]	194104	1			T2	3		T5	3		T8	742
all_levels[28]	auto[1]	19	1			T78	1		T316	1		T284	2
all_levels[29]	auto[0]	333470	1			T5	2		T8	737		T9	625
all_levels[29]	auto[1]	23	1			T10	1		T21	1		T177	5
all_levels[30]	auto[0]	201190	1			T5	7		T8	738		T9	631
all_levels[30]	auto[1]	23	1			T57	2		T206	2		T321	1
all_levels[31]	auto[0]	487322	1			T8	974		T9	3043		T11	6
all_levels[31]	auto[1]	14	1			T241	1		T129	2		T39	2
all_levels[32]	auto[0]	12867733	1			T3	2		T5	4		T8	10447
all_levels[32]	auto[1]	523	1			T3	1		T8	1		T10	5