Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	858	1			T2	7		T13	7		T14	18
all_values[1]	858	1			T2	7		T13	7		T14	18
all_values[2]	858	1			T2	7		T13	7		T14	18
all_values[3]	858	1			T2	7		T13	7		T14	18
all_values[4]	858	1			T2	7		T13	7		T14	18
all_values[5]	858	1			T2	7		T13	7		T14	18
all_values[6]	858	1			T2	7		T13	7		T14	18
all_values[7]	858	1			T2	7		T13	7		T14	18
all_values[8]	858	1			T2	7		T13	7		T14	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4113

1

T2

28

T13

32

T14

86

auto[1]

3609

1

T2

35

T13

31

T14

76

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2585

1

T2

25

T13

19

T14

55

auto[1]

5137

1

T2

38

T13

44

T14

107

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4601

1

T2

33

T13

34

T14

97

auto[1]

3121

1

T2

30

T13

29

T14

65

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	251	1			T2	2		T13	1		T14	5
all_values[0]	auto[0]	auto[1]	auto[1]	258	1			T2	1		T13	4		T14	7
all_values[0]	auto[1]	auto[0]	auto[1]	194	1			T2	2		T13	2		T14	3
all_values[0]	auto[1]	auto[1]	auto[1]	155	1			T2	2		T14	3		T28	1
all_values[1]	auto[0]	auto[0]	auto[0]	294	1			T2	2		T13	2		T14	4
all_values[1]	auto[0]	auto[1]	auto[0]	234	1			T2	1		T13	1		T14	4
all_values[1]	auto[1]	auto[0]	auto[1]	184	1			T2	1		T14	6		T28	2
all_values[1]	auto[1]	auto[1]	auto[1]	146	1			T2	3		T13	4		T14	4
all_values[2]	auto[0]	auto[0]	auto[0]	166	1			T2	2		T14	5		T28	2
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T2	1		T13	1		T14	4
all_values[2]	auto[0]	auto[1]	auto[0]	165	1			T13	2		T14	3		T28	1
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T28	1		T19	1		T111	2
all_values[2]	auto[1]	auto[0]	auto[1]	183	1			T2	3		T14	4		T28	4
all_values[2]	auto[1]	auto[1]	auto[1]	171	1			T2	1		T13	4		T14	2
all_values[3]	auto[0]	auto[0]	auto[0]	228	1			T2	4		T13	2		T14	5
all_values[3]	auto[0]	auto[0]	auto[1]	90	1			T13	1		T14	3		T28	2
all_values[3]	auto[0]	auto[1]	auto[0]	124	1			T13	1		T14	2		T28	1
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T14	1		T19	1		T32	3
all_values[3]	auto[1]	auto[0]	auto[1]	177	1			T2	1		T13	2		T14	4
all_values[3]	auto[1]	auto[1]	auto[1]	155	1			T2	2		T13	1		T14	3
all_values[4]	auto[0]	auto[0]	auto[0]	187	1			T2	2		T13	1		T14	6
all_values[4]	auto[0]	auto[0]	auto[1]	71	1			T13	1		T14	1		T19	2
all_values[4]	auto[0]	auto[1]	auto[0]	173	1			T2	4		T13	2		T14	4
all_values[4]	auto[0]	auto[1]	auto[1]	82	1			T14	2		T28	1		T19	2
all_values[4]	auto[1]	auto[0]	auto[1]	188	1			T2	1		T13	1		T14	4
all_values[4]	auto[1]	auto[1]	auto[1]	157	1			T13	2		T14	1		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	180	1			T13	3		T14	3		T28	2
all_values[5]	auto[0]	auto[0]	auto[1]	86	1			T13	1		T14	2		T28	2
all_values[5]	auto[0]	auto[1]	auto[0]	148	1			T2	2		T13	1		T14	5
all_values[5]	auto[0]	auto[1]	auto[1]	95	1			T14	3		T32	1		T33	2
all_values[5]	auto[1]	auto[0]	auto[1]	190	1			T2	3		T13	2		T14	2
all_values[5]	auto[1]	auto[1]	auto[1]	159	1			T2	2		T14	3		T19	1
all_values[6]	auto[0]	auto[0]	auto[0]	193	1			T2	1		T13	3		T14	1
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T14	2		T19	1		T33	1
all_values[6]	auto[0]	auto[1]	auto[0]	179	1			T2	5		T14	5		T28	3
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T13	1		T14	1		T19	1
all_values[6]	auto[1]	auto[0]	auto[1]	178	1			T13	1		T14	3		T19	2
all_values[6]	auto[1]	auto[1]	auto[1]	152	1			T2	1		T13	2		T14	6
all_values[7]	auto[0]	auto[0]	auto[0]	173	1			T2	1		T13	1		T14	5
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T2	1		T13	1		T28	1
all_values[7]	auto[0]	auto[1]	auto[0]	141	1			T2	1		T14	3		T38	1
all_values[7]	auto[0]	auto[1]	auto[1]	87	1			T14	1		T32	4		T111	2
all_values[7]	auto[1]	auto[0]	auto[1]	204	1			T2	1		T13	2		T14	5
all_values[7]	auto[1]	auto[1]	auto[1]	169	1			T2	3		T13	3		T14	4
all_values[8]	auto[0]	auto[0]	auto[1]	252	1			T13	2		T14	7		T28	2
all_values[8]	auto[0]	auto[1]	auto[1]	247	1			T2	3		T13	2		T14	3
all_values[8]	auto[1]	auto[0]	auto[1]	197	1			T13	2		T14	2		T28	1
all_values[8]	auto[1]	auto[1]	auto[1]	162	1			T2	4		T13	1		T14	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal