Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.50


Total test records in report: 1316
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T1255 /workspace/coverage/cover_reg_top/1.uart_intr_test.857793871 Jul 05 04:20:55 PM PDT 24 Jul 05 04:20:56 PM PDT 24 34115578 ps
T1256 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3302457201 Jul 05 04:23:15 PM PDT 24 Jul 05 04:23:17 PM PDT 24 147907311 ps
T1257 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2891911073 Jul 05 04:23:31 PM PDT 24 Jul 05 04:23:32 PM PDT 24 33472872 ps
T1258 /workspace/coverage/cover_reg_top/44.uart_intr_test.2308912952 Jul 05 04:20:06 PM PDT 24 Jul 05 04:20:07 PM PDT 24 16337982 ps
T1259 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2840648756 Jul 05 04:22:10 PM PDT 24 Jul 05 04:22:11 PM PDT 24 184932470 ps
T114 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.704160650 Jul 05 04:21:58 PM PDT 24 Jul 05 04:21:59 PM PDT 24 161327982 ps
T1260 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4085996671 Jul 05 04:22:18 PM PDT 24 Jul 05 04:22:20 PM PDT 24 20347085 ps
T1261 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2937428486 Jul 05 04:22:46 PM PDT 24 Jul 05 04:22:47 PM PDT 24 20645603 ps
T1262 /workspace/coverage/cover_reg_top/2.uart_tl_errors.4175955896 Jul 05 04:22:33 PM PDT 24 Jul 05 04:22:36 PM PDT 24 52877235 ps
T1263 /workspace/coverage/cover_reg_top/36.uart_intr_test.3085923600 Jul 05 04:18:00 PM PDT 24 Jul 05 04:18:01 PM PDT 24 23733272 ps
T1264 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1730333007 Jul 05 04:20:21 PM PDT 24 Jul 05 04:20:23 PM PDT 24 29141954 ps
T1265 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1012013861 Jul 05 04:22:42 PM PDT 24 Jul 05 04:22:43 PM PDT 24 28272033 ps
T1266 /workspace/coverage/cover_reg_top/43.uart_intr_test.2447069355 Jul 05 04:22:22 PM PDT 24 Jul 05 04:22:24 PM PDT 24 22207789 ps
T1267 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3906023696 Jul 05 04:22:48 PM PDT 24 Jul 05 04:22:49 PM PDT 24 110941449 ps
T87 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1457227342 Jul 05 04:22:33 PM PDT 24 Jul 05 04:22:36 PM PDT 24 250965906 ps
T1268 /workspace/coverage/cover_reg_top/24.uart_intr_test.3361598763 Jul 05 04:17:56 PM PDT 24 Jul 05 04:17:57 PM PDT 24 52632060 ps
T1269 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.927998402 Jul 05 04:22:10 PM PDT 24 Jul 05 04:22:12 PM PDT 24 20830761 ps
T1270 /workspace/coverage/cover_reg_top/18.uart_tl_errors.337039461 Jul 05 04:23:30 PM PDT 24 Jul 05 04:23:32 PM PDT 24 58818821 ps
T1271 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3262705632 Jul 05 04:23:21 PM PDT 24 Jul 05 04:23:22 PM PDT 24 13656565 ps
T1272 /workspace/coverage/cover_reg_top/19.uart_intr_test.1977758276 Jul 05 04:19:21 PM PDT 24 Jul 05 04:19:22 PM PDT 24 23986705 ps
T1273 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3216915189 Jul 05 04:22:58 PM PDT 24 Jul 05 04:23:00 PM PDT 24 20150375 ps
T1274 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2151238088 Jul 05 04:21:49 PM PDT 24 Jul 05 04:21:50 PM PDT 24 12356257 ps
T1275 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1100746845 Jul 05 04:17:47 PM PDT 24 Jul 05 04:17:48 PM PDT 24 25878109 ps
T1276 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4130890430 Jul 05 04:17:49 PM PDT 24 Jul 05 04:17:51 PM PDT 24 44922989 ps
T1277 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1098385512 Jul 05 04:19:48 PM PDT 24 Jul 05 04:19:50 PM PDT 24 33385227 ps
T52 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3964368466 Jul 05 04:20:40 PM PDT 24 Jul 05 04:20:41 PM PDT 24 55329969 ps
T1278 /workspace/coverage/cover_reg_top/6.uart_intr_test.3988837369 Jul 05 04:21:09 PM PDT 24 Jul 05 04:21:10 PM PDT 24 35981661 ps
T1279 /workspace/coverage/cover_reg_top/31.uart_intr_test.3846107876 Jul 05 04:19:58 PM PDT 24 Jul 05 04:19:58 PM PDT 24 17814636 ps
T1280 /workspace/coverage/cover_reg_top/8.uart_csr_rw.4041637880 Jul 05 04:19:34 PM PDT 24 Jul 05 04:19:35 PM PDT 24 48610501 ps
T1281 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1362818248 Jul 05 04:17:45 PM PDT 24 Jul 05 04:17:46 PM PDT 24 58571896 ps
T1282 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.299539550 Jul 05 04:22:31 PM PDT 24 Jul 05 04:22:33 PM PDT 24 16423216 ps
T1283 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.718304694 Jul 05 04:22:26 PM PDT 24 Jul 05 04:22:27 PM PDT 24 30188067 ps
T1284 /workspace/coverage/cover_reg_top/7.uart_tl_errors.1284703319 Jul 05 04:22:44 PM PDT 24 Jul 05 04:22:47 PM PDT 24 41579367 ps
T1285 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.549079348 Jul 05 04:20:54 PM PDT 24 Jul 05 04:20:55 PM PDT 24 31134488 ps
T1286 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3188317936 Jul 05 04:20:19 PM PDT 24 Jul 05 04:20:23 PM PDT 24 177663772 ps
T1287 /workspace/coverage/cover_reg_top/14.uart_intr_test.3390768448 Jul 05 04:23:07 PM PDT 24 Jul 05 04:23:08 PM PDT 24 18541247 ps
T1288 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3127905174 Jul 05 04:21:21 PM PDT 24 Jul 05 04:21:22 PM PDT 24 21804256 ps
T1289 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3776856021 Jul 05 04:22:34 PM PDT 24 Jul 05 04:22:37 PM PDT 24 287898866 ps
T1290 /workspace/coverage/cover_reg_top/25.uart_intr_test.2530666918 Jul 05 04:22:36 PM PDT 24 Jul 05 04:22:38 PM PDT 24 196635309 ps
T1291 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2013907412 Jul 05 04:22:18 PM PDT 24 Jul 05 04:22:20 PM PDT 24 95586590 ps
T1292 /workspace/coverage/cover_reg_top/22.uart_intr_test.317651967 Jul 05 04:20:21 PM PDT 24 Jul 05 04:20:23 PM PDT 24 54467456 ps
T1293 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.914074238 Jul 05 04:23:23 PM PDT 24 Jul 05 04:23:24 PM PDT 24 30216475 ps
T1294 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3624382393 Jul 05 04:18:47 PM PDT 24 Jul 05 04:18:48 PM PDT 24 106355800 ps
T1295 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3973508873 Jul 05 04:19:34 PM PDT 24 Jul 05 04:19:35 PM PDT 24 84265468 ps
T1296 /workspace/coverage/cover_reg_top/32.uart_intr_test.2810287941 Jul 05 04:23:02 PM PDT 24 Jul 05 04:23:04 PM PDT 24 17937239 ps
T53 /workspace/coverage/cover_reg_top/13.uart_csr_rw.559739388 Jul 05 04:21:36 PM PDT 24 Jul 05 04:21:37 PM PDT 24 16006616 ps
T1297 /workspace/coverage/cover_reg_top/49.uart_intr_test.908699189 Jul 05 04:18:29 PM PDT 24 Jul 05 04:18:30 PM PDT 24 14520123 ps
T1298 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1963525760 Jul 05 04:19:22 PM PDT 24 Jul 05 04:19:23 PM PDT 24 46162751 ps
T1299 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1058533637 Jul 05 04:21:51 PM PDT 24 Jul 05 04:21:52 PM PDT 24 275226705 ps
T1300 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1928168621 Jul 05 04:22:10 PM PDT 24 Jul 05 04:22:11 PM PDT 24 13033783 ps
T1301 /workspace/coverage/cover_reg_top/5.uart_tl_errors.2820810243 Jul 05 04:22:49 PM PDT 24 Jul 05 04:22:53 PM PDT 24 47124532 ps
T1302 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2861442228 Jul 05 04:22:42 PM PDT 24 Jul 05 04:22:43 PM PDT 24 82152823 ps
T1303 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.696122750 Jul 05 04:18:27 PM PDT 24 Jul 05 04:18:29 PM PDT 24 26406909 ps
T1304 /workspace/coverage/cover_reg_top/8.uart_intr_test.2399870706 Jul 05 04:22:11 PM PDT 24 Jul 05 04:22:12 PM PDT 24 14043055 ps
T1305 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1934472704 Jul 05 04:20:41 PM PDT 24 Jul 05 04:20:43 PM PDT 24 35337564 ps
T1306 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3915103258 Jul 05 04:21:57 PM PDT 24 Jul 05 04:21:58 PM PDT 24 22434863 ps
T1307 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.131669925 Jul 05 04:21:55 PM PDT 24 Jul 05 04:21:56 PM PDT 24 136130175 ps
T1308 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2706368692 Jul 05 04:22:54 PM PDT 24 Jul 05 04:22:57 PM PDT 24 78951949 ps
T1309 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2323759670 Jul 05 04:22:59 PM PDT 24 Jul 05 04:23:01 PM PDT 24 44487855 ps
T1310 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.687919115 Jul 05 04:22:48 PM PDT 24 Jul 05 04:22:50 PM PDT 24 75587509 ps
T1311 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3858729791 Jul 05 04:22:48 PM PDT 24 Jul 05 04:22:50 PM PDT 24 337873753 ps
T1312 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2505501398 Jul 05 04:23:19 PM PDT 24 Jul 05 04:23:20 PM PDT 24 50373808 ps
T1313 /workspace/coverage/cover_reg_top/11.uart_intr_test.4243415089 Jul 05 04:21:50 PM PDT 24 Jul 05 04:21:51 PM PDT 24 34670582 ps
T1314 /workspace/coverage/cover_reg_top/27.uart_intr_test.271668533 Jul 05 04:17:51 PM PDT 24 Jul 05 04:17:52 PM PDT 24 14381834 ps
T1315 /workspace/coverage/cover_reg_top/5.uart_intr_test.540256429 Jul 05 04:22:33 PM PDT 24 Jul 05 04:22:35 PM PDT 24 30130401 ps
T1316 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1450617304 Jul 05 04:18:17 PM PDT 24 Jul 05 04:18:20 PM PDT 24 265475133 ps

Test location /workspace/coverage/default/3.uart_stress_all.549008570
Short name T8
Test name
Test status
Simulation time 353404967683 ps
CPU time 227.56 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:40:53 PM PDT 24
Peak memory 199980 kb
Host smart-2503fc21-8fad-4455-9f0e-3af33b69c8b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549008570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.549008570
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1526205693
Short name T19
Test name
Test status
Simulation time 360994417557 ps
CPU time 965.6 seconds
Started Jul 05 05:39:59 PM PDT 24
Finished Jul 05 05:56:05 PM PDT 24
Peak memory 224916 kb
Host smart-ea5ac5dd-2548-4713-88f9-95f4c18e3066
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526205693 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1526205693
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3318952655
Short name T33
Test name
Test status
Simulation time 113533912603 ps
CPU time 810.79 seconds
Started Jul 05 05:38:58 PM PDT 24
Finished Jul 05 05:52:29 PM PDT 24
Peak memory 224864 kb
Host smart-4bcdb1de-f77f-4b33-86f4-fe09cdfe68d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318952655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3318952655
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1941176247
Short name T28
Test name
Test status
Simulation time 211596234989 ps
CPU time 1424.76 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 06:01:19 PM PDT 24
Peak memory 227276 kb
Host smart-c68bb99b-6339-49e4-b311-d3de867eb716
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941176247 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1941176247
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all.4007103033
Short name T11
Test name
Test status
Simulation time 544969093892 ps
CPU time 277.94 seconds
Started Jul 05 05:39:35 PM PDT 24
Finished Jul 05 05:44:14 PM PDT 24
Peak memory 208280 kb
Host smart-87d96a29-efe1-408a-98ce-1dc7ed96f5b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007103033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.4007103033
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2574777021
Short name T38
Test name
Test status
Simulation time 211626337068 ps
CPU time 508.99 seconds
Started Jul 05 05:39:43 PM PDT 24
Finished Jul 05 05:48:13 PM PDT 24
Peak memory 224356 kb
Host smart-e96bef7c-5b9e-43e0-bc89-f833f5f91905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574777021 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2574777021
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.3092369237
Short name T17
Test name
Test status
Simulation time 120044279269 ps
CPU time 446.63 seconds
Started Jul 05 05:37:07 PM PDT 24
Finished Jul 05 05:44:35 PM PDT 24
Peak memory 199996 kb
Host smart-699a325c-5ea3-4e6f-b851-e719c8407138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092369237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3092369237
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1690817716
Short name T25
Test name
Test status
Simulation time 34328722 ps
CPU time 0.78 seconds
Started Jul 05 05:37:17 PM PDT 24
Finished Jul 05 05:37:19 PM PDT 24
Peak memory 218468 kb
Host smart-0b137756-f19b-41ad-9199-a036681ccf22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690817716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1690817716
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1841530497
Short name T111
Test name
Test status
Simulation time 529535070101 ps
CPU time 1452.44 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 06:04:19 PM PDT 24
Peak memory 216056 kb
Host smart-71ac9504-6639-47db-a6a3-0b16d8b7d8b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841530497 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1841530497
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all.2826740120
Short name T21
Test name
Test status
Simulation time 128316058569 ps
CPU time 107.89 seconds
Started Jul 05 05:38:52 PM PDT 24
Finished Jul 05 05:40:40 PM PDT 24
Peak memory 199908 kb
Host smart-e5f3d585-b61b-4af5-a0a4-f99aef14cb77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826740120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2826740120
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1548841200
Short name T5
Test name
Test status
Simulation time 116108558836 ps
CPU time 162.99 seconds
Started Jul 05 05:37:05 PM PDT 24
Finished Jul 05 05:39:49 PM PDT 24
Peak memory 199984 kb
Host smart-69955f37-f805-40ad-a063-1e6522854f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548841200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1548841200
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3575365473
Short name T122
Test name
Test status
Simulation time 190312664613 ps
CPU time 584.57 seconds
Started Jul 05 05:38:17 PM PDT 24
Finished Jul 05 05:48:03 PM PDT 24
Peak memory 214240 kb
Host smart-c7544f2a-c803-48bc-a2f7-9b9e905c266c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575365473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3575365473
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3630065422
Short name T83
Test name
Test status
Simulation time 1012283315 ps
CPU time 1.36 seconds
Started Jul 05 04:17:49 PM PDT 24
Finished Jul 05 04:17:51 PM PDT 24
Peak memory 199956 kb
Host smart-526c2ac2-4df9-450a-a9bb-f36e5d8c0035
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630065422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3630065422
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1938917690
Short name T12
Test name
Test status
Simulation time 159045343366 ps
CPU time 70.01 seconds
Started Jul 05 05:38:58 PM PDT 24
Finished Jul 05 05:40:09 PM PDT 24
Peak memory 199956 kb
Host smart-9ec0f9da-c378-4963-8e01-eccbe0977413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938917690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1938917690
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.331934008
Short name T129
Test name
Test status
Simulation time 68558199976 ps
CPU time 165.81 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:42:59 PM PDT 24
Peak memory 199940 kb
Host smart-2106ee41-c5c6-4ea7-b42a-28eade8475af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331934008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.331934008
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.2975214802
Short name T435
Test name
Test status
Simulation time 244581719557 ps
CPU time 666.88 seconds
Started Jul 05 05:37:56 PM PDT 24
Finished Jul 05 05:49:05 PM PDT 24
Peak memory 199976 kb
Host smart-c3879392-bcf9-4f24-9321-95c695b6bb8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975214802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2975214802
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all.870365537
Short name T105
Test name
Test status
Simulation time 42496217592 ps
CPU time 681.48 seconds
Started Jul 05 05:38:58 PM PDT 24
Finished Jul 05 05:50:20 PM PDT 24
Peak memory 199964 kb
Host smart-271ed0b5-01b5-41fa-8957-cc1471a48d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870365537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.870365537
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_alert_test.1298576958
Short name T331
Test name
Test status
Simulation time 38364184 ps
CPU time 0.58 seconds
Started Jul 05 05:37:30 PM PDT 24
Finished Jul 05 05:37:32 PM PDT 24
Peak memory 195328 kb
Host smart-2d592700-9c44-4318-a166-e1d848e93360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298576958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1298576958
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.79530836
Short name T47
Test name
Test status
Simulation time 54187580 ps
CPU time 0.63 seconds
Started Jul 05 04:21:41 PM PDT 24
Finished Jul 05 04:21:43 PM PDT 24
Peak memory 196048 kb
Host smart-d21ad56d-5948-46f3-8bff-0f7155b1ca87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79530836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.79530836
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/default/23.uart_stress_all.2645577456
Short name T266
Test name
Test status
Simulation time 92086287875 ps
CPU time 143.17 seconds
Started Jul 05 05:37:52 PM PDT 24
Finished Jul 05 05:40:16 PM PDT 24
Peak memory 199940 kb
Host smart-6fd21e47-d686-4369-b8ea-12d9e0d03ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645577456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2645577456
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1803629771
Short name T241
Test name
Test status
Simulation time 189659891143 ps
CPU time 111.08 seconds
Started Jul 05 05:38:25 PM PDT 24
Finished Jul 05 05:40:17 PM PDT 24
Peak memory 199992 kb
Host smart-23e813d2-1e25-4bce-af75-be9e7b22238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803629771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1803629771
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.978179205
Short name T29
Test name
Test status
Simulation time 61567461430 ps
CPU time 520.59 seconds
Started Jul 05 05:39:56 PM PDT 24
Finished Jul 05 05:48:37 PM PDT 24
Peak memory 216464 kb
Host smart-4cc4d0cd-fbf3-414f-8707-e4a563d80ab0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978179205 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.978179205
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1773445047
Short name T275
Test name
Test status
Simulation time 230546057989 ps
CPU time 243.24 seconds
Started Jul 05 05:39:23 PM PDT 24
Finished Jul 05 05:43:27 PM PDT 24
Peak memory 199880 kb
Host smart-96559292-bdc0-4d45-8788-e1338426c9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773445047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1773445047
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1202792622
Short name T157
Test name
Test status
Simulation time 94565631845 ps
CPU time 221.54 seconds
Started Jul 05 05:40:16 PM PDT 24
Finished Jul 05 05:43:59 PM PDT 24
Peak memory 199848 kb
Host smart-e1bc0089-6536-482d-b8d5-abcd6cf5e5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202792622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1202792622
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3639098205
Short name T100
Test name
Test status
Simulation time 257915426773 ps
CPU time 511.58 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:46:09 PM PDT 24
Peak memory 216508 kb
Host smart-1f720d84-3a2c-43b3-832f-fd4c5629129d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639098205 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3639098205
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1128078950
Short name T58
Test name
Test status
Simulation time 53288084926 ps
CPU time 25.39 seconds
Started Jul 05 05:40:21 PM PDT 24
Finished Jul 05 05:40:47 PM PDT 24
Peak memory 199832 kb
Host smart-6dc99d83-66e8-4961-baba-d915ceea9802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128078950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1128078950
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2565757539
Short name T13
Test name
Test status
Simulation time 125994605689 ps
CPU time 667.21 seconds
Started Jul 05 05:39:43 PM PDT 24
Finished Jul 05 05:50:51 PM PDT 24
Peak memory 224768 kb
Host smart-b525323c-2e7c-4e4e-8073-9a7d4715b63a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565757539 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2565757539
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.2371110319
Short name T558
Test name
Test status
Simulation time 509270028834 ps
CPU time 1045.49 seconds
Started Jul 05 05:37:29 PM PDT 24
Finished Jul 05 05:54:56 PM PDT 24
Peak memory 199844 kb
Host smart-ea9d911c-8680-4e0e-a83c-e9ae9b1e9016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371110319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2371110319
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.4242443384
Short name T151
Test name
Test status
Simulation time 272546863040 ps
CPU time 172.74 seconds
Started Jul 05 05:40:20 PM PDT 24
Finished Jul 05 05:43:14 PM PDT 24
Peak memory 199956 kb
Host smart-fecc98c4-d79d-43bf-a64e-0e936355dde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242443384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.4242443384
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2038706403
Short name T117
Test name
Test status
Simulation time 53585658604 ps
CPU time 165.87 seconds
Started Jul 05 05:40:19 PM PDT 24
Finished Jul 05 05:43:06 PM PDT 24
Peak memory 199528 kb
Host smart-e4575fa8-6bb8-4052-a35e-1cefb77b932f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038706403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2038706403
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2436965309
Short name T178
Test name
Test status
Simulation time 162266870437 ps
CPU time 76.3 seconds
Started Jul 05 05:40:19 PM PDT 24
Finished Jul 05 05:41:36 PM PDT 24
Peak memory 199908 kb
Host smart-1361fc82-a96e-4bb2-9a39-2b20e5acdcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436965309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2436965309
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2624971251
Short name T144
Test name
Test status
Simulation time 71834278628 ps
CPU time 37.84 seconds
Started Jul 05 05:40:51 PM PDT 24
Finished Jul 05 05:41:29 PM PDT 24
Peak memory 199988 kb
Host smart-3f70d39d-045e-4d24-bbf0-97efe8a36397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624971251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2624971251
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3611678175
Short name T85
Test name
Test status
Simulation time 95951768 ps
CPU time 0.88 seconds
Started Jul 05 04:19:20 PM PDT 24
Finished Jul 05 04:19:21 PM PDT 24
Peak memory 199388 kb
Host smart-e2a47f15-18b4-49dc-91d7-542c2820466b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611678175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3611678175
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2874283626
Short name T158
Test name
Test status
Simulation time 42612655379 ps
CPU time 66.92 seconds
Started Jul 05 05:40:21 PM PDT 24
Finished Jul 05 05:41:28 PM PDT 24
Peak memory 199920 kb
Host smart-bc00fd0a-5db8-4250-af86-456da59e6d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874283626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2874283626
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2192558099
Short name T148
Test name
Test status
Simulation time 92658318625 ps
CPU time 434.49 seconds
Started Jul 05 05:37:05 PM PDT 24
Finished Jul 05 05:44:21 PM PDT 24
Peak memory 216540 kb
Host smart-0e75ed88-ca07-43bf-ad51-33b37e9cc998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192558099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2192558099
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3019517046
Short name T152
Test name
Test status
Simulation time 199663782755 ps
CPU time 292.22 seconds
Started Jul 05 05:40:06 PM PDT 24
Finished Jul 05 05:44:59 PM PDT 24
Peak memory 199892 kb
Host smart-61d2b1ad-7c41-4b1f-8ed2-c9d9a15d4e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019517046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3019517046
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1021290867
Short name T167
Test name
Test status
Simulation time 28180781907 ps
CPU time 10.39 seconds
Started Jul 05 05:40:29 PM PDT 24
Finished Jul 05 05:40:40 PM PDT 24
Peak memory 199528 kb
Host smart-c0eeacbb-08f2-4c57-8c88-158084241bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021290867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1021290867
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1562471430
Short name T90
Test name
Test status
Simulation time 92097701548 ps
CPU time 129.49 seconds
Started Jul 05 05:38:54 PM PDT 24
Finished Jul 05 05:41:04 PM PDT 24
Peak memory 199060 kb
Host smart-30340ce4-e0d3-4c8d-9a32-f4ad270baee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562471430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1562471430
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3676592028
Short name T189
Test name
Test status
Simulation time 122385381153 ps
CPU time 91.5 seconds
Started Jul 05 05:38:58 PM PDT 24
Finished Jul 05 05:40:30 PM PDT 24
Peak memory 199944 kb
Host smart-74632f81-4c38-42b2-920b-a2abb96e2327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676592028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3676592028
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1391835492
Short name T40
Test name
Test status
Simulation time 134791637748 ps
CPU time 1162.53 seconds
Started Jul 05 05:39:51 PM PDT 24
Finished Jul 05 05:59:14 PM PDT 24
Peak memory 224848 kb
Host smart-9c73a3bb-c0bc-4629-beb7-aa67e8f4b5f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391835492 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1391835492
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4194587623
Short name T235
Test name
Test status
Simulation time 30396783176 ps
CPU time 14.14 seconds
Started Jul 05 05:40:11 PM PDT 24
Finished Jul 05 05:40:26 PM PDT 24
Peak memory 199972 kb
Host smart-80c491fc-7c40-489e-aece-226237d577e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194587623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4194587623
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.281980927
Short name T675
Test name
Test status
Simulation time 24497168255 ps
CPU time 37.74 seconds
Started Jul 05 05:40:19 PM PDT 24
Finished Jul 05 05:40:57 PM PDT 24
Peak memory 199872 kb
Host smart-3427a2ad-19b9-4989-9d51-74119e7bf70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281980927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.281980927
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1057820065
Short name T498
Test name
Test status
Simulation time 216038958208 ps
CPU time 300.27 seconds
Started Jul 05 05:37:49 PM PDT 24
Finished Jul 05 05:42:51 PM PDT 24
Peak memory 199920 kb
Host smart-f85dc5c9-3806-44c7-ad44-6e265c64b07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057820065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1057820065
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1207612977
Short name T164
Test name
Test status
Simulation time 115187471157 ps
CPU time 123.67 seconds
Started Jul 05 05:40:51 PM PDT 24
Finished Jul 05 05:42:55 PM PDT 24
Peak memory 199900 kb
Host smart-6884c29a-40c6-4b7d-a74e-5a081ca2cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207612977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1207612977
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1711454046
Short name T203
Test name
Test status
Simulation time 7913408938 ps
CPU time 15.67 seconds
Started Jul 05 05:41:14 PM PDT 24
Finished Jul 05 05:41:30 PM PDT 24
Peak memory 199884 kb
Host smart-072ae480-79e9-460f-bb79-809586038815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711454046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1711454046
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all.3636192839
Short name T18
Test name
Test status
Simulation time 99438908844 ps
CPU time 74.12 seconds
Started Jul 05 05:38:41 PM PDT 24
Finished Jul 05 05:39:55 PM PDT 24
Peak memory 200016 kb
Host smart-abf8aec7-efdb-4385-a440-2b363f9b6485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636192839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3636192839
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2990438412
Short name T273
Test name
Test status
Simulation time 83453301572 ps
CPU time 69.26 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:40:44 PM PDT 24
Peak memory 199988 kb
Host smart-0e05ca8e-7098-43a9-baf9-1b25b3e7db58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990438412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2990438412
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.825981954
Short name T207
Test name
Test status
Simulation time 16571718563 ps
CPU time 34.85 seconds
Started Jul 05 05:37:28 PM PDT 24
Finished Jul 05 05:38:04 PM PDT 24
Peak memory 199884 kb
Host smart-736fe0c7-d3a2-4371-89bf-61227616db0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825981954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.825981954
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2166714185
Short name T172
Test name
Test status
Simulation time 111907516488 ps
CPU time 42.46 seconds
Started Jul 05 05:40:35 PM PDT 24
Finished Jul 05 05:41:18 PM PDT 24
Peak memory 199816 kb
Host smart-7b798e6c-0163-48a3-ae57-a920ebacafb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166714185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2166714185
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2869125804
Short name T210
Test name
Test status
Simulation time 309014197152 ps
CPU time 512.26 seconds
Started Jul 05 05:40:50 PM PDT 24
Finished Jul 05 05:49:23 PM PDT 24
Peak memory 200000 kb
Host smart-9d198648-26a5-4ab2-98b3-c9e1017c7445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869125804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2869125804
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1133876811
Short name T213
Test name
Test status
Simulation time 115958199966 ps
CPU time 45.51 seconds
Started Jul 05 05:41:15 PM PDT 24
Finished Jul 05 05:42:01 PM PDT 24
Peak memory 199872 kb
Host smart-b776f0ef-2f3c-4cae-a884-917064d4d3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133876811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1133876811
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.3064144775
Short name T193
Test name
Test status
Simulation time 289973867510 ps
CPU time 404.11 seconds
Started Jul 05 05:38:23 PM PDT 24
Finished Jul 05 05:45:08 PM PDT 24
Peak memory 199880 kb
Host smart-55dea39d-fad8-4c03-885c-a9648a0246af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064144775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3064144775
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2065414773
Short name T138
Test name
Test status
Simulation time 52332999641 ps
CPU time 36.56 seconds
Started Jul 05 05:39:49 PM PDT 24
Finished Jul 05 05:40:27 PM PDT 24
Peak memory 199980 kb
Host smart-8fc2a183-7dbe-4620-8cc3-edafe589b43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065414773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2065414773
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1248332320
Short name T282
Test name
Test status
Simulation time 223838547763 ps
CPU time 43.93 seconds
Started Jul 05 05:36:55 PM PDT 24
Finished Jul 05 05:37:39 PM PDT 24
Peak memory 199996 kb
Host smart-81d27442-7d0a-4d5a-a302-ed44fe74cebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248332320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1248332320
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.456711544
Short name T1142
Test name
Test status
Simulation time 86130670627 ps
CPU time 126.78 seconds
Started Jul 05 05:40:12 PM PDT 24
Finished Jul 05 05:42:20 PM PDT 24
Peak memory 199940 kb
Host smart-cd07a960-5879-4730-91e7-d8bb55992014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456711544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.456711544
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1713837986
Short name T234
Test name
Test status
Simulation time 26692116530 ps
CPU time 23.35 seconds
Started Jul 05 05:40:19 PM PDT 24
Finished Jul 05 05:40:43 PM PDT 24
Peak memory 199720 kb
Host smart-21c78c4a-be93-4a66-85c5-a012309c1adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713837986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1713837986
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.2588710654
Short name T269
Test name
Test status
Simulation time 97627761816 ps
CPU time 376.47 seconds
Started Jul 05 05:37:34 PM PDT 24
Finished Jul 05 05:43:51 PM PDT 24
Peak memory 199956 kb
Host smart-460a779b-04ac-4d27-84cb-6ac08ae5ce73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588710654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2588710654
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3057850252
Short name T141
Test name
Test status
Simulation time 99541875376 ps
CPU time 26.23 seconds
Started Jul 05 05:40:23 PM PDT 24
Finished Jul 05 05:40:49 PM PDT 24
Peak memory 199952 kb
Host smart-f1202de3-3561-427a-a5c9-c20b7de9fc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057850252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3057850252
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.556267940
Short name T225
Test name
Test status
Simulation time 165735006127 ps
CPU time 21.42 seconds
Started Jul 05 05:40:29 PM PDT 24
Finished Jul 05 05:40:52 PM PDT 24
Peak memory 199868 kb
Host smart-9513888b-73d9-430b-a67f-903e21a7d567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556267940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.556267940
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2812718599
Short name T228
Test name
Test status
Simulation time 151629840543 ps
CPU time 58.02 seconds
Started Jul 05 05:40:37 PM PDT 24
Finished Jul 05 05:41:35 PM PDT 24
Peak memory 199912 kb
Host smart-f2325866-c81c-4d08-b189-a1f18630f988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812718599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2812718599
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3808988900
Short name T212
Test name
Test status
Simulation time 22185826490 ps
CPU time 32.34 seconds
Started Jul 05 05:40:38 PM PDT 24
Finished Jul 05 05:41:11 PM PDT 24
Peak memory 199120 kb
Host smart-6f3b7b82-dbe8-4980-ba7c-542353e0312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808988900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3808988900
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4213007577
Short name T209
Test name
Test status
Simulation time 25655474394 ps
CPU time 11.15 seconds
Started Jul 05 05:40:43 PM PDT 24
Finished Jul 05 05:40:54 PM PDT 24
Peak memory 199968 kb
Host smart-97ece4ea-f67f-4fe2-8cd7-8de7920f432a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213007577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4213007577
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2515247591
Short name T169
Test name
Test status
Simulation time 113820985752 ps
CPU time 42.9 seconds
Started Jul 05 05:40:44 PM PDT 24
Finished Jul 05 05:41:28 PM PDT 24
Peak memory 199960 kb
Host smart-c28fa6b4-8ab3-4539-9448-115518100e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515247591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2515247591
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1769361462
Short name T230
Test name
Test status
Simulation time 81815617671 ps
CPU time 32.66 seconds
Started Jul 05 05:41:04 PM PDT 24
Finished Jul 05 05:41:37 PM PDT 24
Peak memory 199996 kb
Host smart-374790a0-3f70-4363-a236-5e657e8ae138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769361462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1769361462
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1987198280
Short name T237
Test name
Test status
Simulation time 9417632804 ps
CPU time 22.2 seconds
Started Jul 05 05:38:46 PM PDT 24
Finished Jul 05 05:39:09 PM PDT 24
Peak memory 199952 kb
Host smart-22d5af24-f94b-4975-91fc-ef63667ff32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987198280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1987198280
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2618779038
Short name T229
Test name
Test status
Simulation time 86018100400 ps
CPU time 69.16 seconds
Started Jul 05 05:37:05 PM PDT 24
Finished Jul 05 05:38:15 PM PDT 24
Peak memory 199940 kb
Host smart-04d8d5d5-caf6-499c-8e2f-267a5ce4fb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618779038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2618779038
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3672777918
Short name T149
Test name
Test status
Simulation time 146298365831 ps
CPU time 65.75 seconds
Started Jul 05 05:39:59 PM PDT 24
Finished Jul 05 05:41:05 PM PDT 24
Peak memory 199860 kb
Host smart-f8ab4216-5d01-4782-9bbd-3dc81cd4fd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672777918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3672777918
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3800248870
Short name T233
Test name
Test status
Simulation time 152458796559 ps
CPU time 56.37 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:41:02 PM PDT 24
Peak memory 199956 kb
Host smart-ca89a6b3-546e-4cde-a51f-b1f86f80fc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800248870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3800248870
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2357241875
Short name T50
Test name
Test status
Simulation time 40469330 ps
CPU time 0.66 seconds
Started Jul 05 04:22:28 PM PDT 24
Finished Jul 05 04:22:30 PM PDT 24
Peak memory 194752 kb
Host smart-88f4d49d-6a69-430f-bfbb-4c8d45b9b728
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357241875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2357241875
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.81159394
Short name T1189
Test name
Test status
Simulation time 227335296 ps
CPU time 2.29 seconds
Started Jul 05 04:22:37 PM PDT 24
Finished Jul 05 04:22:40 PM PDT 24
Peak memory 198092 kb
Host smart-890c526c-3721-44e5-b4e4-07422a7c644b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81159394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.81159394
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.69493781
Short name T1216
Test name
Test status
Simulation time 12892916 ps
CPU time 0.59 seconds
Started Jul 05 04:22:32 PM PDT 24
Finished Jul 05 04:22:34 PM PDT 24
Peak memory 196012 kb
Host smart-16c2364e-8277-4dc8-b433-c55b502bf77c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69493781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.69493781
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.963738758
Short name T1199
Test name
Test status
Simulation time 39717270 ps
CPU time 0.97 seconds
Started Jul 05 04:22:41 PM PDT 24
Finished Jul 05 04:22:42 PM PDT 24
Peak memory 199264 kb
Host smart-6ed481bf-ee65-4c5c-abcd-102ba69354ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963738758 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.963738758
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1474354411
Short name T1198
Test name
Test status
Simulation time 18714630 ps
CPU time 0.53 seconds
Started Jul 05 04:22:41 PM PDT 24
Finished Jul 05 04:22:42 PM PDT 24
Peak memory 195968 kb
Host smart-b62dc06a-ea14-415a-9810-8b10d3b7b043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474354411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1474354411
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3895806411
Short name T1201
Test name
Test status
Simulation time 15759602 ps
CPU time 0.58 seconds
Started Jul 05 04:22:28 PM PDT 24
Finished Jul 05 04:22:30 PM PDT 24
Peak memory 193708 kb
Host smart-36c4610b-4dfe-4e23-b97a-b8b4e0cf2767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895806411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3895806411
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3637972626
Short name T70
Test name
Test status
Simulation time 58095246 ps
CPU time 0.64 seconds
Started Jul 05 04:23:31 PM PDT 24
Finished Jul 05 04:23:32 PM PDT 24
Peak memory 196092 kb
Host smart-7777f7e8-d38b-4676-9a2f-9c7517e983d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637972626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3637972626
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.849152261
Short name T1241
Test name
Test status
Simulation time 90026847 ps
CPU time 1.21 seconds
Started Jul 05 04:21:08 PM PDT 24
Finished Jul 05 04:21:10 PM PDT 24
Peak memory 200680 kb
Host smart-aa831770-8efe-471f-8285-f85c9e73b67b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849152261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.849152261
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3188317936
Short name T1286
Test name
Test status
Simulation time 177663772 ps
CPU time 1 seconds
Started Jul 05 04:20:19 PM PDT 24
Finished Jul 05 04:20:23 PM PDT 24
Peak memory 199656 kb
Host smart-45b7a033-2f3c-40cd-906e-0e0cf02515db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188317936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3188317936
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1100746845
Short name T1275
Test name
Test status
Simulation time 25878109 ps
CPU time 0.78 seconds
Started Jul 05 04:17:47 PM PDT 24
Finished Jul 05 04:17:48 PM PDT 24
Peak memory 196928 kb
Host smart-b3420fe2-7481-4f06-a631-8d98a2eb96b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100746845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1100746845
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.4194842476
Short name T1251
Test name
Test status
Simulation time 908526361 ps
CPU time 2.68 seconds
Started Jul 05 04:20:55 PM PDT 24
Finished Jul 05 04:20:58 PM PDT 24
Peak memory 198084 kb
Host smart-7d9b17fc-8484-4851-9d52-be79e828afe3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194842476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.4194842476
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1012013861
Short name T1265
Test name
Test status
Simulation time 28272033 ps
CPU time 0.56 seconds
Started Jul 05 04:22:42 PM PDT 24
Finished Jul 05 04:22:43 PM PDT 24
Peak memory 195992 kb
Host smart-ce03b189-7136-4daf-961d-3dea60f4a887
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012013861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1012013861
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.599767884
Short name T1197
Test name
Test status
Simulation time 20459581 ps
CPU time 0.88 seconds
Started Jul 05 04:22:49 PM PDT 24
Finished Jul 05 04:22:51 PM PDT 24
Peak memory 200420 kb
Host smart-2a361def-68eb-45b5-9c3f-211cd07526f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599767884 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.599767884
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3262705632
Short name T1271
Test name
Test status
Simulation time 13656565 ps
CPU time 0.58 seconds
Started Jul 05 04:23:21 PM PDT 24
Finished Jul 05 04:23:22 PM PDT 24
Peak memory 195976 kb
Host smart-6983b9ee-cb4b-4a29-9fc5-bb7327783fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262705632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3262705632
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.857793871
Short name T1255
Test name
Test status
Simulation time 34115578 ps
CPU time 0.66 seconds
Started Jul 05 04:20:55 PM PDT 24
Finished Jul 05 04:20:56 PM PDT 24
Peak memory 194852 kb
Host smart-8fdb90c2-f39c-49c4-a254-0bf8c10ea23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857793871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.857793871
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2861442228
Short name T1302
Test name
Test status
Simulation time 82152823 ps
CPU time 0.7 seconds
Started Jul 05 04:22:42 PM PDT 24
Finished Jul 05 04:22:43 PM PDT 24
Peak memory 198200 kb
Host smart-1146caed-6f51-46c9-80b5-5ca65ab69cd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861442228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2861442228
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2403973839
Short name T1247
Test name
Test status
Simulation time 56280035 ps
CPU time 1.33 seconds
Started Jul 05 04:22:36 PM PDT 24
Finished Jul 05 04:22:39 PM PDT 24
Peak memory 198832 kb
Host smart-dcb377bf-fb27-44c4-bc33-396059a605d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403973839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2403973839
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3903701490
Short name T112
Test name
Test status
Simulation time 75290813 ps
CPU time 0.89 seconds
Started Jul 05 04:23:21 PM PDT 24
Finished Jul 05 04:23:22 PM PDT 24
Peak memory 199500 kb
Host smart-a11fd34e-1e60-488c-b7db-8162dd58d638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903701490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3903701490
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3412304593
Short name T1249
Test name
Test status
Simulation time 68492611 ps
CPU time 0.92 seconds
Started Jul 05 04:22:12 PM PDT 24
Finished Jul 05 04:22:13 PM PDT 24
Peak memory 200444 kb
Host smart-2ad77d87-66c1-4678-8732-60aa57138312
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412304593 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3412304593
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.4287739241
Short name T67
Test name
Test status
Simulation time 23698662 ps
CPU time 0.56 seconds
Started Jul 05 04:22:13 PM PDT 24
Finished Jul 05 04:22:14 PM PDT 24
Peak memory 196032 kb
Host smart-6c5defc4-fe2b-4058-b045-bbe73d410510
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287739241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4287739241
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3377138203
Short name T1245
Test name
Test status
Simulation time 15463085 ps
CPU time 0.57 seconds
Started Jul 05 04:22:34 PM PDT 24
Finished Jul 05 04:22:36 PM PDT 24
Peak memory 194952 kb
Host smart-7fb66200-41b4-47f5-b05d-d38b69dfd23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377138203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3377138203
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1744714989
Short name T75
Test name
Test status
Simulation time 74541560 ps
CPU time 0.72 seconds
Started Jul 05 04:22:33 PM PDT 24
Finished Jul 05 04:22:35 PM PDT 24
Peak memory 196668 kb
Host smart-e5ae8242-ad84-4ddd-8508-accccd49c9ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744714989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1744714989
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.384923747
Short name T1212
Test name
Test status
Simulation time 46389281 ps
CPU time 1.21 seconds
Started Jul 05 04:22:19 PM PDT 24
Finished Jul 05 04:22:21 PM PDT 24
Peak memory 200404 kb
Host smart-cd411d34-6547-4650-98ee-307386ac9806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384923747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.384923747
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1963525760
Short name T1298
Test name
Test status
Simulation time 46162751 ps
CPU time 1.02 seconds
Started Jul 05 04:19:22 PM PDT 24
Finished Jul 05 04:19:23 PM PDT 24
Peak memory 199440 kb
Host smart-6d8e7e39-f572-4044-81dd-71113a1833ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963525760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1963525760
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2706368692
Short name T1308
Test name
Test status
Simulation time 78951949 ps
CPU time 1.06 seconds
Started Jul 05 04:22:54 PM PDT 24
Finished Jul 05 04:22:57 PM PDT 24
Peak memory 200360 kb
Host smart-daccf82e-cf38-4390-9ae5-6f015a02cc14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706368692 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2706368692
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4243415089
Short name T1313
Test name
Test status
Simulation time 34670582 ps
CPU time 0.57 seconds
Started Jul 05 04:21:50 PM PDT 24
Finished Jul 05 04:21:51 PM PDT 24
Peak memory 195092 kb
Host smart-cf97309d-cf58-4fac-b4e2-e28429bd609e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243415089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4243415089
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3216915189
Short name T1273
Test name
Test status
Simulation time 20150375 ps
CPU time 0.7 seconds
Started Jul 05 04:22:58 PM PDT 24
Finished Jul 05 04:23:00 PM PDT 24
Peak memory 195228 kb
Host smart-236c1db6-06c5-4a4d-a333-c553341b7918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216915189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3216915189
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3307213028
Short name T1225
Test name
Test status
Simulation time 218120632 ps
CPU time 1.54 seconds
Started Jul 05 04:22:10 PM PDT 24
Finished Jul 05 04:22:12 PM PDT 24
Peak memory 199112 kb
Host smart-dbe4f1e6-f6c8-4ed8-b7d6-6ef2e3612b93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307213028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3307213028
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.109907570
Short name T1250
Test name
Test status
Simulation time 987405141 ps
CPU time 1 seconds
Started Jul 05 04:22:03 PM PDT 24
Finished Jul 05 04:22:06 PM PDT 24
Peak memory 197216 kb
Host smart-3ca276cc-bf3a-4d4a-b47d-b56ff58ee6a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109907570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.109907570
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1058533637
Short name T1299
Test name
Test status
Simulation time 275226705 ps
CPU time 0.66 seconds
Started Jul 05 04:21:51 PM PDT 24
Finished Jul 05 04:21:52 PM PDT 24
Peak memory 198468 kb
Host smart-40af6d6a-6ba8-4b80-ba4f-372ab7b38556
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058533637 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1058533637
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2151238088
Short name T1274
Test name
Test status
Simulation time 12356257 ps
CPU time 0.61 seconds
Started Jul 05 04:21:49 PM PDT 24
Finished Jul 05 04:21:50 PM PDT 24
Peak memory 196044 kb
Host smart-59613f07-d646-4e22-9e92-4fbb5cf0b837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151238088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2151238088
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2110590336
Short name T1186
Test name
Test status
Simulation time 14304770 ps
CPU time 0.58 seconds
Started Jul 05 04:20:37 PM PDT 24
Finished Jul 05 04:20:38 PM PDT 24
Peak memory 195032 kb
Host smart-76925603-c653-4d2f-bd4e-d84c7fe60d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110590336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2110590336
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.576345632
Short name T1221
Test name
Test status
Simulation time 11508773 ps
CPU time 0.6 seconds
Started Jul 05 04:22:20 PM PDT 24
Finished Jul 05 04:22:21 PM PDT 24
Peak memory 196096 kb
Host smart-fe35e73b-a0e2-4ce9-8928-6cc8dcacf08c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576345632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.576345632
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3901268580
Short name T1210
Test name
Test status
Simulation time 40436776 ps
CPU time 1.06 seconds
Started Jul 05 04:21:51 PM PDT 24
Finished Jul 05 04:21:53 PM PDT 24
Peak memory 200572 kb
Host smart-46e08846-7f06-459e-b657-e588dbde720a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901268580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3901268580
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.914074238
Short name T1293
Test name
Test status
Simulation time 30216475 ps
CPU time 0.79 seconds
Started Jul 05 04:23:23 PM PDT 24
Finished Jul 05 04:23:24 PM PDT 24
Peak memory 200140 kb
Host smart-c813f4ab-6e41-48f7-808e-fb42eeaa93ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914074238 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.914074238
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.559739388
Short name T53
Test name
Test status
Simulation time 16006616 ps
CPU time 0.59 seconds
Started Jul 05 04:21:36 PM PDT 24
Finished Jul 05 04:21:37 PM PDT 24
Peak memory 196452 kb
Host smart-a2629809-5e64-4dd0-83f1-19ba00df130e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559739388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.559739388
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2690824587
Short name T1243
Test name
Test status
Simulation time 29566445 ps
CPU time 0.59 seconds
Started Jul 05 04:19:41 PM PDT 24
Finished Jul 05 04:19:42 PM PDT 24
Peak memory 194988 kb
Host smart-080de213-cb2c-400a-ae80-88c3a9d7253e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690824587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2690824587
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2891911073
Short name T1257
Test name
Test status
Simulation time 33472872 ps
CPU time 0.6 seconds
Started Jul 05 04:23:31 PM PDT 24
Finished Jul 05 04:23:32 PM PDT 24
Peak memory 196168 kb
Host smart-c1c2b59e-5e20-4e34-9ec0-94f2051c442f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891911073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2891911073
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1362818248
Short name T1281
Test name
Test status
Simulation time 58571896 ps
CPU time 1.07 seconds
Started Jul 05 04:17:45 PM PDT 24
Finished Jul 05 04:17:46 PM PDT 24
Peak memory 200404 kb
Host smart-17be0127-b7c1-4d84-a450-adf2f4527a42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362818248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1362818248
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2112063549
Short name T84
Test name
Test status
Simulation time 183811161 ps
CPU time 0.98 seconds
Started Jul 05 04:22:54 PM PDT 24
Finished Jul 05 04:22:56 PM PDT 24
Peak memory 198752 kb
Host smart-2840e577-ed77-485b-8f45-02f54c593783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112063549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2112063549
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2323759670
Short name T1309
Test name
Test status
Simulation time 44487855 ps
CPU time 1.15 seconds
Started Jul 05 04:22:59 PM PDT 24
Finished Jul 05 04:23:01 PM PDT 24
Peak memory 200424 kb
Host smart-5544b6bb-9c94-486f-be68-73601ff9f123
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323759670 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2323759670
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3112787013
Short name T1236
Test name
Test status
Simulation time 183999255 ps
CPU time 0.62 seconds
Started Jul 05 04:18:25 PM PDT 24
Finished Jul 05 04:18:27 PM PDT 24
Peak memory 196032 kb
Host smart-6635950f-0d94-456f-b9bb-7720479a6dbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112787013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3112787013
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3390768448
Short name T1287
Test name
Test status
Simulation time 18541247 ps
CPU time 0.62 seconds
Started Jul 05 04:23:07 PM PDT 24
Finished Jul 05 04:23:08 PM PDT 24
Peak memory 194132 kb
Host smart-2fe1d440-27bb-4657-9711-01186e82c955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390768448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3390768448
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.131669925
Short name T1307
Test name
Test status
Simulation time 136130175 ps
CPU time 0.68 seconds
Started Jul 05 04:21:55 PM PDT 24
Finished Jul 05 04:21:56 PM PDT 24
Peak memory 196084 kb
Host smart-e4c533db-8776-42f0-8068-5c08b8f2682b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131669925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.131669925
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.210398691
Short name T1239
Test name
Test status
Simulation time 46049106 ps
CPU time 0.97 seconds
Started Jul 05 04:23:28 PM PDT 24
Finished Jul 05 04:23:29 PM PDT 24
Peak memory 200388 kb
Host smart-07e8f2ec-e28e-452d-bcfc-2bf3f9384b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210398691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.210398691
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.632132470
Short name T1244
Test name
Test status
Simulation time 142770211 ps
CPU time 1.04 seconds
Started Jul 05 04:22:04 PM PDT 24
Finished Jul 05 04:22:07 PM PDT 24
Peak memory 198832 kb
Host smart-b40cb401-7bb0-4f33-9464-a9885ddaf28f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632132470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.632132470
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4130890430
Short name T1276
Test name
Test status
Simulation time 44922989 ps
CPU time 0.88 seconds
Started Jul 05 04:17:49 PM PDT 24
Finished Jul 05 04:17:51 PM PDT 24
Peak memory 200348 kb
Host smart-57703371-05b8-4b8f-ab2d-1c1cf919dc12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130890430 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4130890430
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3711046641
Short name T1240
Test name
Test status
Simulation time 205814662 ps
CPU time 0.67 seconds
Started Jul 05 04:23:11 PM PDT 24
Finished Jul 05 04:23:12 PM PDT 24
Peak memory 195236 kb
Host smart-461dabb4-25b1-43e3-85c5-939df58b2f5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711046641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3711046641
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2089842142
Short name T1194
Test name
Test status
Simulation time 13567085 ps
CPU time 0.56 seconds
Started Jul 05 04:23:23 PM PDT 24
Finished Jul 05 04:23:24 PM PDT 24
Peak memory 194680 kb
Host smart-6f9310db-d4c2-4127-b285-53bf1761675b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089842142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2089842142
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.450259550
Short name T1227
Test name
Test status
Simulation time 41441573 ps
CPU time 0.62 seconds
Started Jul 05 04:22:20 PM PDT 24
Finished Jul 05 04:22:21 PM PDT 24
Peak memory 195288 kb
Host smart-3c8b4089-9142-45cd-807e-8477c1b6f83e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450259550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.450259550
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1450617304
Short name T1316
Test name
Test status
Simulation time 265475133 ps
CPU time 2.35 seconds
Started Jul 05 04:18:17 PM PDT 24
Finished Jul 05 04:18:20 PM PDT 24
Peak memory 200820 kb
Host smart-41ce52b9-fb42-4384-880c-c34bd6fd1b98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450617304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1450617304
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.213071879
Short name T81
Test name
Test status
Simulation time 42575055 ps
CPU time 0.9 seconds
Started Jul 05 04:23:22 PM PDT 24
Finished Jul 05 04:23:24 PM PDT 24
Peak memory 199688 kb
Host smart-26bd4fd0-f1be-4fbe-a3fb-db4f3aae3155
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213071879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.213071879
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.687919115
Short name T1310
Test name
Test status
Simulation time 75587509 ps
CPU time 0.72 seconds
Started Jul 05 04:22:48 PM PDT 24
Finished Jul 05 04:22:50 PM PDT 24
Peak memory 200032 kb
Host smart-eeae8f56-d47d-468b-908f-fb85cacf3857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687919115 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.687919115
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.716287578
Short name T51
Test name
Test status
Simulation time 61264872 ps
CPU time 0.56 seconds
Started Jul 05 04:18:36 PM PDT 24
Finished Jul 05 04:18:37 PM PDT 24
Peak memory 196076 kb
Host smart-c0f377af-4963-41bc-b1e4-7b7710a719c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716287578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.716287578
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.312585986
Short name T1230
Test name
Test status
Simulation time 22147551 ps
CPU time 0.54 seconds
Started Jul 05 04:22:48 PM PDT 24
Finished Jul 05 04:22:50 PM PDT 24
Peak memory 195000 kb
Host smart-c06b63ff-8cb0-4853-91cb-8921ea1f663b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312585986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.312585986
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2937428486
Short name T1261
Test name
Test status
Simulation time 20645603 ps
CPU time 0.63 seconds
Started Jul 05 04:22:46 PM PDT 24
Finished Jul 05 04:22:47 PM PDT 24
Peak memory 195272 kb
Host smart-a7c08b26-261c-44a0-9924-3f4be56cfffa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937428486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2937428486
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1475955504
Short name T1202
Test name
Test status
Simulation time 102466204 ps
CPU time 1.15 seconds
Started Jul 05 04:22:48 PM PDT 24
Finished Jul 05 04:22:51 PM PDT 24
Peak memory 200268 kb
Host smart-2738d09c-8336-41a2-87a3-364ace05cf76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475955504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1475955504
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3858729791
Short name T1311
Test name
Test status
Simulation time 337873753 ps
CPU time 1.29 seconds
Started Jul 05 04:22:48 PM PDT 24
Finished Jul 05 04:22:50 PM PDT 24
Peak memory 199816 kb
Host smart-255f42c2-0a4c-49c4-a4ac-665247c335bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858729791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3858729791
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3915103258
Short name T1306
Test name
Test status
Simulation time 22434863 ps
CPU time 0.69 seconds
Started Jul 05 04:21:57 PM PDT 24
Finished Jul 05 04:21:58 PM PDT 24
Peak memory 198928 kb
Host smart-ce50010a-9fbd-47e5-840c-496fd8774f47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915103258 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3915103258
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3656043262
Short name T71
Test name
Test status
Simulation time 22792450 ps
CPU time 0.64 seconds
Started Jul 05 04:18:13 PM PDT 24
Finished Jul 05 04:18:14 PM PDT 24
Peak memory 196172 kb
Host smart-f27cf0df-530f-40b2-83cf-062a6ff8d5a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656043262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3656043262
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2706331119
Short name T1204
Test name
Test status
Simulation time 13809106 ps
CPU time 0.57 seconds
Started Jul 05 04:22:48 PM PDT 24
Finished Jul 05 04:22:50 PM PDT 24
Peak memory 194984 kb
Host smart-293aae1f-a654-439d-bbda-b2becedd70d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706331119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2706331119
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3906023696
Short name T1267
Test name
Test status
Simulation time 110941449 ps
CPU time 0.71 seconds
Started Jul 05 04:22:48 PM PDT 24
Finished Jul 05 04:22:49 PM PDT 24
Peak memory 196392 kb
Host smart-80529721-daec-4c40-8861-dd1bcbe2269c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906023696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3906023696
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.188867510
Short name T1232
Test name
Test status
Simulation time 43695676 ps
CPU time 1.99 seconds
Started Jul 05 04:22:47 PM PDT 24
Finished Jul 05 04:22:49 PM PDT 24
Peak memory 200276 kb
Host smart-69fbca14-0467-4dd7-96bb-f88c4d426062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188867510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.188867510
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2902175355
Short name T82
Test name
Test status
Simulation time 140335522 ps
CPU time 1.35 seconds
Started Jul 05 04:22:20 PM PDT 24
Finished Jul 05 04:22:22 PM PDT 24
Peak memory 199856 kb
Host smart-30bf9581-8265-4a59-8bcf-5d2d5965d29b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902175355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2902175355
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3680945782
Short name T1195
Test name
Test status
Simulation time 64882557 ps
CPU time 0.71 seconds
Started Jul 05 04:22:48 PM PDT 24
Finished Jul 05 04:22:50 PM PDT 24
Peak memory 198652 kb
Host smart-306a51b8-5cf4-4aec-9d30-2456f3d7a99b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680945782 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3680945782
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.4135570709
Short name T1207
Test name
Test status
Simulation time 54493556 ps
CPU time 0.61 seconds
Started Jul 05 04:22:06 PM PDT 24
Finished Jul 05 04:22:07 PM PDT 24
Peak memory 196024 kb
Host smart-e9a90908-f5fe-45a4-a77e-9de66b745871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135570709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.4135570709
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1152958947
Short name T1229
Test name
Test status
Simulation time 14428853 ps
CPU time 0.58 seconds
Started Jul 05 04:22:48 PM PDT 24
Finished Jul 05 04:22:50 PM PDT 24
Peak memory 194920 kb
Host smart-bb680892-dbea-409d-a8a5-498a934c98d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152958947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1152958947
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.299539550
Short name T1282
Test name
Test status
Simulation time 16423216 ps
CPU time 0.68 seconds
Started Jul 05 04:22:31 PM PDT 24
Finished Jul 05 04:22:33 PM PDT 24
Peak memory 195424 kb
Host smart-1e3ebf3b-74d1-4388-a932-6f42c0440be5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299539550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.299539550
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.337039461
Short name T1270
Test name
Test status
Simulation time 58818821 ps
CPU time 1.29 seconds
Started Jul 05 04:23:30 PM PDT 24
Finished Jul 05 04:23:32 PM PDT 24
Peak memory 200628 kb
Host smart-3af0df85-65ed-4a6f-a3e5-12c03edaed7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337039461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.337039461
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.704160650
Short name T114
Test name
Test status
Simulation time 161327982 ps
CPU time 1.25 seconds
Started Jul 05 04:21:58 PM PDT 24
Finished Jul 05 04:21:59 PM PDT 24
Peak memory 199756 kb
Host smart-0d7f0c27-d018-43a1-802c-cd936647ab7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704160650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.704160650
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3302457201
Short name T1256
Test name
Test status
Simulation time 147907311 ps
CPU time 0.77 seconds
Started Jul 05 04:23:15 PM PDT 24
Finished Jul 05 04:23:17 PM PDT 24
Peak memory 200412 kb
Host smart-ed906862-1a58-487f-8463-5f495d221434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302457201 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3302457201
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2505501398
Short name T1312
Test name
Test status
Simulation time 50373808 ps
CPU time 0.58 seconds
Started Jul 05 04:23:19 PM PDT 24
Finished Jul 05 04:23:20 PM PDT 24
Peak memory 196084 kb
Host smart-0a1c00f3-70a9-4ef9-9e84-c8909b2d49b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505501398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2505501398
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1977758276
Short name T1272
Test name
Test status
Simulation time 23986705 ps
CPU time 0.57 seconds
Started Jul 05 04:19:21 PM PDT 24
Finished Jul 05 04:19:22 PM PDT 24
Peak memory 194952 kb
Host smart-c6ff0145-f379-4c5b-b0d2-a5d5d1651e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977758276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1977758276
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3360843252
Short name T1226
Test name
Test status
Simulation time 14001461 ps
CPU time 0.72 seconds
Started Jul 05 04:18:57 PM PDT 24
Finished Jul 05 04:18:58 PM PDT 24
Peak memory 196112 kb
Host smart-1df06530-c72a-4374-b15b-ebe03cad175d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360843252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3360843252
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.147666211
Short name T1234
Test name
Test status
Simulation time 384999493 ps
CPU time 1.81 seconds
Started Jul 05 04:17:53 PM PDT 24
Finished Jul 05 04:17:55 PM PDT 24
Peak memory 200664 kb
Host smart-d9ae19af-2d18-421d-89bf-5e6edd6b3acf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147666211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.147666211
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.242905535
Short name T113
Test name
Test status
Simulation time 76115647 ps
CPU time 1.34 seconds
Started Jul 05 04:22:48 PM PDT 24
Finished Jul 05 04:22:51 PM PDT 24
Peak memory 199988 kb
Host smart-fc27697e-f6f2-46f3-a1ce-e7109f86d570
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242905535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.242905535
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3204133467
Short name T1206
Test name
Test status
Simulation time 93203429 ps
CPU time 0.79 seconds
Started Jul 05 04:22:18 PM PDT 24
Finished Jul 05 04:22:20 PM PDT 24
Peak memory 194968 kb
Host smart-b0c5d0eb-16df-43db-9c2e-fbef4603d9bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204133467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3204133467
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1133769676
Short name T48
Test name
Test status
Simulation time 210089661 ps
CPU time 2.18 seconds
Started Jul 05 04:22:04 PM PDT 24
Finished Jul 05 04:22:08 PM PDT 24
Peak memory 196936 kb
Host smart-ece16f9d-27b8-492c-a9f1-8b059cbb29b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133769676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1133769676
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.718304694
Short name T1283
Test name
Test status
Simulation time 30188067 ps
CPU time 0.55 seconds
Started Jul 05 04:22:26 PM PDT 24
Finished Jul 05 04:22:27 PM PDT 24
Peak memory 195988 kb
Host smart-9a4dea97-7659-4b9c-afc8-f1385542705c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718304694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.718304694
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3973508873
Short name T1295
Test name
Test status
Simulation time 84265468 ps
CPU time 0.85 seconds
Started Jul 05 04:19:34 PM PDT 24
Finished Jul 05 04:19:35 PM PDT 24
Peak memory 200420 kb
Host smart-87813711-db66-46da-acce-5a98a5a9bdb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973508873 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3973508873
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1928168621
Short name T1300
Test name
Test status
Simulation time 13033783 ps
CPU time 0.61 seconds
Started Jul 05 04:22:10 PM PDT 24
Finished Jul 05 04:22:11 PM PDT 24
Peak memory 195140 kb
Host smart-ef3f1d0e-8734-4fc7-bd3b-228ecffef164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928168621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1928168621
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1072577182
Short name T1254
Test name
Test status
Simulation time 19481579 ps
CPU time 0.56 seconds
Started Jul 05 04:22:41 PM PDT 24
Finished Jul 05 04:22:42 PM PDT 24
Peak memory 194104 kb
Host smart-f6fe36cf-2bc3-41b1-8593-ce2c9a713b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072577182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1072577182
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4186689730
Short name T1218
Test name
Test status
Simulation time 19397340 ps
CPU time 0.63 seconds
Started Jul 05 04:22:33 PM PDT 24
Finished Jul 05 04:22:35 PM PDT 24
Peak memory 196156 kb
Host smart-45512ec4-a88b-4bc2-be20-de6e311a6e32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186689730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.4186689730
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4175955896
Short name T1262
Test name
Test status
Simulation time 52877235 ps
CPU time 1.46 seconds
Started Jul 05 04:22:33 PM PDT 24
Finished Jul 05 04:22:36 PM PDT 24
Peak memory 199724 kb
Host smart-12519f2b-730f-4dea-9358-785766f292e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175955896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4175955896
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1973671391
Short name T79
Test name
Test status
Simulation time 336202093 ps
CPU time 1.24 seconds
Started Jul 05 04:23:00 PM PDT 24
Finished Jul 05 04:23:02 PM PDT 24
Peak memory 199660 kb
Host smart-9145dbd7-8cca-42bb-b787-8c4223a97c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973671391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1973671391
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3256830283
Short name T1200
Test name
Test status
Simulation time 15421667 ps
CPU time 0.55 seconds
Started Jul 05 04:23:36 PM PDT 24
Finished Jul 05 04:23:37 PM PDT 24
Peak memory 194992 kb
Host smart-59b5d690-bec3-408f-b5bb-5f7ef16d4eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256830283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3256830283
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3424606514
Short name T1211
Test name
Test status
Simulation time 12182688 ps
CPU time 0.63 seconds
Started Jul 05 04:17:56 PM PDT 24
Finished Jul 05 04:17:57 PM PDT 24
Peak memory 194964 kb
Host smart-e4068e4c-38f7-464c-8fbe-7d8626702841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424606514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3424606514
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.317651967
Short name T1292
Test name
Test status
Simulation time 54467456 ps
CPU time 0.59 seconds
Started Jul 05 04:20:21 PM PDT 24
Finished Jul 05 04:20:23 PM PDT 24
Peak memory 195020 kb
Host smart-0281ee5b-dc14-4c10-a2a5-e2c24fa60ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317651967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.317651967
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2379010738
Short name T1233
Test name
Test status
Simulation time 19619202 ps
CPU time 0.58 seconds
Started Jul 05 04:17:54 PM PDT 24
Finished Jul 05 04:17:55 PM PDT 24
Peak memory 194948 kb
Host smart-32f1f312-a821-4f8f-ab4d-369c9cf64d1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379010738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2379010738
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3361598763
Short name T1268
Test name
Test status
Simulation time 52632060 ps
CPU time 0.59 seconds
Started Jul 05 04:17:56 PM PDT 24
Finished Jul 05 04:17:57 PM PDT 24
Peak memory 194928 kb
Host smart-746c1547-46ba-45a0-a1fc-eaba3d814b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361598763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3361598763
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2530666918
Short name T1290
Test name
Test status
Simulation time 196635309 ps
CPU time 0.62 seconds
Started Jul 05 04:22:36 PM PDT 24
Finished Jul 05 04:22:38 PM PDT 24
Peak memory 193420 kb
Host smart-9d7cb286-8c31-4d93-b61e-119d81f265e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530666918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2530666918
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.488364626
Short name T1209
Test name
Test status
Simulation time 80419836 ps
CPU time 0.61 seconds
Started Jul 05 04:19:48 PM PDT 24
Finished Jul 05 04:19:49 PM PDT 24
Peak memory 195020 kb
Host smart-7b7ec5b1-e4d5-4121-8f0d-77f7c03d821f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488364626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.488364626
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.271668533
Short name T1314
Test name
Test status
Simulation time 14381834 ps
CPU time 0.59 seconds
Started Jul 05 04:17:51 PM PDT 24
Finished Jul 05 04:17:52 PM PDT 24
Peak memory 195012 kb
Host smart-0c70b8e1-c4c5-4d73-ab89-d23ab10726e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271668533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.271668533
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1221050178
Short name T1252
Test name
Test status
Simulation time 14630014 ps
CPU time 0.6 seconds
Started Jul 05 04:17:59 PM PDT 24
Finished Jul 05 04:18:00 PM PDT 24
Peak memory 194912 kb
Host smart-a1347e94-af04-4229-ba81-2177be8ab5a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221050178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1221050178
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3729612970
Short name T1238
Test name
Test status
Simulation time 16346440 ps
CPU time 0.59 seconds
Started Jul 05 04:18:57 PM PDT 24
Finished Jul 05 04:18:58 PM PDT 24
Peak memory 195444 kb
Host smart-5fe5c8fd-04a3-4d42-bdff-7b82c857a6e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729612970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3729612970
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2840648756
Short name T1259
Test name
Test status
Simulation time 184932470 ps
CPU time 0.76 seconds
Started Jul 05 04:22:10 PM PDT 24
Finished Jul 05 04:22:11 PM PDT 24
Peak memory 196052 kb
Host smart-e953278b-a4b8-4704-9119-8bd69e48dc8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840648756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2840648756
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.779486637
Short name T46
Test name
Test status
Simulation time 227558639 ps
CPU time 2.15 seconds
Started Jul 05 04:22:25 PM PDT 24
Finished Jul 05 04:22:28 PM PDT 24
Peak memory 198440 kb
Host smart-11aabc6e-cc06-40e1-a60e-1ab035e206dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779486637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.779486637
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.334809132
Short name T1235
Test name
Test status
Simulation time 99429333 ps
CPU time 0.6 seconds
Started Jul 05 04:21:04 PM PDT 24
Finished Jul 05 04:21:05 PM PDT 24
Peak memory 195980 kb
Host smart-6fbda546-f949-4001-834d-4f4093364709
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334809132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.334809132
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2926781915
Short name T1237
Test name
Test status
Simulation time 73911341 ps
CPU time 1.12 seconds
Started Jul 05 04:22:25 PM PDT 24
Finished Jul 05 04:22:27 PM PDT 24
Peak memory 200660 kb
Host smart-8a301851-f64f-4999-bfff-487e349656f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926781915 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2926781915
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3793125261
Short name T1231
Test name
Test status
Simulation time 24306984 ps
CPU time 0.67 seconds
Started Jul 05 04:22:34 PM PDT 24
Finished Jul 05 04:22:37 PM PDT 24
Peak memory 195164 kb
Host smart-d2d76fce-ea12-4d29-9858-def7d67731dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793125261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3793125261
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3478980015
Short name T1203
Test name
Test status
Simulation time 16817845 ps
CPU time 0.58 seconds
Started Jul 05 04:20:30 PM PDT 24
Finished Jul 05 04:20:31 PM PDT 24
Peak memory 195156 kb
Host smart-81f9ee49-7f20-4062-99b3-1e1fde597e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478980015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3478980015
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1098385512
Short name T1277
Test name
Test status
Simulation time 33385227 ps
CPU time 0.76 seconds
Started Jul 05 04:19:48 PM PDT 24
Finished Jul 05 04:19:50 PM PDT 24
Peak memory 197624 kb
Host smart-f27eba4e-ae74-4afa-9441-e3268d13356c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098385512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1098385512
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2241443313
Short name T1182
Test name
Test status
Simulation time 214151744 ps
CPU time 2.14 seconds
Started Jul 05 04:22:57 PM PDT 24
Finished Jul 05 04:23:00 PM PDT 24
Peak memory 199776 kb
Host smart-7aaef2e0-9791-4eed-92d5-dbeea90e303e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241443313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2241443313
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3091294013
Short name T1208
Test name
Test status
Simulation time 49245612 ps
CPU time 0.58 seconds
Started Jul 05 04:19:20 PM PDT 24
Finished Jul 05 04:19:21 PM PDT 24
Peak memory 194916 kb
Host smart-d340a843-72a5-4320-8d6b-3842bd46e97b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091294013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3091294013
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3846107876
Short name T1279
Test name
Test status
Simulation time 17814636 ps
CPU time 0.65 seconds
Started Jul 05 04:19:58 PM PDT 24
Finished Jul 05 04:19:58 PM PDT 24
Peak memory 195160 kb
Host smart-60450df3-4f2b-49d8-a2f1-9caf9a7e9097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846107876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3846107876
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2810287941
Short name T1296
Test name
Test status
Simulation time 17937239 ps
CPU time 0.63 seconds
Started Jul 05 04:23:02 PM PDT 24
Finished Jul 05 04:23:04 PM PDT 24
Peak memory 194136 kb
Host smart-74e3ed0d-1bae-44cb-8869-4271f58a0f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810287941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2810287941
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3210541707
Short name T1222
Test name
Test status
Simulation time 23929322 ps
CPU time 0.58 seconds
Started Jul 05 04:20:48 PM PDT 24
Finished Jul 05 04:20:49 PM PDT 24
Peak memory 195440 kb
Host smart-402e31b2-f4c7-4a50-93f6-955b89b52a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210541707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3210541707
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2879520594
Short name T1192
Test name
Test status
Simulation time 11349078 ps
CPU time 0.6 seconds
Started Jul 05 04:18:16 PM PDT 24
Finished Jul 05 04:18:17 PM PDT 24
Peak memory 195016 kb
Host smart-a88e913f-c81a-4538-a237-9d2666f28cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879520594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2879520594
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1244965660
Short name T1220
Test name
Test status
Simulation time 19662220 ps
CPU time 0.59 seconds
Started Jul 05 04:20:19 PM PDT 24
Finished Jul 05 04:20:22 PM PDT 24
Peak memory 195076 kb
Host smart-d7717927-d2d7-45f8-89ef-2978a51ac97a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244965660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1244965660
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3085923600
Short name T1263
Test name
Test status
Simulation time 23733272 ps
CPU time 0.57 seconds
Started Jul 05 04:18:00 PM PDT 24
Finished Jul 05 04:18:01 PM PDT 24
Peak memory 195012 kb
Host smart-36e4e125-9d4f-4066-9fbb-b04691fddcf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085923600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3085923600
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.867674046
Short name T1205
Test name
Test status
Simulation time 11853132 ps
CPU time 0.66 seconds
Started Jul 05 04:20:19 PM PDT 24
Finished Jul 05 04:20:22 PM PDT 24
Peak memory 195112 kb
Host smart-825f9246-b406-42a8-a9e6-38ae8e1855a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867674046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.867674046
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.4001651930
Short name T1185
Test name
Test status
Simulation time 17507581 ps
CPU time 0.6 seconds
Started Jul 05 04:17:57 PM PDT 24
Finished Jul 05 04:17:58 PM PDT 24
Peak memory 195440 kb
Host smart-d1a9dfc8-493c-4075-9eeb-6d3ed9cde387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001651930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.4001651930
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2735545811
Short name T1193
Test name
Test status
Simulation time 48078290 ps
CPU time 0.54 seconds
Started Jul 05 04:22:22 PM PDT 24
Finished Jul 05 04:22:24 PM PDT 24
Peak memory 194948 kb
Host smart-dcf245dc-9a46-4601-9db8-79cfc9e56966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735545811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2735545811
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1730333007
Short name T1264
Test name
Test status
Simulation time 29141954 ps
CPU time 0.83 seconds
Started Jul 05 04:20:21 PM PDT 24
Finished Jul 05 04:20:23 PM PDT 24
Peak memory 196928 kb
Host smart-5057b8e4-214a-43ec-b854-04e527cea82b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730333007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1730333007
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3177034912
Short name T49
Test name
Test status
Simulation time 1039573731 ps
CPU time 2.41 seconds
Started Jul 05 04:22:13 PM PDT 24
Finished Jul 05 04:22:16 PM PDT 24
Peak memory 196844 kb
Host smart-9597c7aa-856d-49d2-9765-99804a903b14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177034912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3177034912
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3139550766
Short name T1228
Test name
Test status
Simulation time 66584161 ps
CPU time 0.62 seconds
Started Jul 05 04:18:35 PM PDT 24
Finished Jul 05 04:18:36 PM PDT 24
Peak memory 196448 kb
Host smart-6a7b42dc-d46e-42ba-ad71-42aac152b8a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139550766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3139550766
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3970357441
Short name T1248
Test name
Test status
Simulation time 37979322 ps
CPU time 0.78 seconds
Started Jul 05 04:22:13 PM PDT 24
Finished Jul 05 04:22:15 PM PDT 24
Peak memory 198628 kb
Host smart-252ceac8-4a31-40a9-9e8d-0cc49a07161d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970357441 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3970357441
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3964368466
Short name T52
Test name
Test status
Simulation time 55329969 ps
CPU time 0.6 seconds
Started Jul 05 04:20:40 PM PDT 24
Finished Jul 05 04:20:41 PM PDT 24
Peak memory 196036 kb
Host smart-2a71bd1c-e2e6-4f8b-9b2f-426ec7954b18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964368466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3964368466
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1031549907
Short name T1181
Test name
Test status
Simulation time 16614191 ps
CPU time 0.6 seconds
Started Jul 05 04:18:43 PM PDT 24
Finished Jul 05 04:18:44 PM PDT 24
Peak memory 195024 kb
Host smart-a69b3b06-5186-4c76-a9c9-295edfdf7aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031549907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1031549907
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.696122750
Short name T1303
Test name
Test status
Simulation time 26406909 ps
CPU time 0.7 seconds
Started Jul 05 04:18:27 PM PDT 24
Finished Jul 05 04:18:29 PM PDT 24
Peak memory 195620 kb
Host smart-082531f7-aa20-4e19-8422-5872624e8754
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696122750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.696122750
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1329426517
Short name T1184
Test name
Test status
Simulation time 86370912 ps
CPU time 1.31 seconds
Started Jul 05 04:22:03 PM PDT 24
Finished Jul 05 04:22:06 PM PDT 24
Peak memory 198680 kb
Host smart-1a3466be-ba4e-446b-b37d-af867bfb240c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329426517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1329426517
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3624382393
Short name T1294
Test name
Test status
Simulation time 106355800 ps
CPU time 1.26 seconds
Started Jul 05 04:18:47 PM PDT 24
Finished Jul 05 04:18:48 PM PDT 24
Peak memory 199908 kb
Host smart-d1c0190c-4f83-43dd-8a47-579ea4323b77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624382393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3624382393
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1918064641
Short name T1196
Test name
Test status
Simulation time 38934906 ps
CPU time 0.57 seconds
Started Jul 05 04:19:55 PM PDT 24
Finished Jul 05 04:19:56 PM PDT 24
Peak memory 195160 kb
Host smart-48c81067-58bd-41b5-a597-7603059fbae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918064641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1918064641
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1618128961
Short name T1187
Test name
Test status
Simulation time 17349155 ps
CPU time 0.6 seconds
Started Jul 05 04:21:22 PM PDT 24
Finished Jul 05 04:21:23 PM PDT 24
Peak memory 194988 kb
Host smart-d4b85a48-e635-47b6-bf42-8a34d1286e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618128961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1618128961
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4220239301
Short name T1219
Test name
Test status
Simulation time 33385050 ps
CPU time 0.59 seconds
Started Jul 05 04:22:54 PM PDT 24
Finished Jul 05 04:22:56 PM PDT 24
Peak memory 194752 kb
Host smart-8a0c1bd7-3e52-4b65-98b6-39a8a7cdd4db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220239301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4220239301
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2447069355
Short name T1266
Test name
Test status
Simulation time 22207789 ps
CPU time 0.53 seconds
Started Jul 05 04:22:22 PM PDT 24
Finished Jul 05 04:22:24 PM PDT 24
Peak memory 194948 kb
Host smart-f2684e23-98f6-4315-8cf7-a03d54118f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447069355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2447069355
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2308912952
Short name T1258
Test name
Test status
Simulation time 16337982 ps
CPU time 0.59 seconds
Started Jul 05 04:20:06 PM PDT 24
Finished Jul 05 04:20:07 PM PDT 24
Peak memory 195032 kb
Host smart-59b6c009-407d-4abf-bfd6-31f32e24ec3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308912952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2308912952
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3157102790
Short name T1215
Test name
Test status
Simulation time 16081951 ps
CPU time 0.62 seconds
Started Jul 05 04:23:17 PM PDT 24
Finished Jul 05 04:23:18 PM PDT 24
Peak memory 194128 kb
Host smart-7dc83c6d-b12e-4615-abc1-95ed60964f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157102790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3157102790
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3262608146
Short name T1213
Test name
Test status
Simulation time 27884171 ps
CPU time 0.58 seconds
Started Jul 05 04:21:09 PM PDT 24
Finished Jul 05 04:21:11 PM PDT 24
Peak memory 195024 kb
Host smart-da70ab89-c9c3-4dad-9701-beb34d17a1a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262608146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3262608146
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3908060762
Short name T1183
Test name
Test status
Simulation time 50252544 ps
CPU time 0.57 seconds
Started Jul 05 04:21:21 PM PDT 24
Finished Jul 05 04:21:22 PM PDT 24
Peak memory 195084 kb
Host smart-a564d845-9e8c-4e43-bed1-c78b04426cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908060762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3908060762
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2712904024
Short name T1191
Test name
Test status
Simulation time 12004807 ps
CPU time 0.58 seconds
Started Jul 05 04:18:16 PM PDT 24
Finished Jul 05 04:18:17 PM PDT 24
Peak memory 195024 kb
Host smart-43abb5c8-ec97-4da3-a00b-75d877001e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712904024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2712904024
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.908699189
Short name T1297
Test name
Test status
Simulation time 14520123 ps
CPU time 0.64 seconds
Started Jul 05 04:18:29 PM PDT 24
Finished Jul 05 04:18:30 PM PDT 24
Peak memory 195032 kb
Host smart-8a193ca4-f8b1-4ab5-a1d8-2d1ba48bc0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908699189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.908699189
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4085996671
Short name T1260
Test name
Test status
Simulation time 20347085 ps
CPU time 0.64 seconds
Started Jul 05 04:22:18 PM PDT 24
Finished Jul 05 04:22:20 PM PDT 24
Peak memory 198036 kb
Host smart-577cd67e-04ca-463b-ac2a-1a1dd77881b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085996671 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.4085996671
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3313356960
Short name T74
Test name
Test status
Simulation time 23346927 ps
CPU time 0.64 seconds
Started Jul 05 04:17:55 PM PDT 24
Finished Jul 05 04:17:56 PM PDT 24
Peak memory 196080 kb
Host smart-a4c39bac-5e64-43e3-a68c-b5a0b9604669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313356960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3313356960
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.540256429
Short name T1315
Test name
Test status
Simulation time 30130401 ps
CPU time 0.63 seconds
Started Jul 05 04:22:33 PM PDT 24
Finished Jul 05 04:22:35 PM PDT 24
Peak memory 193624 kb
Host smart-b68e8179-21cd-498e-8c0a-1598a5dee6eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540256429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.540256429
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1490105040
Short name T1224
Test name
Test status
Simulation time 22231440 ps
CPU time 0.82 seconds
Started Jul 05 04:22:10 PM PDT 24
Finished Jul 05 04:22:11 PM PDT 24
Peak memory 194716 kb
Host smart-6c8077ce-646c-4e15-851a-9e1e5fd0a6cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490105040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1490105040
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2820810243
Short name T1301
Test name
Test status
Simulation time 47124532 ps
CPU time 2.36 seconds
Started Jul 05 04:22:49 PM PDT 24
Finished Jul 05 04:22:53 PM PDT 24
Peak memory 200616 kb
Host smart-94720441-a6cd-4370-8ed4-cd99ac54ba6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820810243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2820810243
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1457227342
Short name T87
Test name
Test status
Simulation time 250965906 ps
CPU time 1.34 seconds
Started Jul 05 04:22:33 PM PDT 24
Finished Jul 05 04:22:36 PM PDT 24
Peak memory 198680 kb
Host smart-e878cea0-30d5-4cad-859d-f740c2994a12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457227342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1457227342
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1647897031
Short name T1246
Test name
Test status
Simulation time 55593111 ps
CPU time 0.67 seconds
Started Jul 05 04:22:33 PM PDT 24
Finished Jul 05 04:22:35 PM PDT 24
Peak memory 199688 kb
Host smart-8b6dd4cf-fda9-4b05-84e5-2a5fad8e7bb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647897031 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1647897031
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.474411310
Short name T1223
Test name
Test status
Simulation time 14152467 ps
CPU time 0.65 seconds
Started Jul 05 04:18:08 PM PDT 24
Finished Jul 05 04:18:09 PM PDT 24
Peak memory 196040 kb
Host smart-61b4561c-39bd-473a-b0a9-adacecaf945d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474411310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.474411310
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3988837369
Short name T1278
Test name
Test status
Simulation time 35981661 ps
CPU time 0.6 seconds
Started Jul 05 04:21:09 PM PDT 24
Finished Jul 05 04:21:10 PM PDT 24
Peak memory 195020 kb
Host smart-4a32ebf6-89bc-449e-8cbd-d86872078a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988837369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3988837369
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1878094818
Short name T73
Test name
Test status
Simulation time 66703788 ps
CPU time 0.78 seconds
Started Jul 05 04:21:21 PM PDT 24
Finished Jul 05 04:21:22 PM PDT 24
Peak memory 196628 kb
Host smart-840aabbb-6587-4c7b-b2ae-565cb2afd3b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878094818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1878094818
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1832939668
Short name T1188
Test name
Test status
Simulation time 25427869 ps
CPU time 1.33 seconds
Started Jul 05 04:20:15 PM PDT 24
Finished Jul 05 04:20:18 PM PDT 24
Peak memory 200684 kb
Host smart-eeb57ab5-b0f8-4da7-8d01-1d6a63597c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832939668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1832939668
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2013907412
Short name T1291
Test name
Test status
Simulation time 95586590 ps
CPU time 0.93 seconds
Started Jul 05 04:22:18 PM PDT 24
Finished Jul 05 04:22:20 PM PDT 24
Peak memory 197592 kb
Host smart-665d2ead-e91f-41f5-ae27-607f5076bcac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013907412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2013907412
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.927998402
Short name T1269
Test name
Test status
Simulation time 20830761 ps
CPU time 0.72 seconds
Started Jul 05 04:22:10 PM PDT 24
Finished Jul 05 04:22:12 PM PDT 24
Peak memory 198196 kb
Host smart-81ae1717-effc-4288-8768-956a916625dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927998402 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.927998402
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3395232186
Short name T68
Test name
Test status
Simulation time 58151529 ps
CPU time 0.7 seconds
Started Jul 05 04:22:44 PM PDT 24
Finished Jul 05 04:22:45 PM PDT 24
Peak memory 195344 kb
Host smart-601e9ef7-9dff-4524-969a-b64901af30d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395232186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3395232186
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.511586729
Short name T1242
Test name
Test status
Simulation time 14240640 ps
CPU time 0.58 seconds
Started Jul 05 04:22:25 PM PDT 24
Finished Jul 05 04:22:26 PM PDT 24
Peak memory 194992 kb
Host smart-25c36a40-80e4-4834-a4b6-153af3793fbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511586729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.511586729
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3127905174
Short name T1288
Test name
Test status
Simulation time 21804256 ps
CPU time 0.64 seconds
Started Jul 05 04:21:21 PM PDT 24
Finished Jul 05 04:21:22 PM PDT 24
Peak memory 195220 kb
Host smart-4062487b-2f4b-4f5c-b493-649bcff59d57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127905174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3127905174
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1284703319
Short name T1284
Test name
Test status
Simulation time 41579367 ps
CPU time 1.84 seconds
Started Jul 05 04:22:44 PM PDT 24
Finished Jul 05 04:22:47 PM PDT 24
Peak memory 199564 kb
Host smart-56ac46a5-719a-4b85-82ad-eea5ab678397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284703319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1284703319
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2783234661
Short name T1253
Test name
Test status
Simulation time 703902605 ps
CPU time 1.35 seconds
Started Jul 05 04:17:39 PM PDT 24
Finished Jul 05 04:17:40 PM PDT 24
Peak memory 199892 kb
Host smart-7ae8051d-9ab2-4553-91ae-868b72309347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783234661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2783234661
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1934472704
Short name T1305
Test name
Test status
Simulation time 35337564 ps
CPU time 0.72 seconds
Started Jul 05 04:20:41 PM PDT 24
Finished Jul 05 04:20:43 PM PDT 24
Peak memory 198688 kb
Host smart-aba5f893-0fda-4333-93bb-5556fdc5b38c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934472704 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1934472704
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.4041637880
Short name T1280
Test name
Test status
Simulation time 48610501 ps
CPU time 0.69 seconds
Started Jul 05 04:19:34 PM PDT 24
Finished Jul 05 04:19:35 PM PDT 24
Peak memory 196140 kb
Host smart-75281e7e-ac94-4e7c-b01d-134a118b0513
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041637880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.4041637880
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2399870706
Short name T1304
Test name
Test status
Simulation time 14043055 ps
CPU time 0.55 seconds
Started Jul 05 04:22:11 PM PDT 24
Finished Jul 05 04:22:12 PM PDT 24
Peak memory 194696 kb
Host smart-68818458-2557-4573-8b7d-fbaaa6ebb64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399870706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2399870706
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1927933206
Short name T69
Test name
Test status
Simulation time 86421586 ps
CPU time 0.66 seconds
Started Jul 05 04:17:55 PM PDT 24
Finished Jul 05 04:17:56 PM PDT 24
Peak memory 195324 kb
Host smart-1a5373bf-7f1b-404c-a8c6-9647f8523505
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927933206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1927933206
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3776856021
Short name T1289
Test name
Test status
Simulation time 287898866 ps
CPU time 1.51 seconds
Started Jul 05 04:22:34 PM PDT 24
Finished Jul 05 04:22:37 PM PDT 24
Peak memory 200620 kb
Host smart-d0cf8cbf-efc3-4344-b1dd-6ad4c89376d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776856021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3776856021
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2319956105
Short name T80
Test name
Test status
Simulation time 63497426 ps
CPU time 0.9 seconds
Started Jul 05 04:22:16 PM PDT 24
Finished Jul 05 04:22:17 PM PDT 24
Peak memory 199708 kb
Host smart-544f769f-7694-4497-b0a0-208fba965b34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319956105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2319956105
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.549079348
Short name T1285
Test name
Test status
Simulation time 31134488 ps
CPU time 0.85 seconds
Started Jul 05 04:20:54 PM PDT 24
Finished Jul 05 04:20:55 PM PDT 24
Peak memory 200828 kb
Host smart-d49e599b-fe9b-40c2-b5e4-580318db732d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549079348 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.549079348
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1805712552
Short name T1214
Test name
Test status
Simulation time 13926059 ps
CPU time 0.62 seconds
Started Jul 05 04:22:26 PM PDT 24
Finished Jul 05 04:22:27 PM PDT 24
Peak memory 196340 kb
Host smart-c3904162-aedf-4875-9bc1-41768e35c407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805712552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1805712552
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.26656321
Short name T1190
Test name
Test status
Simulation time 14465247 ps
CPU time 0.6 seconds
Started Jul 05 04:22:05 PM PDT 24
Finished Jul 05 04:22:06 PM PDT 24
Peak memory 194760 kb
Host smart-5b501150-aaaf-4a40-9645-d6ea796e087e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26656321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.26656321
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.907920431
Short name T72
Test name
Test status
Simulation time 135293746 ps
CPU time 0.66 seconds
Started Jul 05 04:22:11 PM PDT 24
Finished Jul 05 04:22:12 PM PDT 24
Peak memory 195896 kb
Host smart-39fcd67c-3698-45c1-8621-074f3eae3ee2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907920431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.907920431
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2108030129
Short name T1217
Test name
Test status
Simulation time 897630552 ps
CPU time 1.55 seconds
Started Jul 05 04:18:31 PM PDT 24
Finished Jul 05 04:18:34 PM PDT 24
Peak memory 200656 kb
Host smart-9e734bd1-cc41-4cf5-b5a6-8b2caf5e9e93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108030129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2108030129
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.700994670
Short name T86
Test name
Test status
Simulation time 84184567 ps
CPU time 1.26 seconds
Started Jul 05 04:18:32 PM PDT 24
Finished Jul 05 04:18:34 PM PDT 24
Peak memory 199696 kb
Host smart-3fe49472-6ba7-4b36-bdc7-084de78858bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700994670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.700994670
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.999234950
Short name T965
Test name
Test status
Simulation time 12206945 ps
CPU time 0.58 seconds
Started Jul 05 05:36:55 PM PDT 24
Finished Jul 05 05:36:57 PM PDT 24
Peak memory 195328 kb
Host smart-955c3292-f9c5-4a75-8b94-ee37e67a9984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999234950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.999234950
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3797548818
Short name T762
Test name
Test status
Simulation time 118303738615 ps
CPU time 72.37 seconds
Started Jul 05 05:36:51 PM PDT 24
Finished Jul 05 05:38:06 PM PDT 24
Peak memory 199940 kb
Host smart-974a49ea-5233-4ded-8b4a-044cd68a449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797548818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3797548818
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.476799880
Short name T1094
Test name
Test status
Simulation time 101773471385 ps
CPU time 54.71 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:37:53 PM PDT 24
Peak memory 199992 kb
Host smart-14a0cd15-367a-4351-a429-1dff0eb2cfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476799880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.476799880
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1466619688
Short name T146
Test name
Test status
Simulation time 185100598264 ps
CPU time 105.63 seconds
Started Jul 05 05:36:55 PM PDT 24
Finished Jul 05 05:38:41 PM PDT 24
Peak memory 199900 kb
Host smart-4b6875e4-32c5-40cf-a46f-d58708f3f766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466619688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1466619688
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2940850231
Short name T948
Test name
Test status
Simulation time 22739789987 ps
CPU time 39 seconds
Started Jul 05 05:37:17 PM PDT 24
Finished Jul 05 05:37:57 PM PDT 24
Peak memory 199796 kb
Host smart-08cee937-bc38-4fd0-afec-072cfb330eb6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940850231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2940850231
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2948167263
Short name T825
Test name
Test status
Simulation time 59232894883 ps
CPU time 430.43 seconds
Started Jul 05 05:36:55 PM PDT 24
Finished Jul 05 05:44:06 PM PDT 24
Peak memory 199944 kb
Host smart-fa07ffb4-c725-4ccf-b13d-3fc7499db3ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948167263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2948167263
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1909872268
Short name T642
Test name
Test status
Simulation time 4421462043 ps
CPU time 4.04 seconds
Started Jul 05 05:36:59 PM PDT 24
Finished Jul 05 05:37:04 PM PDT 24
Peak memory 199816 kb
Host smart-0e9d3535-7927-49d8-9f31-42b562e90a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909872268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1909872268
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1310314436
Short name T1168
Test name
Test status
Simulation time 154991983954 ps
CPU time 12.92 seconds
Started Jul 05 05:36:59 PM PDT 24
Finished Jul 05 05:37:12 PM PDT 24
Peak memory 194484 kb
Host smart-8a2acb0b-5288-4157-8a12-827d879aba9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310314436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1310314436
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3314821223
Short name T1169
Test name
Test status
Simulation time 10281180517 ps
CPU time 616.91 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:47:16 PM PDT 24
Peak memory 199996 kb
Host smart-afa7ebd4-8bb2-4f1c-a1ee-f9bf06db25f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314821223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3314821223
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2545743211
Short name T396
Test name
Test status
Simulation time 5798724559 ps
CPU time 48.19 seconds
Started Jul 05 05:36:56 PM PDT 24
Finished Jul 05 05:37:45 PM PDT 24
Peak memory 199204 kb
Host smart-84effb0f-204f-45f2-a61d-16e28731c7ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545743211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2545743211
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2717221145
Short name T1041
Test name
Test status
Simulation time 76691988547 ps
CPU time 28.34 seconds
Started Jul 05 05:37:02 PM PDT 24
Finished Jul 05 05:37:31 PM PDT 24
Peak memory 199916 kb
Host smart-c8b074e6-5138-4021-a488-cff807849253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717221145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2717221145
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.459461251
Short name T405
Test name
Test status
Simulation time 1574606916 ps
CPU time 1.2 seconds
Started Jul 05 05:37:04 PM PDT 24
Finished Jul 05 05:37:07 PM PDT 24
Peak memory 195312 kb
Host smart-5cb3ca8e-a6d8-4d23-9a48-56e63d050278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459461251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.459461251
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.926572402
Short name T88
Test name
Test status
Simulation time 76297762 ps
CPU time 0.85 seconds
Started Jul 05 05:36:56 PM PDT 24
Finished Jul 05 05:36:58 PM PDT 24
Peak memory 218284 kb
Host smart-b58cf5f8-a854-488c-ba73-fc42d2c6ddc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926572402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.926572402
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.3358708880
Short name T382
Test name
Test status
Simulation time 647673832 ps
CPU time 2.71 seconds
Started Jul 05 05:36:50 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 199372 kb
Host smart-656ecc72-74a0-4b06-8cf3-a9d720ce54cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358708880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3358708880
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.4269664241
Short name T699
Test name
Test status
Simulation time 28608728146 ps
CPU time 348.16 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:42:54 PM PDT 24
Peak memory 216712 kb
Host smart-1df9a30c-303c-4092-a89a-b402863840e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269664241 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.4269664241
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1347228053
Short name T370
Test name
Test status
Simulation time 805080790 ps
CPU time 2.4 seconds
Started Jul 05 05:37:02 PM PDT 24
Finished Jul 05 05:37:09 PM PDT 24
Peak memory 199744 kb
Host smart-94a38b7b-04c0-4ca8-9771-74600b455aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347228053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1347228053
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_alert_test.1683623293
Short name T1129
Test name
Test status
Simulation time 56286809 ps
CPU time 0.6 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:37:00 PM PDT 24
Peak memory 195324 kb
Host smart-a2484d40-a656-4700-91cf-06713eca533f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683623293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1683623293
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4227242230
Short name T1043
Test name
Test status
Simulation time 97921059169 ps
CPU time 35.63 seconds
Started Jul 05 05:36:56 PM PDT 24
Finished Jul 05 05:37:33 PM PDT 24
Peak memory 199924 kb
Host smart-7c55013f-9614-40b5-8541-aec2740aa412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227242230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4227242230
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1612120821
Short name T1123
Test name
Test status
Simulation time 31420842080 ps
CPU time 22.78 seconds
Started Jul 05 05:36:59 PM PDT 24
Finished Jul 05 05:37:22 PM PDT 24
Peak memory 199864 kb
Host smart-9d6c69a0-2b4c-4320-9614-9dddf1aefdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612120821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1612120821
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.968538910
Short name T840
Test name
Test status
Simulation time 66785264578 ps
CPU time 24.43 seconds
Started Jul 05 05:37:06 PM PDT 24
Finished Jul 05 05:37:32 PM PDT 24
Peak memory 199816 kb
Host smart-50a68aca-68d3-4f73-b0af-a643e31bf500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968538910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.968538910
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2056970256
Short name T615
Test name
Test status
Simulation time 17937749456 ps
CPU time 13.52 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:37:31 PM PDT 24
Peak memory 199732 kb
Host smart-ac3934ad-02f1-455a-a3d4-ac05873b249b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056970256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2056970256
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1265308978
Short name T1048
Test name
Test status
Simulation time 38861401417 ps
CPU time 348.6 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:42:47 PM PDT 24
Peak memory 200000 kb
Host smart-263c4847-90ed-4b80-9cfd-7504e28b13c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265308978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1265308978
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3431649942
Short name T741
Test name
Test status
Simulation time 4472063108 ps
CPU time 8.99 seconds
Started Jul 05 05:37:04 PM PDT 24
Finished Jul 05 05:37:15 PM PDT 24
Peak memory 199860 kb
Host smart-ae6ff1f6-36fb-4cea-ab32-1cd0b1975674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431649942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3431649942
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.71731578
Short name T1175
Test name
Test status
Simulation time 29787864418 ps
CPU time 47.74 seconds
Started Jul 05 05:37:06 PM PDT 24
Finished Jul 05 05:37:55 PM PDT 24
Peak memory 200056 kb
Host smart-f33ff561-237a-4dfd-89f9-5f73a1f39867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71731578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.71731578
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2822788062
Short name T306
Test name
Test status
Simulation time 12463047667 ps
CPU time 73.15 seconds
Started Jul 05 05:37:04 PM PDT 24
Finished Jul 05 05:38:19 PM PDT 24
Peak memory 199944 kb
Host smart-1323d6d5-9e6d-407f-930e-e6d639772746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822788062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2822788062
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.80658021
Short name T928
Test name
Test status
Simulation time 5048803027 ps
CPU time 9.85 seconds
Started Jul 05 05:36:59 PM PDT 24
Finished Jul 05 05:37:10 PM PDT 24
Peak memory 199188 kb
Host smart-2b8e27de-2cf8-489f-ad30-b62d44b6e59e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80658021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.80658021
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.921642607
Short name T613
Test name
Test status
Simulation time 81727591061 ps
CPU time 22.12 seconds
Started Jul 05 05:36:59 PM PDT 24
Finished Jul 05 05:37:22 PM PDT 24
Peak memory 199772 kb
Host smart-88905707-6f0a-4ff9-bf3c-d60e24febf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921642607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.921642607
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2063801417
Short name T1
Test name
Test status
Simulation time 3954612499 ps
CPU time 1.99 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:37:07 PM PDT 24
Peak memory 196116 kb
Host smart-4b2b0200-a7cf-4049-9a42-d5f5a68af4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063801417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2063801417
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.926926989
Short name T915
Test name
Test status
Simulation time 265830962 ps
CPU time 1.48 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:37:01 PM PDT 24
Peak memory 198708 kb
Host smart-76e9f4a2-82e4-4094-bf05-6e2f5f320c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926926989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.926926989
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1679179414
Short name T943
Test name
Test status
Simulation time 17436826589 ps
CPU time 10.55 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:37:28 PM PDT 24
Peak memory 199908 kb
Host smart-062c749a-332e-4565-b175-04301690b461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679179414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1679179414
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2884568924
Short name T1163
Test name
Test status
Simulation time 76002880035 ps
CPU time 783.05 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:50:06 PM PDT 24
Peak memory 224796 kb
Host smart-3f6e7e40-dd4e-47ae-81b1-c2b3c6e73d4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884568924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2884568924
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.967231374
Short name T1046
Test name
Test status
Simulation time 8075200239 ps
CPU time 8.2 seconds
Started Jul 05 05:36:57 PM PDT 24
Finished Jul 05 05:37:06 PM PDT 24
Peak memory 200004 kb
Host smart-33c5ccc4-854f-4d67-a448-8ab1ac2f1943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967231374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.967231374
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1535636600
Short name T512
Test name
Test status
Simulation time 51208465537 ps
CPU time 82.58 seconds
Started Jul 05 05:37:02 PM PDT 24
Finished Jul 05 05:38:31 PM PDT 24
Peak memory 199980 kb
Host smart-12006406-8a21-4f24-95b5-33c4622450f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535636600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1535636600
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2137985923
Short name T666
Test name
Test status
Simulation time 66557860 ps
CPU time 0.55 seconds
Started Jul 05 05:37:28 PM PDT 24
Finished Jul 05 05:37:30 PM PDT 24
Peak memory 195276 kb
Host smart-ef748990-4b3f-4188-8f95-66ea199bcbd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137985923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2137985923
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.4251433825
Short name T417
Test name
Test status
Simulation time 13995289407 ps
CPU time 20.58 seconds
Started Jul 05 05:37:27 PM PDT 24
Finished Jul 05 05:37:49 PM PDT 24
Peak memory 199860 kb
Host smart-3672937f-6797-4d4f-ad36-495e3f6d0673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251433825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.4251433825
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1389184528
Short name T904
Test name
Test status
Simulation time 46944623685 ps
CPU time 32.74 seconds
Started Jul 05 05:37:27 PM PDT 24
Finished Jul 05 05:38:01 PM PDT 24
Peak memory 199852 kb
Host smart-e136ec3d-35d1-40a5-8b15-bf79f8c8af45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389184528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1389184528
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1033863736
Short name T714
Test name
Test status
Simulation time 50868615708 ps
CPU time 99.92 seconds
Started Jul 05 05:37:30 PM PDT 24
Finished Jul 05 05:39:11 PM PDT 24
Peak memory 199908 kb
Host smart-2524018c-fa0c-4c41-a208-c024af14e60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033863736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1033863736
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3122859410
Short name T379
Test name
Test status
Simulation time 26258040917 ps
CPU time 42.1 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:38:09 PM PDT 24
Peak memory 198788 kb
Host smart-5ebf35fd-eff8-452b-89de-11983107048b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122859410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3122859410
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1511379524
Short name T1013
Test name
Test status
Simulation time 121622185382 ps
CPU time 529.87 seconds
Started Jul 05 05:37:24 PM PDT 24
Finished Jul 05 05:46:15 PM PDT 24
Peak memory 199920 kb
Host smart-cf515fbc-686f-4ef1-bcc3-b3a713d05358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511379524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1511379524
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.756800242
Short name T1149
Test name
Test status
Simulation time 1648833829 ps
CPU time 1.55 seconds
Started Jul 05 05:37:34 PM PDT 24
Finished Jul 05 05:37:36 PM PDT 24
Peak memory 198408 kb
Host smart-f2196b0a-4a7f-4163-ac21-a8f1ebfd698f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756800242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.756800242
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3708842545
Short name T294
Test name
Test status
Simulation time 18631330867 ps
CPU time 9.18 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 05:37:44 PM PDT 24
Peak memory 200048 kb
Host smart-14bb5e24-a258-41eb-8003-0bf4f0d5bd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708842545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3708842545
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2802928952
Short name T463
Test name
Test status
Simulation time 17950728793 ps
CPU time 80.35 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:38:48 PM PDT 24
Peak memory 199972 kb
Host smart-57e6caaa-f35f-434d-ac6e-a3023aacf21b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802928952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2802928952
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2933011859
Short name T979
Test name
Test status
Simulation time 2113232645 ps
CPU time 9.49 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:37:38 PM PDT 24
Peak memory 198144 kb
Host smart-8afac13e-807a-40d0-8e63-e5139846cd85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933011859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2933011859
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3672686017
Short name T701
Test name
Test status
Simulation time 16316742027 ps
CPU time 23.58 seconds
Started Jul 05 05:37:30 PM PDT 24
Finished Jul 05 05:37:55 PM PDT 24
Peak memory 199612 kb
Host smart-712ab4a2-7438-4f03-9e96-39045e1edf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672686017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3672686017
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3982070180
Short name T993
Test name
Test status
Simulation time 37736607628 ps
CPU time 50.34 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:38:16 PM PDT 24
Peak memory 196028 kb
Host smart-03937986-8bca-4fc9-99fc-e6791f4b6be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982070180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3982070180
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1873866404
Short name T1030
Test name
Test status
Simulation time 5902789052 ps
CPU time 12.95 seconds
Started Jul 05 05:37:28 PM PDT 24
Finished Jul 05 05:37:42 PM PDT 24
Peak memory 199924 kb
Host smart-534d877b-b2a4-43fe-bf82-0eccef393168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873866404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1873866404
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2243979169
Short name T263
Test name
Test status
Simulation time 164078854745 ps
CPU time 482.51 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:45:29 PM PDT 24
Peak memory 215928 kb
Host smart-10b89712-89ae-4a59-8669-7fc9074226b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243979169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2243979169
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3858921057
Short name T961
Test name
Test status
Simulation time 13493573106 ps
CPU time 118.24 seconds
Started Jul 05 05:37:27 PM PDT 24
Finished Jul 05 05:39:27 PM PDT 24
Peak memory 216732 kb
Host smart-d5de5f6b-c42b-4a22-a4a7-348afa04b47f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858921057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3858921057
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3033147550
Short name T789
Test name
Test status
Simulation time 7033384947 ps
CPU time 12.65 seconds
Started Jul 05 05:37:24 PM PDT 24
Finished Jul 05 05:37:37 PM PDT 24
Peak memory 199996 kb
Host smart-1f23b64a-914a-444a-aff7-abe776076bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033147550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3033147550
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.632059723
Short name T1054
Test name
Test status
Simulation time 59709479152 ps
CPU time 20.71 seconds
Started Jul 05 05:37:30 PM PDT 24
Finished Jul 05 05:37:52 PM PDT 24
Peak memory 199904 kb
Host smart-dbc27247-2041-4804-90a0-140edbc620bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632059723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.632059723
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3809441098
Short name T936
Test name
Test status
Simulation time 24362741663 ps
CPU time 38.46 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:40:44 PM PDT 24
Peak memory 199876 kb
Host smart-22506037-b51c-4393-bd9c-751bb441c048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809441098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3809441098
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2596540224
Short name T197
Test name
Test status
Simulation time 77235071950 ps
CPU time 107.95 seconds
Started Jul 05 05:40:14 PM PDT 24
Finished Jul 05 05:42:03 PM PDT 24
Peak memory 199996 kb
Host smart-1dad5d79-5d00-45b9-a867-4eb3ec6a4a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596540224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2596540224
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1863801871
Short name T1106
Test name
Test status
Simulation time 71764654759 ps
CPU time 121.35 seconds
Started Jul 05 05:40:12 PM PDT 24
Finished Jul 05 05:42:14 PM PDT 24
Peak memory 199920 kb
Host smart-ed425d6b-ec34-4f65-930d-e61aca4fdcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863801871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1863801871
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2419937639
Short name T484
Test name
Test status
Simulation time 14248650192 ps
CPU time 38.45 seconds
Started Jul 05 05:40:14 PM PDT 24
Finished Jul 05 05:40:53 PM PDT 24
Peak memory 199872 kb
Host smart-c9ab4260-bcfa-46c6-aafd-1ec2c79b150a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419937639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2419937639
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3699712706
Short name T202
Test name
Test status
Simulation time 20460586278 ps
CPU time 35.69 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:40:49 PM PDT 24
Peak memory 199976 kb
Host smart-7f7d8923-f9a6-4165-b26e-6aaa8f775852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699712706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3699712706
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3086402118
Short name T617
Test name
Test status
Simulation time 9053658518 ps
CPU time 14.93 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:40:29 PM PDT 24
Peak memory 199544 kb
Host smart-69772ce8-4a10-4ee7-9f9a-cbb5f12800bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086402118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3086402118
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3618313736
Short name T731
Test name
Test status
Simulation time 104855492197 ps
CPU time 106.14 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:42:00 PM PDT 24
Peak memory 199792 kb
Host smart-9c4c9f31-615e-4312-9860-8cf3fdbdd4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618313736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3618313736
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3435141698
Short name T252
Test name
Test status
Simulation time 10474063776 ps
CPU time 15.98 seconds
Started Jul 05 05:40:11 PM PDT 24
Finished Jul 05 05:40:28 PM PDT 24
Peak memory 199880 kb
Host smart-6a603c7d-8d53-461c-a5f5-191a32e5ee7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435141698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3435141698
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1338696252
Short name T574
Test name
Test status
Simulation time 92591480516 ps
CPU time 10.96 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:40:25 PM PDT 24
Peak memory 199932 kb
Host smart-faf25825-8544-41d9-91ff-2305fcaf8f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338696252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1338696252
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2106446140
Short name T391
Test name
Test status
Simulation time 21300271446 ps
CPU time 37.56 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:38:05 PM PDT 24
Peak memory 199924 kb
Host smart-2ece0fcc-fde3-4586-81d1-92603ee752e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106446140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2106446140
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4862226
Short name T826
Test name
Test status
Simulation time 153894084980 ps
CPU time 71.86 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:38:40 PM PDT 24
Peak memory 199380 kb
Host smart-f44386b4-0930-4f4c-a373-74c8e48c817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4862226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4862226
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3486290125
Short name T670
Test name
Test status
Simulation time 161854747229 ps
CPU time 14.76 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:37:43 PM PDT 24
Peak memory 199976 kb
Host smart-c2613bd8-b4d2-4d91-9fd7-5534e0e18d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486290125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3486290125
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3896664501
Short name T110
Test name
Test status
Simulation time 46277095603 ps
CPU time 67.52 seconds
Started Jul 05 05:37:37 PM PDT 24
Finished Jul 05 05:38:47 PM PDT 24
Peak memory 199948 kb
Host smart-b4e10464-50ad-4278-8d89-424d86a66e30
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896664501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3896664501
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3608050516
Short name T663
Test name
Test status
Simulation time 51282745782 ps
CPU time 207.04 seconds
Started Jul 05 05:37:31 PM PDT 24
Finished Jul 05 05:41:00 PM PDT 24
Peak memory 199932 kb
Host smart-d6e9d008-bb13-45a5-8ea7-9091717bb82d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608050516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3608050516
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2887377602
Short name T96
Test name
Test status
Simulation time 12636234109 ps
CPU time 14.29 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:37:42 PM PDT 24
Peak memory 199904 kb
Host smart-036a4dd7-c8eb-40c7-9df3-75063653be34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887377602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2887377602
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2775219390
Short name T754
Test name
Test status
Simulation time 94664219414 ps
CPU time 38.03 seconds
Started Jul 05 05:37:31 PM PDT 24
Finished Jul 05 05:38:10 PM PDT 24
Peak memory 199212 kb
Host smart-a62126ae-399a-4e41-a651-75bd68112341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775219390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2775219390
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2108280477
Short name T940
Test name
Test status
Simulation time 19945931265 ps
CPU time 867.15 seconds
Started Jul 05 05:37:24 PM PDT 24
Finished Jul 05 05:51:52 PM PDT 24
Peak memory 200008 kb
Host smart-8045d406-6ead-4aa8-8da2-5e4ba2410007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108280477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2108280477
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1350199684
Short name T647
Test name
Test status
Simulation time 5399621671 ps
CPU time 42.59 seconds
Started Jul 05 05:37:31 PM PDT 24
Finished Jul 05 05:38:15 PM PDT 24
Peak memory 198216 kb
Host smart-1d4931a0-9391-4006-88e0-1b914268d924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350199684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1350199684
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1974905808
Short name T819
Test name
Test status
Simulation time 132793383965 ps
CPU time 35.49 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:38:04 PM PDT 24
Peak memory 199324 kb
Host smart-278ceda9-5fab-44f3-8b64-c264241abfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974905808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1974905808
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.995573060
Short name T412
Test name
Test status
Simulation time 33668446105 ps
CPU time 13.27 seconds
Started Jul 05 05:37:32 PM PDT 24
Finished Jul 05 05:37:47 PM PDT 24
Peak memory 196088 kb
Host smart-ca20dedf-3810-4745-a6a7-2555f24e30ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995573060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.995573060
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2863954907
Short name T796
Test name
Test status
Simulation time 292005093 ps
CPU time 1.17 seconds
Started Jul 05 05:37:24 PM PDT 24
Finished Jul 05 05:37:27 PM PDT 24
Peak memory 198328 kb
Host smart-3761fd5a-3d70-48cb-9238-c02132daf2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863954907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2863954907
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1210092941
Short name T749
Test name
Test status
Simulation time 321771308971 ps
CPU time 1336.43 seconds
Started Jul 05 05:37:24 PM PDT 24
Finished Jul 05 05:59:42 PM PDT 24
Peak memory 208380 kb
Host smart-a2fb2ea9-acc4-42ec-afdc-d305269b5c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210092941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1210092941
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2359347024
Short name T865
Test name
Test status
Simulation time 1986442162 ps
CPU time 2.57 seconds
Started Jul 05 05:37:29 PM PDT 24
Finished Jul 05 05:37:33 PM PDT 24
Peak memory 198796 kb
Host smart-b47e350f-70ef-44f4-849c-e49fb99a475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359347024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2359347024
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.999123928
Short name T508
Test name
Test status
Simulation time 312458650 ps
CPU time 1.09 seconds
Started Jul 05 05:37:24 PM PDT 24
Finished Jul 05 05:37:26 PM PDT 24
Peak memory 196540 kb
Host smart-2deb2a55-d942-4535-a65d-6a8de9ec4fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999123928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.999123928
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1720049936
Short name T132
Test name
Test status
Simulation time 40426537147 ps
CPU time 76.85 seconds
Started Jul 05 05:40:15 PM PDT 24
Finished Jul 05 05:41:32 PM PDT 24
Peak memory 199924 kb
Host smart-f1fad00b-6a29-430e-b35a-cf736f417b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720049936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1720049936
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1561288027
Short name T995
Test name
Test status
Simulation time 442997635409 ps
CPU time 160.47 seconds
Started Jul 05 05:40:15 PM PDT 24
Finished Jul 05 05:42:56 PM PDT 24
Peak memory 199896 kb
Host smart-4be1bdf6-f248-40cb-bd2a-398b6118d0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561288027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1561288027
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3454332626
Short name T404
Test name
Test status
Simulation time 31729552008 ps
CPU time 17.35 seconds
Started Jul 05 05:40:12 PM PDT 24
Finished Jul 05 05:40:30 PM PDT 24
Peak memory 199928 kb
Host smart-6676791b-eba0-4167-87a4-8f95397d5510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454332626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3454332626
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.4197166298
Short name T561
Test name
Test status
Simulation time 69300408212 ps
CPU time 14.11 seconds
Started Jul 05 05:40:10 PM PDT 24
Finished Jul 05 05:40:25 PM PDT 24
Peak memory 199964 kb
Host smart-80e98d2f-fe23-46cf-9234-24d98a098107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197166298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4197166298
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.515051433
Short name T768
Test name
Test status
Simulation time 104570954192 ps
CPU time 156.06 seconds
Started Jul 05 05:40:14 PM PDT 24
Finished Jul 05 05:42:50 PM PDT 24
Peak memory 199904 kb
Host smart-bd26985b-b5db-4bc1-bdd1-9ff9db20fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515051433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.515051433
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.4241883758
Short name T834
Test name
Test status
Simulation time 63094729520 ps
CPU time 38.78 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:40:52 PM PDT 24
Peak memory 199992 kb
Host smart-2e5d3f63-b903-4c5d-9503-d639a0aaaece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241883758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.4241883758
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3438340006
Short name T850
Test name
Test status
Simulation time 54008805658 ps
CPU time 76.66 seconds
Started Jul 05 05:40:10 PM PDT 24
Finished Jul 05 05:41:27 PM PDT 24
Peak memory 199720 kb
Host smart-fc5db282-2678-4382-a734-a610a1cd2654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438340006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3438340006
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1150095054
Short name T10
Test name
Test status
Simulation time 8235211926 ps
CPU time 15.01 seconds
Started Jul 05 05:40:12 PM PDT 24
Finished Jul 05 05:40:28 PM PDT 24
Peak memory 199900 kb
Host smart-4472f712-6344-4a6a-a9e5-5518e9d3e2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150095054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1150095054
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.228339611
Short name T614
Test name
Test status
Simulation time 243938218701 ps
CPU time 24.59 seconds
Started Jul 05 05:40:12 PM PDT 24
Finished Jul 05 05:40:38 PM PDT 24
Peak memory 199964 kb
Host smart-f75d49a4-92e1-4a5d-b773-352c6642c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228339611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.228339611
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.314569527
Short name T183
Test name
Test status
Simulation time 69849018105 ps
CPU time 23.07 seconds
Started Jul 05 05:40:12 PM PDT 24
Finished Jul 05 05:40:36 PM PDT 24
Peak memory 199944 kb
Host smart-bd7d057c-5e82-492a-894b-180805500d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314569527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.314569527
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1873810880
Short name T472
Test name
Test status
Simulation time 15205066 ps
CPU time 0.54 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:37:27 PM PDT 24
Peak memory 195320 kb
Host smart-dd948c88-1fcf-485f-9cbe-17d8244ab012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873810880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1873810880
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2481424207
Short name T415
Test name
Test status
Simulation time 47647774708 ps
CPU time 77.07 seconds
Started Jul 05 05:37:32 PM PDT 24
Finished Jul 05 05:38:50 PM PDT 24
Peak memory 199928 kb
Host smart-a280b3b0-0b4f-4936-ae45-a5fc48d204f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481424207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2481424207
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3786998264
Short name T121
Test name
Test status
Simulation time 28155768698 ps
CPU time 22.36 seconds
Started Jul 05 05:37:29 PM PDT 24
Finished Jul 05 05:37:53 PM PDT 24
Peak memory 199208 kb
Host smart-b5e7ae0b-ac5a-437c-b2d9-08874d8c5d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786998264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3786998264
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.2308229767
Short name T753
Test name
Test status
Simulation time 39780934143 ps
CPU time 18.29 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:37:46 PM PDT 24
Peak memory 199960 kb
Host smart-c8ecffbc-283b-4d2c-8bf0-5821f4e00d0e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308229767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2308229767
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.4120929394
Short name T424
Test name
Test status
Simulation time 49211070384 ps
CPU time 429.46 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:44:38 PM PDT 24
Peak memory 199984 kb
Host smart-75e9382b-e60e-4343-b527-5f13d9c76fc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4120929394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.4120929394
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.4284890302
Short name T467
Test name
Test status
Simulation time 2007290147 ps
CPU time 2.01 seconds
Started Jul 05 05:37:35 PM PDT 24
Finished Jul 05 05:37:37 PM PDT 24
Peak memory 198608 kb
Host smart-9edb2f46-db6a-4c7b-9ccb-72bf38ccb037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284890302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4284890302
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2754012977
Short name T495
Test name
Test status
Simulation time 91241304890 ps
CPU time 45.24 seconds
Started Jul 05 05:37:35 PM PDT 24
Finished Jul 05 05:38:22 PM PDT 24
Peak memory 200164 kb
Host smart-6ec9cca2-91dc-4a81-8b19-0e4a83e784fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754012977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2754012977
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2443846851
Short name T9
Test name
Test status
Simulation time 26572606403 ps
CPU time 359.34 seconds
Started Jul 05 05:37:35 PM PDT 24
Finished Jul 05 05:43:36 PM PDT 24
Peak memory 200008 kb
Host smart-d6a962de-5cb1-4868-86d6-625714f274ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2443846851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2443846851
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2839049473
Short name T717
Test name
Test status
Simulation time 6774554322 ps
CPU time 9.06 seconds
Started Jul 05 05:37:30 PM PDT 24
Finished Jul 05 05:37:40 PM PDT 24
Peak memory 198208 kb
Host smart-8abf930c-15b7-4c61-8c73-96b3d6612fe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839049473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2839049473
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2424599568
Short name T562
Test name
Test status
Simulation time 77633486857 ps
CPU time 125.31 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:39:43 PM PDT 24
Peak memory 199896 kb
Host smart-70ccf267-d190-478f-bec7-e3ba670fadbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424599568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2424599568
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2345304792
Short name T256
Test name
Test status
Simulation time 3047402183 ps
CPU time 4.85 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:37:42 PM PDT 24
Peak memory 196476 kb
Host smart-f6c06360-4982-409b-a4c9-3795844de231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345304792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2345304792
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.228548128
Short name T585
Test name
Test status
Simulation time 701020479 ps
CPU time 3.42 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:37:31 PM PDT 24
Peak memory 198852 kb
Host smart-235cf453-7861-49e1-83d1-a27a9b49eeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228548128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.228548128
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3788902970
Short name T1021
Test name
Test status
Simulation time 256492286491 ps
CPU time 625.55 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:47:53 PM PDT 24
Peak memory 208376 kb
Host smart-3bb8a887-0070-411a-ae56-e2135966fe59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788902970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3788902970
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.705919133
Short name T1153
Test name
Test status
Simulation time 67432311400 ps
CPU time 731.53 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 05:49:46 PM PDT 24
Peak memory 216448 kb
Host smart-3554b68b-34ca-4c0f-8fa4-2e8a2e936a53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705919133 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.705919133
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2456929931
Short name T552
Test name
Test status
Simulation time 401966698 ps
CPU time 1.22 seconds
Started Jul 05 05:37:35 PM PDT 24
Finished Jul 05 05:37:37 PM PDT 24
Peak memory 198404 kb
Host smart-234994d6-26e9-469a-a7dc-4ad3e183feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456929931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2456929931
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.164511103
Short name T694
Test name
Test status
Simulation time 94255315880 ps
CPU time 70.72 seconds
Started Jul 05 05:37:27 PM PDT 24
Finished Jul 05 05:38:40 PM PDT 24
Peak memory 199988 kb
Host smart-c6e76d3d-9595-4ec6-90b6-f87856bcc1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164511103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.164511103
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2162481614
Short name T1154
Test name
Test status
Simulation time 9264369119 ps
CPU time 13.98 seconds
Started Jul 05 05:40:15 PM PDT 24
Finished Jul 05 05:40:29 PM PDT 24
Peak memory 199952 kb
Host smart-79cbc60c-ca6b-47d6-bb0a-1726a84e184c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162481614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2162481614
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.192532239
Short name T284
Test name
Test status
Simulation time 45178818658 ps
CPU time 17.87 seconds
Started Jul 05 05:40:14 PM PDT 24
Finished Jul 05 05:40:32 PM PDT 24
Peak memory 199940 kb
Host smart-283f65ba-9267-46b3-9258-b5960144c438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192532239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.192532239
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2527583943
Short name T578
Test name
Test status
Simulation time 22230142281 ps
CPU time 9.43 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:40:23 PM PDT 24
Peak memory 199904 kb
Host smart-3ca67009-dc6d-431c-9299-a649407716ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527583943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2527583943
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2291314209
Short name T462
Test name
Test status
Simulation time 89699040266 ps
CPU time 474.91 seconds
Started Jul 05 05:40:14 PM PDT 24
Finished Jul 05 05:48:09 PM PDT 24
Peak memory 199836 kb
Host smart-3862a017-0f91-4557-b955-059445a8decb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291314209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2291314209
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1686447425
Short name T851
Test name
Test status
Simulation time 39375359248 ps
CPU time 14.87 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:40:29 PM PDT 24
Peak memory 199544 kb
Host smart-189237cd-3f65-4487-a358-079de40c4021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686447425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1686447425
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3996597107
Short name T1114
Test name
Test status
Simulation time 113152457628 ps
CPU time 38.84 seconds
Started Jul 05 05:40:12 PM PDT 24
Finished Jul 05 05:40:51 PM PDT 24
Peak memory 200000 kb
Host smart-092c8981-d267-4946-a20d-5ba3e5976c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996597107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3996597107
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2992310658
Short name T1124
Test name
Test status
Simulation time 9782774490 ps
CPU time 15.3 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:40:29 PM PDT 24
Peak memory 199992 kb
Host smart-6344a300-0692-4ede-8141-fb57ff89ef31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992310658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2992310658
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.646274021
Short name T676
Test name
Test status
Simulation time 69278744046 ps
CPU time 25.73 seconds
Started Jul 05 05:40:12 PM PDT 24
Finished Jul 05 05:40:38 PM PDT 24
Peak memory 199960 kb
Host smart-d5ac1520-50c4-4c4e-a8ba-d756653b9a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646274021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.646274021
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2774274561
Short name T374
Test name
Test status
Simulation time 25562182102 ps
CPU time 10.45 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:40:24 PM PDT 24
Peak memory 197920 kb
Host smart-0d23ca01-d64e-4c1f-b683-16bedc75baab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774274561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2774274561
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2694454184
Short name T803
Test name
Test status
Simulation time 16572335 ps
CPU time 0.55 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:37:28 PM PDT 24
Peak memory 195328 kb
Host smart-8e2bbcad-2bd0-434b-b69f-0b7637bbc630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694454184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2694454184
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2003131713
Short name T939
Test name
Test status
Simulation time 37257731211 ps
CPU time 70.56 seconds
Started Jul 05 05:37:27 PM PDT 24
Finished Jul 05 05:38:39 PM PDT 24
Peak memory 199968 kb
Host smart-5a032687-d9e8-4971-9857-d81a41e831a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003131713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2003131713
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3473387851
Short name T1172
Test name
Test status
Simulation time 180324805291 ps
CPU time 329.27 seconds
Started Jul 05 05:37:31 PM PDT 24
Finished Jul 05 05:43:01 PM PDT 24
Peak memory 200004 kb
Host smart-2f6a6bc9-c862-471f-b249-1ce5cd556392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473387851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3473387851
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2680453978
Short name T1162
Test name
Test status
Simulation time 24458823591 ps
CPU time 37.22 seconds
Started Jul 05 05:37:31 PM PDT 24
Finished Jul 05 05:38:10 PM PDT 24
Peak memory 199940 kb
Host smart-d2f82ae9-4a94-40ae-8868-a4ff367eb737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680453978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2680453978
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.4035594981
Short name T781
Test name
Test status
Simulation time 60527577616 ps
CPU time 87.22 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 05:39:01 PM PDT 24
Peak memory 199936 kb
Host smart-70c49694-2ec9-4cec-87de-5332dec721bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035594981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.4035594981
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.712820626
Short name T727
Test name
Test status
Simulation time 188664902808 ps
CPU time 177.37 seconds
Started Jul 05 05:37:37 PM PDT 24
Finished Jul 05 05:40:36 PM PDT 24
Peak memory 199908 kb
Host smart-c37a9d3f-64a1-4fed-a874-8995af3d7cc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712820626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.712820626
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.780756832
Short name T355
Test name
Test status
Simulation time 8531002200 ps
CPU time 9.22 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:37:47 PM PDT 24
Peak memory 199408 kb
Host smart-48cfa6e7-7898-47bb-9139-a7746d997976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780756832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.780756832
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3131274232
Short name T291
Test name
Test status
Simulation time 37162670103 ps
CPU time 14.02 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:37:52 PM PDT 24
Peak memory 196264 kb
Host smart-a4749450-8800-4664-90fa-e7c940432db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131274232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3131274232
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3125629263
Short name T828
Test name
Test status
Simulation time 16190640756 ps
CPU time 353.93 seconds
Started Jul 05 05:37:39 PM PDT 24
Finished Jul 05 05:43:35 PM PDT 24
Peak memory 200020 kb
Host smart-96d5a200-0a79-4bc1-ae4e-a0bce5997782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125629263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3125629263
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.908552177
Short name T335
Test name
Test status
Simulation time 5165540898 ps
CPU time 33.96 seconds
Started Jul 05 05:37:32 PM PDT 24
Finished Jul 05 05:38:07 PM PDT 24
Peak memory 198948 kb
Host smart-d07870d7-5913-48cd-919a-6c5b8c6289f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908552177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.908552177
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3821035840
Short name T876
Test name
Test status
Simulation time 21550087171 ps
CPU time 21.71 seconds
Started Jul 05 05:37:30 PM PDT 24
Finished Jul 05 05:37:53 PM PDT 24
Peak memory 199964 kb
Host smart-445d0821-5e76-44a0-9a7c-d08ffbd88eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821035840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3821035840
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2038910463
Short name T1003
Test name
Test status
Simulation time 4392392473 ps
CPU time 6.84 seconds
Started Jul 05 05:37:30 PM PDT 24
Finished Jul 05 05:37:38 PM PDT 24
Peak memory 196256 kb
Host smart-2481c17f-e7b9-4e75-8da1-3d648de3ec87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038910463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2038910463
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2735776075
Short name T1103
Test name
Test status
Simulation time 5388513926 ps
CPU time 16.37 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:37:43 PM PDT 24
Peak memory 199960 kb
Host smart-78371c6f-14e6-49c3-9329-8cf0922a5be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735776075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2735776075
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2041452440
Short name T248
Test name
Test status
Simulation time 150608384070 ps
CPU time 378.09 seconds
Started Jul 05 05:37:32 PM PDT 24
Finished Jul 05 05:43:52 PM PDT 24
Peak memory 216468 kb
Host smart-2cfd57c2-f956-4a25-8bb6-ba84fb3549aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041452440 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2041452440
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3444435606
Short name T506
Test name
Test status
Simulation time 760252551 ps
CPU time 2.16 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:37:31 PM PDT 24
Peak memory 198640 kb
Host smart-78996c27-8b71-445a-9e48-7d9f36d6109f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444435606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3444435606
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3421544352
Short name T482
Test name
Test status
Simulation time 15462317353 ps
CPU time 24.98 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:37:51 PM PDT 24
Peak memory 199664 kb
Host smart-0deca155-6821-47c0-ba95-af6850e1c146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421544352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3421544352
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1457776264
Short name T713
Test name
Test status
Simulation time 14989289137 ps
CPU time 38.57 seconds
Started Jul 05 05:40:12 PM PDT 24
Finished Jul 05 05:40:51 PM PDT 24
Peak memory 199992 kb
Host smart-d8939758-0685-447d-81b3-619b05ccdc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457776264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1457776264
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2845641579
Short name T560
Test name
Test status
Simulation time 31184875463 ps
CPU time 84.14 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:41:38 PM PDT 24
Peak memory 199864 kb
Host smart-02825422-6013-4913-aaed-e1b003d84802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845641579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2845641579
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1245120077
Short name T475
Test name
Test status
Simulation time 29381691384 ps
CPU time 49.58 seconds
Started Jul 05 05:40:12 PM PDT 24
Finished Jul 05 05:41:03 PM PDT 24
Peak memory 199980 kb
Host smart-59ae4e76-b696-4381-a1c9-02d7befa0343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245120077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1245120077
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.4113029572
Short name T224
Test name
Test status
Simulation time 41134044752 ps
CPU time 32.51 seconds
Started Jul 05 05:40:13 PM PDT 24
Finished Jul 05 05:40:46 PM PDT 24
Peak memory 199992 kb
Host smart-ccca4f7a-bbf8-47a5-b3a0-5fcdd2019dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113029572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.4113029572
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2481248953
Short name T316
Test name
Test status
Simulation time 24252703228 ps
CPU time 50.8 seconds
Started Jul 05 05:40:19 PM PDT 24
Finished Jul 05 05:41:11 PM PDT 24
Peak memory 199996 kb
Host smart-3cda1f71-3d89-4ee8-8396-d1238226d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481248953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2481248953
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1149178151
Short name T785
Test name
Test status
Simulation time 22190571709 ps
CPU time 43.43 seconds
Started Jul 05 05:40:19 PM PDT 24
Finished Jul 05 05:41:02 PM PDT 24
Peak memory 199948 kb
Host smart-858f80f9-71f7-45af-b231-b8b5ed267ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149178151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1149178151
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1655995141
Short name T399
Test name
Test status
Simulation time 193974358806 ps
CPU time 48.59 seconds
Started Jul 05 05:40:18 PM PDT 24
Finished Jul 05 05:41:07 PM PDT 24
Peak memory 200012 kb
Host smart-9224c16c-72ba-4ae1-91d4-03c846e944d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655995141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1655995141
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.190127393
Short name T97
Test name
Test status
Simulation time 68089865 ps
CPU time 0.56 seconds
Started Jul 05 05:37:37 PM PDT 24
Finished Jul 05 05:37:40 PM PDT 24
Peak memory 195324 kb
Host smart-29fc4ba8-c642-4297-8ba1-b652e3f4a423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190127393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.190127393
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2848750675
Short name T447
Test name
Test status
Simulation time 54519526291 ps
CPU time 52.59 seconds
Started Jul 05 05:37:29 PM PDT 24
Finished Jul 05 05:38:23 PM PDT 24
Peak memory 199904 kb
Host smart-5fb773c4-3ee6-408a-8e22-0d664054bc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848750675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2848750675
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1842389788
Short name T527
Test name
Test status
Simulation time 20464961881 ps
CPU time 33.44 seconds
Started Jul 05 05:37:37 PM PDT 24
Finished Jul 05 05:38:12 PM PDT 24
Peak memory 199864 kb
Host smart-0bcf4caa-c0a3-4740-b1a5-4557f1412da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842389788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1842389788
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2941893555
Short name T194
Test name
Test status
Simulation time 33566288175 ps
CPU time 15.85 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:37:44 PM PDT 24
Peak memory 199992 kb
Host smart-0338111d-1e59-4dc4-9349-504d6441039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941893555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2941893555
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3503768592
Short name T107
Test name
Test status
Simulation time 19503381677 ps
CPU time 41.2 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 05:38:15 PM PDT 24
Peak memory 199944 kb
Host smart-073ad613-bb9d-4bd3-96cf-2707341dbb69
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503768592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3503768592
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1965946114
Short name T1082
Test name
Test status
Simulation time 209425912913 ps
CPU time 227.78 seconds
Started Jul 05 05:37:39 PM PDT 24
Finished Jul 05 05:41:28 PM PDT 24
Peak memory 199900 kb
Host smart-be64cf79-ac62-406c-99b5-8790d3ad4f03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965946114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1965946114
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.715880899
Short name T541
Test name
Test status
Simulation time 1462003640 ps
CPU time 1.13 seconds
Started Jul 05 05:37:29 PM PDT 24
Finished Jul 05 05:37:31 PM PDT 24
Peak memory 195596 kb
Host smart-274f4525-d2d0-42a4-a717-039cff72666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715880899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.715880899
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3745972711
Short name T307
Test name
Test status
Simulation time 30006109497 ps
CPU time 13.45 seconds
Started Jul 05 05:37:31 PM PDT 24
Finished Jul 05 05:37:46 PM PDT 24
Peak memory 196036 kb
Host smart-ede2808b-2ef1-4a6d-ac36-ddfc2bc6eb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745972711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3745972711
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3187188235
Short name T394
Test name
Test status
Simulation time 16787058461 ps
CPU time 195.86 seconds
Started Jul 05 05:37:32 PM PDT 24
Finished Jul 05 05:40:49 PM PDT 24
Peak memory 199956 kb
Host smart-ea43ae72-da67-4c22-b909-05847a9c7293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3187188235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3187188235
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2778420716
Short name T786
Test name
Test status
Simulation time 4556693904 ps
CPU time 9.04 seconds
Started Jul 05 05:37:31 PM PDT 24
Finished Jul 05 05:37:41 PM PDT 24
Peak memory 199428 kb
Host smart-f8e7eb91-f578-4db8-968f-9dfecf7133ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2778420716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2778420716
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.882034409
Short name T772
Test name
Test status
Simulation time 45790882805 ps
CPU time 69.83 seconds
Started Jul 05 05:37:30 PM PDT 24
Finished Jul 05 05:38:41 PM PDT 24
Peak memory 199928 kb
Host smart-4a6e0e69-02fd-4e03-8081-c5d30ae4cdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882034409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.882034409
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.4002124140
Short name T63
Test name
Test status
Simulation time 834735169 ps
CPU time 0.89 seconds
Started Jul 05 05:37:40 PM PDT 24
Finished Jul 05 05:37:42 PM PDT 24
Peak memory 195448 kb
Host smart-eb487da1-bd1a-4a24-8af9-393d84571290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002124140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4002124140
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1311785417
Short name T436
Test name
Test status
Simulation time 11061649772 ps
CPU time 16.36 seconds
Started Jul 05 05:37:42 PM PDT 24
Finished Jul 05 05:37:59 PM PDT 24
Peak memory 199812 kb
Host smart-816a694f-6ee1-4c5e-82b5-97707431e37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311785417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1311785417
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1834474567
Short name T99
Test name
Test status
Simulation time 28576378928 ps
CPU time 281.45 seconds
Started Jul 05 05:37:27 PM PDT 24
Finished Jul 05 05:42:10 PM PDT 24
Peak memory 216668 kb
Host smart-59a1a476-f2e9-4b74-958d-15b0fe2a2027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834474567 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1834474567
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2903217701
Short name T640
Test name
Test status
Simulation time 1492579637 ps
CPU time 1.74 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:37:29 PM PDT 24
Peak memory 199748 kb
Host smart-b73a971a-9d9a-4e3c-a20d-09f1bac16895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903217701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2903217701
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3248203948
Short name T606
Test name
Test status
Simulation time 80937434387 ps
CPU time 36.28 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:38:04 PM PDT 24
Peak memory 199936 kb
Host smart-0392d149-ba80-4c4d-96ba-7e808d5a7daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248203948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3248203948
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.620369913
Short name T188
Test name
Test status
Simulation time 57773601953 ps
CPU time 93.27 seconds
Started Jul 05 05:40:20 PM PDT 24
Finished Jul 05 05:41:54 PM PDT 24
Peak memory 199848 kb
Host smart-fa559d0c-3875-4252-a776-2173e6d9efac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620369913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.620369913
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.462074329
Short name T204
Test name
Test status
Simulation time 63400504065 ps
CPU time 25.46 seconds
Started Jul 05 05:40:19 PM PDT 24
Finished Jul 05 05:40:45 PM PDT 24
Peak memory 199908 kb
Host smart-077bf1b9-16a8-40ee-adca-ffb88068cc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462074329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.462074329
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.931277518
Short name T863
Test name
Test status
Simulation time 92716049351 ps
CPU time 82.96 seconds
Started Jul 05 05:40:23 PM PDT 24
Finished Jul 05 05:41:46 PM PDT 24
Peak memory 199872 kb
Host smart-2309a7ab-2aec-49c8-a2b7-244fd4bde4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931277518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.931277518
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1326242613
Short name T57
Test name
Test status
Simulation time 29710067873 ps
CPU time 48.83 seconds
Started Jul 05 05:40:20 PM PDT 24
Finished Jul 05 05:41:09 PM PDT 24
Peak memory 199908 kb
Host smart-f62e2322-0fc5-4430-9545-1d40ff5aa81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326242613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1326242613
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3815393262
Short name T770
Test name
Test status
Simulation time 165810948169 ps
CPU time 72.79 seconds
Started Jul 05 05:40:18 PM PDT 24
Finished Jul 05 05:41:32 PM PDT 24
Peak memory 199984 kb
Host smart-9156b2c0-fbcd-489d-a59d-0acf677e2871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815393262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3815393262
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1265235991
Short name T179
Test name
Test status
Simulation time 22438547779 ps
CPU time 10.85 seconds
Started Jul 05 05:40:21 PM PDT 24
Finished Jul 05 05:40:32 PM PDT 24
Peak memory 199920 kb
Host smart-8359faa6-f618-4056-911a-07ebbf98ce27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265235991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1265235991
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.4172279789
Short name T610
Test name
Test status
Simulation time 10875201 ps
CPU time 0.54 seconds
Started Jul 05 05:37:38 PM PDT 24
Finished Jul 05 05:37:40 PM PDT 24
Peak memory 194304 kb
Host smart-ae6733d7-78bc-4b80-a54e-0ba9456b996f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172279789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4172279789
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2840685622
Short name T1002
Test name
Test status
Simulation time 104059780352 ps
CPU time 39.09 seconds
Started Jul 05 05:37:34 PM PDT 24
Finished Jul 05 05:38:14 PM PDT 24
Peak memory 199960 kb
Host smart-18cf27ce-0ef4-4121-b596-27b4fe1859bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840685622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2840685622
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1997461828
Short name T535
Test name
Test status
Simulation time 20304447091 ps
CPU time 30.67 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 05:38:05 PM PDT 24
Peak memory 199692 kb
Host smart-ee68379b-d107-4c38-88c9-dfba2a643a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997461828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1997461828
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2648338874
Short name T191
Test name
Test status
Simulation time 20208897275 ps
CPU time 39.36 seconds
Started Jul 05 05:37:46 PM PDT 24
Finished Jul 05 05:38:26 PM PDT 24
Peak memory 200004 kb
Host smart-464ec981-e3fa-4750-98f5-aedfef9a5502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648338874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2648338874
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2720426052
Short name T488
Test name
Test status
Simulation time 13852419974 ps
CPU time 21.08 seconds
Started Jul 05 05:37:34 PM PDT 24
Finished Jul 05 05:37:56 PM PDT 24
Peak memory 197164 kb
Host smart-39ef03ef-4b53-41b0-a841-3acf144b489a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720426052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2720426052
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3855123695
Short name T409
Test name
Test status
Simulation time 80444200229 ps
CPU time 415.31 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 05:44:29 PM PDT 24
Peak memory 199952 kb
Host smart-3ca0af46-355f-47e8-b195-e606cdd46a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3855123695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3855123695
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2729290646
Short name T802
Test name
Test status
Simulation time 3197060130 ps
CPU time 2.29 seconds
Started Jul 05 05:37:37 PM PDT 24
Finished Jul 05 05:37:41 PM PDT 24
Peak memory 198540 kb
Host smart-6fc1d33b-a878-47a9-bd01-b067b04620da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729290646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2729290646
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2024413342
Short name T1133
Test name
Test status
Simulation time 49423310252 ps
CPU time 88.05 seconds
Started Jul 05 05:37:29 PM PDT 24
Finished Jul 05 05:38:58 PM PDT 24
Peak memory 200088 kb
Host smart-6482f58e-3874-41bd-be7c-06068fc1d71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024413342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2024413342
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.4086204451
Short name T958
Test name
Test status
Simulation time 21966782260 ps
CPU time 501.43 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:45:49 PM PDT 24
Peak memory 199904 kb
Host smart-cac2e561-5a99-41f0-a328-dad7f352f2bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086204451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.4086204451
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1390105651
Short name T1092
Test name
Test status
Simulation time 2131744737 ps
CPU time 4.88 seconds
Started Jul 05 05:37:32 PM PDT 24
Finished Jul 05 05:37:38 PM PDT 24
Peak memory 198220 kb
Host smart-ce61a33e-92c6-45b7-aa5d-d0baa8f43335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390105651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1390105651
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.4243010872
Short name T579
Test name
Test status
Simulation time 117649312802 ps
CPU time 174.41 seconds
Started Jul 05 05:37:29 PM PDT 24
Finished Jul 05 05:40:24 PM PDT 24
Peak memory 199904 kb
Host smart-9b16ba18-bff3-4b73-a7ac-a259a0675ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243010872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4243010872
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3862076331
Short name T739
Test name
Test status
Simulation time 2790539436 ps
CPU time 5.01 seconds
Started Jul 05 05:37:27 PM PDT 24
Finished Jul 05 05:37:34 PM PDT 24
Peak memory 196444 kb
Host smart-04b1ce05-1797-49ef-999e-2d07809b1133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862076331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3862076331
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.932001061
Short name T711
Test name
Test status
Simulation time 5384059154 ps
CPU time 18.43 seconds
Started Jul 05 05:37:31 PM PDT 24
Finished Jul 05 05:37:51 PM PDT 24
Peak memory 199204 kb
Host smart-1928e1c3-3abb-49b3-a001-1efd2cc878c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932001061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.932001061
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3754601564
Short name T1158
Test name
Test status
Simulation time 22082055295 ps
CPU time 45.9 seconds
Started Jul 05 05:37:32 PM PDT 24
Finished Jul 05 05:38:20 PM PDT 24
Peak memory 199892 kb
Host smart-d573eb50-257b-45df-ba62-1a8d12308cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754601564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3754601564
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3334504060
Short name T346
Test name
Test status
Simulation time 6887751872 ps
CPU time 22.58 seconds
Started Jul 05 05:37:28 PM PDT 24
Finished Jul 05 05:37:52 PM PDT 24
Peak memory 199948 kb
Host smart-ebc61c21-15de-4726-bc3a-aaa85eb50135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334504060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3334504060
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.710136696
Short name T703
Test name
Test status
Simulation time 28058442116 ps
CPU time 46.91 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:38:15 PM PDT 24
Peak memory 199924 kb
Host smart-865cec75-f58a-46a7-957c-90c274e3cb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710136696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.710136696
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2301759801
Short name T544
Test name
Test status
Simulation time 4093853081 ps
CPU time 8.2 seconds
Started Jul 05 05:40:20 PM PDT 24
Finished Jul 05 05:40:29 PM PDT 24
Peak memory 199920 kb
Host smart-1a9e2738-1248-48e1-a5e9-669dabfa4f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301759801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2301759801
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1338469532
Short name T473
Test name
Test status
Simulation time 29223408821 ps
CPU time 26.19 seconds
Started Jul 05 05:40:18 PM PDT 24
Finished Jul 05 05:40:45 PM PDT 24
Peak memory 199928 kb
Host smart-890937c8-4b49-4e52-9749-39aaf0c77aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338469532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1338469532
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.284090561
Short name T1081
Test name
Test status
Simulation time 32860055979 ps
CPU time 20.33 seconds
Started Jul 05 05:40:20 PM PDT 24
Finished Jul 05 05:40:40 PM PDT 24
Peak memory 199948 kb
Host smart-95881355-6285-4d5a-9abb-c2fcb89c8680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284090561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.284090561
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.845919354
Short name T1165
Test name
Test status
Simulation time 72272980959 ps
CPU time 112.82 seconds
Started Jul 05 05:40:19 PM PDT 24
Finished Jul 05 05:42:13 PM PDT 24
Peak memory 199608 kb
Host smart-131117af-96a1-43a2-8558-3dcccae6a6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845919354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.845919354
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2464195515
Short name T290
Test name
Test status
Simulation time 110356092765 ps
CPU time 191.95 seconds
Started Jul 05 05:40:20 PM PDT 24
Finished Jul 05 05:43:33 PM PDT 24
Peak memory 199956 kb
Host smart-366aece2-54fb-447b-ad9e-ccbd7adf0130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464195515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2464195515
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2473211194
Short name T710
Test name
Test status
Simulation time 37024483904 ps
CPU time 19.65 seconds
Started Jul 05 05:40:19 PM PDT 24
Finished Jul 05 05:40:39 PM PDT 24
Peak memory 199944 kb
Host smart-c7746b98-228f-4058-8225-5a24e17103e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473211194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2473211194
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2529713319
Short name T433
Test name
Test status
Simulation time 195440486724 ps
CPU time 22.75 seconds
Started Jul 05 05:40:20 PM PDT 24
Finished Jul 05 05:40:44 PM PDT 24
Peak memory 199820 kb
Host smart-e50dd08b-dc5d-49e8-9d21-2e4af84c0cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529713319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2529713319
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2071032564
Short name T190
Test name
Test status
Simulation time 58686166926 ps
CPU time 31.23 seconds
Started Jul 05 05:40:18 PM PDT 24
Finished Jul 05 05:40:49 PM PDT 24
Peak memory 199960 kb
Host smart-db9b4019-16ad-41a1-8bb3-37cf3375739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071032564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2071032564
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.4084441470
Short name T360
Test name
Test status
Simulation time 27251597 ps
CPU time 0.55 seconds
Started Jul 05 05:37:37 PM PDT 24
Finished Jul 05 05:37:39 PM PDT 24
Peak memory 195252 kb
Host smart-7b8eeabe-c07a-478f-8413-96fbf9f55738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084441470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.4084441470
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2508860304
Short name T77
Test name
Test status
Simulation time 19522159848 ps
CPU time 39.04 seconds
Started Jul 05 05:37:29 PM PDT 24
Finished Jul 05 05:38:09 PM PDT 24
Peak memory 199928 kb
Host smart-98e6d89d-12e0-444e-9bfc-3eb4ba24b907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508860304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2508860304
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3473275939
Short name T1178
Test name
Test status
Simulation time 113637201443 ps
CPU time 67.62 seconds
Started Jul 05 05:37:38 PM PDT 24
Finished Jul 05 05:38:47 PM PDT 24
Peak memory 199904 kb
Host smart-1706a3e3-77c5-4da8-8572-7ef21f961e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473275939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3473275939
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.293251915
Short name T1100
Test name
Test status
Simulation time 48286738122 ps
CPU time 39.03 seconds
Started Jul 05 05:37:34 PM PDT 24
Finished Jul 05 05:38:14 PM PDT 24
Peak memory 199864 kb
Host smart-1a081b7a-7656-4d20-8f13-679f8e467fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293251915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.293251915
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2451541380
Short name T1150
Test name
Test status
Simulation time 34793552609 ps
CPU time 52.35 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:38:30 PM PDT 24
Peak memory 199532 kb
Host smart-9487f0be-2223-448f-a8d5-2a74d7223eed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451541380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2451541380
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3134224184
Short name T1116
Test name
Test status
Simulation time 31212301449 ps
CPU time 245.63 seconds
Started Jul 05 05:37:39 PM PDT 24
Finished Jul 05 05:41:46 PM PDT 24
Peak memory 199968 kb
Host smart-d576d59d-bcc1-4fb1-9725-8ffd848a9774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134224184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3134224184
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1658656003
Short name T692
Test name
Test status
Simulation time 4748934919 ps
CPU time 8.72 seconds
Started Jul 05 05:37:39 PM PDT 24
Finished Jul 05 05:37:49 PM PDT 24
Peak memory 199932 kb
Host smart-9f76948b-5bb4-4729-806a-66bbdee8bec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658656003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1658656003
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3484049804
Short name T536
Test name
Test status
Simulation time 34563561268 ps
CPU time 15.76 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:37:53 PM PDT 24
Peak memory 198132 kb
Host smart-233af121-498c-42ed-aab1-dadb933bfe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484049804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3484049804
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1213479173
Short name T852
Test name
Test status
Simulation time 34636510682 ps
CPU time 997.45 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:54:16 PM PDT 24
Peak memory 199924 kb
Host smart-50c814de-b6de-47fd-9b37-7c2e2d8418de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1213479173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1213479173
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.644714301
Short name T1069
Test name
Test status
Simulation time 3588985351 ps
CPU time 7.27 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:37:44 PM PDT 24
Peak memory 198044 kb
Host smart-11f1d1e8-f6ef-45b9-8cb1-103bf41411b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=644714301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.644714301
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.206930968
Short name T793
Test name
Test status
Simulation time 27711338510 ps
CPU time 48.66 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:38:45 PM PDT 24
Peak memory 199928 kb
Host smart-7484c1e0-65e4-42fd-9173-e9a384300d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206930968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.206930968
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2558437484
Short name T454
Test name
Test status
Simulation time 2451235196 ps
CPU time 1.5 seconds
Started Jul 05 05:37:42 PM PDT 24
Finished Jul 05 05:37:44 PM PDT 24
Peak memory 195956 kb
Host smart-500c5d81-2a79-4136-a2aa-65eadbd03056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558437484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2558437484
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1219408216
Short name T1065
Test name
Test status
Simulation time 512351547 ps
CPU time 1.94 seconds
Started Jul 05 05:37:35 PM PDT 24
Finished Jul 05 05:37:38 PM PDT 24
Peak memory 198332 kb
Host smart-feb966d6-7a5e-4f2e-8044-a89b5408db0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219408216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1219408216
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.747604911
Short name T214
Test name
Test status
Simulation time 395914941327 ps
CPU time 275.22 seconds
Started Jul 05 05:37:42 PM PDT 24
Finished Jul 05 05:42:18 PM PDT 24
Peak memory 199924 kb
Host smart-2524c17f-8349-40c3-a47c-4664946ff9fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747604911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.747604911
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1156912100
Short name T780
Test name
Test status
Simulation time 6713337365 ps
CPU time 18.24 seconds
Started Jul 05 05:37:34 PM PDT 24
Finished Jul 05 05:37:53 PM PDT 24
Peak memory 199636 kb
Host smart-27ac79c0-2fde-48d8-9ab1-2a0bd3919f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156912100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1156912100
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.177753431
Short name T449
Test name
Test status
Simulation time 245044089573 ps
CPU time 139.63 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 05:39:54 PM PDT 24
Peak memory 199900 kb
Host smart-91f1d4d1-e5e7-4318-b13b-97aec3bd07dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177753431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.177753431
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1476882735
Short name T257
Test name
Test status
Simulation time 125480592940 ps
CPU time 183.82 seconds
Started Jul 05 05:40:23 PM PDT 24
Finished Jul 05 05:43:27 PM PDT 24
Peak memory 199908 kb
Host smart-2900f4a4-364b-4d57-937d-3b296e4cee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476882735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1476882735
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3401433403
Short name T593
Test name
Test status
Simulation time 151609599276 ps
CPU time 110.21 seconds
Started Jul 05 05:40:20 PM PDT 24
Finished Jul 05 05:42:11 PM PDT 24
Peak memory 199848 kb
Host smart-d42c78e6-6839-47bf-b130-84f2dc1b04e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401433403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3401433403
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3015004203
Short name T1036
Test name
Test status
Simulation time 147604877892 ps
CPU time 227.81 seconds
Started Jul 05 05:40:27 PM PDT 24
Finished Jul 05 05:44:16 PM PDT 24
Peak memory 199860 kb
Host smart-a3999836-a9cb-4f39-b990-df7e8e8ace7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015004203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3015004203
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.22945993
Short name T309
Test name
Test status
Simulation time 33839013975 ps
CPU time 13.19 seconds
Started Jul 05 05:40:28 PM PDT 24
Finished Jul 05 05:40:42 PM PDT 24
Peak memory 199940 kb
Host smart-2bc96ef2-c91f-40d6-ba12-ea530727cd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22945993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.22945993
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2056109866
Short name T644
Test name
Test status
Simulation time 132039017427 ps
CPU time 243.43 seconds
Started Jul 05 05:40:31 PM PDT 24
Finished Jul 05 05:44:35 PM PDT 24
Peak memory 199812 kb
Host smart-37715498-9480-48b0-ba49-f3577913d5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056109866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2056109866
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3293623270
Short name T459
Test name
Test status
Simulation time 169874181402 ps
CPU time 76.59 seconds
Started Jul 05 05:40:30 PM PDT 24
Finished Jul 05 05:41:47 PM PDT 24
Peak memory 199852 kb
Host smart-7cac8ffa-1226-4d4e-80f4-ad9a8565bfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293623270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3293623270
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3615762278
Short name T1042
Test name
Test status
Simulation time 8852110577 ps
CPU time 15.52 seconds
Started Jul 05 05:40:29 PM PDT 24
Finished Jul 05 05:40:46 PM PDT 24
Peak memory 199816 kb
Host smart-f4b2cc5b-e900-4594-9ae7-b8e220ce8cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615762278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3615762278
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1240199210
Short name T1155
Test name
Test status
Simulation time 19668457706 ps
CPU time 30.47 seconds
Started Jul 05 05:40:29 PM PDT 24
Finished Jul 05 05:41:00 PM PDT 24
Peak memory 199824 kb
Host smart-f4311959-f39c-4bb2-88a5-f5c1cd784fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240199210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1240199210
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.176413204
Short name T186
Test name
Test status
Simulation time 21731083913 ps
CPU time 58.96 seconds
Started Jul 05 05:40:29 PM PDT 24
Finished Jul 05 05:41:29 PM PDT 24
Peak memory 199928 kb
Host smart-31d873e0-e66b-4a5f-ad29-7de5145ee976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176413204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.176413204
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2132380483
Short name T24
Test name
Test status
Simulation time 41029450 ps
CPU time 0.54 seconds
Started Jul 05 05:37:49 PM PDT 24
Finished Jul 05 05:37:50 PM PDT 24
Peak memory 195328 kb
Host smart-bd01ff02-20e8-43a3-ac15-0d399570260c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132380483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2132380483
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.4069787908
Short name T628
Test name
Test status
Simulation time 64233855125 ps
CPU time 51.05 seconds
Started Jul 05 05:37:49 PM PDT 24
Finished Jul 05 05:38:41 PM PDT 24
Peak memory 199892 kb
Host smart-d674984c-014c-46b8-b6c1-1c76776a099a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069787908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.4069787908
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3009137752
Short name T1004
Test name
Test status
Simulation time 16637842292 ps
CPU time 21.99 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:38:00 PM PDT 24
Peak memory 198524 kb
Host smart-99adee3a-14de-4a06-8ca7-6f02103d0ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009137752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3009137752
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3821916928
Short name T155
Test name
Test status
Simulation time 170861551148 ps
CPU time 402.4 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:44:21 PM PDT 24
Peak memory 199928 kb
Host smart-32b8c946-3101-4555-859e-472bf41bb080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821916928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3821916928
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2729559279
Short name T912
Test name
Test status
Simulation time 28841170512 ps
CPU time 54.5 seconds
Started Jul 05 05:37:43 PM PDT 24
Finished Jul 05 05:38:38 PM PDT 24
Peak memory 199940 kb
Host smart-b70f80a5-b0b7-4eb7-ba5d-70ca6f61c7b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729559279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2729559279
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.226883826
Short name T464
Test name
Test status
Simulation time 63971101070 ps
CPU time 160.17 seconds
Started Jul 05 05:37:56 PM PDT 24
Finished Jul 05 05:40:38 PM PDT 24
Peak memory 199896 kb
Host smart-6972a52a-cc58-4969-a7a8-acbdcac72fc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=226883826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.226883826
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.53891626
Short name T509
Test name
Test status
Simulation time 3673516720 ps
CPU time 12.67 seconds
Started Jul 05 05:37:50 PM PDT 24
Finished Jul 05 05:38:03 PM PDT 24
Peak memory 198880 kb
Host smart-56bc9986-ea03-43bf-a4aa-20d59a0d1ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53891626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.53891626
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2164009816
Short name T556
Test name
Test status
Simulation time 74447395006 ps
CPU time 121.58 seconds
Started Jul 05 05:37:46 PM PDT 24
Finished Jul 05 05:39:48 PM PDT 24
Peak memory 200128 kb
Host smart-522e07b9-3b33-4c59-b699-1c68f39f35dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164009816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2164009816
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3561746978
Short name T806
Test name
Test status
Simulation time 21441558762 ps
CPU time 271.06 seconds
Started Jul 05 05:37:52 PM PDT 24
Finished Jul 05 05:42:23 PM PDT 24
Peak memory 199996 kb
Host smart-00a50b88-cce5-448d-a189-5e1bc45f5e77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561746978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3561746978
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.429838881
Short name T602
Test name
Test status
Simulation time 1693436674 ps
CPU time 8.93 seconds
Started Jul 05 05:40:01 PM PDT 24
Finished Jul 05 05:40:10 PM PDT 24
Peak memory 198072 kb
Host smart-b2a9b465-27c3-4fb3-a94c-fdd9c38df779
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429838881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.429838881
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3272422099
Short name T998
Test name
Test status
Simulation time 84187874039 ps
CPU time 142.38 seconds
Started Jul 05 05:37:37 PM PDT 24
Finished Jul 05 05:40:02 PM PDT 24
Peak memory 199960 kb
Host smart-605e6558-a317-46f1-a516-f630739d97cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272422099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3272422099
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.859931950
Short name T656
Test name
Test status
Simulation time 3626524142 ps
CPU time 3.41 seconds
Started Jul 05 05:37:50 PM PDT 24
Finished Jul 05 05:37:54 PM PDT 24
Peak memory 196132 kb
Host smart-50035cab-a546-4495-923f-65b9e0f95853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859931950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.859931950
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1061650212
Short name T603
Test name
Test status
Simulation time 625131456 ps
CPU time 3.24 seconds
Started Jul 05 05:37:39 PM PDT 24
Finished Jul 05 05:37:44 PM PDT 24
Peak memory 198632 kb
Host smart-0f8dfb29-8cbb-41af-bf8f-803ba5072fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061650212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1061650212
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3906586056
Short name T994
Test name
Test status
Simulation time 141579221334 ps
CPU time 92.72 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:39:11 PM PDT 24
Peak memory 199976 kb
Host smart-feae29f5-65b6-4445-9486-43adb94b02a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906586056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3906586056
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2070305214
Short name T966
Test name
Test status
Simulation time 152465764903 ps
CPU time 932.09 seconds
Started Jul 05 05:37:46 PM PDT 24
Finished Jul 05 05:53:19 PM PDT 24
Peak memory 225912 kb
Host smart-41032506-a2e0-4ab9-8ddb-d5017d4c180c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070305214 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2070305214
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1993049280
Short name T392
Test name
Test status
Simulation time 2565101859 ps
CPU time 1.79 seconds
Started Jul 05 05:37:38 PM PDT 24
Finished Jul 05 05:37:42 PM PDT 24
Peak memory 198816 kb
Host smart-46ec763a-43b5-429a-b6fc-f1d6dc70f875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993049280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1993049280
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2141409860
Short name T1026
Test name
Test status
Simulation time 50659472919 ps
CPU time 72.77 seconds
Started Jul 05 05:37:41 PM PDT 24
Finished Jul 05 05:38:55 PM PDT 24
Peak memory 199888 kb
Host smart-6f86967f-9011-43b2-8b4b-d10a5c3075ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141409860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2141409860
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.161234327
Short name T759
Test name
Test status
Simulation time 199437217345 ps
CPU time 398.06 seconds
Started Jul 05 05:40:27 PM PDT 24
Finished Jul 05 05:47:06 PM PDT 24
Peak memory 199944 kb
Host smart-9a85a553-a642-459e-bae4-8e94e010bdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161234327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.161234327
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3081088718
Short name T624
Test name
Test status
Simulation time 150305314158 ps
CPU time 204.27 seconds
Started Jul 05 05:40:27 PM PDT 24
Finished Jul 05 05:43:52 PM PDT 24
Peak memory 200008 kb
Host smart-22785d84-2cb5-42b8-bb6a-1947f429d222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081088718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3081088718
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1222470578
Short name T586
Test name
Test status
Simulation time 211576435746 ps
CPU time 335.41 seconds
Started Jul 05 05:40:28 PM PDT 24
Finished Jul 05 05:46:04 PM PDT 24
Peak memory 199992 kb
Host smart-665f58fd-9d64-4989-a33f-b0b0275fc199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222470578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1222470578
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3058887688
Short name T313
Test name
Test status
Simulation time 25239056078 ps
CPU time 21.06 seconds
Started Jul 05 05:40:29 PM PDT 24
Finished Jul 05 05:40:52 PM PDT 24
Peak memory 199896 kb
Host smart-8c0839af-84da-4921-849b-7310b76a2823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058887688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3058887688
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.4163880405
Short name T693
Test name
Test status
Simulation time 20412194894 ps
CPU time 28.52 seconds
Started Jul 05 05:40:29 PM PDT 24
Finished Jul 05 05:40:58 PM PDT 24
Peak memory 199932 kb
Host smart-0131263f-8773-4535-80c7-51783d979cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163880405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.4163880405
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3936352856
Short name T425
Test name
Test status
Simulation time 102396075508 ps
CPU time 47.27 seconds
Started Jul 05 05:40:29 PM PDT 24
Finished Jul 05 05:41:17 PM PDT 24
Peak memory 199884 kb
Host smart-5c72df25-5251-444a-91fd-5f4614962b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936352856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3936352856
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2064829934
Short name T206
Test name
Test status
Simulation time 53486456935 ps
CPU time 44.18 seconds
Started Jul 05 05:40:28 PM PDT 24
Finished Jul 05 05:41:13 PM PDT 24
Peak memory 199968 kb
Host smart-16fa19ff-f08b-4549-9790-febb5e01caac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064829934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2064829934
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1442208948
Short name T317
Test name
Test status
Simulation time 77272135006 ps
CPU time 35.47 seconds
Started Jul 05 05:40:28 PM PDT 24
Finished Jul 05 05:41:05 PM PDT 24
Peak memory 199904 kb
Host smart-67e4b1cb-e7b9-4033-8cb8-6205661539f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442208948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1442208948
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2659425241
Short name T345
Test name
Test status
Simulation time 46033704 ps
CPU time 0.61 seconds
Started Jul 05 05:37:56 PM PDT 24
Finished Jul 05 05:37:58 PM PDT 24
Peak memory 195328 kb
Host smart-5ff1d199-ddd6-458c-a9d6-f079d2e0d038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659425241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2659425241
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3850610437
Short name T131
Test name
Test status
Simulation time 57242618681 ps
CPU time 23.33 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:38:01 PM PDT 24
Peak memory 199984 kb
Host smart-b2b06f15-48c3-4c35-9c5a-2c3565365595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850610437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3850610437
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1940675518
Short name T444
Test name
Test status
Simulation time 43929973105 ps
CPU time 66.07 seconds
Started Jul 05 05:37:38 PM PDT 24
Finished Jul 05 05:38:46 PM PDT 24
Peak memory 199956 kb
Host smart-9deae869-a608-4f02-8214-3df57dc763bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940675518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1940675518
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.228115569
Short name T1090
Test name
Test status
Simulation time 27409392481 ps
CPU time 16.77 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:37:55 PM PDT 24
Peak memory 200004 kb
Host smart-6f57218d-b48f-4a12-bf0c-e0a12b07530d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228115569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.228115569
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1014732284
Short name T452
Test name
Test status
Simulation time 12648267908 ps
CPU time 16.57 seconds
Started Jul 05 05:37:44 PM PDT 24
Finished Jul 05 05:38:02 PM PDT 24
Peak memory 196448 kb
Host smart-992d4478-51c5-4884-aa1e-0b30b097bf5f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014732284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1014732284
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4010754117
Short name T645
Test name
Test status
Simulation time 211962920964 ps
CPU time 209.4 seconds
Started Jul 05 05:37:38 PM PDT 24
Finished Jul 05 05:41:09 PM PDT 24
Peak memory 199996 kb
Host smart-2c67b70d-65eb-4ec2-90f1-767ef7f9b199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010754117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4010754117
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3028427512
Short name T677
Test name
Test status
Simulation time 6011413286 ps
CPU time 9.53 seconds
Started Jul 05 05:37:38 PM PDT 24
Finished Jul 05 05:37:49 PM PDT 24
Peak memory 199396 kb
Host smart-c9f6233d-ef29-48db-bf56-7a888525d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028427512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3028427512
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.627160055
Short name T98
Test name
Test status
Simulation time 316980065310 ps
CPU time 101.1 seconds
Started Jul 05 05:37:38 PM PDT 24
Finished Jul 05 05:39:21 PM PDT 24
Peak memory 208376 kb
Host smart-4eceef81-616b-439c-a272-64d77b86a868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627160055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.627160055
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.441547392
Short name T690
Test name
Test status
Simulation time 11720505965 ps
CPU time 241.47 seconds
Started Jul 05 05:37:38 PM PDT 24
Finished Jul 05 05:41:41 PM PDT 24
Peak memory 199900 kb
Host smart-74225ef3-37dc-466e-8513-a2d1063ed35c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441547392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.441547392
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1467905058
Short name T324
Test name
Test status
Simulation time 6235941952 ps
CPU time 15.22 seconds
Started Jul 05 05:37:47 PM PDT 24
Finished Jul 05 05:38:03 PM PDT 24
Peak memory 199160 kb
Host smart-21731fea-b2f2-4735-8dcc-33c7b333950e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467905058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1467905058
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.88617274
Short name T734
Test name
Test status
Simulation time 20718630734 ps
CPU time 54.31 seconds
Started Jul 05 05:37:48 PM PDT 24
Finished Jul 05 05:38:43 PM PDT 24
Peak memory 199936 kb
Host smart-d837339b-c2b4-4301-8fab-d2a3b309cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88617274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.88617274
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1806033999
Short name T885
Test name
Test status
Simulation time 2480987515 ps
CPU time 1.62 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:37:39 PM PDT 24
Peak memory 195896 kb
Host smart-bec8769f-fd24-4e0b-9629-bea59902f51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806033999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1806033999
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.4103347239
Short name T832
Test name
Test status
Simulation time 494262536 ps
CPU time 1.43 seconds
Started Jul 05 05:37:49 PM PDT 24
Finished Jul 05 05:37:51 PM PDT 24
Peak memory 198412 kb
Host smart-f3208dad-4091-4b8a-b976-7d3e04c9b4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103347239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.4103347239
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3044598634
Short name T576
Test name
Test status
Simulation time 94553632497 ps
CPU time 918.15 seconds
Started Jul 05 05:37:45 PM PDT 24
Finished Jul 05 05:53:05 PM PDT 24
Peak memory 199964 kb
Host smart-91525a00-46d1-4ea0-826f-1515d17b3bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044598634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3044598634
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3357388353
Short name T918
Test name
Test status
Simulation time 43504901431 ps
CPU time 377.17 seconds
Started Jul 05 05:37:56 PM PDT 24
Finished Jul 05 05:44:15 PM PDT 24
Peak memory 216644 kb
Host smart-bcf68922-1c9d-44c4-995b-c3b2a66a08ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357388353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3357388353
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1761755311
Short name T545
Test name
Test status
Simulation time 743648578 ps
CPU time 2.68 seconds
Started Jul 05 05:37:39 PM PDT 24
Finished Jul 05 05:37:43 PM PDT 24
Peak memory 199792 kb
Host smart-9ad33190-899f-4b00-849a-25a518e66649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761755311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1761755311
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1995553403
Short name T895
Test name
Test status
Simulation time 5368223848 ps
CPU time 8.35 seconds
Started Jul 05 05:37:37 PM PDT 24
Finished Jul 05 05:37:47 PM PDT 24
Peak memory 197856 kb
Host smart-fdf31afd-e037-44d8-8d56-09d2e7fb1b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995553403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1995553403
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1326273101
Short name T1034
Test name
Test status
Simulation time 62281877975 ps
CPU time 188.1 seconds
Started Jul 05 05:40:30 PM PDT 24
Finished Jul 05 05:43:39 PM PDT 24
Peak memory 199972 kb
Host smart-1e53f305-eb9c-4116-8765-342234572b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326273101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1326273101
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1661656515
Short name T401
Test name
Test status
Simulation time 20558302008 ps
CPU time 34.06 seconds
Started Jul 05 05:40:28 PM PDT 24
Finished Jul 05 05:41:03 PM PDT 24
Peak memory 199792 kb
Host smart-6e08ef3a-d219-450e-b0fd-03b2d7f8e648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661656515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1661656515
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.687724214
Short name T554
Test name
Test status
Simulation time 18814983945 ps
CPU time 28.45 seconds
Started Jul 05 05:40:32 PM PDT 24
Finished Jul 05 05:41:00 PM PDT 24
Peak memory 199976 kb
Host smart-3f9ac723-c6d6-4b0f-a0a9-c8921aa4ea78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687724214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.687724214
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.576117214
Short name T662
Test name
Test status
Simulation time 95381766550 ps
CPU time 115.18 seconds
Started Jul 05 05:40:27 PM PDT 24
Finished Jul 05 05:42:23 PM PDT 24
Peak memory 199944 kb
Host smart-575ee5a8-7c00-4521-ba5b-2836a7e4e08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576117214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.576117214
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.228997203
Short name T285
Test name
Test status
Simulation time 20004967141 ps
CPU time 21.38 seconds
Started Jul 05 05:40:29 PM PDT 24
Finished Jul 05 05:40:52 PM PDT 24
Peak memory 199972 kb
Host smart-3b5c4245-769d-4452-9c6f-f3890863f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228997203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.228997203
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.413876583
Short name T977
Test name
Test status
Simulation time 37662287466 ps
CPU time 8.57 seconds
Started Jul 05 05:40:30 PM PDT 24
Finished Jul 05 05:40:40 PM PDT 24
Peak memory 199940 kb
Host smart-b8c567a1-abd2-4854-af31-7e663d35f29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413876583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.413876583
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2644697530
Short name T1071
Test name
Test status
Simulation time 30095315242 ps
CPU time 40.66 seconds
Started Jul 05 05:40:29 PM PDT 24
Finished Jul 05 05:41:10 PM PDT 24
Peak memory 199856 kb
Host smart-f1fcb68e-2e88-4778-a8d4-3caeba4b7178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644697530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2644697530
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1721909103
Short name T1095
Test name
Test status
Simulation time 15470587075 ps
CPU time 11.5 seconds
Started Jul 05 05:40:30 PM PDT 24
Finished Jul 05 05:40:42 PM PDT 24
Peak memory 199916 kb
Host smart-f1984ce2-4074-4de1-b128-d8e4a474927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721909103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1721909103
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.4201755574
Short name T1008
Test name
Test status
Simulation time 49201682429 ps
CPU time 81.45 seconds
Started Jul 05 05:40:35 PM PDT 24
Finished Jul 05 05:41:57 PM PDT 24
Peak memory 199980 kb
Host smart-a0b60046-6e6d-4106-aa33-07c0e3077777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201755574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.4201755574
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2560625402
Short name T899
Test name
Test status
Simulation time 13799655 ps
CPU time 0.55 seconds
Started Jul 05 05:37:45 PM PDT 24
Finished Jul 05 05:37:46 PM PDT 24
Peak memory 194304 kb
Host smart-7cd7f7b9-1d07-482a-905c-d446722dd9fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560625402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2560625402
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2399771613
Short name T799
Test name
Test status
Simulation time 144204939579 ps
CPU time 148.22 seconds
Started Jul 05 05:37:37 PM PDT 24
Finished Jul 05 05:40:07 PM PDT 24
Peak memory 199924 kb
Host smart-7c6078e1-46b6-4c22-9d0e-8f382c23c00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399771613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2399771613
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1751785307
Short name T835
Test name
Test status
Simulation time 74597968096 ps
CPU time 32.73 seconds
Started Jul 05 05:37:37 PM PDT 24
Finished Jul 05 05:38:12 PM PDT 24
Peak memory 199944 kb
Host smart-658d7b22-11f4-4d74-854d-7fdbd9d2dce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751785307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1751785307
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2018989232
Short name T981
Test name
Test status
Simulation time 38729658785 ps
CPU time 20.39 seconds
Started Jul 05 05:37:43 PM PDT 24
Finished Jul 05 05:38:04 PM PDT 24
Peak memory 199976 kb
Host smart-88c74288-c4a4-4059-ba09-ffbcdeaa72d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018989232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2018989232
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3852550478
Short name T330
Test name
Test status
Simulation time 6275975372 ps
CPU time 5.19 seconds
Started Jul 05 05:37:40 PM PDT 24
Finished Jul 05 05:37:46 PM PDT 24
Peak memory 196772 kb
Host smart-cc49f734-c49a-4f83-948e-00fd939f8161
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852550478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3852550478
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3682813878
Short name T246
Test name
Test status
Simulation time 142876758704 ps
CPU time 663.04 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 199984 kb
Host smart-beb2ba36-f7ac-498d-9934-032296a91177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682813878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3682813878
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1880809310
Short name T1141
Test name
Test status
Simulation time 10317426695 ps
CPU time 21.49 seconds
Started Jul 05 05:37:49 PM PDT 24
Finished Jul 05 05:38:11 PM PDT 24
Peak memory 199896 kb
Host smart-3836c1e7-b355-4879-9a3e-18a6a803721d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880809310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1880809310
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1432686270
Short name T719
Test name
Test status
Simulation time 17570173338 ps
CPU time 25.41 seconds
Started Jul 05 05:37:47 PM PDT 24
Finished Jul 05 05:38:13 PM PDT 24
Peak memory 198284 kb
Host smart-a602fbe3-cb16-4bd9-9b35-fc6adae7dcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432686270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1432686270
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2914187895
Short name T1083
Test name
Test status
Simulation time 13089525930 ps
CPU time 169.51 seconds
Started Jul 05 05:37:45 PM PDT 24
Finished Jul 05 05:40:35 PM PDT 24
Peak memory 199888 kb
Host smart-321292b8-d94d-45af-abf6-851cf9493581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2914187895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2914187895
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3579626955
Short name T458
Test name
Test status
Simulation time 1804067474 ps
CPU time 8.79 seconds
Started Jul 05 05:37:51 PM PDT 24
Finished Jul 05 05:38:01 PM PDT 24
Peak memory 199152 kb
Host smart-102028dd-fb51-4bae-abd9-78de2509b51e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579626955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3579626955
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3327076984
Short name T988
Test name
Test status
Simulation time 159182368255 ps
CPU time 67.34 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:38:45 PM PDT 24
Peak memory 200000 kb
Host smart-55a94445-c6f3-4e72-afe7-671d724d23df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327076984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3327076984
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.696544102
Short name T534
Test name
Test status
Simulation time 40931934684 ps
CPU time 4.09 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:37:41 PM PDT 24
Peak memory 196072 kb
Host smart-74beae42-f59a-4868-b908-20823457f9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696544102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.696544102
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2807219068
Short name T706
Test name
Test status
Simulation time 5742534039 ps
CPU time 6.83 seconds
Started Jul 05 05:37:51 PM PDT 24
Finished Jul 05 05:37:59 PM PDT 24
Peak memory 199876 kb
Host smart-76acf9f7-fcaf-45e0-a1a8-817bf5778866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807219068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2807219068
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1425823837
Short name T816
Test name
Test status
Simulation time 129819854711 ps
CPU time 209.24 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:41:26 PM PDT 24
Peak memory 208324 kb
Host smart-31364f36-de8e-4fa9-8676-a698d6a64615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425823837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1425823837
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3497228082
Short name T791
Test name
Test status
Simulation time 43789747302 ps
CPU time 370.58 seconds
Started Jul 05 05:37:50 PM PDT 24
Finished Jul 05 05:44:01 PM PDT 24
Peak memory 208396 kb
Host smart-f2f350ef-59c7-4f6f-8b0c-2a9a8d2e0fda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497228082 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3497228082
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3719712083
Short name T538
Test name
Test status
Simulation time 553819940 ps
CPU time 2.29 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:37:41 PM PDT 24
Peak memory 198688 kb
Host smart-cb9ea7cc-6fd9-4220-ae86-420267e5d367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719712083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3719712083
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.493289776
Short name T570
Test name
Test status
Simulation time 60205353750 ps
CPU time 134.92 seconds
Started Jul 05 05:37:39 PM PDT 24
Finished Jul 05 05:39:55 PM PDT 24
Peak memory 199988 kb
Host smart-43919ed4-723e-43ed-b192-4af7071522e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493289776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.493289776
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.47854671
Short name T408
Test name
Test status
Simulation time 112974970296 ps
CPU time 30.7 seconds
Started Jul 05 05:40:35 PM PDT 24
Finished Jul 05 05:41:06 PM PDT 24
Peak memory 200000 kb
Host smart-e61c6522-829a-4b68-801e-132bfbe63fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47854671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.47854671
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2067901403
Short name T997
Test name
Test status
Simulation time 29731220553 ps
CPU time 41.99 seconds
Started Jul 05 05:40:36 PM PDT 24
Finished Jul 05 05:41:19 PM PDT 24
Peak memory 199916 kb
Host smart-3088796d-ec10-4481-b040-c0dd3e548314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067901403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2067901403
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4104328483
Short name T910
Test name
Test status
Simulation time 68449487722 ps
CPU time 30.55 seconds
Started Jul 05 05:40:38 PM PDT 24
Finished Jul 05 05:41:09 PM PDT 24
Peak memory 199956 kb
Host smart-df2e2aad-651f-45ec-8879-ddce58fb5bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104328483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4104328483
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3868006267
Short name T1177
Test name
Test status
Simulation time 202753389913 ps
CPU time 182.93 seconds
Started Jul 05 05:40:38 PM PDT 24
Finished Jul 05 05:43:41 PM PDT 24
Peak memory 198908 kb
Host smart-77411066-03ae-490b-a7d0-99d1bd65140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868006267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3868006267
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.4193669298
Short name T708
Test name
Test status
Simulation time 16087784721 ps
CPU time 10.46 seconds
Started Jul 05 05:40:34 PM PDT 24
Finished Jul 05 05:40:45 PM PDT 24
Peak memory 199984 kb
Host smart-cb6b9906-99c8-4da4-b1f9-e95d349ab394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193669298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.4193669298
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3276478510
Short name T215
Test name
Test status
Simulation time 28423837107 ps
CPU time 29.9 seconds
Started Jul 05 05:40:38 PM PDT 24
Finished Jul 05 05:41:09 PM PDT 24
Peak memory 199920 kb
Host smart-e26e0166-6654-4d15-8abe-cbcffcf926a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276478510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3276478510
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1787555343
Short name T421
Test name
Test status
Simulation time 109431874699 ps
CPU time 89.16 seconds
Started Jul 05 05:40:37 PM PDT 24
Finished Jul 05 05:42:06 PM PDT 24
Peak memory 199936 kb
Host smart-9acf6410-e2b2-4cb8-b455-2ebbb2950db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787555343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1787555343
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.341857732
Short name T591
Test name
Test status
Simulation time 21940892748 ps
CPU time 38.04 seconds
Started Jul 05 05:40:35 PM PDT 24
Finished Jul 05 05:41:13 PM PDT 24
Peak memory 199976 kb
Host smart-4fd3d291-74c2-4e2b-9da9-b9bc528a0def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341857732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.341857732
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2448278531
Short name T171
Test name
Test status
Simulation time 52063869533 ps
CPU time 79.85 seconds
Started Jul 05 05:40:36 PM PDT 24
Finished Jul 05 05:41:56 PM PDT 24
Peak memory 199988 kb
Host smart-a698263f-ada0-4b72-be9f-365570dd87f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448278531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2448278531
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3548011658
Short name T406
Test name
Test status
Simulation time 43126246 ps
CPU time 0.55 seconds
Started Jul 05 05:36:59 PM PDT 24
Finished Jul 05 05:37:00 PM PDT 24
Peak memory 195520 kb
Host smart-aea2d12b-477c-4b7d-8a11-c01c6b498637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548011658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3548011658
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.416780976
Short name T503
Test name
Test status
Simulation time 30398241296 ps
CPU time 18.06 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:37:36 PM PDT 24
Peak memory 200000 kb
Host smart-ecb5bf80-7a0e-4836-99b5-71985385f210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416780976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.416780976
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.229262468
Short name T1006
Test name
Test status
Simulation time 83366814985 ps
CPU time 114.61 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:39:12 PM PDT 24
Peak memory 199892 kb
Host smart-288bfab4-65f6-4664-aead-dc78dce3dc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229262468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.229262468
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.73883752
Short name T1044
Test name
Test status
Simulation time 15949215049 ps
CPU time 12.39 seconds
Started Jul 05 05:36:56 PM PDT 24
Finished Jul 05 05:37:09 PM PDT 24
Peak memory 199984 kb
Host smart-046f965c-525f-40a2-926a-5e0eea55dd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73883752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.73883752
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1870404472
Short name T760
Test name
Test status
Simulation time 13336798181 ps
CPU time 10.96 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:37:10 PM PDT 24
Peak memory 199980 kb
Host smart-ef398523-0157-4d80-b896-fc9967dc66db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870404472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1870404472
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1255088818
Short name T515
Test name
Test status
Simulation time 174617220965 ps
CPU time 68.16 seconds
Started Jul 05 05:36:57 PM PDT 24
Finished Jul 05 05:38:06 PM PDT 24
Peak memory 199900 kb
Host smart-37bed014-20b4-460f-bf5c-3555f333241d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255088818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1255088818
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2053535565
Short name T7
Test name
Test status
Simulation time 1900489326 ps
CPU time 4.45 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:37:03 PM PDT 24
Peak memory 198672 kb
Host smart-d5c86b6d-d5aa-4014-b72a-2b54b390942f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053535565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2053535565
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2169961149
Short name T587
Test name
Test status
Simulation time 101014652970 ps
CPU time 186.88 seconds
Started Jul 05 05:37:01 PM PDT 24
Finished Jul 05 05:40:08 PM PDT 24
Peak memory 199920 kb
Host smart-b602062f-b111-42e1-933f-3b8b80169059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169961149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2169961149
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2697415675
Short name T872
Test name
Test status
Simulation time 4087508710 ps
CPU time 73.5 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:38:13 PM PDT 24
Peak memory 199944 kb
Host smart-911a0752-2cd3-469c-ac14-c43b989e6e18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697415675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2697415675
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2521064148
Short name T381
Test name
Test status
Simulation time 5152695696 ps
CPU time 50.02 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:38:08 PM PDT 24
Peak memory 199312 kb
Host smart-87c7a2b4-9e57-4c9b-86fd-1b6542a3dc9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521064148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2521064148
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.930553148
Short name T244
Test name
Test status
Simulation time 171451084459 ps
CPU time 68.46 seconds
Started Jul 05 05:37:18 PM PDT 24
Finished Jul 05 05:38:27 PM PDT 24
Peak memory 200024 kb
Host smart-6925cdf8-158a-4ccf-af25-2ec137f01e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930553148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.930553148
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3012809319
Short name T1077
Test name
Test status
Simulation time 54251048355 ps
CPU time 17.1 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:37:20 PM PDT 24
Peak memory 195784 kb
Host smart-c64d4ce0-034f-4a63-af6c-2a7fa72067de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012809319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3012809319
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.279537891
Short name T26
Test name
Test status
Simulation time 205768006 ps
CPU time 0.78 seconds
Started Jul 05 05:37:01 PM PDT 24
Finished Jul 05 05:37:02 PM PDT 24
Peak memory 218392 kb
Host smart-687438f8-964e-4078-b653-80e2d83ae882
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279537891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.279537891
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3019215095
Short name T418
Test name
Test status
Simulation time 509452338 ps
CPU time 2.11 seconds
Started Jul 05 05:37:01 PM PDT 24
Finished Jul 05 05:37:03 PM PDT 24
Peak memory 198688 kb
Host smart-40a2e65c-3bb2-4b21-9db1-826714cb86db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019215095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3019215095
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1241160572
Short name T126
Test name
Test status
Simulation time 123082490261 ps
CPU time 187.43 seconds
Started Jul 05 05:36:55 PM PDT 24
Finished Jul 05 05:40:03 PM PDT 24
Peak memory 199976 kb
Host smart-a011aab2-8297-4acb-8716-66152f6d2379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241160572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1241160572
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.5761432
Short name T880
Test name
Test status
Simulation time 812830140265 ps
CPU time 719.77 seconds
Started Jul 05 05:36:57 PM PDT 24
Finished Jul 05 05:48:57 PM PDT 24
Peak memory 216520 kb
Host smart-a7d2d3d5-915f-4194-869a-7eb46c3a9b43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5761432 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.5761432
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2446240279
Short name T492
Test name
Test status
Simulation time 6345405978 ps
CPU time 17.92 seconds
Started Jul 05 05:36:59 PM PDT 24
Finished Jul 05 05:37:17 PM PDT 24
Peak memory 199860 kb
Host smart-c9170773-6796-4cbf-a83c-5b74a6988b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446240279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2446240279
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.4130006529
Short name T91
Test name
Test status
Simulation time 32541537993 ps
CPU time 43.55 seconds
Started Jul 05 05:37:08 PM PDT 24
Finished Jul 05 05:37:53 PM PDT 24
Peak memory 199972 kb
Host smart-c36c1601-1dd1-4538-8eb2-161b4c163747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130006529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4130006529
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2643586324
Short name T648
Test name
Test status
Simulation time 16099412 ps
CPU time 0.58 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:37:57 PM PDT 24
Peak memory 195528 kb
Host smart-d8237e52-043d-42d7-a560-e5dcd47abdc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643586324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2643586324
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3703069520
Short name T868
Test name
Test status
Simulation time 28080916860 ps
CPU time 47.06 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:38:43 PM PDT 24
Peak memory 199980 kb
Host smart-b6fc1a00-04c3-42ae-a3a2-d11f30515f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703069520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3703069520
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3264846877
Short name T1138
Test name
Test status
Simulation time 356582094037 ps
CPU time 160.01 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:40:37 PM PDT 24
Peak memory 199820 kb
Host smart-45002eb5-f011-4ad0-a470-223dd5bea78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264846877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3264846877
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.171631468
Short name T232
Test name
Test status
Simulation time 9649635201 ps
CPU time 15.99 seconds
Started Jul 05 05:37:43 PM PDT 24
Finished Jul 05 05:37:59 PM PDT 24
Peak memory 200236 kb
Host smart-fc138bd2-674c-46e2-b8c5-b4045423ea9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171631468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.171631468
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.849497514
Short name T764
Test name
Test status
Simulation time 70868479804 ps
CPU time 23.18 seconds
Started Jul 05 05:37:44 PM PDT 24
Finished Jul 05 05:38:08 PM PDT 24
Peak memory 199968 kb
Host smart-f8da2cc4-802f-41b8-9253-2adabb57bcbb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849497514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.849497514
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.313113873
Short name T477
Test name
Test status
Simulation time 126850702213 ps
CPU time 87.69 seconds
Started Jul 05 05:37:51 PM PDT 24
Finished Jul 05 05:39:20 PM PDT 24
Peak memory 199924 kb
Host smart-d75587cb-9c53-44f2-8b60-971e8fda950e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313113873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.313113873
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1466978626
Short name T931
Test name
Test status
Simulation time 5261752430 ps
CPU time 4.41 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:38:00 PM PDT 24
Peak memory 198792 kb
Host smart-4c723512-e5f2-4e4c-a613-360bff1ba7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466978626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1466978626
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1794736701
Short name T667
Test name
Test status
Simulation time 154640399626 ps
CPU time 79.78 seconds
Started Jul 05 05:37:50 PM PDT 24
Finished Jul 05 05:39:11 PM PDT 24
Peak memory 200164 kb
Host smart-34e198fd-345a-4711-80b0-db9ab59d1baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794736701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1794736701
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3502458545
Short name T932
Test name
Test status
Simulation time 10627943592 ps
CPU time 110.95 seconds
Started Jul 05 05:37:49 PM PDT 24
Finished Jul 05 05:39:40 PM PDT 24
Peak memory 199932 kb
Host smart-cf5979fd-dd4e-46d5-8772-eb43206fe0c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502458545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3502458545
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.761298973
Short name T747
Test name
Test status
Simulation time 1784966892 ps
CPU time 7.95 seconds
Started Jul 05 05:37:39 PM PDT 24
Finished Jul 05 05:37:48 PM PDT 24
Peak memory 197764 kb
Host smart-fdfc7e09-caa8-48cc-9975-edbae6bef240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761298973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.761298973
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1217900158
Short name T271
Test name
Test status
Simulation time 100369705061 ps
CPU time 152.79 seconds
Started Jul 05 05:37:44 PM PDT 24
Finished Jul 05 05:40:17 PM PDT 24
Peak memory 199936 kb
Host smart-9ec56115-3efe-404d-92f9-7a4429e9e021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217900158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1217900158
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3042168890
Short name T427
Test name
Test status
Simulation time 1398455696 ps
CPU time 2.06 seconds
Started Jul 05 05:37:44 PM PDT 24
Finished Jul 05 05:37:47 PM PDT 24
Peak memory 195604 kb
Host smart-7b132bfb-ce44-46e8-904a-0d61cfc62c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042168890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3042168890
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2959295935
Short name T277
Test name
Test status
Simulation time 266357361 ps
CPU time 1.31 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:37:57 PM PDT 24
Peak memory 198508 kb
Host smart-da3114aa-8fde-4c6a-8549-4555469d10b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959295935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2959295935
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1211701120
Short name T935
Test name
Test status
Simulation time 299060357820 ps
CPU time 138.21 seconds
Started Jul 05 05:37:42 PM PDT 24
Finished Jul 05 05:40:01 PM PDT 24
Peak memory 199928 kb
Host smart-099c6fa3-c6e9-4daa-b8b6-c61e6554a672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211701120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1211701120
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3558197114
Short name T278
Test name
Test status
Simulation time 195117025425 ps
CPU time 531.07 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:46:48 PM PDT 24
Peak memory 216628 kb
Host smart-3f29c995-23d9-4a2d-9866-c8c024ae3b6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558197114 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3558197114
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.999816888
Short name T1001
Test name
Test status
Simulation time 1174721774 ps
CPU time 2.51 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:37:59 PM PDT 24
Peak memory 198704 kb
Host smart-05935148-a7ae-4450-9bf7-bd3c103a2aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999816888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.999816888
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.4009238928
Short name T1057
Test name
Test status
Simulation time 59435350574 ps
CPU time 77.73 seconds
Started Jul 05 05:37:52 PM PDT 24
Finished Jul 05 05:39:11 PM PDT 24
Peak memory 199928 kb
Host smart-f071b606-7c74-4dd3-ae8f-3026364786e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009238928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.4009238928
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.4069687653
Short name T220
Test name
Test status
Simulation time 285190257677 ps
CPU time 102.72 seconds
Started Jul 05 05:40:36 PM PDT 24
Finished Jul 05 05:42:19 PM PDT 24
Peak memory 199900 kb
Host smart-768d9d68-8ead-43dd-9d7c-200104c964e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069687653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4069687653
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.917742944
Short name T874
Test name
Test status
Simulation time 69111671734 ps
CPU time 150.27 seconds
Started Jul 05 05:40:34 PM PDT 24
Finished Jul 05 05:43:05 PM PDT 24
Peak memory 199940 kb
Host smart-b4bf4771-dc16-4d5a-9dab-a94cea7748be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917742944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.917742944
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1362799314
Short name T584
Test name
Test status
Simulation time 96048817759 ps
CPU time 39.28 seconds
Started Jul 05 05:40:35 PM PDT 24
Finished Jul 05 05:41:15 PM PDT 24
Peak memory 199980 kb
Host smart-1b8e3dec-7e3b-47da-9ab1-e12db9274c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362799314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1362799314
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.464746708
Short name T168
Test name
Test status
Simulation time 41616455706 ps
CPU time 66.15 seconds
Started Jul 05 05:40:38 PM PDT 24
Finished Jul 05 05:41:44 PM PDT 24
Peak memory 199936 kb
Host smart-dbb044a3-e6d2-4569-862a-d5142f1cfb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464746708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.464746708
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.899712721
Short name T599
Test name
Test status
Simulation time 28221326802 ps
CPU time 33.96 seconds
Started Jul 05 05:40:37 PM PDT 24
Finished Jul 05 05:41:11 PM PDT 24
Peak memory 199900 kb
Host smart-ddc92484-770b-4e39-af98-af803e2f7f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899712721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.899712721
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1301067110
Short name T135
Test name
Test status
Simulation time 38978872773 ps
CPU time 61.54 seconds
Started Jul 05 05:40:36 PM PDT 24
Finished Jul 05 05:41:38 PM PDT 24
Peak memory 199996 kb
Host smart-eebaa56e-49f1-4c5a-8edb-c173a33f172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301067110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1301067110
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3885159590
Short name T839
Test name
Test status
Simulation time 176645803871 ps
CPU time 49.82 seconds
Started Jul 05 05:40:38 PM PDT 24
Finished Jul 05 05:41:28 PM PDT 24
Peak memory 199856 kb
Host smart-55bd3c9d-66ba-45d6-a202-20d4f60b68c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885159590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3885159590
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1119374562
Short name T945
Test name
Test status
Simulation time 39915230013 ps
CPU time 15.97 seconds
Started Jul 05 05:40:35 PM PDT 24
Finished Jul 05 05:40:52 PM PDT 24
Peak memory 199932 kb
Host smart-aa2af0c2-d4af-4cd1-af4e-54d2c55b5ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119374562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1119374562
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3833628161
Short name T952
Test name
Test status
Simulation time 37914605656 ps
CPU time 18.5 seconds
Started Jul 05 05:40:39 PM PDT 24
Finished Jul 05 05:40:57 PM PDT 24
Peak memory 199916 kb
Host smart-5c22ea39-63f9-4eb4-8625-242a22d00483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833628161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3833628161
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.4016049151
Short name T550
Test name
Test status
Simulation time 11210383 ps
CPU time 0.58 seconds
Started Jul 05 05:37:58 PM PDT 24
Finished Jul 05 05:37:59 PM PDT 24
Peak memory 195524 kb
Host smart-8bae38ab-021f-454b-8489-0a882171a94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016049151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.4016049151
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.785068732
Short name T812
Test name
Test status
Simulation time 74225814098 ps
CPU time 70.03 seconds
Started Jul 05 05:37:50 PM PDT 24
Finished Jul 05 05:39:00 PM PDT 24
Peak memory 199984 kb
Host smart-6cdbb3c7-9c51-4b7f-9278-f9a4d8acbc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785068732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.785068732
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2856563163
Short name T118
Test name
Test status
Simulation time 12658032423 ps
CPU time 14.78 seconds
Started Jul 05 05:37:44 PM PDT 24
Finished Jul 05 05:37:59 PM PDT 24
Peak memory 199964 kb
Host smart-58d1dbce-61aa-41ca-aa6f-3ddd0832e63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856563163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2856563163
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.2819235521
Short name T728
Test name
Test status
Simulation time 18801985552 ps
CPU time 7.88 seconds
Started Jul 05 05:37:46 PM PDT 24
Finished Jul 05 05:37:54 PM PDT 24
Peak memory 198392 kb
Host smart-f42da83d-9796-4d69-a6a9-b39f290d6093
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819235521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2819235521
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2168027190
Short name T375
Test name
Test status
Simulation time 139967956756 ps
CPU time 361.15 seconds
Started Jul 05 05:37:42 PM PDT 24
Finished Jul 05 05:43:44 PM PDT 24
Peak memory 199924 kb
Host smart-25b55cac-6ec4-4996-87ad-ca4a8ad516c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168027190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2168027190
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1645789050
Short name T844
Test name
Test status
Simulation time 3326646286 ps
CPU time 6.57 seconds
Started Jul 05 05:37:59 PM PDT 24
Finished Jul 05 05:38:07 PM PDT 24
Peak memory 198484 kb
Host smart-54d1dac1-d7af-499e-9bd8-e356e658ddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645789050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1645789050
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2483887014
Short name T877
Test name
Test status
Simulation time 51196038361 ps
CPU time 24.37 seconds
Started Jul 05 05:37:58 PM PDT 24
Finished Jul 05 05:38:24 PM PDT 24
Peak memory 199028 kb
Host smart-149f9158-953f-4037-a467-5b35a80ab736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483887014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2483887014
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.451552216
Short name T1110
Test name
Test status
Simulation time 11044035562 ps
CPU time 304.46 seconds
Started Jul 05 05:37:45 PM PDT 24
Finished Jul 05 05:42:50 PM PDT 24
Peak memory 200000 kb
Host smart-11a55150-b172-4813-8cf9-9f9095b823f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451552216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.451552216
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3476543791
Short name T985
Test name
Test status
Simulation time 6735096390 ps
CPU time 15.92 seconds
Started Jul 05 05:37:41 PM PDT 24
Finished Jul 05 05:37:58 PM PDT 24
Peak memory 197852 kb
Host smart-fb8075f3-b6e9-49a6-aaed-63e6a7789af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476543791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3476543791
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2452551607
Short name T1131
Test name
Test status
Simulation time 50359499891 ps
CPU time 85.04 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:39:22 PM PDT 24
Peak memory 199840 kb
Host smart-fb653008-2b31-4ba5-8003-11408e2aaaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452551607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2452551607
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.508526629
Short name T1159
Test name
Test status
Simulation time 3549478379 ps
CPU time 3.21 seconds
Started Jul 05 05:37:45 PM PDT 24
Finished Jul 05 05:37:49 PM PDT 24
Peak memory 196524 kb
Host smart-b0d1a7f2-e7da-4df2-836f-27fcf30a2c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508526629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.508526629
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.917359684
Short name T377
Test name
Test status
Simulation time 293237938 ps
CPU time 1.35 seconds
Started Jul 05 05:37:46 PM PDT 24
Finished Jul 05 05:37:48 PM PDT 24
Peak memory 198616 kb
Host smart-a274a11c-9b87-4284-a34f-e959463335e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917359684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.917359684
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.4080595746
Short name T56
Test name
Test status
Simulation time 241385790501 ps
CPU time 716.53 seconds
Started Jul 05 05:37:53 PM PDT 24
Finished Jul 05 05:49:50 PM PDT 24
Peak memory 216520 kb
Host smart-64f65f43-d477-4e42-8c90-31176fd3c011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080595746 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.4080595746
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.387914996
Short name T1000
Test name
Test status
Simulation time 1648306161 ps
CPU time 1.98 seconds
Started Jul 05 05:37:43 PM PDT 24
Finished Jul 05 05:37:46 PM PDT 24
Peak memory 199816 kb
Host smart-e76baae2-862c-4cc5-8969-5a93ae15547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387914996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.387914996
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3745267677
Short name T748
Test name
Test status
Simulation time 42454108025 ps
CPU time 79.9 seconds
Started Jul 05 05:37:53 PM PDT 24
Finished Jul 05 05:39:14 PM PDT 24
Peak memory 199924 kb
Host smart-74277168-0438-4e8a-8069-53b28cb34612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745267677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3745267677
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1445576364
Short name T976
Test name
Test status
Simulation time 83281822490 ps
CPU time 36.82 seconds
Started Jul 05 05:40:36 PM PDT 24
Finished Jul 05 05:41:13 PM PDT 24
Peak memory 199844 kb
Host smart-3a99a300-49f6-475e-83a3-4f6ad4ff3695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445576364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1445576364
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.276375594
Short name T76
Test name
Test status
Simulation time 119465392553 ps
CPU time 188.79 seconds
Started Jul 05 05:40:45 PM PDT 24
Finished Jul 05 05:43:54 PM PDT 24
Peak memory 199940 kb
Host smart-7626c556-1d6e-47a7-84d8-a78954ed65a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276375594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.276375594
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2325096533
Short name T905
Test name
Test status
Simulation time 188893571867 ps
CPU time 15.48 seconds
Started Jul 05 05:40:42 PM PDT 24
Finished Jul 05 05:40:58 PM PDT 24
Peak memory 199872 kb
Host smart-d9b92c9d-f127-4a41-8537-806e515d0dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325096533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2325096533
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2717250647
Short name T223
Test name
Test status
Simulation time 17697545848 ps
CPU time 12.13 seconds
Started Jul 05 05:40:43 PM PDT 24
Finished Jul 05 05:40:55 PM PDT 24
Peak memory 199932 kb
Host smart-b1ff4029-6377-4fbc-83f5-325db0511a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717250647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2717250647
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.521970775
Short name T1160
Test name
Test status
Simulation time 486480894405 ps
CPU time 43.95 seconds
Started Jul 05 05:40:44 PM PDT 24
Finished Jul 05 05:41:28 PM PDT 24
Peak memory 199992 kb
Host smart-c868e4e6-20b4-4b22-8f31-91b4dbdc96f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521970775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.521970775
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1998259370
Short name T980
Test name
Test status
Simulation time 36380928728 ps
CPU time 14.01 seconds
Started Jul 05 05:40:45 PM PDT 24
Finished Jul 05 05:41:00 PM PDT 24
Peak memory 199680 kb
Host smart-25dc79d7-7d18-45f0-a24d-9ebdc1c7351a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998259370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1998259370
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2116401390
Short name T567
Test name
Test status
Simulation time 11417134362 ps
CPU time 20 seconds
Started Jul 05 05:40:45 PM PDT 24
Finished Jul 05 05:41:06 PM PDT 24
Peak memory 199992 kb
Host smart-e92140a8-3b37-4be3-9ef4-a6b96972c897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116401390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2116401390
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.666397602
Short name T134
Test name
Test status
Simulation time 111488874966 ps
CPU time 47.95 seconds
Started Jul 05 05:40:43 PM PDT 24
Finished Jul 05 05:41:31 PM PDT 24
Peak memory 199996 kb
Host smart-410a62e7-dfcc-4063-b98f-ac4e497d4f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666397602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.666397602
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.4066879788
Short name T938
Test name
Test status
Simulation time 42619120 ps
CPU time 0.53 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:37:57 PM PDT 24
Peak memory 195312 kb
Host smart-d105a651-5172-4f6c-bd69-bab18a9a0a3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066879788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4066879788
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1544349385
Short name T548
Test name
Test status
Simulation time 256102031220 ps
CPU time 390.24 seconds
Started Jul 05 05:37:43 PM PDT 24
Finished Jul 05 05:44:14 PM PDT 24
Peak memory 199928 kb
Host smart-ab8bf376-cf2d-4012-b174-f2534319a70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544349385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1544349385
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2208884434
Short name T320
Test name
Test status
Simulation time 61197274288 ps
CPU time 83.64 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:39:20 PM PDT 24
Peak memory 199940 kb
Host smart-bb54cf21-a5d7-475a-9187-7f57641890bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208884434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2208884434
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3769268244
Short name T216
Test name
Test status
Simulation time 25247914414 ps
CPU time 19.3 seconds
Started Jul 05 05:37:52 PM PDT 24
Finished Jul 05 05:38:12 PM PDT 24
Peak memory 199936 kb
Host smart-9c18df4b-cc79-4f42-a7f8-ee68beccac0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769268244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3769268244
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3582056150
Short name T429
Test name
Test status
Simulation time 284078292959 ps
CPU time 183.65 seconds
Started Jul 05 05:37:50 PM PDT 24
Finished Jul 05 05:40:55 PM PDT 24
Peak memory 198348 kb
Host smart-b4958505-431b-4745-b03b-fcf9b44a2738
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582056150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3582056150
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2456331309
Short name T1017
Test name
Test status
Simulation time 68435553712 ps
CPU time 212.45 seconds
Started Jul 05 05:37:57 PM PDT 24
Finished Jul 05 05:41:31 PM PDT 24
Peak memory 199820 kb
Host smart-da55a4f3-459c-4525-9ce7-f20f2136ef9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456331309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2456331309
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2565227219
Short name T738
Test name
Test status
Simulation time 1764965033 ps
CPU time 6.73 seconds
Started Jul 05 05:37:56 PM PDT 24
Finished Jul 05 05:38:04 PM PDT 24
Peak memory 198296 kb
Host smart-f75f3559-40b0-4aee-97a9-e8a8a3fa9e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565227219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2565227219
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.428131538
Short name T873
Test name
Test status
Simulation time 62997838002 ps
CPU time 87.98 seconds
Started Jul 05 05:37:56 PM PDT 24
Finished Jul 05 05:39:25 PM PDT 24
Peak memory 216296 kb
Host smart-b2991c08-0fa4-4a3e-ae68-fa3e995ec832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428131538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.428131538
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3619289150
Short name T843
Test name
Test status
Simulation time 11588891766 ps
CPU time 641.33 seconds
Started Jul 05 05:37:51 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 200008 kb
Host smart-31be9a66-47b1-4e79-8278-ee5f380df916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619289150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3619289150
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2425199918
Short name T445
Test name
Test status
Simulation time 6935833390 ps
CPU time 57.73 seconds
Started Jul 05 05:37:50 PM PDT 24
Finished Jul 05 05:38:48 PM PDT 24
Peak memory 198416 kb
Host smart-c0fe6cf5-76dd-452e-9626-2a234246326a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425199918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2425199918
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3709464005
Short name T968
Test name
Test status
Simulation time 7558392490 ps
CPU time 11.27 seconds
Started Jul 05 05:37:57 PM PDT 24
Finished Jul 05 05:38:10 PM PDT 24
Peak memory 198384 kb
Host smart-6f1b52ca-798e-4330-924e-38a82718a137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709464005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3709464005
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3636873918
Short name T1074
Test name
Test status
Simulation time 3110681984 ps
CPU time 5.34 seconds
Started Jul 05 05:37:56 PM PDT 24
Finished Jul 05 05:38:03 PM PDT 24
Peak memory 195820 kb
Host smart-8fcb1c34-4c9a-4b3a-9ad3-5fe26a46dd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636873918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3636873918
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2925215778
Short name T571
Test name
Test status
Simulation time 285491633 ps
CPU time 1.94 seconds
Started Jul 05 05:37:42 PM PDT 24
Finished Jul 05 05:37:45 PM PDT 24
Peak memory 198364 kb
Host smart-644f0e27-c16b-4dc2-be05-6354881b9a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925215778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2925215778
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3092423587
Short name T480
Test name
Test status
Simulation time 170761730137 ps
CPU time 389.18 seconds
Started Jul 05 05:38:02 PM PDT 24
Finished Jul 05 05:44:32 PM PDT 24
Peak memory 199920 kb
Host smart-c2ba7c6e-699e-4b59-9877-37a207a7d351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092423587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3092423587
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3722814912
Short name T342
Test name
Test status
Simulation time 1092670701 ps
CPU time 2.9 seconds
Started Jul 05 05:37:56 PM PDT 24
Finished Jul 05 05:38:00 PM PDT 24
Peak memory 198724 kb
Host smart-a92b6be1-00ee-4068-a93a-8b2eeeff8a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722814912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3722814912
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2116783016
Short name T240
Test name
Test status
Simulation time 300850883325 ps
CPU time 86.99 seconds
Started Jul 05 05:37:58 PM PDT 24
Finished Jul 05 05:39:27 PM PDT 24
Peak memory 199840 kb
Host smart-54df93c6-1b11-41fa-81e7-0f7a5e1cc5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116783016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2116783016
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.784565744
Short name T136
Test name
Test status
Simulation time 47869178086 ps
CPU time 30.43 seconds
Started Jul 05 05:40:42 PM PDT 24
Finished Jul 05 05:41:13 PM PDT 24
Peak memory 199964 kb
Host smart-99d772a3-91cf-4c05-987a-6b0dc81be5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784565744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.784565744
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.448512298
Short name T790
Test name
Test status
Simulation time 17119892161 ps
CPU time 28.9 seconds
Started Jul 05 05:40:42 PM PDT 24
Finished Jul 05 05:41:12 PM PDT 24
Peak memory 199940 kb
Host smart-601b9d2d-7c4a-4601-b7b5-9345b4a7eb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448512298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.448512298
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1929990992
Short name T891
Test name
Test status
Simulation time 41025111763 ps
CPU time 16.45 seconds
Started Jul 05 05:40:43 PM PDT 24
Finished Jul 05 05:41:00 PM PDT 24
Peak memory 197632 kb
Host smart-7d00ec1f-363e-4df2-9728-f97fde0f5205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929990992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1929990992
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2696725262
Short name T669
Test name
Test status
Simulation time 95825439439 ps
CPU time 314.3 seconds
Started Jul 05 05:40:42 PM PDT 24
Finished Jul 05 05:45:56 PM PDT 24
Peak memory 199744 kb
Host smart-59615094-3df4-4869-895f-6aca9bf3363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696725262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2696725262
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.828825302
Short name T177
Test name
Test status
Simulation time 125874717519 ps
CPU time 85.53 seconds
Started Jul 05 05:40:45 PM PDT 24
Finished Jul 05 05:42:11 PM PDT 24
Peak memory 200004 kb
Host smart-4708cd3f-9d7c-4e4e-88c0-d0cd639f3d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828825302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.828825302
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.747971442
Short name T564
Test name
Test status
Simulation time 44073291974 ps
CPU time 40.76 seconds
Started Jul 05 05:40:44 PM PDT 24
Finished Jul 05 05:41:25 PM PDT 24
Peak memory 199952 kb
Host smart-1aea8bd1-2bee-47f2-b913-7687bf4c25d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747971442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.747971442
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3023357664
Short name T626
Test name
Test status
Simulation time 378005928643 ps
CPU time 38.49 seconds
Started Jul 05 05:40:50 PM PDT 24
Finished Jul 05 05:41:30 PM PDT 24
Peak memory 199916 kb
Host smart-5bc65c74-5c78-4d00-8c94-389e4a154f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023357664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3023357664
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.811567673
Short name T182
Test name
Test status
Simulation time 22967758498 ps
CPU time 37.29 seconds
Started Jul 05 05:40:50 PM PDT 24
Finished Jul 05 05:41:28 PM PDT 24
Peak memory 199972 kb
Host smart-187b25d6-7d90-4ebe-b1fe-7121b2381bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811567673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.811567673
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1614460257
Short name T218
Test name
Test status
Simulation time 61009912163 ps
CPU time 49.58 seconds
Started Jul 05 05:40:51 PM PDT 24
Finished Jul 05 05:41:41 PM PDT 24
Peak memory 200016 kb
Host smart-3b071a5c-8f94-488a-a858-2b0cd712abf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614460257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1614460257
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3247087271
Short name T22
Test name
Test status
Simulation time 13017101 ps
CPU time 0.56 seconds
Started Jul 05 05:37:52 PM PDT 24
Finished Jul 05 05:37:53 PM PDT 24
Peak memory 194992 kb
Host smart-eebc46c4-8033-4c4a-8bbc-6d07ee495be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247087271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3247087271
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2791793799
Short name T888
Test name
Test status
Simulation time 17215688865 ps
CPU time 11.88 seconds
Started Jul 05 05:37:53 PM PDT 24
Finished Jul 05 05:38:05 PM PDT 24
Peak memory 199616 kb
Host smart-06b5a19e-5e7d-4f70-9898-270bbf5d19ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791793799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2791793799
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4074011503
Short name T143
Test name
Test status
Simulation time 20271606702 ps
CPU time 17.54 seconds
Started Jul 05 05:37:56 PM PDT 24
Finished Jul 05 05:38:15 PM PDT 24
Peak memory 199900 kb
Host smart-6f84ef21-a9b5-4cc3-afa6-817006c5ac4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074011503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4074011503
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.678349256
Short name T78
Test name
Test status
Simulation time 59317698826 ps
CPU time 55.87 seconds
Started Jul 05 05:37:54 PM PDT 24
Finished Jul 05 05:38:51 PM PDT 24
Peak memory 199952 kb
Host smart-ff645a83-d7b8-4166-99f7-37d633e459f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678349256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.678349256
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1980307177
Short name T1157
Test name
Test status
Simulation time 164799919942 ps
CPU time 241.8 seconds
Started Jul 05 05:37:51 PM PDT 24
Finished Jul 05 05:41:53 PM PDT 24
Peak memory 199920 kb
Host smart-3e8195d4-77ff-4ab2-bcea-3fc97caae65d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980307177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1980307177
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1165017835
Short name T494
Test name
Test status
Simulation time 162471031649 ps
CPU time 207.72 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:41:24 PM PDT 24
Peak memory 199868 kb
Host smart-08106432-2f74-4a03-94ec-e1cedd338e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1165017835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1165017835
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2910522918
Short name T920
Test name
Test status
Simulation time 1403176128 ps
CPU time 1.43 seconds
Started Jul 05 05:37:51 PM PDT 24
Finished Jul 05 05:37:53 PM PDT 24
Peak memory 197624 kb
Host smart-4879454d-5ad5-4073-81a3-f28088f47353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910522918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2910522918
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1736294541
Short name T437
Test name
Test status
Simulation time 31872661334 ps
CPU time 25.68 seconds
Started Jul 05 05:38:00 PM PDT 24
Finished Jul 05 05:38:27 PM PDT 24
Peak memory 197740 kb
Host smart-c04b3303-b845-4429-9c60-1d18758aaa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736294541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1736294541
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2471936398
Short name T684
Test name
Test status
Simulation time 15539941986 ps
CPU time 183.7 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:41:00 PM PDT 24
Peak memory 199992 kb
Host smart-96e467aa-6e0b-4480-975a-14f3a6628f8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2471936398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2471936398
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1574701642
Short name T724
Test name
Test status
Simulation time 2656480728 ps
CPU time 22.35 seconds
Started Jul 05 05:37:55 PM PDT 24
Finished Jul 05 05:38:19 PM PDT 24
Peak memory 198140 kb
Host smart-f1ff961d-f424-44e4-a61a-34847417192f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574701642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1574701642
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1028003068
Short name T451
Test name
Test status
Simulation time 114758661078 ps
CPU time 51.02 seconds
Started Jul 05 05:37:53 PM PDT 24
Finished Jul 05 05:38:45 PM PDT 24
Peak memory 199508 kb
Host smart-a40c4709-7886-4ce8-b5dd-e5fec6c0dcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028003068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1028003068
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.4134646929
Short name T526
Test name
Test status
Simulation time 4228393444 ps
CPU time 2.45 seconds
Started Jul 05 05:37:52 PM PDT 24
Finished Jul 05 05:37:56 PM PDT 24
Peak memory 196192 kb
Host smart-0c1bb09e-e99a-44a9-a24e-2296b9807347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134646929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.4134646929
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.692345976
Short name T1156
Test name
Test status
Simulation time 461653102 ps
CPU time 1.94 seconds
Started Jul 05 05:38:05 PM PDT 24
Finished Jul 05 05:38:08 PM PDT 24
Peak memory 199064 kb
Host smart-a6635365-1e68-4c88-9ada-a4b61526896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692345976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.692345976
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2319555754
Short name T1180
Test name
Test status
Simulation time 196548644592 ps
CPU time 605.04 seconds
Started Jul 05 05:37:49 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 224832 kb
Host smart-af79e994-c1c8-40b2-a465-7af8993d8ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319555754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2319555754
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2933172502
Short name T683
Test name
Test status
Simulation time 237552314 ps
CPU time 1.18 seconds
Started Jul 05 05:37:56 PM PDT 24
Finished Jul 05 05:37:59 PM PDT 24
Peak memory 197980 kb
Host smart-aac656a4-0670-499d-b365-9902998896b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933172502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2933172502
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.182361101
Short name T1073
Test name
Test status
Simulation time 125464932567 ps
CPU time 29.41 seconds
Started Jul 05 05:38:03 PM PDT 24
Finished Jul 05 05:38:33 PM PDT 24
Peak memory 199908 kb
Host smart-f8b2e590-def1-4916-83b7-a735228e2f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182361101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.182361101
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.750008405
Short name T784
Test name
Test status
Simulation time 72156769889 ps
CPU time 54.36 seconds
Started Jul 05 05:40:49 PM PDT 24
Finished Jul 05 05:41:44 PM PDT 24
Peak memory 199908 kb
Host smart-a741dab8-de3b-4827-b6b9-16a768e7b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750008405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.750008405
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1964592363
Short name T982
Test name
Test status
Simulation time 78468378857 ps
CPU time 40.86 seconds
Started Jul 05 05:40:52 PM PDT 24
Finished Jul 05 05:41:33 PM PDT 24
Peak memory 199984 kb
Host smart-2f8a1c77-6313-4c80-af0e-3bdd921983c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964592363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1964592363
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1248172833
Short name T1051
Test name
Test status
Simulation time 18863041784 ps
CPU time 7.82 seconds
Started Jul 05 05:40:51 PM PDT 24
Finished Jul 05 05:41:00 PM PDT 24
Peak memory 199992 kb
Host smart-5ea9b1ef-9fb7-4259-a2f3-8e85d6b27877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248172833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1248172833
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.50133853
Short name T944
Test name
Test status
Simulation time 52295229150 ps
CPU time 111.52 seconds
Started Jul 05 05:40:51 PM PDT 24
Finished Jul 05 05:42:43 PM PDT 24
Peak memory 199952 kb
Host smart-e8d5b7f6-d02d-4b66-9f40-28fa6dfeb1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50133853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.50133853
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3194056699
Short name T201
Test name
Test status
Simulation time 208451530649 ps
CPU time 78.39 seconds
Started Jul 05 05:40:50 PM PDT 24
Finished Jul 05 05:42:09 PM PDT 24
Peak memory 199904 kb
Host smart-e5bf6708-9f72-4529-99a7-0169e4a8be0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194056699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3194056699
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1722960443
Short name T528
Test name
Test status
Simulation time 42312007315 ps
CPU time 13.4 seconds
Started Jul 05 05:40:51 PM PDT 24
Finished Jul 05 05:41:05 PM PDT 24
Peak memory 199872 kb
Host smart-84424bc1-34f9-4aa8-99c3-6b0920fb9fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722960443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1722960443
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.599069764
Short name T270
Test name
Test status
Simulation time 133851105659 ps
CPU time 228.14 seconds
Started Jul 05 05:40:49 PM PDT 24
Finished Jul 05 05:44:37 PM PDT 24
Peak memory 199948 kb
Host smart-663c686f-26b6-4d77-9493-8800329b9298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599069764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.599069764
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1649436490
Short name T627
Test name
Test status
Simulation time 113231100992 ps
CPU time 50.13 seconds
Started Jul 05 05:41:00 PM PDT 24
Finished Jul 05 05:41:51 PM PDT 24
Peak memory 199996 kb
Host smart-4b6124d5-bc9e-46b4-9858-631f9f6b6055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649436490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1649436490
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1881164998
Short name T497
Test name
Test status
Simulation time 14837667 ps
CPU time 0.57 seconds
Started Jul 05 05:37:59 PM PDT 24
Finished Jul 05 05:38:01 PM PDT 24
Peak memory 195328 kb
Host smart-07aaabe5-2c45-4985-afdc-900dbdb8648a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881164998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1881164998
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.4283431179
Short name T973
Test name
Test status
Simulation time 156915227201 ps
CPU time 34.19 seconds
Started Jul 05 05:38:00 PM PDT 24
Finished Jul 05 05:38:36 PM PDT 24
Peak memory 199984 kb
Host smart-37c0e388-fc32-481d-b7a9-3497652f32e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283431179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.4283431179
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2108706396
Short name T456
Test name
Test status
Simulation time 53715091497 ps
CPU time 40.69 seconds
Started Jul 05 05:38:02 PM PDT 24
Finished Jul 05 05:38:44 PM PDT 24
Peak memory 199940 kb
Host smart-15b14b97-a2fc-450d-a4dc-cad5228413dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108706396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2108706396
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1858102649
Short name T226
Test name
Test status
Simulation time 63466210559 ps
CPU time 49.08 seconds
Started Jul 05 05:38:00 PM PDT 24
Finished Jul 05 05:38:50 PM PDT 24
Peak memory 199956 kb
Host smart-fcb792ed-25f8-4d0e-a7a6-45fa12a40cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858102649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1858102649
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2850272927
Short name T687
Test name
Test status
Simulation time 322785419687 ps
CPU time 115.35 seconds
Started Jul 05 05:40:26 PM PDT 24
Finished Jul 05 05:42:22 PM PDT 24
Peak memory 198216 kb
Host smart-d71e9dcb-3f25-4eda-9151-cf1e0e7597ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850272927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2850272927
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2821362766
Short name T600
Test name
Test status
Simulation time 111776666638 ps
CPU time 479.8 seconds
Started Jul 05 05:38:03 PM PDT 24
Finished Jul 05 05:46:05 PM PDT 24
Peak memory 199960 kb
Host smart-578d3f5e-f4b0-431a-8f6c-8258868e1d15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821362766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2821362766
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3718869386
Short name T517
Test name
Test status
Simulation time 5091465249 ps
CPU time 17.09 seconds
Started Jul 05 05:38:03 PM PDT 24
Finished Jul 05 05:38:22 PM PDT 24
Peak memory 199924 kb
Host smart-413bb19b-6342-4a9e-8176-ce6749b86032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718869386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3718869386
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2087668948
Short name T518
Test name
Test status
Simulation time 162546925997 ps
CPU time 95.99 seconds
Started Jul 05 05:38:03 PM PDT 24
Finished Jul 05 05:39:41 PM PDT 24
Peak memory 200088 kb
Host smart-16b671db-d535-4c97-bcd4-2558caad1bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087668948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2087668948
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2349085041
Short name T1078
Test name
Test status
Simulation time 7747764629 ps
CPU time 460.21 seconds
Started Jul 05 05:38:05 PM PDT 24
Finished Jul 05 05:45:47 PM PDT 24
Peak memory 199876 kb
Host smart-c1827330-78bc-43f5-8452-62a7387f6501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349085041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2349085041
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.268430639
Short name T774
Test name
Test status
Simulation time 2315137408 ps
CPU time 15.69 seconds
Started Jul 05 05:37:53 PM PDT 24
Finished Jul 05 05:38:09 PM PDT 24
Peak memory 198224 kb
Host smart-c1063b89-9472-4cbb-bb43-d94ce7e67028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=268430639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.268430639
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.36605194
Short name T249
Test name
Test status
Simulation time 18546421503 ps
CPU time 13.89 seconds
Started Jul 05 05:38:01 PM PDT 24
Finished Jul 05 05:38:16 PM PDT 24
Peak memory 199680 kb
Host smart-4d0dce58-8261-4951-bcda-472f41452ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36605194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.36605194
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2702306920
Short name T479
Test name
Test status
Simulation time 4116711331 ps
CPU time 3.53 seconds
Started Jul 05 05:38:02 PM PDT 24
Finished Jul 05 05:38:07 PM PDT 24
Peak memory 196724 kb
Host smart-e8e432b0-bf8f-409a-b138-4c106c17c78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702306920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2702306920
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2160743810
Short name T94
Test name
Test status
Simulation time 735294324 ps
CPU time 2.68 seconds
Started Jul 05 05:38:00 PM PDT 24
Finished Jul 05 05:38:04 PM PDT 24
Peak memory 199912 kb
Host smart-bfccab18-b48e-4205-bef9-1e760a6e14dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160743810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2160743810
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3969338282
Short name T668
Test name
Test status
Simulation time 86921175727 ps
CPU time 137.01 seconds
Started Jul 05 05:37:58 PM PDT 24
Finished Jul 05 05:40:17 PM PDT 24
Peak memory 199956 kb
Host smart-e271e8fe-1200-4cb5-be30-bb4eb399e505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969338282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3969338282
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3768409435
Short name T726
Test name
Test status
Simulation time 34287665445 ps
CPU time 460.88 seconds
Started Jul 05 05:37:59 PM PDT 24
Finished Jul 05 05:45:41 PM PDT 24
Peak memory 216636 kb
Host smart-452610f9-9ad5-4cbc-9897-8b0a908fc4fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768409435 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3768409435
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.4090065141
Short name T1151
Test name
Test status
Simulation time 1901436179 ps
CPU time 2.52 seconds
Started Jul 05 05:38:04 PM PDT 24
Finished Jul 05 05:38:07 PM PDT 24
Peak memory 199944 kb
Host smart-8273947e-82f1-46a6-b96d-6efbc99d7bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090065141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.4090065141
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2268893210
Short name T723
Test name
Test status
Simulation time 53384038213 ps
CPU time 40.77 seconds
Started Jul 05 05:37:52 PM PDT 24
Finished Jul 05 05:38:34 PM PDT 24
Peak memory 199984 kb
Host smart-c68aec01-e027-49c1-a700-f937ff5e16c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268893210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2268893210
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.555199378
Short name T594
Test name
Test status
Simulation time 254891864408 ps
CPU time 27.96 seconds
Started Jul 05 05:40:57 PM PDT 24
Finished Jul 05 05:41:26 PM PDT 24
Peak memory 200004 kb
Host smart-a222bf6f-f17b-4f95-9473-4b8191816b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555199378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.555199378
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3525966857
Short name T725
Test name
Test status
Simulation time 27478765477 ps
CPU time 34.74 seconds
Started Jul 05 05:40:57 PM PDT 24
Finished Jul 05 05:41:32 PM PDT 24
Peak memory 199932 kb
Host smart-e8bf19c5-addc-4a6f-859a-070ebb6802ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525966857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3525966857
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1645446429
Short name T1096
Test name
Test status
Simulation time 198716769148 ps
CPU time 148.22 seconds
Started Jul 05 05:40:58 PM PDT 24
Finished Jul 05 05:43:27 PM PDT 24
Peak memory 200000 kb
Host smart-6e346432-8ed7-4344-a0a9-7b340373c087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645446429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1645446429
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.230838423
Short name T1049
Test name
Test status
Simulation time 20652707189 ps
CPU time 11.21 seconds
Started Jul 05 05:40:58 PM PDT 24
Finished Jul 05 05:41:10 PM PDT 24
Peak memory 200000 kb
Host smart-8c547d5a-d8f3-448c-a665-6d3f1ef30c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230838423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.230838423
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3155895958
Short name T236
Test name
Test status
Simulation time 217057570331 ps
CPU time 26.72 seconds
Started Jul 05 05:40:59 PM PDT 24
Finished Jul 05 05:41:26 PM PDT 24
Peak memory 199872 kb
Host smart-378d7ddc-93c1-4e17-9a82-5e6ea328b4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155895958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3155895958
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.677059356
Short name T208
Test name
Test status
Simulation time 29832407651 ps
CPU time 50.43 seconds
Started Jul 05 05:40:57 PM PDT 24
Finished Jul 05 05:41:48 PM PDT 24
Peak memory 199900 kb
Host smart-c3d3b5a5-f74a-4b84-bd4c-25a7397d6465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677059356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.677059356
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.485864013
Short name T1120
Test name
Test status
Simulation time 79925980961 ps
CPU time 142.95 seconds
Started Jul 05 05:41:00 PM PDT 24
Finished Jul 05 05:43:24 PM PDT 24
Peak memory 200000 kb
Host smart-5a5a2a33-4f36-4080-833e-d0c8a815fb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485864013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.485864013
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1171470079
Short name T788
Test name
Test status
Simulation time 17382593099 ps
CPU time 32.67 seconds
Started Jul 05 05:40:57 PM PDT 24
Finished Jul 05 05:41:31 PM PDT 24
Peak memory 199924 kb
Host smart-76c9ed0b-a68e-4281-89a6-31b997ceecb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171470079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1171470079
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3603736928
Short name T165
Test name
Test status
Simulation time 157439285241 ps
CPU time 70.31 seconds
Started Jul 05 05:41:03 PM PDT 24
Finished Jul 05 05:42:14 PM PDT 24
Peak memory 199864 kb
Host smart-01ec837a-bf61-4e6d-99b5-bcfd3b2cd96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603736928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3603736928
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3458911321
Short name T108
Test name
Test status
Simulation time 48779119325 ps
CPU time 79.04 seconds
Started Jul 05 05:41:00 PM PDT 24
Finished Jul 05 05:42:20 PM PDT 24
Peak memory 199920 kb
Host smart-efed196b-6a9a-41a0-86bf-9d4e1bda2c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458911321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3458911321
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2950885593
Short name T846
Test name
Test status
Simulation time 24292917 ps
CPU time 0.57 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:38:09 PM PDT 24
Peak memory 195292 kb
Host smart-23e1925f-3ef7-4a1d-afc4-6577b4ceda02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950885593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2950885593
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2125592695
Short name T238
Test name
Test status
Simulation time 142513186838 ps
CPU time 93.75 seconds
Started Jul 05 05:38:04 PM PDT 24
Finished Jul 05 05:39:39 PM PDT 24
Peak memory 199900 kb
Host smart-71dd8a8d-1c87-4fae-b7d2-0bb5ca833c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125592695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2125592695
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1031143788
Short name T416
Test name
Test status
Simulation time 85064085637 ps
CPU time 67.9 seconds
Started Jul 05 05:37:58 PM PDT 24
Finished Jul 05 05:39:07 PM PDT 24
Peak memory 199996 kb
Host smart-f33aa09a-3388-41f3-be33-2e0a9f15e1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031143788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1031143788
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2168435923
Short name T991
Test name
Test status
Simulation time 70071190133 ps
CPU time 24.08 seconds
Started Jul 05 05:37:59 PM PDT 24
Finished Jul 05 05:38:24 PM PDT 24
Peak memory 199664 kb
Host smart-a6021fa8-286d-481a-a67e-0b649fc47e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168435923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2168435923
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.4190193340
Short name T308
Test name
Test status
Simulation time 16996953703 ps
CPU time 6.87 seconds
Started Jul 05 05:37:57 PM PDT 24
Finished Jul 05 05:38:05 PM PDT 24
Peak memory 197548 kb
Host smart-58853dd9-70ca-4956-9886-41e700e5181b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190193340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4190193340
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3524113863
Short name T471
Test name
Test status
Simulation time 77225224436 ps
CPU time 96.57 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:39:44 PM PDT 24
Peak memory 199996 kb
Host smart-58824290-2d3f-41ae-9f0e-604c11f046af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524113863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3524113863
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1486710216
Short name T849
Test name
Test status
Simulation time 3177798829 ps
CPU time 2.96 seconds
Started Jul 05 05:38:08 PM PDT 24
Finished Jul 05 05:38:13 PM PDT 24
Peak memory 196300 kb
Host smart-7eacbd59-ff46-45e4-afa3-e3945577cbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486710216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1486710216
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1375738652
Short name T860
Test name
Test status
Simulation time 250956038576 ps
CPU time 100.72 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:39:48 PM PDT 24
Peak memory 208268 kb
Host smart-39d91498-ade7-42ac-8fef-a1a2582d1ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375738652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1375738652
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2665348351
Short name T348
Test name
Test status
Simulation time 4927432562 ps
CPU time 264.36 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:42:31 PM PDT 24
Peak memory 199920 kb
Host smart-06a7c421-78ed-4911-ad76-28c8b5021bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665348351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2665348351
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.134740694
Short name T743
Test name
Test status
Simulation time 5394900991 ps
CPU time 9.34 seconds
Started Jul 05 05:38:02 PM PDT 24
Finished Jul 05 05:38:12 PM PDT 24
Peak memory 198156 kb
Host smart-3c3f789b-f0c5-4935-ba75-591949f640a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134740694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.134740694
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3339329510
Short name T542
Test name
Test status
Simulation time 60457826374 ps
CPU time 52.09 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:38:59 PM PDT 24
Peak memory 199808 kb
Host smart-29bb4f4c-13e0-4beb-9082-f713de88574d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339329510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3339329510
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1982653055
Short name T917
Test name
Test status
Simulation time 1864690157 ps
CPU time 3.2 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:38:10 PM PDT 24
Peak memory 195380 kb
Host smart-f484d162-4aa9-467c-8a4b-b71582d96554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982653055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1982653055
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.773118447
Short name T426
Test name
Test status
Simulation time 5691765403 ps
CPU time 21.63 seconds
Started Jul 05 05:38:02 PM PDT 24
Finished Jul 05 05:38:24 PM PDT 24
Peak memory 199732 kb
Host smart-5bfe2c43-3793-4f82-b16c-941004c86a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773118447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.773118447
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2132172952
Short name T398
Test name
Test status
Simulation time 6194259609 ps
CPU time 5.37 seconds
Started Jul 05 05:38:07 PM PDT 24
Finished Jul 05 05:38:14 PM PDT 24
Peak memory 198688 kb
Host smart-f2abfa3d-aa24-496b-a9ed-a0edde6463b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132172952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2132172952
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3631943518
Short name T32
Test name
Test status
Simulation time 117984503721 ps
CPU time 954.32 seconds
Started Jul 05 05:38:04 PM PDT 24
Finished Jul 05 05:53:59 PM PDT 24
Peak memory 224780 kb
Host smart-e70d0586-5d76-4d73-a5c9-b37bab57b895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631943518 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3631943518
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3531335143
Short name T870
Test name
Test status
Simulation time 12606095261 ps
CPU time 23.2 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:38:31 PM PDT 24
Peak memory 199824 kb
Host smart-e1d54645-5096-4d3d-a424-16b1ffbbd595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531335143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3531335143
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2288495017
Short name T685
Test name
Test status
Simulation time 243788884158 ps
CPU time 106.51 seconds
Started Jul 05 05:38:01 PM PDT 24
Finished Jul 05 05:39:48 PM PDT 24
Peak memory 199964 kb
Host smart-b246af5c-9e81-436c-8eb7-b45bc29358a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288495017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2288495017
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.4012977920
Short name T217
Test name
Test status
Simulation time 36992414979 ps
CPU time 29.89 seconds
Started Jul 05 05:40:58 PM PDT 24
Finished Jul 05 05:41:28 PM PDT 24
Peak memory 199944 kb
Host smart-1be3dbda-4f32-4ce0-8990-55b687ea0b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012977920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.4012977920
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.343283214
Short name T688
Test name
Test status
Simulation time 181540927534 ps
CPU time 245.09 seconds
Started Jul 05 05:41:00 PM PDT 24
Finished Jul 05 05:45:06 PM PDT 24
Peak memory 200000 kb
Host smart-107a1194-580b-43d0-b56e-c8d57f948421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343283214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.343283214
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2139989111
Short name T926
Test name
Test status
Simulation time 59164006555 ps
CPU time 91.91 seconds
Started Jul 05 05:41:00 PM PDT 24
Finished Jul 05 05:42:33 PM PDT 24
Peak memory 199928 kb
Host smart-c1845da8-a517-46c9-b794-6b8352acd499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139989111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2139989111
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.4276908284
Short name T775
Test name
Test status
Simulation time 52159156498 ps
CPU time 102.03 seconds
Started Jul 05 05:41:03 PM PDT 24
Finished Jul 05 05:42:46 PM PDT 24
Peak memory 199916 kb
Host smart-f359c745-9eb8-4c6c-811a-734db31a69e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276908284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.4276908284
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1579810799
Short name T704
Test name
Test status
Simulation time 20160713420 ps
CPU time 9.71 seconds
Started Jul 05 05:40:55 PM PDT 24
Finished Jul 05 05:41:05 PM PDT 24
Peak memory 199908 kb
Host smart-47f3749d-450b-460e-a600-395aad38c729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579810799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1579810799
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3230797759
Short name T555
Test name
Test status
Simulation time 87518733423 ps
CPU time 82.18 seconds
Started Jul 05 05:40:59 PM PDT 24
Finished Jul 05 05:42:21 PM PDT 24
Peak memory 199992 kb
Host smart-e842a704-fd59-475c-a14f-4056794304ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230797759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3230797759
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2144251372
Short name T1037
Test name
Test status
Simulation time 37655605449 ps
CPU time 16.31 seconds
Started Jul 05 05:40:59 PM PDT 24
Finished Jul 05 05:41:16 PM PDT 24
Peak memory 199788 kb
Host smart-e43f4e9b-6778-4aa2-babe-ae17d6420a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144251372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2144251372
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2368209378
Short name T116
Test name
Test status
Simulation time 113377809283 ps
CPU time 193.82 seconds
Started Jul 05 05:40:57 PM PDT 24
Finished Jul 05 05:44:12 PM PDT 24
Peak memory 199884 kb
Host smart-4fff7835-b25f-48d0-8108-b06b718c52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368209378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2368209378
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1261532912
Short name T601
Test name
Test status
Simulation time 28110349281 ps
CPU time 17.9 seconds
Started Jul 05 05:40:59 PM PDT 24
Finished Jul 05 05:41:17 PM PDT 24
Peak memory 199884 kb
Host smart-c573d55e-a420-4192-929e-09a46f3685e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261532912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1261532912
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.839922711
Short name T180
Test name
Test status
Simulation time 23092958768 ps
CPU time 33.07 seconds
Started Jul 05 05:41:03 PM PDT 24
Finished Jul 05 05:41:37 PM PDT 24
Peak memory 199940 kb
Host smart-e0a33b12-2471-4f24-88f4-c888a43e2bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839922711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.839922711
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2532678230
Short name T1023
Test name
Test status
Simulation time 12069222 ps
CPU time 0.58 seconds
Started Jul 05 05:38:08 PM PDT 24
Finished Jul 05 05:38:10 PM PDT 24
Peak memory 195328 kb
Host smart-b5355fba-5e73-4a49-baa1-1635f267c0d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532678230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2532678230
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2440952221
Short name T1135
Test name
Test status
Simulation time 81512623564 ps
CPU time 117.18 seconds
Started Jul 05 05:38:09 PM PDT 24
Finished Jul 05 05:40:07 PM PDT 24
Peak memory 199988 kb
Host smart-509d0f54-8fcc-4d2f-bbe9-c45e10018e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440952221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2440952221
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.450508538
Short name T1075
Test name
Test status
Simulation time 13326559331 ps
CPU time 10.11 seconds
Started Jul 05 05:38:08 PM PDT 24
Finished Jul 05 05:38:20 PM PDT 24
Peak memory 199980 kb
Host smart-aee4345b-a5c4-40b1-ade3-6853b461fa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450508538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.450508538
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3938802838
Short name T804
Test name
Test status
Simulation time 27440693838 ps
CPU time 44.11 seconds
Started Jul 05 05:38:07 PM PDT 24
Finished Jul 05 05:38:53 PM PDT 24
Peak memory 199952 kb
Host smart-2f05fba9-02d4-41ec-a8ce-a87d79482f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938802838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3938802838
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2611487823
Short name T1070
Test name
Test status
Simulation time 36566277873 ps
CPU time 20.21 seconds
Started Jul 05 05:38:11 PM PDT 24
Finished Jul 05 05:38:31 PM PDT 24
Peak memory 199616 kb
Host smart-76108620-7c18-4db0-a592-207fde1d95be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611487823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2611487823
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3981114257
Short name T302
Test name
Test status
Simulation time 120275062221 ps
CPU time 342.8 seconds
Started Jul 05 05:38:08 PM PDT 24
Finished Jul 05 05:43:52 PM PDT 24
Peak memory 199904 kb
Host smart-769c8984-bd2a-49e9-a7b2-2228deb36ca2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981114257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3981114257
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.835600119
Short name T386
Test name
Test status
Simulation time 5954844060 ps
CPU time 6.88 seconds
Started Jul 05 05:38:07 PM PDT 24
Finished Jul 05 05:38:16 PM PDT 24
Peak memory 199908 kb
Host smart-e0aa835e-bd58-4a34-84b6-3bdced89a4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835600119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.835600119
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.532169507
Short name T403
Test name
Test status
Simulation time 125675889407 ps
CPU time 53.24 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:39:00 PM PDT 24
Peak memory 208112 kb
Host smart-d7e54120-83ab-4e54-b0a4-2f84fd14146f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532169507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.532169507
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.4193502464
Short name T631
Test name
Test status
Simulation time 12751091110 ps
CPU time 765.47 seconds
Started Jul 05 05:38:07 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 199932 kb
Host smart-b653688d-3610-49ba-91e2-73862f0f6d18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193502464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4193502464
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.402182846
Short name T744
Test name
Test status
Simulation time 5470496408 ps
CPU time 46.48 seconds
Started Jul 05 05:38:07 PM PDT 24
Finished Jul 05 05:38:55 PM PDT 24
Peak memory 199164 kb
Host smart-48aeb45e-9f9f-4f0a-a005-6ccad1fe73c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402182846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.402182846
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2709691654
Short name T837
Test name
Test status
Simulation time 141309188994 ps
CPU time 12.24 seconds
Started Jul 05 05:38:05 PM PDT 24
Finished Jul 05 05:38:19 PM PDT 24
Peak memory 199924 kb
Host smart-b1e4beaf-941a-499e-80bc-645acca1f5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709691654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2709691654
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2314299497
Short name T695
Test name
Test status
Simulation time 2579359398 ps
CPU time 1.19 seconds
Started Jul 05 05:38:08 PM PDT 24
Finished Jul 05 05:38:10 PM PDT 24
Peak memory 195680 kb
Host smart-134eabaa-7cbf-4a62-a08a-3b4f55a1d4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314299497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2314299497
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1109463736
Short name T776
Test name
Test status
Simulation time 882926536 ps
CPU time 6.08 seconds
Started Jul 05 05:38:08 PM PDT 24
Finished Jul 05 05:38:15 PM PDT 24
Peak memory 198204 kb
Host smart-73982a11-9a7c-41f4-abe2-a5bed0da17cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109463736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1109463736
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1552231133
Short name T1173
Test name
Test status
Simulation time 459825088994 ps
CPU time 93.09 seconds
Started Jul 05 05:38:05 PM PDT 24
Finished Jul 05 05:39:39 PM PDT 24
Peak memory 199928 kb
Host smart-16c63249-a961-4cea-a482-b82db3533360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552231133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1552231133
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.477006241
Short name T925
Test name
Test status
Simulation time 210274087223 ps
CPU time 737.02 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:50:25 PM PDT 24
Peak memory 224888 kb
Host smart-22e7731b-c257-4f08-8c54-9dbd3d147f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477006241 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.477006241
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1208164842
Short name T777
Test name
Test status
Simulation time 959319115 ps
CPU time 2.68 seconds
Started Jul 05 05:38:08 PM PDT 24
Finished Jul 05 05:38:12 PM PDT 24
Peak memory 198524 kb
Host smart-740611fd-421c-469b-9aba-12f0cfadc2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208164842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1208164842
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2235709436
Short name T914
Test name
Test status
Simulation time 8994174045 ps
CPU time 17.11 seconds
Started Jul 05 05:38:06 PM PDT 24
Finished Jul 05 05:38:25 PM PDT 24
Peak memory 199804 kb
Host smart-9c7ee2b0-605d-44b1-ac7b-ed2e86b1108c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235709436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2235709436
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.553913735
Short name T176
Test name
Test status
Simulation time 28380707589 ps
CPU time 47.7 seconds
Started Jul 05 05:41:05 PM PDT 24
Finished Jul 05 05:41:54 PM PDT 24
Peak memory 199928 kb
Host smart-83a5db49-020d-40af-9862-151699e0fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553913735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.553913735
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.4078461677
Short name T199
Test name
Test status
Simulation time 15821552945 ps
CPU time 24.74 seconds
Started Jul 05 05:41:05 PM PDT 24
Finished Jul 05 05:41:30 PM PDT 24
Peak memory 199720 kb
Host smart-d0515dd2-3628-4101-bf24-1921f2bc1963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078461677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.4078461677
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3474403996
Short name T1121
Test name
Test status
Simulation time 11031511203 ps
CPU time 4.99 seconds
Started Jul 05 05:41:16 PM PDT 24
Finished Jul 05 05:41:21 PM PDT 24
Peak memory 199972 kb
Host smart-72e0cf22-81e3-498c-a7b2-29cd985c3e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474403996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3474403996
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2335900463
Short name T222
Test name
Test status
Simulation time 12501342361 ps
CPU time 21.65 seconds
Started Jul 05 05:41:05 PM PDT 24
Finished Jul 05 05:41:27 PM PDT 24
Peak memory 199936 kb
Host smart-c2a893d2-76be-4623-9a68-32ad01ba9d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335900463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2335900463
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2881771306
Short name T231
Test name
Test status
Simulation time 36003443761 ps
CPU time 14.68 seconds
Started Jul 05 05:41:06 PM PDT 24
Finished Jul 05 05:41:21 PM PDT 24
Peak memory 199692 kb
Host smart-f851c144-b0f7-492d-9723-12bab9532de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881771306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2881771306
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.4118593315
Short name T1064
Test name
Test status
Simulation time 137384851528 ps
CPU time 65.08 seconds
Started Jul 05 05:41:06 PM PDT 24
Finished Jul 05 05:42:12 PM PDT 24
Peak memory 199908 kb
Host smart-5124d144-d3db-49e0-a47b-134488fceb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118593315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.4118593315
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2736600932
Short name T673
Test name
Test status
Simulation time 43789609606 ps
CPU time 20.67 seconds
Started Jul 05 05:41:05 PM PDT 24
Finished Jul 05 05:41:26 PM PDT 24
Peak memory 199908 kb
Host smart-18d724bb-0e6f-46d6-b9eb-403e61c7da68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736600932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2736600932
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2393498394
Short name T187
Test name
Test status
Simulation time 23132941411 ps
CPU time 37.88 seconds
Started Jul 05 05:41:16 PM PDT 24
Finished Jul 05 05:41:54 PM PDT 24
Peak memory 199912 kb
Host smart-6583a55c-ad6d-425f-add8-7cabcc8264d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393498394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2393498394
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.696097312
Short name T892
Test name
Test status
Simulation time 15329969322 ps
CPU time 22.26 seconds
Started Jul 05 05:41:06 PM PDT 24
Finished Jul 05 05:41:29 PM PDT 24
Peak memory 199940 kb
Host smart-6ae8feff-73e3-440b-931c-36ee9a56d4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696097312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.696097312
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2007810896
Short name T919
Test name
Test status
Simulation time 18490219 ps
CPU time 0.56 seconds
Started Jul 05 05:38:14 PM PDT 24
Finished Jul 05 05:38:15 PM PDT 24
Peak memory 195332 kb
Host smart-a1738267-b5ea-4321-b722-49a0e50b303d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007810896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2007810896
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.115566899
Short name T303
Test name
Test status
Simulation time 43271849101 ps
CPU time 29.69 seconds
Started Jul 05 05:38:21 PM PDT 24
Finished Jul 05 05:38:52 PM PDT 24
Peak memory 199868 kb
Host smart-71e5eb5d-2134-4df5-beac-ea7c58027974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115566899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.115566899
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3845742236
Short name T921
Test name
Test status
Simulation time 103200884758 ps
CPU time 41.95 seconds
Started Jul 05 05:38:31 PM PDT 24
Finished Jul 05 05:39:14 PM PDT 24
Peak memory 199992 kb
Host smart-588845c8-adb1-4c2b-804d-2ae1b17fb8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845742236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3845742236
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.766767522
Short name T1125
Test name
Test status
Simulation time 87585361573 ps
CPU time 72.45 seconds
Started Jul 05 05:38:23 PM PDT 24
Finished Jul 05 05:39:36 PM PDT 24
Peak memory 199916 kb
Host smart-e88b8d2c-d529-461e-b43d-52c153c109e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766767522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.766767522
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1117260476
Short name T682
Test name
Test status
Simulation time 1042416260 ps
CPU time 1.04 seconds
Started Jul 05 05:38:17 PM PDT 24
Finished Jul 05 05:38:18 PM PDT 24
Peak memory 195588 kb
Host smart-0c5717c1-7f37-4671-b023-e879db8749f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117260476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1117260476
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.476626730
Short name T967
Test name
Test status
Simulation time 125827094044 ps
CPU time 820.03 seconds
Started Jul 05 05:38:25 PM PDT 24
Finished Jul 05 05:52:07 PM PDT 24
Peak memory 199856 kb
Host smart-10cf3886-2fd3-4115-bb7a-1b458881e276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476626730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.476626730
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.523504176
Short name T933
Test name
Test status
Simulation time 1553364830 ps
CPU time 3.57 seconds
Started Jul 05 05:38:17 PM PDT 24
Finished Jul 05 05:38:21 PM PDT 24
Peak memory 197124 kb
Host smart-ef87cba2-2993-4917-a9e2-204a62b8cd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523504176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.523504176
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.887613278
Short name T1012
Test name
Test status
Simulation time 135323657779 ps
CPU time 118.71 seconds
Started Jul 05 05:38:13 PM PDT 24
Finished Jul 05 05:40:12 PM PDT 24
Peak memory 199868 kb
Host smart-617a13be-0853-4232-bfcf-f1233a095be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887613278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.887613278
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2284629322
Short name T465
Test name
Test status
Simulation time 22155912013 ps
CPU time 275.83 seconds
Started Jul 05 05:38:20 PM PDT 24
Finished Jul 05 05:42:57 PM PDT 24
Peak memory 199944 kb
Host smart-d2f340fb-ae66-4cd6-9f1c-e12738b81815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284629322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2284629322
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3927283028
Short name T363
Test name
Test status
Simulation time 3762058982 ps
CPU time 27.53 seconds
Started Jul 05 05:38:15 PM PDT 24
Finished Jul 05 05:38:43 PM PDT 24
Peak memory 197888 kb
Host smart-c6c967ae-9e4b-4848-88c7-588e84a27ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927283028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3927283028
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.848263806
Short name T1032
Test name
Test status
Simulation time 341587220698 ps
CPU time 562.33 seconds
Started Jul 05 05:38:15 PM PDT 24
Finished Jul 05 05:47:38 PM PDT 24
Peak memory 199996 kb
Host smart-4e9e2549-b8e8-48b6-8060-cd31860593e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848263806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.848263806
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2235953246
Short name T612
Test name
Test status
Simulation time 2131084538 ps
CPU time 2.3 seconds
Started Jul 05 05:38:14 PM PDT 24
Finished Jul 05 05:38:17 PM PDT 24
Peak memory 195596 kb
Host smart-3f08d063-23d3-4b4b-aa1b-9b561bc3b4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235953246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2235953246
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.588167516
Short name T1134
Test name
Test status
Simulation time 1005216712 ps
CPU time 1.12 seconds
Started Jul 05 05:38:16 PM PDT 24
Finished Jul 05 05:38:17 PM PDT 24
Peak memory 198332 kb
Host smart-33942670-8c1d-4ce4-a342-d78a22b0bc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588167516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.588167516
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3180606462
Short name T106
Test name
Test status
Simulation time 93183011196 ps
CPU time 97.34 seconds
Started Jul 05 05:38:20 PM PDT 24
Finished Jul 05 05:39:57 PM PDT 24
Peak memory 199624 kb
Host smart-4db1224f-b5d8-41bf-85b0-9952959f6a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180606462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3180606462
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1395468518
Short name T258
Test name
Test status
Simulation time 6057341142 ps
CPU time 17.65 seconds
Started Jul 05 05:38:17 PM PDT 24
Finished Jul 05 05:38:35 PM PDT 24
Peak memory 199908 kb
Host smart-8469695a-aa78-4004-aa15-6b858ecc6533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395468518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1395468518
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2943586111
Short name T572
Test name
Test status
Simulation time 88620803938 ps
CPU time 148.02 seconds
Started Jul 05 05:38:17 PM PDT 24
Finished Jul 05 05:40:46 PM PDT 24
Peak memory 199844 kb
Host smart-8057e88e-a1ed-4e3d-a36e-3da5c16be3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943586111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2943586111
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1128491112
Short name T413
Test name
Test status
Simulation time 109911331415 ps
CPU time 121.61 seconds
Started Jul 05 05:41:06 PM PDT 24
Finished Jul 05 05:43:08 PM PDT 24
Peak memory 199956 kb
Host smart-e4d641bb-989e-4803-ab7e-105fc3c7c537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128491112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1128491112
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2602767264
Short name T582
Test name
Test status
Simulation time 15908202564 ps
CPU time 7.03 seconds
Started Jul 05 05:41:06 PM PDT 24
Finished Jul 05 05:41:13 PM PDT 24
Peak memory 198820 kb
Host smart-41c1b38c-bfd0-441a-9a0a-3d3cf5ab6b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602767264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2602767264
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3091373573
Short name T139
Test name
Test status
Simulation time 31649673524 ps
CPU time 56.06 seconds
Started Jul 05 05:41:07 PM PDT 24
Finished Jul 05 05:42:04 PM PDT 24
Peak memory 199980 kb
Host smart-d5537265-17e2-48ce-ac9b-509236d5e72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091373573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3091373573
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2122502989
Short name T532
Test name
Test status
Simulation time 35875167708 ps
CPU time 38.01 seconds
Started Jul 05 05:41:04 PM PDT 24
Finished Jul 05 05:41:43 PM PDT 24
Peak memory 199988 kb
Host smart-b5d8f7a2-ad3d-4441-b8e7-0ae1b43dcd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122502989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2122502989
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1823504252
Short name T686
Test name
Test status
Simulation time 150065312892 ps
CPU time 53.97 seconds
Started Jul 05 05:41:06 PM PDT 24
Finished Jul 05 05:42:01 PM PDT 24
Peak memory 199900 kb
Host smart-b395a5a1-0e52-4151-a669-2f304719d478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823504252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1823504252
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1881344044
Short name T531
Test name
Test status
Simulation time 16614019096 ps
CPU time 24.52 seconds
Started Jul 05 05:41:05 PM PDT 24
Finished Jul 05 05:41:30 PM PDT 24
Peak memory 199908 kb
Host smart-9b671ecc-6da3-468f-b485-120b39f727fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881344044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1881344044
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3256225304
Short name T801
Test name
Test status
Simulation time 141859228148 ps
CPU time 132.63 seconds
Started Jul 05 05:41:05 PM PDT 24
Finished Jul 05 05:43:18 PM PDT 24
Peak memory 199932 kb
Host smart-5a5f9470-c1f0-4a11-8e43-119f38f12eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256225304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3256225304
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3434918648
Short name T1098
Test name
Test status
Simulation time 69802746922 ps
CPU time 72.1 seconds
Started Jul 05 05:42:19 PM PDT 24
Finished Jul 05 05:43:31 PM PDT 24
Peak memory 199968 kb
Host smart-65bd4af8-a720-4da0-a611-d45bb8e949cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434918648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3434918648
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3510196966
Short name T279
Test name
Test status
Simulation time 57227917213 ps
CPU time 32.7 seconds
Started Jul 05 05:41:05 PM PDT 24
Finished Jul 05 05:41:38 PM PDT 24
Peak memory 199980 kb
Host smart-ea10453a-a463-4364-b903-b0502e3fa66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510196966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3510196966
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2885833063
Short name T281
Test name
Test status
Simulation time 135730598802 ps
CPU time 44.18 seconds
Started Jul 05 05:41:05 PM PDT 24
Finished Jul 05 05:41:50 PM PDT 24
Peak memory 199816 kb
Host smart-fd1e8c06-a8dc-49b0-a34c-c63d33b1c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885833063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2885833063
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3852916992
Short name T1011
Test name
Test status
Simulation time 39248686 ps
CPU time 0.56 seconds
Started Jul 05 05:38:16 PM PDT 24
Finished Jul 05 05:38:18 PM PDT 24
Peak memory 195568 kb
Host smart-d1a9f089-7dbc-49ee-ab25-44742838f6cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852916992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3852916992
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3090307542
Short name T821
Test name
Test status
Simulation time 48204480566 ps
CPU time 80.03 seconds
Started Jul 05 05:38:15 PM PDT 24
Finished Jul 05 05:39:36 PM PDT 24
Peak memory 199860 kb
Host smart-02bbb86e-6851-491b-ac4b-0ed2e9a95a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090307542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3090307542
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1625117427
Short name T124
Test name
Test status
Simulation time 37584018560 ps
CPU time 28.5 seconds
Started Jul 05 05:38:15 PM PDT 24
Finished Jul 05 05:38:44 PM PDT 24
Peak memory 199656 kb
Host smart-5e926b09-3972-4b0b-b7b4-c2ee2142cbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625117427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1625117427
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4192045095
Short name T737
Test name
Test status
Simulation time 15068150286 ps
CPU time 26.78 seconds
Started Jul 05 05:38:16 PM PDT 24
Finished Jul 05 05:38:44 PM PDT 24
Peak memory 200000 kb
Host smart-bedc7347-378a-4805-bd83-2e1683a6ccd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192045095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4192045095
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1878491710
Short name T16
Test name
Test status
Simulation time 13340897856 ps
CPU time 9.06 seconds
Started Jul 05 05:38:20 PM PDT 24
Finished Jul 05 05:38:29 PM PDT 24
Peak memory 199968 kb
Host smart-325d4c87-2c9f-4dd3-993c-247be0bbd125
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878491710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1878491710
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2131549877
Short name T621
Test name
Test status
Simulation time 46956003978 ps
CPU time 68.44 seconds
Started Jul 05 05:38:21 PM PDT 24
Finished Jul 05 05:39:31 PM PDT 24
Peak memory 199872 kb
Host smart-e805576a-be0e-4504-a50d-accd8cd5ce69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2131549877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2131549877
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2744457237
Short name T720
Test name
Test status
Simulation time 3816910146 ps
CPU time 8.02 seconds
Started Jul 05 05:38:23 PM PDT 24
Finished Jul 05 05:38:32 PM PDT 24
Peak memory 198696 kb
Host smart-7142434f-9ad6-47a4-a789-fe5d30f7392b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744457237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2744457237
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1557913816
Short name T814
Test name
Test status
Simulation time 12607963928 ps
CPU time 12.43 seconds
Started Jul 05 05:38:17 PM PDT 24
Finished Jul 05 05:38:31 PM PDT 24
Peak memory 200072 kb
Host smart-5f7208ba-2f8a-4ea6-89b4-545ac1e89fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557913816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1557913816
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.378101381
Short name T568
Test name
Test status
Simulation time 14295216443 ps
CPU time 425.84 seconds
Started Jul 05 05:38:14 PM PDT 24
Finished Jul 05 05:45:20 PM PDT 24
Peak memory 199840 kb
Host smart-0a025838-c7ad-4c91-bbc1-2bdcec507195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378101381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.378101381
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.299536203
Short name T326
Test name
Test status
Simulation time 4694018453 ps
CPU time 39.76 seconds
Started Jul 05 05:38:14 PM PDT 24
Finished Jul 05 05:38:55 PM PDT 24
Peak memory 198864 kb
Host smart-0bda27ff-8711-415b-b294-48292e8c7f48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=299536203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.299536203
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1837117553
Short name T358
Test name
Test status
Simulation time 51868608146 ps
CPU time 39.76 seconds
Started Jul 05 05:38:16 PM PDT 24
Finished Jul 05 05:38:56 PM PDT 24
Peak memory 199992 kb
Host smart-1eec95b0-80c5-4cc2-8ec0-609f75f9488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837117553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1837117553
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2482730340
Short name T707
Test name
Test status
Simulation time 33189766607 ps
CPU time 51.81 seconds
Started Jul 05 05:38:18 PM PDT 24
Finished Jul 05 05:39:10 PM PDT 24
Peak memory 196740 kb
Host smart-1053a9af-413d-4912-bb7a-dada8caca9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482730340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2482730340
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3104976675
Short name T1038
Test name
Test status
Simulation time 719409786 ps
CPU time 1.47 seconds
Started Jul 05 05:38:17 PM PDT 24
Finished Jul 05 05:38:19 PM PDT 24
Peak memory 199772 kb
Host smart-6d72e711-a429-4ba1-b59e-b73af7bfa115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104976675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3104976675
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3618921452
Short name T878
Test name
Test status
Simulation time 33726438096 ps
CPU time 152.93 seconds
Started Jul 05 05:38:15 PM PDT 24
Finished Jul 05 05:40:48 PM PDT 24
Peak memory 199980 kb
Host smart-e91eff20-67c8-4744-ab05-83fa47aa93a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618921452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3618921452
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2462724484
Short name T1005
Test name
Test status
Simulation time 215470917852 ps
CPU time 575.23 seconds
Started Jul 05 05:38:12 PM PDT 24
Finished Jul 05 05:47:48 PM PDT 24
Peak memory 224912 kb
Host smart-5099515b-b830-4576-a021-c64b7e733a94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462724484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2462724484
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1375908726
Short name T718
Test name
Test status
Simulation time 2018548908 ps
CPU time 1.66 seconds
Started Jul 05 05:38:16 PM PDT 24
Finished Jul 05 05:38:18 PM PDT 24
Peak memory 198356 kb
Host smart-074f5ed5-1b54-4164-93e0-8398adb3e91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375908726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1375908726
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.216811589
Short name T34
Test name
Test status
Simulation time 112667534961 ps
CPU time 232.86 seconds
Started Jul 05 05:38:17 PM PDT 24
Finished Jul 05 05:42:11 PM PDT 24
Peak memory 199912 kb
Host smart-d71e1f14-5a5b-46a8-9cf7-62e2b26eab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216811589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.216811589
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.901573591
Short name T1112
Test name
Test status
Simulation time 8821884588 ps
CPU time 15.63 seconds
Started Jul 05 05:41:08 PM PDT 24
Finished Jul 05 05:41:24 PM PDT 24
Peak memory 199952 kb
Host smart-6cdd3749-a346-4449-ada0-8a9bd6a1fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901573591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.901573591
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2303588378
Short name T986
Test name
Test status
Simulation time 48150730563 ps
CPU time 35.41 seconds
Started Jul 05 05:41:09 PM PDT 24
Finished Jul 05 05:41:44 PM PDT 24
Peak memory 199936 kb
Host smart-4ac62474-0cd7-4e51-b32a-ec707a1f1033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303588378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2303588378
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2984509859
Short name T798
Test name
Test status
Simulation time 163274281427 ps
CPU time 125.03 seconds
Started Jul 05 05:41:16 PM PDT 24
Finished Jul 05 05:43:21 PM PDT 24
Peak memory 199960 kb
Host smart-eb9e74c9-7b43-4a9e-90b0-ce560d72c659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984509859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2984509859
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.995636547
Short name T289
Test name
Test status
Simulation time 17092744491 ps
CPU time 24.26 seconds
Started Jul 05 05:41:05 PM PDT 24
Finished Jul 05 05:41:30 PM PDT 24
Peak memory 199924 kb
Host smart-c48972d1-a609-40a4-97f6-85d97692261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995636547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.995636547
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.12173811
Short name T930
Test name
Test status
Simulation time 27889569236 ps
CPU time 45.34 seconds
Started Jul 05 05:41:05 PM PDT 24
Finished Jul 05 05:41:51 PM PDT 24
Peak memory 199960 kb
Host smart-2b100c16-b208-434a-8ef5-ab108d4490e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12173811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.12173811
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1325045994
Short name T553
Test name
Test status
Simulation time 22974945913 ps
CPU time 35.51 seconds
Started Jul 05 05:41:10 PM PDT 24
Finished Jul 05 05:41:46 PM PDT 24
Peak memory 199976 kb
Host smart-e5478306-f863-4fb1-8c4b-175006220b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325045994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1325045994
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2949174905
Short name T680
Test name
Test status
Simulation time 93332356060 ps
CPU time 26.54 seconds
Started Jul 05 05:41:06 PM PDT 24
Finished Jul 05 05:41:33 PM PDT 24
Peak memory 199988 kb
Host smart-42744690-c0cf-4ea8-9bbd-3c2aa73f899a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949174905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2949174905
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1782929494
Short name T428
Test name
Test status
Simulation time 83529812110 ps
CPU time 36.01 seconds
Started Jul 05 05:41:09 PM PDT 24
Finished Jul 05 05:41:45 PM PDT 24
Peak memory 199448 kb
Host smart-c1da884e-c01b-494c-be9e-4b26b3861249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782929494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1782929494
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3331521596
Short name T460
Test name
Test status
Simulation time 102232219029 ps
CPU time 157.87 seconds
Started Jul 05 05:41:17 PM PDT 24
Finished Jul 05 05:43:55 PM PDT 24
Peak memory 199900 kb
Host smart-1a8787ba-b824-4838-95e1-db14c36ddb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331521596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3331521596
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1266704902
Short name T861
Test name
Test status
Simulation time 38114570 ps
CPU time 0.56 seconds
Started Jul 05 05:38:21 PM PDT 24
Finished Jul 05 05:38:22 PM PDT 24
Peak memory 195268 kb
Host smart-102a0ca5-106d-4936-93e9-a9bfe39fedfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266704902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1266704902
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1805378619
Short name T946
Test name
Test status
Simulation time 95691793351 ps
CPU time 135.58 seconds
Started Jul 05 05:38:18 PM PDT 24
Finished Jul 05 05:40:35 PM PDT 24
Peak memory 199928 kb
Host smart-06dd4747-aa3f-474d-810e-d9db0bcd6ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805378619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1805378619
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3996356491
Short name T120
Test name
Test status
Simulation time 20268443428 ps
CPU time 61.07 seconds
Started Jul 05 05:38:25 PM PDT 24
Finished Jul 05 05:39:28 PM PDT 24
Peak memory 199916 kb
Host smart-8420f374-5ab1-45f2-b672-1ad3ac718014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996356491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3996356491
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.4274572313
Short name T343
Test name
Test status
Simulation time 62970293930 ps
CPU time 17.31 seconds
Started Jul 05 05:38:17 PM PDT 24
Finished Jul 05 05:38:35 PM PDT 24
Peak memory 199904 kb
Host smart-a74f7040-cc0c-4f12-9d1c-162676c74b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274572313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.4274572313
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2712105861
Short name T251
Test name
Test status
Simulation time 57351333166 ps
CPU time 86.83 seconds
Started Jul 05 05:38:16 PM PDT 24
Finished Jul 05 05:39:43 PM PDT 24
Peak memory 199820 kb
Host smart-a62fb2a6-79f1-448e-8734-9468b6bcf526
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712105861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2712105861
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3231001917
Short name T1167
Test name
Test status
Simulation time 67684469430 ps
CPU time 564.28 seconds
Started Jul 05 05:38:35 PM PDT 24
Finished Jul 05 05:48:01 PM PDT 24
Peak memory 199240 kb
Host smart-aeed6cf0-ddaf-44b6-a02b-d94921c32f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231001917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3231001917
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.4077441054
Short name T311
Test name
Test status
Simulation time 4233303157 ps
CPU time 4.23 seconds
Started Jul 05 05:38:26 PM PDT 24
Finished Jul 05 05:38:31 PM PDT 24
Peak memory 197336 kb
Host smart-02fe8ae7-f1a6-4120-96f6-5cee8db12ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077441054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.4077441054
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3851528489
Short name T276
Test name
Test status
Simulation time 35564938893 ps
CPU time 45.56 seconds
Started Jul 05 05:38:14 PM PDT 24
Finished Jul 05 05:39:00 PM PDT 24
Peak memory 200192 kb
Host smart-4c964e60-7b69-4cd5-beaf-247d65860112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851528489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3851528489
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2826760986
Short name T636
Test name
Test status
Simulation time 28093877648 ps
CPU time 366.52 seconds
Started Jul 05 05:38:29 PM PDT 24
Finished Jul 05 05:44:36 PM PDT 24
Peak memory 200004 kb
Host smart-a2c499ec-360e-41bc-abf2-b630ddb441c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826760986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2826760986
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.849877533
Short name T1174
Test name
Test status
Simulation time 4198206710 ps
CPU time 8.69 seconds
Started Jul 05 05:38:20 PM PDT 24
Finished Jul 05 05:38:29 PM PDT 24
Peak memory 198332 kb
Host smart-2f88a0f7-cfb0-4992-84f7-0bb464faf5da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=849877533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.849877533
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.437116291
Short name T901
Test name
Test status
Simulation time 122659398367 ps
CPU time 44.05 seconds
Started Jul 05 05:38:18 PM PDT 24
Finished Jul 05 05:39:03 PM PDT 24
Peak memory 199876 kb
Host smart-981855d0-f135-4a2f-b06e-4fce02d42c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437116291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.437116291
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.695067401
Short name T736
Test name
Test status
Simulation time 5164397270 ps
CPU time 2.31 seconds
Started Jul 05 05:38:16 PM PDT 24
Finished Jul 05 05:38:19 PM PDT 24
Peak memory 196700 kb
Host smart-1fff9282-ba70-4a0f-b204-3f345e792b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695067401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.695067401
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3793946864
Short name T366
Test name
Test status
Simulation time 5752228799 ps
CPU time 7.63 seconds
Started Jul 05 05:38:25 PM PDT 24
Finished Jul 05 05:38:34 PM PDT 24
Peak memory 199000 kb
Host smart-28a69d6b-e7f2-4a21-af24-184ed9d994b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793946864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3793946864
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2012005547
Short name T300
Test name
Test status
Simulation time 324230006295 ps
CPU time 272.95 seconds
Started Jul 05 05:38:22 PM PDT 24
Finished Jul 05 05:42:56 PM PDT 24
Peak memory 215772 kb
Host smart-96bac0be-3f4c-4371-a538-426311ce4376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012005547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2012005547
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1185835664
Short name T154
Test name
Test status
Simulation time 739885350053 ps
CPU time 1332.43 seconds
Started Jul 05 05:38:35 PM PDT 24
Finished Jul 05 06:00:49 PM PDT 24
Peak memory 227340 kb
Host smart-47d16b7f-7b90-4ebd-ac4b-868d7386f842
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185835664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1185835664
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2996152716
Short name T830
Test name
Test status
Simulation time 812336010 ps
CPU time 3.5 seconds
Started Jul 05 05:38:24 PM PDT 24
Finished Jul 05 05:38:29 PM PDT 24
Peak memory 198368 kb
Host smart-fab0ab30-4977-4799-9150-15f75e7257e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996152716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2996152716
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.775930406
Short name T261
Test name
Test status
Simulation time 126768185577 ps
CPU time 98.91 seconds
Started Jul 05 05:38:17 PM PDT 24
Finished Jul 05 05:39:57 PM PDT 24
Peak memory 199948 kb
Host smart-9ba9a3eb-3e35-443e-b105-58f691b1c970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775930406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.775930406
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1416972637
Short name T616
Test name
Test status
Simulation time 35140668566 ps
CPU time 12.02 seconds
Started Jul 05 05:41:15 PM PDT 24
Finished Jul 05 05:41:28 PM PDT 24
Peak memory 199924 kb
Host smart-55f445a8-5ff8-4bb5-aab5-ea0a53c85251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416972637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1416972637
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1221286339
Short name T848
Test name
Test status
Simulation time 4472458068 ps
CPU time 8.24 seconds
Started Jul 05 05:41:15 PM PDT 24
Finished Jul 05 05:41:24 PM PDT 24
Peak memory 199540 kb
Host smart-1c6f1bae-1a97-4a49-8c93-6ef202910b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221286339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1221286339
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3261903418
Short name T1055
Test name
Test status
Simulation time 169025909564 ps
CPU time 46.51 seconds
Started Jul 05 05:41:13 PM PDT 24
Finished Jul 05 05:42:00 PM PDT 24
Peak memory 199996 kb
Host smart-016dd7c3-b32a-4f16-9e99-b12fef064c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261903418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3261903418
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1657213765
Short name T787
Test name
Test status
Simulation time 33299412000 ps
CPU time 72.35 seconds
Started Jul 05 05:41:28 PM PDT 24
Finished Jul 05 05:42:41 PM PDT 24
Peak memory 200020 kb
Host smart-f10e29ad-7c6a-4600-b987-75226a8a0d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657213765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1657213765
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1860326095
Short name T95
Test name
Test status
Simulation time 182051889072 ps
CPU time 67.27 seconds
Started Jul 05 05:41:13 PM PDT 24
Finished Jul 05 05:42:21 PM PDT 24
Peak memory 199840 kb
Host smart-33879f0c-330f-450a-80be-e2cabacad55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860326095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1860326095
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.4116429567
Short name T625
Test name
Test status
Simulation time 11794445826 ps
CPU time 17.02 seconds
Started Jul 05 05:41:14 PM PDT 24
Finished Jul 05 05:41:31 PM PDT 24
Peak memory 199692 kb
Host smart-be2c1438-22cf-47ad-920b-01e61382dcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116429567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.4116429567
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3076436095
Short name T809
Test name
Test status
Simulation time 52908247551 ps
CPU time 109.74 seconds
Started Jul 05 05:41:13 PM PDT 24
Finished Jul 05 05:43:03 PM PDT 24
Peak memory 199932 kb
Host smart-9b88e5e2-4559-4669-be62-0e9abfdf22ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076436095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3076436095
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.824249001
Short name T884
Test name
Test status
Simulation time 31229111690 ps
CPU time 25.22 seconds
Started Jul 05 05:41:13 PM PDT 24
Finished Jul 05 05:41:39 PM PDT 24
Peak memory 200224 kb
Host smart-ad9bbb76-8162-4a8a-8a7d-069dec935b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824249001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.824249001
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3206600294
Short name T1084
Test name
Test status
Simulation time 65065527565 ps
CPU time 42.72 seconds
Started Jul 05 05:41:12 PM PDT 24
Finished Jul 05 05:41:55 PM PDT 24
Peak memory 199948 kb
Host smart-0eb610a2-f853-4e58-b2d6-ccf21b408dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206600294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3206600294
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1055899966
Short name T1105
Test name
Test status
Simulation time 18942948 ps
CPU time 0.57 seconds
Started Jul 05 05:37:10 PM PDT 24
Finished Jul 05 05:37:11 PM PDT 24
Peak memory 194744 kb
Host smart-5fbd4448-6f47-4b11-a776-ef7c93135a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055899966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1055899966
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1817210336
Short name T395
Test name
Test status
Simulation time 98150330046 ps
CPU time 37.61 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:37:36 PM PDT 24
Peak memory 199988 kb
Host smart-ac973efe-b220-4d30-b3f3-3109a9b94aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817210336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1817210336
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.418882101
Short name T618
Test name
Test status
Simulation time 102934257435 ps
CPU time 41.18 seconds
Started Jul 05 05:36:57 PM PDT 24
Finished Jul 05 05:37:39 PM PDT 24
Peak memory 199940 kb
Host smart-65e8e72d-5bb6-4f74-a592-4c3ec503bc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418882101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.418882101
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.4104038473
Short name T1139
Test name
Test status
Simulation time 100544106445 ps
CPU time 46.54 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:37:46 PM PDT 24
Peak memory 199992 kb
Host smart-2d9fa26e-ece9-4b6d-af78-ba33a5a857ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104038473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4104038473
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1378166793
Short name T62
Test name
Test status
Simulation time 2606801537 ps
CPU time 2.84 seconds
Started Jul 05 05:36:57 PM PDT 24
Finished Jul 05 05:37:01 PM PDT 24
Peak memory 198628 kb
Host smart-7c6eb071-4eb1-40fc-ae8d-6a224f657e6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378166793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1378166793
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.907831819
Short name T356
Test name
Test status
Simulation time 187478951917 ps
CPU time 667.06 seconds
Started Jul 05 05:37:08 PM PDT 24
Finished Jul 05 05:48:16 PM PDT 24
Peak memory 199980 kb
Host smart-4743262a-5444-4a3a-a23d-f40494ebd635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907831819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.907831819
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3365717904
Short name T949
Test name
Test status
Simulation time 5885763524 ps
CPU time 25.3 seconds
Started Jul 05 05:37:09 PM PDT 24
Finished Jul 05 05:37:35 PM PDT 24
Peak memory 199384 kb
Host smart-ee4bada9-1cd5-4128-b7c4-743640bca0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365717904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3365717904
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3582542701
Short name T551
Test name
Test status
Simulation time 14348357621 ps
CPU time 7.29 seconds
Started Jul 05 05:37:17 PM PDT 24
Finished Jul 05 05:37:26 PM PDT 24
Peak memory 198268 kb
Host smart-d4e9d9b6-9e71-4fe5-aa4c-b5f9f2811fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582542701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3582542701
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3552061806
Short name T969
Test name
Test status
Simulation time 9452748153 ps
CPU time 420.7 seconds
Started Jul 05 05:37:04 PM PDT 24
Finished Jul 05 05:44:07 PM PDT 24
Peak memory 199872 kb
Host smart-4ee046b9-1065-4a42-9e18-0bab15d5c5bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552061806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3552061806
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3842333726
Short name T420
Test name
Test status
Simulation time 5500589539 ps
CPU time 12.57 seconds
Started Jul 05 05:37:06 PM PDT 24
Finished Jul 05 05:37:20 PM PDT 24
Peak memory 198128 kb
Host smart-07bc893e-27ff-42be-b3b7-5cedd7d495ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842333726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3842333726
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2994741067
Short name T866
Test name
Test status
Simulation time 12546426057 ps
CPU time 34.4 seconds
Started Jul 05 05:36:58 PM PDT 24
Finished Jul 05 05:37:33 PM PDT 24
Peak memory 199948 kb
Host smart-c389b6cc-7b9a-4b66-aed2-9ec31b488d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994741067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2994741067
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.777734794
Short name T978
Test name
Test status
Simulation time 4389285125 ps
CPU time 2.32 seconds
Started Jul 05 05:37:09 PM PDT 24
Finished Jul 05 05:37:12 PM PDT 24
Peak memory 196020 kb
Host smart-933e0ca2-9782-4b74-a3f8-23adff09dd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777734794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.777734794
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2045416996
Short name T27
Test name
Test status
Simulation time 118365750 ps
CPU time 0.78 seconds
Started Jul 05 05:37:04 PM PDT 24
Finished Jul 05 05:37:07 PM PDT 24
Peak memory 218416 kb
Host smart-584a95e7-fe2a-49c5-8a77-349c60bdbb7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045416996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2045416996
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1967748398
Short name T361
Test name
Test status
Simulation time 719163176 ps
CPU time 1.63 seconds
Started Jul 05 05:37:01 PM PDT 24
Finished Jul 05 05:37:04 PM PDT 24
Peak memory 198556 kb
Host smart-41beefee-5112-4cc9-95c2-a94e94d31415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967748398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1967748398
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1585343409
Short name T1014
Test name
Test status
Simulation time 95928576198 ps
CPU time 825.67 seconds
Started Jul 05 05:37:04 PM PDT 24
Finished Jul 05 05:50:52 PM PDT 24
Peak memory 225804 kb
Host smart-216c950c-475e-491a-9f6d-989076a7222b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585343409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1585343409
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1649418623
Short name T950
Test name
Test status
Simulation time 6138479061 ps
CPU time 16.6 seconds
Started Jul 05 05:37:09 PM PDT 24
Finished Jul 05 05:37:26 PM PDT 24
Peak memory 199832 kb
Host smart-93cf4dcb-8b52-4ccb-854d-a82a072350a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649418623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1649418623
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3858278689
Short name T1031
Test name
Test status
Simulation time 32861886294 ps
CPU time 114.97 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:38:58 PM PDT 24
Peak memory 199932 kb
Host smart-4b223958-d326-4d1e-9ac5-0fca3242fadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858278689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3858278689
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1952378168
Short name T23
Test name
Test status
Simulation time 10959516 ps
CPU time 0.58 seconds
Started Jul 05 05:38:27 PM PDT 24
Finished Jul 05 05:38:28 PM PDT 24
Peak memory 195332 kb
Host smart-068342af-c7be-47ba-9910-d1683f323d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952378168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1952378168
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1388784384
Short name T163
Test name
Test status
Simulation time 162017119135 ps
CPU time 67.55 seconds
Started Jul 05 05:38:26 PM PDT 24
Finished Jul 05 05:39:35 PM PDT 24
Peak memory 199312 kb
Host smart-bfeb2caa-0d5a-48a2-b6d1-e7fb23b8c790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388784384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1388784384
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3319853241
Short name T442
Test name
Test status
Simulation time 11533823922 ps
CPU time 15.35 seconds
Started Jul 05 05:38:24 PM PDT 24
Finished Jul 05 05:38:40 PM PDT 24
Peak memory 199940 kb
Host smart-a1b4bbd2-085f-494a-bbe2-f7f3c8b3b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319853241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3319853241
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.244829152
Short name T1097
Test name
Test status
Simulation time 44072963249 ps
CPU time 19.68 seconds
Started Jul 05 05:38:25 PM PDT 24
Finished Jul 05 05:38:45 PM PDT 24
Peak memory 199524 kb
Host smart-abf0f5fd-2bf7-4862-9463-e09e491ffb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244829152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.244829152
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3425484151
Short name T336
Test name
Test status
Simulation time 9700893834 ps
CPU time 3.62 seconds
Started Jul 05 05:38:23 PM PDT 24
Finished Jul 05 05:38:27 PM PDT 24
Peak memory 198088 kb
Host smart-3b648318-dee3-4d9e-b1ec-d32dfa2fceab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425484151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3425484151
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1531178855
Short name T608
Test name
Test status
Simulation time 63763806295 ps
CPU time 228.03 seconds
Started Jul 05 05:38:21 PM PDT 24
Finished Jul 05 05:42:10 PM PDT 24
Peak memory 199984 kb
Host smart-ac77575b-b27d-41fe-b646-b3d0fc3cf9cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531178855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1531178855
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2867216733
Short name T312
Test name
Test status
Simulation time 5036940955 ps
CPU time 11.17 seconds
Started Jul 05 05:38:22 PM PDT 24
Finished Jul 05 05:38:34 PM PDT 24
Peak memory 199984 kb
Host smart-c5f643c2-1d1d-480f-b5aa-8e2e0582f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867216733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2867216733
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2231758949
Short name T639
Test name
Test status
Simulation time 104104219433 ps
CPU time 74.64 seconds
Started Jul 05 05:38:29 PM PDT 24
Finished Jul 05 05:39:44 PM PDT 24
Peak memory 200168 kb
Host smart-36f3e970-7cfe-44f8-9b67-b42031a73325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231758949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2231758949
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.338023175
Short name T414
Test name
Test status
Simulation time 18354263579 ps
CPU time 953.7 seconds
Started Jul 05 05:38:25 PM PDT 24
Finished Jul 05 05:54:20 PM PDT 24
Peak memory 199896 kb
Host smart-10dc9d34-eaef-47cd-9d19-f396c83eb385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338023175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.338023175
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.320886992
Short name T329
Test name
Test status
Simulation time 8016281346 ps
CPU time 70.16 seconds
Started Jul 05 05:38:39 PM PDT 24
Finished Jul 05 05:39:49 PM PDT 24
Peak memory 198080 kb
Host smart-f19b1161-b80a-48f9-96c5-9a5482561d38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=320886992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.320886992
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.335262165
Short name T1132
Test name
Test status
Simulation time 24573701122 ps
CPU time 18.59 seconds
Started Jul 05 05:38:26 PM PDT 24
Finished Jul 05 05:38:45 PM PDT 24
Peak memory 199584 kb
Host smart-6be8457c-291f-453f-a8c5-c98c8ce4729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335262165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.335262165
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.160874456
Short name T577
Test name
Test status
Simulation time 2817985931 ps
CPU time 2.64 seconds
Started Jul 05 05:38:26 PM PDT 24
Finished Jul 05 05:38:29 PM PDT 24
Peak memory 195936 kb
Host smart-56e3071d-dcee-493a-b1c4-954941285271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160874456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.160874456
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.4210205541
Short name T1137
Test name
Test status
Simulation time 466514957 ps
CPU time 2.73 seconds
Started Jul 05 05:38:24 PM PDT 24
Finished Jul 05 05:38:28 PM PDT 24
Peak memory 198768 kb
Host smart-315cf420-aa3a-4589-be2d-fcdd31a792ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210205541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.4210205541
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.284437560
Short name T522
Test name
Test status
Simulation time 22434289485 ps
CPU time 251.05 seconds
Started Jul 05 05:38:26 PM PDT 24
Finished Jul 05 05:42:38 PM PDT 24
Peak memory 208244 kb
Host smart-86580e30-6236-426f-bbd1-185d43663f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284437560 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.284437560
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.4251179660
Short name T838
Test name
Test status
Simulation time 1083908106 ps
CPU time 1.7 seconds
Started Jul 05 05:38:22 PM PDT 24
Finished Jul 05 05:38:25 PM PDT 24
Peak memory 198008 kb
Host smart-55818aa9-4f92-4416-be77-70ba02b1ccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251179660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.4251179660
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1143173284
Short name T1130
Test name
Test status
Simulation time 97280307923 ps
CPU time 114.71 seconds
Started Jul 05 05:38:26 PM PDT 24
Finished Jul 05 05:40:22 PM PDT 24
Peak memory 199564 kb
Host smart-ccdd9e7c-1408-4441-a28a-fb64453d0538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143173284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1143173284
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1477607420
Short name T1053
Test name
Test status
Simulation time 17289893 ps
CPU time 0.63 seconds
Started Jul 05 05:38:24 PM PDT 24
Finished Jul 05 05:38:25 PM PDT 24
Peak memory 195324 kb
Host smart-4fd1b875-dc05-418a-8d50-9d2a85be6c3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477607420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1477607420
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.4198305910
Short name T654
Test name
Test status
Simulation time 134882453065 ps
CPU time 218.41 seconds
Started Jul 05 05:38:21 PM PDT 24
Finished Jul 05 05:42:00 PM PDT 24
Peak memory 199936 kb
Host smart-471fffa4-0a3a-4eed-ba11-4d87e5fa9998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198305910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.4198305910
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3807966426
Short name T1079
Test name
Test status
Simulation time 52085055881 ps
CPU time 19.26 seconds
Started Jul 05 05:38:35 PM PDT 24
Finished Jul 05 05:38:56 PM PDT 24
Peak memory 199220 kb
Host smart-6a4511c1-94ad-4e92-a286-a702944a2903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807966426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3807966426
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_intr.3651703002
Short name T569
Test name
Test status
Simulation time 83662543508 ps
CPU time 31.46 seconds
Started Jul 05 05:38:27 PM PDT 24
Finished Jul 05 05:38:59 PM PDT 24
Peak memory 197068 kb
Host smart-7087ef2f-94f8-42df-bcfb-fd455411da63
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651703002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3651703002
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1529063139
Short name T254
Test name
Test status
Simulation time 81320066103 ps
CPU time 504.2 seconds
Started Jul 05 05:38:24 PM PDT 24
Finished Jul 05 05:46:49 PM PDT 24
Peak memory 200224 kb
Host smart-eaac547b-8615-443a-a73f-5cb87d9b57b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529063139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1529063139
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.397553222
Short name T629
Test name
Test status
Simulation time 10897375988 ps
CPU time 11.4 seconds
Started Jul 05 05:38:24 PM PDT 24
Finished Jul 05 05:38:36 PM PDT 24
Peak memory 199528 kb
Host smart-7bb8d40c-858b-473a-9a3b-d2d45b1da190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397553222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.397553222
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.17486316
Short name T620
Test name
Test status
Simulation time 15969529824 ps
CPU time 27.26 seconds
Started Jul 05 05:38:26 PM PDT 24
Finished Jul 05 05:38:55 PM PDT 24
Peak memory 198848 kb
Host smart-9b4836c2-b2ab-4894-bf67-bac1464e6cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17486316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.17486316
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.423732457
Short name T362
Test name
Test status
Simulation time 24660564442 ps
CPU time 1348.28 seconds
Started Jul 05 05:38:25 PM PDT 24
Finished Jul 05 06:00:55 PM PDT 24
Peak memory 199952 kb
Host smart-41a921b5-7ee8-4b2f-bee9-21671bc512ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423732457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.423732457
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2529929848
Short name T61
Test name
Test status
Simulation time 1354215280 ps
CPU time 0.84 seconds
Started Jul 05 05:38:22 PM PDT 24
Finished Jul 05 05:38:24 PM PDT 24
Peak memory 198108 kb
Host smart-efa4d9f4-13ec-468a-8a70-48588ee03cf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2529929848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2529929848
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3306408684
Short name T125
Test name
Test status
Simulation time 49321523508 ps
CPU time 11.02 seconds
Started Jul 05 05:38:36 PM PDT 24
Finished Jul 05 05:38:48 PM PDT 24
Peak memory 199904 kb
Host smart-a2d9a57f-49e2-4261-b76e-c84c6b903baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306408684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3306408684
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1030375941
Short name T1009
Test name
Test status
Simulation time 1743938333 ps
CPU time 2.77 seconds
Started Jul 05 05:38:35 PM PDT 24
Finished Jul 05 05:38:39 PM PDT 24
Peak memory 195328 kb
Host smart-35aeb668-db35-4adc-8ddd-82411e4418d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030375941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1030375941
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.4267564761
Short name T4
Test name
Test status
Simulation time 700563934 ps
CPU time 2.63 seconds
Started Jul 05 05:38:21 PM PDT 24
Finished Jul 05 05:38:24 PM PDT 24
Peak memory 199660 kb
Host smart-f7456052-6b55-44e9-be78-019451b26895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267564761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4267564761
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.4251900976
Short name T173
Test name
Test status
Simulation time 169209640949 ps
CPU time 443.98 seconds
Started Jul 05 05:38:23 PM PDT 24
Finished Jul 05 05:45:48 PM PDT 24
Peak memory 199912 kb
Host smart-ac143d7d-b1c6-4b00-836b-b9f99def36f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251900976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.4251900976
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.4015821996
Short name T539
Test name
Test status
Simulation time 304167054931 ps
CPU time 999.33 seconds
Started Jul 05 05:38:24 PM PDT 24
Finished Jul 05 05:55:04 PM PDT 24
Peak memory 224876 kb
Host smart-f9d44e19-4e68-4f6d-85c2-c70319c2b02e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015821996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.4015821996
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.340688649
Short name T761
Test name
Test status
Simulation time 1199315273 ps
CPU time 2.87 seconds
Started Jul 05 05:38:23 PM PDT 24
Finished Jul 05 05:38:26 PM PDT 24
Peak memory 199844 kb
Host smart-c9c63cf8-3576-498a-ae18-a9a51ee5c4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340688649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.340688649
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1208718109
Short name T245
Test name
Test status
Simulation time 75663593193 ps
CPU time 123.72 seconds
Started Jul 05 05:38:27 PM PDT 24
Finished Jul 05 05:40:32 PM PDT 24
Peak memory 199900 kb
Host smart-39d989c9-96e6-4ca6-a53e-ce54099f5c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208718109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1208718109
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3164967026
Short name T520
Test name
Test status
Simulation time 13685403 ps
CPU time 0.59 seconds
Started Jul 05 05:38:33 PM PDT 24
Finished Jul 05 05:38:34 PM PDT 24
Peak memory 195328 kb
Host smart-971a13ee-7d53-449d-894a-bc58184d1907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164967026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3164967026
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.47633517
Short name T505
Test name
Test status
Simulation time 186786084586 ps
CPU time 287.65 seconds
Started Jul 05 05:38:33 PM PDT 24
Finished Jul 05 05:43:22 PM PDT 24
Peak memory 200004 kb
Host smart-00b12901-1f46-49b2-be85-552f1d902de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47633517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.47633517
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.19436997
Short name T156
Test name
Test status
Simulation time 7086433424 ps
CPU time 3.84 seconds
Started Jul 05 05:38:32 PM PDT 24
Finished Jul 05 05:38:36 PM PDT 24
Peak memory 199912 kb
Host smart-cc39ab09-83c3-4afb-bcb5-ee122322a776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19436997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.19436997
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1610574378
Short name T898
Test name
Test status
Simulation time 29833938944 ps
CPU time 13.02 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:38:48 PM PDT 24
Peak memory 199940 kb
Host smart-28738814-6ec7-47d2-a557-97d9ee34b482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610574378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1610574378
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2302956716
Short name T927
Test name
Test status
Simulation time 264861441932 ps
CPU time 242.69 seconds
Started Jul 05 05:38:37 PM PDT 24
Finished Jul 05 05:42:40 PM PDT 24
Peak memory 200008 kb
Host smart-3846e163-ac53-4ad7-b3f9-15434f8175de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302956716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2302956716
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1531745382
Short name T1126
Test name
Test status
Simulation time 78922574867 ps
CPU time 308.26 seconds
Started Jul 05 05:38:35 PM PDT 24
Finished Jul 05 05:43:44 PM PDT 24
Peak memory 199896 kb
Host smart-03cf5c84-4182-419b-a02f-c37653e8778a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531745382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1531745382
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2877090443
Short name T521
Test name
Test status
Simulation time 6644412801 ps
CPU time 13.25 seconds
Started Jul 05 05:38:33 PM PDT 24
Finished Jul 05 05:38:47 PM PDT 24
Peak memory 199512 kb
Host smart-c7d1fcda-6601-45db-b9d6-e11516718533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877090443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2877090443
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.848118284
Short name T1028
Test name
Test status
Simulation time 122066577738 ps
CPU time 56.54 seconds
Started Jul 05 05:38:32 PM PDT 24
Finished Jul 05 05:39:29 PM PDT 24
Peak memory 198912 kb
Host smart-85f5d1c3-07ba-4289-ac96-aebe9db0c0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848118284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.848118284
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.372297481
Short name T974
Test name
Test status
Simulation time 13359775462 ps
CPU time 598.19 seconds
Started Jul 05 05:38:35 PM PDT 24
Finished Jul 05 05:48:34 PM PDT 24
Peak memory 200004 kb
Host smart-0a69cd50-67f8-4379-8ce2-eb8399f7aff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=372297481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.372297481
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2219121398
Short name T622
Test name
Test status
Simulation time 1508011068 ps
CPU time 1.77 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:38:36 PM PDT 24
Peak memory 198272 kb
Host smart-6f16a475-fae7-4bc8-af1d-2d0f71b55496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219121398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2219121398
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3886456756
Short name T293
Test name
Test status
Simulation time 101928884780 ps
CPU time 37.18 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:39:12 PM PDT 24
Peak memory 199916 kb
Host smart-cf1ba614-26d1-4d3e-b5e7-680402dc2c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886456756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3886456756
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.844022863
Short name T709
Test name
Test status
Simulation time 31467035389 ps
CPU time 46.06 seconds
Started Jul 05 05:38:37 PM PDT 24
Finished Jul 05 05:39:23 PM PDT 24
Peak memory 196072 kb
Host smart-673bacb7-c01d-4085-9655-99f47ab2a5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844022863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.844022863
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1324219917
Short name T729
Test name
Test status
Simulation time 711239574 ps
CPU time 1.4 seconds
Started Jul 05 05:38:23 PM PDT 24
Finished Jul 05 05:38:26 PM PDT 24
Peak memory 198204 kb
Host smart-7a80f6d9-717c-401e-aa32-48d2ae48854e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324219917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1324219917
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3610301825
Short name T857
Test name
Test status
Simulation time 149024179477 ps
CPU time 1312.95 seconds
Started Jul 05 05:38:30 PM PDT 24
Finished Jul 05 06:00:24 PM PDT 24
Peak memory 209088 kb
Host smart-4bac5e53-151e-4e65-9977-4e7cc85c1c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610301825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3610301825
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1747182732
Short name T44
Test name
Test status
Simulation time 153374251769 ps
CPU time 213.95 seconds
Started Jul 05 05:38:33 PM PDT 24
Finished Jul 05 05:42:07 PM PDT 24
Peak memory 215720 kb
Host smart-91ce0f48-fa34-498e-b0b5-9366563a4fb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747182732 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1747182732
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3393129231
Short name T630
Test name
Test status
Simulation time 550012498 ps
CPU time 1.78 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:38:37 PM PDT 24
Peak memory 198508 kb
Host smart-b19bbb5d-f0bb-4db2-9a39-d5a7944a184f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393129231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3393129231
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1751832042
Short name T296
Test name
Test status
Simulation time 48189409331 ps
CPU time 19.16 seconds
Started Jul 05 05:38:35 PM PDT 24
Finished Jul 05 05:38:56 PM PDT 24
Peak memory 199892 kb
Host smart-c3987ad7-cb12-44b2-b8a5-4b9b881c228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751832042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1751832042
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.520027130
Short name T907
Test name
Test status
Simulation time 25831147 ps
CPU time 0.57 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:38:36 PM PDT 24
Peak memory 195308 kb
Host smart-56cd39ff-433c-4151-976a-b2168439841c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520027130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.520027130
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1646253186
Short name T893
Test name
Test status
Simulation time 133575448053 ps
CPU time 197.48 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:41:52 PM PDT 24
Peak memory 199968 kb
Host smart-d1f1e66a-c550-4e9e-af41-10cf5e837e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646253186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1646253186
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.352280413
Short name T563
Test name
Test status
Simulation time 39382542154 ps
CPU time 41.34 seconds
Started Jul 05 05:38:32 PM PDT 24
Finished Jul 05 05:39:14 PM PDT 24
Peak memory 199944 kb
Host smart-58fdaef8-303c-472e-b9c9-f13a367e8f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352280413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.352280413
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3076073863
Short name T1143
Test name
Test status
Simulation time 103226023244 ps
CPU time 165.96 seconds
Started Jul 05 05:38:36 PM PDT 24
Finished Jul 05 05:41:23 PM PDT 24
Peak memory 199988 kb
Host smart-7554ae4d-971f-4791-a181-9fab0dedabd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076073863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3076073863
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3557697890
Short name T432
Test name
Test status
Simulation time 23220258464 ps
CPU time 16.95 seconds
Started Jul 05 05:38:36 PM PDT 24
Finished Jul 05 05:38:54 PM PDT 24
Peak memory 199108 kb
Host smart-94614a3d-43df-4d0e-900d-46ad18ea43d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557697890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3557697890
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1057906679
Short name T347
Test name
Test status
Simulation time 110494291843 ps
CPU time 807.15 seconds
Started Jul 05 05:38:32 PM PDT 24
Finished Jul 05 05:51:59 PM PDT 24
Peak memory 199924 kb
Host smart-47e6c7f9-689f-42ae-9b4f-dbb730be5e6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057906679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1057906679
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2331838631
Short name T822
Test name
Test status
Simulation time 9894066000 ps
CPU time 17.91 seconds
Started Jul 05 05:38:33 PM PDT 24
Finished Jul 05 05:38:52 PM PDT 24
Peak memory 199936 kb
Host smart-e1271f3b-f303-42d0-94b6-87f793f71985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331838631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2331838631
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1801024795
Short name T909
Test name
Test status
Simulation time 136472314318 ps
CPU time 67.76 seconds
Started Jul 05 05:38:33 PM PDT 24
Finished Jul 05 05:39:42 PM PDT 24
Peak memory 208108 kb
Host smart-ede8c1d6-5ffd-4a2a-a571-ed8f674e8d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801024795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1801024795
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.111843095
Short name T380
Test name
Test status
Simulation time 14326441067 ps
CPU time 67.65 seconds
Started Jul 05 05:38:35 PM PDT 24
Finished Jul 05 05:39:44 PM PDT 24
Peak memory 199944 kb
Host smart-dc589525-6980-4dfb-8180-9d5bd01e4787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111843095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.111843095
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2336795109
Short name T364
Test name
Test status
Simulation time 3184905776 ps
CPU time 5.49 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:38:41 PM PDT 24
Peak memory 197996 kb
Host smart-c513b7eb-6257-4b23-9ed9-9c1ff4a58220
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2336795109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2336795109
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.158291250
Short name T162
Test name
Test status
Simulation time 28448556700 ps
CPU time 52.8 seconds
Started Jul 05 05:38:31 PM PDT 24
Finished Jul 05 05:39:24 PM PDT 24
Peak memory 199920 kb
Host smart-e9a8d259-142d-4449-94c9-8c5538a5021c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158291250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.158291250
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1440197853
Short name T962
Test name
Test status
Simulation time 685681742 ps
CPU time 0.93 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:38:36 PM PDT 24
Peak memory 195436 kb
Host smart-8f76c784-4bb8-4bec-bac5-f2e846c55696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440197853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1440197853
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2116871493
Short name T1136
Test name
Test status
Simulation time 5469104642 ps
CPU time 16.16 seconds
Started Jul 05 05:38:32 PM PDT 24
Finished Jul 05 05:38:48 PM PDT 24
Peak memory 199972 kb
Host smart-5f4f55f1-7a8b-480f-bce0-d94eed625b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116871493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2116871493
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3517534353
Short name T159
Test name
Test status
Simulation time 357546645514 ps
CPU time 671.48 seconds
Started Jul 05 05:38:33 PM PDT 24
Finished Jul 05 05:49:45 PM PDT 24
Peak memory 216712 kb
Host smart-8ef6387c-1537-44af-a7f0-53b0aa71d9d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517534353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3517534353
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.117783829
Short name T592
Test name
Test status
Simulation time 1926692939 ps
CPU time 2.59 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:38:38 PM PDT 24
Peak memory 198472 kb
Host smart-2381a10b-dc14-4cac-ac28-3e0cdd8c2a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117783829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.117783829
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1901478384
Short name T1010
Test name
Test status
Simulation time 104160881368 ps
CPU time 43.63 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:39:19 PM PDT 24
Peak memory 199936 kb
Host smart-119169ec-1af3-4d1a-b6f5-518c6a4aa690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901478384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1901478384
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2000208416
Short name T1091
Test name
Test status
Simulation time 14695219 ps
CPU time 0.58 seconds
Started Jul 05 05:38:44 PM PDT 24
Finished Jul 05 05:38:46 PM PDT 24
Peak memory 195612 kb
Host smart-12add317-8f7e-493a-969d-b048d12b6479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000208416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2000208416
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3971094804
Short name T795
Test name
Test status
Simulation time 56266801570 ps
CPU time 60.85 seconds
Started Jul 05 05:38:33 PM PDT 24
Finished Jul 05 05:39:34 PM PDT 24
Peak memory 199880 kb
Host smart-934504af-70db-4047-a7e2-3e6a7b319b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971094804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3971094804
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1748033973
Short name T1144
Test name
Test status
Simulation time 90535960992 ps
CPU time 71.73 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:39:47 PM PDT 24
Peak memory 199916 kb
Host smart-7768f1ee-edf9-42d0-af3c-4c514ad541bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748033973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1748033973
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2825121989
Short name T1127
Test name
Test status
Simulation time 123750425560 ps
CPU time 226.84 seconds
Started Jul 05 05:38:40 PM PDT 24
Finished Jul 05 05:42:27 PM PDT 24
Peak memory 199876 kb
Host smart-09e081ed-99e7-4a62-a95a-4d3cfa9d5437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825121989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2825121989
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1678055014
Short name T259
Test name
Test status
Simulation time 13877334480 ps
CPU time 16.06 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:38:59 PM PDT 24
Peak memory 199924 kb
Host smart-d4a8769d-17e1-4aae-b8ec-de5841e92f4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678055014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1678055014
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3423728446
Short name T833
Test name
Test status
Simulation time 157756980464 ps
CPU time 999.69 seconds
Started Jul 05 05:38:54 PM PDT 24
Finished Jul 05 05:55:34 PM PDT 24
Peak memory 199984 kb
Host smart-3b9365ce-aa4f-4255-9de6-572eac665e8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423728446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3423728446
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3148252085
Short name T430
Test name
Test status
Simulation time 8235921744 ps
CPU time 5.12 seconds
Started Jul 05 05:38:44 PM PDT 24
Finished Jul 05 05:38:50 PM PDT 24
Peak memory 199320 kb
Host smart-5a277ca7-9469-44e8-bcd0-e1cbd41068c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148252085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3148252085
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2824475925
Short name T999
Test name
Test status
Simulation time 51185535619 ps
CPU time 15.42 seconds
Started Jul 05 05:38:41 PM PDT 24
Finished Jul 05 05:38:57 PM PDT 24
Peak memory 199704 kb
Host smart-e61423fe-cc7c-4687-9535-9926649ae8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824475925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2824475925
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1344699714
Short name T691
Test name
Test status
Simulation time 18376722607 ps
CPU time 1001.9 seconds
Started Jul 05 05:38:41 PM PDT 24
Finished Jul 05 05:55:24 PM PDT 24
Peak memory 199948 kb
Host smart-5f20002e-2105-4f3d-a793-bd825689953b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1344699714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1344699714
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.357528645
Short name T758
Test name
Test status
Simulation time 6837584137 ps
CPU time 7.21 seconds
Started Jul 05 05:38:43 PM PDT 24
Finished Jul 05 05:38:51 PM PDT 24
Peak memory 199400 kb
Host smart-6076777d-9d4b-425b-8a08-56333f8d774e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357528645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.357528645
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.189863648
Short name T730
Test name
Test status
Simulation time 108732788578 ps
CPU time 143.56 seconds
Started Jul 05 05:38:44 PM PDT 24
Finished Jul 05 05:41:08 PM PDT 24
Peak memory 200000 kb
Host smart-98da03af-057f-4891-8e84-b8c3d7e7e935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189863648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.189863648
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3699309210
Short name T957
Test name
Test status
Simulation time 4898001707 ps
CPU time 2.34 seconds
Started Jul 05 05:38:54 PM PDT 24
Finished Jul 05 05:38:57 PM PDT 24
Peak memory 196760 kb
Host smart-3a16e212-0ff5-4e12-ad96-b50ff2bc4e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699309210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3699309210
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.739813763
Short name T807
Test name
Test status
Simulation time 460192635 ps
CPU time 1.74 seconds
Started Jul 05 05:38:33 PM PDT 24
Finished Jul 05 05:38:36 PM PDT 24
Peak memory 198832 kb
Host smart-97db5574-f604-4da1-b566-5860f0419472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739813763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.739813763
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3945977042
Short name T1102
Test name
Test status
Simulation time 305072999427 ps
CPU time 648.99 seconds
Started Jul 05 05:38:44 PM PDT 24
Finished Jul 05 05:49:34 PM PDT 24
Peak memory 199980 kb
Host smart-d09a01c7-7d70-40a8-83eb-144a298c03de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945977042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3945977042
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2979764764
Short name T2
Test name
Test status
Simulation time 94834378516 ps
CPU time 436.66 seconds
Started Jul 05 05:38:54 PM PDT 24
Finished Jul 05 05:46:11 PM PDT 24
Peak memory 216432 kb
Host smart-24a4e717-9892-4b20-8693-afaac9b98f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979764764 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2979764764
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3234993836
Short name T996
Test name
Test status
Simulation time 930972128 ps
CPU time 3.12 seconds
Started Jul 05 05:38:46 PM PDT 24
Finished Jul 05 05:38:49 PM PDT 24
Peak memory 198400 kb
Host smart-f7182b7b-1f9f-457d-974a-af25b60adac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234993836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3234993836
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2936474372
Short name T847
Test name
Test status
Simulation time 19504579424 ps
CPU time 14.42 seconds
Started Jul 05 05:38:34 PM PDT 24
Finished Jul 05 05:38:49 PM PDT 24
Peak memory 199868 kb
Host smart-b23dc46e-460d-4b39-89f4-617303d4849e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936474372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2936474372
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2695734599
Short name T1161
Test name
Test status
Simulation time 11404529 ps
CPU time 0.55 seconds
Started Jul 05 05:38:43 PM PDT 24
Finished Jul 05 05:38:44 PM PDT 24
Peak memory 195612 kb
Host smart-3b9b1e62-e292-404e-84cf-b714b9a5898e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695734599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2695734599
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.41099077
Short name T537
Test name
Test status
Simulation time 119729961847 ps
CPU time 48.29 seconds
Started Jul 05 05:38:44 PM PDT 24
Finished Jul 05 05:39:33 PM PDT 24
Peak memory 199992 kb
Host smart-782b80df-82fc-4086-95de-65db12966294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41099077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.41099077
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3617333841
Short name T886
Test name
Test status
Simulation time 474489724934 ps
CPU time 69.17 seconds
Started Jul 05 05:38:45 PM PDT 24
Finished Jul 05 05:39:55 PM PDT 24
Peak memory 199800 kb
Host smart-0e30b38a-08f8-4ab8-9c4b-06eb5649c909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617333841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3617333841
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.806588346
Short name T1052
Test name
Test status
Simulation time 41686993165 ps
CPU time 31.08 seconds
Started Jul 05 05:38:44 PM PDT 24
Finished Jul 05 05:39:16 PM PDT 24
Peak memory 199988 kb
Host smart-f2ba42df-8490-4e0e-b3e7-de2ac75be880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806588346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.806588346
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1083721198
Short name T653
Test name
Test status
Simulation time 37452641119 ps
CPU time 24.06 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:39:07 PM PDT 24
Peak memory 198824 kb
Host smart-cbb62b78-069e-47e5-9ac3-c62e3262cb35
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083721198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1083721198
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1341382200
Short name T1088
Test name
Test status
Simulation time 60318916218 ps
CPU time 161.98 seconds
Started Jul 05 05:38:45 PM PDT 24
Finished Jul 05 05:41:28 PM PDT 24
Peak memory 199980 kb
Host smart-d144ae0b-3c41-4708-a705-9d9fdfa43f7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341382200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1341382200
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3300067709
Short name T328
Test name
Test status
Simulation time 6008425250 ps
CPU time 13.46 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:38:56 PM PDT 24
Peak memory 198256 kb
Host smart-87754f32-16ef-4bf5-aae7-fa06053df149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300067709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3300067709
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3814458636
Short name T410
Test name
Test status
Simulation time 91766751601 ps
CPU time 77.62 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:40:00 PM PDT 24
Peak memory 200168 kb
Host smart-28776c76-b116-46aa-8872-bf3871328d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814458636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3814458636
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1896108087
Short name T1019
Test name
Test status
Simulation time 16002911293 ps
CPU time 466.34 seconds
Started Jul 05 05:38:41 PM PDT 24
Finished Jul 05 05:46:28 PM PDT 24
Peak memory 200172 kb
Host smart-6f64fe30-fc40-4e87-a57e-e17fd0c8a957
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896108087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1896108087
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1880680066
Short name T352
Test name
Test status
Simulation time 6436271838 ps
CPU time 10.46 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:38:53 PM PDT 24
Peak memory 198248 kb
Host smart-a50f6372-790d-4903-9737-eb347a2c03d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1880680066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1880680066
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1952882456
Short name T36
Test name
Test status
Simulation time 18144832497 ps
CPU time 17.46 seconds
Started Jul 05 05:38:41 PM PDT 24
Finished Jul 05 05:39:00 PM PDT 24
Peak memory 199892 kb
Host smart-25f181a7-473d-4b13-87d7-469c3ed11bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952882456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1952882456
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.735148787
Short name T443
Test name
Test status
Simulation time 6378083987 ps
CPU time 3.3 seconds
Started Jul 05 05:38:53 PM PDT 24
Finished Jul 05 05:38:57 PM PDT 24
Peak memory 196456 kb
Host smart-cf1cc44e-494b-4d75-a9fc-546157486ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735148787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.735148787
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1700808809
Short name T487
Test name
Test status
Simulation time 896773302 ps
CPU time 2.17 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:38:45 PM PDT 24
Peak memory 198940 kb
Host smart-0c0b728a-d869-4c57-b8db-c73b77987419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700808809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1700808809
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.928970282
Short name T1179
Test name
Test status
Simulation time 138791003396 ps
CPU time 318.47 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:44:02 PM PDT 24
Peak memory 199940 kb
Host smart-e62dbac4-65c8-4832-94b2-5b289b166fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928970282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.928970282
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3403842017
Short name T597
Test name
Test status
Simulation time 470165681777 ps
CPU time 1500.43 seconds
Started Jul 05 05:38:44 PM PDT 24
Finished Jul 05 06:03:46 PM PDT 24
Peak memory 230772 kb
Host smart-ea8dfa50-80a6-42d7-8d09-9f4b9982db30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403842017 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3403842017
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2699464636
Short name T286
Test name
Test status
Simulation time 1364622432 ps
CPU time 2.48 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:38:46 PM PDT 24
Peak memory 198424 kb
Host smart-8f9bda03-7bdb-4f8c-8107-15cd706bf1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699464636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2699464636
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3601529569
Short name T384
Test name
Test status
Simulation time 106595141833 ps
CPU time 52.07 seconds
Started Jul 05 05:38:53 PM PDT 24
Finished Jul 05 05:39:46 PM PDT 24
Peak memory 199928 kb
Host smart-4983c7f0-fe00-40d9-84af-b974d27b4f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601529569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3601529569
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.4141602779
Short name T327
Test name
Test status
Simulation time 25673764 ps
CPU time 0.57 seconds
Started Jul 05 05:38:53 PM PDT 24
Finished Jul 05 05:38:55 PM PDT 24
Peak memory 195328 kb
Host smart-d2b87549-c4bc-4311-b453-961d1a88b2f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141602779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.4141602779
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3048073825
Short name T827
Test name
Test status
Simulation time 96876238026 ps
CPU time 23.82 seconds
Started Jul 05 05:38:45 PM PDT 24
Finished Jul 05 05:39:09 PM PDT 24
Peak memory 199948 kb
Host smart-af582766-a28a-4668-ba88-43e71fe20978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048073825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3048073825
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1369175214
Short name T242
Test name
Test status
Simulation time 114258411558 ps
CPU time 148.03 seconds
Started Jul 05 05:38:41 PM PDT 24
Finished Jul 05 05:41:09 PM PDT 24
Peak memory 199928 kb
Host smart-405915ba-b163-48d6-98fd-5f0568a85798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369175214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1369175214
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4190299623
Short name T871
Test name
Test status
Simulation time 19455482512 ps
CPU time 14.92 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:38:58 PM PDT 24
Peak memory 200000 kb
Host smart-a06272ec-7c4c-43e0-b9ce-c1df8d167937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190299623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4190299623
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2984380875
Short name T543
Test name
Test status
Simulation time 31838764350 ps
CPU time 7.05 seconds
Started Jul 05 05:38:45 PM PDT 24
Finished Jul 05 05:38:53 PM PDT 24
Peak memory 199940 kb
Host smart-e079f4bd-4a08-40bd-9797-60c8a875e71d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984380875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2984380875
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2440351990
Short name T1085
Test name
Test status
Simulation time 69580392890 ps
CPU time 217.71 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:42:20 PM PDT 24
Peak memory 199928 kb
Host smart-1630ddbf-438c-468c-8cee-fd8fec04add0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440351990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2440351990
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.275122287
Short name T820
Test name
Test status
Simulation time 7012212848 ps
CPU time 4.42 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:38:48 PM PDT 24
Peak memory 198356 kb
Host smart-d7cd21f2-f89b-40f2-89e4-2932913464f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275122287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.275122287
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.551979747
Short name T810
Test name
Test status
Simulation time 27688056057 ps
CPU time 1382.95 seconds
Started Jul 05 05:38:53 PM PDT 24
Finished Jul 05 06:01:57 PM PDT 24
Peak memory 200008 kb
Host smart-c21bd884-3942-4b29-9d7b-40437d932eae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551979747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.551979747
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.664784871
Short name T486
Test name
Test status
Simulation time 6597851564 ps
CPU time 18.22 seconds
Started Jul 05 05:38:45 PM PDT 24
Finished Jul 05 05:39:04 PM PDT 24
Peak memory 199316 kb
Host smart-5292f68d-d067-43ba-b23e-0f865a8bc06d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=664784871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.664784871
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3509632678
Short name T1109
Test name
Test status
Simulation time 107129599262 ps
CPU time 20.69 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:39:03 PM PDT 24
Peak memory 199932 kb
Host smart-1755c4f2-6e95-40fa-a9a8-de4719375a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509632678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3509632678
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3231812179
Short name T660
Test name
Test status
Simulation time 2012146653 ps
CPU time 1.88 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:38:44 PM PDT 24
Peak memory 195440 kb
Host smart-3c7a89a1-a079-4575-8ea5-09c72ed728d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231812179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3231812179
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3664453127
Short name T272
Test name
Test status
Simulation time 5377908585 ps
CPU time 7.55 seconds
Started Jul 05 05:38:40 PM PDT 24
Finished Jul 05 05:38:47 PM PDT 24
Peak memory 199720 kb
Host smart-7228a09f-1ec5-4950-b792-407939fcc16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664453127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3664453127
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4212941156
Short name T674
Test name
Test status
Simulation time 260357035990 ps
CPU time 1146.12 seconds
Started Jul 05 05:38:44 PM PDT 24
Finished Jul 05 05:57:51 PM PDT 24
Peak memory 199920 kb
Host smart-f87b0253-ccf5-426d-be55-d45b6407e594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212941156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4212941156
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3658000530
Short name T911
Test name
Test status
Simulation time 380852399543 ps
CPU time 740.34 seconds
Started Jul 05 05:38:41 PM PDT 24
Finished Jul 05 05:51:03 PM PDT 24
Peak memory 224936 kb
Host smart-fcf1f324-02ba-42f1-b4c9-01eea00896de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658000530 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3658000530
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1108104336
Short name T855
Test name
Test status
Simulation time 1409382105 ps
CPU time 2.81 seconds
Started Jul 05 05:38:43 PM PDT 24
Finished Jul 05 05:38:47 PM PDT 24
Peak memory 198408 kb
Host smart-c3336fc9-0b28-4052-a2e1-33ac3f5bb12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108104336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1108104336
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.4114595574
Short name T605
Test name
Test status
Simulation time 68368981801 ps
CPU time 190.57 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:41:54 PM PDT 24
Peak memory 199936 kb
Host smart-ec48e782-d862-4a8a-844a-496055c4ead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114595574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4114595574
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1774211374
Short name T390
Test name
Test status
Simulation time 67311109 ps
CPU time 0.53 seconds
Started Jul 05 05:38:52 PM PDT 24
Finished Jul 05 05:38:53 PM PDT 24
Peak memory 195252 kb
Host smart-4ce8d0bf-ecb5-41a7-a871-0bf9e199153f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774211374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1774211374
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3260478307
Short name T1171
Test name
Test status
Simulation time 144542886222 ps
CPU time 67.57 seconds
Started Jul 05 05:38:46 PM PDT 24
Finished Jul 05 05:39:54 PM PDT 24
Peak memory 200008 kb
Host smart-ef96d027-0513-47bf-a987-e4501f472eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260478307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3260478307
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.944458374
Short name T516
Test name
Test status
Simulation time 19840913747 ps
CPU time 31.4 seconds
Started Jul 05 05:38:54 PM PDT 24
Finished Jul 05 05:39:27 PM PDT 24
Peak memory 199964 kb
Host smart-4e0889e0-5670-43a6-9f5e-e9ae126a47e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944458374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.944458374
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.957372983
Short name T983
Test name
Test status
Simulation time 58519743661 ps
CPU time 114.26 seconds
Started Jul 05 05:38:47 PM PDT 24
Finished Jul 05 05:40:42 PM PDT 24
Peak memory 199900 kb
Host smart-7b36d693-bda7-4b47-a398-01b2b564969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957372983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.957372983
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2192953466
Short name T483
Test name
Test status
Simulation time 48339756150 ps
CPU time 82.43 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:40:13 PM PDT 24
Peak memory 199596 kb
Host smart-ecd6990e-1ac1-4ff2-8d3a-3f8dd68383c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192953466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2192953466
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1619568058
Short name T1059
Test name
Test status
Simulation time 111742985493 ps
CPU time 784.71 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:51:55 PM PDT 24
Peak memory 199948 kb
Host smart-5a61281d-997f-4754-997b-5551ad37590f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619568058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1619568058
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.166480558
Short name T353
Test name
Test status
Simulation time 4682150664 ps
CPU time 6.39 seconds
Started Jul 05 05:38:47 PM PDT 24
Finished Jul 05 05:38:54 PM PDT 24
Peak memory 199836 kb
Host smart-cab89cde-e255-44b1-add7-bab77463569d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166480558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.166480558
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.4041642627
Short name T953
Test name
Test status
Simulation time 22995150732 ps
CPU time 37.15 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:39:27 PM PDT 24
Peak memory 200128 kb
Host smart-3596e4bb-d17d-4ec5-bce8-4423a1d1ec6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041642627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4041642627
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.302169885
Short name T934
Test name
Test status
Simulation time 16467654154 ps
CPU time 135.97 seconds
Started Jul 05 05:38:47 PM PDT 24
Finished Jul 05 05:41:03 PM PDT 24
Peak memory 199984 kb
Host smart-0e4a4062-956f-480a-af68-ccadebf9590b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302169885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.302169885
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1897836667
Short name T1060
Test name
Test status
Simulation time 5194322494 ps
CPU time 41.39 seconds
Started Jul 05 05:38:48 PM PDT 24
Finished Jul 05 05:39:31 PM PDT 24
Peak memory 198092 kb
Host smart-44483c16-b287-4961-93c4-7687cd336c3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1897836667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1897836667
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2962192507
Short name T35
Test name
Test status
Simulation time 33669594813 ps
CPU time 55.3 seconds
Started Jul 05 05:38:48 PM PDT 24
Finished Jul 05 05:39:45 PM PDT 24
Peak memory 199960 kb
Host smart-7309c2ea-e7df-47e3-97a1-210af5a1b0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962192507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2962192507
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3584619010
Short name T400
Test name
Test status
Simulation time 2927506194 ps
CPU time 1.75 seconds
Started Jul 05 05:38:50 PM PDT 24
Finished Jul 05 05:38:53 PM PDT 24
Peak memory 196424 kb
Host smart-cd38071d-30da-4f07-bfea-31e30474fd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584619010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3584619010
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3994570127
Short name T557
Test name
Test status
Simulation time 5389592000 ps
CPU time 16.19 seconds
Started Jul 05 05:38:44 PM PDT 24
Finished Jul 05 05:39:01 PM PDT 24
Peak memory 199152 kb
Host smart-2ed9231f-4c1a-48d4-83dd-e77f103f0133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994570127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3994570127
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.328841676
Short name T14
Test name
Test status
Simulation time 154349199710 ps
CPU time 441.15 seconds
Started Jul 05 05:38:52 PM PDT 24
Finished Jul 05 05:46:14 PM PDT 24
Peak memory 208200 kb
Host smart-e2bd0955-27e5-4faf-a183-cbd713b21568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328841676 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.328841676
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3479504101
Short name T664
Test name
Test status
Simulation time 6440027430 ps
CPU time 19.05 seconds
Started Jul 05 05:38:52 PM PDT 24
Finished Jul 05 05:39:11 PM PDT 24
Peak memory 199864 kb
Host smart-9057c760-c385-411a-ad4d-a5b6add7aad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479504101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3479504101
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.4262646511
Short name T301
Test name
Test status
Simulation time 51885219967 ps
CPU time 70.15 seconds
Started Jul 05 05:38:42 PM PDT 24
Finished Jul 05 05:39:53 PM PDT 24
Peak memory 199988 kb
Host smart-dc0a4ce8-c298-4fb5-9882-7f5cd12e20b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262646511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.4262646511
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1927058560
Short name T60
Test name
Test status
Simulation time 20996309 ps
CPU time 0.54 seconds
Started Jul 05 05:38:48 PM PDT 24
Finished Jul 05 05:38:49 PM PDT 24
Peak memory 195608 kb
Host smart-1eda918e-c19f-4e1d-b98f-6617344f222c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927058560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1927058560
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.141719428
Short name T818
Test name
Test status
Simulation time 172856325332 ps
CPU time 132.39 seconds
Started Jul 05 05:38:50 PM PDT 24
Finished Jul 05 05:41:03 PM PDT 24
Peak memory 199940 kb
Host smart-23b3927d-de7d-4ee0-9966-5fe0548b746e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141719428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.141719428
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.508117565
Short name T595
Test name
Test status
Simulation time 136666828840 ps
CPU time 245.2 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:42:55 PM PDT 24
Peak memory 200020 kb
Host smart-42ccf2b0-5905-4356-b29e-5a5e4a6a122a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508117565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.508117565
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_intr.2618185550
Short name T1029
Test name
Test status
Simulation time 22629086052 ps
CPU time 4.86 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:38:55 PM PDT 24
Peak memory 197432 kb
Host smart-1abc80ec-aaed-4e59-8694-79c5e8164dfa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618185550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2618185550
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.483207309
Short name T549
Test name
Test status
Simulation time 132100416131 ps
CPU time 956.9 seconds
Started Jul 05 05:38:48 PM PDT 24
Finished Jul 05 05:54:46 PM PDT 24
Peak memory 200032 kb
Host smart-55974e0b-9858-4f46-b682-4c20ae4bfddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483207309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.483207309
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1560087117
Short name T357
Test name
Test status
Simulation time 7250436954 ps
CPU time 14.33 seconds
Started Jul 05 05:38:48 PM PDT 24
Finished Jul 05 05:39:03 PM PDT 24
Peak memory 198312 kb
Host smart-ae94a3d4-da14-4e29-b630-bbf8c8000b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560087117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1560087117
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1130965140
Short name T318
Test name
Test status
Simulation time 26947362718 ps
CPU time 37.2 seconds
Started Jul 05 05:38:51 PM PDT 24
Finished Jul 05 05:39:29 PM PDT 24
Peak memory 197676 kb
Host smart-12b1e1b4-6adf-4763-818c-9d6c9551edbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130965140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1130965140
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2995564000
Short name T862
Test name
Test status
Simulation time 9754772165 ps
CPU time 98.07 seconds
Started Jul 05 05:38:51 PM PDT 24
Finished Jul 05 05:40:30 PM PDT 24
Peak memory 199932 kb
Host smart-50a8d389-11c4-42ab-bcd0-40350341eebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995564000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2995564000
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1888932784
Short name T1024
Test name
Test status
Simulation time 5997452486 ps
CPU time 28.08 seconds
Started Jul 05 05:38:51 PM PDT 24
Finished Jul 05 05:39:20 PM PDT 24
Peak memory 199248 kb
Host smart-c6a6a7b3-6b9b-4a75-8a80-be991d05c64e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1888932784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1888932784
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.282100147
Short name T879
Test name
Test status
Simulation time 21501832896 ps
CPU time 41.52 seconds
Started Jul 05 05:38:48 PM PDT 24
Finished Jul 05 05:39:31 PM PDT 24
Peak memory 199892 kb
Host smart-322f2406-65eb-4da3-aa1b-fabe862d4524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282100147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.282100147
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1588542959
Short name T742
Test name
Test status
Simulation time 4987165655 ps
CPU time 4.51 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:38:55 PM PDT 24
Peak memory 196176 kb
Host smart-87d92797-881f-45e8-bf33-011b747e9309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588542959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1588542959
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2713655393
Short name T359
Test name
Test status
Simulation time 714688282 ps
CPU time 1.37 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:38:51 PM PDT 24
Peak memory 198656 kb
Host smart-a1e5118d-8aa1-4368-ae08-f265dd8b05ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713655393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2713655393
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1871603239
Short name T623
Test name
Test status
Simulation time 200635509581 ps
CPU time 544.36 seconds
Started Jul 05 05:38:47 PM PDT 24
Finished Jul 05 05:47:52 PM PDT 24
Peak memory 199900 kb
Host smart-937651bf-404c-4b75-aafe-99f71dcd3bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871603239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1871603239
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.557848699
Short name T906
Test name
Test status
Simulation time 57593739271 ps
CPU time 729.17 seconds
Started Jul 05 05:38:48 PM PDT 24
Finished Jul 05 05:50:58 PM PDT 24
Peak memory 216488 kb
Host smart-d4a02fb1-ce8b-409c-a66d-8716b52b7b26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557848699 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.557848699
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1761526395
Short name T341
Test name
Test status
Simulation time 189711291 ps
CPU time 1.04 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:38:51 PM PDT 24
Peak memory 197764 kb
Host smart-8384a4d1-5e2a-4851-8391-bb52cf97e69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761526395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1761526395
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.437227813
Short name T297
Test name
Test status
Simulation time 66771134208 ps
CPU time 100.47 seconds
Started Jul 05 05:38:51 PM PDT 24
Finished Jul 05 05:40:32 PM PDT 24
Peak memory 199872 kb
Host smart-842b1925-55c9-4838-bbc2-818297d51c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437227813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.437227813
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.4015278580
Short name T325
Test name
Test status
Simulation time 33104981 ps
CPU time 0.55 seconds
Started Jul 05 05:38:55 PM PDT 24
Finished Jul 05 05:38:56 PM PDT 24
Peak memory 195560 kb
Host smart-3e4d47aa-7f42-4e40-b3f0-f10d3821fe49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015278580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.4015278580
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2764462936
Short name T170
Test name
Test status
Simulation time 40468729445 ps
CPU time 41.12 seconds
Started Jul 05 05:38:51 PM PDT 24
Finished Jul 05 05:39:33 PM PDT 24
Peak memory 199988 kb
Host smart-c06d9853-3195-4f5b-bfaf-26bcd90b09f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764462936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2764462936
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3011649440
Short name T956
Test name
Test status
Simulation time 9888065331 ps
CPU time 15.89 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:39:06 PM PDT 24
Peak memory 199728 kb
Host smart-80163e41-f2ff-491d-8efe-08ebad9f2f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011649440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3011649440
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1488931242
Short name T493
Test name
Test status
Simulation time 36943463074 ps
CPU time 25.49 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:39:15 PM PDT 24
Peak memory 199964 kb
Host smart-979216f8-1fd9-41ee-ba78-15ce42c885cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488931242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1488931242
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.280016404
Short name T376
Test name
Test status
Simulation time 36589342160 ps
CPU time 66.94 seconds
Started Jul 05 05:38:52 PM PDT 24
Finished Jul 05 05:40:00 PM PDT 24
Peak memory 199880 kb
Host smart-78ea6bf9-ea04-44be-8a8a-a06621f16ea2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280016404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.280016404
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2726798194
Short name T1050
Test name
Test status
Simulation time 49696328288 ps
CPU time 300.41 seconds
Started Jul 05 05:38:57 PM PDT 24
Finished Jul 05 05:43:59 PM PDT 24
Peak memory 199928 kb
Host smart-65f9f3ce-437e-47b9-95da-d786514377b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726798194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2726798194
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1124341551
Short name T344
Test name
Test status
Simulation time 7958026420 ps
CPU time 13.82 seconds
Started Jul 05 05:38:55 PM PDT 24
Finished Jul 05 05:39:10 PM PDT 24
Peak memory 199884 kb
Host smart-d3b2987d-91f1-4eae-9030-2ca68adce621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124341551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1124341551
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3530474927
Short name T253
Test name
Test status
Simulation time 150955853345 ps
CPU time 181.67 seconds
Started Jul 05 05:38:52 PM PDT 24
Finished Jul 05 05:41:55 PM PDT 24
Peak memory 200264 kb
Host smart-23f1f9f0-4753-4d9d-b9c3-3f64afb4fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530474927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3530474927
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.194793177
Short name T643
Test name
Test status
Simulation time 9589442467 ps
CPU time 519.65 seconds
Started Jul 05 05:38:56 PM PDT 24
Finished Jul 05 05:47:36 PM PDT 24
Peak memory 199888 kb
Host smart-4a9c0e53-7235-430e-8a61-db5b32f94acc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194793177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.194793177
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.961614316
Short name T411
Test name
Test status
Simulation time 2961954342 ps
CPU time 5.02 seconds
Started Jul 05 05:38:51 PM PDT 24
Finished Jul 05 05:38:57 PM PDT 24
Peak memory 197984 kb
Host smart-590f5752-37d0-4099-9805-5c5eb04d8792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961614316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.961614316
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1562399983
Short name T947
Test name
Test status
Simulation time 4479333045 ps
CPU time 7.29 seconds
Started Jul 05 05:38:48 PM PDT 24
Finished Jul 05 05:38:57 PM PDT 24
Peak memory 196256 kb
Host smart-7df8c1a2-b79b-4c49-aab6-3b35c7e0a46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562399983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1562399983
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1346331681
Short name T510
Test name
Test status
Simulation time 502381096 ps
CPU time 2.34 seconds
Started Jul 05 05:38:49 PM PDT 24
Finished Jul 05 05:38:53 PM PDT 24
Peak memory 198608 kb
Host smart-6ebf70bc-70e1-4374-8283-759ec1868f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346331681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1346331681
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1315174519
Short name T453
Test name
Test status
Simulation time 26790596516 ps
CPU time 21.23 seconds
Started Jul 05 05:38:56 PM PDT 24
Finished Jul 05 05:39:18 PM PDT 24
Peak memory 199920 kb
Host smart-b4a94d78-47a2-4816-8f2f-891c9748d252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315174519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1315174519
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3327706192
Short name T513
Test name
Test status
Simulation time 206887283 ps
CPU time 1.09 seconds
Started Jul 05 05:38:56 PM PDT 24
Finished Jul 05 05:38:58 PM PDT 24
Peak memory 197020 kb
Host smart-b7666700-8270-4e1e-98e2-1b83de2ecfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327706192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3327706192
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3491917589
Short name T267
Test name
Test status
Simulation time 27007432844 ps
CPU time 31.59 seconds
Started Jul 05 05:38:53 PM PDT 24
Finished Jul 05 05:39:25 PM PDT 24
Peak memory 199836 kb
Host smart-82e47cfd-606c-42e9-8245-74c1fd13d7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491917589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3491917589
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3189358776
Short name T431
Test name
Test status
Simulation time 35472645 ps
CPU time 0.58 seconds
Started Jul 05 05:37:07 PM PDT 24
Finished Jul 05 05:37:09 PM PDT 24
Peak memory 195324 kb
Host smart-4eda2b8a-67e4-40a5-8484-9b214affdcda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189358776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3189358776
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1064948163
Short name T333
Test name
Test status
Simulation time 21704074992 ps
CPU time 18 seconds
Started Jul 05 05:37:07 PM PDT 24
Finished Jul 05 05:37:26 PM PDT 24
Peak memory 199920 kb
Host smart-0e817e82-1bed-4eec-9e67-c6bb9768e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064948163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1064948163
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1226198613
Short name T434
Test name
Test status
Simulation time 47008994449 ps
CPU time 51.21 seconds
Started Jul 05 05:37:07 PM PDT 24
Finished Jul 05 05:37:59 PM PDT 24
Peak memory 199924 kb
Host smart-b4c45368-32a0-4f28-8ac3-c1125de56ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226198613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1226198613
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.131088959
Short name T1128
Test name
Test status
Simulation time 33652065642 ps
CPU time 47.11 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:37:52 PM PDT 24
Peak memory 199976 kb
Host smart-eaabaef0-9c18-43b4-b958-118675d42aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131088959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.131088959
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1336433611
Short name T455
Test name
Test status
Simulation time 21814922637 ps
CPU time 27.46 seconds
Started Jul 05 05:37:08 PM PDT 24
Finished Jul 05 05:37:36 PM PDT 24
Peak memory 199920 kb
Host smart-8cb74e50-b86d-4490-97c7-a6fde9c17f29
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336433611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1336433611
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1450755948
Short name T960
Test name
Test status
Simulation time 97567175592 ps
CPU time 826.49 seconds
Started Jul 05 05:37:06 PM PDT 24
Finished Jul 05 05:50:54 PM PDT 24
Peak memory 199952 kb
Host smart-d344e4cb-ead6-451e-88c0-936080fa592e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450755948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1450755948
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3795795623
Short name T92
Test name
Test status
Simulation time 87177390 ps
CPU time 0.75 seconds
Started Jul 05 05:37:02 PM PDT 24
Finished Jul 05 05:37:03 PM PDT 24
Peak memory 196036 kb
Host smart-47b69b3c-beb9-468d-b45c-8fb9ea43cae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795795623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3795795623
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1765183757
Short name T491
Test name
Test status
Simulation time 50764025032 ps
CPU time 50.15 seconds
Started Jul 05 05:37:07 PM PDT 24
Finished Jul 05 05:37:58 PM PDT 24
Peak memory 200172 kb
Host smart-e5967329-3211-451d-83bb-217340d5a869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765183757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1765183757
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1885723821
Short name T992
Test name
Test status
Simulation time 13302730769 ps
CPU time 173.94 seconds
Started Jul 05 05:37:05 PM PDT 24
Finished Jul 05 05:40:01 PM PDT 24
Peak memory 199880 kb
Host smart-1b573e96-aab7-4c7d-b9b8-1514c8298ae6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885723821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1885723821
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3268882348
Short name T524
Test name
Test status
Simulation time 1492472424 ps
CPU time 3.33 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:37:09 PM PDT 24
Peak memory 198596 kb
Host smart-04c53cfb-2b50-4eb1-b63a-ba96a6ce905a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268882348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3268882348
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3641510112
Short name T6
Test name
Test status
Simulation time 38014739391 ps
CPU time 52.42 seconds
Started Jul 05 05:37:05 PM PDT 24
Finished Jul 05 05:37:58 PM PDT 24
Peak memory 195960 kb
Host smart-53fb1703-58bc-4b38-a4c3-d5dd93ebf3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641510112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3641510112
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1033452782
Short name T89
Test name
Test status
Simulation time 467754038 ps
CPU time 0.92 seconds
Started Jul 05 05:37:02 PM PDT 24
Finished Jul 05 05:37:04 PM PDT 24
Peak memory 218316 kb
Host smart-a472700f-7983-447b-91fa-28f518fda928
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033452782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1033452782
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1245704432
Short name T651
Test name
Test status
Simulation time 269167408 ps
CPU time 1.26 seconds
Started Jul 05 05:37:28 PM PDT 24
Finished Jul 05 05:37:31 PM PDT 24
Peak memory 198400 kb
Host smart-990f11fb-a265-4805-a0c7-68adc18b3201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245704432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1245704432
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2341089620
Short name T109
Test name
Test status
Simulation time 130751304347 ps
CPU time 636.17 seconds
Started Jul 05 05:37:10 PM PDT 24
Finished Jul 05 05:47:47 PM PDT 24
Peak memory 199944 kb
Host smart-891bbf7e-7cb4-414a-98aa-849de2640d06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341089620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2341089620
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.794403253
Short name T1056
Test name
Test status
Simulation time 2263997571 ps
CPU time 3.4 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:37:08 PM PDT 24
Peak memory 199688 kb
Host smart-38dbd86b-5e3a-4de6-a745-6e32b8207ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794403253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.794403253
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1326238636
Short name T773
Test name
Test status
Simulation time 43688405179 ps
CPU time 14.29 seconds
Started Jul 05 05:37:04 PM PDT 24
Finished Jul 05 05:37:20 PM PDT 24
Peak memory 199916 kb
Host smart-6feb1f3e-bbc3-424b-b92c-47462046eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326238636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1326238636
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.15329608
Short name T546
Test name
Test status
Simulation time 11661778 ps
CPU time 0.55 seconds
Started Jul 05 05:38:56 PM PDT 24
Finished Jul 05 05:38:57 PM PDT 24
Peak memory 194984 kb
Host smart-40603791-e924-4865-a3cc-9a79660088cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15329608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.15329608
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2124145760
Short name T314
Test name
Test status
Simulation time 65132890668 ps
CPU time 17.23 seconds
Started Jul 05 05:38:57 PM PDT 24
Finished Jul 05 05:39:15 PM PDT 24
Peak memory 199896 kb
Host smart-99d95810-bd01-41c8-bef1-6d6a289ea5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124145760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2124145760
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3593957594
Short name T1068
Test name
Test status
Simulation time 16005340557 ps
CPU time 12.93 seconds
Started Jul 05 05:38:55 PM PDT 24
Finished Jul 05 05:39:09 PM PDT 24
Peak memory 198328 kb
Host smart-9c9349a1-d2be-40f3-9c60-d936f12cefa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593957594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3593957594
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.287339710
Short name T869
Test name
Test status
Simulation time 74776147096 ps
CPU time 34.53 seconds
Started Jul 05 05:38:58 PM PDT 24
Finished Jul 05 05:39:33 PM PDT 24
Peak memory 199964 kb
Host smart-baf7173d-6bfb-4a63-b340-612fa2107067
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287339710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.287339710
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.600840139
Short name T972
Test name
Test status
Simulation time 100791017287 ps
CPU time 650.65 seconds
Started Jul 05 05:38:58 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 199980 kb
Host smart-766a8bee-fc0d-4c77-a7c7-ccfccc1f26bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600840139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.600840139
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2432748338
Short name T397
Test name
Test status
Simulation time 5208734712 ps
CPU time 4.5 seconds
Started Jul 05 05:38:59 PM PDT 24
Finished Jul 05 05:39:04 PM PDT 24
Peak memory 199948 kb
Host smart-0b8bc551-45ea-452c-ae05-b9e3842130a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432748338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2432748338
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1368703963
Short name T583
Test name
Test status
Simulation time 44873210581 ps
CPU time 76.68 seconds
Started Jul 05 05:39:00 PM PDT 24
Finished Jul 05 05:40:17 PM PDT 24
Peak memory 200136 kb
Host smart-306002e0-9532-4e76-bffd-88e1742e3254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368703963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1368703963
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2546190490
Short name T638
Test name
Test status
Simulation time 24037309397 ps
CPU time 107.76 seconds
Started Jul 05 05:38:56 PM PDT 24
Finished Jul 05 05:40:44 PM PDT 24
Peak memory 199872 kb
Host smart-cce178ad-f99a-4253-9e3d-496e97c660c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546190490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2546190490
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2424212293
Short name T581
Test name
Test status
Simulation time 6064424634 ps
CPU time 51.27 seconds
Started Jul 05 05:38:56 PM PDT 24
Finished Jul 05 05:39:48 PM PDT 24
Peak memory 199356 kb
Host smart-d4318732-03e5-4693-a461-e16c4997aff8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424212293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2424212293
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2405333923
Short name T750
Test name
Test status
Simulation time 76644932120 ps
CPU time 36.59 seconds
Started Jul 05 05:38:56 PM PDT 24
Finished Jul 05 05:39:33 PM PDT 24
Peak memory 199644 kb
Host smart-a129ee3b-0d77-4ec0-80de-1a44e5cac3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405333923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2405333923
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2296446451
Short name T941
Test name
Test status
Simulation time 44299686488 ps
CPU time 62.11 seconds
Started Jul 05 05:38:57 PM PDT 24
Finished Jul 05 05:39:59 PM PDT 24
Peak memory 196072 kb
Host smart-6799abb6-18e5-4f5b-ad92-c441d7d92c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296446451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2296446451
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.4034495211
Short name T782
Test name
Test status
Simulation time 486567528 ps
CPU time 2.39 seconds
Started Jul 05 05:38:55 PM PDT 24
Finished Jul 05 05:38:58 PM PDT 24
Peak memory 198712 kb
Host smart-6f92559d-80f8-4b59-b444-a60a5fa5543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034495211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.4034495211
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.535429461
Short name T166
Test name
Test status
Simulation time 30774710015 ps
CPU time 193.61 seconds
Started Jul 05 05:38:57 PM PDT 24
Finished Jul 05 05:42:11 PM PDT 24
Peak memory 216716 kb
Host smart-09b8949d-8187-42d7-820e-ef345a5ab6e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535429461 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.535429461
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2019716678
Short name T696
Test name
Test status
Simulation time 894675412 ps
CPU time 1.73 seconds
Started Jul 05 05:38:57 PM PDT 24
Finished Jul 05 05:39:00 PM PDT 24
Peak memory 198420 kb
Host smart-2dc50a77-8b58-4f6b-ba0f-d2730a6f47ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019716678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2019716678
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2452087805
Short name T441
Test name
Test status
Simulation time 49547522183 ps
CPU time 71.25 seconds
Started Jul 05 05:38:56 PM PDT 24
Finished Jul 05 05:40:08 PM PDT 24
Peak memory 199992 kb
Host smart-8f6edcb5-e4b7-42be-a546-631f186b9648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452087805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2452087805
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1706233939
Short name T514
Test name
Test status
Simulation time 17498560 ps
CPU time 0.55 seconds
Started Jul 05 05:39:04 PM PDT 24
Finished Jul 05 05:39:05 PM PDT 24
Peak memory 194276 kb
Host smart-c373a262-11ac-4c79-8538-70b29fdf2807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706233939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1706233939
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1719899934
Short name T476
Test name
Test status
Simulation time 16408656388 ps
CPU time 13.86 seconds
Started Jul 05 05:38:58 PM PDT 24
Finished Jul 05 05:39:13 PM PDT 24
Peak memory 199948 kb
Host smart-2d92d486-7bfe-45bf-836a-462fc44a365e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719899934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1719899934
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.679154373
Short name T896
Test name
Test status
Simulation time 25757475762 ps
CPU time 37.14 seconds
Started Jul 05 05:39:00 PM PDT 24
Finished Jul 05 05:39:37 PM PDT 24
Peak memory 200004 kb
Host smart-faea8f3b-4b59-4306-87c2-bebf8ebe118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679154373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.679154373
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.4218178427
Short name T332
Test name
Test status
Simulation time 6621588237 ps
CPU time 5.18 seconds
Started Jul 05 05:39:02 PM PDT 24
Finished Jul 05 05:39:08 PM PDT 24
Peak memory 196580 kb
Host smart-044671c3-1674-48b0-ac5b-16a603fbc92e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218178427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4218178427
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3962108136
Short name T339
Test name
Test status
Simulation time 81951761944 ps
CPU time 602.47 seconds
Started Jul 05 05:39:05 PM PDT 24
Finished Jul 05 05:49:08 PM PDT 24
Peak memory 199980 kb
Host smart-8fa0f9d6-7eb5-47de-aa63-bea13c72a8e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962108136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3962108136
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.522657138
Short name T1093
Test name
Test status
Simulation time 4218855519 ps
CPU time 8.07 seconds
Started Jul 05 05:39:03 PM PDT 24
Finished Jul 05 05:39:12 PM PDT 24
Peak memory 198400 kb
Host smart-756802e4-3507-4674-98f7-b3b2304e0dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522657138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.522657138
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.231756071
Short name T900
Test name
Test status
Simulation time 237293102283 ps
CPU time 92.41 seconds
Started Jul 05 05:38:59 PM PDT 24
Finished Jul 05 05:40:32 PM PDT 24
Peak memory 208500 kb
Host smart-1c5dfd97-445c-47d9-8cf4-6bcb0384519d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231756071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.231756071
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2737710554
Short name T439
Test name
Test status
Simulation time 20262567930 ps
CPU time 242.9 seconds
Started Jul 05 05:39:05 PM PDT 24
Finished Jul 05 05:43:09 PM PDT 24
Peak memory 199920 kb
Host smart-aa8deb79-6224-49a9-9e40-a0985f443460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737710554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2737710554
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2611462442
Short name T757
Test name
Test status
Simulation time 7406313358 ps
CPU time 27.98 seconds
Started Jul 05 05:39:03 PM PDT 24
Finished Jul 05 05:39:31 PM PDT 24
Peak memory 198824 kb
Host smart-072311ad-0b71-4e27-ab65-b9c43549623d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611462442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2611462442
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2382353343
Short name T533
Test name
Test status
Simulation time 35452828008 ps
CPU time 23.06 seconds
Started Jul 05 05:39:02 PM PDT 24
Finished Jul 05 05:39:26 PM PDT 24
Peak memory 199992 kb
Host smart-f5cd8a58-0a59-4ca6-b40f-20a7ef2b8040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382353343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2382353343
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3965550624
Short name T262
Test name
Test status
Simulation time 48461813349 ps
CPU time 12.82 seconds
Started Jul 05 05:39:04 PM PDT 24
Finished Jul 05 05:39:17 PM PDT 24
Peak memory 195760 kb
Host smart-234e9f7c-4c11-48fb-94c8-293f2fe38ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965550624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3965550624
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1027538170
Short name T287
Test name
Test status
Simulation time 864488021 ps
CPU time 2.33 seconds
Started Jul 05 05:38:57 PM PDT 24
Finished Jul 05 05:39:00 PM PDT 24
Peak memory 198888 kb
Host smart-dcfc6291-c673-410a-b355-7df36f8c6dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027538170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1027538170
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2220457834
Short name T589
Test name
Test status
Simulation time 161260451276 ps
CPU time 397.33 seconds
Started Jul 05 05:39:05 PM PDT 24
Finished Jul 05 05:45:43 PM PDT 24
Peak memory 208316 kb
Host smart-8e0bfd26-0c40-42ac-af0a-1d25124a40dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220457834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2220457834
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3953656008
Short name T102
Test name
Test status
Simulation time 88088419639 ps
CPU time 809.23 seconds
Started Jul 05 05:39:01 PM PDT 24
Finished Jul 05 05:52:31 PM PDT 24
Peak memory 224844 kb
Host smart-03b565d4-015c-4b55-981e-3c521da2344a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953656008 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3953656008
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2003464442
Short name T836
Test name
Test status
Simulation time 8523094227 ps
CPU time 11.4 seconds
Started Jul 05 05:39:04 PM PDT 24
Finished Jul 05 05:39:16 PM PDT 24
Peak memory 199720 kb
Host smart-ccf165ad-b175-4821-8cf4-d5d3b1cdcd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003464442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2003464442
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2723367130
Short name T115
Test name
Test status
Simulation time 10238953739 ps
CPU time 4.84 seconds
Started Jul 05 05:38:57 PM PDT 24
Finished Jul 05 05:39:03 PM PDT 24
Peak memory 197440 kb
Host smart-6db66f9e-2c48-4661-a887-6c497efe1d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723367130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2723367130
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3997300784
Short name T1166
Test name
Test status
Simulation time 37991921 ps
CPU time 0.61 seconds
Started Jul 05 05:39:10 PM PDT 24
Finished Jul 05 05:39:11 PM PDT 24
Peak memory 195328 kb
Host smart-a812b0e2-e295-4234-8310-230e1fee43af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997300784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3997300784
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2869320746
Short name T174
Test name
Test status
Simulation time 49493870452 ps
CPU time 43.88 seconds
Started Jul 05 05:39:05 PM PDT 24
Finished Jul 05 05:39:49 PM PDT 24
Peak memory 199844 kb
Host smart-2a65c9dc-02ac-49e1-b8ef-deaccc88fc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869320746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2869320746
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3598541820
Short name T389
Test name
Test status
Simulation time 26774058576 ps
CPU time 34.36 seconds
Started Jul 05 05:39:06 PM PDT 24
Finished Jul 05 05:39:41 PM PDT 24
Peak memory 199936 kb
Host smart-fb2188d8-9946-43a6-87b6-8f33f55cf260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598541820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3598541820
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3819897134
Short name T502
Test name
Test status
Simulation time 128762741223 ps
CPU time 243.91 seconds
Started Jul 05 05:39:02 PM PDT 24
Finished Jul 05 05:43:07 PM PDT 24
Peak memory 199992 kb
Host smart-1d99cacc-777d-4dff-beac-03ee838a1b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819897134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3819897134
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1450308799
Short name T334
Test name
Test status
Simulation time 9273327820 ps
CPU time 16.01 seconds
Started Jul 05 05:39:05 PM PDT 24
Finished Jul 05 05:39:22 PM PDT 24
Peak memory 197796 kb
Host smart-c2ec7949-9abd-4cb7-8c0a-3f01bb824a04
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450308799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1450308799
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3652939984
Short name T858
Test name
Test status
Simulation time 64885000916 ps
CPU time 83.6 seconds
Started Jul 05 05:39:12 PM PDT 24
Finished Jul 05 05:40:36 PM PDT 24
Peak memory 199920 kb
Host smart-56f248c8-6199-4cff-a798-76e474a7b299
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652939984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3652939984
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.377509097
Short name T369
Test name
Test status
Simulation time 4031150403 ps
CPU time 5.63 seconds
Started Jul 05 05:39:02 PM PDT 24
Finished Jul 05 05:39:09 PM PDT 24
Peak memory 199696 kb
Host smart-ede3cf19-14bf-434c-bcc5-c8b592a346bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377509097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.377509097
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2287906721
Short name T264
Test name
Test status
Simulation time 74721647725 ps
CPU time 140.28 seconds
Started Jul 05 05:39:05 PM PDT 24
Finished Jul 05 05:41:26 PM PDT 24
Peak memory 208080 kb
Host smart-5d4486db-c2d0-47f8-9a3b-f1b1f95ac38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287906721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2287906721
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1157508484
Short name T716
Test name
Test status
Simulation time 23669651316 ps
CPU time 187.5 seconds
Started Jul 05 05:39:02 PM PDT 24
Finished Jul 05 05:42:10 PM PDT 24
Peak memory 199912 kb
Host smart-54ac2fc7-5ff3-4dcb-b80d-5797492fa91e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157508484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1157508484
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2082437907
Short name T1063
Test name
Test status
Simulation time 6021214191 ps
CPU time 53.03 seconds
Started Jul 05 05:39:02 PM PDT 24
Finished Jul 05 05:39:56 PM PDT 24
Peak memory 198176 kb
Host smart-89b6ede3-8b86-428c-94b0-87498b9c33f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082437907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2082437907
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1837136993
Short name T1140
Test name
Test status
Simulation time 150933561631 ps
CPU time 198.17 seconds
Started Jul 05 05:39:04 PM PDT 24
Finished Jul 05 05:42:23 PM PDT 24
Peak memory 199912 kb
Host smart-f6a5cec8-ce05-46aa-953d-a109c525ce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837136993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1837136993
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3176860989
Short name T649
Test name
Test status
Simulation time 33469326754 ps
CPU time 3.18 seconds
Started Jul 05 05:39:02 PM PDT 24
Finished Jul 05 05:39:06 PM PDT 24
Peak memory 196256 kb
Host smart-16dcef8f-0605-4dce-ba10-f7b0ace74884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176860989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3176860989
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2866718784
Short name T897
Test name
Test status
Simulation time 974605402 ps
CPU time 4.44 seconds
Started Jul 05 05:39:01 PM PDT 24
Finished Jul 05 05:39:06 PM PDT 24
Peak memory 198832 kb
Host smart-7463d3eb-7da4-495c-968f-b483a465d740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866718784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2866718784
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.4258541351
Short name T450
Test name
Test status
Simulation time 162097602471 ps
CPU time 371.15 seconds
Started Jul 05 05:39:12 PM PDT 24
Finished Jul 05 05:45:24 PM PDT 24
Peak memory 199892 kb
Host smart-ef6b717f-1ecc-4210-b1e4-51589e2f78be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258541351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.4258541351
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3288774642
Short name T1113
Test name
Test status
Simulation time 18488517400 ps
CPU time 218.34 seconds
Started Jul 05 05:39:12 PM PDT 24
Finished Jul 05 05:42:51 PM PDT 24
Peak memory 216676 kb
Host smart-272e1d3b-6994-4766-88a7-f9f5d6e99e2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288774642 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3288774642
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3030990829
Short name T655
Test name
Test status
Simulation time 7254943797 ps
CPU time 8.98 seconds
Started Jul 05 05:39:26 PM PDT 24
Finished Jul 05 05:39:36 PM PDT 24
Peak memory 199544 kb
Host smart-ed26c65f-a354-491d-8a45-cd7488ae881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030990829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3030990829
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.4037060068
Short name T268
Test name
Test status
Simulation time 38490447774 ps
CPU time 13.52 seconds
Started Jul 05 05:39:04 PM PDT 24
Finished Jul 05 05:39:18 PM PDT 24
Peak memory 199896 kb
Host smart-8633a021-cbba-4f5e-a2d0-0babe63b8d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037060068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4037060068
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2753093906
Short name T337
Test name
Test status
Simulation time 12971730 ps
CPU time 0.56 seconds
Started Jul 05 05:39:10 PM PDT 24
Finished Jul 05 05:39:11 PM PDT 24
Peak memory 195288 kb
Host smart-36fa667c-cfe8-4213-a1da-d1faed79f238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753093906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2753093906
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1007852759
Short name T150
Test name
Test status
Simulation time 17044124713 ps
CPU time 7.7 seconds
Started Jul 05 05:39:12 PM PDT 24
Finished Jul 05 05:39:20 PM PDT 24
Peak memory 199864 kb
Host smart-aca3e361-9d8e-4e3b-8d3a-0fb1af0b8818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007852759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1007852759
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3061450751
Short name T619
Test name
Test status
Simulation time 9519729311 ps
CPU time 15.83 seconds
Started Jul 05 05:39:10 PM PDT 24
Finished Jul 05 05:39:26 PM PDT 24
Peak memory 199912 kb
Host smart-21862d5a-aa9f-4dbc-99f7-277b352bc4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061450751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3061450751
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3363780313
Short name T181
Test name
Test status
Simulation time 26507335753 ps
CPU time 48.87 seconds
Started Jul 05 05:39:09 PM PDT 24
Finished Jul 05 05:39:58 PM PDT 24
Peak memory 199992 kb
Host smart-d3945af8-a827-4ad1-96a3-3b69fcde9304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363780313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3363780313
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3675422047
Short name T740
Test name
Test status
Simulation time 19238208714 ps
CPU time 28.4 seconds
Started Jul 05 05:39:12 PM PDT 24
Finished Jul 05 05:39:41 PM PDT 24
Peak memory 199912 kb
Host smart-acccad59-cd6c-4fdc-980e-51b773a12b82
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675422047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3675422047
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1232386958
Short name T283
Test name
Test status
Simulation time 123459639568 ps
CPU time 255.01 seconds
Started Jul 05 05:39:11 PM PDT 24
Finished Jul 05 05:43:26 PM PDT 24
Peak memory 199988 kb
Host smart-43cae720-c12d-46c6-bd7e-f8999dac9f10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232386958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1232386958
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.821200062
Short name T659
Test name
Test status
Simulation time 395903596 ps
CPU time 1.39 seconds
Started Jul 05 05:39:12 PM PDT 24
Finished Jul 05 05:39:13 PM PDT 24
Peak memory 196280 kb
Host smart-07cd4f46-4ba9-4e3f-8a54-dcdbf668be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821200062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.821200062
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.433162409
Short name T766
Test name
Test status
Simulation time 18275207641 ps
CPU time 32.81 seconds
Started Jul 05 05:39:09 PM PDT 24
Finished Jul 05 05:39:42 PM PDT 24
Peak memory 199536 kb
Host smart-c5d1281c-a170-427e-b35b-dc74b1a0a2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433162409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.433162409
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1792834121
Short name T469
Test name
Test status
Simulation time 11797835671 ps
CPU time 147.65 seconds
Started Jul 05 05:39:12 PM PDT 24
Finished Jul 05 05:41:40 PM PDT 24
Peak memory 199944 kb
Host smart-395afe55-f5a6-466b-a5e4-2997ab4d89fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792834121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1792834121
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2919740
Short name T767
Test name
Test status
Simulation time 6472771258 ps
CPU time 37.12 seconds
Started Jul 05 05:39:12 PM PDT 24
Finished Jul 05 05:39:50 PM PDT 24
Peak memory 198364 kb
Host smart-8973c3c2-ae78-4315-963d-a7cee317d4c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2919740
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2643750839
Short name T175
Test name
Test status
Simulation time 85049791398 ps
CPU time 33.88 seconds
Started Jul 05 05:39:10 PM PDT 24
Finished Jul 05 05:39:45 PM PDT 24
Peak memory 199936 kb
Host smart-dec2fae7-4091-4fe5-b955-16afd4a28752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643750839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2643750839
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3922443213
Short name T712
Test name
Test status
Simulation time 491567635 ps
CPU time 1.35 seconds
Started Jul 05 05:39:10 PM PDT 24
Finished Jul 05 05:39:11 PM PDT 24
Peak memory 195464 kb
Host smart-5d9f4774-70af-4fb2-b3b1-cd3e34f4e1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922443213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3922443213
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3263277796
Short name T501
Test name
Test status
Simulation time 5294848831 ps
CPU time 17.8 seconds
Started Jul 05 05:39:12 PM PDT 24
Finished Jul 05 05:39:31 PM PDT 24
Peak memory 199708 kb
Host smart-816597eb-be2e-47a4-982f-62b889e971b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263277796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3263277796
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.15686446
Short name T916
Test name
Test status
Simulation time 46856136162 ps
CPU time 252.93 seconds
Started Jul 05 05:39:08 PM PDT 24
Finished Jul 05 05:43:21 PM PDT 24
Peak memory 199848 kb
Host smart-2c1c83d6-8614-4e62-9532-9062563d411f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15686446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.15686446
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.422303852
Short name T1101
Test name
Test status
Simulation time 40374704770 ps
CPU time 115.28 seconds
Started Jul 05 05:39:14 PM PDT 24
Finished Jul 05 05:41:10 PM PDT 24
Peak memory 211564 kb
Host smart-d09c43cf-5f40-48ba-8bf3-b7a242e8ee4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422303852 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.422303852
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3879540638
Short name T15
Test name
Test status
Simulation time 1591432960 ps
CPU time 2.09 seconds
Started Jul 05 05:39:09 PM PDT 24
Finished Jul 05 05:39:12 PM PDT 24
Peak memory 198904 kb
Host smart-078245e8-77bc-4416-a4e6-e28c3d977b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879540638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3879540638
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1735426924
Short name T466
Test name
Test status
Simulation time 80010107001 ps
CPU time 32.26 seconds
Started Jul 05 05:39:09 PM PDT 24
Finished Jul 05 05:39:42 PM PDT 24
Peak memory 199952 kb
Host smart-2c954b49-f1e7-41dc-a6d3-263c98e77693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735426924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1735426924
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2037231565
Short name T575
Test name
Test status
Simulation time 12362896 ps
CPU time 0.56 seconds
Started Jul 05 05:39:18 PM PDT 24
Finished Jul 05 05:39:19 PM PDT 24
Peak memory 195220 kb
Host smart-05f181c9-f26b-48d9-bba1-fd855a32cafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037231565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2037231565
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.4190759147
Short name T887
Test name
Test status
Simulation time 63243952199 ps
CPU time 47.03 seconds
Started Jul 05 05:39:18 PM PDT 24
Finished Jul 05 05:40:05 PM PDT 24
Peak memory 199960 kb
Host smart-a1c82bdd-c73a-485b-9a1a-9c942e661d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190759147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4190759147
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1812688308
Short name T457
Test name
Test status
Simulation time 15812808460 ps
CPU time 25.29 seconds
Started Jul 05 05:39:17 PM PDT 24
Finished Jul 05 05:39:43 PM PDT 24
Peak memory 199940 kb
Host smart-98bef619-9ba5-46c1-96cc-4442c439feec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812688308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1812688308
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3035943326
Short name T559
Test name
Test status
Simulation time 200981030875 ps
CPU time 35.57 seconds
Started Jul 05 05:39:15 PM PDT 24
Finished Jul 05 05:39:51 PM PDT 24
Peak memory 199968 kb
Host smart-e3068df1-0cd4-419c-ac05-33a0c36cddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035943326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3035943326
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.508560707
Short name T292
Test name
Test status
Simulation time 223059587394 ps
CPU time 173.33 seconds
Started Jul 05 05:39:18 PM PDT 24
Finished Jul 05 05:42:12 PM PDT 24
Peak memory 199840 kb
Host smart-614af2fa-9535-41f8-87b0-97f2d38509bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508560707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.508560707
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3824085155
Short name T1170
Test name
Test status
Simulation time 100478429203 ps
CPU time 228.67 seconds
Started Jul 05 05:39:17 PM PDT 24
Finished Jul 05 05:43:06 PM PDT 24
Peak memory 199956 kb
Host smart-133cc66d-dc01-4d8d-b6fd-ba598c389047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3824085155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3824085155
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3828626048
Short name T368
Test name
Test status
Simulation time 7603963396 ps
CPU time 4.56 seconds
Started Jul 05 05:39:17 PM PDT 24
Finished Jul 05 05:39:22 PM PDT 24
Peak memory 198344 kb
Host smart-d43b4a24-40bf-455f-a653-7d7e69a4b246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828626048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3828626048
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3756061419
Short name T304
Test name
Test status
Simulation time 42625450397 ps
CPU time 70.02 seconds
Started Jul 05 05:39:19 PM PDT 24
Finished Jul 05 05:40:29 PM PDT 24
Peak memory 200124 kb
Host smart-376d0376-58c4-4af5-84d3-7610ed6ad3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756061419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3756061419
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3522896684
Short name T854
Test name
Test status
Simulation time 27579357878 ps
CPU time 146.16 seconds
Started Jul 05 05:39:19 PM PDT 24
Finished Jul 05 05:41:45 PM PDT 24
Peak memory 199904 kb
Host smart-cd450fbb-41cb-4370-97d9-c13a7da91d0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522896684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3522896684
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2745614506
Short name T438
Test name
Test status
Simulation time 6880039764 ps
CPU time 66.06 seconds
Started Jul 05 05:39:18 PM PDT 24
Finished Jul 05 05:40:25 PM PDT 24
Peak memory 198180 kb
Host smart-19da1996-9c20-4183-8b70-ac5cdddb3817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745614506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2745614506
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1382931645
Short name T951
Test name
Test status
Simulation time 85327330310 ps
CPU time 13.08 seconds
Started Jul 05 05:39:18 PM PDT 24
Finished Jul 05 05:39:32 PM PDT 24
Peak memory 199992 kb
Host smart-65a162f7-9147-47ed-838e-cba9608f697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382931645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1382931645
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.229065062
Short name T913
Test name
Test status
Simulation time 4676442268 ps
CPU time 1.69 seconds
Started Jul 05 05:39:19 PM PDT 24
Finished Jul 05 05:39:21 PM PDT 24
Peak memory 196364 kb
Host smart-c2a3a561-db02-461d-ad10-35e643c10cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229065062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.229065062
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1621724997
Short name T365
Test name
Test status
Simulation time 672385864 ps
CPU time 1.93 seconds
Started Jul 05 05:39:18 PM PDT 24
Finished Jul 05 05:39:21 PM PDT 24
Peak memory 199844 kb
Host smart-1b143ab5-3fa0-498c-a1b4-eb2c7a54a42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621724997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1621724997
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.426323125
Short name T632
Test name
Test status
Simulation time 82191255971 ps
CPU time 435.77 seconds
Started Jul 05 05:39:20 PM PDT 24
Finished Jul 05 05:46:36 PM PDT 24
Peak memory 199912 kb
Host smart-c8f99ad1-39a7-4f1b-85b2-29e56726ecbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426323125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.426323125
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1664555244
Short name T681
Test name
Test status
Simulation time 28831863829 ps
CPU time 378.91 seconds
Started Jul 05 05:39:18 PM PDT 24
Finished Jul 05 05:45:37 PM PDT 24
Peak memory 216132 kb
Host smart-a991e51b-a82a-4f82-b6d5-560fa221c560
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664555244 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1664555244
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2890523355
Short name T373
Test name
Test status
Simulation time 1652914655 ps
CPU time 2.56 seconds
Started Jul 05 05:39:19 PM PDT 24
Finished Jul 05 05:39:23 PM PDT 24
Peak memory 198500 kb
Host smart-098689fc-dff6-4ffa-ba62-1a8081a78e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890523355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2890523355
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3375463476
Short name T319
Test name
Test status
Simulation time 68867016254 ps
CPU time 29.18 seconds
Started Jul 05 05:39:18 PM PDT 24
Finished Jul 05 05:39:48 PM PDT 24
Peak memory 199984 kb
Host smart-8abbe3d0-5dbb-4e22-9290-83d3cee4bf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375463476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3375463476
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1289921821
Short name T511
Test name
Test status
Simulation time 31720962 ps
CPU time 0.56 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:39:28 PM PDT 24
Peak memory 195608 kb
Host smart-cfc8e8bb-f640-4ded-9d55-0bb810f1d4fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289921821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1289921821
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3854857035
Short name T611
Test name
Test status
Simulation time 149353109597 ps
CPU time 69.17 seconds
Started Jul 05 05:39:19 PM PDT 24
Finished Jul 05 05:40:29 PM PDT 24
Peak memory 199972 kb
Host smart-fe64711b-8a82-4cd7-93ab-086e895c673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854857035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3854857035
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2522047969
Short name T1104
Test name
Test status
Simulation time 48157204724 ps
CPU time 38.1 seconds
Started Jul 05 05:39:18 PM PDT 24
Finished Jul 05 05:39:57 PM PDT 24
Peak memory 200000 kb
Host smart-2255c676-6577-4fe5-b49f-6ef0729ad199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522047969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2522047969
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.606427974
Short name T1035
Test name
Test status
Simulation time 40452503596 ps
CPU time 62.91 seconds
Started Jul 05 05:39:19 PM PDT 24
Finished Jul 05 05:40:22 PM PDT 24
Peak memory 199988 kb
Host smart-2abb89c3-81fb-4ab0-b7b2-e8830c46096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606427974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.606427974
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.680850605
Short name T596
Test name
Test status
Simulation time 46177644023 ps
CPU time 52.81 seconds
Started Jul 05 05:39:17 PM PDT 24
Finished Jul 05 05:40:10 PM PDT 24
Peak memory 199852 kb
Host smart-7703e44a-0805-4929-8c44-79597b89d475
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680850605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.680850605
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.4245305963
Short name T859
Test name
Test status
Simulation time 130296381400 ps
CPU time 310.15 seconds
Started Jul 05 05:39:26 PM PDT 24
Finished Jul 05 05:44:37 PM PDT 24
Peak memory 200008 kb
Host smart-5d9623a8-5060-4181-b768-4562b43d0df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245305963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.4245305963
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1186755280
Short name T387
Test name
Test status
Simulation time 11008683124 ps
CPU time 11.88 seconds
Started Jul 05 05:39:25 PM PDT 24
Finished Jul 05 05:39:37 PM PDT 24
Peak memory 199944 kb
Host smart-b7e0697c-010b-47ca-a65f-794e2b645729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186755280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1186755280
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2164708506
Short name T813
Test name
Test status
Simulation time 46755174962 ps
CPU time 80.71 seconds
Started Jul 05 05:39:24 PM PDT 24
Finished Jul 05 05:40:46 PM PDT 24
Peak memory 200240 kb
Host smart-6bb38a17-d894-4e3a-bf5f-5874a4f34d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164708506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2164708506
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.887668426
Short name T243
Test name
Test status
Simulation time 12335138583 ps
CPU time 158.14 seconds
Started Jul 05 05:39:24 PM PDT 24
Finished Jul 05 05:42:02 PM PDT 24
Peak memory 199944 kb
Host smart-2c3dcf42-0a89-408f-b9d8-724fb4e490f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887668426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.887668426
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.479935580
Short name T385
Test name
Test status
Simulation time 6157700863 ps
CPU time 13.56 seconds
Started Jul 05 05:39:19 PM PDT 24
Finished Jul 05 05:39:33 PM PDT 24
Peak memory 198808 kb
Host smart-15ebc86d-1761-4daf-98c1-3d12f642d356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479935580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.479935580
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2710148381
Short name T1066
Test name
Test status
Simulation time 188789866561 ps
CPU time 73.04 seconds
Started Jul 05 05:39:17 PM PDT 24
Finished Jul 05 05:40:31 PM PDT 24
Peak memory 199936 kb
Host smart-ec6c2967-1a1b-41c4-a80e-353a79c25dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710148381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2710148381
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2943388826
Short name T367
Test name
Test status
Simulation time 2625881681 ps
CPU time 4.2 seconds
Started Jul 05 05:39:19 PM PDT 24
Finished Jul 05 05:39:24 PM PDT 24
Peak memory 196428 kb
Host smart-7a84744c-54ba-4d3c-9353-7733b334bb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943388826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2943388826
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2264699187
Short name T1016
Test name
Test status
Simulation time 612103314 ps
CPU time 0.96 seconds
Started Jul 05 05:39:20 PM PDT 24
Finished Jul 05 05:39:21 PM PDT 24
Peak memory 199388 kb
Host smart-1ba13f02-a959-4e60-8d64-2476f13d6be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264699187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2264699187
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2476279918
Short name T198
Test name
Test status
Simulation time 71670547103 ps
CPU time 172.77 seconds
Started Jul 05 05:39:24 PM PDT 24
Finished Jul 05 05:42:17 PM PDT 24
Peak memory 199888 kb
Host smart-868c89a1-6f70-46b3-8a59-8c715919d788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476279918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2476279918
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2046106588
Short name T954
Test name
Test status
Simulation time 32736569104 ps
CPU time 336.21 seconds
Started Jul 05 05:39:25 PM PDT 24
Finished Jul 05 05:45:02 PM PDT 24
Peak memory 216740 kb
Host smart-6407bfd9-6e8e-461d-a37e-dbfdb1349641
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046106588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2046106588
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2784487899
Short name T646
Test name
Test status
Simulation time 1383978847 ps
CPU time 2.74 seconds
Started Jul 05 05:39:26 PM PDT 24
Finished Jul 05 05:39:29 PM PDT 24
Peak memory 198240 kb
Host smart-0850f785-0a7e-4394-928b-7749f7c7e9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784487899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2784487899
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2631615086
Short name T274
Test name
Test status
Simulation time 95363212276 ps
CPU time 281.67 seconds
Started Jul 05 05:39:19 PM PDT 24
Finished Jul 05 05:44:02 PM PDT 24
Peak memory 199916 kb
Host smart-b86b1c09-c67f-4283-b3cf-8a6f9d0c4a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631615086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2631615086
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1094635858
Short name T351
Test name
Test status
Simulation time 22159430 ps
CPU time 0.56 seconds
Started Jul 05 05:39:24 PM PDT 24
Finished Jul 05 05:39:25 PM PDT 24
Peak memory 195560 kb
Host smart-b9ac6d69-d188-4e66-b7e2-0a470646430d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094635858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1094635858
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2679383094
Short name T383
Test name
Test status
Simulation time 14782302486 ps
CPU time 16.77 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:39:45 PM PDT 24
Peak memory 199984 kb
Host smart-3d83b2f1-4e11-4b7d-adcf-02eb515a56ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679383094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2679383094
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1546824077
Short name T963
Test name
Test status
Simulation time 42913736182 ps
CPU time 83.62 seconds
Started Jul 05 05:39:25 PM PDT 24
Finished Jul 05 05:40:49 PM PDT 24
Peak memory 199956 kb
Host smart-08ef688b-7674-4d46-934f-611a55da95ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546824077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1546824077
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1448244995
Short name T752
Test name
Test status
Simulation time 35267247016 ps
CPU time 63.9 seconds
Started Jul 05 05:39:26 PM PDT 24
Finished Jul 05 05:40:31 PM PDT 24
Peak memory 199940 kb
Host smart-cc216c45-e350-458e-a0e7-392a45a137e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448244995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1448244995
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1549623447
Short name T354
Test name
Test status
Simulation time 41410280297 ps
CPU time 59.87 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:40:35 PM PDT 24
Peak memory 199392 kb
Host smart-c82076fd-06af-4216-9942-1643bc100387
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549623447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1549623447
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3277662907
Short name T288
Test name
Test status
Simulation time 122661920450 ps
CPU time 223.8 seconds
Started Jul 05 05:39:28 PM PDT 24
Finished Jul 05 05:43:12 PM PDT 24
Peak memory 199984 kb
Host smart-88fe1079-907e-4fec-abaa-31b3ac244871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277662907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3277662907
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.819685539
Short name T697
Test name
Test status
Simulation time 3496105566 ps
CPU time 6.59 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:39:34 PM PDT 24
Peak memory 196256 kb
Host smart-522f57ca-7de5-4f39-af17-5aefa33fdbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819685539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.819685539
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.861201301
Short name T661
Test name
Test status
Simulation time 85459729553 ps
CPU time 119.32 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:41:27 PM PDT 24
Peak memory 200080 kb
Host smart-0eae5175-aa70-41b7-baee-b61983f9c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861201301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.861201301
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.4088268874
Short name T250
Test name
Test status
Simulation time 12141386179 ps
CPU time 124.99 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:41:39 PM PDT 24
Peak memory 199988 kb
Host smart-1471f4e5-9fa9-4c7d-8282-657dbdedddc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088268874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.4088268874
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3234315381
Short name T604
Test name
Test status
Simulation time 6034867468 ps
CPU time 54.73 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:40:23 PM PDT 24
Peak memory 198092 kb
Host smart-1c7da0f3-6bd5-4283-8061-11adb9492552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234315381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3234315381
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.968467391
Short name T145
Test name
Test status
Simulation time 130558454005 ps
CPU time 180.62 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:42:29 PM PDT 24
Peak memory 200000 kb
Host smart-020a926f-5fb6-44a0-ace0-ade2a96c0ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968467391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.968467391
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3847829623
Short name T573
Test name
Test status
Simulation time 4761380810 ps
CPU time 7.47 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:39:41 PM PDT 24
Peak memory 196436 kb
Host smart-8cacc396-d65e-4c58-a611-0dc9296a7e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847829623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3847829623
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4066357587
Short name T702
Test name
Test status
Simulation time 905489766 ps
CPU time 2.37 seconds
Started Jul 05 05:39:26 PM PDT 24
Finished Jul 05 05:39:29 PM PDT 24
Peak memory 199508 kb
Host smart-ac80e1d7-b8de-4c1f-ba0a-c07c1feeffcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066357587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4066357587
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.916765655
Short name T800
Test name
Test status
Simulation time 180778371422 ps
CPU time 535.38 seconds
Started Jul 05 05:39:26 PM PDT 24
Finished Jul 05 05:48:22 PM PDT 24
Peak memory 199980 kb
Host smart-29d0ec04-6560-4e30-a6d5-a4b5b34eb760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916765655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.916765655
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2811314367
Short name T41
Test name
Test status
Simulation time 88383227205 ps
CPU time 648.06 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:50:16 PM PDT 24
Peak memory 216460 kb
Host smart-6a173902-81db-41f5-a088-4a4d2620edb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811314367 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2811314367
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2917115377
Short name T955
Test name
Test status
Simulation time 1713105970 ps
CPU time 1.85 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:39:30 PM PDT 24
Peak memory 198324 kb
Host smart-cb966ad7-7ad5-42e9-9089-f60bedbe93d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917115377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2917115377
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3109768181
Short name T565
Test name
Test status
Simulation time 8971976832 ps
CPU time 14.66 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:39:42 PM PDT 24
Peak memory 199952 kb
Host smart-3480751f-4e29-4c3b-bc94-e4060090ca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109768181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3109768181
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3968844162
Short name T883
Test name
Test status
Simulation time 16383839 ps
CPU time 0.58 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:39:34 PM PDT 24
Peak memory 194744 kb
Host smart-1be0cc22-ea7a-4130-b313-010db5321d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968844162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3968844162
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2182860893
Short name T59
Test name
Test status
Simulation time 22074204048 ps
CPU time 15.02 seconds
Started Jul 05 05:39:26 PM PDT 24
Finished Jul 05 05:39:41 PM PDT 24
Peak memory 199864 kb
Host smart-161ee1dd-3ce1-4549-a50f-c99d6e1ace0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182860893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2182860893
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3912052869
Short name T671
Test name
Test status
Simulation time 44156451679 ps
CPU time 18.58 seconds
Started Jul 05 05:39:32 PM PDT 24
Finished Jul 05 05:39:51 PM PDT 24
Peak memory 199968 kb
Host smart-d6264652-ac03-46b6-89dc-d2f9ad4ec2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912052869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3912052869
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.244991988
Short name T889
Test name
Test status
Simulation time 31524184839 ps
CPU time 16.01 seconds
Started Jul 05 05:39:25 PM PDT 24
Finished Jul 05 05:39:42 PM PDT 24
Peak memory 199868 kb
Host smart-915e64d0-99f7-44e5-b868-6a79de398b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244991988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.244991988
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1823600220
Short name T402
Test name
Test status
Simulation time 142923725668 ps
CPU time 257.28 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:43:51 PM PDT 24
Peak memory 199812 kb
Host smart-c0864966-cfb6-4ef7-bbaa-c24f68c04671
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823600220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1823600220
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.67086165
Short name T929
Test name
Test status
Simulation time 100567214774 ps
CPU time 771.77 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:52:19 PM PDT 24
Peak memory 199988 kb
Host smart-0d74586a-2aee-416c-9d3d-730ba6d09f4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67086165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.67086165
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.371971000
Short name T1148
Test name
Test status
Simulation time 9281949304 ps
CPU time 5.67 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:39:33 PM PDT 24
Peak memory 199968 kb
Host smart-6f738709-5463-4efa-82da-c7cf9aac7e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371971000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.371971000
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1839717252
Short name T1007
Test name
Test status
Simulation time 127007525 ps
CPU time 0.83 seconds
Started Jul 05 05:39:27 PM PDT 24
Finished Jul 05 05:39:29 PM PDT 24
Peak memory 199804 kb
Host smart-1744e18f-25c1-4d38-aa83-ecb698f3faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839717252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1839717252
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.261296069
Short name T735
Test name
Test status
Simulation time 30807589955 ps
CPU time 677.63 seconds
Started Jul 05 05:39:26 PM PDT 24
Finished Jul 05 05:50:45 PM PDT 24
Peak memory 199872 kb
Host smart-8ce240e9-358a-4d85-b514-08c3eaee8ad4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261296069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.261296069
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2838959880
Short name T792
Test name
Test status
Simulation time 6791687364 ps
CPU time 28.84 seconds
Started Jul 05 05:39:26 PM PDT 24
Finished Jul 05 05:39:56 PM PDT 24
Peak memory 198184 kb
Host smart-a4da100b-a4b7-4583-8744-e2a62e410bc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838959880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2838959880
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.4122061688
Short name T678
Test name
Test status
Simulation time 212582447343 ps
CPU time 370.87 seconds
Started Jul 05 05:39:24 PM PDT 24
Finished Jul 05 05:45:35 PM PDT 24
Peak memory 200000 kb
Host smart-def4b75d-2d54-47b9-8600-20fdc5845fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122061688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.4122061688
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1520961963
Short name T1108
Test name
Test status
Simulation time 560676898 ps
CPU time 0.86 seconds
Started Jul 05 05:39:25 PM PDT 24
Finished Jul 05 05:39:26 PM PDT 24
Peak memory 195432 kb
Host smart-8863f55a-926b-42be-80d3-9181ddf8ec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520961963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1520961963
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2327792105
Short name T239
Test name
Test status
Simulation time 5676661554 ps
CPU time 16.23 seconds
Started Jul 05 05:39:24 PM PDT 24
Finished Jul 05 05:39:41 PM PDT 24
Peak memory 199076 kb
Host smart-7cf9d0fe-7eb8-4380-9f07-9fc267eb1faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327792105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2327792105
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2985345964
Short name T1033
Test name
Test status
Simulation time 125493930923 ps
CPU time 52.08 seconds
Started Jul 05 05:39:30 PM PDT 24
Finished Jul 05 05:40:22 PM PDT 24
Peak memory 199844 kb
Host smart-736aa37d-f8dc-4e53-b901-646392b5d006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985345964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2985345964
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2975965515
Short name T393
Test name
Test status
Simulation time 16266540284 ps
CPU time 643.54 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 216540 kb
Host smart-56481124-6e17-4e20-804b-33321dd56d2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975965515 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2975965515
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1334817210
Short name T419
Test name
Test status
Simulation time 7249790887 ps
CPU time 10.15 seconds
Started Jul 05 05:39:25 PM PDT 24
Finished Jul 05 05:39:36 PM PDT 24
Peak memory 199868 kb
Host smart-dfefff3f-2da8-4228-99fc-5cc6199005dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334817210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1334817210
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.4206323641
Short name T1087
Test name
Test status
Simulation time 9827698937 ps
CPU time 16.45 seconds
Started Jul 05 05:39:23 PM PDT 24
Finished Jul 05 05:39:40 PM PDT 24
Peak memory 199996 kb
Host smart-b530d614-c2e6-4e09-82c9-452c88b1cae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206323641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4206323641
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2974768304
Short name T1099
Test name
Test status
Simulation time 15424403 ps
CPU time 0.56 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:39:34 PM PDT 24
Peak memory 195276 kb
Host smart-51e477f7-c6fe-428d-81d0-adcec6df279b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974768304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2974768304
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1656312398
Short name T93
Test name
Test status
Simulation time 16475331583 ps
CPU time 8.17 seconds
Started Jul 05 05:39:31 PM PDT 24
Finished Jul 05 05:39:39 PM PDT 24
Peak memory 199912 kb
Host smart-6f84bcb3-e83e-4584-885a-327a60e729b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656312398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1656312398
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2863797105
Short name T679
Test name
Test status
Simulation time 24043818884 ps
CPU time 19.44 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:39:54 PM PDT 24
Peak memory 199996 kb
Host smart-5c58a830-2884-4a9a-a710-099d5d7f927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863797105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2863797105
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.201896441
Short name T478
Test name
Test status
Simulation time 74066748933 ps
CPU time 34.21 seconds
Started Jul 05 05:39:36 PM PDT 24
Finished Jul 05 05:40:11 PM PDT 24
Peak memory 199872 kb
Host smart-74f8dc0e-31bc-4023-8a3c-51cf3bcdd474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201896441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.201896441
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1845923824
Short name T566
Test name
Test status
Simulation time 12000853110 ps
CPU time 42.39 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:40:18 PM PDT 24
Peak memory 199944 kb
Host smart-da0caa2a-d9e7-4ab0-9d15-728ad420b624
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845923824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1845923824
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1374661294
Short name T831
Test name
Test status
Simulation time 70552968837 ps
CPU time 561.24 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:48:57 PM PDT 24
Peak memory 199984 kb
Host smart-3fa963d2-31b5-4168-ae90-3275547d4746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374661294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1374661294
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1809970549
Short name T971
Test name
Test status
Simulation time 3810237816 ps
CPU time 3.34 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:39:38 PM PDT 24
Peak memory 198428 kb
Host smart-fb807c09-e55e-4434-896c-382a72e8db66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809970549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1809970549
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1954105195
Short name T525
Test name
Test status
Simulation time 16824051407 ps
CPU time 15.15 seconds
Started Jul 05 05:39:37 PM PDT 24
Finished Jul 05 05:39:53 PM PDT 24
Peak memory 195092 kb
Host smart-410f3246-cde8-4a54-a8a0-b3b5ef8d6b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954105195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1954105195
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.404008271
Short name T37
Test name
Test status
Simulation time 20658941321 ps
CPU time 1151.76 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:58:47 PM PDT 24
Peak memory 199880 kb
Host smart-e658a790-fb79-47fa-803b-686fb8f01057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=404008271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.404008271
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.4103138140
Short name T922
Test name
Test status
Simulation time 6483643706 ps
CPU time 59.48 seconds
Started Jul 05 05:39:35 PM PDT 24
Finished Jul 05 05:40:35 PM PDT 24
Peak memory 198180 kb
Host smart-3e7bf393-327d-4f19-8ac0-6a7e53c166df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103138140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.4103138140
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.439038751
Short name T875
Test name
Test status
Simulation time 284997449325 ps
CPU time 184.22 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:42:40 PM PDT 24
Peak memory 200008 kb
Host smart-a59299e1-6c2b-478b-96db-1f9393e2d902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439038751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.439038751
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.88446773
Short name T746
Test name
Test status
Simulation time 4486178412 ps
CPU time 1.14 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:39:35 PM PDT 24
Peak memory 196036 kb
Host smart-97292325-f8f4-4339-9332-a271df564a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88446773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.88446773
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3670425776
Short name T298
Test name
Test status
Simulation time 6154036783 ps
CPU time 13.98 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:39:50 PM PDT 24
Peak memory 199764 kb
Host smart-4ed4b5fb-aa61-49bf-8948-1ee2507a715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670425776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3670425776
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2627572206
Short name T1164
Test name
Test status
Simulation time 97310616729 ps
CPU time 644.14 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:50:20 PM PDT 24
Peak memory 224908 kb
Host smart-9e5df93a-73c5-41fc-abf5-9e5f293141fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627572206 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2627572206
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.889703512
Short name T817
Test name
Test status
Simulation time 6632014050 ps
CPU time 16.8 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:39:52 PM PDT 24
Peak memory 199388 kb
Host smart-4cd8f7b4-3f5f-402c-bb29-37c30c1a7e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889703512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.889703512
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1099694675
Short name T763
Test name
Test status
Simulation time 27082368876 ps
CPU time 12.49 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:39:48 PM PDT 24
Peak memory 199932 kb
Host smart-ea58bd0d-9bf9-4289-bca2-102b30dc3c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099694675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1099694675
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.654339717
Short name T1027
Test name
Test status
Simulation time 51797545 ps
CPU time 0.58 seconds
Started Jul 05 05:39:43 PM PDT 24
Finished Jul 05 05:39:44 PM PDT 24
Peak memory 195216 kb
Host smart-99c02b25-73a2-4acf-80d7-d7a4aca9e51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654339717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.654339717
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1878201768
Short name T247
Test name
Test status
Simulation time 64367987058 ps
CPU time 50.08 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:40:25 PM PDT 24
Peak memory 199440 kb
Host smart-8c6297ba-9e99-4d61-b840-5692bb42afbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878201768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1878201768
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1812397397
Short name T1020
Test name
Test status
Simulation time 19735814822 ps
CPU time 27.86 seconds
Started Jul 05 05:39:35 PM PDT 24
Finished Jul 05 05:40:04 PM PDT 24
Peak memory 199944 kb
Host smart-4d65aedb-71e7-4bd8-8f45-fb708295301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812397397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1812397397
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.48408924
Short name T783
Test name
Test status
Simulation time 31368783120 ps
CPU time 12.41 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:39:46 PM PDT 24
Peak memory 199916 kb
Host smart-6e2123b8-fdaa-44d0-b163-093782bc0b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48408924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.48408924
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1934223827
Short name T841
Test name
Test status
Simulation time 36638514074 ps
CPU time 62 seconds
Started Jul 05 05:39:31 PM PDT 24
Finished Jul 05 05:40:33 PM PDT 24
Peak memory 199676 kb
Host smart-666841f9-fa4d-4805-a3cf-09b8b5c70fdd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934223827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1934223827
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1685342233
Short name T634
Test name
Test status
Simulation time 84855442845 ps
CPU time 483.37 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:47:39 PM PDT 24
Peak memory 199916 kb
Host smart-7ffa1a3f-bdb4-4bf7-944b-5702d6821ecd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685342233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1685342233
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3884496533
Short name T407
Test name
Test status
Simulation time 7223929622 ps
CPU time 13.44 seconds
Started Jul 05 05:39:33 PM PDT 24
Finished Jul 05 05:39:46 PM PDT 24
Peak memory 198264 kb
Host smart-c6e853fc-19fb-44fa-8a4e-5d634b878fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884496533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3884496533
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1735741383
Short name T519
Test name
Test status
Simulation time 58193901669 ps
CPU time 24.76 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:40:00 PM PDT 24
Peak memory 198260 kb
Host smart-7443e947-dda5-45f9-8db9-a6fa08165332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735741383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1735741383
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1938747078
Short name T485
Test name
Test status
Simulation time 23679281686 ps
CPU time 291.25 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:44:26 PM PDT 24
Peak memory 199956 kb
Host smart-07c4c6e1-c8b1-4a60-9a4a-7518add2b3ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938747078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1938747078
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.619882502
Short name T1115
Test name
Test status
Simulation time 7402411290 ps
CPU time 64.94 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:40:40 PM PDT 24
Peak memory 198788 kb
Host smart-ad951a9f-fe18-4490-917b-40ea1d181f72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619882502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.619882502
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.712448769
Short name T388
Test name
Test status
Simulation time 11926440375 ps
CPU time 10.12 seconds
Started Jul 05 05:39:37 PM PDT 24
Finished Jul 05 05:39:47 PM PDT 24
Peak memory 199904 kb
Host smart-7b71a92c-df2a-4a99-a49e-d368878a27bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712448769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.712448769
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.829143390
Short name T1072
Test name
Test status
Simulation time 838618661 ps
CPU time 1.85 seconds
Started Jul 05 05:39:35 PM PDT 24
Finished Jul 05 05:39:38 PM PDT 24
Peak memory 195372 kb
Host smart-537bd0bf-22bd-4a2d-931a-76c403989b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829143390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.829143390
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2276877126
Short name T778
Test name
Test status
Simulation time 650311434 ps
CPU time 1.31 seconds
Started Jul 05 05:39:34 PM PDT 24
Finished Jul 05 05:39:36 PM PDT 24
Peak memory 198880 kb
Host smart-e889e632-16ce-487f-86ae-44ab2286c461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276877126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2276877126
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.579044477
Short name T161
Test name
Test status
Simulation time 283773661230 ps
CPU time 124.01 seconds
Started Jul 05 05:39:42 PM PDT 24
Finished Jul 05 05:41:46 PM PDT 24
Peak memory 199980 kb
Host smart-9fe2f72d-7470-43c4-a0c8-aa566ac389c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579044477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.579044477
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2881770665
Short name T829
Test name
Test status
Simulation time 9703175232 ps
CPU time 104.3 seconds
Started Jul 05 05:39:36 PM PDT 24
Finished Jul 05 05:41:21 PM PDT 24
Peak memory 215828 kb
Host smart-aa148f05-329f-48cc-801a-81323e2af6c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881770665 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2881770665
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2366651547
Short name T350
Test name
Test status
Simulation time 1042397925 ps
CPU time 2.03 seconds
Started Jul 05 05:39:36 PM PDT 24
Finished Jul 05 05:39:39 PM PDT 24
Peak memory 199516 kb
Host smart-a0e8fece-72c9-4e93-ad6d-6154ac53a992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366651547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2366651547
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_alert_test.2310810969
Short name T987
Test name
Test status
Simulation time 134849652 ps
CPU time 0.56 seconds
Started Jul 05 05:37:05 PM PDT 24
Finished Jul 05 05:37:07 PM PDT 24
Peak memory 195612 kb
Host smart-b205d074-5c98-46c1-812d-234955d7d3a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310810969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2310810969
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1241948526
Short name T338
Test name
Test status
Simulation time 46494673521 ps
CPU time 17.95 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:37:36 PM PDT 24
Peak memory 199444 kb
Host smart-d6fe5b39-bc26-40fd-a688-74b7c67e97c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241948526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1241948526
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2656077864
Short name T305
Test name
Test status
Simulation time 38653825928 ps
CPU time 12.04 seconds
Started Jul 05 05:37:05 PM PDT 24
Finished Jul 05 05:37:18 PM PDT 24
Peak memory 199812 kb
Host smart-2c8b50d7-66a2-4290-9a48-f7bbbf38090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656077864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2656077864
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3799335375
Short name T137
Test name
Test status
Simulation time 64456829685 ps
CPU time 27.75 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 05:38:02 PM PDT 24
Peak memory 200012 kb
Host smart-44f2fdc6-fbb3-4811-892f-8ad2685e48b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799335375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3799335375
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2383891237
Short name T715
Test name
Test status
Simulation time 61565080264 ps
CPU time 60.52 seconds
Started Jul 05 05:37:08 PM PDT 24
Finished Jul 05 05:38:09 PM PDT 24
Peak memory 199976 kb
Host smart-43a3abf9-7adc-45a2-91c3-f7d618160caa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383891237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2383891237
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1213637897
Short name T975
Test name
Test status
Simulation time 65759748008 ps
CPU time 156.32 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:39:54 PM PDT 24
Peak memory 199240 kb
Host smart-1a152b4c-2712-42d2-b114-701b28d9ebc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1213637897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1213637897
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1142669648
Short name T1146
Test name
Test status
Simulation time 6687551128 ps
CPU time 6.01 seconds
Started Jul 05 05:37:04 PM PDT 24
Finished Jul 05 05:37:12 PM PDT 24
Peak memory 199528 kb
Host smart-00f73436-724a-4d9a-ba22-00e994430196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142669648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1142669648
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.432928134
Short name T295
Test name
Test status
Simulation time 49882139990 ps
CPU time 65.17 seconds
Started Jul 05 05:37:05 PM PDT 24
Finished Jul 05 05:38:12 PM PDT 24
Peak memory 200100 kb
Host smart-b840e7dc-7ea5-4b5e-86fb-664eac4125a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432928134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.432928134
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1728835942
Short name T864
Test name
Test status
Simulation time 17770439520 ps
CPU time 1056.2 seconds
Started Jul 05 05:37:07 PM PDT 24
Finished Jul 05 05:54:45 PM PDT 24
Peak memory 200000 kb
Host smart-7fb017f6-b3f5-4427-9844-8efbf2ac27f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728835942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1728835942
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2490283560
Short name T340
Test name
Test status
Simulation time 1901934175 ps
CPU time 9.33 seconds
Started Jul 05 05:37:14 PM PDT 24
Finished Jul 05 05:37:24 PM PDT 24
Peak memory 198116 kb
Host smart-87cd452e-1eff-4d3d-ab4e-8ce77cab1910
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490283560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2490283560
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.440237435
Short name T590
Test name
Test status
Simulation time 25220921520 ps
CPU time 17.25 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:37:36 PM PDT 24
Peak memory 199888 kb
Host smart-818f15d8-d28a-47bf-a8a8-f7b626047093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440237435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.440237435
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1520956541
Short name T989
Test name
Test status
Simulation time 2442584472 ps
CPU time 3.99 seconds
Started Jul 05 05:37:04 PM PDT 24
Finished Jul 05 05:37:10 PM PDT 24
Peak memory 196496 kb
Host smart-7e50cfcc-4b80-49ad-ac35-afc97337d2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520956541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1520956541
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3619374073
Short name T665
Test name
Test status
Simulation time 307800656 ps
CPU time 0.92 seconds
Started Jul 05 05:37:05 PM PDT 24
Finished Jul 05 05:37:08 PM PDT 24
Peak memory 198304 kb
Host smart-9d29ba8d-9a86-4647-8d1c-785b9014213c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619374073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3619374073
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3168092831
Short name T195
Test name
Test status
Simulation time 35192919986 ps
CPU time 310.94 seconds
Started Jul 05 05:37:34 PM PDT 24
Finished Jul 05 05:42:46 PM PDT 24
Peak memory 215924 kb
Host smart-42593362-ed2a-4e47-b675-cf177e9dc40e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168092831 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3168092831
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2006508215
Short name T499
Test name
Test status
Simulation time 887257719 ps
CPU time 3.49 seconds
Started Jul 05 05:37:06 PM PDT 24
Finished Jul 05 05:37:10 PM PDT 24
Peak memory 198700 kb
Host smart-13746f87-e5de-4d2e-82a0-202565a6571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006508215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2006508215
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3620989157
Short name T529
Test name
Test status
Simulation time 111199941696 ps
CPU time 37.65 seconds
Started Jul 05 05:37:07 PM PDT 24
Finished Jul 05 05:37:51 PM PDT 24
Peak memory 199868 kb
Host smart-c1243eeb-b703-48c4-bf26-b877d3030b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620989157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3620989157
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.109919755
Short name T196
Test name
Test status
Simulation time 58126158535 ps
CPU time 12.37 seconds
Started Jul 05 05:39:42 PM PDT 24
Finished Jul 05 05:39:55 PM PDT 24
Peak memory 199816 kb
Host smart-5084d1d6-83ed-473f-8999-7aa7be635b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109919755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.109919755
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.466113108
Short name T867
Test name
Test status
Simulation time 348127282202 ps
CPU time 1116.02 seconds
Started Jul 05 05:39:44 PM PDT 24
Finished Jul 05 05:58:21 PM PDT 24
Peak memory 224672 kb
Host smart-b56b25a1-c429-4165-a2fb-f2ef4cffca6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466113108 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.466113108
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2600600926
Short name T794
Test name
Test status
Simulation time 24087931589 ps
CPU time 12 seconds
Started Jul 05 05:39:45 PM PDT 24
Finished Jul 05 05:39:58 PM PDT 24
Peak memory 199576 kb
Host smart-d3287090-474f-4094-831e-356480ab721d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600600926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2600600926
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2702743583
Short name T1117
Test name
Test status
Simulation time 16080484505 ps
CPU time 16.01 seconds
Started Jul 05 05:39:43 PM PDT 24
Finished Jul 05 05:40:00 PM PDT 24
Peak memory 199908 kb
Host smart-e82af6db-d356-4d65-972e-0562594cdb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702743583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2702743583
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.303371274
Short name T1122
Test name
Test status
Simulation time 100660787821 ps
CPU time 1397.47 seconds
Started Jul 05 05:39:48 PM PDT 24
Finished Jul 05 06:03:06 PM PDT 24
Peak memory 212300 kb
Host smart-3fd4a1c1-18e9-4921-9c8f-163a44e80d92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303371274 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.303371274
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1923679785
Short name T1152
Test name
Test status
Simulation time 61169481302 ps
CPU time 24.98 seconds
Started Jul 05 05:39:42 PM PDT 24
Finished Jul 05 05:40:08 PM PDT 24
Peak memory 199892 kb
Host smart-d0a206f4-c2a7-4fb6-8a07-c3128a168a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923679785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1923679785
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2069556996
Short name T924
Test name
Test status
Simulation time 38054461804 ps
CPU time 580.27 seconds
Started Jul 05 05:39:43 PM PDT 24
Finished Jul 05 05:49:24 PM PDT 24
Peak memory 216528 kb
Host smart-2c763633-8b50-4cf7-90c0-13384a3c1a34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069556996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2069556996
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3167198562
Short name T219
Test name
Test status
Simulation time 41768622194 ps
CPU time 23.41 seconds
Started Jul 05 05:39:42 PM PDT 24
Finished Jul 05 05:40:06 PM PDT 24
Peak memory 199976 kb
Host smart-dee0e612-aa3b-40c3-a551-ca3d14e75571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167198562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3167198562
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1892278398
Short name T103
Test name
Test status
Simulation time 49675407562 ps
CPU time 240.85 seconds
Started Jul 05 05:39:43 PM PDT 24
Finished Jul 05 05:43:45 PM PDT 24
Peak memory 216476 kb
Host smart-1f7a9952-435e-42e9-817a-395b792f5ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892278398 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1892278398
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.180425533
Short name T755
Test name
Test status
Simulation time 85740498254 ps
CPU time 21.74 seconds
Started Jul 05 05:40:19 PM PDT 24
Finished Jul 05 05:40:41 PM PDT 24
Peak memory 199980 kb
Host smart-51920f4b-fd91-4421-bafd-795f747d1e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180425533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.180425533
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1634144923
Short name T637
Test name
Test status
Simulation time 91625580667 ps
CPU time 1034.37 seconds
Started Jul 05 05:39:44 PM PDT 24
Finished Jul 05 05:57:00 PM PDT 24
Peak memory 224684 kb
Host smart-acf27ec9-dd35-4c39-a238-d448bd36ac1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634144923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1634144923
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1985405489
Short name T547
Test name
Test status
Simulation time 49997158791 ps
CPU time 4.94 seconds
Started Jul 05 05:39:44 PM PDT 24
Finished Jul 05 05:39:50 PM PDT 24
Peak memory 199984 kb
Host smart-02fb3dfc-f377-47cc-a02e-b4399859b31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985405489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1985405489
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3402173525
Short name T633
Test name
Test status
Simulation time 24498980082 ps
CPU time 289.1 seconds
Started Jul 05 05:39:44 PM PDT 24
Finished Jul 05 05:44:34 PM PDT 24
Peak memory 213700 kb
Host smart-b1f39065-1704-4c20-9f7b-42ad16f2da53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402173525 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3402173525
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.546391876
Short name T705
Test name
Test status
Simulation time 22411259971 ps
CPU time 35.91 seconds
Started Jul 05 05:39:42 PM PDT 24
Finished Jul 05 05:40:18 PM PDT 24
Peak memory 199972 kb
Host smart-521723e0-707b-47d6-b278-88aa9a7a08b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546391876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.546391876
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.584269822
Short name T908
Test name
Test status
Simulation time 46812333566 ps
CPU time 523.62 seconds
Started Jul 05 05:39:44 PM PDT 24
Finished Jul 05 05:48:29 PM PDT 24
Peak memory 216716 kb
Host smart-d50f5741-79ba-4ef0-aaf1-ada165e4c560
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584269822 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.584269822
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3976642496
Short name T221
Test name
Test status
Simulation time 76956141880 ps
CPU time 31.26 seconds
Started Jul 05 05:39:43 PM PDT 24
Finished Jul 05 05:40:16 PM PDT 24
Peak memory 199884 kb
Host smart-1a782358-6c2b-46a2-8078-1561d4d2974b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976642496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3976642496
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2851607626
Short name T1061
Test name
Test status
Simulation time 20760953596 ps
CPU time 253.88 seconds
Started Jul 05 05:39:43 PM PDT 24
Finished Jul 05 05:43:57 PM PDT 24
Peak memory 216420 kb
Host smart-96628509-9a11-4917-b50c-14b408a605ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851607626 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2851607626
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3272666981
Short name T751
Test name
Test status
Simulation time 144063651303 ps
CPU time 124.26 seconds
Started Jul 05 05:39:43 PM PDT 24
Finished Jul 05 05:41:48 PM PDT 24
Peak memory 199860 kb
Host smart-668d5dfa-7f02-4da6-8cc1-de5d47bd9983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272666981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3272666981
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2344851996
Short name T31
Test name
Test status
Simulation time 62006611669 ps
CPU time 484.35 seconds
Started Jul 05 05:39:42 PM PDT 24
Finished Jul 05 05:47:47 PM PDT 24
Peak memory 215808 kb
Host smart-8b475b35-0cfb-4e21-b6a5-e7f7dfb16de7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344851996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2344851996
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2694234369
Short name T641
Test name
Test status
Simulation time 21745689 ps
CPU time 0.55 seconds
Started Jul 05 05:37:11 PM PDT 24
Finished Jul 05 05:37:13 PM PDT 24
Peak memory 194272 kb
Host smart-0a4bc14a-0333-4e77-9124-04b8b0f19007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694234369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2694234369
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1872240074
Short name T481
Test name
Test status
Simulation time 232699109536 ps
CPU time 75.43 seconds
Started Jul 05 05:37:05 PM PDT 24
Finished Jul 05 05:38:22 PM PDT 24
Peak memory 199888 kb
Host smart-c8e81fba-1131-4d28-a4e1-92088575e31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872240074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1872240074
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1347484100
Short name T128
Test name
Test status
Simulation time 57396188936 ps
CPU time 122.31 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:39:08 PM PDT 24
Peak memory 199996 kb
Host smart-d699c419-1077-43bd-8e34-8c9f099364d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347484100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1347484100
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.2238318723
Short name T500
Test name
Test status
Simulation time 50727421674 ps
CPU time 16.6 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:37:35 PM PDT 24
Peak memory 199264 kb
Host smart-efbca63c-a6f6-4478-a1cc-b9b96091d7e8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238318723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2238318723
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3252136672
Short name T372
Test name
Test status
Simulation time 132897311139 ps
CPU time 588.53 seconds
Started Jul 05 05:37:24 PM PDT 24
Finished Jul 05 05:47:14 PM PDT 24
Peak memory 199948 kb
Host smart-63a455e8-99b9-40c3-8ce5-c738499afb09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252136672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3252136672
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.78046213
Short name T322
Test name
Test status
Simulation time 3049031805 ps
CPU time 3.57 seconds
Started Jul 05 05:37:14 PM PDT 24
Finished Jul 05 05:37:19 PM PDT 24
Peak memory 198724 kb
Host smart-4cbe2a70-9a8a-4fe1-a4a7-44e9fe0106a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78046213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.78046213
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3575618056
Short name T378
Test name
Test status
Simulation time 131314463996 ps
CPU time 53.75 seconds
Started Jul 05 05:37:14 PM PDT 24
Finished Jul 05 05:38:09 PM PDT 24
Peak memory 199376 kb
Host smart-25f2ccc2-4165-4262-a896-67a2da6906b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575618056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3575618056
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2894238072
Short name T689
Test name
Test status
Simulation time 4208402461 ps
CPU time 55.17 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:38:00 PM PDT 24
Peak memory 199884 kb
Host smart-568bcd4a-2231-46ff-9ddb-50950fec51e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894238072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2894238072
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1245755547
Short name T658
Test name
Test status
Simulation time 2851556589 ps
CPU time 4.26 seconds
Started Jul 05 05:37:20 PM PDT 24
Finished Jul 05 05:37:25 PM PDT 24
Peak memory 198172 kb
Host smart-229c22f8-be52-42a3-b44c-ebc87232fb85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245755547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1245755547
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1186296408
Short name T1119
Test name
Test status
Simulation time 105567695623 ps
CPU time 13.22 seconds
Started Jul 05 05:37:09 PM PDT 24
Finished Jul 05 05:37:23 PM PDT 24
Peak memory 199948 kb
Host smart-78078d9d-985b-4005-8862-9386afb266d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186296408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1186296408
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2320386184
Short name T1107
Test name
Test status
Simulation time 612418976 ps
CPU time 1.53 seconds
Started Jul 05 05:37:03 PM PDT 24
Finished Jul 05 05:37:06 PM PDT 24
Peak memory 195344 kb
Host smart-c06506b1-f773-477c-8726-4f544cf7274d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320386184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2320386184
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3518624074
Short name T733
Test name
Test status
Simulation time 344839846 ps
CPU time 0.99 seconds
Started Jul 05 05:37:02 PM PDT 24
Finished Jul 05 05:37:04 PM PDT 24
Peak memory 198480 kb
Host smart-424e5f5c-a92c-4956-9f84-fe7f8fc15aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518624074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3518624074
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1089319177
Short name T990
Test name
Test status
Simulation time 163903237028 ps
CPU time 513.07 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:45:51 PM PDT 24
Peak memory 199856 kb
Host smart-dc58480b-53d3-4d55-bcf1-aa26ca14ee58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089319177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1089319177
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2500312937
Short name T698
Test name
Test status
Simulation time 123644600001 ps
CPU time 413.12 seconds
Started Jul 05 05:37:20 PM PDT 24
Finished Jul 05 05:44:13 PM PDT 24
Peak memory 225888 kb
Host smart-bf136ff6-5b71-4fe0-a0a5-f91d949e3d4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500312937 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2500312937
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.954926355
Short name T423
Test name
Test status
Simulation time 11952088981 ps
CPU time 33.93 seconds
Started Jul 05 05:37:16 PM PDT 24
Finished Jul 05 05:37:52 PM PDT 24
Peak memory 199044 kb
Host smart-6196aa27-3056-4b87-9614-52a991d0a036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954926355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.954926355
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1353700548
Short name T856
Test name
Test status
Simulation time 25690503630 ps
CPU time 41.48 seconds
Started Jul 05 05:37:20 PM PDT 24
Finished Jul 05 05:38:02 PM PDT 24
Peak memory 199956 kb
Host smart-67233c60-e723-4c03-aeb7-aaef412eb8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353700548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1353700548
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1951913490
Short name T315
Test name
Test status
Simulation time 81949272779 ps
CPU time 42.68 seconds
Started Jul 05 05:39:43 PM PDT 24
Finished Jul 05 05:40:27 PM PDT 24
Peak memory 199908 kb
Host smart-dd81d2ca-7f8b-4630-9a1d-24f2043c2e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951913490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1951913490
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1095226186
Short name T1086
Test name
Test status
Simulation time 98466166246 ps
CPU time 87.09 seconds
Started Jul 05 05:39:44 PM PDT 24
Finished Jul 05 05:41:12 PM PDT 24
Peak memory 199912 kb
Host smart-42699baa-50c3-451a-b9e0-1af6b371569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095226186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1095226186
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.285225702
Short name T815
Test name
Test status
Simulation time 71155321696 ps
CPU time 404.37 seconds
Started Jul 05 05:39:44 PM PDT 24
Finished Jul 05 05:46:29 PM PDT 24
Peak memory 216548 kb
Host smart-f502623e-00b4-4a01-b86f-696307aab8d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285225702 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.285225702
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.267722111
Short name T937
Test name
Test status
Simulation time 65548548638 ps
CPU time 26.34 seconds
Started Jul 05 05:39:48 PM PDT 24
Finished Jul 05 05:40:15 PM PDT 24
Peak memory 199804 kb
Host smart-5ee67d71-d258-4c35-85d3-978c4d9bfd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267722111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.267722111
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3419990720
Short name T1067
Test name
Test status
Simulation time 612837442577 ps
CPU time 1089.71 seconds
Started Jul 05 05:39:55 PM PDT 24
Finished Jul 05 05:58:05 PM PDT 24
Peak memory 225048 kb
Host smart-c166e788-9f7d-420e-b522-2ef3ed76900b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419990720 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3419990720
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.9942980
Short name T192
Test name
Test status
Simulation time 189345548229 ps
CPU time 283.49 seconds
Started Jul 05 05:39:48 PM PDT 24
Finished Jul 05 05:44:32 PM PDT 24
Peak memory 199908 kb
Host smart-c5b4021b-f1a4-4dc9-a7fb-338b5aa9c426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9942980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.9942980
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.525274394
Short name T43
Test name
Test status
Simulation time 34884805926 ps
CPU time 1243.93 seconds
Started Jul 05 05:39:50 PM PDT 24
Finished Jul 05 06:00:35 PM PDT 24
Peak memory 208324 kb
Host smart-cd80d65a-f1e6-4aeb-a841-28c02ed5a222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525274394 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.525274394
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.407315587
Short name T45
Test name
Test status
Simulation time 113269698257 ps
CPU time 281.77 seconds
Started Jul 05 05:39:50 PM PDT 24
Finished Jul 05 05:44:32 PM PDT 24
Peak memory 216644 kb
Host smart-1a77f466-c35b-4616-922b-784714c0db34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407315587 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.407315587
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.24954779
Short name T321
Test name
Test status
Simulation time 95741861147 ps
CPU time 26.59 seconds
Started Jul 05 05:39:52 PM PDT 24
Finished Jul 05 05:40:19 PM PDT 24
Peak memory 199932 kb
Host smart-1f5442c0-28bc-444e-a8c4-d0f5adbf032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24954779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.24954779
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1527354748
Short name T101
Test name
Test status
Simulation time 81003575949 ps
CPU time 234.26 seconds
Started Jul 05 05:39:48 PM PDT 24
Finished Jul 05 05:43:43 PM PDT 24
Peak memory 216704 kb
Host smart-7db5745a-21b4-4e36-ace6-684c7ae50bab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527354748 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1527354748
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2179958445
Short name T607
Test name
Test status
Simulation time 103654452681 ps
CPU time 131.25 seconds
Started Jul 05 05:39:48 PM PDT 24
Finished Jul 05 05:42:00 PM PDT 24
Peak memory 199944 kb
Host smart-fb256336-012a-493b-ae2f-bc3882115b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179958445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2179958445
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1427038512
Short name T580
Test name
Test status
Simulation time 98315958743 ps
CPU time 590.31 seconds
Started Jul 05 05:39:48 PM PDT 24
Finished Jul 05 05:49:39 PM PDT 24
Peak memory 212912 kb
Host smart-87a4ed4c-444e-4f03-b0ca-b8b06c40f647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427038512 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1427038512
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3577179856
Short name T650
Test name
Test status
Simulation time 53557991157 ps
CPU time 83.42 seconds
Started Jul 05 05:40:24 PM PDT 24
Finished Jul 05 05:41:49 PM PDT 24
Peak memory 199904 kb
Host smart-40f2c574-1000-41bd-903a-6be08434bd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577179856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3577179856
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1146322693
Short name T1147
Test name
Test status
Simulation time 104311146127 ps
CPU time 590.49 seconds
Started Jul 05 05:39:49 PM PDT 24
Finished Jul 05 05:49:41 PM PDT 24
Peak memory 225132 kb
Host smart-e0914f4b-4ca1-4237-96f9-9b3bd459ac4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146322693 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1146322693
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2089903587
Short name T1145
Test name
Test status
Simulation time 72721831955 ps
CPU time 32.19 seconds
Started Jul 05 05:39:53 PM PDT 24
Finished Jul 05 05:40:25 PM PDT 24
Peak memory 199996 kb
Host smart-4185c85e-51d2-4978-88c3-4991dd654258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089903587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2089903587
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.893799665
Short name T797
Test name
Test status
Simulation time 90319861941 ps
CPU time 647.72 seconds
Started Jul 05 05:39:48 PM PDT 24
Finished Jul 05 05:50:36 PM PDT 24
Peak memory 216720 kb
Host smart-e3148294-1bd8-4de9-a574-6f212efde750
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893799665 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.893799665
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2070822295
Short name T1111
Test name
Test status
Simulation time 73426031874 ps
CPU time 67.02 seconds
Started Jul 05 05:39:50 PM PDT 24
Finished Jul 05 05:40:58 PM PDT 24
Peak memory 199892 kb
Host smart-ba115593-69bd-477b-be4a-1b8f95ed7b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070822295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2070822295
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.103774026
Short name T523
Test name
Test status
Simulation time 342173004081 ps
CPU time 647.79 seconds
Started Jul 05 05:39:50 PM PDT 24
Finished Jul 05 05:50:39 PM PDT 24
Peak memory 216696 kb
Host smart-77b8644f-2d54-4bb1-805e-c4dc36d3521e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103774026 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.103774026
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1891722903
Short name T530
Test name
Test status
Simulation time 14619976 ps
CPU time 0.56 seconds
Started Jul 05 05:37:11 PM PDT 24
Finished Jul 05 05:37:12 PM PDT 24
Peak memory 195236 kb
Host smart-20573f46-37b4-4c33-80b4-78ae99915d35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891722903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1891722903
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1013053134
Short name T805
Test name
Test status
Simulation time 15277930609 ps
CPU time 7.79 seconds
Started Jul 05 05:37:15 PM PDT 24
Finished Jul 05 05:37:24 PM PDT 24
Peak memory 199936 kb
Host smart-cf5ce2b6-3177-44fd-84f1-6c2674700064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013053134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1013053134
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3279940325
Short name T446
Test name
Test status
Simulation time 12092874813 ps
CPU time 10.18 seconds
Started Jul 05 05:37:12 PM PDT 24
Finished Jul 05 05:37:23 PM PDT 24
Peak memory 199960 kb
Host smart-1cce38fa-5839-4284-8a7f-0d7e1998d414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279940325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3279940325
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2359200286
Short name T811
Test name
Test status
Simulation time 118387507888 ps
CPU time 35.65 seconds
Started Jul 05 05:37:10 PM PDT 24
Finished Jul 05 05:37:46 PM PDT 24
Peak memory 199920 kb
Host smart-51c9aac0-7e54-40c9-b63a-d7c56886b82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359200286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2359200286
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1499275973
Short name T732
Test name
Test status
Simulation time 14131419231 ps
CPU time 23.09 seconds
Started Jul 05 05:37:14 PM PDT 24
Finished Jul 05 05:37:38 PM PDT 24
Peak memory 197228 kb
Host smart-5fe172df-5a9f-4d5a-9019-e9c7d0edd144
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499275973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1499275973
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3524833550
Short name T721
Test name
Test status
Simulation time 81346063494 ps
CPU time 382.45 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:43:51 PM PDT 24
Peak memory 199856 kb
Host smart-9d903438-d84b-4183-8e5e-d8b23b3b2db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524833550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3524833550
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.86939923
Short name T323
Test name
Test status
Simulation time 7896616292 ps
CPU time 13.52 seconds
Started Jul 05 05:37:15 PM PDT 24
Finished Jul 05 05:37:29 PM PDT 24
Peak memory 199968 kb
Host smart-2e3e1c0d-1367-4cab-8cbd-fe37c3cb6acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86939923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.86939923
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4141275560
Short name T923
Test name
Test status
Simulation time 41273459018 ps
CPU time 33.22 seconds
Started Jul 05 05:37:12 PM PDT 24
Finished Jul 05 05:37:46 PM PDT 24
Peak memory 200220 kb
Host smart-650fa4fd-1d1f-4c85-aefb-20741d793391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141275560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4141275560
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.753629177
Short name T371
Test name
Test status
Simulation time 9683433885 ps
CPU time 547.09 seconds
Started Jul 05 05:37:15 PM PDT 24
Finished Jul 05 05:46:23 PM PDT 24
Peak memory 199976 kb
Host smart-805367b8-ec26-4815-b8e4-4d32e72a0e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753629177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.753629177
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1281204685
Short name T970
Test name
Test status
Simulation time 7307683881 ps
CPU time 15.91 seconds
Started Jul 05 05:37:10 PM PDT 24
Finished Jul 05 05:37:27 PM PDT 24
Peak memory 198708 kb
Host smart-8db70599-c733-49e3-b353-3a82f035223f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1281204685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1281204685
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.522376451
Short name T142
Test name
Test status
Simulation time 25335559444 ps
CPU time 36.13 seconds
Started Jul 05 05:37:19 PM PDT 24
Finished Jul 05 05:37:55 PM PDT 24
Peak memory 199904 kb
Host smart-21e6eb48-7649-4381-9ef7-0e73b8678a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522376451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.522376451
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1955645540
Short name T808
Test name
Test status
Simulation time 4319108372 ps
CPU time 1.19 seconds
Started Jul 05 05:37:15 PM PDT 24
Finished Jul 05 05:37:17 PM PDT 24
Peak memory 196080 kb
Host smart-5693e7eb-031a-4e11-833f-4f1674cb80d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955645540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1955645540
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1412525334
Short name T280
Test name
Test status
Simulation time 5701140993 ps
CPU time 4.97 seconds
Started Jul 05 05:37:10 PM PDT 24
Finished Jul 05 05:37:16 PM PDT 24
Peak memory 199876 kb
Host smart-9eb9fac9-9658-49df-9bb3-6dea18d83d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412525334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1412525334
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3378746095
Short name T200
Test name
Test status
Simulation time 202031711057 ps
CPU time 201.22 seconds
Started Jul 05 05:37:11 PM PDT 24
Finished Jul 05 05:40:33 PM PDT 24
Peak memory 199952 kb
Host smart-381e1756-5fc8-4655-b768-ba47ea46fd44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378746095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3378746095
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.306097482
Short name T609
Test name
Test status
Simulation time 94990977848 ps
CPU time 389.93 seconds
Started Jul 05 05:37:12 PM PDT 24
Finished Jul 05 05:43:42 PM PDT 24
Peak memory 216392 kb
Host smart-05d28227-d8c3-43b4-8e43-abed079b8575
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306097482 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.306097482
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.337438019
Short name T1089
Test name
Test status
Simulation time 7040997654 ps
CPU time 15.26 seconds
Started Jul 05 05:37:31 PM PDT 24
Finished Jul 05 05:37:48 PM PDT 24
Peak memory 199832 kb
Host smart-147a5107-d84d-40dd-9820-36c65b68e91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337438019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.337438019
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.6602011
Short name T1025
Test name
Test status
Simulation time 119214207500 ps
CPU time 36.45 seconds
Started Jul 05 05:37:12 PM PDT 24
Finished Jul 05 05:37:49 PM PDT 24
Peak memory 199952 kb
Host smart-9b9ddcd2-c77b-482e-808c-27715eee1b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6602011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.6602011
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2711331869
Short name T211
Test name
Test status
Simulation time 409974433657 ps
CPU time 52 seconds
Started Jul 05 05:39:52 PM PDT 24
Finished Jul 05 05:40:45 PM PDT 24
Peak memory 199856 kb
Host smart-3fde2926-4679-4577-ae9e-e1be97049a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711331869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2711331869
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3544274650
Short name T55
Test name
Test status
Simulation time 50979408518 ps
CPU time 560.78 seconds
Started Jul 05 05:39:52 PM PDT 24
Finished Jul 05 05:49:14 PM PDT 24
Peak memory 216440 kb
Host smart-b0466689-3180-488b-9449-5cc51c1091f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544274650 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3544274650
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.4174997693
Short name T745
Test name
Test status
Simulation time 26453984856 ps
CPU time 42.48 seconds
Started Jul 05 05:39:49 PM PDT 24
Finished Jul 05 05:40:33 PM PDT 24
Peak memory 200152 kb
Host smart-71612b2d-6314-4afd-9c87-820616aad34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174997693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.4174997693
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2906336544
Short name T890
Test name
Test status
Simulation time 22252492442 ps
CPU time 261.27 seconds
Started Jul 05 05:39:54 PM PDT 24
Finished Jul 05 05:44:15 PM PDT 24
Peak memory 216452 kb
Host smart-988b60ab-a793-4f04-9b3a-6a62883480b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906336544 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2906336544
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3486013973
Short name T160
Test name
Test status
Simulation time 6576403189 ps
CPU time 10.2 seconds
Started Jul 05 05:39:49 PM PDT 24
Finished Jul 05 05:39:59 PM PDT 24
Peak memory 199964 kb
Host smart-f1b04061-edb2-4a8b-a44f-483b3089fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486013973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3486013973
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.172037387
Short name T468
Test name
Test status
Simulation time 19347240271 ps
CPU time 324.87 seconds
Started Jul 05 05:39:46 PM PDT 24
Finished Jul 05 05:45:11 PM PDT 24
Peak memory 215560 kb
Host smart-545f11e7-2966-427f-ba4b-7d587e51f026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172037387 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.172037387
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.154543153
Short name T504
Test name
Test status
Simulation time 20274796393 ps
CPU time 35.35 seconds
Started Jul 05 05:39:50 PM PDT 24
Finished Jul 05 05:40:26 PM PDT 24
Peak memory 199984 kb
Host smart-e9c14a2e-d430-4269-9867-c516940cc20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154543153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.154543153
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2694111608
Short name T903
Test name
Test status
Simulation time 163459600277 ps
CPU time 73.74 seconds
Started Jul 05 05:39:52 PM PDT 24
Finished Jul 05 05:41:07 PM PDT 24
Peak memory 216284 kb
Host smart-330aecf1-7dc6-422c-8ee6-d5c95377172e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694111608 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2694111608
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1026840579
Short name T1045
Test name
Test status
Simulation time 29997771360 ps
CPU time 49.29 seconds
Started Jul 05 05:39:50 PM PDT 24
Finished Jul 05 05:40:40 PM PDT 24
Peak memory 199944 kb
Host smart-43140604-4f49-4a5c-8fb7-5cce524308e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026840579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1026840579
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3121931438
Short name T140
Test name
Test status
Simulation time 37532720307 ps
CPU time 15.88 seconds
Started Jul 05 05:39:51 PM PDT 24
Finished Jul 05 05:40:07 PM PDT 24
Peak memory 199696 kb
Host smart-3ebf9fe7-ef0d-4e27-8b3b-c3a4eed8ce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121931438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3121931438
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1643335447
Short name T1022
Test name
Test status
Simulation time 34660006163 ps
CPU time 571.68 seconds
Started Jul 05 05:39:48 PM PDT 24
Finished Jul 05 05:49:20 PM PDT 24
Peak memory 216644 kb
Host smart-74dd7520-84d2-4a55-a7dd-95993f188009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643335447 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1643335447
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3728381914
Short name T1076
Test name
Test status
Simulation time 57290468235 ps
CPU time 14.6 seconds
Started Jul 05 05:39:50 PM PDT 24
Finished Jul 05 05:40:05 PM PDT 24
Peak memory 199968 kb
Host smart-5d5af68f-f2ce-4f8a-a780-74c2fc206a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728381914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3728381914
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1069366789
Short name T39
Test name
Test status
Simulation time 66196686958 ps
CPU time 551.2 seconds
Started Jul 05 05:39:50 PM PDT 24
Finished Jul 05 05:49:02 PM PDT 24
Peak memory 216676 kb
Host smart-8c048bc5-7e8a-49ee-a504-62d6672f283f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069366789 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1069366789
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1221207729
Short name T448
Test name
Test status
Simulation time 87146352394 ps
CPU time 125.72 seconds
Started Jul 05 05:39:51 PM PDT 24
Finished Jul 05 05:41:57 PM PDT 24
Peak memory 199940 kb
Host smart-d2ac6b92-e3be-4d7c-bbf6-0c78ca8e842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221207729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1221207729
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1123376790
Short name T902
Test name
Test status
Simulation time 53513157642 ps
CPU time 743.23 seconds
Started Jul 05 05:39:50 PM PDT 24
Finished Jul 05 05:52:14 PM PDT 24
Peak memory 216476 kb
Host smart-08b6178a-1202-4584-8f5d-19ef33a1da6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123376790 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1123376790
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.73155130
Short name T964
Test name
Test status
Simulation time 125405042778 ps
CPU time 45.49 seconds
Started Jul 05 05:39:57 PM PDT 24
Finished Jul 05 05:40:44 PM PDT 24
Peak memory 199992 kb
Host smart-c5780114-cdfb-47a5-9c07-b9db4647857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73155130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.73155130
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2667928155
Short name T42
Test name
Test status
Simulation time 120253770605 ps
CPU time 540.75 seconds
Started Jul 05 05:39:57 PM PDT 24
Finished Jul 05 05:48:59 PM PDT 24
Peak memory 224876 kb
Host smart-d2b12a9a-4b8d-43da-bacc-84101771393f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667928155 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2667928155
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2882022182
Short name T470
Test name
Test status
Simulation time 11781706 ps
CPU time 0.58 seconds
Started Jul 05 05:37:15 PM PDT 24
Finished Jul 05 05:37:16 PM PDT 24
Peak memory 194776 kb
Host smart-354d83c5-30af-4f51-a406-06ce12b05d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882022182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2882022182
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2352842962
Short name T652
Test name
Test status
Simulation time 32834985100 ps
CPU time 49.03 seconds
Started Jul 05 05:37:27 PM PDT 24
Finished Jul 05 05:38:18 PM PDT 24
Peak memory 199824 kb
Host smart-cc631e90-0ed2-4309-b198-d0998375c5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352842962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2352842962
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.106723901
Short name T588
Test name
Test status
Simulation time 94686143560 ps
CPU time 20.21 seconds
Started Jul 05 05:37:11 PM PDT 24
Finished Jul 05 05:37:32 PM PDT 24
Peak memory 199972 kb
Host smart-8aa1ce5d-5fde-4ca6-ac89-bbd1957d01d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106723901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.106723901
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.857953115
Short name T133
Test name
Test status
Simulation time 43981605490 ps
CPU time 71.86 seconds
Started Jul 05 05:37:09 PM PDT 24
Finished Jul 05 05:38:21 PM PDT 24
Peak memory 199916 kb
Host smart-48326eab-a78e-4863-9d28-80c92e7432aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857953115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.857953115
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3321858262
Short name T894
Test name
Test status
Simulation time 7749127038 ps
CPU time 13.54 seconds
Started Jul 05 05:37:12 PM PDT 24
Finished Jul 05 05:37:26 PM PDT 24
Peak memory 196080 kb
Host smart-f8e5de95-318d-4f22-aaed-66a246a03d0a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321858262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3321858262
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3800137794
Short name T507
Test name
Test status
Simulation time 78449565574 ps
CPU time 449.35 seconds
Started Jul 05 05:37:11 PM PDT 24
Finished Jul 05 05:44:41 PM PDT 24
Peak memory 199892 kb
Host smart-bc1726fe-b47b-48f9-8615-442db55292a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800137794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3800137794
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.657386347
Short name T1018
Test name
Test status
Simulation time 12574562182 ps
CPU time 13.04 seconds
Started Jul 05 05:37:11 PM PDT 24
Finished Jul 05 05:37:25 PM PDT 24
Peak memory 199908 kb
Host smart-5bf6d5e3-a283-4c64-89e6-a469b52c6784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657386347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.657386347
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.194437263
Short name T842
Test name
Test status
Simulation time 85411758598 ps
CPU time 139.46 seconds
Started Jul 05 05:37:14 PM PDT 24
Finished Jul 05 05:39:34 PM PDT 24
Peak memory 199480 kb
Host smart-a5341b3a-0787-4ccb-a2e4-f2cbc85a0cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194437263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.194437263
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.4048828730
Short name T769
Test name
Test status
Simulation time 4237457212 ps
CPU time 194.53 seconds
Started Jul 05 05:37:12 PM PDT 24
Finished Jul 05 05:40:28 PM PDT 24
Peak memory 200004 kb
Host smart-50c7cbbb-cca8-4ec9-a591-3c5af09169f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048828730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.4048828730
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3857554285
Short name T771
Test name
Test status
Simulation time 3160823430 ps
CPU time 21.37 seconds
Started Jul 05 05:37:08 PM PDT 24
Finished Jul 05 05:37:30 PM PDT 24
Peak memory 198136 kb
Host smart-f0a148c1-2ace-49e4-acf8-1d412dbd6c75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857554285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3857554285
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3590548327
Short name T942
Test name
Test status
Simulation time 34889971711 ps
CPU time 29.67 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:37:57 PM PDT 24
Peak memory 199960 kb
Host smart-9abe0780-6041-4c27-b468-151063d28a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590548327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3590548327
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3930920220
Short name T461
Test name
Test status
Simulation time 45314895095 ps
CPU time 14.98 seconds
Started Jul 05 05:37:30 PM PDT 24
Finished Jul 05 05:37:46 PM PDT 24
Peak memory 196096 kb
Host smart-a1880fab-5d8e-495d-b59d-150496c12f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930920220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3930920220
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1875402317
Short name T64
Test name
Test status
Simulation time 689510224 ps
CPU time 1.71 seconds
Started Jul 05 05:37:12 PM PDT 24
Finished Jul 05 05:37:15 PM PDT 24
Peak memory 199896 kb
Host smart-e0a39e94-bbb9-4842-bd30-748a4a6bcc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875402317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1875402317
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.4194767340
Short name T227
Test name
Test status
Simulation time 180245257067 ps
CPU time 991.1 seconds
Started Jul 05 05:37:12 PM PDT 24
Finished Jul 05 05:53:44 PM PDT 24
Peak memory 199904 kb
Host smart-df23b829-040e-415d-9f51-47677b7bf444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194767340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4194767340
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2444287153
Short name T635
Test name
Test status
Simulation time 75776656636 ps
CPU time 821.79 seconds
Started Jul 05 05:37:25 PM PDT 24
Finished Jul 05 05:51:09 PM PDT 24
Peak memory 224948 kb
Host smart-defcd9e2-c21e-4d46-8e57-6bc062200036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444287153 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2444287153
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2277387243
Short name T1062
Test name
Test status
Simulation time 903449163 ps
CPU time 4.47 seconds
Started Jul 05 05:37:26 PM PDT 24
Finished Jul 05 05:37:32 PM PDT 24
Peak memory 199824 kb
Host smart-1934b2f4-89ed-4373-aeb9-13c1593c4266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277387243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2277387243
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3046221163
Short name T756
Test name
Test status
Simulation time 65510487819 ps
CPU time 46.52 seconds
Started Jul 05 05:37:13 PM PDT 24
Finished Jul 05 05:38:01 PM PDT 24
Peak memory 199952 kb
Host smart-f72c8752-916d-4e7b-9bd8-df6ff7889b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046221163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3046221163
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.214263640
Short name T1039
Test name
Test status
Simulation time 36341505779 ps
CPU time 54.55 seconds
Started Jul 05 05:39:56 PM PDT 24
Finished Jul 05 05:40:51 PM PDT 24
Peak memory 199904 kb
Host smart-53afa0da-a071-4b1a-9f18-5bd39b3b05a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214263640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.214263640
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.237514334
Short name T104
Test name
Test status
Simulation time 19026701845 ps
CPU time 312.72 seconds
Started Jul 05 05:39:56 PM PDT 24
Finished Jul 05 05:45:09 PM PDT 24
Peak memory 209832 kb
Host smart-246bfa72-6cf4-48e5-8a6b-165deabd7ef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237514334 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.237514334
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3350656258
Short name T185
Test name
Test status
Simulation time 65889486673 ps
CPU time 50.61 seconds
Started Jul 05 05:40:06 PM PDT 24
Finished Jul 05 05:40:57 PM PDT 24
Peak memory 199748 kb
Host smart-307ffb4c-18e7-429f-8bc9-35bf9bf1ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350656258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3350656258
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3621536647
Short name T823
Test name
Test status
Simulation time 34090454351 ps
CPU time 400.68 seconds
Started Jul 05 05:39:56 PM PDT 24
Finished Jul 05 05:46:38 PM PDT 24
Peak memory 215268 kb
Host smart-19c4ecbb-15d3-44c8-b948-7b5bfb7ba7df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621536647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3621536647
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2142076847
Short name T490
Test name
Test status
Simulation time 158410815674 ps
CPU time 53.91 seconds
Started Jul 05 05:39:54 PM PDT 24
Finished Jul 05 05:40:49 PM PDT 24
Peak memory 199868 kb
Host smart-8264f584-a64f-4977-b943-86a012076985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142076847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2142076847
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3714670372
Short name T184
Test name
Test status
Simulation time 33342800702 ps
CPU time 11.78 seconds
Started Jul 05 05:39:57 PM PDT 24
Finished Jul 05 05:40:10 PM PDT 24
Peak memory 199988 kb
Host smart-fb9b0b7b-a8ae-4295-aa26-c241b4d894e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714670372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3714670372
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1689508915
Short name T1040
Test name
Test status
Simulation time 142547814937 ps
CPU time 435.39 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:47:22 PM PDT 24
Peak memory 209512 kb
Host smart-1fff58cc-1886-45e0-8590-9782c7dcf713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689508915 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1689508915
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.4052794951
Short name T30
Test name
Test status
Simulation time 31563872068 ps
CPU time 366.21 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:46:13 PM PDT 24
Peak memory 216732 kb
Host smart-cd9ffe26-5974-474f-b289-d81735e8e721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052794951 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.4052794951
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3962026639
Short name T1047
Test name
Test status
Simulation time 104694337190 ps
CPU time 181.43 seconds
Started Jul 05 05:40:06 PM PDT 24
Finished Jul 05 05:43:08 PM PDT 24
Peak memory 199696 kb
Host smart-05f2c298-827a-4f33-8ca2-1bead899901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962026639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3962026639
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3993332422
Short name T422
Test name
Test status
Simulation time 322808996574 ps
CPU time 67.79 seconds
Started Jul 05 05:39:57 PM PDT 24
Finished Jul 05 05:41:06 PM PDT 24
Peak memory 199968 kb
Host smart-cc023112-a445-4640-8b4d-8ec9eb984613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993332422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3993332422
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3343386222
Short name T349
Test name
Test status
Simulation time 47160113130 ps
CPU time 494.44 seconds
Started Jul 05 05:40:06 PM PDT 24
Finished Jul 05 05:48:22 PM PDT 24
Peak memory 226196 kb
Host smart-c219c3c1-b58a-45ba-a8eb-d317dedcb7b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343386222 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3343386222
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3651066894
Short name T205
Test name
Test status
Simulation time 333534388242 ps
CPU time 47.51 seconds
Started Jul 05 05:39:56 PM PDT 24
Finished Jul 05 05:40:44 PM PDT 24
Peak memory 199696 kb
Host smart-fd2f90a0-a69e-4402-87d7-7a5fa516f5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651066894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3651066894
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3102680318
Short name T66
Test name
Test status
Simulation time 112706345532 ps
CPU time 1228.96 seconds
Started Jul 05 05:39:56 PM PDT 24
Finished Jul 05 06:00:26 PM PDT 24
Peak memory 233028 kb
Host smart-485e3b64-fb33-45b3-85f6-d92bd2fd4b44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102680318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3102680318
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.4159756404
Short name T657
Test name
Test status
Simulation time 89389810648 ps
CPU time 152.07 seconds
Started Jul 05 05:39:54 PM PDT 24
Finished Jul 05 05:42:26 PM PDT 24
Peak memory 199920 kb
Host smart-3f50f6b4-1ff0-4860-a932-f5caa52f8974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159756404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.4159756404
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2151080772
Short name T310
Test name
Test status
Simulation time 76831875464 ps
CPU time 749.65 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:52:36 PM PDT 24
Peak memory 229412 kb
Host smart-23330097-09e0-4a14-8372-6b309134011e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151080772 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2151080772
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3789817771
Short name T779
Test name
Test status
Simulation time 51777936021 ps
CPU time 79.79 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:41:26 PM PDT 24
Peak memory 199960 kb
Host smart-2ec31dc7-fe0f-434d-8bd5-297be21e1b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789817771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3789817771
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2464745268
Short name T299
Test name
Test status
Simulation time 23588107621 ps
CPU time 261.13 seconds
Started Jul 05 05:40:06 PM PDT 24
Finished Jul 05 05:44:28 PM PDT 24
Peak memory 208316 kb
Host smart-7c050451-0627-488e-8998-66e7964496a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464745268 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2464745268
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1787079814
Short name T1118
Test name
Test status
Simulation time 21402756 ps
CPU time 0.58 seconds
Started Jul 05 05:37:36 PM PDT 24
Finished Jul 05 05:37:38 PM PDT 24
Peak memory 195332 kb
Host smart-1662e4ed-9d5e-449f-8ff3-0b33ddf072e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787079814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1787079814
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1015466931
Short name T672
Test name
Test status
Simulation time 40362132149 ps
CPU time 18.59 seconds
Started Jul 05 05:37:13 PM PDT 24
Finished Jul 05 05:37:32 PM PDT 24
Peak memory 199992 kb
Host smart-fd1de143-fbf8-4018-852e-b89174cedcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015466931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1015466931
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.570791813
Short name T700
Test name
Test status
Simulation time 77637235322 ps
CPU time 114.76 seconds
Started Jul 05 05:37:15 PM PDT 24
Finished Jul 05 05:39:12 PM PDT 24
Peak memory 199980 kb
Host smart-afae3a9c-4d59-42b6-bc44-1621077e191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570791813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.570791813
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2044718882
Short name T119
Test name
Test status
Simulation time 24748456910 ps
CPU time 22.67 seconds
Started Jul 05 05:37:15 PM PDT 24
Finished Jul 05 05:37:39 PM PDT 24
Peak memory 200000 kb
Host smart-5d4afa19-2521-4e39-9823-e4c509d6cbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044718882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2044718882
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2762778368
Short name T1058
Test name
Test status
Simulation time 59549198512 ps
CPU time 26.46 seconds
Started Jul 05 05:37:15 PM PDT 24
Finished Jul 05 05:37:42 PM PDT 24
Peak memory 199944 kb
Host smart-3941fe41-9e31-42cc-8f09-4dc42f829815
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762778368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2762778368
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3701274075
Short name T984
Test name
Test status
Simulation time 75922314129 ps
CPU time 260.55 seconds
Started Jul 05 05:37:29 PM PDT 24
Finished Jul 05 05:41:51 PM PDT 24
Peak memory 199948 kb
Host smart-334ef6da-4a47-4edf-9de3-7c96ca699b24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701274075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3701274075
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3507526478
Short name T20
Test name
Test status
Simulation time 877260642 ps
CPU time 1.86 seconds
Started Jul 05 05:37:22 PM PDT 24
Finished Jul 05 05:37:24 PM PDT 24
Peak memory 195364 kb
Host smart-40f683fd-999b-4384-af6c-7ce8f52c357f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507526478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3507526478
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.693611887
Short name T722
Test name
Test status
Simulation time 53634065559 ps
CPU time 78.67 seconds
Started Jul 05 05:37:12 PM PDT 24
Finished Jul 05 05:38:31 PM PDT 24
Peak memory 200168 kb
Host smart-03dda566-8e15-42a8-a5ed-4559ef41f1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693611887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.693611887
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1098858455
Short name T474
Test name
Test status
Simulation time 8339264552 ps
CPU time 72.08 seconds
Started Jul 05 05:37:29 PM PDT 24
Finished Jul 05 05:38:42 PM PDT 24
Peak memory 199900 kb
Host smart-53ca2294-663c-4cf8-aa9f-fdc714a49965
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098858455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1098858455
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.4135119421
Short name T853
Test name
Test status
Simulation time 3899018195 ps
CPU time 32.96 seconds
Started Jul 05 05:37:12 PM PDT 24
Finished Jul 05 05:37:45 PM PDT 24
Peak memory 198068 kb
Host smart-9a229cbb-4e62-4948-91c6-3c2109e43ffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135119421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4135119421
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2884459704
Short name T845
Test name
Test status
Simulation time 97505113373 ps
CPU time 65.68 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 05:38:40 PM PDT 24
Peak memory 199944 kb
Host smart-f099b0d0-8165-4f30-925b-642cde243ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884459704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2884459704
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1281277791
Short name T496
Test name
Test status
Simulation time 5004673718 ps
CPU time 2.23 seconds
Started Jul 05 05:37:30 PM PDT 24
Finished Jul 05 05:37:34 PM PDT 24
Peak memory 196436 kb
Host smart-26b319d6-aa0a-40d7-bfe0-7db27dce1e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281277791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1281277791
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1932046888
Short name T824
Test name
Test status
Simulation time 6190456916 ps
CPU time 14.77 seconds
Started Jul 05 05:37:11 PM PDT 24
Finished Jul 05 05:37:26 PM PDT 24
Peak memory 199152 kb
Host smart-462e9f9d-62d3-493b-9e86-9158f2c1bf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932046888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1932046888
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3772740217
Short name T765
Test name
Test status
Simulation time 162564458032 ps
CPU time 229.56 seconds
Started Jul 05 05:37:21 PM PDT 24
Finished Jul 05 05:41:11 PM PDT 24
Peak memory 199900 kb
Host smart-2eb6698d-050c-4dd8-afe2-0a82c364196c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772740217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3772740217
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1995231291
Short name T65
Test name
Test status
Simulation time 64632010634 ps
CPU time 872.86 seconds
Started Jul 05 05:37:33 PM PDT 24
Finished Jul 05 05:52:07 PM PDT 24
Peak memory 216708 kb
Host smart-310a2065-92c6-4289-ac7f-d15df46d0a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995231291 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1995231291
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.396922395
Short name T440
Test name
Test status
Simulation time 2245606200 ps
CPU time 1.87 seconds
Started Jul 05 05:37:19 PM PDT 24
Finished Jul 05 05:37:22 PM PDT 24
Peak memory 198532 kb
Host smart-96f0499b-00a9-4246-9b4f-5b5f823c3aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396922395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.396922395
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1128271457
Short name T598
Test name
Test status
Simulation time 46261520696 ps
CPU time 80.63 seconds
Started Jul 05 05:37:15 PM PDT 24
Finished Jul 05 05:38:36 PM PDT 24
Peak memory 199996 kb
Host smart-aec5b43c-8b66-422c-ade7-9abf61f6359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128271457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1128271457
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2578093424
Short name T153
Test name
Test status
Simulation time 235910647392 ps
CPU time 88.59 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:41:35 PM PDT 24
Peak memory 199952 kb
Host smart-b5f7f214-5e90-45f3-b563-87cb29ab3179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578093424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2578093424
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.4284500886
Short name T127
Test name
Test status
Simulation time 105108217230 ps
CPU time 209.85 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:43:36 PM PDT 24
Peak memory 216732 kb
Host smart-fbe3c75c-c288-494e-9e86-8ccf937504dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284500886 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.4284500886
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.648101263
Short name T959
Test name
Test status
Simulation time 28991001485 ps
CPU time 46.65 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:40:52 PM PDT 24
Peak memory 199948 kb
Host smart-2bd7ae82-2c3b-468a-b853-bb379050a14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648101263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.648101263
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2104045486
Short name T1080
Test name
Test status
Simulation time 79199563492 ps
CPU time 529.29 seconds
Started Jul 05 05:40:09 PM PDT 24
Finished Jul 05 05:48:59 PM PDT 24
Peak memory 216408 kb
Host smart-6a1a06b5-6b89-4242-a64f-72f38a86cb88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104045486 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2104045486
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4015347366
Short name T489
Test name
Test status
Simulation time 12836432310 ps
CPU time 17.79 seconds
Started Jul 05 05:40:04 PM PDT 24
Finished Jul 05 05:40:22 PM PDT 24
Peak memory 200024 kb
Host smart-1fc0cd34-7444-4140-9efb-963f07f4a32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015347366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4015347366
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2444354444
Short name T123
Test name
Test status
Simulation time 62982104978 ps
CPU time 354.59 seconds
Started Jul 05 05:40:06 PM PDT 24
Finished Jul 05 05:46:02 PM PDT 24
Peak memory 211080 kb
Host smart-9709ffcf-4150-40f0-b296-cd204f6fbdc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444354444 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2444354444
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3023038849
Short name T255
Test name
Test status
Simulation time 85205053364 ps
CPU time 196.55 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:43:23 PM PDT 24
Peak memory 199824 kb
Host smart-b4dab2cc-8365-41c7-b1b6-d74ed7a26e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023038849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3023038849
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1134725640
Short name T147
Test name
Test status
Simulation time 37496462203 ps
CPU time 19.4 seconds
Started Jul 05 05:40:07 PM PDT 24
Finished Jul 05 05:40:27 PM PDT 24
Peak memory 199932 kb
Host smart-c90c1507-ce21-4df8-bc8a-beb2572b6688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134725640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1134725640
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.829094574
Short name T260
Test name
Test status
Simulation time 54709577336 ps
CPU time 466.03 seconds
Started Jul 05 05:40:06 PM PDT 24
Finished Jul 05 05:47:53 PM PDT 24
Peak memory 216576 kb
Host smart-3c4f7def-2fa4-4de9-975e-90e244218975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829094574 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.829094574
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1502563703
Short name T540
Test name
Test status
Simulation time 130487808528 ps
CPU time 51.28 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:40:58 PM PDT 24
Peak memory 199916 kb
Host smart-b4d2dbb0-2952-4f57-9464-2f432faf8570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502563703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1502563703
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2674118783
Short name T1176
Test name
Test status
Simulation time 34952644169 ps
CPU time 370.5 seconds
Started Jul 05 05:40:04 PM PDT 24
Finished Jul 05 05:46:15 PM PDT 24
Peak memory 226988 kb
Host smart-49be7630-1722-471e-a69d-7abc64c4c1cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674118783 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2674118783
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3395298082
Short name T3
Test name
Test status
Simulation time 230094104187 ps
CPU time 35.97 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:40:42 PM PDT 24
Peak memory 199868 kb
Host smart-9b3da246-61be-47bb-8e59-478cb9761b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395298082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3395298082
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3996931336
Short name T881
Test name
Test status
Simulation time 127581569360 ps
CPU time 380.2 seconds
Started Jul 05 05:40:07 PM PDT 24
Finished Jul 05 05:46:28 PM PDT 24
Peak memory 216036 kb
Host smart-d85e494f-ba82-4bd9-89c3-fd07d6dd2c2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996931336 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3996931336
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.799463589
Short name T130
Test name
Test status
Simulation time 25564144706 ps
CPU time 45.67 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:40:52 PM PDT 24
Peak memory 199904 kb
Host smart-91e1f942-9955-47fe-a7f5-e6996ddebb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799463589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.799463589
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2207288199
Short name T54
Test name
Test status
Simulation time 271525982177 ps
CPU time 792.72 seconds
Started Jul 05 05:40:01 PM PDT 24
Finished Jul 05 05:53:15 PM PDT 24
Peak memory 230092 kb
Host smart-f062291f-4c12-4004-b278-a72cc3ffc200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207288199 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2207288199
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.164311753
Short name T882
Test name
Test status
Simulation time 189082178238 ps
CPU time 148 seconds
Started Jul 05 05:40:04 PM PDT 24
Finished Jul 05 05:42:33 PM PDT 24
Peak memory 199920 kb
Host smart-36fdc208-bfa2-47cc-93bc-37601cca7ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164311753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.164311753
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.4097475167
Short name T265
Test name
Test status
Simulation time 46663966937 ps
CPU time 293.96 seconds
Started Jul 05 05:40:05 PM PDT 24
Finished Jul 05 05:45:00 PM PDT 24
Peak memory 216716 kb
Host smart-067f04a7-9bd4-477c-833e-eaa31a07e1e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097475167 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.4097475167
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.692542882
Short name T1015
Test name
Test status
Simulation time 248030252461 ps
CPU time 456.68 seconds
Started Jul 05 05:40:07 PM PDT 24
Finished Jul 05 05:47:44 PM PDT 24
Peak memory 224888 kb
Host smart-db6d8268-6a4b-4371-ad75-be0d6df0ae13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692542882 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.692542882
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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