Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	108732	1			T1	37		T2	16		T3	80
all_values[1]	108732	1			T1	37		T2	16		T3	80
all_values[2]	108732	1			T1	37		T2	16		T3	80
all_values[3]	108732	1			T1	37		T2	16		T3	80
all_values[4]	108732	1			T1	37		T2	16		T3	80
all_values[5]	108732	1			T1	37		T2	16		T3	80
all_values[6]	108732	1			T1	37		T2	16		T3	80
all_values[7]	108732	1			T1	37		T2	16		T3	80
all_values[8]	108732	1			T1	37		T2	16		T3	80

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

494777

1

T1

151

T2

69

T3

382

auto[1]

483811

1

T1

182

T2

75

T3

338

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

885771

1

T1

316

T2

103

T3

655

auto[1]

92817

1

T1

17

T2

41

T3

65

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29834	1			T1	6		T2	1		T3	39
all_values[0]	auto[0]	auto[1]	23286	1			T1	3		T3	29		T4	4
all_values[0]	auto[1]	auto[0]	33055	1			T1	25		T2	2		T3	11
all_values[0]	auto[1]	auto[1]	22557	1			T1	3		T2	13		T3	1
all_values[1]	auto[0]	auto[0]	51734	1			T1	28		T3	11		T4	8
all_values[1]	auto[0]	auto[1]	1848	1			T8	1		T9	6		T30	2
all_values[1]	auto[1]	auto[0]	53560	1			T1	9		T2	5		T3	69
all_values[1]	auto[1]	auto[1]	1590	1			T2	11		T5	1		T6	26
all_values[2]	auto[0]	auto[0]	54178	1			T1	5		T2	3		T3	50
all_values[2]	auto[0]	auto[1]	2851	1			T2	1		T3	3		T5	6
all_values[2]	auto[1]	auto[0]	49189	1			T1	27		T2	10		T3	25
all_values[2]	auto[1]	auto[1]	2514	1			T1	5		T2	2		T3	2
all_values[3]	auto[0]	auto[0]	55754	1			T1	26		T2	14		T3	13
all_values[3]	auto[0]	auto[1]	299	1			T2	1		T5	1		T6	3
all_values[3]	auto[1]	auto[0]	52381	1			T1	11		T2	1		T3	67
all_values[3]	auto[1]	auto[1]	298	1			T5	1		T8	1		T9	2
all_values[4]	auto[0]	auto[0]	55055	1			T1	12		T2	15		T4	16
all_values[4]	auto[0]	auto[1]	422	1			T6	10		T8	1		T11	14
all_values[4]	auto[1]	auto[0]	52864	1			T1	25		T2	1		T3	80
all_values[4]	auto[1]	auto[1]	391	1			T5	2		T6	6		T8	2
all_values[5]	auto[0]	auto[0]	54750	1			T1	10		T3	80		T4	8
all_values[5]	auto[0]	auto[1]	157	1			T8	3		T9	2		T10	4
all_values[5]	auto[1]	auto[0]	53616	1			T1	27		T2	16		T4	8
all_values[5]	auto[1]	auto[1]	209	1			T5	3		T23	3		T42	1
all_values[6]	auto[0]	auto[0]	54730	1			T1	29		T2	15		T3	39
all_values[6]	auto[0]	auto[1]	176	1			T5	1		T8	1		T9	2
all_values[6]	auto[1]	auto[0]	53619	1			T1	8		T2	1		T3	41
all_values[6]	auto[1]	auto[1]	207	1			T8	4		T27	2		T42	3
all_values[7]	auto[0]	auto[0]	53539	1			T1	32		T2	4		T3	51
all_values[7]	auto[0]	auto[1]	329	1			T5	2		T6	1		T8	1
all_values[7]	auto[1]	auto[0]	54499	1			T1	5		T2	12		T3	29
all_values[7]	auto[1]	auto[1]	365	1			T5	1		T8	5		T23	2
all_values[8]	auto[0]	auto[0]	36614	1			T2	2		T3	39		T4	3
all_values[8]	auto[0]	auto[1]	19221	1			T2	13		T3	28		T4	1
all_values[8]	auto[1]	auto[0]	36800	1			T1	31		T2	1		T3	11
all_values[8]	auto[1]	auto[1]	16097	1			T1	6		T3	2		T4	1