Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2375	1			T1	5		T2	1		T3	3
auto[BaudRate115200]	1991	1			T2	1		T3	2		T4	1
auto[BaudRate230400]	2062	1			T1	1		T2	2		T3	2
auto[BaudRate128Kbps]	2106	1			T1	2		T2	1		T4	3
auto[BaudRate256Kbps]	2311	1			T1	3		T2	2		T5	15
auto[BaudRate1Mbps]	1933	1			T1	7		T2	2		T3	2
auto[BaudRate1p5Mbps]	1337	1			T1	2		T2	1		T4	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1738	1			T1	20		T14	39		T15	119
freqs[25]	1565	1			T2	10		T29	10		T37	2
freqs[48]	499	1			T26	70		T268	8		T136	6
freqs[50]	705	1			T9	52		T28	2		T34	2
freqs[100]	1211	1			T3	9		T125	6		T40	10

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	286	1			T1	5		T14	6		T15	8
auto[BaudRate9600]	freqs[25]	233	1			T2	1		T339	3		T188	3
auto[BaudRate9600]	freqs[48]	73	1			T26	7		T268	1		T289	1
auto[BaudRate9600]	freqs[50]	91	1			T9	4		T304	2		T139	21
auto[BaudRate9600]	freqs[100]	221	1			T3	3		T125	2		T40	3
auto[BaudRate115200]	freqs[24]	204	1			T14	3		T15	10		T45	1
auto[BaudRate115200]	freqs[25]	235	1			T2	1		T12	2		T339	6
auto[BaudRate115200]	freqs[48]	68	1			T26	15		T268	2		T136	1
auto[BaudRate115200]	freqs[50]	87	1			T9	4		T304	1		T319	1
auto[BaudRate115200]	freqs[100]	155	1			T3	2		T125	1		T40	1
auto[BaudRate230400]	freqs[24]	258	1			T1	1		T14	6		T15	25
auto[BaudRate230400]	freqs[25]	220	1			T2	2		T12	1		T339	3
auto[BaudRate230400]	freqs[48]	65	1			T26	10		T268	1		T136	1
auto[BaudRate230400]	freqs[50]	120	1			T9	7		T304	2		T319	2
auto[BaudRate230400]	freqs[100]	165	1			T3	2		T125	1		T40	2
auto[BaudRate128Kbps]	freqs[24]	252	1			T1	2		T14	9		T15	20
auto[BaudRate128Kbps]	freqs[25]	213	1			T2	1		T308	1		T339	6
auto[BaudRate128Kbps]	freqs[48]	72	1			T26	4		T268	1		T136	1
auto[BaudRate128Kbps]	freqs[50]	104	1			T9	11		T34	1		T304	1
auto[BaudRate128Kbps]	freqs[100]	171	1			T40	1		T290	1		T27	3
auto[BaudRate256Kbps]	freqs[24]	298	1			T1	3		T14	9		T15	29
auto[BaudRate256Kbps]	freqs[25]	239	1			T2	2		T29	5		T37	1
auto[BaudRate256Kbps]	freqs[48]	84	1			T26	12		T268	1		T84	1
auto[BaudRate256Kbps]	freqs[50]	94	1			T9	8		T34	1		T304	1
auto[BaudRate256Kbps]	freqs[100]	164	1			T125	1		T40	1		T290	1
auto[BaudRate1Mbps]	freqs[24]	308	1			T1	7		T14	6		T15	18
auto[BaudRate1Mbps]	freqs[25]	275	1			T2	2		T29	4		T308	1
auto[BaudRate1Mbps]	freqs[48]	71	1			T26	13		T268	1		T136	2
auto[BaudRate1Mbps]	freqs[50]	105	1			T9	9		T319	1		T340	1
auto[BaudRate1Mbps]	freqs[100]	173	1			T3	2		T40	1		T27	4
auto[BaudRate1p5Mbps]	freqs[25]	150	1			T2	1		T29	1		T37	1
auto[BaudRate1p5Mbps]	freqs[48]	66	1			T26	9		T268	1		T136	1
auto[BaudRate1p5Mbps]	freqs[50]	104	1			T9	9		T28	2		T304	2
auto[BaudRate1p5Mbps]	freqs[100]	162	1			T125	1		T40	1		T27	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded