Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.45	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	7	123	94.62

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	7	123	94.62	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	30210287	1			T1	381		T2	52		T3	216
all_levels[1]	198653	1			T1	20		T2	15		T3	13
all_levels[2]	2841	1			T2	6		T4	3		T5	1
all_levels[3]	1127	1			T2	7		T5	2		T9	5
all_levels[4]	722	1			T2	8		T5	1		T8	2
all_levels[5]	531	1			T9	2		T10	1		T36	1
all_levels[6]	427	1			T2	1		T8	1		T9	1
all_levels[7]	353	1			T2	1		T5	1		T8	2
all_levels[8]	295	1			T5	4		T9	1		T32	1
all_levels[9]	255	1			T1	1		T5	3		T8	1
all_levels[10]	236	1			T5	2		T23	2		T38	1
all_levels[11]	173	1			T133	1		T40	1		T134	1
all_levels[12]	152	1			T5	1		T40	3		T135	1
all_levels[13]	141	1			T5	1		T23	1		T38	1
all_levels[14]	129	1			T5	2		T10	1		T32	2
all_levels[15]	127	1			T23	2		T134	1		T42	4
all_levels[16]	92	1			T5	1		T38	3		T42	2
all_levels[17]	96	1			T23	1		T38	3		T44	1
all_levels[18]	80	1			T125	1		T38	1		T136	2
all_levels[19]	78	1			T38	1		T137	1		T135	1
all_levels[20]	82	1			T5	2		T38	1		T40	2
all_levels[21]	67	1			T2	1		T134	2		T42	1
all_levels[22]	54	1			T134	1		T138	1		T139	1
all_levels[23]	63	1			T32	1		T40	3		T126	1
all_levels[24]	54	1			T134	2		T140	1		T141	1
all_levels[25]	61	1			T38	1		T142	1		T126	2
all_levels[26]	52	1			T15	1		T24	1		T42	1
all_levels[27]	35	1			T38	2		T143	1		T144	1
all_levels[28]	48	1			T38	1		T135	1		T145	2
all_levels[29]	31	1			T42	1		T128	1		T146	1
all_levels[30]	46	1			T8	1		T38	1		T42	1
all_levels[31]	33	1			T8	1		T30	1		T142	1
all_levels[32]	36	1			T30	1		T147	1		T142	1
all_levels[33]	28	1			T147	1		T148	2		T146	1
all_levels[34]	38	1			T32	1		T42	1		T149	1
all_levels[35]	40	1			T32	1		T135	1		T126	2
all_levels[36]	20	1			T42	1		T150	2		T78	2
all_levels[37]	19	1			T135	1		T141	1		T151	1
all_levels[38]	22	1			T48	2		T82	1		T151	1
all_levels[39]	18	1			T44	1		T152	1		T153	1
all_levels[40]	22	1			T42	1		T154	4		T155	1
all_levels[41]	6	1			T156	1		T157	1		T158	1
all_levels[42]	30	1			T159	1		T61	1		T160	1
all_levels[43]	7	1			T161	1		T162	1		T163	1
all_levels[44]	26	1			T164	1		T165	1		T166	1
all_levels[45]	17	1			T32	1		T149	1		T49	1
all_levels[46]	17	1			T43	3		T139	1		T167	1
all_levels[47]	17	1			T42	1		T168	1		T169	1
all_levels[48]	16	1			T135	1		T136	1		T142	1
all_levels[49]	11	1			T136	1		T170	1		T155	1
all_levels[50]	11	1			T143	1		T119	1		T170	1
all_levels[51]	23	1			T30	1		T43	1		T171	2
all_levels[52]	7	1			T128	1		T172	1		T173	1
all_levels[53]	14	1			T30	1		T174	1		T143	1
all_levels[54]	16	1			T165	1		T175	1		T176	1
all_levels[55]	10	1			T177	1		T158	1		T173	2
all_levels[56]	12	1			T126	1		T149	1		T139	1
all_levels[57]	10	1			T51	1		T178	1		T179	1
all_levels[58]	9	1			T30	1		T167	1		T180	1
all_levels[59]	11	1			T181	1		T155	1		T182	1
all_levels[60]	8	1			T5	1		T183	1		T184	1
all_levels[61]	7	1			T174	1		T141	2		T185	1
all_levels[62]	5	1			T118	1		T144	1		T186	1
all_levels[63]	13	1			T147	1		T187	1		T78	1
all_levels[64]	151	1			T5	1		T30	1		T133	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30413258

1

T1

402

T2

83

T3

224

auto[1]

4860

1

T2

8

T3

5

T5

7

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	7	123	94.62	7

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[22]]	[auto[1]]	0	1	1
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[58] , all_levels[59]]	[auto[1]]	--	--	2
[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	30205936	1			T1	381		T2	45		T3	211
all_levels[0]	auto[1]	4351	1			T2	7		T3	5		T5	7
all_levels[1]	auto[0]	198583	1			T1	20		T2	15		T3	13
all_levels[1]	auto[1]	70	1			T188	1		T152	1		T189	2
all_levels[2]	auto[0]	2809	1			T2	6		T4	3		T5	1
all_levels[2]	auto[1]	32	1			T190	1		T63	1		T123	1
all_levels[3]	auto[0]	1095	1			T2	7		T5	2		T9	5
all_levels[3]	auto[1]	32	1			T191	2		T192	1		T193	1
all_levels[4]	auto[0]	702	1			T2	7		T5	1		T8	2
all_levels[4]	auto[1]	20	1			T2	1		T194	3		T195	4
all_levels[5]	auto[0]	516	1			T9	2		T10	1		T36	1
all_levels[5]	auto[1]	15	1			T125	1		T152	1		T153	1
all_levels[6]	auto[0]	415	1			T2	1		T8	1		T9	1
all_levels[6]	auto[1]	12	1			T156	2		T196	1		T197	2
all_levels[7]	auto[0]	333	1			T2	1		T5	1		T8	2
all_levels[7]	auto[1]	20	1			T38	1		T198	2		T199	1
all_levels[8]	auto[0]	278	1			T5	4		T9	1		T32	1
all_levels[8]	auto[1]	17	1			T145	3		T50	5		T200	1
all_levels[9]	auto[0]	242	1			T1	1		T5	3		T8	1
all_levels[9]	auto[1]	13	1			T126	1		T201	1		T202	1
all_levels[10]	auto[0]	218	1			T5	2		T23	2		T38	1
all_levels[10]	auto[1]	18	1			T187	1		T193	1		T203	3
all_levels[11]	auto[0]	162	1			T133	1		T40	1		T134	1
all_levels[11]	auto[1]	11	1			T189	1		T48	2		T183	1
all_levels[12]	auto[0]	141	1			T5	1		T40	3		T135	1
all_levels[12]	auto[1]	11	1			T78	1		T165	1		T63	1
all_levels[13]	auto[0]	134	1			T5	1		T23	1		T38	1
all_levels[13]	auto[1]	7	1			T204	1		T205	1		T206	2
all_levels[14]	auto[0]	109	1			T5	2		T10	1		T32	2
all_levels[14]	auto[1]	20	1			T202	2		T207	1		T208	3
all_levels[15]	auto[0]	116	1			T23	2		T134	1		T42	4
all_levels[15]	auto[1]	11	1			T126	1		T82	1		T141	2
all_levels[16]	auto[0]	78	1			T5	1		T38	1		T42	2
all_levels[16]	auto[1]	14	1			T38	2		T209	4		T210	1
all_levels[17]	auto[0]	86	1			T23	1		T38	3		T44	1
all_levels[17]	auto[1]	10	1			T211	2		T212	1		T173	2
all_levels[18]	auto[0]	76	1			T125	1		T38	1		T136	2
all_levels[18]	auto[1]	4	1			T213	1		T214	1		T215	1
all_levels[19]	auto[0]	67	1			T38	1		T137	1		T135	1
all_levels[19]	auto[1]	11	1			T188	1		T216	2		T217	3
all_levels[20]	auto[0]	76	1			T5	2		T38	1		T40	2
all_levels[20]	auto[1]	6	1			T201	1		T204	1		T218	1
all_levels[21]	auto[0]	55	1			T2	1		T134	2		T42	1
all_levels[21]	auto[1]	12	1			T219	1		T201	3		T169	2
all_levels[22]	auto[0]	54	1			T134	1		T138	1		T139	1
all_levels[23]	auto[0]	57	1			T32	1		T40	2		T126	1
all_levels[23]	auto[1]	6	1			T40	1		T190	2		T220	1
all_levels[24]	auto[0]	53	1			T134	2		T140	1		T141	1
all_levels[24]	auto[1]	1	1			T208	1		-	-		-	-
all_levels[25]	auto[0]	60	1			T38	1		T142	1		T126	2
all_levels[25]	auto[1]	1	1			T50	1		-	-		-	-
all_levels[26]	auto[0]	48	1			T15	1		T24	1		T42	1
all_levels[26]	auto[1]	4	1			T221	1		T222	1		T223	2
all_levels[27]	auto[0]	34	1			T38	2		T143	1		T144	1
all_levels[27]	auto[1]	1	1			T224	1		-	-		-	-
all_levels[28]	auto[0]	43	1			T38	1		T135	1		T145	2
all_levels[28]	auto[1]	5	1			T204	2		T225	2		T226	1
all_levels[29]	auto[0]	28	1			T42	1		T128	1		T146	1
all_levels[29]	auto[1]	3	1			T213	1		T227	1		T228	1
all_levels[30]	auto[0]	40	1			T8	1		T38	1		T42	1
all_levels[30]	auto[1]	6	1			T229	2		T230	1		T231	1
all_levels[31]	auto[0]	32	1			T8	1		T30	1		T142	1
all_levels[31]	auto[1]	1	1			T175	1		-	-		-	-
all_levels[32]	auto[0]	32	1			T30	1		T147	1		T142	1
all_levels[32]	auto[1]	4	1			T232	2		T141	1		T233	1
all_levels[33]	auto[0]	27	1			T147	1		T148	1		T146	1
all_levels[33]	auto[1]	1	1			T148	1		-	-		-	-
all_levels[34]	auto[0]	33	1			T32	1		T42	1		T149	1
all_levels[34]	auto[1]	5	1			T234	4		T235	1		-	-
all_levels[35]	auto[0]	32	1			T32	1		T135	1		T126	2
all_levels[35]	auto[1]	8	1			T82	1		T217	1		T236	1
all_levels[36]	auto[0]	17	1			T42	1		T150	1		T78	1
all_levels[36]	auto[1]	3	1			T150	1		T78	1		T237	1
all_levels[37]	auto[0]	19	1			T135	1		T141	1		T151	1
all_levels[38]	auto[0]	17	1			T48	1		T82	1		T151	1
all_levels[38]	auto[1]	5	1			T48	1		T238	2		T239	1
all_levels[39]	auto[0]	17	1			T44	1		T152	1		T153	1
all_levels[39]	auto[1]	1	1			T173	1		-	-		-	-
all_levels[40]	auto[0]	15	1			T42	1		T154	1		T155	1
all_levels[40]	auto[1]	7	1			T154	3		T240	1		T241	3
all_levels[41]	auto[0]	6	1			T156	1		T157	1		T158	1
all_levels[42]	auto[0]	23	1			T159	1		T61	1		T160	1
all_levels[42]	auto[1]	7	1			T242	1		T212	2		T243	1
all_levels[43]	auto[0]	6	1			T161	1		T162	1		T163	1
all_levels[43]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[44]	auto[0]	19	1			T164	1		T165	1		T166	1
all_levels[44]	auto[1]	7	1			T245	2		T246	1		T247	4
all_levels[45]	auto[0]	13	1			T32	1		T149	1		T49	1
all_levels[45]	auto[1]	4	1			T248	1		T249	2		T234	1
all_levels[46]	auto[0]	13	1			T43	1		T139	1		T167	1
all_levels[46]	auto[1]	4	1			T43	2		T183	1		T250	1
all_levels[47]	auto[0]	14	1			T42	1		T168	1		T169	1
all_levels[47]	auto[1]	3	1			T251	3		-	-		-	-
all_levels[48]	auto[0]	13	1			T135	1		T136	1		T142	1
all_levels[48]	auto[1]	3	1			T252	3		-	-		-	-
all_levels[49]	auto[0]	9	1			T136	1		T170	1		T155	1
all_levels[49]	auto[1]	2	1			T253	2		-	-		-	-
all_levels[50]	auto[0]	9	1			T143	1		T119	1		T170	1
all_levels[50]	auto[1]	2	1			T228	2		-	-		-	-
all_levels[51]	auto[0]	20	1			T30	1		T43	1		T171	1
all_levels[51]	auto[1]	3	1			T171	1		T254	2		-	-
all_levels[52]	auto[0]	7	1			T128	1		T172	1		T173	1
all_levels[53]	auto[0]	11	1			T30	1		T174	1		T143	1
all_levels[53]	auto[1]	3	1			T255	1		T256	1		T257	1
all_levels[54]	auto[0]	15	1			T165	1		T175	1		T176	1
all_levels[54]	auto[1]	1	1			T258	1		-	-		-	-
all_levels[55]	auto[0]	9	1			T177	1		T158	1		T173	1
all_levels[55]	auto[1]	1	1			T173	1		-	-		-	-
all_levels[56]	auto[0]	11	1			T126	1		T149	1		T139	1
all_levels[56]	auto[1]	1	1			T259	1		-	-		-	-
all_levels[57]	auto[0]	9	1			T51	1		T178	1		T179	1
all_levels[57]	auto[1]	1	1			T260	1		-	-		-	-
all_levels[58]	auto[0]	9	1			T30	1		T167	1		T180	1
all_levels[59]	auto[0]	11	1			T181	1		T155	1		T182	1
all_levels[60]	auto[0]	7	1			T5	1		T183	1		T184	1
all_levels[60]	auto[1]	1	1			T246	1		-	-		-	-
all_levels[61]	auto[0]	5	1			T174	1		T141	1		T185	1
all_levels[61]	auto[1]	2	1			T141	1		T217	1		-	-
all_levels[62]	auto[0]	5	1			T118	1		T144	1		T186	1
all_levels[63]	auto[0]	11	1			T147	1		T187	1		T78	1
all_levels[63]	auto[1]	2	1			T261	2		-	-		-	-
all_levels[64]	auto[0]	118	1			T5	1		T30	1		T133	1
all_levels[64]	auto[1]	33	1			T133	1		T171	3		T255	3