Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 13 0 13 100.00
Crosses 36 0 36 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 9 0 9 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 36 0 36 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 9 0 9 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 108732 1 T1 37 T2 16 T3 80
all_pins[1] 108732 1 T1 37 T2 16 T3 80
all_pins[2] 108732 1 T1 37 T2 16 T3 80
all_pins[3] 108732 1 T1 37 T2 16 T3 80
all_pins[4] 108732 1 T1 37 T2 16 T3 80
all_pins[5] 108732 1 T1 37 T2 16 T3 80
all_pins[6] 108732 1 T1 37 T2 16 T3 80
all_pins[7] 108732 1 T1 37 T2 16 T3 80
all_pins[8] 108732 1 T1 37 T2 16 T3 80



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 933390 1 T1 319 T2 118 T3 715
values[0x1] 45198 1 T1 14 T2 26 T3 5
transitions[0x0=>0x1] 36363 1 T1 11 T2 15 T3 5
transitions[0x1=>0x0] 36153 1 T1 12 T2 14 T3 5



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 36 0 36 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 86081 1 T1 34 T2 3 T3 79
all_pins[0] values[0x1] 22651 1 T1 3 T2 13 T3 1
all_pins[0] transitions[0x0=>0x1] 22071 1 T1 3 T2 4 T3 1
all_pins[0] transitions[0x1=>0x0] 1005 1 T2 2 T5 1 T6 19
all_pins[1] values[0x0] 107147 1 T1 37 T2 5 T3 80
all_pins[1] values[0x1] 1585 1 T2 11 T5 1 T6 26
all_pins[1] transitions[0x0=>0x1] 1461 1 T2 9 T5 1 T6 26
all_pins[1] transitions[0x1=>0x0] 2449 1 T1 5 T3 2 T4 3
all_pins[2] values[0x0] 106159 1 T1 32 T2 14 T3 78
all_pins[2] values[0x1] 2573 1 T1 5 T2 2 T3 2
all_pins[2] transitions[0x0=>0x1] 2516 1 T1 5 T2 2 T3 2
all_pins[2] transitions[0x1=>0x0] 241 1 T8 1 T9 2 T10 1
all_pins[3] values[0x0] 108434 1 T1 37 T2 16 T3 80
all_pins[3] values[0x1] 298 1 T5 1 T8 1 T9 2
all_pins[3] transitions[0x0=>0x1] 262 1 T5 1 T8 1 T9 2
all_pins[3] transitions[0x1=>0x0] 355 1 T5 2 T6 6 T8 2
all_pins[4] values[0x0] 108341 1 T1 37 T2 16 T3 80
all_pins[4] values[0x1] 391 1 T5 2 T6 6 T8 2
all_pins[4] transitions[0x0=>0x1] 315 1 T6 5 T8 2 T10 2
all_pins[4] transitions[0x1=>0x0] 174 1 T5 1 T11 1 T23 3
all_pins[5] values[0x0] 108482 1 T1 37 T2 16 T3 80
all_pins[5] values[0x1] 250 1 T5 3 T6 1 T11 1
all_pins[5] transitions[0x0=>0x1] 192 1 T5 3 T6 1 T11 1
all_pins[5] transitions[0x1=>0x0] 838 1 T8 4 T10 3 T15 3
all_pins[6] values[0x0] 107836 1 T1 37 T2 16 T3 80
all_pins[6] values[0x1] 896 1 T8 4 T10 3 T15 3
all_pins[6] transitions[0x0=>0x1] 837 1 T8 1 T10 3 T15 3
all_pins[6] transitions[0x1=>0x0] 306 1 T5 1 T8 2 T23 2
all_pins[7] values[0x0] 108367 1 T1 37 T2 16 T3 80
all_pins[7] values[0x1] 365 1 T5 1 T8 5 T23 2
all_pins[7] transitions[0x0=>0x1] 218 1 T8 3 T44 2 T42 2
all_pins[7] transitions[0x1=>0x0] 16042 1 T1 6 T3 2 T4 1
all_pins[8] values[0x0] 92543 1 T1 31 T2 16 T3 78
all_pins[8] values[0x1] 16189 1 T1 6 T3 2 T4 1
all_pins[8] transitions[0x0=>0x1] 8491 1 T1 3 T3 2 T5 4
all_pins[8] transitions[0x1=>0x0] 14743 1 T1 1 T2 12 T3 1

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