Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7497605	1			T1	127		T2	43		T3	177
all_levels[1]	2061444	1			T1	27		T2	2		T3	1
all_levels[2]	571796	1			T1	8		T2	1		T4	247
all_levels[3]	250834	1			T1	7		T2	1		T4	2
all_levels[4]	341129	1			T1	8		T2	2		T4	4
all_levels[5]	265952	1			T1	18		T2	1		T5	2
all_levels[6]	320202	1			T1	11		T2	11		T4	10
all_levels[7]	197932	1			T1	8		T2	1		T4	12
all_levels[8]	289432	1			T1	12		T3	3		T6	729
all_levels[9]	224007	1			T1	16		T2	3		T5	6
all_levels[10]	219484	1			T1	5		T2	1		T5	1
all_levels[11]	190490	1			T1	3		T2	3		T5	6
all_levels[12]	325615	1			T1	3		T4	14		T5	1
all_levels[13]	221632	1			T1	2		T2	1		T5	10
all_levels[14]	217230	1			T1	3		T2	2		T9	1309
all_levels[15]	268724	1			T5	2		T9	1394		T10	1179
all_levels[16]	247757	1			T2	1		T5	3		T9	1305
all_levels[17]	175508	1			T1	1		T5	2		T9	1415
all_levels[18]	218774	1			T1	2		T5	3		T9	1199
all_levels[19]	169404	1			T1	2		T2	3		T5	1
all_levels[20]	290300	1			T1	73		T2	1		T9	1535
all_levels[21]	193089	1			T2	1		T3	3		T5	1
all_levels[22]	351103	1			T1	8		T3	3		T5	11
all_levels[23]	751357	1			T3	7		T9	1219		T10	1336
all_levels[24]	373721	1			T2	3		T3	4		T5	2
all_levels[25]	233914	1			T1	10		T3	1		T9	1116
all_levels[26]	231711	1			T3	12		T5	1		T9	1344
all_levels[27]	165798	1			T2	1		T3	4		T9	1142
all_levels[28]	338304	1			T3	8		T8	7		T9	1185
all_levels[29]	179014	1			T2	2		T3	1		T9	1459
all_levels[30]	232547	1			T2	3		T3	4		T9	927
all_levels[31]	502327	1			T2	3		T3	4		T5	1
all_levels[32]	12299526	1			T1	49		T2	1		T5	12

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30413258

1

T1

402

T2

83

T3

224

auto[1]

4404

1

T1

1

T2

8

T3

8

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7495163	1			T1	127		T2	38		T3	175
all_levels[0]	auto[1]	2442	1			T2	5		T3	2		T6	2
all_levels[1]	auto[0]	2061108	1			T1	27		T2	1		T3	1
all_levels[1]	auto[1]	336	1			T2	1		T5	1		T35	2
all_levels[2]	auto[0]	571750	1			T1	8		T2	1		T4	247
all_levels[2]	auto[1]	46	1			T268	4		T145	3		T82	2
all_levels[3]	auto[0]	250746	1			T1	7		T2	1		T4	2
all_levels[3]	auto[1]	88	1			T189	3		T85	2		T341	3
all_levels[4]	auto[0]	341100	1			T1	8		T2	2		T4	4
all_levels[4]	auto[1]	29	1			T201	2		T159	1		T342	1
all_levels[5]	auto[0]	265920	1			T1	18		T2	1		T5	2
all_levels[5]	auto[1]	32	1			T140	2		T189	1		T199	1
all_levels[6]	auto[0]	320175	1			T1	11		T2	9		T4	10
all_levels[6]	auto[1]	27	1			T2	2		T35	1		T154	2
all_levels[7]	auto[0]	197730	1			T1	8		T2	1		T4	12
all_levels[7]	auto[1]	202	1			T6	34		T268	1		T191	2
all_levels[8]	auto[0]	289394	1			T1	12		T3	2		T6	729
all_levels[8]	auto[1]	38	1			T3	1		T268	3		T190	2
all_levels[9]	auto[0]	223981	1			T1	16		T2	3		T5	6
all_levels[9]	auto[1]	26	1			T189	1		T154	1		T156	1
all_levels[10]	auto[0]	219459	1			T1	5		T2	1		T5	1
all_levels[10]	auto[1]	25	1			T36	1		T38	2		T43	1
all_levels[11]	auto[0]	190447	1			T1	3		T2	3		T5	6
all_levels[11]	auto[1]	43	1			T125	1		T171	3		T340	1
all_levels[12]	auto[0]	325584	1			T1	3		T4	13		T5	1
all_levels[12]	auto[1]	31	1			T4	1		T9	1		T42	2
all_levels[13]	auto[0]	221610	1			T1	2		T2	1		T5	10
all_levels[13]	auto[1]	22	1			T15	1		T304	1		T191	2
all_levels[14]	auto[0]	217206	1			T1	3		T2	2		T9	1309
all_levels[14]	auto[1]	24	1			T40	2		T25	1		T191	1
all_levels[15]	auto[0]	268585	1			T5	2		T9	1394		T10	1179
all_levels[15]	auto[1]	139	1			T192	1		T118	1		T203	1
all_levels[16]	auto[0]	247735	1			T2	1		T5	3		T9	1304
all_levels[16]	auto[1]	22	1			T9	1		T269	1		T48	2
all_levels[17]	auto[0]	175486	1			T1	1		T5	2		T9	1415
all_levels[17]	auto[1]	22	1			T190	1		T198	2		T324	2
all_levels[18]	auto[0]	218757	1			T1	2		T5	3		T9	1199
all_levels[18]	auto[1]	17	1			T188	1		T199	1		T65	1
all_levels[19]	auto[0]	169395	1			T1	2		T2	3		T5	1
all_levels[19]	auto[1]	9	1			T38	1		T343	1		T344	1
all_levels[20]	auto[0]	290281	1			T1	73		T2	1		T9	1535
all_levels[20]	auto[1]	19	1			T125	1		T314	1		T345	1
all_levels[21]	auto[0]	193064	1			T2	1		T3	2		T5	1
all_levels[21]	auto[1]	25	1			T3	1		T35	2		T40	2
all_levels[22]	auto[0]	351073	1			T1	8		T3	3		T5	11
all_levels[22]	auto[1]	30	1			T42	1		T190	2		T346	1
all_levels[23]	auto[0]	751331	1			T3	7		T9	1219		T10	1336
all_levels[23]	auto[1]	26	1			T147	1		T304	1		T280	2
all_levels[24]	auto[0]	373696	1			T2	3		T3	4		T5	2
all_levels[24]	auto[1]	25	1			T297	1		T280	2		T141	2
all_levels[25]	auto[0]	233906	1			T1	10		T3	1		T9	1116
all_levels[25]	auto[1]	8	1			T255	1		T165	1		T347	2
all_levels[26]	auto[0]	231685	1			T3	8		T5	1		T9	1344
all_levels[26]	auto[1]	26	1			T3	4		T119	3		T348	2
all_levels[27]	auto[0]	165782	1			T2	1		T3	4		T9	1142
all_levels[27]	auto[1]	16	1			T160	1		T238	2		T349	2
all_levels[28]	auto[0]	338288	1			T3	8		T8	7		T9	1185
all_levels[28]	auto[1]	16	1			T306	2		T159	1		T350	2
all_levels[29]	auto[0]	178998	1			T2	2		T3	1		T9	1459
all_levels[29]	auto[1]	16	1			T183	2		T343	1		T242	2
all_levels[30]	auto[0]	232525	1			T2	3		T3	4		T9	927
all_levels[30]	auto[1]	22	1			T164	1		T219	1		T351	1
all_levels[31]	auto[0]	502310	1			T2	3		T3	4		T5	1
all_levels[31]	auto[1]	17	1			T304	1		T292	1		T50	1
all_levels[32]	auto[0]	12298988	1			T1	48		T2	1		T5	12
all_levels[32]	auto[1]	538	1			T1	1		T9	1		T10	1