Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	781	1			T5	4		T8	7		T9	4
all_values[1]	781	1			T5	4		T8	7		T9	4
all_values[2]	781	1			T5	4		T8	7		T9	4
all_values[3]	781	1			T5	4		T8	7		T9	4
all_values[4]	781	1			T5	4		T8	7		T9	4
all_values[5]	781	1			T5	4		T8	7		T9	4
all_values[6]	781	1			T5	4		T8	7		T9	4
all_values[7]	781	1			T5	4		T8	7		T9	4
all_values[8]	781	1			T5	4		T8	7		T9	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3738

1

T5

22

T8

27

T9

26

auto[1]

3291

1

T5

14

T8

36

T9

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2329

1

T5

12

T8

22

T9

9

auto[1]

4700

1

T5

24

T8

41

T9

27

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4161

1

T5

22

T8

37

T9

20

auto[1]

2868

1

T5

14

T8

26

T9

16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	251	1			T5	2		T8	1		T9	1
all_values[0]	auto[0]	auto[1]	auto[1]	202	1			T5	1		T8	2		T9	2
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T5	1		T9	1		T10	2
all_values[0]	auto[1]	auto[1]	auto[1]	150	1			T8	4		T10	1		T42	1
all_values[1]	auto[0]	auto[0]	auto[0]	225	1			T5	2		T9	2		T10	2
all_values[1]	auto[0]	auto[1]	auto[0]	219	1			T5	1		T8	4		T10	1
all_values[1]	auto[1]	auto[0]	auto[1]	191	1			T8	1		T9	2		T23	1
all_values[1]	auto[1]	auto[1]	auto[1]	146	1			T5	1		T8	2		T10	1
all_values[2]	auto[0]	auto[0]	auto[0]	155	1			T8	2		T10	1		T42	2
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T5	1		T9	2		T23	2
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T8	2		T27	2		T42	2
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T8	1		T10	1		T23	1
all_values[2]	auto[1]	auto[0]	auto[1]	190	1			T5	2		T8	2		T9	2
all_values[2]	auto[1]	auto[1]	auto[1]	139	1			T5	1		T10	2		T27	2
all_values[3]	auto[0]	auto[0]	auto[0]	190	1			T5	2		T8	2		T23	1
all_values[3]	auto[0]	auto[0]	auto[1]	75	1			T10	1		T42	1		T117	2
all_values[3]	auto[0]	auto[1]	auto[0]	134	1			T5	1		T8	3		T27	2
all_values[3]	auto[0]	auto[1]	auto[1]	68	1			T9	1		T128	3		T119	1
all_values[3]	auto[1]	auto[0]	auto[1]	166	1			T8	1		T9	2		T10	2
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T5	1		T8	1		T9	1
all_values[4]	auto[0]	auto[0]	auto[0]	201	1			T5	1		T8	2		T9	1
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T8	1		T117	2		T129	2
all_values[4]	auto[0]	auto[1]	auto[0]	130	1			T5	1		T8	1		T9	2
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T5	1		T27	2		T42	1
all_values[4]	auto[1]	auto[0]	auto[1]	152	1			T8	1		T9	1		T10	1
all_values[4]	auto[1]	auto[1]	auto[1]	144	1			T5	1		T8	2		T10	2
all_values[5]	auto[0]	auto[0]	auto[0]	157	1			T5	1		T8	2		T9	1
all_values[5]	auto[0]	auto[0]	auto[1]	68	1			T8	2		T9	1		T10	2
all_values[5]	auto[0]	auto[1]	auto[0]	156	1			T8	2		T9	1		T27	1
all_values[5]	auto[0]	auto[1]	auto[1]	86	1			T5	1		T23	3		T42	1
all_values[5]	auto[1]	auto[0]	auto[1]	161	1			T8	1		T9	1		T10	2
all_values[5]	auto[1]	auto[1]	auto[1]	153	1			T5	2		T27	1		T42	1
all_values[6]	auto[0]	auto[0]	auto[0]	157	1			T5	2		T10	2		T23	1
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T8	1		T9	1		T122	1
all_values[6]	auto[0]	auto[1]	auto[0]	142	1			T8	1		T10	1		T23	1
all_values[6]	auto[0]	auto[1]	auto[1]	89	1			T8	1		T23	1		T27	1
all_values[6]	auto[1]	auto[0]	auto[1]	159	1			T5	2		T8	1		T9	2
all_values[6]	auto[1]	auto[1]	auto[1]	153	1			T8	3		T9	1		T27	1
all_values[7]	auto[0]	auto[0]	auto[0]	172	1			T5	1		T8	1		T10	1
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T5	1		T8	1		T9	1
all_values[7]	auto[0]	auto[1]	auto[0]	147	1			T9	2		T10	1		T23	1
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T8	2		T23	1		T42	1
all_values[7]	auto[1]	auto[0]	auto[1]	165	1			T5	1		T8	2		T9	1
all_values[7]	auto[1]	auto[1]	auto[1]	149	1			T5	1		T8	1		T23	1
all_values[8]	auto[0]	auto[0]	auto[1]	225	1			T5	3		T8	2		T9	2
all_values[8]	auto[0]	auto[1]	auto[1]	232	1			T8	1		T10	3		T23	1
all_values[8]	auto[1]	auto[0]	auto[1]	183	1			T8	1		T9	2		T10	1
all_values[8]	auto[1]	auto[1]	auto[1]	141	1			T5	1		T8	3		T23	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal