Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.62


Total test records in report: 1312
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T1257 /workspace/coverage/cover_reg_top/6.uart_intr_test.2681734351 Jul 06 04:52:38 PM PDT 24 Jul 06 04:52:39 PM PDT 24 51847177 ps
T1258 /workspace/coverage/cover_reg_top/30.uart_intr_test.3523511434 Jul 06 04:52:47 PM PDT 24 Jul 06 04:52:48 PM PDT 24 27311944 ps
T72 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3176114774 Jul 06 04:52:37 PM PDT 24 Jul 06 04:52:38 PM PDT 24 46939776 ps
T1259 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3275251113 Jul 06 04:52:23 PM PDT 24 Jul 06 04:52:24 PM PDT 24 48419817 ps
T132 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.14076346 Jul 06 04:52:36 PM PDT 24 Jul 06 04:52:38 PM PDT 24 222760983 ps
T1260 /workspace/coverage/cover_reg_top/16.uart_tl_errors.2337774255 Jul 06 04:52:42 PM PDT 24 Jul 06 04:52:44 PM PDT 24 228804362 ps
T1261 /workspace/coverage/cover_reg_top/19.uart_intr_test.3013681341 Jul 06 04:52:48 PM PDT 24 Jul 06 04:52:50 PM PDT 24 15300257 ps
T1262 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2061445533 Jul 06 04:52:24 PM PDT 24 Jul 06 04:52:25 PM PDT 24 50193457 ps
T1263 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3257959459 Jul 06 04:52:31 PM PDT 24 Jul 06 04:52:33 PM PDT 24 115180157 ps
T104 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2317835062 Jul 06 04:52:46 PM PDT 24 Jul 06 04:52:47 PM PDT 24 538030796 ps
T1264 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.247370991 Jul 06 04:52:47 PM PDT 24 Jul 06 04:52:48 PM PDT 24 46611272 ps
T1265 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2427693523 Jul 06 04:52:38 PM PDT 24 Jul 06 04:52:40 PM PDT 24 34748416 ps
T73 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2754808792 Jul 06 04:52:38 PM PDT 24 Jul 06 04:52:39 PM PDT 24 30315398 ps
T74 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3835929332 Jul 06 04:52:34 PM PDT 24 Jul 06 04:52:35 PM PDT 24 17934196 ps
T1266 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2495362768 Jul 06 04:52:32 PM PDT 24 Jul 06 04:52:33 PM PDT 24 13212877 ps
T1267 /workspace/coverage/cover_reg_top/17.uart_intr_test.3563625139 Jul 06 04:52:47 PM PDT 24 Jul 06 04:52:48 PM PDT 24 45197431 ps
T1268 /workspace/coverage/cover_reg_top/36.uart_intr_test.1862838737 Jul 06 04:52:48 PM PDT 24 Jul 06 04:52:49 PM PDT 24 42075869 ps
T1269 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1085694784 Jul 06 04:52:37 PM PDT 24 Jul 06 04:52:38 PM PDT 24 22755481 ps
T1270 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1238144009 Jul 06 04:52:23 PM PDT 24 Jul 06 04:52:24 PM PDT 24 18353081 ps
T1271 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2740759920 Jul 06 04:52:47 PM PDT 24 Jul 06 04:52:49 PM PDT 24 57195023 ps
T1272 /workspace/coverage/cover_reg_top/7.uart_tl_errors.3594004886 Jul 06 04:52:37 PM PDT 24 Jul 06 04:52:40 PM PDT 24 239567261 ps
T1273 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1622807853 Jul 06 04:52:34 PM PDT 24 Jul 06 04:52:37 PM PDT 24 51598668 ps
T1274 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3001420186 Jul 06 04:52:24 PM PDT 24 Jul 06 04:52:25 PM PDT 24 31427046 ps
T1275 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1189027057 Jul 06 04:52:45 PM PDT 24 Jul 06 04:52:46 PM PDT 24 25965813 ps
T1276 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3021158800 Jul 06 04:52:42 PM PDT 24 Jul 06 04:52:43 PM PDT 24 66829237 ps
T1277 /workspace/coverage/cover_reg_top/18.uart_intr_test.3569888547 Jul 06 04:52:47 PM PDT 24 Jul 06 04:52:48 PM PDT 24 18043273 ps
T75 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1557234208 Jul 06 04:52:29 PM PDT 24 Jul 06 04:52:32 PM PDT 24 108340935 ps
T1278 /workspace/coverage/cover_reg_top/47.uart_intr_test.2689026926 Jul 06 04:52:49 PM PDT 24 Jul 06 04:52:50 PM PDT 24 32298882 ps
T1279 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1478792834 Jul 06 04:52:44 PM PDT 24 Jul 06 04:52:45 PM PDT 24 63858753 ps
T1280 /workspace/coverage/cover_reg_top/3.uart_intr_test.4109544493 Jul 06 04:52:29 PM PDT 24 Jul 06 04:52:30 PM PDT 24 62360482 ps
T1281 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.172379255 Jul 06 04:52:46 PM PDT 24 Jul 06 04:52:47 PM PDT 24 19220655 ps
T1282 /workspace/coverage/cover_reg_top/43.uart_intr_test.1119990028 Jul 06 04:52:50 PM PDT 24 Jul 06 04:52:51 PM PDT 24 18662799 ps
T1283 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3870802061 Jul 06 04:52:24 PM PDT 24 Jul 06 04:52:25 PM PDT 24 22732991 ps
T1284 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1186988905 Jul 06 04:52:22 PM PDT 24 Jul 06 04:52:23 PM PDT 24 15751957 ps
T1285 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1551979790 Jul 06 04:52:35 PM PDT 24 Jul 06 04:52:36 PM PDT 24 59372185 ps
T1286 /workspace/coverage/cover_reg_top/9.uart_intr_test.1103951660 Jul 06 04:52:33 PM PDT 24 Jul 06 04:52:34 PM PDT 24 26353382 ps
T1287 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2113480731 Jul 06 04:52:34 PM PDT 24 Jul 06 04:52:36 PM PDT 24 21049226 ps
T1288 /workspace/coverage/cover_reg_top/39.uart_intr_test.1760637393 Jul 06 04:52:46 PM PDT 24 Jul 06 04:52:47 PM PDT 24 141574226 ps
T1289 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2814017233 Jul 06 04:52:24 PM PDT 24 Jul 06 04:52:27 PM PDT 24 795046817 ps
T1290 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3837606509 Jul 06 04:52:49 PM PDT 24 Jul 06 04:52:50 PM PDT 24 49515906 ps
T1291 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.893614986 Jul 06 04:52:23 PM PDT 24 Jul 06 04:52:24 PM PDT 24 15316797 ps
T1292 /workspace/coverage/cover_reg_top/11.uart_intr_test.2207386715 Jul 06 04:52:33 PM PDT 24 Jul 06 04:52:34 PM PDT 24 15244692 ps
T1293 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.72822323 Jul 06 04:52:34 PM PDT 24 Jul 06 04:52:35 PM PDT 24 180255067 ps
T1294 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2879874317 Jul 06 04:52:32 PM PDT 24 Jul 06 04:52:33 PM PDT 24 32517068 ps
T1295 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1765285557 Jul 06 04:52:46 PM PDT 24 Jul 06 04:52:49 PM PDT 24 381840993 ps
T1296 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1829166101 Jul 06 04:52:24 PM PDT 24 Jul 06 04:52:26 PM PDT 24 359943649 ps
T1297 /workspace/coverage/cover_reg_top/20.uart_intr_test.1802440251 Jul 06 04:52:46 PM PDT 24 Jul 06 04:52:47 PM PDT 24 89639265 ps
T1298 /workspace/coverage/cover_reg_top/14.uart_intr_test.3115018053 Jul 06 04:52:36 PM PDT 24 Jul 06 04:52:38 PM PDT 24 10701065 ps
T1299 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.766694078 Jul 06 04:52:23 PM PDT 24 Jul 06 04:52:24 PM PDT 24 150136715 ps
T1300 /workspace/coverage/cover_reg_top/16.uart_intr_test.2231483830 Jul 06 04:52:52 PM PDT 24 Jul 06 04:52:53 PM PDT 24 50440934 ps
T1301 /workspace/coverage/cover_reg_top/17.uart_tl_errors.450839228 Jul 06 04:52:51 PM PDT 24 Jul 06 04:52:53 PM PDT 24 16808367 ps
T1302 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3832378213 Jul 06 04:52:57 PM PDT 24 Jul 06 04:52:59 PM PDT 24 32672653 ps
T1303 /workspace/coverage/cover_reg_top/1.uart_intr_test.3598809514 Jul 06 04:52:23 PM PDT 24 Jul 06 04:52:25 PM PDT 24 12610326 ps
T1304 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3889570903 Jul 06 04:52:24 PM PDT 24 Jul 06 04:52:25 PM PDT 24 106534479 ps
T1305 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2634152071 Jul 06 04:52:44 PM PDT 24 Jul 06 04:52:45 PM PDT 24 35863803 ps
T1306 /workspace/coverage/cover_reg_top/48.uart_intr_test.41359303 Jul 06 04:52:45 PM PDT 24 Jul 06 04:52:46 PM PDT 24 18335310 ps
T1307 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4289507257 Jul 06 04:52:28 PM PDT 24 Jul 06 04:52:30 PM PDT 24 119457541 ps
T1308 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1734124157 Jul 06 04:52:37 PM PDT 24 Jul 06 04:52:39 PM PDT 24 65904890 ps
T1309 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2280874412 Jul 06 04:52:36 PM PDT 24 Jul 06 04:52:37 PM PDT 24 65589570 ps
T1310 /workspace/coverage/cover_reg_top/13.uart_csr_rw.3451014323 Jul 06 04:52:39 PM PDT 24 Jul 06 04:52:40 PM PDT 24 17819525 ps
T1311 /workspace/coverage/cover_reg_top/12.uart_tl_errors.407821249 Jul 06 04:52:39 PM PDT 24 Jul 06 04:52:41 PM PDT 24 118530020 ps
T1312 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4020494625 Jul 06 04:52:32 PM PDT 24 Jul 06 04:52:33 PM PDT 24 253634145 ps

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3709089195
Short name T10
Test name
Test status
Simulation time 159467783217 ps
CPU time 683.5 seconds
Started Jul 06 06:00:47 PM PDT 24
Finished Jul 06 06:12:11 PM PDT 24
Peak memory 216432 kb
Host smart-24787b2d-c56d-4f98-8d14-90a581e6d4bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709089195 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3709089195
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3103820171
Short name T15
Test name
Test status
Simulation time 452226720510 ps
CPU time 1401.2 seconds
Started Jul 06 06:01:10 PM PDT 24
Finished Jul 06 06:24:31 PM PDT 24
Peak memory 224944 kb
Host smart-b7f754bb-50b3-419e-9afa-9cc0bcb0f102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103820171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3103820171
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2012246547
Short name T118
Test name
Test status
Simulation time 350846848690 ps
CPU time 665.56 seconds
Started Jul 06 06:00:46 PM PDT 24
Finished Jul 06 06:11:51 PM PDT 24
Peak memory 216692 kb
Host smart-b8eda19b-285d-4a64-909d-2c34b4596aae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012246547 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2012246547
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2274088363
Short name T9
Test name
Test status
Simulation time 156871834365 ps
CPU time 643.38 seconds
Started Jul 06 05:56:49 PM PDT 24
Finished Jul 06 06:07:33 PM PDT 24
Peak memory 216732 kb
Host smart-98a18675-a240-4cf6-b492-b4bbc3b209d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274088363 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2274088363
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_intr.800379021
Short name T11
Test name
Test status
Simulation time 401531062685 ps
CPU time 133.25 seconds
Started Jul 06 05:57:36 PM PDT 24
Finished Jul 06 05:59:50 PM PDT 24
Peak memory 199920 kb
Host smart-5a56c991-7bf3-484c-88b1-2700d1f2c646
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800379021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.800379021
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.798378278
Short name T128
Test name
Test status
Simulation time 151175182204 ps
CPU time 671.92 seconds
Started Jul 06 06:01:10 PM PDT 24
Finished Jul 06 06:12:22 PM PDT 24
Peak memory 224836 kb
Host smart-8c107da8-8b96-49d5-b1ce-11b179365522
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798378278 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.798378278
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1956270630
Short name T144
Test name
Test status
Simulation time 187630562611 ps
CPU time 319.51 seconds
Started Jul 06 05:56:47 PM PDT 24
Finished Jul 06 06:02:07 PM PDT 24
Peak memory 199872 kb
Host smart-f2c465c1-bdd9-4729-accb-c7855c9f15e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956270630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1956270630
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1588611449
Short name T5
Test name
Test status
Simulation time 330102189624 ps
CPU time 234.38 seconds
Started Jul 06 05:59:28 PM PDT 24
Finished Jul 06 06:03:23 PM PDT 24
Peak memory 216644 kb
Host smart-8c602de7-3e1d-4318-b900-9cf7acf0e86d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588611449 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1588611449
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1131908850
Short name T267
Test name
Test status
Simulation time 67936096406 ps
CPU time 232.59 seconds
Started Jul 06 05:59:24 PM PDT 24
Finished Jul 06 06:03:17 PM PDT 24
Peak memory 200004 kb
Host smart-294b1465-97e8-4799-9d38-1bb3a01d9e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131908850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1131908850
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3310149032
Short name T98
Test name
Test status
Simulation time 454897751 ps
CPU time 1.3 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 200024 kb
Host smart-f57ebc99-be19-4dc2-bd01-2cfd264d8768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310149032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3310149032
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2326676017
Short name T86
Test name
Test status
Simulation time 18289727 ps
CPU time 0.54 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 05:56:44 PM PDT 24
Peak memory 195236 kb
Host smart-0d6abf87-e4c9-4f79-b594-8d9c9b66e715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326676017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2326676017
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.266085241
Short name T119
Test name
Test status
Simulation time 379824860205 ps
CPU time 1298.91 seconds
Started Jul 06 06:00:57 PM PDT 24
Finished Jul 06 06:22:36 PM PDT 24
Peak memory 226980 kb
Host smart-a236ee95-4e9c-4314-aac0-e36cdd4bec47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266085241 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.266085241
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.238748504
Short name T50
Test name
Test status
Simulation time 299158677750 ps
CPU time 936.59 seconds
Started Jul 06 06:00:52 PM PDT 24
Finished Jul 06 06:16:30 PM PDT 24
Peak memory 229432 kb
Host smart-afe05457-6712-4c54-a1c5-fa4636920400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238748504 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.238748504
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2044345254
Short name T188
Test name
Test status
Simulation time 90298885199 ps
CPU time 82.36 seconds
Started Jul 06 06:02:16 PM PDT 24
Finished Jul 06 06:03:39 PM PDT 24
Peak memory 199964 kb
Host smart-aa51800d-8130-4693-9216-9a0181afd05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044345254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2044345254
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.1758853532
Short name T42
Test name
Test status
Simulation time 244092703855 ps
CPU time 546.1 seconds
Started Jul 06 05:57:46 PM PDT 24
Finished Jul 06 06:06:52 PM PDT 24
Peak memory 199932 kb
Host smart-add506fb-644c-4d0f-8929-4238a9547c6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758853532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1758853532
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.950560635
Short name T20
Test name
Test status
Simulation time 61049711 ps
CPU time 0.93 seconds
Started Jul 06 05:56:45 PM PDT 24
Finished Jul 06 05:56:46 PM PDT 24
Peak memory 218480 kb
Host smart-60061e70-25f8-4008-b930-128895ec2f93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950560635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.950560635
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3605375624
Short name T281
Test name
Test status
Simulation time 203690866313 ps
CPU time 414.34 seconds
Started Jul 06 06:02:20 PM PDT 24
Finished Jul 06 06:09:15 PM PDT 24
Peak memory 200004 kb
Host smart-e4baecac-19d1-4317-a2ec-9b8a6b521169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605375624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3605375624
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2899643118
Short name T48
Test name
Test status
Simulation time 70510684878 ps
CPU time 847.52 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 06:10:51 PM PDT 24
Peak memory 224920 kb
Host smart-7e1e2df6-d3fd-40fd-8ec5-297b0d3e32ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899643118 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2899643118
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1789805033
Short name T125
Test name
Test status
Simulation time 153881382604 ps
CPU time 394.22 seconds
Started Jul 06 06:01:55 PM PDT 24
Finished Jul 06 06:08:29 PM PDT 24
Peak memory 200000 kb
Host smart-27b3ebe0-a272-4a06-ba08-4713fea539bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789805033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1789805033
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all.1098273854
Short name T174
Test name
Test status
Simulation time 129891914867 ps
CPU time 62.98 seconds
Started Jul 06 05:57:23 PM PDT 24
Finished Jul 06 05:58:26 PM PDT 24
Peak memory 199544 kb
Host smart-a5f7ef08-aec3-48c5-9675-4c38621e9bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098273854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1098273854
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2195673784
Short name T201
Test name
Test status
Simulation time 114487828473 ps
CPU time 190.93 seconds
Started Jul 06 06:00:18 PM PDT 24
Finished Jul 06 06:03:29 PM PDT 24
Peak memory 199988 kb
Host smart-0febda43-dbb8-4d4f-b17f-e63673b24f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195673784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2195673784
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.4032204595
Short name T268
Test name
Test status
Simulation time 97143310111 ps
CPU time 131.6 seconds
Started Jul 06 06:00:57 PM PDT 24
Finished Jul 06 06:03:08 PM PDT 24
Peak memory 199988 kb
Host smart-a865a1ca-1674-4d6b-afef-1bd2d10c82a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032204595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.4032204595
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.2083254923
Short name T155
Test name
Test status
Simulation time 299954823316 ps
CPU time 445.93 seconds
Started Jul 06 05:56:47 PM PDT 24
Finished Jul 06 06:04:13 PM PDT 24
Peak memory 199948 kb
Host smart-a3418475-7c12-49c8-bf19-04cdfe3f9578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083254923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2083254923
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.802590702
Short name T96
Test name
Test status
Simulation time 32551012 ps
CPU time 0.69 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 196276 kb
Host smart-a37987e0-2e96-4736-bda2-bfeb0a82fe0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802590702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.802590702
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1557234208
Short name T75
Test name
Test status
Simulation time 108340935 ps
CPU time 2.29 seconds
Started Jul 06 04:52:29 PM PDT 24
Finished Jul 06 04:52:32 PM PDT 24
Peak memory 198852 kb
Host smart-3ca3938d-a3d0-434b-9bfa-1c9778cd2c9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557234208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1557234208
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/default/16.uart_stress_all.1016588183
Short name T156
Test name
Test status
Simulation time 253713540749 ps
CPU time 807.22 seconds
Started Jul 06 05:57:57 PM PDT 24
Finished Jul 06 06:11:25 PM PDT 24
Peak memory 199972 kb
Host smart-d9f85587-1d9b-4160-af59-e48e9ed2f5e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016588183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1016588183
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3466780549
Short name T78
Test name
Test status
Simulation time 66046726451 ps
CPU time 38.82 seconds
Started Jul 06 06:02:00 PM PDT 24
Finished Jul 06 06:02:39 PM PDT 24
Peak memory 199948 kb
Host smart-6a868efa-5a99-4e70-9ea2-82f147596429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466780549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3466780549
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1603264255
Short name T141
Test name
Test status
Simulation time 26491640974 ps
CPU time 15.24 seconds
Started Jul 06 06:02:33 PM PDT 24
Finished Jul 06 06:02:49 PM PDT 24
Peak memory 200012 kb
Host smart-c94ffadf-5866-48e7-bb81-427a29a3676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603264255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1603264255
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.1685736653
Short name T329
Test name
Test status
Simulation time 378561893442 ps
CPU time 357.6 seconds
Started Jul 06 05:56:50 PM PDT 24
Finished Jul 06 06:02:48 PM PDT 24
Peak memory 199976 kb
Host smart-ea2fcd11-d234-4b26-9921-bfe580c43330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685736653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1685736653
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.4073115203
Short name T173
Test name
Test status
Simulation time 25532329933 ps
CPU time 19.57 seconds
Started Jul 06 06:02:30 PM PDT 24
Finished Jul 06 06:02:50 PM PDT 24
Peak memory 199912 kb
Host smart-680ce3c7-3d57-4a9d-aea3-086130449680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073115203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.4073115203
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1037537091
Short name T44
Test name
Test status
Simulation time 35817296069 ps
CPU time 62.14 seconds
Started Jul 06 06:00:13 PM PDT 24
Finished Jul 06 06:01:16 PM PDT 24
Peak memory 200008 kb
Host smart-254b4daa-e419-4fbc-97d7-d15a8604dc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037537091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1037537091
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2910005346
Short name T486
Test name
Test status
Simulation time 119591459276 ps
CPU time 65.21 seconds
Started Jul 06 06:01:18 PM PDT 24
Finished Jul 06 06:02:24 PM PDT 24
Peak memory 199932 kb
Host smart-09f00a3b-83b2-441c-a904-6f1f6a422e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910005346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2910005346
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.2045923116
Short name T179
Test name
Test status
Simulation time 287315512056 ps
CPU time 220.8 seconds
Started Jul 06 05:58:11 PM PDT 24
Finished Jul 06 06:01:52 PM PDT 24
Peak memory 199988 kb
Host smart-832e7e69-6ea2-4895-8fd1-f7bb8d7c6939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045923116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2045923116
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1035643110
Short name T99
Test name
Test status
Simulation time 136478364 ps
CPU time 0.99 seconds
Started Jul 06 04:52:45 PM PDT 24
Finished Jul 06 04:52:46 PM PDT 24
Peak memory 199872 kb
Host smart-accef4d8-97cd-455d-b5a8-e84f64c3f0f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035643110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1035643110
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1087011786
Short name T30
Test name
Test status
Simulation time 15556807010 ps
CPU time 26.6 seconds
Started Jul 06 06:01:41 PM PDT 24
Finished Jul 06 06:02:08 PM PDT 24
Peak memory 199948 kb
Host smart-8b53f2c2-9759-4a02-88f8-a06a1d5db640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087011786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1087011786
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1484163437
Short name T234
Test name
Test status
Simulation time 132723159671 ps
CPU time 21.65 seconds
Started Jul 06 06:01:41 PM PDT 24
Finished Jul 06 06:02:03 PM PDT 24
Peak memory 199868 kb
Host smart-03f919d9-9b2e-4837-9bca-d5b91d298cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484163437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1484163437
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1488700031
Short name T286
Test name
Test status
Simulation time 178724974642 ps
CPU time 19.75 seconds
Started Jul 06 06:02:01 PM PDT 24
Finished Jul 06 06:02:21 PM PDT 24
Peak memory 199972 kb
Host smart-728bf43f-b943-4710-afcc-0eeb75d2f0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488700031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1488700031
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.265063108
Short name T255
Test name
Test status
Simulation time 27820264643 ps
CPU time 25.98 seconds
Started Jul 06 05:57:18 PM PDT 24
Finished Jul 06 05:57:44 PM PDT 24
Peak memory 199856 kb
Host smart-c1db494c-3ab0-4da1-a447-965cc4128f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265063108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.265063108
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3770234993
Short name T182
Test name
Test status
Simulation time 55602778740 ps
CPU time 148.97 seconds
Started Jul 06 06:01:54 PM PDT 24
Finished Jul 06 06:04:23 PM PDT 24
Peak memory 199876 kb
Host smart-d4d29dc2-b3f4-4fdf-8b31-80605e121419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770234993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3770234993
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1169510415
Short name T244
Test name
Test status
Simulation time 30243334112 ps
CPU time 367.71 seconds
Started Jul 06 05:56:53 PM PDT 24
Finished Jul 06 06:03:01 PM PDT 24
Peak memory 216064 kb
Host smart-09cb0527-49c7-465a-953c-24bd82761d5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169510415 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1169510415
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3494849035
Short name T126
Test name
Test status
Simulation time 37816589272 ps
CPU time 54.5 seconds
Started Jul 06 06:02:07 PM PDT 24
Finished Jul 06 06:03:02 PM PDT 24
Peak memory 200016 kb
Host smart-a9e28cc2-80ad-4457-876b-c89be0582370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494849035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3494849035
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1808840362
Short name T584
Test name
Test status
Simulation time 276057185168 ps
CPU time 174.91 seconds
Started Jul 06 06:00:26 PM PDT 24
Finished Jul 06 06:03:21 PM PDT 24
Peak memory 199944 kb
Host smart-60502d7e-875c-4314-bf68-af25eba7e1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808840362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1808840362
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1882606465
Short name T38
Test name
Test status
Simulation time 47023509464 ps
CPU time 68.33 seconds
Started Jul 06 06:00:45 PM PDT 24
Finished Jul 06 06:01:54 PM PDT 24
Peak memory 199876 kb
Host smart-d4791d88-8789-4fc7-b93a-c75323bb7f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882606465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1882606465
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3617464658
Short name T213
Test name
Test status
Simulation time 159245402760 ps
CPU time 65.96 seconds
Started Jul 06 06:02:16 PM PDT 24
Finished Jul 06 06:03:23 PM PDT 24
Peak memory 199976 kb
Host smart-56468ebf-6a77-4630-b958-886bebd65eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617464658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3617464658
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.487215956
Short name T582
Test name
Test status
Simulation time 16947604716 ps
CPU time 28.04 seconds
Started Jul 06 06:01:17 PM PDT 24
Finished Jul 06 06:01:45 PM PDT 24
Peak memory 199912 kb
Host smart-5a57fef8-3e8c-41b1-a279-98f9a3b859c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487215956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.487215956
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.53466801
Short name T208
Test name
Test status
Simulation time 110168358228 ps
CPU time 29.87 seconds
Started Jul 06 06:01:22 PM PDT 24
Finished Jul 06 06:01:52 PM PDT 24
Peak memory 200000 kb
Host smart-764c45e0-57d6-4454-be33-dade55c6a24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53466801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.53466801
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2749880006
Short name T238
Test name
Test status
Simulation time 136143283629 ps
CPU time 28.59 seconds
Started Jul 06 06:01:25 PM PDT 24
Finished Jul 06 06:01:54 PM PDT 24
Peak memory 199972 kb
Host smart-ad9b12a8-34ca-4d96-8a2f-adec8d756b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749880006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2749880006
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2471143150
Short name T146
Test name
Test status
Simulation time 17912181529 ps
CPU time 23.79 seconds
Started Jul 06 06:01:34 PM PDT 24
Finished Jul 06 06:01:58 PM PDT 24
Peak memory 199988 kb
Host smart-343684f6-4623-4440-a285-37ed6e7bf23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471143150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2471143150
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1021056646
Short name T204
Test name
Test status
Simulation time 391464445927 ps
CPU time 33.12 seconds
Started Jul 06 06:02:09 PM PDT 24
Finished Jul 06 06:02:42 PM PDT 24
Peak memory 200032 kb
Host smart-1f5ac539-3289-4924-9070-940e0ea33a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021056646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1021056646
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1461253849
Short name T193
Test name
Test status
Simulation time 42982917612 ps
CPU time 66.32 seconds
Started Jul 06 06:02:24 PM PDT 24
Finished Jul 06 06:03:30 PM PDT 24
Peak memory 199900 kb
Host smart-3d6b8935-998e-4e2d-ba36-213c5fce86e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461253849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1461253849
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.976794906
Short name T246
Test name
Test status
Simulation time 55251204914 ps
CPU time 11.11 seconds
Started Jul 06 06:01:07 PM PDT 24
Finished Jul 06 06:01:19 PM PDT 24
Peak memory 199992 kb
Host smart-d6b6907d-070d-40d9-864f-e228bb95dd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976794906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.976794906
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3629570927
Short name T131
Test name
Test status
Simulation time 81452949 ps
CPU time 1.27 seconds
Started Jul 06 04:52:22 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 200200 kb
Host smart-ac8369ee-de4e-4396-9be2-bc136b936ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629570927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3629570927
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2730088668
Short name T224
Test name
Test status
Simulation time 81829360938 ps
CPU time 149.33 seconds
Started Jul 06 05:57:18 PM PDT 24
Finished Jul 06 05:59:48 PM PDT 24
Peak memory 199928 kb
Host smart-9cce979e-12fe-408d-bbd5-16af9b3d621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730088668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2730088668
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3246766687
Short name T212
Test name
Test status
Simulation time 60922059473 ps
CPU time 29.22 seconds
Started Jul 06 06:01:21 PM PDT 24
Finished Jul 06 06:01:51 PM PDT 24
Peak memory 199840 kb
Host smart-02616af4-aa08-4801-a8cd-12e6848f7edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246766687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3246766687
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3575355830
Short name T36
Test name
Test status
Simulation time 59244371945 ps
CPU time 24.66 seconds
Started Jul 06 06:01:24 PM PDT 24
Finished Jul 06 06:01:49 PM PDT 24
Peak memory 200016 kb
Host smart-3616add6-cb3a-4cbc-ac68-6fb666c16fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575355830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3575355830
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1000141044
Short name T252
Test name
Test status
Simulation time 148634114691 ps
CPU time 65.06 seconds
Started Jul 06 05:57:28 PM PDT 24
Finished Jul 06 05:58:33 PM PDT 24
Peak memory 199956 kb
Host smart-a58c2dca-0769-44e7-8d29-ffbafb50298b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000141044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1000141044
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1810173716
Short name T254
Test name
Test status
Simulation time 199766571171 ps
CPU time 126.96 seconds
Started Jul 06 06:01:24 PM PDT 24
Finished Jul 06 06:03:32 PM PDT 24
Peak memory 200012 kb
Host smart-d2d62ca3-3ecd-4d80-bace-a5ea29bfb59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810173716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1810173716
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.771720839
Short name T217
Test name
Test status
Simulation time 244125099302 ps
CPU time 118.94 seconds
Started Jul 06 06:01:29 PM PDT 24
Finished Jul 06 06:03:28 PM PDT 24
Peak memory 199976 kb
Host smart-1ec8ab04-64e8-4b6f-8580-df509002f42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771720839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.771720839
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1592626153
Short name T241
Test name
Test status
Simulation time 118931919618 ps
CPU time 19.47 seconds
Started Jul 06 06:01:31 PM PDT 24
Finished Jul 06 06:01:51 PM PDT 24
Peak memory 199928 kb
Host smart-96cd53af-9688-42c8-8419-4a1b081530ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592626153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1592626153
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1459772705
Short name T148
Test name
Test status
Simulation time 51714838325 ps
CPU time 20.66 seconds
Started Jul 06 06:01:40 PM PDT 24
Finished Jul 06 06:02:01 PM PDT 24
Peak memory 200000 kb
Host smart-0b966d17-7d2a-4042-bba3-d4a0330ccd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459772705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1459772705
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2770216006
Short name T445
Test name
Test status
Simulation time 42291295948 ps
CPU time 64.15 seconds
Started Jul 06 05:57:46 PM PDT 24
Finished Jul 06 05:58:51 PM PDT 24
Peak memory 199892 kb
Host smart-29b8167c-95a2-40b1-83a9-183b961121a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770216006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2770216006
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3310169045
Short name T183
Test name
Test status
Simulation time 190681476746 ps
CPU time 123.43 seconds
Started Jul 06 06:01:41 PM PDT 24
Finished Jul 06 06:03:45 PM PDT 24
Peak memory 199928 kb
Host smart-3b8347dd-d322-4229-a1f8-4a958b5b32d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310169045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3310169045
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2605727300
Short name T230
Test name
Test status
Simulation time 141886719729 ps
CPU time 193.45 seconds
Started Jul 06 06:01:45 PM PDT 24
Finished Jul 06 06:04:59 PM PDT 24
Peak memory 200012 kb
Host smart-74044829-ca6f-4d09-a96c-32de31c28531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605727300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2605727300
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3149244780
Short name T198
Test name
Test status
Simulation time 80576571303 ps
CPU time 115.6 seconds
Started Jul 06 06:01:45 PM PDT 24
Finished Jul 06 06:03:41 PM PDT 24
Peak memory 199652 kb
Host smart-62e96a1d-6dba-4812-a77d-aaed97364b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149244780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3149244780
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.534219573
Short name T251
Test name
Test status
Simulation time 194069107771 ps
CPU time 88.91 seconds
Started Jul 06 06:02:12 PM PDT 24
Finished Jul 06 06:03:41 PM PDT 24
Peak memory 199944 kb
Host smart-2232c3d5-0066-465a-bb2b-c09af9b70c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534219573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.534219573
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2701896079
Short name T222
Test name
Test status
Simulation time 146320432600 ps
CPU time 109.13 seconds
Started Jul 06 06:02:10 PM PDT 24
Finished Jul 06 06:03:59 PM PDT 24
Peak memory 199900 kb
Host smart-c85d1699-f16e-460b-87a4-07f15ec684aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701896079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2701896079
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1255183206
Short name T253
Test name
Test status
Simulation time 24998857140 ps
CPU time 46.25 seconds
Started Jul 06 06:02:11 PM PDT 24
Finished Jul 06 06:02:57 PM PDT 24
Peak memory 199900 kb
Host smart-f14a680a-d295-4bc5-b2d9-4608eeaff027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255183206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1255183206
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.4138573588
Short name T228
Test name
Test status
Simulation time 126145258744 ps
CPU time 19.54 seconds
Started Jul 06 06:02:25 PM PDT 24
Finished Jul 06 06:02:45 PM PDT 24
Peak memory 199984 kb
Host smart-3eec3737-9137-4c2f-b03e-c8b52e6deea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138573588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.4138573588
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1525011983
Short name T261
Test name
Test status
Simulation time 27168586549 ps
CPU time 9.92 seconds
Started Jul 06 06:02:31 PM PDT 24
Finished Jul 06 06:02:42 PM PDT 24
Peak memory 199812 kb
Host smart-4f8d21f4-7539-4409-bc09-9b8d50ca5056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525011983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1525011983
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1791752532
Short name T259
Test name
Test status
Simulation time 25381709813 ps
CPU time 28.96 seconds
Started Jul 06 06:02:35 PM PDT 24
Finished Jul 06 06:03:04 PM PDT 24
Peak memory 199968 kb
Host smart-53d3a4ca-798e-4b1e-a5a1-b5a7c85f2cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791752532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1791752532
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1352619393
Short name T258
Test name
Test status
Simulation time 43129756676 ps
CPU time 11.39 seconds
Started Jul 06 06:02:36 PM PDT 24
Finished Jul 06 06:02:48 PM PDT 24
Peak memory 199992 kb
Host smart-a51690d1-7221-4ce5-add1-3f46a2b079ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352619393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1352619393
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1910125942
Short name T260
Test name
Test status
Simulation time 78840790955 ps
CPU time 482.72 seconds
Started Jul 06 05:56:59 PM PDT 24
Finished Jul 06 06:05:02 PM PDT 24
Peak memory 208664 kb
Host smart-5d1b645f-b632-4c97-a787-1dd73aa0b8d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910125942 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1910125942
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2265142062
Short name T175
Test name
Test status
Simulation time 102884948089 ps
CPU time 43.45 seconds
Started Jul 06 06:00:51 PM PDT 24
Finished Jul 06 06:01:34 PM PDT 24
Peak memory 199924 kb
Host smart-85a3e123-42ce-4f00-a056-4453a491f837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265142062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2265142062
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3459355942
Short name T67
Test name
Test status
Simulation time 47736234 ps
CPU time 0.76 seconds
Started Jul 06 04:52:21 PM PDT 24
Finished Jul 06 04:52:22 PM PDT 24
Peak memory 197008 kb
Host smart-b3db0cb2-2564-46c9-8d7d-761c0c6b9b06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459355942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3459355942
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2441793960
Short name T1183
Test name
Test status
Simulation time 113908667 ps
CPU time 2.2 seconds
Started Jul 06 04:52:25 PM PDT 24
Finished Jul 06 04:52:28 PM PDT 24
Peak memory 198336 kb
Host smart-d5a4c24b-ee4d-47db-868c-5e2fdfece2ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441793960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2441793960
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.893614986
Short name T1291
Test name
Test status
Simulation time 15316797 ps
CPU time 0.66 seconds
Started Jul 06 04:52:23 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 196172 kb
Host smart-b6f9d2cf-5820-4b2b-a4e8-4e803140cfcd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893614986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.893614986
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.865348274
Short name T1228
Test name
Test status
Simulation time 78139005 ps
CPU time 1.01 seconds
Started Jul 06 04:52:23 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 200632 kb
Host smart-1ed03d83-7fa3-47ee-a107-70d9d09352ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865348274 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.865348274
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1186988905
Short name T1284
Test name
Test status
Simulation time 15751957 ps
CPU time 0.6 seconds
Started Jul 06 04:52:22 PM PDT 24
Finished Jul 06 04:52:23 PM PDT 24
Peak memory 196184 kb
Host smart-dcf76586-9060-4ed1-8d35-9560bfd5de01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186988905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1186988905
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.720215697
Short name T1212
Test name
Test status
Simulation time 26130269 ps
CPU time 0.59 seconds
Started Jul 06 04:52:25 PM PDT 24
Finished Jul 06 04:52:26 PM PDT 24
Peak memory 195176 kb
Host smart-05acc7a7-defb-46b4-aabd-10d87d938afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720215697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.720215697
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3889570903
Short name T1304
Test name
Test status
Simulation time 106534479 ps
CPU time 0.63 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:25 PM PDT 24
Peak memory 196128 kb
Host smart-d0fff1ff-eb34-4dac-bdb9-a76142908884
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889570903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3889570903
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.243790226
Short name T1233
Test name
Test status
Simulation time 144597125 ps
CPU time 1.93 seconds
Started Jul 06 04:52:22 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 200744 kb
Host smart-93735d63-ccd4-4f4d-a18a-243e29b16c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243790226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.243790226
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1238144009
Short name T1270
Test name
Test status
Simulation time 18353081 ps
CPU time 0.77 seconds
Started Jul 06 04:52:23 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 197496 kb
Host smart-f0a8f023-8b34-4ba4-8309-c1e9a3ef9b37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238144009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1238144009
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2487014225
Short name T1239
Test name
Test status
Simulation time 63598802 ps
CPU time 1.4 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:26 PM PDT 24
Peak memory 198488 kb
Host smart-236bde1b-04ed-467c-9f02-ab9a58f6af64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487014225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2487014225
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3275251113
Short name T1259
Test name
Test status
Simulation time 48419817 ps
CPU time 0.61 seconds
Started Jul 06 04:52:23 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 196172 kb
Host smart-75cd4068-3bfc-4f94-9f6b-3ac4d11f32db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275251113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3275251113
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3870802061
Short name T1283
Test name
Test status
Simulation time 22732991 ps
CPU time 0.72 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:25 PM PDT 24
Peak memory 199044 kb
Host smart-c1df0aca-8dc6-46f4-90d5-7ce33d101005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870802061 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3870802061
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.699450846
Short name T1186
Test name
Test status
Simulation time 35203390 ps
CPU time 0.59 seconds
Started Jul 06 04:52:25 PM PDT 24
Finished Jul 06 04:52:26 PM PDT 24
Peak memory 196204 kb
Host smart-af8fbf7d-4d85-4ada-9490-a9f68935d81e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699450846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.699450846
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3598809514
Short name T1303
Test name
Test status
Simulation time 12610326 ps
CPU time 0.59 seconds
Started Jul 06 04:52:23 PM PDT 24
Finished Jul 06 04:52:25 PM PDT 24
Peak memory 195052 kb
Host smart-3f4d5c4b-1df1-4213-8cd7-8ca5c47a3ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598809514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3598809514
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3001420186
Short name T1274
Test name
Test status
Simulation time 31427046 ps
CPU time 0.73 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:25 PM PDT 24
Peak memory 197684 kb
Host smart-f0471278-5873-4b01-bb14-dde0cb3bee5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001420186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3001420186
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2016527172
Short name T1249
Test name
Test status
Simulation time 125593389 ps
CPU time 1.35 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:26 PM PDT 24
Peak memory 200820 kb
Host smart-79bf1866-c9ab-4422-adb2-25f4b0af500c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016527172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2016527172
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3987402178
Short name T100
Test name
Test status
Simulation time 167026937 ps
CPU time 0.97 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:25 PM PDT 24
Peak memory 199524 kb
Host smart-c19f8f56-47b7-4450-9197-a75b00636d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987402178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3987402178
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1085694784
Short name T1269
Test name
Test status
Simulation time 22755481 ps
CPU time 0.76 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 200036 kb
Host smart-d4bb4838-9852-42c7-a14c-0ed5bc29cf15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085694784 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1085694784
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.440135462
Short name T1237
Test name
Test status
Simulation time 27598120 ps
CPU time 0.64 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:36 PM PDT 24
Peak memory 196548 kb
Host smart-aafc9dd6-3266-44fd-828e-a4e6a3c7c37b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440135462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.440135462
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3583126846
Short name T1197
Test name
Test status
Simulation time 11898063 ps
CPU time 0.57 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 195048 kb
Host smart-06a94802-d8ab-444e-ab31-bde69c5d2165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583126846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3583126846
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.738689389
Short name T1246
Test name
Test status
Simulation time 86244820 ps
CPU time 1.8 seconds
Started Jul 06 04:52:36 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 200792 kb
Host smart-d0c37148-877a-4351-84b6-ae0c2f684cff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738689389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.738689389
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2041403357
Short name T102
Test name
Test status
Simulation time 54228405 ps
CPU time 1 seconds
Started Jul 06 04:52:33 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 199660 kb
Host smart-01afc389-b6bf-42f8-90d1-441fb34ac7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041403357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2041403357
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2775403443
Short name T1184
Test name
Test status
Simulation time 93681951 ps
CPU time 0.86 seconds
Started Jul 06 04:52:36 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 200584 kb
Host smart-d905ccd1-68b1-44aa-a665-669206f27b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775403443 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2775403443
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.695074165
Short name T77
Test name
Test status
Simulation time 34870398 ps
CPU time 0.61 seconds
Started Jul 06 04:52:38 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 196192 kb
Host smart-975bff23-d21b-479f-9684-fcb722c8c383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695074165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.695074165
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2207386715
Short name T1292
Test name
Test status
Simulation time 15244692 ps
CPU time 0.56 seconds
Started Jul 06 04:52:33 PM PDT 24
Finished Jul 06 04:52:34 PM PDT 24
Peak memory 195116 kb
Host smart-fb3a637c-02c6-4456-972a-dd03892b4109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207386715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2207386715
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2427693523
Short name T1265
Test name
Test status
Simulation time 34748416 ps
CPU time 0.78 seconds
Started Jul 06 04:52:38 PM PDT 24
Finished Jul 06 04:52:40 PM PDT 24
Peak memory 196684 kb
Host smart-c3601fcd-18ee-4827-8872-7680653c6d17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427693523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2427693523
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.269392985
Short name T1201
Test name
Test status
Simulation time 98079351 ps
CPU time 1.1 seconds
Started Jul 06 04:52:33 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 200520 kb
Host smart-75abf524-6c6b-494a-9070-f03445d1cfa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269392985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.269392985
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.14076346
Short name T132
Test name
Test status
Simulation time 222760983 ps
CPU time 0.97 seconds
Started Jul 06 04:52:36 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 199496 kb
Host smart-47dd8bcd-cee0-4693-9a71-f7ab8dfb62a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14076346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.14076346
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2280874412
Short name T1309
Test name
Test status
Simulation time 65589570 ps
CPU time 0.88 seconds
Started Jul 06 04:52:36 PM PDT 24
Finished Jul 06 04:52:37 PM PDT 24
Peak memory 200608 kb
Host smart-92e874ae-6c37-4426-916b-2ace7a5cb505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280874412 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2280874412
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3262034017
Short name T87
Test name
Test status
Simulation time 12397469 ps
CPU time 0.62 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 196220 kb
Host smart-3517cc50-bd76-4baf-9b2e-868838548643
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262034017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3262034017
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1409888383
Short name T1214
Test name
Test status
Simulation time 10658130 ps
CPU time 0.55 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 195144 kb
Host smart-5c584c5b-63e7-40e7-9d47-b7e348d5e284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409888383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1409888383
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4242963565
Short name T1250
Test name
Test status
Simulation time 34800271 ps
CPU time 0.68 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 197316 kb
Host smart-5d476f73-8767-43bb-8db5-ffd985ddce01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242963565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.4242963565
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.407821249
Short name T1311
Test name
Test status
Simulation time 118530020 ps
CPU time 1.5 seconds
Started Jul 06 04:52:39 PM PDT 24
Finished Jul 06 04:52:41 PM PDT 24
Peak memory 200780 kb
Host smart-28791b73-dd93-4b80-b84e-bd0ae42db345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407821249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.407821249
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.956638248
Short name T101
Test name
Test status
Simulation time 85355216 ps
CPU time 1.24 seconds
Started Jul 06 04:52:33 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 199716 kb
Host smart-edf79452-2f5a-4ada-a2e7-d5ac8cca777b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956638248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.956638248
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2220188531
Short name T1244
Test name
Test status
Simulation time 47268069 ps
CPU time 1.26 seconds
Started Jul 06 04:52:38 PM PDT 24
Finished Jul 06 04:52:40 PM PDT 24
Peak memory 200704 kb
Host smart-630b2be3-6201-4705-a489-44c46afeec8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220188531 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2220188531
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3451014323
Short name T1310
Test name
Test status
Simulation time 17819525 ps
CPU time 0.61 seconds
Started Jul 06 04:52:39 PM PDT 24
Finished Jul 06 04:52:40 PM PDT 24
Peak memory 196176 kb
Host smart-7e2ce546-c3f9-4e17-8798-dc2f94894718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451014323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3451014323
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1747460283
Short name T1209
Test name
Test status
Simulation time 97735648 ps
CPU time 0.57 seconds
Started Jul 06 04:52:38 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 195220 kb
Host smart-3b75020a-3b37-40de-b16e-bd269cdabd48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747460283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1747460283
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3983854486
Short name T1247
Test name
Test status
Simulation time 36355039 ps
CPU time 0.88 seconds
Started Jul 06 04:52:36 PM PDT 24
Finished Jul 06 04:52:37 PM PDT 24
Peak memory 196724 kb
Host smart-57e24566-d06e-4645-9bb3-fdfa5117a5ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983854486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3983854486
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.545677938
Short name T1213
Test name
Test status
Simulation time 123590168 ps
CPU time 1.18 seconds
Started Jul 06 04:52:36 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 200816 kb
Host smart-ca08455b-5c97-4bff-9eb4-eab7b16ea9de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545677938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.545677938
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3161785866
Short name T97
Test name
Test status
Simulation time 88822912 ps
CPU time 1 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 199332 kb
Host smart-2284b58e-b516-43d5-80d3-0832f98312dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161785866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3161785866
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3337070001
Short name T1229
Test name
Test status
Simulation time 32954033 ps
CPU time 0.76 seconds
Started Jul 06 04:52:46 PM PDT 24
Finished Jul 06 04:52:47 PM PDT 24
Peak memory 199896 kb
Host smart-9b422fd9-c89d-4474-982b-91f9c39cfc4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337070001 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3337070001
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2304214901
Short name T70
Test name
Test status
Simulation time 72626227 ps
CPU time 0.61 seconds
Started Jul 06 04:52:38 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 195832 kb
Host smart-af31b532-d630-4708-83d9-f224b3871ac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304214901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2304214901
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3115018053
Short name T1298
Test name
Test status
Simulation time 10701065 ps
CPU time 0.58 seconds
Started Jul 06 04:52:36 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 195180 kb
Host smart-daa138f3-9fc9-4f85-b0a4-0eea6907772a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115018053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3115018053
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.172379255
Short name T1281
Test name
Test status
Simulation time 19220655 ps
CPU time 0.71 seconds
Started Jul 06 04:52:46 PM PDT 24
Finished Jul 06 04:52:47 PM PDT 24
Peak memory 197568 kb
Host smart-eaf23010-f604-44a7-becd-392b1d27049f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172379255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.172379255
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1734124157
Short name T1308
Test name
Test status
Simulation time 65904890 ps
CPU time 1.61 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 200772 kb
Host smart-03522a3d-502b-4d2d-a130-35283abe1c36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734124157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1734124157
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3677784720
Short name T1232
Test name
Test status
Simulation time 220243284 ps
CPU time 0.96 seconds
Started Jul 06 04:52:38 PM PDT 24
Finished Jul 06 04:52:40 PM PDT 24
Peak memory 199820 kb
Host smart-d7f21fbf-856d-4ad9-99ba-13332297cc4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677784720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3677784720
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.551051392
Short name T1203
Test name
Test status
Simulation time 17985101 ps
CPU time 0.68 seconds
Started Jul 06 04:52:41 PM PDT 24
Finished Jul 06 04:52:42 PM PDT 24
Peak memory 198240 kb
Host smart-21d140d4-2279-45b3-9a51-1d3a3c4ee814
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551051392 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.551051392
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.310221395
Short name T68
Test name
Test status
Simulation time 13953220 ps
CPU time 0.59 seconds
Started Jul 06 04:52:50 PM PDT 24
Finished Jul 06 04:52:51 PM PDT 24
Peak memory 196088 kb
Host smart-ab17737d-8cb5-4d20-9fc9-da73260ec365
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310221395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.310221395
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.15366494
Short name T1205
Test name
Test status
Simulation time 33979852 ps
CPU time 0.56 seconds
Started Jul 06 04:52:44 PM PDT 24
Finished Jul 06 04:52:45 PM PDT 24
Peak memory 195112 kb
Host smart-9aa1e674-37dc-4477-aae4-55a9bf3878f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15366494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.15366494
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3810568878
Short name T94
Test name
Test status
Simulation time 30307867 ps
CPU time 0.7 seconds
Started Jul 06 04:52:50 PM PDT 24
Finished Jul 06 04:52:51 PM PDT 24
Peak memory 196440 kb
Host smart-97bc13d2-2231-46ad-a1d4-d443f2ce3580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810568878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3810568878
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1765285557
Short name T1295
Test name
Test status
Simulation time 381840993 ps
CPU time 1.85 seconds
Started Jul 06 04:52:46 PM PDT 24
Finished Jul 06 04:52:49 PM PDT 24
Peak memory 200740 kb
Host smart-08c112ee-a85b-4293-88c2-e58ca3d76e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765285557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1765285557
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.563017365
Short name T1206
Test name
Test status
Simulation time 122632690 ps
CPU time 0.79 seconds
Started Jul 06 04:52:44 PM PDT 24
Finished Jul 06 04:52:45 PM PDT 24
Peak memory 200616 kb
Host smart-5d9ae146-f53c-4840-ad8e-e7d0314dbbaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563017365 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.563017365
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2740759920
Short name T1271
Test name
Test status
Simulation time 57195023 ps
CPU time 0.61 seconds
Started Jul 06 04:52:47 PM PDT 24
Finished Jul 06 04:52:49 PM PDT 24
Peak memory 196144 kb
Host smart-f0b954df-df28-4100-a3dc-182109324479
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740759920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2740759920
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2231483830
Short name T1300
Test name
Test status
Simulation time 50440934 ps
CPU time 0.58 seconds
Started Jul 06 04:52:52 PM PDT 24
Finished Jul 06 04:52:53 PM PDT 24
Peak memory 195060 kb
Host smart-f53f4378-90d3-4698-b13e-4f307d4bf2d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231483830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2231483830
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1478792834
Short name T1279
Test name
Test status
Simulation time 63858753 ps
CPU time 0.69 seconds
Started Jul 06 04:52:44 PM PDT 24
Finished Jul 06 04:52:45 PM PDT 24
Peak memory 197368 kb
Host smart-08f2e59d-6acc-4a75-8c5d-f2b646ebd302
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478792834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1478792834
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2337774255
Short name T1260
Test name
Test status
Simulation time 228804362 ps
CPU time 1.61 seconds
Started Jul 06 04:52:42 PM PDT 24
Finished Jul 06 04:52:44 PM PDT 24
Peak memory 200816 kb
Host smart-20b985e3-71cd-4cd7-bc4c-010d4572addc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337774255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2337774255
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3632178140
Short name T1251
Test name
Test status
Simulation time 83428230 ps
CPU time 1.38 seconds
Started Jul 06 04:52:44 PM PDT 24
Finished Jul 06 04:52:46 PM PDT 24
Peak memory 200148 kb
Host smart-12d31fab-b8aa-47f2-a563-175ca7403786
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632178140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3632178140
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.247370991
Short name T1264
Test name
Test status
Simulation time 46611272 ps
CPU time 0.87 seconds
Started Jul 06 04:52:47 PM PDT 24
Finished Jul 06 04:52:48 PM PDT 24
Peak memory 200500 kb
Host smart-4a3f0bf6-6693-40bf-9ac3-85dc44cb2ff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247370991 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.247370991
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2634152071
Short name T1305
Test name
Test status
Simulation time 35863803 ps
CPU time 0.66 seconds
Started Jul 06 04:52:44 PM PDT 24
Finished Jul 06 04:52:45 PM PDT 24
Peak memory 196324 kb
Host smart-628d8b81-324e-486f-850b-e6710b942b54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634152071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2634152071
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3563625139
Short name T1267
Test name
Test status
Simulation time 45197431 ps
CPU time 0.6 seconds
Started Jul 06 04:52:47 PM PDT 24
Finished Jul 06 04:52:48 PM PDT 24
Peak memory 195192 kb
Host smart-b57313f9-cac2-4f3a-83e7-a61315d2d4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563625139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3563625139
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3837606509
Short name T1290
Test name
Test status
Simulation time 49515906 ps
CPU time 0.73 seconds
Started Jul 06 04:52:49 PM PDT 24
Finished Jul 06 04:52:50 PM PDT 24
Peak memory 196824 kb
Host smart-f59daa6d-859f-420e-bae0-a2dbdda3aacb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837606509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3837606509
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.450839228
Short name T1301
Test name
Test status
Simulation time 16808367 ps
CPU time 0.9 seconds
Started Jul 06 04:52:51 PM PDT 24
Finished Jul 06 04:52:53 PM PDT 24
Peak memory 200600 kb
Host smart-437dbf6f-e697-4d1b-9c67-cd61be32ff95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450839228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.450839228
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3021158800
Short name T1276
Test name
Test status
Simulation time 66829237 ps
CPU time 0.94 seconds
Started Jul 06 04:52:42 PM PDT 24
Finished Jul 06 04:52:43 PM PDT 24
Peak memory 199644 kb
Host smart-83ffa1b3-e541-45ab-9883-650faca2e6cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021158800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3021158800
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3252669077
Short name T1185
Test name
Test status
Simulation time 81686270 ps
CPU time 0.76 seconds
Started Jul 06 04:52:50 PM PDT 24
Finished Jul 06 04:52:51 PM PDT 24
Peak memory 199644 kb
Host smart-de98e214-ad61-4643-b8a0-55dd2bf15159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252669077 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3252669077
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2616864569
Short name T69
Test name
Test status
Simulation time 34906542 ps
CPU time 0.58 seconds
Started Jul 06 04:52:47 PM PDT 24
Finished Jul 06 04:52:48 PM PDT 24
Peak memory 196136 kb
Host smart-fa669ffa-27aa-4597-b708-35fe95431dd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616864569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2616864569
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3569888547
Short name T1277
Test name
Test status
Simulation time 18043273 ps
CPU time 0.58 seconds
Started Jul 06 04:52:47 PM PDT 24
Finished Jul 06 04:52:48 PM PDT 24
Peak memory 195208 kb
Host smart-cf26d7a5-2deb-48db-9927-7cc8b471f449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569888547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3569888547
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3815546804
Short name T92
Test name
Test status
Simulation time 529638199 ps
CPU time 0.78 seconds
Started Jul 06 04:52:48 PM PDT 24
Finished Jul 06 04:52:49 PM PDT 24
Peak memory 197900 kb
Host smart-e82e5ccc-d4eb-4f14-9972-27e60436e587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815546804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3815546804
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3832378213
Short name T1302
Test name
Test status
Simulation time 32672653 ps
CPU time 1.63 seconds
Started Jul 06 04:52:57 PM PDT 24
Finished Jul 06 04:52:59 PM PDT 24
Peak memory 200768 kb
Host smart-ddb9a538-55fe-4a72-9a1c-88eb92150da2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832378213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3832378213
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2317835062
Short name T104
Test name
Test status
Simulation time 538030796 ps
CPU time 1.01 seconds
Started Jul 06 04:52:46 PM PDT 24
Finished Jul 06 04:52:47 PM PDT 24
Peak memory 199860 kb
Host smart-4d34fca3-0bdb-4071-a04c-5726d9a06ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317835062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2317835062
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2421202064
Short name T1195
Test name
Test status
Simulation time 34868744 ps
CPU time 0.89 seconds
Started Jul 06 04:52:50 PM PDT 24
Finished Jul 06 04:52:52 PM PDT 24
Peak memory 200480 kb
Host smart-1182dec0-7207-44e1-8b6f-01bc060c3508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421202064 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2421202064
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.304444145
Short name T91
Test name
Test status
Simulation time 72599150 ps
CPU time 0.58 seconds
Started Jul 06 04:52:47 PM PDT 24
Finished Jul 06 04:52:48 PM PDT 24
Peak memory 196128 kb
Host smart-f5c5e675-df7f-432f-b6fd-26669480a30e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304444145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.304444145
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3013681341
Short name T1261
Test name
Test status
Simulation time 15300257 ps
CPU time 0.59 seconds
Started Jul 06 04:52:48 PM PDT 24
Finished Jul 06 04:52:50 PM PDT 24
Peak memory 195108 kb
Host smart-a738fc4c-7af7-4ecc-bda5-07d2d8093d22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013681341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3013681341
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1189027057
Short name T1275
Test name
Test status
Simulation time 25965813 ps
CPU time 0.68 seconds
Started Jul 06 04:52:45 PM PDT 24
Finished Jul 06 04:52:46 PM PDT 24
Peak memory 197636 kb
Host smart-2859f1c9-fb67-400b-8ef2-83030b22e407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189027057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1189027057
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.836713937
Short name T1217
Test name
Test status
Simulation time 61471717 ps
CPU time 1.41 seconds
Started Jul 06 04:52:51 PM PDT 24
Finished Jul 06 04:52:53 PM PDT 24
Peak memory 200756 kb
Host smart-4b3d8075-ae39-447f-a17c-76e3285a453c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836713937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.836713937
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2381253417
Short name T1235
Test name
Test status
Simulation time 167869565 ps
CPU time 0.87 seconds
Started Jul 06 04:52:46 PM PDT 24
Finished Jul 06 04:52:48 PM PDT 24
Peak memory 199600 kb
Host smart-b7b1f479-0db8-4c8f-a34c-f016651ee851
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381253417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2381253417
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.413604918
Short name T1238
Test name
Test status
Simulation time 89324814 ps
CPU time 0.8 seconds
Started Jul 06 04:52:23 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 197152 kb
Host smart-da6939a6-b544-434d-87fc-e39f2bdc852b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413604918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.413604918
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1829166101
Short name T1296
Test name
Test status
Simulation time 359943649 ps
CPU time 1.5 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:26 PM PDT 24
Peak memory 198592 kb
Host smart-140f63f9-c723-4b3a-9bf4-a4df803b767d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829166101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1829166101
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1222399372
Short name T1255
Test name
Test status
Simulation time 11858026 ps
CPU time 0.59 seconds
Started Jul 06 04:52:23 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 196064 kb
Host smart-b79c1cd5-5ed7-4e53-a0d3-a227cd8dd8db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222399372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1222399372
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3868750956
Short name T1221
Test name
Test status
Simulation time 216141369 ps
CPU time 1.06 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 200632 kb
Host smart-09e24c64-0148-4218-b755-614d7fd21999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868750956 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3868750956
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.348516693
Short name T90
Test name
Test status
Simulation time 25051567 ps
CPU time 0.6 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:25 PM PDT 24
Peak memory 196136 kb
Host smart-174f06f6-5c70-4f8b-bd64-6e315511b6ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348516693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.348516693
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2291950537
Short name T1256
Test name
Test status
Simulation time 26776986 ps
CPU time 0.58 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:25 PM PDT 24
Peak memory 195148 kb
Host smart-5496d196-347d-4498-93a9-717e9b9e9ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291950537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2291950537
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2061445533
Short name T1262
Test name
Test status
Simulation time 50193457 ps
CPU time 0.76 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:25 PM PDT 24
Peak memory 197676 kb
Host smart-9229ff35-5368-44e2-809a-dc2d167df8be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061445533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2061445533
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2814017233
Short name T1289
Test name
Test status
Simulation time 795046817 ps
CPU time 1.82 seconds
Started Jul 06 04:52:24 PM PDT 24
Finished Jul 06 04:52:27 PM PDT 24
Peak memory 200760 kb
Host smart-16eef19e-b84b-4d19-8b8a-31e4d4cab0c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814017233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2814017233
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.766694078
Short name T1299
Test name
Test status
Simulation time 150136715 ps
CPU time 0.95 seconds
Started Jul 06 04:52:23 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 199660 kb
Host smart-05999647-8aa0-4c31-838a-03cc47f34f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766694078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.766694078
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1802440251
Short name T1297
Test name
Test status
Simulation time 89639265 ps
CPU time 0.58 seconds
Started Jul 06 04:52:46 PM PDT 24
Finished Jul 06 04:52:47 PM PDT 24
Peak memory 195152 kb
Host smart-a6f8d699-1c33-42b3-be55-3c2d594dd29b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802440251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1802440251
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1323202675
Short name T1204
Test name
Test status
Simulation time 35568874 ps
CPU time 0.58 seconds
Started Jul 06 04:52:42 PM PDT 24
Finished Jul 06 04:52:43 PM PDT 24
Peak memory 195120 kb
Host smart-49ccdf2f-2aa4-42ad-914d-c61de36b8b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323202675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1323202675
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3491739805
Short name T1191
Test name
Test status
Simulation time 14420534 ps
CPU time 0.56 seconds
Started Jul 06 04:52:49 PM PDT 24
Finished Jul 06 04:52:50 PM PDT 24
Peak memory 195140 kb
Host smart-5a6ac24d-78fe-4926-bdcf-a163da1b1cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491739805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3491739805
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2375855613
Short name T1231
Test name
Test status
Simulation time 79530593 ps
CPU time 0.58 seconds
Started Jul 06 04:52:47 PM PDT 24
Finished Jul 06 04:52:48 PM PDT 24
Peak memory 195220 kb
Host smart-31a47b92-e3c4-4bdc-a450-c34122e05415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375855613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2375855613
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3087072205
Short name T1208
Test name
Test status
Simulation time 15300422 ps
CPU time 0.58 seconds
Started Jul 06 04:52:47 PM PDT 24
Finished Jul 06 04:52:53 PM PDT 24
Peak memory 195052 kb
Host smart-0c6b1113-2954-49e7-afb9-f2b7d7281ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087072205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3087072205
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2382740204
Short name T1216
Test name
Test status
Simulation time 39015322 ps
CPU time 0.56 seconds
Started Jul 06 04:52:48 PM PDT 24
Finished Jul 06 04:52:49 PM PDT 24
Peak memory 195040 kb
Host smart-23e2bab9-8e68-4ace-95fe-576c48a458fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382740204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2382740204
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2699192910
Short name T1218
Test name
Test status
Simulation time 37574442 ps
CPU time 0.58 seconds
Started Jul 06 04:53:02 PM PDT 24
Finished Jul 06 04:53:03 PM PDT 24
Peak memory 195144 kb
Host smart-a40c0e53-9862-492d-8105-0957965faeac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699192910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2699192910
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1511199767
Short name T1190
Test name
Test status
Simulation time 36239515 ps
CPU time 0.59 seconds
Started Jul 06 04:52:52 PM PDT 24
Finished Jul 06 04:52:53 PM PDT 24
Peak memory 195064 kb
Host smart-e8c3a7d5-39c9-45b2-a4c4-97550cba1baa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511199767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1511199767
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1472392857
Short name T1194
Test name
Test status
Simulation time 44532346 ps
CPU time 0.57 seconds
Started Jul 06 04:52:43 PM PDT 24
Finished Jul 06 04:52:43 PM PDT 24
Peak memory 195096 kb
Host smart-56c1d0c5-6a3a-4f2f-9622-28722eff1f45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472392857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1472392857
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.711068176
Short name T1196
Test name
Test status
Simulation time 12864602 ps
CPU time 0.56 seconds
Started Jul 06 04:52:49 PM PDT 24
Finished Jul 06 04:52:50 PM PDT 24
Peak memory 194976 kb
Host smart-a3c1727c-5694-485b-8de4-2de8cb67193f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711068176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.711068176
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.764096270
Short name T1224
Test name
Test status
Simulation time 18899021 ps
CPU time 0.79 seconds
Started Jul 06 04:52:31 PM PDT 24
Finished Jul 06 04:52:32 PM PDT 24
Peak memory 196936 kb
Host smart-cf4c6e9c-aeaf-4d9e-b028-04d90501febc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764096270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.764096270
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3786990199
Short name T1254
Test name
Test status
Simulation time 1030519905 ps
CPU time 2.04 seconds
Started Jul 06 04:52:35 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 196108 kb
Host smart-e650803c-9290-4bce-a515-4f6efefcadff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786990199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3786990199
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4020494625
Short name T1312
Test name
Test status
Simulation time 253634145 ps
CPU time 0.8 seconds
Started Jul 06 04:52:32 PM PDT 24
Finished Jul 06 04:52:33 PM PDT 24
Peak memory 198792 kb
Host smart-d0295c79-e6ab-4384-b9a8-82e4f9b3a954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020494625 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4020494625
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2495362768
Short name T1266
Test name
Test status
Simulation time 13212877 ps
CPU time 0.58 seconds
Started Jul 06 04:52:32 PM PDT 24
Finished Jul 06 04:52:33 PM PDT 24
Peak memory 196156 kb
Host smart-4c161b5b-e37f-45ad-9c7a-304d0137dfca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495362768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2495362768
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.4109544493
Short name T1280
Test name
Test status
Simulation time 62360482 ps
CPU time 0.57 seconds
Started Jul 06 04:52:29 PM PDT 24
Finished Jul 06 04:52:30 PM PDT 24
Peak memory 195112 kb
Host smart-c1840430-3987-47c2-8940-51e748b0c904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109544493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.4109544493
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3914217060
Short name T1241
Test name
Test status
Simulation time 39984825 ps
CPU time 0.77 seconds
Started Jul 06 04:52:32 PM PDT 24
Finished Jul 06 04:52:33 PM PDT 24
Peak memory 196612 kb
Host smart-b34b31aa-5f8e-406e-b1be-3c549a275e5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914217060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3914217060
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3092451559
Short name T1219
Test name
Test status
Simulation time 70392584 ps
CPU time 1.53 seconds
Started Jul 06 04:52:30 PM PDT 24
Finished Jul 06 04:52:32 PM PDT 24
Peak memory 200800 kb
Host smart-23f35623-bb86-4e3f-8a25-30c6dfc39c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092451559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3092451559
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3625003941
Short name T1230
Test name
Test status
Simulation time 143487158 ps
CPU time 1 seconds
Started Jul 06 04:52:30 PM PDT 24
Finished Jul 06 04:52:32 PM PDT 24
Peak memory 199684 kb
Host smart-8bdb0cb2-2eac-4531-b8cc-d422fc0ca241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625003941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3625003941
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3523511434
Short name T1258
Test name
Test status
Simulation time 27311944 ps
CPU time 0.55 seconds
Started Jul 06 04:52:47 PM PDT 24
Finished Jul 06 04:52:48 PM PDT 24
Peak memory 195064 kb
Host smart-46df93d7-e677-4127-8c6c-aa85074f0b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523511434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3523511434
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3298018864
Short name T1198
Test name
Test status
Simulation time 43902817 ps
CPU time 0.55 seconds
Started Jul 06 04:52:48 PM PDT 24
Finished Jul 06 04:52:50 PM PDT 24
Peak memory 195216 kb
Host smart-908ee2f5-21e5-4050-9d79-056b5addf9cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298018864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3298018864
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1881789241
Short name T1192
Test name
Test status
Simulation time 44865129 ps
CPU time 0.59 seconds
Started Jul 06 04:52:42 PM PDT 24
Finished Jul 06 04:52:43 PM PDT 24
Peak memory 195112 kb
Host smart-a5e1abaf-2f0a-4eb9-b801-116ddd10e4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881789241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1881789241
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.275816491
Short name T1253
Test name
Test status
Simulation time 13435332 ps
CPU time 0.54 seconds
Started Jul 06 04:52:51 PM PDT 24
Finished Jul 06 04:52:52 PM PDT 24
Peak memory 195084 kb
Host smart-df46084f-7c5c-4b23-bd20-001de0ec52d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275816491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.275816491
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1275854889
Short name T1207
Test name
Test status
Simulation time 14226035 ps
CPU time 0.54 seconds
Started Jul 06 04:52:42 PM PDT 24
Finished Jul 06 04:52:43 PM PDT 24
Peak memory 195032 kb
Host smart-160c3fd1-7e2b-4f73-9260-1ec874fbf10d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275854889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1275854889
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.4017752704
Short name T1240
Test name
Test status
Simulation time 13159409 ps
CPU time 0.56 seconds
Started Jul 06 04:52:41 PM PDT 24
Finished Jul 06 04:52:41 PM PDT 24
Peak memory 195096 kb
Host smart-dac36f19-e657-4772-a8e5-04981229ad0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017752704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4017752704
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1862838737
Short name T1268
Test name
Test status
Simulation time 42075869 ps
CPU time 0.55 seconds
Started Jul 06 04:52:48 PM PDT 24
Finished Jul 06 04:52:49 PM PDT 24
Peak memory 195116 kb
Host smart-acd7e311-e955-4771-a415-f94bd156bc78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862838737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1862838737
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1926099968
Short name T1236
Test name
Test status
Simulation time 46862715 ps
CPU time 0.55 seconds
Started Jul 06 04:52:48 PM PDT 24
Finished Jul 06 04:52:50 PM PDT 24
Peak memory 195116 kb
Host smart-172bf73e-5800-43c7-a821-5491be08be79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926099968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1926099968
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1935377878
Short name T1182
Test name
Test status
Simulation time 15151743 ps
CPU time 0.57 seconds
Started Jul 06 04:52:48 PM PDT 24
Finished Jul 06 04:52:50 PM PDT 24
Peak memory 195052 kb
Host smart-93583f00-1b42-487e-ac96-761d7c6ced04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935377878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1935377878
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1760637393
Short name T1288
Test name
Test status
Simulation time 141574226 ps
CPU time 0.63 seconds
Started Jul 06 04:52:46 PM PDT 24
Finished Jul 06 04:52:47 PM PDT 24
Peak memory 195100 kb
Host smart-d775aef2-ef16-41a1-a164-0b2d2737b653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760637393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1760637393
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1579910133
Short name T1252
Test name
Test status
Simulation time 49357338 ps
CPU time 0.8 seconds
Started Jul 06 04:52:31 PM PDT 24
Finished Jul 06 04:52:32 PM PDT 24
Peak memory 196928 kb
Host smart-4f16832f-6a82-4d66-9584-21818f68274f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579910133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1579910133
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4289507257
Short name T1307
Test name
Test status
Simulation time 119457541 ps
CPU time 1.54 seconds
Started Jul 06 04:52:28 PM PDT 24
Finished Jul 06 04:52:30 PM PDT 24
Peak memory 198488 kb
Host smart-22d4f64c-fc76-4e27-9881-df7c68614a72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289507257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4289507257
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.149385247
Short name T1211
Test name
Test status
Simulation time 45989933 ps
CPU time 0.59 seconds
Started Jul 06 04:52:29 PM PDT 24
Finished Jul 06 04:52:30 PM PDT 24
Peak memory 196200 kb
Host smart-4d147172-28d3-442e-b3c9-14d49d0d408a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149385247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.149385247
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1487422165
Short name T1248
Test name
Test status
Simulation time 25863603 ps
CPU time 0.79 seconds
Started Jul 06 04:52:32 PM PDT 24
Finished Jul 06 04:52:33 PM PDT 24
Peak memory 200540 kb
Host smart-b0c357d8-2630-4c7a-a8c5-d0f6192c7372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487422165 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1487422165
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1795820414
Short name T71
Test name
Test status
Simulation time 11221029 ps
CPU time 0.68 seconds
Started Jul 06 04:52:35 PM PDT 24
Finished Jul 06 04:52:36 PM PDT 24
Peak memory 196212 kb
Host smart-79186066-4313-4a03-8e3d-59b112ece774
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795820414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1795820414
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.241014109
Short name T1210
Test name
Test status
Simulation time 17311340 ps
CPU time 0.59 seconds
Started Jul 06 04:52:32 PM PDT 24
Finished Jul 06 04:52:33 PM PDT 24
Peak memory 195144 kb
Host smart-7fe8150b-99a4-4fde-bac4-017ec990c701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241014109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.241014109
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1346218606
Short name T95
Test name
Test status
Simulation time 25606680 ps
CPU time 0.71 seconds
Started Jul 06 04:52:28 PM PDT 24
Finished Jul 06 04:52:29 PM PDT 24
Peak memory 196568 kb
Host smart-277f38ac-6779-445d-8d20-822926468fcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346218606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1346218606
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1229770413
Short name T1188
Test name
Test status
Simulation time 279052364 ps
CPU time 1.38 seconds
Started Jul 06 04:52:30 PM PDT 24
Finished Jul 06 04:52:32 PM PDT 24
Peak memory 200852 kb
Host smart-5ad7e954-9cdf-4ced-af10-e5d3cbfc4fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229770413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1229770413
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.72822323
Short name T1293
Test name
Test status
Simulation time 180255067 ps
CPU time 1.08 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 199896 kb
Host smart-b5afb840-caa6-4744-bf7e-c5e4fb482cef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72822323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.72822323
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1327559678
Short name T1189
Test name
Test status
Simulation time 23477420 ps
CPU time 0.58 seconds
Started Jul 06 04:52:50 PM PDT 24
Finished Jul 06 04:52:51 PM PDT 24
Peak memory 195072 kb
Host smart-3624d44c-5241-415c-963a-e6332760f2bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327559678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1327559678
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.577608421
Short name T1245
Test name
Test status
Simulation time 29800564 ps
CPU time 0.59 seconds
Started Jul 06 04:52:47 PM PDT 24
Finished Jul 06 04:52:54 PM PDT 24
Peak memory 195108 kb
Host smart-aa39d656-0572-4a25-a810-ea86d3181144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577608421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.577608421
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4084623600
Short name T1227
Test name
Test status
Simulation time 12331511 ps
CPU time 0.57 seconds
Started Jul 06 04:52:55 PM PDT 24
Finished Jul 06 04:52:56 PM PDT 24
Peak memory 195068 kb
Host smart-52f74f36-dc99-4d0c-a133-ef52c9d769f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084623600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4084623600
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1119990028
Short name T1282
Test name
Test status
Simulation time 18662799 ps
CPU time 0.56 seconds
Started Jul 06 04:52:50 PM PDT 24
Finished Jul 06 04:52:51 PM PDT 24
Peak memory 195132 kb
Host smart-471f112a-d255-45fe-80ed-3cf8d8ea6982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119990028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1119990028
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2321427906
Short name T1181
Test name
Test status
Simulation time 31924884 ps
CPU time 0.56 seconds
Started Jul 06 04:52:46 PM PDT 24
Finished Jul 06 04:52:48 PM PDT 24
Peak memory 195104 kb
Host smart-dde4ff21-2d25-4892-88c1-0c768e2657ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321427906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2321427906
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2522789656
Short name T1187
Test name
Test status
Simulation time 19885074 ps
CPU time 0.56 seconds
Started Jul 06 04:52:49 PM PDT 24
Finished Jul 06 04:52:51 PM PDT 24
Peak memory 195216 kb
Host smart-6a37d80c-440c-4fd6-a6ee-3dee47a6c519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522789656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2522789656
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.907503912
Short name T1215
Test name
Test status
Simulation time 14769527 ps
CPU time 0.55 seconds
Started Jul 06 04:52:51 PM PDT 24
Finished Jul 06 04:52:52 PM PDT 24
Peak memory 195044 kb
Host smart-cd5658f9-bb7c-462f-a7ca-c89d808357dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907503912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.907503912
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2689026926
Short name T1278
Test name
Test status
Simulation time 32298882 ps
CPU time 0.61 seconds
Started Jul 06 04:52:49 PM PDT 24
Finished Jul 06 04:52:50 PM PDT 24
Peak memory 195084 kb
Host smart-082e8ff5-8f87-4199-9450-81b1de7be01b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689026926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2689026926
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.41359303
Short name T1306
Test name
Test status
Simulation time 18335310 ps
CPU time 0.58 seconds
Started Jul 06 04:52:45 PM PDT 24
Finished Jul 06 04:52:46 PM PDT 24
Peak memory 195168 kb
Host smart-c1cbc420-b800-4602-97af-f5d58f5fac4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41359303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.41359303
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3928030963
Short name T1242
Test name
Test status
Simulation time 14880277 ps
CPU time 0.59 seconds
Started Jul 06 04:52:52 PM PDT 24
Finished Jul 06 04:52:53 PM PDT 24
Peak memory 195132 kb
Host smart-dceaf426-848c-4028-a020-d6c2d5f14331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928030963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3928030963
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2879874317
Short name T1294
Test name
Test status
Simulation time 32517068 ps
CPU time 1.42 seconds
Started Jul 06 04:52:32 PM PDT 24
Finished Jul 06 04:52:33 PM PDT 24
Peak memory 200868 kb
Host smart-ad613d9a-b099-4564-a935-21c25ae0b2c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879874317 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2879874317
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3835929332
Short name T74
Test name
Test status
Simulation time 17934196 ps
CPU time 0.65 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 196312 kb
Host smart-5747ecae-7772-4a61-a5dc-ce25190ffba2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835929332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3835929332
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3751383785
Short name T1220
Test name
Test status
Simulation time 18573703 ps
CPU time 0.61 seconds
Started Jul 06 04:52:35 PM PDT 24
Finished Jul 06 04:52:36 PM PDT 24
Peak memory 195044 kb
Host smart-5af620ef-83c9-4136-8747-575182306ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751383785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3751383785
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.206991808
Short name T1234
Test name
Test status
Simulation time 21172884 ps
CPU time 0.71 seconds
Started Jul 06 04:52:29 PM PDT 24
Finished Jul 06 04:52:30 PM PDT 24
Peak memory 197300 kb
Host smart-457ca596-18e7-42b2-b75b-d4ee0a3aa9be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206991808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.206991808
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3257959459
Short name T1263
Test name
Test status
Simulation time 115180157 ps
CPU time 2.03 seconds
Started Jul 06 04:52:31 PM PDT 24
Finished Jul 06 04:52:33 PM PDT 24
Peak memory 200808 kb
Host smart-50c9f106-cfd8-42f4-8156-0ef2b4d3117f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257959459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3257959459
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2326908940
Short name T1199
Test name
Test status
Simulation time 185917366 ps
CPU time 0.98 seconds
Started Jul 06 04:52:30 PM PDT 24
Finished Jul 06 04:52:32 PM PDT 24
Peak memory 199808 kb
Host smart-48525d7e-10ad-4447-8a7d-d5195b6be4f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326908940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2326908940
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1552041762
Short name T1225
Test name
Test status
Simulation time 32637639 ps
CPU time 0.95 seconds
Started Jul 06 04:52:31 PM PDT 24
Finished Jul 06 04:52:32 PM PDT 24
Peak memory 200496 kb
Host smart-101b8bfc-a1e4-4e47-89ee-51886ed42c2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552041762 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1552041762
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3072978096
Short name T76
Test name
Test status
Simulation time 16791012 ps
CPU time 0.59 seconds
Started Jul 06 04:52:28 PM PDT 24
Finished Jul 06 04:52:29 PM PDT 24
Peak memory 196124 kb
Host smart-3e312f41-1f88-4b29-b94f-1e7eaf1b5476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072978096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3072978096
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2681734351
Short name T1257
Test name
Test status
Simulation time 51847177 ps
CPU time 0.58 seconds
Started Jul 06 04:52:38 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 195156 kb
Host smart-b2587874-7648-4083-a64e-bf0ce7f75e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681734351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2681734351
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1717290328
Short name T89
Test name
Test status
Simulation time 62599342 ps
CPU time 0.75 seconds
Started Jul 06 04:52:33 PM PDT 24
Finished Jul 06 04:52:34 PM PDT 24
Peak memory 197828 kb
Host smart-bdea98b4-4e3f-4b4f-b72e-7aa1e52138ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717290328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1717290328
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1622807853
Short name T1273
Test name
Test status
Simulation time 51598668 ps
CPU time 2.31 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:37 PM PDT 24
Peak memory 200876 kb
Host smart-9693ceaf-e3c6-4976-a0a6-f400f026921b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622807853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1622807853
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.212621607
Short name T130
Test name
Test status
Simulation time 175414980 ps
CPU time 0.99 seconds
Started Jul 06 04:52:30 PM PDT 24
Finished Jul 06 04:52:32 PM PDT 24
Peak memory 199916 kb
Host smart-7ef08c97-e254-4b51-a7ce-e73908494e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212621607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.212621607
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.371963184
Short name T1243
Test name
Test status
Simulation time 36232334 ps
CPU time 0.82 seconds
Started Jul 06 04:52:36 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 200564 kb
Host smart-7126a059-0539-4865-8f66-090f2137d24c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371963184 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.371963184
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.4217697910
Short name T1222
Test name
Test status
Simulation time 14299300 ps
CPU time 0.59 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 196068 kb
Host smart-c44583ea-bb20-44e3-84b2-c9370ab282b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217697910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4217697910
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2835204860
Short name T1193
Test name
Test status
Simulation time 50774821 ps
CPU time 0.56 seconds
Started Jul 06 04:52:36 PM PDT 24
Finished Jul 06 04:52:37 PM PDT 24
Peak memory 195132 kb
Host smart-a0771ed6-b4d2-4651-b654-a6eb41d5db1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835204860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2835204860
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.13733293
Short name T88
Test name
Test status
Simulation time 125235262 ps
CPU time 0.71 seconds
Started Jul 06 04:52:33 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 197356 kb
Host smart-dfd13f02-1375-4276-8c4c-ca23409f7262
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13733293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_o
utstanding.13733293
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3594004886
Short name T1272
Test name
Test status
Simulation time 239567261 ps
CPU time 1.54 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:40 PM PDT 24
Peak memory 200820 kb
Host smart-fcc3ec78-516e-4171-988b-676732fce832
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594004886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3594004886
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1409325484
Short name T103
Test name
Test status
Simulation time 851680439 ps
CPU time 1.27 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 200084 kb
Host smart-bf35bcce-6d86-4c56-a0e3-8eabd1301929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409325484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1409325484
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.630841932
Short name T1202
Test name
Test status
Simulation time 59405789 ps
CPU time 0.75 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 199640 kb
Host smart-c078c91f-4b5f-4032-b918-cb53df0b8c92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630841932 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.630841932
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3176114774
Short name T72
Test name
Test status
Simulation time 46939776 ps
CPU time 0.6 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 196180 kb
Host smart-7be42f9c-6da2-4cc7-98dc-f04e33da4611
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176114774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3176114774
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2695660884
Short name T1200
Test name
Test status
Simulation time 37145650 ps
CPU time 0.57 seconds
Started Jul 06 04:52:37 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 195096 kb
Host smart-8eabe3c9-9e10-4653-86d8-23c4f6f29361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695660884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2695660884
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2113480731
Short name T1287
Test name
Test status
Simulation time 21049226 ps
CPU time 0.66 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:36 PM PDT 24
Peak memory 196308 kb
Host smart-e9506cb3-19f0-447b-aec7-578d1df0cf81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113480731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2113480731
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1243593732
Short name T1226
Test name
Test status
Simulation time 39584199 ps
CPU time 1.12 seconds
Started Jul 06 04:52:35 PM PDT 24
Finished Jul 06 04:52:36 PM PDT 24
Peak memory 200580 kb
Host smart-58065909-d679-44c0-9cfd-286dd8b55f69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243593732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1243593732
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.59727577
Short name T105
Test name
Test status
Simulation time 169370756 ps
CPU time 1.38 seconds
Started Jul 06 04:52:34 PM PDT 24
Finished Jul 06 04:52:36 PM PDT 24
Peak memory 200032 kb
Host smart-ac5fe9e5-458e-44b5-8384-b9b552d5e39f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59727577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.59727577
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1551979790
Short name T1285
Test name
Test status
Simulation time 59372185 ps
CPU time 0.83 seconds
Started Jul 06 04:52:35 PM PDT 24
Finished Jul 06 04:52:36 PM PDT 24
Peak memory 200564 kb
Host smart-52de36c0-6c81-44e0-95ca-1ee166472a9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551979790 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1551979790
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2754808792
Short name T73
Test name
Test status
Simulation time 30315398 ps
CPU time 0.62 seconds
Started Jul 06 04:52:38 PM PDT 24
Finished Jul 06 04:52:39 PM PDT 24
Peak memory 196032 kb
Host smart-5518031d-d0c8-4f90-b7f3-0b2ae9b37fae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754808792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2754808792
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1103951660
Short name T1286
Test name
Test status
Simulation time 26353382 ps
CPU time 0.54 seconds
Started Jul 06 04:52:33 PM PDT 24
Finished Jul 06 04:52:34 PM PDT 24
Peak memory 195164 kb
Host smart-e44399fe-5bdb-45ea-9966-ad4eb4912be0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103951660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1103951660
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2787575057
Short name T93
Test name
Test status
Simulation time 118441731 ps
CPU time 0.76 seconds
Started Jul 06 04:52:39 PM PDT 24
Finished Jul 06 04:52:41 PM PDT 24
Peak memory 196588 kb
Host smart-235522c3-bdff-48ab-a7d4-18ae564c62ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787575057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2787575057
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1294907362
Short name T1223
Test name
Test status
Simulation time 134526207 ps
CPU time 1.94 seconds
Started Jul 06 04:52:38 PM PDT 24
Finished Jul 06 04:52:41 PM PDT 24
Peak memory 200480 kb
Host smart-ffed5f53-719f-4fa6-b7f9-e381ad0f1f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294907362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1294907362
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3330712510
Short name T945
Test name
Test status
Simulation time 98164870693 ps
CPU time 19.38 seconds
Started Jul 06 05:56:44 PM PDT 24
Finished Jul 06 05:57:04 PM PDT 24
Peak memory 199924 kb
Host smart-dd89510a-9343-4252-9c1d-641efaa30391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330712510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3330712510
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2463451838
Short name T468
Test name
Test status
Simulation time 192633809145 ps
CPU time 57.72 seconds
Started Jul 06 05:56:44 PM PDT 24
Finished Jul 06 05:57:42 PM PDT 24
Peak memory 199988 kb
Host smart-3b55b91e-8e1c-4205-901e-2c4f02fa823b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463451838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2463451838
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.707440853
Short name T206
Test name
Test status
Simulation time 99326791282 ps
CPU time 63.94 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 05:57:48 PM PDT 24
Peak memory 199892 kb
Host smart-f277dec6-1365-4d2f-92b0-47b8c4d5b097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707440853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.707440853
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2453575185
Short name T1039
Test name
Test status
Simulation time 27552049469 ps
CPU time 8.27 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 05:56:52 PM PDT 24
Peak memory 197876 kb
Host smart-78684d44-7f2b-4d96-a1cc-fe9eead2c7ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453575185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2453575185
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3856764028
Short name T749
Test name
Test status
Simulation time 70878850355 ps
CPU time 282 seconds
Started Jul 06 05:56:46 PM PDT 24
Finished Jul 06 06:01:29 PM PDT 24
Peak memory 199984 kb
Host smart-18fc9c75-ebc3-4e5a-8453-0325c6e6827d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856764028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3856764028
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1049675657
Short name T1163
Test name
Test status
Simulation time 1483915061 ps
CPU time 1.28 seconds
Started Jul 06 05:56:42 PM PDT 24
Finished Jul 06 05:56:44 PM PDT 24
Peak memory 196136 kb
Host smart-7036f421-7365-46d5-98d4-c5960e87cc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049675657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1049675657
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1444274616
Short name T1024
Test name
Test status
Simulation time 107589336025 ps
CPU time 206.86 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 06:00:10 PM PDT 24
Peak memory 199216 kb
Host smart-5a9d739c-918c-485f-baf8-32a662dfb17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444274616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1444274616
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1106478640
Short name T530
Test name
Test status
Simulation time 20380308802 ps
CPU time 434.47 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 06:03:58 PM PDT 24
Peak memory 199904 kb
Host smart-93ebce12-cccb-4cdf-8883-ee020ca77476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106478640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1106478640
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3145280256
Short name T567
Test name
Test status
Simulation time 5706174789 ps
CPU time 12.18 seconds
Started Jul 06 05:56:42 PM PDT 24
Finished Jul 06 05:56:55 PM PDT 24
Peak memory 198188 kb
Host smart-e15b813f-7928-427e-91a4-540df236a195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145280256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3145280256
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2572624888
Short name T300
Test name
Test status
Simulation time 61485383557 ps
CPU time 26.56 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 05:57:10 PM PDT 24
Peak memory 199936 kb
Host smart-683d0e87-2455-4f6c-a134-46e867a60eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572624888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2572624888
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2445062320
Short name T45
Test name
Test status
Simulation time 5397052677 ps
CPU time 2.61 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 05:56:46 PM PDT 24
Peak memory 196032 kb
Host smart-31e41327-bcd9-4c93-a69b-75dcb186db73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445062320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2445062320
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1601216563
Short name T592
Test name
Test status
Simulation time 300564229 ps
CPU time 0.96 seconds
Started Jul 06 05:56:38 PM PDT 24
Finished Jul 06 05:56:40 PM PDT 24
Peak memory 198232 kb
Host smart-36a7d71c-9e14-47f5-bbf8-8084131bb475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601216563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1601216563
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2897628918
Short name T803
Test name
Test status
Simulation time 306199810532 ps
CPU time 552.93 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 06:05:57 PM PDT 24
Peak memory 199944 kb
Host smart-866b353f-fb71-402d-8729-01532b15052f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897628918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2897628918
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.586845548
Short name T548
Test name
Test status
Simulation time 1225155380 ps
CPU time 1.43 seconds
Started Jul 06 05:56:46 PM PDT 24
Finished Jul 06 05:56:48 PM PDT 24
Peak memory 198500 kb
Host smart-5d668931-da0d-4dc7-b16f-108daf967240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586845548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.586845548
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3405403451
Short name T1021
Test name
Test status
Simulation time 131376294770 ps
CPU time 121 seconds
Started Jul 06 05:56:44 PM PDT 24
Finished Jul 06 05:58:46 PM PDT 24
Peak memory 199996 kb
Host smart-b22a6db1-e61b-4a93-a92f-ec035f14e2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405403451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3405403451
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2074496586
Short name T1140
Test name
Test status
Simulation time 12569380 ps
CPU time 0.54 seconds
Started Jul 06 05:56:50 PM PDT 24
Finished Jul 06 05:56:50 PM PDT 24
Peak memory 194496 kb
Host smart-01b2e9de-4012-47d1-a18c-2124ac492935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074496586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2074496586
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1239345510
Short name T688
Test name
Test status
Simulation time 33531643513 ps
CPU time 18.58 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 05:57:02 PM PDT 24
Peak memory 199960 kb
Host smart-ed21db5f-f1e1-465f-9b0f-9e8cc984e196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239345510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1239345510
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1041426533
Short name T932
Test name
Test status
Simulation time 71937809868 ps
CPU time 28.55 seconds
Started Jul 06 05:56:45 PM PDT 24
Finished Jul 06 05:57:14 PM PDT 24
Peak memory 199408 kb
Host smart-aaf20a60-be53-4ae1-88f5-983859fc9914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041426533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1041426533
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3035733644
Short name T233
Test name
Test status
Simulation time 118353264783 ps
CPU time 177.88 seconds
Started Jul 06 05:56:42 PM PDT 24
Finished Jul 06 05:59:40 PM PDT 24
Peak memory 199956 kb
Host smart-e9e9b7c8-e989-4f9e-9b5a-7ea97fedc07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035733644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3035733644
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.89257410
Short name T788
Test name
Test status
Simulation time 39159644007 ps
CPU time 11.55 seconds
Started Jul 06 05:56:44 PM PDT 24
Finished Jul 06 05:56:56 PM PDT 24
Peak memory 199940 kb
Host smart-7b33bea9-8dc0-4434-9809-9887859e4f76
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89257410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.89257410
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3462591292
Short name T392
Test name
Test status
Simulation time 73304222569 ps
CPU time 401.41 seconds
Started Jul 06 05:56:46 PM PDT 24
Finished Jul 06 06:03:28 PM PDT 24
Peak memory 199956 kb
Host smart-17617bd2-1929-4701-805c-8e64bffaa848
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3462591292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3462591292
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3318570088
Short name T359
Test name
Test status
Simulation time 4585259315 ps
CPU time 4.27 seconds
Started Jul 06 05:56:49 PM PDT 24
Finished Jul 06 05:56:54 PM PDT 24
Peak memory 199680 kb
Host smart-44ac77c5-de7a-4ca7-bb37-3d20bf85353f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318570088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3318570088
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2000230989
Short name T639
Test name
Test status
Simulation time 81613003496 ps
CPU time 76.05 seconds
Started Jul 06 05:56:48 PM PDT 24
Finished Jul 06 05:58:04 PM PDT 24
Peak memory 200068 kb
Host smart-fc2726e6-a2da-4224-bff1-c0e01074bd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000230989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2000230989
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2615657340
Short name T1005
Test name
Test status
Simulation time 26560059195 ps
CPU time 1096.21 seconds
Started Jul 06 05:56:46 PM PDT 24
Finished Jul 06 06:15:03 PM PDT 24
Peak memory 199916 kb
Host smart-a667989b-ca0a-4a70-9fb9-5d38b86cd12f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615657340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2615657340
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1021644002
Short name T933
Test name
Test status
Simulation time 1380065533 ps
CPU time 2.95 seconds
Started Jul 06 05:56:42 PM PDT 24
Finished Jul 06 05:56:45 PM PDT 24
Peak memory 198224 kb
Host smart-28cd08c7-5890-4b2c-8172-79848f7e414c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021644002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1021644002
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.4048186970
Short name T853
Test name
Test status
Simulation time 160383013089 ps
CPU time 341.77 seconds
Started Jul 06 05:56:47 PM PDT 24
Finished Jul 06 06:02:29 PM PDT 24
Peak memory 199908 kb
Host smart-4af2ff7d-eecd-4d98-bf1b-f0a386361007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048186970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.4048186970
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2195652803
Short name T316
Test name
Test status
Simulation time 26777064637 ps
CPU time 39.98 seconds
Started Jul 06 05:56:46 PM PDT 24
Finished Jul 06 05:57:26 PM PDT 24
Peak memory 196268 kb
Host smart-38682be1-d70c-41c6-bff1-66b628ac61dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195652803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2195652803
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.275020738
Short name T106
Test name
Test status
Simulation time 75167326 ps
CPU time 0.87 seconds
Started Jul 06 05:56:48 PM PDT 24
Finished Jul 06 05:56:49 PM PDT 24
Peak memory 218432 kb
Host smart-813f4226-58c4-435e-8327-312495e5732e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275020738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.275020738
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3435434946
Short name T779
Test name
Test status
Simulation time 930223524 ps
CPU time 4.11 seconds
Started Jul 06 05:56:42 PM PDT 24
Finished Jul 06 05:56:47 PM PDT 24
Peak memory 199620 kb
Host smart-866f82bf-603f-43f4-bb82-273a00f24bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435434946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3435434946
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.260571457
Short name T664
Test name
Test status
Simulation time 1135606355 ps
CPU time 3.9 seconds
Started Jul 06 05:56:47 PM PDT 24
Finished Jul 06 05:56:51 PM PDT 24
Peak memory 199268 kb
Host smart-fbe72a49-aae6-46ee-9984-c4dee0188dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260571457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.260571457
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.4251662398
Short name T804
Test name
Test status
Simulation time 24019629075 ps
CPU time 39.37 seconds
Started Jul 06 05:56:43 PM PDT 24
Finished Jul 06 05:57:23 PM PDT 24
Peak memory 199968 kb
Host smart-de3f461f-0689-4421-bbaf-c7a8cf31bb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251662398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4251662398
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1900274957
Short name T981
Test name
Test status
Simulation time 48873044 ps
CPU time 0.57 seconds
Started Jul 06 05:57:18 PM PDT 24
Finished Jul 06 05:57:19 PM PDT 24
Peak memory 195624 kb
Host smart-4b73d673-c821-4128-96f1-fb27a4b71560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900274957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1900274957
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1434236384
Short name T586
Test name
Test status
Simulation time 81051003338 ps
CPU time 27.25 seconds
Started Jul 06 05:57:17 PM PDT 24
Finished Jul 06 05:57:45 PM PDT 24
Peak memory 199980 kb
Host smart-40128718-c464-4acf-bad2-cb9749c2825a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434236384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1434236384
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.684615622
Short name T605
Test name
Test status
Simulation time 60663017581 ps
CPU time 48.82 seconds
Started Jul 06 05:57:18 PM PDT 24
Finished Jul 06 05:58:08 PM PDT 24
Peak memory 200000 kb
Host smart-4d1c3308-7e1f-47c1-aa42-dd70e73fe0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684615622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.684615622
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.1237317600
Short name T555
Test name
Test status
Simulation time 50246625392 ps
CPU time 70.35 seconds
Started Jul 06 05:57:18 PM PDT 24
Finished Jul 06 05:58:28 PM PDT 24
Peak memory 199036 kb
Host smart-a1440a81-0e1d-4ba7-b387-06b477e6da4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237317600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1237317600
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.4114271815
Short name T876
Test name
Test status
Simulation time 130269696542 ps
CPU time 345.45 seconds
Started Jul 06 05:57:19 PM PDT 24
Finished Jul 06 06:03:05 PM PDT 24
Peak memory 199992 kb
Host smart-a21e3cbd-cb0e-42a9-b743-f34f7d4f4c3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4114271815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4114271815
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.806838376
Short name T446
Test name
Test status
Simulation time 1071922598 ps
CPU time 0.82 seconds
Started Jul 06 05:57:19 PM PDT 24
Finished Jul 06 05:57:20 PM PDT 24
Peak memory 195544 kb
Host smart-5cf2ac4d-c88d-41b8-a1be-2028b8d1643c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806838376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.806838376
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.209340007
Short name T831
Test name
Test status
Simulation time 114234799528 ps
CPU time 50.92 seconds
Started Jul 06 05:57:18 PM PDT 24
Finished Jul 06 05:58:09 PM PDT 24
Peak memory 200140 kb
Host smart-d49fc5bf-1f7e-4a6b-b02e-29819c7cb8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209340007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.209340007
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.825814733
Short name T813
Test name
Test status
Simulation time 9583550664 ps
CPU time 128.17 seconds
Started Jul 06 05:57:20 PM PDT 24
Finished Jul 06 05:59:29 PM PDT 24
Peak memory 199796 kb
Host smart-25cd9b4b-7211-431c-8747-bc0f6956d233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825814733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.825814733
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1560404977
Short name T1071
Test name
Test status
Simulation time 6451409023 ps
CPU time 17.01 seconds
Started Jul 06 05:57:20 PM PDT 24
Finished Jul 06 05:57:37 PM PDT 24
Peak memory 198840 kb
Host smart-fb88af53-b87b-4cae-adf3-2f8c42711964
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560404977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1560404977
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.28345825
Short name T184
Test name
Test status
Simulation time 149334067353 ps
CPU time 54.46 seconds
Started Jul 06 05:57:19 PM PDT 24
Finished Jul 06 05:58:14 PM PDT 24
Peak memory 199992 kb
Host smart-3861a888-eb36-48e1-8bc3-7a7fdeec49ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28345825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.28345825
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.811905419
Short name T1144
Test name
Test status
Simulation time 4045496470 ps
CPU time 0.98 seconds
Started Jul 06 05:57:20 PM PDT 24
Finished Jul 06 05:57:21 PM PDT 24
Peak memory 196512 kb
Host smart-221bc5fa-879b-4c68-9122-9dafa1ff3645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811905419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.811905419
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1420194969
Short name T1055
Test name
Test status
Simulation time 625601273 ps
CPU time 2.24 seconds
Started Jul 06 05:57:16 PM PDT 24
Finished Jul 06 05:57:18 PM PDT 24
Peak memory 199720 kb
Host smart-9800635c-72c8-4dcc-94e9-32b072926371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420194969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1420194969
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1590017105
Short name T506
Test name
Test status
Simulation time 27003272797 ps
CPU time 991.26 seconds
Started Jul 06 05:57:20 PM PDT 24
Finished Jul 06 06:13:51 PM PDT 24
Peak memory 199964 kb
Host smart-da6834d4-e257-4d52-9318-2517a08e4f10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590017105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1590017105
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.279990435
Short name T121
Test name
Test status
Simulation time 140729770831 ps
CPU time 101.56 seconds
Started Jul 06 05:57:17 PM PDT 24
Finished Jul 06 05:58:59 PM PDT 24
Peak memory 214164 kb
Host smart-238b91b2-b4f3-41ac-a373-1e89abd33468
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279990435 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.279990435
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2631452603
Short name T406
Test name
Test status
Simulation time 229461363 ps
CPU time 1.11 seconds
Started Jul 06 05:57:19 PM PDT 24
Finished Jul 06 05:57:20 PM PDT 24
Peak memory 197300 kb
Host smart-c826b6c8-e035-442a-90cf-d5047b039bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631452603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2631452603
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3863333203
Short name T310
Test name
Test status
Simulation time 166872728968 ps
CPU time 87.4 seconds
Started Jul 06 05:57:13 PM PDT 24
Finished Jul 06 05:58:41 PM PDT 24
Peak memory 199904 kb
Host smart-207287d4-049f-437a-8fd0-1a586cebdc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863333203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3863333203
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1279550100
Short name T1020
Test name
Test status
Simulation time 41566258988 ps
CPU time 63.74 seconds
Started Jul 06 06:01:23 PM PDT 24
Finished Jul 06 06:02:27 PM PDT 24
Peak memory 199712 kb
Host smart-507d6ea0-0105-4d27-9708-9c5be6f43a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279550100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1279550100
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3088369902
Short name T746
Test name
Test status
Simulation time 28148316525 ps
CPU time 29.52 seconds
Started Jul 06 06:01:19 PM PDT 24
Finished Jul 06 06:01:48 PM PDT 24
Peak memory 199980 kb
Host smart-a4ee7216-1395-45bd-9e6d-7d2c9ce31591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088369902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3088369902
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.647398522
Short name T63
Test name
Test status
Simulation time 106690982397 ps
CPU time 46.31 seconds
Started Jul 06 06:01:20 PM PDT 24
Finished Jul 06 06:02:06 PM PDT 24
Peak memory 199936 kb
Host smart-7f0e8f73-ca47-400f-8321-2dbd0f325180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647398522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.647398522
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2625898354
Short name T891
Test name
Test status
Simulation time 94698000237 ps
CPU time 63.64 seconds
Started Jul 06 06:01:21 PM PDT 24
Finished Jul 06 06:02:25 PM PDT 24
Peak memory 199888 kb
Host smart-77a30997-c7e3-466b-8530-cf0beb8560b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625898354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2625898354
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3759616974
Short name T484
Test name
Test status
Simulation time 220724438368 ps
CPU time 38.22 seconds
Started Jul 06 06:01:21 PM PDT 24
Finished Jul 06 06:02:00 PM PDT 24
Peak memory 199940 kb
Host smart-4e5f0626-1a6f-4eaa-93fe-ec877a0e4af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759616974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3759616974
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3493967656
Short name T925
Test name
Test status
Simulation time 67651820625 ps
CPU time 15.23 seconds
Started Jul 06 06:01:20 PM PDT 24
Finished Jul 06 06:01:36 PM PDT 24
Peak memory 199916 kb
Host smart-c8621cf7-ecdf-4ac2-b4c4-54636bdf87b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493967656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3493967656
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2575449746
Short name T668
Test name
Test status
Simulation time 150911514664 ps
CPU time 16.8 seconds
Started Jul 06 06:01:19 PM PDT 24
Finished Jul 06 06:01:36 PM PDT 24
Peak memory 199920 kb
Host smart-9caf863a-e2d6-4ff9-acbe-f8ef46b4e1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575449746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2575449746
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.119728071
Short name T1029
Test name
Test status
Simulation time 36274628741 ps
CPU time 19.36 seconds
Started Jul 06 06:01:23 PM PDT 24
Finished Jul 06 06:01:42 PM PDT 24
Peak memory 199948 kb
Host smart-3a356cb7-8bd4-4cd3-ba41-9d49e92138fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119728071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.119728071
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2793536237
Short name T382
Test name
Test status
Simulation time 12899707 ps
CPU time 0.55 seconds
Started Jul 06 05:57:28 PM PDT 24
Finished Jul 06 05:57:29 PM PDT 24
Peak memory 194292 kb
Host smart-375a1840-07fb-4ded-ada6-f4565437bec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793536237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2793536237
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2746283858
Short name T783
Test name
Test status
Simulation time 68574761092 ps
CPU time 95.3 seconds
Started Jul 06 05:57:21 PM PDT 24
Finished Jul 06 05:58:56 PM PDT 24
Peak memory 200004 kb
Host smart-e0a46100-d370-4e38-a1cb-115ce32b7708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746283858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2746283858
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1286416091
Short name T136
Test name
Test status
Simulation time 20050465304 ps
CPU time 14.1 seconds
Started Jul 06 05:57:18 PM PDT 24
Finished Jul 06 05:57:33 PM PDT 24
Peak memory 199564 kb
Host smart-a4e92152-65b6-4f99-994b-ff9a063f620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286416091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1286416091
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.666069328
Short name T565
Test name
Test status
Simulation time 36913027778 ps
CPU time 65.95 seconds
Started Jul 06 05:57:18 PM PDT 24
Finished Jul 06 05:58:24 PM PDT 24
Peak memory 199976 kb
Host smart-5eba4783-5074-4136-b050-7f32f2a0aedb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666069328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.666069328
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3680678789
Short name T374
Test name
Test status
Simulation time 62561653692 ps
CPU time 270.08 seconds
Started Jul 06 05:57:25 PM PDT 24
Finished Jul 06 06:01:55 PM PDT 24
Peak memory 199956 kb
Host smart-9b262bc9-616c-42c1-8804-06104e9355d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3680678789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3680678789
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3344512745
Short name T892
Test name
Test status
Simulation time 7412260248 ps
CPU time 11.74 seconds
Started Jul 06 05:57:24 PM PDT 24
Finished Jul 06 05:57:36 PM PDT 24
Peak memory 198852 kb
Host smart-16fdf48c-e060-4180-bbb0-c899a4dab2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344512745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3344512745
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3874486399
Short name T490
Test name
Test status
Simulation time 94860163145 ps
CPU time 21.49 seconds
Started Jul 06 05:57:25 PM PDT 24
Finished Jul 06 05:57:46 PM PDT 24
Peak memory 197096 kb
Host smart-b4d8471f-e684-4f25-9f6c-5139bdd4728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874486399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3874486399
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2875102489
Short name T438
Test name
Test status
Simulation time 4109860116 ps
CPU time 40.88 seconds
Started Jul 06 05:57:23 PM PDT 24
Finished Jul 06 05:58:04 PM PDT 24
Peak memory 199908 kb
Host smart-2096b799-a01c-48a2-b38e-45f71b78ec15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2875102489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2875102489
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1990367738
Short name T959
Test name
Test status
Simulation time 5407674675 ps
CPU time 3.83 seconds
Started Jul 06 05:57:20 PM PDT 24
Finished Jul 06 05:57:24 PM PDT 24
Peak memory 199372 kb
Host smart-7a4709bc-bd60-4419-badf-905be9da55bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990367738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1990367738
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.727810855
Short name T855
Test name
Test status
Simulation time 181017054587 ps
CPU time 73.19 seconds
Started Jul 06 05:57:24 PM PDT 24
Finished Jul 06 05:58:37 PM PDT 24
Peak memory 199928 kb
Host smart-ff45dc81-d5ea-48e1-8ac5-3630093d96f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727810855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.727810855
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.319217051
Short name T479
Test name
Test status
Simulation time 3171192311 ps
CPU time 5.64 seconds
Started Jul 06 05:57:23 PM PDT 24
Finished Jul 06 05:57:29 PM PDT 24
Peak memory 196044 kb
Host smart-0cd5e713-be52-4345-98e2-66f622dad3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319217051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.319217051
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3991267840
Short name T434
Test name
Test status
Simulation time 116246838 ps
CPU time 0.97 seconds
Started Jul 06 05:57:18 PM PDT 24
Finished Jul 06 05:57:19 PM PDT 24
Peak memory 197748 kb
Host smart-2416cd80-b07a-4f8a-b298-58a4d68596b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991267840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3991267840
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2706140603
Short name T966
Test name
Test status
Simulation time 214804435707 ps
CPU time 86.45 seconds
Started Jul 06 05:57:29 PM PDT 24
Finished Jul 06 05:58:56 PM PDT 24
Peak memory 208264 kb
Host smart-00b3bc90-b646-4913-9168-3058ae67471d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706140603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2706140603
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3150366513
Short name T480
Test name
Test status
Simulation time 151780585601 ps
CPU time 820.02 seconds
Started Jul 06 05:57:22 PM PDT 24
Finished Jul 06 06:11:02 PM PDT 24
Peak memory 224712 kb
Host smart-93339c43-9ff0-42e1-b854-41e5a01e3a9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150366513 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3150366513
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.960181855
Short name T748
Test name
Test status
Simulation time 1571889982 ps
CPU time 1.74 seconds
Started Jul 06 05:57:23 PM PDT 24
Finished Jul 06 05:57:25 PM PDT 24
Peak memory 198428 kb
Host smart-052ee7b3-0147-4f04-9b4b-fa20209eb495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960181855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.960181855
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.347130091
Short name T830
Test name
Test status
Simulation time 66751459618 ps
CPU time 34.78 seconds
Started Jul 06 05:57:20 PM PDT 24
Finished Jul 06 05:57:55 PM PDT 24
Peak memory 199976 kb
Host smart-80f422f8-e198-4c79-b479-f9e733db98c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347130091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.347130091
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3038749065
Short name T1049
Test name
Test status
Simulation time 31873424845 ps
CPU time 43.41 seconds
Started Jul 06 06:01:19 PM PDT 24
Finished Jul 06 06:02:03 PM PDT 24
Peak memory 199972 kb
Host smart-2875648d-e65b-4172-aaa5-840ea9d888ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038749065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3038749065
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.4180280278
Short name T164
Test name
Test status
Simulation time 87399585195 ps
CPU time 139.84 seconds
Started Jul 06 06:01:20 PM PDT 24
Finished Jul 06 06:03:40 PM PDT 24
Peak memory 199976 kb
Host smart-7fa97b9d-a625-4f57-8327-58d84c917707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180280278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.4180280278
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1830107655
Short name T291
Test name
Test status
Simulation time 143811289271 ps
CPU time 21.3 seconds
Started Jul 06 06:01:23 PM PDT 24
Finished Jul 06 06:01:45 PM PDT 24
Peak memory 199836 kb
Host smart-f211343e-c7a2-4c6b-919d-65d0952e3e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830107655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1830107655
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1388793179
Short name T775
Test name
Test status
Simulation time 20938883725 ps
CPU time 33.01 seconds
Started Jul 06 06:01:24 PM PDT 24
Finished Jul 06 06:01:57 PM PDT 24
Peak memory 199940 kb
Host smart-543a1638-7e49-480e-a1a5-d22d9b1d459d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388793179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1388793179
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.175674780
Short name T191
Test name
Test status
Simulation time 4114269050 ps
CPU time 6.08 seconds
Started Jul 06 06:01:23 PM PDT 24
Finished Jul 06 06:01:30 PM PDT 24
Peak memory 199456 kb
Host smart-6bdcc8e9-36e8-4492-86e0-0dc9b0522ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175674780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.175674780
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.37555682
Short name T249
Test name
Test status
Simulation time 140653465978 ps
CPU time 204.01 seconds
Started Jul 06 06:01:24 PM PDT 24
Finished Jul 06 06:04:48 PM PDT 24
Peak memory 200256 kb
Host smart-95fb0262-4c7f-47c8-b86f-ee50fac2318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37555682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.37555682
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1900347101
Short name T1018
Test name
Test status
Simulation time 30715829845 ps
CPU time 26.07 seconds
Started Jul 06 06:01:23 PM PDT 24
Finished Jul 06 06:01:50 PM PDT 24
Peak memory 199904 kb
Host smart-74460862-5bcc-4f95-99a3-1ff0bb4fcad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900347101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1900347101
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1735731400
Short name T774
Test name
Test status
Simulation time 25045222521 ps
CPU time 21.78 seconds
Started Jul 06 06:01:24 PM PDT 24
Finished Jul 06 06:01:46 PM PDT 24
Peak memory 199848 kb
Host smart-730e4f8e-9a4c-4f0f-9ccc-5fbbc0a699f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735731400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1735731400
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3458030363
Short name T510
Test name
Test status
Simulation time 22418077 ps
CPU time 0.59 seconds
Started Jul 06 05:57:32 PM PDT 24
Finished Jul 06 05:57:33 PM PDT 24
Peak memory 194304 kb
Host smart-b6d7c2f2-8401-4902-a4bd-13d08fb9b707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458030363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3458030363
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3326617955
Short name T143
Test name
Test status
Simulation time 51660799918 ps
CPU time 21.45 seconds
Started Jul 06 05:57:27 PM PDT 24
Finished Jul 06 05:57:49 PM PDT 24
Peak memory 199972 kb
Host smart-f352823b-5dd6-4e5c-a031-be3a5b9fd1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326617955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3326617955
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2091924458
Short name T663
Test name
Test status
Simulation time 120970987942 ps
CPU time 45.34 seconds
Started Jul 06 05:57:27 PM PDT 24
Finished Jul 06 05:58:13 PM PDT 24
Peak memory 199892 kb
Host smart-882a7518-07a1-447d-b02a-b1a55d7dc606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091924458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2091924458
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.488131084
Short name T110
Test name
Test status
Simulation time 47702265498 ps
CPU time 71.8 seconds
Started Jul 06 05:57:28 PM PDT 24
Finished Jul 06 05:58:40 PM PDT 24
Peak memory 199944 kb
Host smart-475f06cb-bcc0-447a-bb49-8833ec03045d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488131084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.488131084
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.791945188
Short name T716
Test name
Test status
Simulation time 87261725437 ps
CPU time 432.6 seconds
Started Jul 06 05:57:33 PM PDT 24
Finished Jul 06 06:04:46 PM PDT 24
Peak memory 199884 kb
Host smart-a6b87b76-d213-4709-a4ba-537b280ead56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791945188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.791945188
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2259297179
Short name T1107
Test name
Test status
Simulation time 7410215741 ps
CPU time 3.35 seconds
Started Jul 06 05:57:33 PM PDT 24
Finished Jul 06 05:57:36 PM PDT 24
Peak memory 199764 kb
Host smart-8f9afd0c-03b1-48f5-9ce0-77a7958035ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259297179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2259297179
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.835252618
Short name T1165
Test name
Test status
Simulation time 336802901062 ps
CPU time 112.13 seconds
Started Jul 06 05:57:27 PM PDT 24
Finished Jul 06 05:59:19 PM PDT 24
Peak memory 208540 kb
Host smart-d2f85853-cce5-46c9-845d-d737e77c8acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835252618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.835252618
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2760271144
Short name T929
Test name
Test status
Simulation time 11192141192 ps
CPU time 146.94 seconds
Started Jul 06 05:57:33 PM PDT 24
Finished Jul 06 06:00:00 PM PDT 24
Peak memory 199928 kb
Host smart-70e022ab-f1d5-47ec-b790-2a6a3c4a5161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2760271144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2760271144
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3651339482
Short name T1130
Test name
Test status
Simulation time 4400194921 ps
CPU time 35.63 seconds
Started Jul 06 05:57:27 PM PDT 24
Finished Jul 06 05:58:03 PM PDT 24
Peak memory 199232 kb
Host smart-a38fe4fd-6c26-478c-83ad-380166e7b4fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651339482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3651339482
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3780463125
Short name T771
Test name
Test status
Simulation time 61354798303 ps
CPU time 47.01 seconds
Started Jul 06 05:57:33 PM PDT 24
Finished Jul 06 05:58:20 PM PDT 24
Peak memory 198692 kb
Host smart-eda68518-889a-45ad-9559-24bd2d6bc905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780463125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3780463125
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2916929972
Short name T939
Test name
Test status
Simulation time 62436300579 ps
CPU time 43.38 seconds
Started Jul 06 05:57:34 PM PDT 24
Finished Jul 06 05:58:18 PM PDT 24
Peak memory 196236 kb
Host smart-680df2ba-7592-4868-897a-d42734299790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916929972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2916929972
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2312476410
Short name T604
Test name
Test status
Simulation time 270942097 ps
CPU time 1.38 seconds
Started Jul 06 05:57:28 PM PDT 24
Finished Jul 06 05:57:30 PM PDT 24
Peak memory 198456 kb
Host smart-0991c1e5-9e41-4b9b-891a-aaaae6695056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312476410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2312476410
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.564579444
Short name T522
Test name
Test status
Simulation time 228366650069 ps
CPU time 733.25 seconds
Started Jul 06 05:57:32 PM PDT 24
Finished Jul 06 06:09:45 PM PDT 24
Peak memory 199976 kb
Host smart-8e19e2c2-6255-43f3-9f5c-e068913671fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564579444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.564579444
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1590608627
Short name T777
Test name
Test status
Simulation time 237507555295 ps
CPU time 1071.41 seconds
Started Jul 06 05:57:33 PM PDT 24
Finished Jul 06 06:15:25 PM PDT 24
Peak memory 232244 kb
Host smart-61437230-95f6-4183-9c0a-57941c6cd192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590608627 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1590608627
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.358681044
Short name T433
Test name
Test status
Simulation time 590775792 ps
CPU time 1.66 seconds
Started Jul 06 05:57:35 PM PDT 24
Finished Jul 06 05:57:37 PM PDT 24
Peak memory 198456 kb
Host smart-58c12d49-f391-41cd-88da-ee149849b8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358681044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.358681044
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2897625540
Short name T972
Test name
Test status
Simulation time 69153920123 ps
CPU time 55.95 seconds
Started Jul 06 05:57:26 PM PDT 24
Finished Jul 06 05:58:22 PM PDT 24
Peak memory 199984 kb
Host smart-7b65e389-89eb-48dc-b43b-15bed7fcfb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897625540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2897625540
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.4106233789
Short name T1139
Test name
Test status
Simulation time 15675845857 ps
CPU time 17.88 seconds
Started Jul 06 06:01:25 PM PDT 24
Finished Jul 06 06:01:43 PM PDT 24
Peak memory 199952 kb
Host smart-2e685d5a-0653-4156-99f9-d1231a6e6a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106233789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4106233789
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1975704486
Short name T516
Test name
Test status
Simulation time 17475445366 ps
CPU time 30.8 seconds
Started Jul 06 06:01:25 PM PDT 24
Finished Jul 06 06:01:56 PM PDT 24
Peak memory 199984 kb
Host smart-f2927fef-f2c9-4887-8e6d-9b05162d1d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975704486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1975704486
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1533142386
Short name T287
Test name
Test status
Simulation time 18245238598 ps
CPU time 40.2 seconds
Started Jul 06 06:01:26 PM PDT 24
Finished Jul 06 06:02:07 PM PDT 24
Peak memory 199920 kb
Host smart-eee09a27-b639-4019-a450-5678afb0f381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533142386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1533142386
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1060018768
Short name T554
Test name
Test status
Simulation time 114963301627 ps
CPU time 230.19 seconds
Started Jul 06 06:01:24 PM PDT 24
Finished Jul 06 06:05:15 PM PDT 24
Peak memory 199908 kb
Host smart-347011f3-4f65-44c6-a8a4-b036be54531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060018768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1060018768
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.919824199
Short name T3
Test name
Test status
Simulation time 105137041405 ps
CPU time 238.75 seconds
Started Jul 06 06:01:24 PM PDT 24
Finished Jul 06 06:05:23 PM PDT 24
Peak memory 200192 kb
Host smart-23711c1f-621f-46c2-883e-5bb2f9cfbe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919824199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.919824199
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3903491699
Short name T512
Test name
Test status
Simulation time 140108292346 ps
CPU time 29.72 seconds
Started Jul 06 06:01:29 PM PDT 24
Finished Jul 06 06:01:59 PM PDT 24
Peak memory 199976 kb
Host smart-b18d4de9-0c09-4cb8-99af-5e9bd19809d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903491699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3903491699
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.344487683
Short name T1117
Test name
Test status
Simulation time 29671521840 ps
CPU time 23.84 seconds
Started Jul 06 06:01:29 PM PDT 24
Finished Jul 06 06:01:53 PM PDT 24
Peak memory 199848 kb
Host smart-cb1669d5-7271-4727-9171-0353d9c62ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344487683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.344487683
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2961936330
Short name T380
Test name
Test status
Simulation time 46537372 ps
CPU time 0.53 seconds
Started Jul 06 05:57:40 PM PDT 24
Finished Jul 06 05:57:41 PM PDT 24
Peak memory 195232 kb
Host smart-d176ad5d-efb7-4ff5-b040-1fb043c8d92b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961936330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2961936330
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.493889908
Short name T31
Test name
Test status
Simulation time 121449887183 ps
CPU time 42.52 seconds
Started Jul 06 05:57:33 PM PDT 24
Finished Jul 06 05:58:16 PM PDT 24
Peak memory 199960 kb
Host smart-69611142-98d5-4a7e-b5a6-ec62e4413494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493889908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.493889908
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3721175045
Short name T786
Test name
Test status
Simulation time 154268263952 ps
CPU time 28.85 seconds
Started Jul 06 05:57:35 PM PDT 24
Finished Jul 06 05:58:04 PM PDT 24
Peak memory 199968 kb
Host smart-f68ff637-df7b-49b9-bb66-e3105a96b526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721175045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3721175045
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1168741349
Short name T2
Test name
Test status
Simulation time 166728766871 ps
CPU time 66.06 seconds
Started Jul 06 05:57:34 PM PDT 24
Finished Jul 06 05:58:40 PM PDT 24
Peak memory 200020 kb
Host smart-9a8c711b-606c-42b5-a4a7-016dd069a485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168741349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1168741349
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.483951426
Short name T1084
Test name
Test status
Simulation time 66238800846 ps
CPU time 615.27 seconds
Started Jul 06 05:57:38 PM PDT 24
Finished Jul 06 06:07:53 PM PDT 24
Peak memory 200000 kb
Host smart-d50f64a6-930d-4252-ae83-f8f3be6997fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483951426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.483951426
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.416518922
Short name T1028
Test name
Test status
Simulation time 3689723911 ps
CPU time 6.74 seconds
Started Jul 06 05:57:39 PM PDT 24
Finished Jul 06 05:57:46 PM PDT 24
Peak memory 197208 kb
Host smart-916363f4-26e9-4e0c-9074-f25ad5270611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416518922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.416518922
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1281156380
Short name T618
Test name
Test status
Simulation time 42325539090 ps
CPU time 62.4 seconds
Started Jul 06 05:57:35 PM PDT 24
Finished Jul 06 05:58:38 PM PDT 24
Peak memory 198588 kb
Host smart-0607b7e0-c5d1-4524-a83d-ced68b4b285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281156380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1281156380
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3880334728
Short name T669
Test name
Test status
Simulation time 17554579096 ps
CPU time 196.64 seconds
Started Jul 06 05:57:37 PM PDT 24
Finished Jul 06 06:00:54 PM PDT 24
Peak memory 199880 kb
Host smart-3fca7ca5-5f3b-4a92-bbbb-bb34636a5346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880334728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3880334728
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2747161553
Short name T784
Test name
Test status
Simulation time 3492948615 ps
CPU time 27.9 seconds
Started Jul 06 05:57:35 PM PDT 24
Finished Jul 06 05:58:03 PM PDT 24
Peak memory 198412 kb
Host smart-20fbc9ad-e472-4149-a1e1-d06b3d778794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747161553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2747161553
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2362912365
Short name T1172
Test name
Test status
Simulation time 85114376673 ps
CPU time 35.07 seconds
Started Jul 06 05:57:37 PM PDT 24
Finished Jul 06 05:58:13 PM PDT 24
Peak memory 199444 kb
Host smart-f33ef766-9df2-47df-a442-f72e44630fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362912365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2362912365
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2602668902
Short name T424
Test name
Test status
Simulation time 41736937336 ps
CPU time 16.08 seconds
Started Jul 06 05:57:40 PM PDT 24
Finished Jul 06 05:57:57 PM PDT 24
Peak memory 196068 kb
Host smart-3cc0fd20-981d-4ff4-842a-f5d2bd662f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602668902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2602668902
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.457686062
Short name T820
Test name
Test status
Simulation time 960105987 ps
CPU time 1.75 seconds
Started Jul 06 05:57:32 PM PDT 24
Finished Jul 06 05:57:35 PM PDT 24
Peak memory 198352 kb
Host smart-b85db364-8638-471e-95cc-38bf4f4c7387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457686062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.457686062
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.409145930
Short name T1106
Test name
Test status
Simulation time 285992078425 ps
CPU time 996.22 seconds
Started Jul 06 05:57:40 PM PDT 24
Finished Jul 06 06:14:16 PM PDT 24
Peak memory 199892 kb
Host smart-dd4bad37-b17a-486b-94da-e8380a78febc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409145930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.409145930
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3762316183
Short name T25
Test name
Test status
Simulation time 9261318135 ps
CPU time 123.27 seconds
Started Jul 06 05:57:36 PM PDT 24
Finished Jul 06 05:59:39 PM PDT 24
Peak memory 208556 kb
Host smart-efb3354f-9f68-4d21-adba-22b9b573bb71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762316183 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3762316183
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1735663453
Short name T408
Test name
Test status
Simulation time 1041379947 ps
CPU time 1.75 seconds
Started Jul 06 05:57:37 PM PDT 24
Finished Jul 06 05:57:39 PM PDT 24
Peak memory 198688 kb
Host smart-29dff345-0e59-4573-827a-bee46132d8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735663453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1735663453
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.31987871
Short name T296
Test name
Test status
Simulation time 44350469558 ps
CPU time 23.29 seconds
Started Jul 06 05:57:32 PM PDT 24
Finished Jul 06 05:57:56 PM PDT 24
Peak memory 199916 kb
Host smart-beb24d58-6606-41c2-a493-3c1ca10e3997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31987871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.31987871
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3101014983
Short name T347
Test name
Test status
Simulation time 50523141977 ps
CPU time 36.76 seconds
Started Jul 06 06:01:31 PM PDT 24
Finished Jul 06 06:02:08 PM PDT 24
Peak memory 199904 kb
Host smart-6115f45f-c4f7-4ff7-b39b-ae91c177f56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101014983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3101014983
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.783752951
Short name T1088
Test name
Test status
Simulation time 138895532932 ps
CPU time 66.07 seconds
Started Jul 06 06:01:28 PM PDT 24
Finished Jul 06 06:02:34 PM PDT 24
Peak memory 199960 kb
Host smart-6c30a3f6-3b7a-49fd-9d6b-23120996aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783752951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.783752951
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.769256696
Short name T936
Test name
Test status
Simulation time 31007978606 ps
CPU time 12.14 seconds
Started Jul 06 06:01:29 PM PDT 24
Finished Jul 06 06:01:42 PM PDT 24
Peak memory 199836 kb
Host smart-d9c1517f-4d3d-4692-8701-38e2086cb455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769256696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.769256696
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3771863096
Short name T904
Test name
Test status
Simulation time 163591005846 ps
CPU time 30.08 seconds
Started Jul 06 06:01:29 PM PDT 24
Finished Jul 06 06:01:59 PM PDT 24
Peak memory 199964 kb
Host smart-96a00d90-e569-4be1-8ef9-a109e195bee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771863096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3771863096
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1986713900
Short name T581
Test name
Test status
Simulation time 19885520779 ps
CPU time 22.69 seconds
Started Jul 06 06:01:33 PM PDT 24
Finished Jul 06 06:01:55 PM PDT 24
Peak memory 199860 kb
Host smart-32cbf1a7-e1f7-49cf-a3e5-32a2e457b2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986713900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1986713900
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1538338920
Short name T210
Test name
Test status
Simulation time 41911797442 ps
CPU time 24.49 seconds
Started Jul 06 06:01:33 PM PDT 24
Finished Jul 06 06:01:58 PM PDT 24
Peak memory 199908 kb
Host smart-42947b4b-e38b-4a19-8053-e0c61439139b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538338920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1538338920
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2621779670
Short name T520
Test name
Test status
Simulation time 96586151658 ps
CPU time 265.57 seconds
Started Jul 06 06:01:36 PM PDT 24
Finished Jul 06 06:06:01 PM PDT 24
Peak memory 199944 kb
Host smart-8cbbfa90-1499-4a9f-988c-a96a440c4841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621779670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2621779670
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.741930844
Short name T901
Test name
Test status
Simulation time 31343950706 ps
CPU time 8.72 seconds
Started Jul 06 06:01:33 PM PDT 24
Finished Jul 06 06:01:42 PM PDT 24
Peak memory 197928 kb
Host smart-81805205-2fe4-4ccd-aa4b-2b00d35242b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741930844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.741930844
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3258693107
Short name T762
Test name
Test status
Simulation time 78572475676 ps
CPU time 252.51 seconds
Started Jul 06 06:01:33 PM PDT 24
Finished Jul 06 06:05:46 PM PDT 24
Peak memory 200008 kb
Host smart-1174b735-b31d-4617-80d5-328a4bc7399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258693107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3258693107
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1997307966
Short name T370
Test name
Test status
Simulation time 30456044 ps
CPU time 0.55 seconds
Started Jul 06 05:57:44 PM PDT 24
Finished Jul 06 05:57:45 PM PDT 24
Peak memory 194784 kb
Host smart-dfccea7a-6807-43e0-bfc9-588b366c0c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997307966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1997307966
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3860947188
Short name T1061
Test name
Test status
Simulation time 55682056916 ps
CPU time 88.54 seconds
Started Jul 06 05:57:41 PM PDT 24
Finished Jul 06 05:59:10 PM PDT 24
Peak memory 199988 kb
Host smart-f4711a90-a4ef-44f8-b4e9-0dba415c1b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860947188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3860947188
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1261499381
Short name T988
Test name
Test status
Simulation time 128327885633 ps
CPU time 45.51 seconds
Started Jul 06 05:57:41 PM PDT 24
Finished Jul 06 05:58:27 PM PDT 24
Peak memory 199868 kb
Host smart-a339df99-3b19-4e7a-b5e7-eb11a820932c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261499381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1261499381
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1154588065
Short name T1150
Test name
Test status
Simulation time 58680762968 ps
CPU time 96.94 seconds
Started Jul 06 05:57:40 PM PDT 24
Finished Jul 06 05:59:17 PM PDT 24
Peak memory 199972 kb
Host smart-da417289-e824-4552-9892-8f88213a7a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154588065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1154588065
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3195602558
Short name T884
Test name
Test status
Simulation time 9975934301 ps
CPU time 8.13 seconds
Started Jul 06 05:57:40 PM PDT 24
Finished Jul 06 05:57:48 PM PDT 24
Peak memory 199584 kb
Host smart-6a7870e1-121b-47b5-90e9-66d8bce6dc83
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195602558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3195602558
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.464524445
Short name T877
Test name
Test status
Simulation time 145684841292 ps
CPU time 225.28 seconds
Started Jul 06 05:57:45 PM PDT 24
Finished Jul 06 06:01:31 PM PDT 24
Peak memory 199972 kb
Host smart-df3bdde9-d839-43de-b7a0-ea355a6d7d5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464524445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.464524445
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3014069408
Short name T353
Test name
Test status
Simulation time 2206001694 ps
CPU time 4.19 seconds
Started Jul 06 05:57:41 PM PDT 24
Finished Jul 06 05:57:46 PM PDT 24
Peak memory 197312 kb
Host smart-413c213f-62b6-4b13-a272-8fdf82851a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014069408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3014069408
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2712005667
Short name T1101
Test name
Test status
Simulation time 390081003639 ps
CPU time 90.06 seconds
Started Jul 06 05:57:41 PM PDT 24
Finished Jul 06 05:59:11 PM PDT 24
Peak memory 208504 kb
Host smart-1f3e9cf4-b1e6-4e46-9407-35fccdd4d958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712005667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2712005667
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.140412277
Short name T538
Test name
Test status
Simulation time 19192295362 ps
CPU time 1052.8 seconds
Started Jul 06 05:57:54 PM PDT 24
Finished Jul 06 06:15:27 PM PDT 24
Peak memory 200000 kb
Host smart-5056f3f8-8b1a-4821-a65a-9173be92e555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=140412277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.140412277
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3844197106
Short name T489
Test name
Test status
Simulation time 3993558635 ps
CPU time 36.49 seconds
Started Jul 06 05:57:45 PM PDT 24
Finished Jul 06 05:58:22 PM PDT 24
Peak memory 198160 kb
Host smart-28e745d3-8697-45a9-be02-e1167b82f765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3844197106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3844197106
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.682123290
Short name T478
Test name
Test status
Simulation time 135224190423 ps
CPU time 199.27 seconds
Started Jul 06 05:57:42 PM PDT 24
Finished Jul 06 06:01:02 PM PDT 24
Peak memory 199912 kb
Host smart-70d00c78-847f-4e6e-bd03-95dfa1b39d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682123290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.682123290
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2760113719
Short name T315
Test name
Test status
Simulation time 6041926492 ps
CPU time 9.07 seconds
Started Jul 06 06:00:05 PM PDT 24
Finished Jul 06 06:00:14 PM PDT 24
Peak memory 196184 kb
Host smart-fec1c1f5-ca1e-4c80-8eac-b156e1351763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760113719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2760113719
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2802779910
Short name T46
Test name
Test status
Simulation time 147754990 ps
CPU time 0.79 seconds
Started Jul 06 05:57:37 PM PDT 24
Finished Jul 06 05:57:38 PM PDT 24
Peak memory 197828 kb
Host smart-a5a6fb8a-3fc1-4132-84a5-0ed1609dd644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802779910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2802779910
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1211395270
Short name T845
Test name
Test status
Simulation time 660931474015 ps
CPU time 444.51 seconds
Started Jul 06 05:57:45 PM PDT 24
Finished Jul 06 06:05:10 PM PDT 24
Peak memory 216664 kb
Host smart-58698333-c247-4960-806c-a91d27f44ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211395270 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1211395270
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1124290584
Short name T334
Test name
Test status
Simulation time 1403441689 ps
CPU time 1.45 seconds
Started Jul 06 05:57:45 PM PDT 24
Finished Jul 06 05:57:47 PM PDT 24
Peak memory 198504 kb
Host smart-f1829c00-e195-4731-a0dd-6f2e3112ecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124290584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1124290584
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1424325375
Short name T1033
Test name
Test status
Simulation time 32973699563 ps
CPU time 58.33 seconds
Started Jul 06 05:57:45 PM PDT 24
Finished Jul 06 05:58:44 PM PDT 24
Peak memory 199960 kb
Host smart-936f6a34-711c-4c8d-a523-8ff106b7156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424325375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1424325375
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2111869835
Short name T350
Test name
Test status
Simulation time 124169327189 ps
CPU time 65.45 seconds
Started Jul 06 06:01:35 PM PDT 24
Finished Jul 06 06:02:40 PM PDT 24
Peak memory 199928 kb
Host smart-19de025a-fe3b-492a-afca-b6cc58e0ac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111869835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2111869835
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3140108671
Short name T851
Test name
Test status
Simulation time 131962334058 ps
CPU time 30.16 seconds
Started Jul 06 06:01:34 PM PDT 24
Finished Jul 06 06:02:04 PM PDT 24
Peak memory 199888 kb
Host smart-9c53e7ef-93b9-4620-85ba-c40f33f900e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140108671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3140108671
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3008836821
Short name T257
Test name
Test status
Simulation time 56309241210 ps
CPU time 26.31 seconds
Started Jul 06 06:01:36 PM PDT 24
Finished Jul 06 06:02:03 PM PDT 24
Peak memory 199980 kb
Host smart-00d32f0c-d617-4da6-ae74-ae258a131753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008836821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3008836821
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3521196874
Short name T306
Test name
Test status
Simulation time 97958515187 ps
CPU time 151.9 seconds
Started Jul 06 06:01:34 PM PDT 24
Finished Jul 06 06:04:06 PM PDT 24
Peak memory 199944 kb
Host smart-1138c664-a1a9-4fbd-bf14-94f5d8257019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521196874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3521196874
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2762776238
Short name T245
Test name
Test status
Simulation time 111522093860 ps
CPU time 161.27 seconds
Started Jul 06 06:01:39 PM PDT 24
Finished Jul 06 06:04:20 PM PDT 24
Peak memory 199964 kb
Host smart-0d234ec3-3887-4eed-8a63-0f9133a12137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762776238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2762776238
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1840280684
Short name T65
Test name
Test status
Simulation time 220681856575 ps
CPU time 76.68 seconds
Started Jul 06 06:01:43 PM PDT 24
Finished Jul 06 06:02:59 PM PDT 24
Peak memory 200004 kb
Host smart-a60b82d2-32a5-40b1-bf14-079b587955db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840280684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1840280684
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2027534672
Short name T731
Test name
Test status
Simulation time 1685223272 ps
CPU time 3.82 seconds
Started Jul 06 06:01:40 PM PDT 24
Finished Jul 06 06:01:44 PM PDT 24
Peak memory 199704 kb
Host smart-e04641a8-ad09-4127-be8e-329621e715d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027534672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2027534672
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2554591193
Short name T324
Test name
Test status
Simulation time 85020431112 ps
CPU time 119.25 seconds
Started Jul 06 06:01:40 PM PDT 24
Finished Jul 06 06:03:39 PM PDT 24
Peak memory 199964 kb
Host smart-dc54dc21-00f6-45de-bc0f-4d4da7659c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554591193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2554591193
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3202462903
Short name T632
Test name
Test status
Simulation time 79407779 ps
CPU time 0.62 seconds
Started Jul 06 05:57:54 PM PDT 24
Finished Jul 06 05:57:55 PM PDT 24
Peak memory 195304 kb
Host smart-ed3676e7-2bba-4d38-91d5-e51d837a97c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202462903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3202462903
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1257933511
Short name T1060
Test name
Test status
Simulation time 38636908130 ps
CPU time 18.67 seconds
Started Jul 06 05:57:46 PM PDT 24
Finished Jul 06 05:58:05 PM PDT 24
Peak memory 199924 kb
Host smart-e3ad0a70-1d74-4977-a064-abd19792f0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257933511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1257933511
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.4248439213
Short name T589
Test name
Test status
Simulation time 96602111731 ps
CPU time 143.36 seconds
Started Jul 06 05:57:54 PM PDT 24
Finished Jul 06 06:00:17 PM PDT 24
Peak memory 199908 kb
Host smart-58b9a854-89f0-4df3-af00-fe62fdfa4c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248439213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4248439213
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1466722901
Short name T899
Test name
Test status
Simulation time 55285183231 ps
CPU time 60.61 seconds
Started Jul 06 05:57:46 PM PDT 24
Finished Jul 06 05:58:47 PM PDT 24
Peak memory 199968 kb
Host smart-24f7b514-bd3a-4398-b121-a354b2d82095
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466722901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1466722901
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1779096331
Short name T561
Test name
Test status
Simulation time 150745682625 ps
CPU time 1088.67 seconds
Started Jul 06 05:57:51 PM PDT 24
Finished Jul 06 06:16:00 PM PDT 24
Peak memory 199920 kb
Host smart-c3898792-0b5b-4613-9e73-1e0ef6dba020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779096331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1779096331
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2570262889
Short name T404
Test name
Test status
Simulation time 5216118446 ps
CPU time 3.76 seconds
Started Jul 06 05:57:49 PM PDT 24
Finished Jul 06 05:57:54 PM PDT 24
Peak memory 199992 kb
Host smart-9d4ac3e4-4cf3-4b26-94d5-9238558711c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570262889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2570262889
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1227543205
Short name T443
Test name
Test status
Simulation time 104572715846 ps
CPU time 46.56 seconds
Started Jul 06 05:57:54 PM PDT 24
Finished Jul 06 05:58:40 PM PDT 24
Peak memory 198384 kb
Host smart-77a7d71b-ee05-4a80-82d4-dcf8bae874d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227543205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1227543205
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1223426229
Short name T1008
Test name
Test status
Simulation time 7032977893 ps
CPU time 408.21 seconds
Started Jul 06 05:57:51 PM PDT 24
Finished Jul 06 06:04:40 PM PDT 24
Peak memory 199944 kb
Host smart-0bd64a57-8d4e-4ffb-b429-783f12a95e84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223426229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1223426229
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3005063818
Short name T355
Test name
Test status
Simulation time 6754787143 ps
CPU time 62.2 seconds
Started Jul 06 05:57:47 PM PDT 24
Finished Jul 06 05:58:49 PM PDT 24
Peak memory 198816 kb
Host smart-84fa9567-dec8-4ed0-9320-90a4609a2dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3005063818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3005063818
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3565251910
Short name T991
Test name
Test status
Simulation time 116510682363 ps
CPU time 183.82 seconds
Started Jul 06 05:57:45 PM PDT 24
Finished Jul 06 06:00:49 PM PDT 24
Peak memory 199992 kb
Host smart-93d3d0c0-a7a2-46f9-be8b-f3d55490929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565251910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3565251910
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2515670073
Short name T1081
Test name
Test status
Simulation time 3331060702 ps
CPU time 1.93 seconds
Started Jul 06 05:57:47 PM PDT 24
Finished Jul 06 05:57:49 PM PDT 24
Peak memory 196208 kb
Host smart-4c8b235c-582f-4958-a37d-26ca5e16f5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515670073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2515670073
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.4044917307
Short name T887
Test name
Test status
Simulation time 5866700782 ps
CPU time 13.53 seconds
Started Jul 06 05:57:47 PM PDT 24
Finished Jul 06 05:58:01 PM PDT 24
Peak memory 199116 kb
Host smart-07e6dac0-6d5e-434a-a789-cb89b3cb6a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044917307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4044917307
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.580095834
Short name T177
Test name
Test status
Simulation time 237924662774 ps
CPU time 551.49 seconds
Started Jul 06 05:57:54 PM PDT 24
Finished Jul 06 06:07:06 PM PDT 24
Peak memory 224920 kb
Host smart-bdb2624b-20f0-4b60-a51f-8a03bebc85f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580095834 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.580095834
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3123480888
Short name T448
Test name
Test status
Simulation time 6157584243 ps
CPU time 25.93 seconds
Started Jul 06 05:57:49 PM PDT 24
Finished Jul 06 05:58:16 PM PDT 24
Peak memory 199908 kb
Host smart-939ecefb-ec0c-4179-8eb8-86063e2b5744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123480888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3123480888
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1793027581
Short name T975
Test name
Test status
Simulation time 68458937306 ps
CPU time 24.55 seconds
Started Jul 06 05:57:45 PM PDT 24
Finished Jul 06 05:58:10 PM PDT 24
Peak memory 199824 kb
Host smart-68130337-4955-4190-bc0b-9e164a5a9a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793027581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1793027581
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1325797263
Short name T227
Test name
Test status
Simulation time 188965577606 ps
CPU time 15.83 seconds
Started Jul 06 06:01:42 PM PDT 24
Finished Jul 06 06:01:58 PM PDT 24
Peak memory 199900 kb
Host smart-91deb35e-dc3e-4146-a65a-e3023746e358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325797263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1325797263
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3530151652
Short name T409
Test name
Test status
Simulation time 31349450138 ps
CPU time 28.57 seconds
Started Jul 06 06:01:42 PM PDT 24
Finished Jul 06 06:02:11 PM PDT 24
Peak memory 199936 kb
Host smart-1e7fac18-34e6-4559-80d7-299f922d3c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530151652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3530151652
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2758427315
Short name T197
Test name
Test status
Simulation time 19378491553 ps
CPU time 31.38 seconds
Started Jul 06 06:01:41 PM PDT 24
Finished Jul 06 06:02:12 PM PDT 24
Peak memory 199984 kb
Host smart-230cea29-f45d-42cb-86b5-df8bb87d7f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758427315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2758427315
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3038122411
Short name T346
Test name
Test status
Simulation time 12289362040 ps
CPU time 19.17 seconds
Started Jul 06 06:01:41 PM PDT 24
Finished Jul 06 06:02:00 PM PDT 24
Peak memory 199880 kb
Host smart-6c8a62b6-97f1-4de6-ae3d-f590ed92c18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038122411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3038122411
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.225091927
Short name T543
Test name
Test status
Simulation time 21159716773 ps
CPU time 16.11 seconds
Started Jul 06 06:01:40 PM PDT 24
Finished Jul 06 06:01:56 PM PDT 24
Peak memory 199996 kb
Host smart-97379fb9-d30b-43c4-a4af-2f673d239353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225091927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.225091927
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2823986053
Short name T702
Test name
Test status
Simulation time 59759750050 ps
CPU time 23.32 seconds
Started Jul 06 06:01:49 PM PDT 24
Finished Jul 06 06:02:13 PM PDT 24
Peak memory 199988 kb
Host smart-a0eab976-4504-4d40-b568-4b04f8749232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823986053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2823986053
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1108293290
Short name T964
Test name
Test status
Simulation time 238759885266 ps
CPU time 101.32 seconds
Started Jul 06 06:01:49 PM PDT 24
Finished Jul 06 06:03:31 PM PDT 24
Peak memory 199988 kb
Host smart-39a9c75f-9830-40b3-b7b6-e89f205816f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108293290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1108293290
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1583535594
Short name T377
Test name
Test status
Simulation time 47033751 ps
CPU time 0.57 seconds
Started Jul 06 05:57:57 PM PDT 24
Finished Jul 06 05:57:58 PM PDT 24
Peak memory 195252 kb
Host smart-83652b2c-5a27-4ecf-9aca-1fd205aabc11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583535594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1583535594
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3307190868
Short name T993
Test name
Test status
Simulation time 75376492335 ps
CPU time 30.29 seconds
Started Jul 06 05:57:51 PM PDT 24
Finished Jul 06 05:58:22 PM PDT 24
Peak memory 199896 kb
Host smart-8d081368-dce4-4089-a15f-af573e911973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307190868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3307190868
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.743778142
Short name T1175
Test name
Test status
Simulation time 134150710198 ps
CPU time 30.05 seconds
Started Jul 06 05:57:49 PM PDT 24
Finished Jul 06 05:58:20 PM PDT 24
Peak memory 199916 kb
Host smart-dffab4e9-cae6-4a8d-a00a-5157dff8c082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743778142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.743778142
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2138690542
Short name T927
Test name
Test status
Simulation time 13449810254 ps
CPU time 13.22 seconds
Started Jul 06 05:57:50 PM PDT 24
Finished Jul 06 05:58:04 PM PDT 24
Peak memory 199856 kb
Host smart-31156c82-3a47-4cac-8c1d-5f9d61e583b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138690542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2138690542
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1629512313
Short name T924
Test name
Test status
Simulation time 45834370591 ps
CPU time 23.4 seconds
Started Jul 06 05:57:50 PM PDT 24
Finished Jul 06 05:58:14 PM PDT 24
Peak memory 199960 kb
Host smart-1a16b20d-613f-4f13-8cb7-c7edeb3fb65c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629512313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1629512313
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2046822859
Short name T938
Test name
Test status
Simulation time 146536187115 ps
CPU time 403.2 seconds
Started Jul 06 05:57:52 PM PDT 24
Finished Jul 06 06:04:36 PM PDT 24
Peak memory 199884 kb
Host smart-1543bf00-76bd-409e-baff-a5a7893d3f46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046822859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2046822859
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3544131866
Short name T477
Test name
Test status
Simulation time 2365253262 ps
CPU time 9.83 seconds
Started Jul 06 05:57:50 PM PDT 24
Finished Jul 06 05:58:01 PM PDT 24
Peak memory 198924 kb
Host smart-3ddbf509-bb60-4bf7-af78-93b758a555b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544131866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3544131866
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.328189876
Short name T447
Test name
Test status
Simulation time 40507114563 ps
CPU time 14.34 seconds
Started Jul 06 05:57:53 PM PDT 24
Finished Jul 06 05:58:08 PM PDT 24
Peak memory 200096 kb
Host smart-9c808de8-e855-499f-9a08-8db45d384188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328189876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.328189876
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3146413739
Short name T519
Test name
Test status
Simulation time 24172905482 ps
CPU time 251.31 seconds
Started Jul 06 05:57:52 PM PDT 24
Finished Jul 06 06:02:04 PM PDT 24
Peak memory 200044 kb
Host smart-ca4c3c65-a6be-466b-9454-0b9e428a2c7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146413739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3146413739
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2042554156
Short name T998
Test name
Test status
Simulation time 5555383960 ps
CPU time 48.73 seconds
Started Jul 06 05:57:52 PM PDT 24
Finished Jul 06 05:58:41 PM PDT 24
Peak memory 198364 kb
Host smart-a491aa19-50ac-4220-8f6d-88de28db14b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2042554156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2042554156
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3859660260
Short name T596
Test name
Test status
Simulation time 177570026698 ps
CPU time 15.92 seconds
Started Jul 06 05:57:51 PM PDT 24
Finished Jul 06 05:58:07 PM PDT 24
Peak memory 199920 kb
Host smart-41ef38e2-906d-448e-aa64-7cd53f0d9119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859660260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3859660260
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.4223025336
Short name T573
Test name
Test status
Simulation time 65397380755 ps
CPU time 84.93 seconds
Started Jul 06 05:57:50 PM PDT 24
Finished Jul 06 05:59:16 PM PDT 24
Peak memory 195856 kb
Host smart-d2073372-724d-4695-9ead-57411a9e8ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223025336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.4223025336
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1861341760
Short name T983
Test name
Test status
Simulation time 543543210 ps
CPU time 1.16 seconds
Started Jul 06 05:57:50 PM PDT 24
Finished Jul 06 05:57:52 PM PDT 24
Peak memory 198744 kb
Host smart-fc2ed02c-71d4-417e-aa15-e109a4714bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861341760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1861341760
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2275850695
Short name T1134
Test name
Test status
Simulation time 40579589229 ps
CPU time 603.71 seconds
Started Jul 06 05:57:49 PM PDT 24
Finished Jul 06 06:07:53 PM PDT 24
Peak memory 216696 kb
Host smart-fe293605-4ec2-4258-b527-8f744d90fe46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275850695 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2275850695
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3478532433
Short name T497
Test name
Test status
Simulation time 398042680 ps
CPU time 1.7 seconds
Started Jul 06 05:57:50 PM PDT 24
Finished Jul 06 05:57:52 PM PDT 24
Peak memory 199036 kb
Host smart-0ccaddcb-7a23-47d7-84c3-8ac27e5e7457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478532433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3478532433
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3845350481
Short name T871
Test name
Test status
Simulation time 50121861366 ps
CPU time 15.94 seconds
Started Jul 06 05:57:50 PM PDT 24
Finished Jul 06 05:58:07 PM PDT 24
Peak memory 199892 kb
Host smart-db79fa98-8c4e-422d-91e9-baecf7ff714c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845350481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3845350481
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3331663478
Short name T1133
Test name
Test status
Simulation time 58813514141 ps
CPU time 32.83 seconds
Started Jul 06 06:01:46 PM PDT 24
Finished Jul 06 06:02:19 PM PDT 24
Peak memory 199964 kb
Host smart-f12bec01-7e26-4a91-ba85-38ec486c5fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331663478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3331663478
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.620154693
Short name T677
Test name
Test status
Simulation time 67342604213 ps
CPU time 9.2 seconds
Started Jul 06 06:01:49 PM PDT 24
Finished Jul 06 06:01:58 PM PDT 24
Peak memory 199932 kb
Host smart-8fc1ff0f-3617-4522-a451-6bd349508772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620154693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.620154693
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3315584924
Short name T214
Test name
Test status
Simulation time 28589203337 ps
CPU time 13.16 seconds
Started Jul 06 06:01:45 PM PDT 24
Finished Jul 06 06:01:58 PM PDT 24
Peak memory 199900 kb
Host smart-4b1f5d00-482b-4db5-ae03-ad1a5c05410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315584924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3315584924
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2012274042
Short name T922
Test name
Test status
Simulation time 40508842844 ps
CPU time 35.08 seconds
Started Jul 06 06:01:44 PM PDT 24
Finished Jul 06 06:02:19 PM PDT 24
Peak memory 199928 kb
Host smart-863e996a-4f9c-4654-bbc4-8d023b3eca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012274042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2012274042
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1145464286
Short name T145
Test name
Test status
Simulation time 43797053107 ps
CPU time 26.64 seconds
Started Jul 06 06:01:46 PM PDT 24
Finished Jul 06 06:02:12 PM PDT 24
Peak memory 199964 kb
Host smart-83ab15b7-9fdc-47ce-a20a-db4a1e43b8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145464286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1145464286
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.933043501
Short name T629
Test name
Test status
Simulation time 36617074589 ps
CPU time 18.33 seconds
Started Jul 06 06:01:46 PM PDT 24
Finished Jul 06 06:02:05 PM PDT 24
Peak memory 199944 kb
Host smart-a1654729-19fe-4245-b58a-45951a6be7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933043501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.933043501
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2792247288
Short name T342
Test name
Test status
Simulation time 47004915350 ps
CPU time 38.58 seconds
Started Jul 06 06:01:45 PM PDT 24
Finished Jul 06 06:02:24 PM PDT 24
Peak memory 199996 kb
Host smart-ac5f6440-e02c-4dfb-be75-d33e9427e1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792247288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2792247288
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.819083263
Short name T546
Test name
Test status
Simulation time 46616364950 ps
CPU time 66.36 seconds
Started Jul 06 06:01:46 PM PDT 24
Finished Jul 06 06:02:52 PM PDT 24
Peak memory 199936 kb
Host smart-6ad40c64-a445-4ef8-8f3e-6cd4063ecfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819083263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.819083263
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.4166599321
Short name T60
Test name
Test status
Simulation time 9480238797 ps
CPU time 10.95 seconds
Started Jul 06 06:01:43 PM PDT 24
Finished Jul 06 06:01:54 PM PDT 24
Peak memory 199696 kb
Host smart-e0b3452e-03bf-4fad-9581-5804fafad988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166599321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.4166599321
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3976106595
Short name T453
Test name
Test status
Simulation time 12308506 ps
CPU time 0.56 seconds
Started Jul 06 05:57:56 PM PDT 24
Finished Jul 06 05:57:57 PM PDT 24
Peak memory 195552 kb
Host smart-f3e596c9-0184-4fb2-95af-6986bd86fa74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976106595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3976106595
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3052768385
Short name T1089
Test name
Test status
Simulation time 100175728507 ps
CPU time 34.85 seconds
Started Jul 06 05:57:55 PM PDT 24
Finished Jul 06 05:58:31 PM PDT 24
Peak memory 199932 kb
Host smart-ea9efc78-a3eb-4d7f-aaac-a5af76297fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052768385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3052768385
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.4159179969
Short name T263
Test name
Test status
Simulation time 90194847451 ps
CPU time 177.9 seconds
Started Jul 06 05:57:55 PM PDT 24
Finished Jul 06 06:00:54 PM PDT 24
Peak memory 199952 kb
Host smart-095cdc69-0797-43b3-bb1a-e069c138bc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159179969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.4159179969
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3093495670
Short name T43
Test name
Test status
Simulation time 132568730348 ps
CPU time 17.32 seconds
Started Jul 06 05:57:55 PM PDT 24
Finished Jul 06 05:58:13 PM PDT 24
Peak memory 199936 kb
Host smart-2ebff205-ec10-4296-b599-356b77c47261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093495670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3093495670
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2113629012
Short name T6
Test name
Test status
Simulation time 46700958111 ps
CPU time 70.49 seconds
Started Jul 06 05:57:56 PM PDT 24
Finished Jul 06 05:59:07 PM PDT 24
Peak memory 199972 kb
Host smart-3cead52f-6753-40d7-83a0-c38fa1bf0295
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113629012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2113629012
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.900771547
Short name T1142
Test name
Test status
Simulation time 126772553500 ps
CPU time 393.41 seconds
Started Jul 06 05:57:55 PM PDT 24
Finished Jul 06 06:04:29 PM PDT 24
Peak memory 199984 kb
Host smart-6a44f970-693b-46ae-ae64-e059366b2095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900771547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.900771547
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1363395990
Short name T367
Test name
Test status
Simulation time 3210599117 ps
CPU time 7.25 seconds
Started Jul 06 05:57:58 PM PDT 24
Finished Jul 06 05:58:05 PM PDT 24
Peak memory 198720 kb
Host smart-189cf86d-b942-41b3-b6c1-912a36b79336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363395990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1363395990
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3315379634
Short name T323
Test name
Test status
Simulation time 77179014748 ps
CPU time 34.71 seconds
Started Jul 06 05:57:55 PM PDT 24
Finished Jul 06 05:58:30 PM PDT 24
Peak memory 199220 kb
Host smart-15b044cb-ee4a-47af-97a6-ad509b0f3bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315379634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3315379634
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1181142445
Short name T1095
Test name
Test status
Simulation time 20055026416 ps
CPU time 189.78 seconds
Started Jul 06 05:57:56 PM PDT 24
Finished Jul 06 06:01:06 PM PDT 24
Peak memory 199904 kb
Host smart-98f86eec-c2f8-44f7-96ed-0821c339e702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1181142445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1181142445
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2055932811
Short name T611
Test name
Test status
Simulation time 4352299541 ps
CPU time 17.45 seconds
Started Jul 06 05:57:55 PM PDT 24
Finished Jul 06 05:58:12 PM PDT 24
Peak memory 199404 kb
Host smart-9544558e-f010-47ec-8e98-a8b18203e562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055932811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2055932811
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2950580372
Short name T979
Test name
Test status
Simulation time 101746427499 ps
CPU time 85.43 seconds
Started Jul 06 05:57:56 PM PDT 24
Finished Jul 06 05:59:22 PM PDT 24
Peak memory 200000 kb
Host smart-607b1da5-9a55-439c-b88d-24ea64b99835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950580372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2950580372
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.810708857
Short name T919
Test name
Test status
Simulation time 35095971850 ps
CPU time 54.15 seconds
Started Jul 06 05:57:55 PM PDT 24
Finished Jul 06 05:58:50 PM PDT 24
Peak memory 196260 kb
Host smart-03c1bbff-9f46-4ad6-8ca4-f814bf6d6da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810708857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.810708857
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2174639942
Short name T723
Test name
Test status
Simulation time 291059985 ps
CPU time 1.73 seconds
Started Jul 06 05:57:55 PM PDT 24
Finished Jul 06 05:57:57 PM PDT 24
Peak memory 199076 kb
Host smart-f74e24f3-93ee-427f-953b-2fb71d9218c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174639942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2174639942
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.4285490203
Short name T53
Test name
Test status
Simulation time 82074478721 ps
CPU time 817.07 seconds
Started Jul 06 05:57:56 PM PDT 24
Finished Jul 06 06:11:33 PM PDT 24
Peak memory 224828 kb
Host smart-923c3411-21d0-4c35-ac2f-544d8c6dc6ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285490203 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.4285490203
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2743941132
Short name T869
Test name
Test status
Simulation time 1474448775 ps
CPU time 1.39 seconds
Started Jul 06 05:57:58 PM PDT 24
Finished Jul 06 05:57:59 PM PDT 24
Peak memory 198480 kb
Host smart-04b6f7c7-abca-4727-91d3-fdc6d8bbaeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743941132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2743941132
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1507989086
Short name T1156
Test name
Test status
Simulation time 55318717094 ps
CPU time 45.46 seconds
Started Jul 06 05:57:56 PM PDT 24
Finished Jul 06 05:58:42 PM PDT 24
Peak memory 199988 kb
Host smart-6534df8e-f9bb-4e7f-9b1f-a1cc7eff4a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507989086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1507989086
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2812040907
Short name T166
Test name
Test status
Simulation time 4848837797 ps
CPU time 5.07 seconds
Started Jul 06 06:01:49 PM PDT 24
Finished Jul 06 06:01:54 PM PDT 24
Peak memory 199976 kb
Host smart-623bc94f-81a5-4f61-aeee-84ecb3015729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812040907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2812040907
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2833356100
Short name T331
Test name
Test status
Simulation time 116845807163 ps
CPU time 81.74 seconds
Started Jul 06 06:01:51 PM PDT 24
Finished Jul 06 06:03:13 PM PDT 24
Peak memory 199924 kb
Host smart-4fcef213-5f7a-48c3-adc5-7a49e3d328e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833356100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2833356100
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3283152191
Short name T1104
Test name
Test status
Simulation time 100427642259 ps
CPU time 16.43 seconds
Started Jul 06 06:01:51 PM PDT 24
Finished Jul 06 06:02:08 PM PDT 24
Peak memory 199948 kb
Host smart-d0282281-08dc-4764-a10a-90cc962f5a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283152191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3283152191
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1667730684
Short name T200
Test name
Test status
Simulation time 114416289137 ps
CPU time 294.14 seconds
Started Jul 06 06:01:53 PM PDT 24
Finished Jul 06 06:06:47 PM PDT 24
Peak memory 199868 kb
Host smart-3eba0214-20d5-40b7-98bc-f47d1034f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667730684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1667730684
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3433786014
Short name T1036
Test name
Test status
Simulation time 42252574920 ps
CPU time 42.55 seconds
Started Jul 06 06:01:51 PM PDT 24
Finished Jul 06 06:02:33 PM PDT 24
Peak memory 199996 kb
Host smart-5b7bf3ce-bb20-4831-8605-56837603bd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433786014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3433786014
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1681255573
Short name T822
Test name
Test status
Simulation time 158717307923 ps
CPU time 50.03 seconds
Started Jul 06 06:01:52 PM PDT 24
Finished Jul 06 06:02:42 PM PDT 24
Peak memory 200192 kb
Host smart-70e57ba4-cb3d-4d82-b335-eb8e8475fc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681255573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1681255573
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3189499840
Short name T243
Test name
Test status
Simulation time 288524413905 ps
CPU time 91.86 seconds
Started Jul 06 06:01:50 PM PDT 24
Finished Jul 06 06:03:22 PM PDT 24
Peak memory 199944 kb
Host smart-506dc534-229c-4acd-a9f7-7f5feae1a57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189499840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3189499840
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.617935609
Short name T1119
Test name
Test status
Simulation time 189214956904 ps
CPU time 65.34 seconds
Started Jul 06 06:01:52 PM PDT 24
Finished Jul 06 06:02:57 PM PDT 24
Peak memory 200192 kb
Host smart-ecf39e87-4ab2-48ca-8e81-ca461b25f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617935609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.617935609
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1611121284
Short name T248
Test name
Test status
Simulation time 160560680275 ps
CPU time 131.28 seconds
Started Jul 06 06:01:51 PM PDT 24
Finished Jul 06 06:04:03 PM PDT 24
Peak memory 199868 kb
Host smart-f0ca60e1-62a9-4118-8889-78971659f636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611121284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1611121284
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2624602555
Short name T1053
Test name
Test status
Simulation time 31848819 ps
CPU time 0.53 seconds
Started Jul 06 05:57:59 PM PDT 24
Finished Jul 06 05:58:00 PM PDT 24
Peak memory 194308 kb
Host smart-163e336b-394c-46eb-9c1e-a7b366a8aa6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624602555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2624602555
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3309175868
Short name T1058
Test name
Test status
Simulation time 30389522551 ps
CPU time 21.64 seconds
Started Jul 06 05:58:02 PM PDT 24
Finished Jul 06 05:58:24 PM PDT 24
Peak memory 200032 kb
Host smart-ac981b1f-6f6e-48b8-8d1f-790dacc3f5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309175868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3309175868
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1878607938
Short name T930
Test name
Test status
Simulation time 176566176644 ps
CPU time 129.13 seconds
Started Jul 06 05:58:01 PM PDT 24
Finished Jul 06 06:00:10 PM PDT 24
Peak memory 199980 kb
Host smart-0b12d885-6efa-4c4a-8041-ff983736a7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878607938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1878607938
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2646552586
Short name T880
Test name
Test status
Simulation time 139673191349 ps
CPU time 82.17 seconds
Started Jul 06 05:58:06 PM PDT 24
Finished Jul 06 05:59:29 PM PDT 24
Peak memory 199272 kb
Host smart-99c65499-4549-404f-895b-ed3c6ae1c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646552586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2646552586
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.4249303885
Short name T423
Test name
Test status
Simulation time 64018274450 ps
CPU time 24.91 seconds
Started Jul 06 05:57:59 PM PDT 24
Finished Jul 06 05:58:24 PM PDT 24
Peak memory 199792 kb
Host smart-bf3e57d3-7d24-46b7-b141-8e811c6c07bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249303885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4249303885
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.60795131
Short name T591
Test name
Test status
Simulation time 152418771056 ps
CPU time 389.3 seconds
Started Jul 06 05:58:00 PM PDT 24
Finished Jul 06 06:04:30 PM PDT 24
Peak memory 199900 kb
Host smart-3838c098-5969-4586-a49e-63e4693fe221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60795131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.60795131
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.859726458
Short name T436
Test name
Test status
Simulation time 2170527072 ps
CPU time 2.8 seconds
Started Jul 06 05:58:00 PM PDT 24
Finished Jul 06 05:58:03 PM PDT 24
Peak memory 199952 kb
Host smart-c3a38c1e-fa4a-4ace-93fe-afd479de85a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859726458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.859726458
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1449579832
Short name T650
Test name
Test status
Simulation time 64876134409 ps
CPU time 109.77 seconds
Started Jul 06 05:58:00 PM PDT 24
Finished Jul 06 05:59:50 PM PDT 24
Peak memory 200204 kb
Host smart-f63aec80-85a3-4d06-a5ba-c745da9e51aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449579832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1449579832
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2805686291
Short name T81
Test name
Test status
Simulation time 22866831592 ps
CPU time 1140.46 seconds
Started Jul 06 05:58:03 PM PDT 24
Finished Jul 06 06:17:04 PM PDT 24
Peak memory 199936 kb
Host smart-a81aba1a-3562-4a4d-8372-880e96a56e24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805686291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2805686291
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2022979147
Short name T1042
Test name
Test status
Simulation time 6088961993 ps
CPU time 57.52 seconds
Started Jul 06 05:58:06 PM PDT 24
Finished Jul 06 05:59:04 PM PDT 24
Peak memory 198224 kb
Host smart-dcf163b9-4c13-4b92-a143-16d2a5e58160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022979147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2022979147
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2459467116
Short name T809
Test name
Test status
Simulation time 15221779926 ps
CPU time 24.57 seconds
Started Jul 06 05:58:00 PM PDT 24
Finished Jul 06 05:58:25 PM PDT 24
Peak memory 199844 kb
Host smart-72de878f-8748-42c1-a954-5d14b8de4195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459467116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2459467116
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3613019733
Short name T278
Test name
Test status
Simulation time 5866180986 ps
CPU time 1.54 seconds
Started Jul 06 05:58:06 PM PDT 24
Finished Jul 06 05:58:08 PM PDT 24
Peak memory 196160 kb
Host smart-992a31ba-b96c-455f-91ac-11a52bc20418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613019733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3613019733
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1316163975
Short name T916
Test name
Test status
Simulation time 421413755 ps
CPU time 1.2 seconds
Started Jul 06 05:57:55 PM PDT 24
Finished Jul 06 05:57:57 PM PDT 24
Peak memory 199888 kb
Host smart-b5d5502b-80b5-4aba-aa8b-03cf3510b05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316163975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1316163975
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3753397164
Short name T1027
Test name
Test status
Simulation time 200359588150 ps
CPU time 624.78 seconds
Started Jul 06 05:57:59 PM PDT 24
Finished Jul 06 06:08:25 PM PDT 24
Peak memory 208324 kb
Host smart-e759e1bb-638a-4ee5-bab8-87156b6eb9fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753397164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3753397164
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3476960473
Short name T305
Test name
Test status
Simulation time 27233845289 ps
CPU time 332.85 seconds
Started Jul 06 05:58:06 PM PDT 24
Finished Jul 06 06:03:39 PM PDT 24
Peak memory 215904 kb
Host smart-c1d4c06e-53cc-41be-ac41-53efc1d5e3b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476960473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3476960473
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.361286777
Short name T637
Test name
Test status
Simulation time 6585590112 ps
CPU time 19.65 seconds
Started Jul 06 05:58:00 PM PDT 24
Finished Jul 06 05:58:20 PM PDT 24
Peak memory 199564 kb
Host smart-4d9caa50-bef2-4c43-bc57-ddc247e2b73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361286777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.361286777
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.4172203916
Short name T704
Test name
Test status
Simulation time 38365211393 ps
CPU time 7.18 seconds
Started Jul 06 05:57:57 PM PDT 24
Finished Jul 06 05:58:04 PM PDT 24
Peak memory 199660 kb
Host smart-ee19c316-9bac-4f0f-965d-1e159077ffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172203916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.4172203916
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.52212449
Short name T621
Test name
Test status
Simulation time 8270486687 ps
CPU time 6.85 seconds
Started Jul 06 06:01:51 PM PDT 24
Finished Jul 06 06:01:58 PM PDT 24
Peak memory 197352 kb
Host smart-87c5487b-5eee-4f5f-b482-cdb8be2a1ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52212449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.52212449
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3773335141
Short name T150
Test name
Test status
Simulation time 24572864622 ps
CPU time 8.17 seconds
Started Jul 06 06:01:49 PM PDT 24
Finished Jul 06 06:01:58 PM PDT 24
Peak memory 199940 kb
Host smart-b98526ae-964f-4005-9290-06c77127cf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773335141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3773335141
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.405479318
Short name T909
Test name
Test status
Simulation time 21965288356 ps
CPU time 35.88 seconds
Started Jul 06 06:01:51 PM PDT 24
Finished Jul 06 06:02:27 PM PDT 24
Peak memory 199972 kb
Host smart-200fa5ab-9267-472c-8f50-e7f9d52ea298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405479318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.405479318
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.699127493
Short name T761
Test name
Test status
Simulation time 46864154216 ps
CPU time 38.91 seconds
Started Jul 06 06:01:55 PM PDT 24
Finished Jul 06 06:02:35 PM PDT 24
Peak memory 199972 kb
Host smart-7572139d-a158-42ab-9945-4293a519a2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699127493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.699127493
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1053684444
Short name T1063
Test name
Test status
Simulation time 285399599956 ps
CPU time 123.39 seconds
Started Jul 06 06:01:55 PM PDT 24
Finished Jul 06 06:03:58 PM PDT 24
Peak memory 200000 kb
Host smart-80adf7fb-113d-4255-9cdd-54b976247cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053684444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1053684444
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1464884871
Short name T466
Test name
Test status
Simulation time 173092213878 ps
CPU time 26.3 seconds
Started Jul 06 06:01:55 PM PDT 24
Finished Jul 06 06:02:22 PM PDT 24
Peak memory 200000 kb
Host smart-7e32a748-d088-43ac-922f-275800dfe13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464884871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1464884871
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3965744378
Short name T556
Test name
Test status
Simulation time 46547891686 ps
CPU time 29.97 seconds
Started Jul 06 06:01:55 PM PDT 24
Finished Jul 06 06:02:25 PM PDT 24
Peak memory 199992 kb
Host smart-27fcbc93-6788-4473-b801-bef550cb2ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965744378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3965744378
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3127332636
Short name T1137
Test name
Test status
Simulation time 32837323519 ps
CPU time 13.59 seconds
Started Jul 06 06:01:55 PM PDT 24
Finished Jul 06 06:02:09 PM PDT 24
Peak memory 199772 kb
Host smart-c39487bb-0f6b-4601-a441-0b37a756c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127332636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3127332636
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3775553053
Short name T464
Test name
Test status
Simulation time 58687201 ps
CPU time 0.56 seconds
Started Jul 06 05:58:03 PM PDT 24
Finished Jul 06 05:58:04 PM PDT 24
Peak memory 195332 kb
Host smart-58d916c4-658a-4204-be40-badda808a5fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775553053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3775553053
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.898660541
Short name T825
Test name
Test status
Simulation time 80559927946 ps
CPU time 30.27 seconds
Started Jul 06 05:57:59 PM PDT 24
Finished Jul 06 05:58:30 PM PDT 24
Peak memory 199956 kb
Host smart-5e02c0b3-e915-4b8c-9806-bce7e526ac83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898660541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.898660541
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.959420487
Short name T421
Test name
Test status
Simulation time 149885545358 ps
CPU time 25.01 seconds
Started Jul 06 05:58:02 PM PDT 24
Finished Jul 06 05:58:28 PM PDT 24
Peak memory 199696 kb
Host smart-4eb4895e-d7d6-4af1-a079-288fcca00893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959420487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.959420487
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1106522532
Short name T247
Test name
Test status
Simulation time 90257608399 ps
CPU time 22.29 seconds
Started Jul 06 05:58:00 PM PDT 24
Finished Jul 06 05:58:22 PM PDT 24
Peak memory 199968 kb
Host smart-f7ece9b8-0091-447e-8f96-383918d4b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106522532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1106522532
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.425393219
Short name T600
Test name
Test status
Simulation time 52922315705 ps
CPU time 23.92 seconds
Started Jul 06 05:58:03 PM PDT 24
Finished Jul 06 05:58:28 PM PDT 24
Peak memory 199836 kb
Host smart-1868fb43-3fea-4918-9034-54a8c5127acb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425393219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.425393219
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1678980651
Short name T580
Test name
Test status
Simulation time 125278498601 ps
CPU time 366.65 seconds
Started Jul 06 05:58:03 PM PDT 24
Finished Jul 06 06:04:10 PM PDT 24
Peak memory 199932 kb
Host smart-7f9c2d76-6147-4c1c-9dc1-a701c1731488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678980651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1678980651
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1127845913
Short name T364
Test name
Test status
Simulation time 3030917592 ps
CPU time 5.83 seconds
Started Jul 06 05:58:08 PM PDT 24
Finished Jul 06 05:58:15 PM PDT 24
Peak memory 197716 kb
Host smart-64fa87c0-641d-4aac-9476-e757a5d7502f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127845913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1127845913
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.869341877
Short name T839
Test name
Test status
Simulation time 123672347891 ps
CPU time 91.99 seconds
Started Jul 06 05:58:03 PM PDT 24
Finished Jul 06 05:59:35 PM PDT 24
Peak memory 200400 kb
Host smart-a9271bfe-8856-4624-a2a1-2076b48c27ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869341877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.869341877
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3396619749
Short name T647
Test name
Test status
Simulation time 13551889625 ps
CPU time 165.08 seconds
Started Jul 06 05:58:04 PM PDT 24
Finished Jul 06 06:00:50 PM PDT 24
Peak memory 200000 kb
Host smart-7581f7cb-31f0-4237-980d-c9c3da80fd89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3396619749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3396619749
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1308078367
Short name T356
Test name
Test status
Simulation time 7371235962 ps
CPU time 67.8 seconds
Started Jul 06 05:58:08 PM PDT 24
Finished Jul 06 05:59:17 PM PDT 24
Peak memory 199224 kb
Host smart-44c58754-f69c-4c13-b76d-90d955150de6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308078367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1308078367
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.8621685
Short name T607
Test name
Test status
Simulation time 57350580540 ps
CPU time 44.24 seconds
Started Jul 06 05:58:08 PM PDT 24
Finished Jul 06 05:58:53 PM PDT 24
Peak memory 199836 kb
Host smart-2720e920-ef22-431e-a2d6-587c050f82b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8621685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.8621685
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2020332857
Short name T294
Test name
Test status
Simulation time 2900730316 ps
CPU time 1.87 seconds
Started Jul 06 05:58:06 PM PDT 24
Finished Jul 06 05:58:08 PM PDT 24
Peak memory 195740 kb
Host smart-9f191c7e-6b35-4558-8bd3-17e9ac1f73be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020332857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2020332857
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.868124839
Short name T273
Test name
Test status
Simulation time 335054831 ps
CPU time 0.93 seconds
Started Jul 06 05:58:06 PM PDT 24
Finished Jul 06 05:58:07 PM PDT 24
Peak memory 197872 kb
Host smart-e0b95f7e-16e3-4534-a991-5d4d764cfa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868124839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.868124839
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2279603551
Short name T636
Test name
Test status
Simulation time 246657667874 ps
CPU time 261.47 seconds
Started Jul 06 05:58:06 PM PDT 24
Finished Jul 06 06:02:28 PM PDT 24
Peak memory 208364 kb
Host smart-f415cc99-d8b9-4f8e-b7db-4c5dcca803fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279603551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2279603551
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.937766523
Short name T1102
Test name
Test status
Simulation time 22308267287 ps
CPU time 380.54 seconds
Started Jul 06 05:58:08 PM PDT 24
Finished Jul 06 06:04:29 PM PDT 24
Peak memory 216344 kb
Host smart-83ed2e93-253f-484d-8c90-c5817b33daed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937766523 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.937766523
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3542123983
Short name T741
Test name
Test status
Simulation time 1008690697 ps
CPU time 1.81 seconds
Started Jul 06 05:58:04 PM PDT 24
Finished Jul 06 05:58:06 PM PDT 24
Peak memory 197264 kb
Host smart-87fe3a65-c079-4ee9-8eba-875043979cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542123983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3542123983
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1317984619
Short name T335
Test name
Test status
Simulation time 24174709854 ps
CPU time 15.82 seconds
Started Jul 06 05:58:00 PM PDT 24
Finished Jul 06 05:58:16 PM PDT 24
Peak memory 199920 kb
Host smart-3e384900-fa3d-4ea5-8eff-97c372edddee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317984619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1317984619
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2264289468
Short name T511
Test name
Test status
Simulation time 23618808689 ps
CPU time 10.99 seconds
Started Jul 06 06:01:56 PM PDT 24
Finished Jul 06 06:02:07 PM PDT 24
Peak memory 199984 kb
Host smart-9e6e1b8d-fa5d-4215-86d0-d78b47b44402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264289468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2264289468
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3285713557
Short name T680
Test name
Test status
Simulation time 20025347763 ps
CPU time 30.32 seconds
Started Jul 06 06:01:56 PM PDT 24
Finished Jul 06 06:02:27 PM PDT 24
Peak memory 200032 kb
Host smart-50fa12e6-6c39-4ee9-9b7d-7e3527791ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285713557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3285713557
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2556474584
Short name T833
Test name
Test status
Simulation time 106647091802 ps
CPU time 273.59 seconds
Started Jul 06 06:01:55 PM PDT 24
Finished Jul 06 06:06:28 PM PDT 24
Peak memory 199908 kb
Host smart-6d8695a3-4f81-4463-9940-4c604d271feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556474584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2556474584
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.543014196
Short name T194
Test name
Test status
Simulation time 18635306904 ps
CPU time 15.32 seconds
Started Jul 06 06:01:55 PM PDT 24
Finished Jul 06 06:02:11 PM PDT 24
Peak memory 199620 kb
Host smart-18692855-6810-465e-bcfc-6656d2221fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543014196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.543014196
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1404904956
Short name T574
Test name
Test status
Simulation time 57923310253 ps
CPU time 83.59 seconds
Started Jul 06 06:01:55 PM PDT 24
Finished Jul 06 06:03:18 PM PDT 24
Peak memory 200032 kb
Host smart-eaa4577a-71ab-42c1-a8b6-75d59f8031ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404904956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1404904956
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3997131049
Short name T113
Test name
Test status
Simulation time 97410304095 ps
CPU time 165.49 seconds
Started Jul 06 06:02:00 PM PDT 24
Finished Jul 06 06:04:45 PM PDT 24
Peak memory 199948 kb
Host smart-fc19d55a-ea13-4b18-9a48-ba2b79511a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997131049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3997131049
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3317848496
Short name T685
Test name
Test status
Simulation time 12871920659 ps
CPU time 6.08 seconds
Started Jul 06 06:02:01 PM PDT 24
Finished Jul 06 06:02:07 PM PDT 24
Peak memory 200012 kb
Host smart-686b14b5-525e-4c01-b138-eaee4ed0004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317848496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3317848496
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1952308310
Short name T215
Test name
Test status
Simulation time 57477653974 ps
CPU time 89.36 seconds
Started Jul 06 06:02:02 PM PDT 24
Finished Jul 06 06:03:31 PM PDT 24
Peak memory 199972 kb
Host smart-b2395679-f319-4d74-821a-68308cdac046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952308310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1952308310
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1252042984
Short name T863
Test name
Test status
Simulation time 63078164659 ps
CPU time 26.98 seconds
Started Jul 06 06:02:01 PM PDT 24
Finished Jul 06 06:02:28 PM PDT 24
Peak memory 199844 kb
Host smart-eeca6157-f776-4e45-b0cb-eca4e0c850ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252042984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1252042984
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3678861197
Short name T437
Test name
Test status
Simulation time 42900384 ps
CPU time 0.58 seconds
Started Jul 06 05:56:51 PM PDT 24
Finished Jul 06 05:56:52 PM PDT 24
Peak memory 195296 kb
Host smart-c0742cd0-e9a5-4666-aa62-4c5920e18f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678861197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3678861197
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1573025371
Short name T739
Test name
Test status
Simulation time 109157738821 ps
CPU time 50.3 seconds
Started Jul 06 05:56:46 PM PDT 24
Finished Jul 06 05:57:36 PM PDT 24
Peak memory 199928 kb
Host smart-12a7fe6f-0233-4250-97e0-5bec2f11aed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573025371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1573025371
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.700061653
Short name T859
Test name
Test status
Simulation time 171734335680 ps
CPU time 185.13 seconds
Started Jul 06 05:56:46 PM PDT 24
Finished Jul 06 05:59:52 PM PDT 24
Peak memory 199996 kb
Host smart-a03fcb12-87e1-4aa4-a581-2b0d3d26c6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700061653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.700061653
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2775707501
Short name T602
Test name
Test status
Simulation time 4353772476 ps
CPU time 7.25 seconds
Started Jul 06 05:56:53 PM PDT 24
Finished Jul 06 05:57:01 PM PDT 24
Peak memory 196768 kb
Host smart-fb6dd5a2-fa91-4c86-8c73-144a349a29d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775707501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2775707501
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.903131900
Short name T631
Test name
Test status
Simulation time 78819099092 ps
CPU time 129.57 seconds
Started Jul 06 05:56:50 PM PDT 24
Finished Jul 06 05:59:00 PM PDT 24
Peak memory 199864 kb
Host smart-c8e050ce-8de9-42e3-bd26-3399e13a6a5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903131900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.903131900
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3707844306
Short name T648
Test name
Test status
Simulation time 13748317734 ps
CPU time 45.27 seconds
Started Jul 06 05:56:54 PM PDT 24
Finished Jul 06 05:57:39 PM PDT 24
Peak memory 199876 kb
Host smart-8e575d9f-e76b-4f40-81b3-278d7b4e1a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707844306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3707844306
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3878921877
Short name T815
Test name
Test status
Simulation time 5582404023 ps
CPU time 8.13 seconds
Started Jul 06 05:56:51 PM PDT 24
Finished Jul 06 05:56:59 PM PDT 24
Peak memory 197728 kb
Host smart-738765dc-8ee6-4e19-8919-eba31499c4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878921877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3878921877
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.4004772939
Short name T624
Test name
Test status
Simulation time 16719616300 ps
CPU time 408.13 seconds
Started Jul 06 05:56:51 PM PDT 24
Finished Jul 06 06:03:39 PM PDT 24
Peak memory 199936 kb
Host smart-a74343b5-4ecd-4c76-8935-fd90c13e3c3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004772939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.4004772939
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3616031942
Short name T362
Test name
Test status
Simulation time 7280118103 ps
CPU time 62.17 seconds
Started Jul 06 05:56:52 PM PDT 24
Finished Jul 06 05:57:54 PM PDT 24
Peak memory 200012 kb
Host smart-0374ac3c-fca5-4f42-8d3d-ee6c37cff46d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3616031942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3616031942
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3484599704
Short name T995
Test name
Test status
Simulation time 253545623575 ps
CPU time 1090.55 seconds
Started Jul 06 05:56:51 PM PDT 24
Finished Jul 06 06:15:02 PM PDT 24
Peak memory 199900 kb
Host smart-1ba68f53-03e4-4e9e-b7bf-d40e3db5c2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484599704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3484599704
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3725297163
Short name T712
Test name
Test status
Simulation time 2719053739 ps
CPU time 4.65 seconds
Started Jul 06 05:56:51 PM PDT 24
Finished Jul 06 05:56:56 PM PDT 24
Peak memory 195752 kb
Host smart-8575170c-df7b-4b30-8626-953db456d24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725297163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3725297163
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3332438466
Short name T21
Test name
Test status
Simulation time 219418394 ps
CPU time 0.87 seconds
Started Jul 06 05:56:52 PM PDT 24
Finished Jul 06 05:56:53 PM PDT 24
Peak memory 218356 kb
Host smart-5e81e787-8b4b-4361-ba0d-5223743e7fcf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332438466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3332438466
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3497741466
Short name T483
Test name
Test status
Simulation time 882704726 ps
CPU time 4.21 seconds
Started Jul 06 05:56:47 PM PDT 24
Finished Jul 06 05:56:51 PM PDT 24
Peak memory 199340 kb
Host smart-f5eca84d-0a07-46a1-a1e6-be6fc9b2a9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497741466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3497741466
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2568009314
Short name T843
Test name
Test status
Simulation time 6729835095 ps
CPU time 41.3 seconds
Started Jul 06 05:56:51 PM PDT 24
Finished Jul 06 05:57:33 PM PDT 24
Peak memory 199784 kb
Host smart-49dc238c-e31d-45da-ba88-abdee7900651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568009314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2568009314
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3493160558
Short name T284
Test name
Test status
Simulation time 13840172785 ps
CPU time 19.23 seconds
Started Jul 06 05:56:48 PM PDT 24
Finished Jul 06 05:57:07 PM PDT 24
Peak memory 199660 kb
Host smart-b3128caf-bb2a-424b-8248-527278c69046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493160558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3493160558
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.506476004
Short name T1099
Test name
Test status
Simulation time 13347221 ps
CPU time 0.57 seconds
Started Jul 06 05:58:15 PM PDT 24
Finished Jul 06 05:58:16 PM PDT 24
Peak memory 194716 kb
Host smart-4fecf3a0-5766-461f-ae2a-61017f5110b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506476004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.506476004
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1488499026
Short name T111
Test name
Test status
Simulation time 27478251765 ps
CPU time 16.88 seconds
Started Jul 06 05:58:08 PM PDT 24
Finished Jul 06 05:58:26 PM PDT 24
Peak memory 199916 kb
Host smart-743906e6-60fa-4f32-85a8-af1c27d18195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488499026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1488499026
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1108316654
Short name T651
Test name
Test status
Simulation time 27374942499 ps
CPU time 44.71 seconds
Started Jul 06 05:58:07 PM PDT 24
Finished Jul 06 05:58:52 PM PDT 24
Peak memory 199880 kb
Host smart-3b50b891-65ca-498d-904d-9d32973a31c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108316654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1108316654
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3790763625
Short name T518
Test name
Test status
Simulation time 172530103072 ps
CPU time 51.77 seconds
Started Jul 06 05:58:08 PM PDT 24
Finished Jul 06 05:59:01 PM PDT 24
Peak memory 199828 kb
Host smart-1f935f45-fa9a-4b4d-8c2e-b0cef7ddf5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790763625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3790763625
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1721318563
Short name T670
Test name
Test status
Simulation time 163377996279 ps
CPU time 339.66 seconds
Started Jul 06 05:58:11 PM PDT 24
Finished Jul 06 06:03:51 PM PDT 24
Peak memory 199948 kb
Host smart-3e733561-9ef1-44df-9a65-a004c33082fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1721318563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1721318563
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.4131079079
Short name T690
Test name
Test status
Simulation time 9079016948 ps
CPU time 3.93 seconds
Started Jul 06 05:58:08 PM PDT 24
Finished Jul 06 05:58:13 PM PDT 24
Peak memory 199880 kb
Host smart-80ccf67e-2f6d-48d5-be0f-f1b718452ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131079079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.4131079079
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1973677017
Short name T990
Test name
Test status
Simulation time 108543341785 ps
CPU time 35.21 seconds
Started Jul 06 05:58:11 PM PDT 24
Finished Jul 06 05:58:46 PM PDT 24
Peak memory 208328 kb
Host smart-fb12e3b2-fff7-47c8-a216-1626b85ad22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973677017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1973677017
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2878199617
Short name T667
Test name
Test status
Simulation time 24177347640 ps
CPU time 183.41 seconds
Started Jul 06 05:58:10 PM PDT 24
Finished Jul 06 06:01:14 PM PDT 24
Peak memory 199928 kb
Host smart-0c48cbd7-335d-448c-9a8f-b88013dfb302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878199617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2878199617
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.80299082
Short name T653
Test name
Test status
Simulation time 7120089003 ps
CPU time 14.96 seconds
Started Jul 06 05:58:08 PM PDT 24
Finished Jul 06 05:58:24 PM PDT 24
Peak memory 199248 kb
Host smart-e6430b51-46fb-43d7-9b58-f4ca0822c489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80299082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.80299082
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3896709581
Short name T763
Test name
Test status
Simulation time 62727388014 ps
CPU time 99.78 seconds
Started Jul 06 05:58:09 PM PDT 24
Finished Jul 06 05:59:49 PM PDT 24
Peak memory 199960 kb
Host smart-7ce9eadc-98a7-4c2a-80a6-34ffbbe50338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896709581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3896709581
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3012347762
Short name T1166
Test name
Test status
Simulation time 3942190792 ps
CPU time 6.31 seconds
Started Jul 06 05:58:11 PM PDT 24
Finished Jul 06 05:58:17 PM PDT 24
Peak memory 196048 kb
Host smart-34dc7b25-b5d8-4e61-bd07-35b676fa04fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012347762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3012347762
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2503608182
Short name T1067
Test name
Test status
Simulation time 466565964 ps
CPU time 2.45 seconds
Started Jul 06 05:58:10 PM PDT 24
Finished Jul 06 05:58:13 PM PDT 24
Peak memory 199828 kb
Host smart-c3c50e0d-d77c-4eb6-a6a9-750980dd8057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503608182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2503608182
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3347482483
Short name T798
Test name
Test status
Simulation time 45159989295 ps
CPU time 552.96 seconds
Started Jul 06 05:58:09 PM PDT 24
Finished Jul 06 06:07:22 PM PDT 24
Peak memory 216432 kb
Host smart-3e0835b4-f52c-445b-8d65-c11c92a5340f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347482483 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3347482483
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3008726750
Short name T37
Test name
Test status
Simulation time 2404914655 ps
CPU time 1.8 seconds
Started Jul 06 05:58:08 PM PDT 24
Finished Jul 06 05:58:10 PM PDT 24
Peak memory 198808 kb
Host smart-4b205cc6-10dc-4486-83c0-2e7481b3d777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008726750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3008726750
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.496521383
Short name T568
Test name
Test status
Simulation time 26425182264 ps
CPU time 44.8 seconds
Started Jul 06 05:58:09 PM PDT 24
Finished Jul 06 05:58:54 PM PDT 24
Peak memory 199900 kb
Host smart-5fe1cdc9-c0d2-431c-a622-93d9dc7ab9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496521383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.496521383
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.4094375355
Short name T646
Test name
Test status
Simulation time 88883789436 ps
CPU time 160.84 seconds
Started Jul 06 06:02:00 PM PDT 24
Finished Jul 06 06:04:41 PM PDT 24
Peak memory 199936 kb
Host smart-e6436257-df7a-499d-a053-7c93cc41a964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094375355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.4094375355
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3869099768
Short name T171
Test name
Test status
Simulation time 45606908275 ps
CPU time 24.05 seconds
Started Jul 06 06:02:05 PM PDT 24
Finished Jul 06 06:02:30 PM PDT 24
Peak memory 199964 kb
Host smart-60c33dc4-1198-40c7-8a52-107666a67ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869099768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3869099768
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2718861545
Short name T229
Test name
Test status
Simulation time 12524270643 ps
CPU time 20.54 seconds
Started Jul 06 06:02:07 PM PDT 24
Finished Jul 06 06:02:28 PM PDT 24
Peak memory 199900 kb
Host smart-7dd68b88-be3b-48e2-ada3-bcc572b082f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718861545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2718861545
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.114851647
Short name T976
Test name
Test status
Simulation time 300392175207 ps
CPU time 131.37 seconds
Started Jul 06 06:02:05 PM PDT 24
Finished Jul 06 06:04:17 PM PDT 24
Peak memory 199952 kb
Host smart-315824d9-7065-4414-857f-9417cfb6c612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114851647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.114851647
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3599328304
Short name T800
Test name
Test status
Simulation time 38795595196 ps
CPU time 15.72 seconds
Started Jul 06 06:02:07 PM PDT 24
Finished Jul 06 06:02:23 PM PDT 24
Peak memory 200008 kb
Host smart-4b0e4e04-4532-4de0-b3d8-53be1f7fed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599328304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3599328304
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2900051761
Short name T856
Test name
Test status
Simulation time 27468506703 ps
CPU time 45.21 seconds
Started Jul 06 06:02:05 PM PDT 24
Finished Jul 06 06:02:51 PM PDT 24
Peak memory 200012 kb
Host smart-f101d844-231d-42ca-900a-690917ec9a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900051761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2900051761
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3714041294
Short name T196
Test name
Test status
Simulation time 73245279538 ps
CPU time 94.83 seconds
Started Jul 06 06:02:05 PM PDT 24
Finished Jul 06 06:03:40 PM PDT 24
Peak memory 199924 kb
Host smart-4ad3d295-733e-444e-91d3-5a822aea76c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714041294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3714041294
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2323997713
Short name T698
Test name
Test status
Simulation time 33106261254 ps
CPU time 17.22 seconds
Started Jul 06 06:02:07 PM PDT 24
Finished Jul 06 06:02:24 PM PDT 24
Peak memory 199916 kb
Host smart-bde235ea-b7fc-40d5-becd-339a12bb4f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323997713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2323997713
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2275458492
Short name T1004
Test name
Test status
Simulation time 11092504929 ps
CPU time 13.2 seconds
Started Jul 06 06:02:05 PM PDT 24
Finished Jul 06 06:02:19 PM PDT 24
Peak memory 199656 kb
Host smart-96acc86f-ecec-49d4-8fe5-0c6f7f8d1e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275458492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2275458492
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3837566049
Short name T659
Test name
Test status
Simulation time 28754670 ps
CPU time 0.58 seconds
Started Jul 06 05:58:19 PM PDT 24
Finished Jul 06 05:58:20 PM PDT 24
Peak memory 195336 kb
Host smart-d4f624e2-d680-4034-8b1e-65f896f45367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837566049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3837566049
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.4132373433
Short name T493
Test name
Test status
Simulation time 33363493347 ps
CPU time 23.04 seconds
Started Jul 06 05:58:13 PM PDT 24
Finished Jul 06 05:58:37 PM PDT 24
Peak memory 198696 kb
Host smart-4a8f6d15-c9b9-4ca5-bf2e-64c12e835771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132373433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.4132373433
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2377449598
Short name T500
Test name
Test status
Simulation time 57312761361 ps
CPU time 72.18 seconds
Started Jul 06 05:58:15 PM PDT 24
Finished Jul 06 05:59:27 PM PDT 24
Peak memory 199928 kb
Host smart-53463062-e5e9-4db3-9df1-b1de21d949fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377449598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2377449598
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3238201370
Short name T84
Test name
Test status
Simulation time 106920760687 ps
CPU time 89.41 seconds
Started Jul 06 05:58:18 PM PDT 24
Finished Jul 06 05:59:47 PM PDT 24
Peak memory 199900 kb
Host smart-e58ea2fc-3df1-4032-9601-d235ca7628f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238201370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3238201370
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.460567903
Short name T821
Test name
Test status
Simulation time 46660866647 ps
CPU time 24.78 seconds
Started Jul 06 05:58:14 PM PDT 24
Finished Jul 06 05:58:39 PM PDT 24
Peak memory 199980 kb
Host smart-4d578e08-d1f3-42a6-8cf9-fb5b2bbf1136
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460567903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.460567903
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.914356167
Short name T1009
Test name
Test status
Simulation time 125687607022 ps
CPU time 1027.59 seconds
Started Jul 06 05:58:21 PM PDT 24
Finished Jul 06 06:15:29 PM PDT 24
Peak memory 199944 kb
Host smart-0191b9b8-0b88-44b0-a08f-2b0377d63aaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914356167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.914356167
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2276269702
Short name T1019
Test name
Test status
Simulation time 10564139571 ps
CPU time 12.38 seconds
Started Jul 06 05:58:23 PM PDT 24
Finished Jul 06 05:58:36 PM PDT 24
Peak memory 199888 kb
Host smart-f896f9ad-1aba-4dd1-bc59-65e96ea9c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276269702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2276269702
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3436435823
Short name T1
Test name
Test status
Simulation time 143522858208 ps
CPU time 106.03 seconds
Started Jul 06 05:58:18 PM PDT 24
Finished Jul 06 06:00:04 PM PDT 24
Peak memory 199492 kb
Host smart-6bbd8808-febe-4843-9cfc-97e189bcb6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436435823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3436435823
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3659521309
Short name T540
Test name
Test status
Simulation time 8506664603 ps
CPU time 194.4 seconds
Started Jul 06 05:58:20 PM PDT 24
Finished Jul 06 06:01:34 PM PDT 24
Peak memory 200024 kb
Host smart-d94abca9-6270-4538-9f2d-b63356569ea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659521309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3659521309
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3704815904
Short name T957
Test name
Test status
Simulation time 6945615457 ps
CPU time 18.37 seconds
Started Jul 06 05:58:13 PM PDT 24
Finished Jul 06 05:58:32 PM PDT 24
Peak memory 199960 kb
Host smart-5e943cf0-3508-4c6d-845b-e3549aad3221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3704815904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3704815904
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2039656446
Short name T262
Test name
Test status
Simulation time 114098864354 ps
CPU time 313.46 seconds
Started Jul 06 05:58:20 PM PDT 24
Finished Jul 06 06:03:34 PM PDT 24
Peak memory 199936 kb
Host smart-3a55b5cd-3dc0-48eb-b3c4-48826a0d8659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039656446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2039656446
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3393450863
Short name T439
Test name
Test status
Simulation time 1515073072 ps
CPU time 2.87 seconds
Started Jul 06 05:58:23 PM PDT 24
Finished Jul 06 05:58:26 PM PDT 24
Peak memory 195592 kb
Host smart-553afa4f-abd9-4618-8f38-af58ad1b742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393450863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3393450863
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1687468273
Short name T487
Test name
Test status
Simulation time 464837559 ps
CPU time 1.65 seconds
Started Jul 06 05:58:14 PM PDT 24
Finished Jul 06 05:58:16 PM PDT 24
Peak memory 198584 kb
Host smart-1d5b1145-10ea-41f3-9afc-91d655702e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687468273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1687468273
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2813726179
Short name T242
Test name
Test status
Simulation time 124430046058 ps
CPU time 1093.54 seconds
Started Jul 06 05:58:17 PM PDT 24
Finished Jul 06 06:16:31 PM PDT 24
Peak memory 199912 kb
Host smart-78af6672-52e7-46d0-814b-aebd13a78a12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813726179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2813726179
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2882093854
Short name T1045
Test name
Test status
Simulation time 115903505920 ps
CPU time 211.61 seconds
Started Jul 06 05:58:19 PM PDT 24
Finished Jul 06 06:01:51 PM PDT 24
Peak memory 208568 kb
Host smart-993419a2-beb9-4ab1-80b9-91a849394b00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882093854 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2882093854
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3492480676
Short name T736
Test name
Test status
Simulation time 1306281709 ps
CPU time 1.3 seconds
Started Jul 06 05:58:19 PM PDT 24
Finished Jul 06 05:58:20 PM PDT 24
Peak memory 196984 kb
Host smart-5c96e03e-89e4-4bd3-88e7-c687b8f0ba48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492480676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3492480676
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1195982492
Short name T314
Test name
Test status
Simulation time 11737087883 ps
CPU time 19.46 seconds
Started Jul 06 05:58:15 PM PDT 24
Finished Jul 06 05:58:34 PM PDT 24
Peak memory 199980 kb
Host smart-e6d69d3d-f3ea-4c48-8d4c-9d811157b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195982492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1195982492
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2965666244
Short name T1076
Test name
Test status
Simulation time 24035590965 ps
CPU time 36.89 seconds
Started Jul 06 06:02:05 PM PDT 24
Finished Jul 06 06:02:42 PM PDT 24
Peak memory 200004 kb
Host smart-7b203c3d-91e3-4a1d-9262-9d5dc15866ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965666244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2965666244
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1178927459
Short name T61
Test name
Test status
Simulation time 30118758178 ps
CPU time 13.77 seconds
Started Jul 06 06:02:05 PM PDT 24
Finished Jul 06 06:02:19 PM PDT 24
Peak memory 199928 kb
Host smart-ff6bb69f-f176-4fd0-a789-f66bdb512742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178927459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1178927459
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1365449582
Short name T672
Test name
Test status
Simulation time 29688445902 ps
CPU time 12.92 seconds
Started Jul 06 06:02:08 PM PDT 24
Finished Jul 06 06:02:21 PM PDT 24
Peak memory 199988 kb
Host smart-f7a7541d-0df4-4dc4-8fcc-79b73f173ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365449582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1365449582
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.935608772
Short name T211
Test name
Test status
Simulation time 81961980901 ps
CPU time 64.35 seconds
Started Jul 06 06:02:05 PM PDT 24
Finished Jul 06 06:03:10 PM PDT 24
Peak memory 199852 kb
Host smart-89dc96f9-55fd-462e-89f9-cbf41af3f65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935608772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.935608772
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1397035986
Short name T202
Test name
Test status
Simulation time 18937215763 ps
CPU time 33.34 seconds
Started Jul 06 06:02:06 PM PDT 24
Finished Jul 06 06:02:40 PM PDT 24
Peak memory 199916 kb
Host smart-e76eecbe-14ca-468b-99c0-033ac341d9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397035986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1397035986
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.574200532
Short name T207
Test name
Test status
Simulation time 45221648863 ps
CPU time 138.8 seconds
Started Jul 06 06:02:11 PM PDT 24
Finished Jul 06 06:04:30 PM PDT 24
Peak memory 199872 kb
Host smart-3deac922-1bdb-44f7-b303-6bd6bec959a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574200532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.574200532
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.4067618861
Short name T165
Test name
Test status
Simulation time 32028806558 ps
CPU time 22.65 seconds
Started Jul 06 06:02:10 PM PDT 24
Finished Jul 06 06:02:32 PM PDT 24
Peak memory 199920 kb
Host smart-529cb18e-932d-4552-9714-85c24594f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067618861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4067618861
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.736732514
Short name T875
Test name
Test status
Simulation time 37887389 ps
CPU time 0.55 seconds
Started Jul 06 05:58:23 PM PDT 24
Finished Jul 06 05:58:24 PM PDT 24
Peak memory 195608 kb
Host smart-5a6eb4eb-8b54-4c8b-b256-632e67397181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736732514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.736732514
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2526621465
Short name T162
Test name
Test status
Simulation time 171312144136 ps
CPU time 60.05 seconds
Started Jul 06 05:58:19 PM PDT 24
Finished Jul 06 05:59:19 PM PDT 24
Peak memory 199956 kb
Host smart-ee61b874-08b2-4a7a-8971-38e23d1a190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526621465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2526621465
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2216957525
Short name T708
Test name
Test status
Simulation time 81447200460 ps
CPU time 33.07 seconds
Started Jul 06 05:58:23 PM PDT 24
Finished Jul 06 05:58:56 PM PDT 24
Peak memory 199956 kb
Host smart-cac89e0d-db43-4341-a20b-3b0279105b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216957525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2216957525
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1721582039
Short name T1012
Test name
Test status
Simulation time 122353665827 ps
CPU time 22.52 seconds
Started Jul 06 05:58:21 PM PDT 24
Finished Jul 06 05:58:44 PM PDT 24
Peak memory 199828 kb
Host smart-f2c4c189-a213-4c15-8a2c-f0143d0534bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721582039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1721582039
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3952731132
Short name T527
Test name
Test status
Simulation time 33966776662 ps
CPU time 26.96 seconds
Started Jul 06 05:58:18 PM PDT 24
Finished Jul 06 05:58:45 PM PDT 24
Peak memory 199936 kb
Host smart-047b9f62-defc-42b9-8b27-83f9f0ad3929
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952731132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3952731132
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3032468893
Short name T265
Test name
Test status
Simulation time 104329514324 ps
CPU time 325.6 seconds
Started Jul 06 05:58:25 PM PDT 24
Finished Jul 06 06:03:50 PM PDT 24
Peak memory 199956 kb
Host smart-399af58d-bdd0-449e-a6ce-90874200bc83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032468893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3032468893
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1295553002
Short name T796
Test name
Test status
Simulation time 831845383 ps
CPU time 2.27 seconds
Started Jul 06 05:58:24 PM PDT 24
Finished Jul 06 05:58:27 PM PDT 24
Peak memory 198328 kb
Host smart-e8cb1886-82c0-4c4b-bcb9-18cd26a178df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295553002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1295553002
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.216775798
Short name T550
Test name
Test status
Simulation time 58803048345 ps
CPU time 95.58 seconds
Started Jul 06 05:58:20 PM PDT 24
Finished Jul 06 05:59:56 PM PDT 24
Peak memory 200064 kb
Host smart-92f0f1c5-0b13-4d58-9001-7d4a94f849c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216775798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.216775798
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.86760220
Short name T413
Test name
Test status
Simulation time 15014783346 ps
CPU time 129.28 seconds
Started Jul 06 05:58:27 PM PDT 24
Finished Jul 06 06:00:36 PM PDT 24
Peak memory 199996 kb
Host smart-8be0f727-4f2f-47ff-b843-04018698b61e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86760220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.86760220
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3417764205
Short name T890
Test name
Test status
Simulation time 6367316482 ps
CPU time 12.73 seconds
Started Jul 06 05:58:19 PM PDT 24
Finished Jul 06 05:58:32 PM PDT 24
Peak memory 198240 kb
Host smart-0bed9316-487f-41b9-b2b6-b4711ca87f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417764205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3417764205
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3128957688
Short name T1127
Test name
Test status
Simulation time 66696292595 ps
CPU time 165.91 seconds
Started Jul 06 05:58:25 PM PDT 24
Finished Jul 06 06:01:11 PM PDT 24
Peak memory 199720 kb
Host smart-0a5107ea-cda5-46e1-8013-120bc8a2c0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128957688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3128957688
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4113878698
Short name T383
Test name
Test status
Simulation time 4170637101 ps
CPU time 2.1 seconds
Started Jul 06 05:58:20 PM PDT 24
Finished Jul 06 05:58:23 PM PDT 24
Peak memory 196072 kb
Host smart-1d1a064c-9711-4b6a-9515-0eed63c7d030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113878698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4113878698
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2950507336
Short name T435
Test name
Test status
Simulation time 648820523 ps
CPU time 2.57 seconds
Started Jul 06 05:58:21 PM PDT 24
Finished Jul 06 05:58:23 PM PDT 24
Peak memory 198656 kb
Host smart-54cf3a15-01a7-4144-ae65-368692a93af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950507336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2950507336
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3800080041
Short name T865
Test name
Test status
Simulation time 151633098258 ps
CPU time 312.3 seconds
Started Jul 06 05:58:24 PM PDT 24
Finished Jul 06 06:03:37 PM PDT 24
Peak memory 199984 kb
Host smart-c2d26adb-8e71-4a4d-acf8-6ec68fb32452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800080041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3800080041
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1551030000
Short name T1155
Test name
Test status
Simulation time 86633363326 ps
CPU time 327.82 seconds
Started Jul 06 05:58:23 PM PDT 24
Finished Jul 06 06:03:51 PM PDT 24
Peak memory 216528 kb
Host smart-333aef87-6562-42dc-b295-e11969c981ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551030000 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1551030000
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2144805688
Short name T299
Test name
Test status
Simulation time 6766476425 ps
CPU time 21.02 seconds
Started Jul 06 05:58:22 PM PDT 24
Finished Jul 06 05:58:43 PM PDT 24
Peak memory 199768 kb
Host smart-2dddc267-c602-43a2-90ec-3df5b7421600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144805688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2144805688
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3275941934
Short name T1037
Test name
Test status
Simulation time 70113634691 ps
CPU time 40.1 seconds
Started Jul 06 05:58:24 PM PDT 24
Finished Jul 06 05:59:05 PM PDT 24
Peak memory 199984 kb
Host smart-f4c3532d-1b5e-4fbb-8ed5-e53d790cbc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275941934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3275941934
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3148553985
Short name T304
Test name
Test status
Simulation time 87104988293 ps
CPU time 68.16 seconds
Started Jul 06 06:02:13 PM PDT 24
Finished Jul 06 06:03:21 PM PDT 24
Peak memory 200020 kb
Host smart-4b5239bd-58e6-45bb-997e-46de2f268292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148553985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3148553985
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.431392528
Short name T178
Test name
Test status
Simulation time 85307529963 ps
CPU time 72.63 seconds
Started Jul 06 06:02:10 PM PDT 24
Finished Jul 06 06:03:23 PM PDT 24
Peak memory 199908 kb
Host smart-ded8f747-629b-4560-9c89-2f329deb4bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431392528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.431392528
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3046852796
Short name T344
Test name
Test status
Simulation time 21180352888 ps
CPU time 8.3 seconds
Started Jul 06 06:02:10 PM PDT 24
Finished Jul 06 06:02:18 PM PDT 24
Peak memory 199924 kb
Host smart-06f26d35-94fe-404e-929d-ca2de0aece9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046852796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3046852796
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1902126495
Short name T1003
Test name
Test status
Simulation time 23307347514 ps
CPU time 19.63 seconds
Started Jul 06 06:02:10 PM PDT 24
Finished Jul 06 06:02:29 PM PDT 24
Peak memory 199828 kb
Host smart-20e45a84-392d-4d5e-a145-9c0b7ad38a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902126495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1902126495
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.830629074
Short name T732
Test name
Test status
Simulation time 150417090794 ps
CPU time 25.25 seconds
Started Jul 06 06:02:11 PM PDT 24
Finished Jul 06 06:02:36 PM PDT 24
Peak memory 199944 kb
Host smart-12ff9827-c08f-48b3-90d8-3db8a122505c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830629074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.830629074
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1514786874
Short name T140
Test name
Test status
Simulation time 17480625832 ps
CPU time 31.22 seconds
Started Jul 06 06:02:13 PM PDT 24
Finished Jul 06 06:02:44 PM PDT 24
Peak memory 199956 kb
Host smart-f9dd31fa-2a86-4464-a357-aa7aa9535e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514786874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1514786874
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3876766616
Short name T192
Test name
Test status
Simulation time 26651718647 ps
CPU time 21.63 seconds
Started Jul 06 06:02:09 PM PDT 24
Finished Jul 06 06:02:31 PM PDT 24
Peak memory 199984 kb
Host smart-747a1094-a386-4404-91f1-d97865380ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876766616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3876766616
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3959841559
Short name T969
Test name
Test status
Simulation time 92505113110 ps
CPU time 140.71 seconds
Started Jul 06 06:02:15 PM PDT 24
Finished Jul 06 06:04:36 PM PDT 24
Peak memory 199768 kb
Host smart-117e3178-d705-40e8-8e84-04c615a3db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959841559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3959841559
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3826344959
Short name T598
Test name
Test status
Simulation time 13344127 ps
CPU time 0.57 seconds
Started Jul 06 05:58:27 PM PDT 24
Finished Jul 06 05:58:28 PM PDT 24
Peak memory 195300 kb
Host smart-b44e9651-a610-4c20-ae09-e2947feeaa7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826344959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3826344959
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1757758647
Short name T836
Test name
Test status
Simulation time 96879932741 ps
CPU time 152.73 seconds
Started Jul 06 05:58:24 PM PDT 24
Finished Jul 06 06:00:57 PM PDT 24
Peak memory 199952 kb
Host smart-9b7bd225-e8f7-4b75-8309-3bf670067ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757758647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1757758647
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4149418024
Short name T185
Test name
Test status
Simulation time 76349929964 ps
CPU time 19.83 seconds
Started Jul 06 05:58:24 PM PDT 24
Finished Jul 06 05:58:44 PM PDT 24
Peak memory 199864 kb
Host smart-83186787-a203-48f6-abf6-9d78b9805db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149418024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4149418024
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.258459014
Short name T203
Test name
Test status
Simulation time 20643926956 ps
CPU time 34.77 seconds
Started Jul 06 05:58:24 PM PDT 24
Finished Jul 06 05:58:59 PM PDT 24
Peak memory 199976 kb
Host smart-c77f492e-7929-4847-97f0-6b587c27e4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258459014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.258459014
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.4137527421
Short name T781
Test name
Test status
Simulation time 2000698372 ps
CPU time 1.62 seconds
Started Jul 06 05:58:23 PM PDT 24
Finished Jul 06 05:58:25 PM PDT 24
Peak memory 195612 kb
Host smart-614bba2b-2356-4eca-b040-7ed4db9a90d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137527421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4137527421
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2969105338
Short name T1168
Test name
Test status
Simulation time 293088806752 ps
CPU time 127.2 seconds
Started Jul 06 05:58:28 PM PDT 24
Finished Jul 06 06:00:36 PM PDT 24
Peak memory 199972 kb
Host smart-ec8f298f-c251-456f-aad7-9b40fa546410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969105338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2969105338
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3212559897
Short name T363
Test name
Test status
Simulation time 892635086 ps
CPU time 1.86 seconds
Started Jul 06 05:58:26 PM PDT 24
Finished Jul 06 05:58:29 PM PDT 24
Peak memory 195952 kb
Host smart-70094a64-6cbf-4de4-9e64-a6bb6504265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212559897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3212559897
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1695395676
Short name T1158
Test name
Test status
Simulation time 46586287252 ps
CPU time 66.79 seconds
Started Jul 06 05:58:26 PM PDT 24
Finished Jul 06 05:59:33 PM PDT 24
Peak memory 199712 kb
Host smart-3e22d21f-6429-428d-b3bc-8297868e08b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695395676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1695395676
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1044743277
Short name T1041
Test name
Test status
Simulation time 16777121493 ps
CPU time 168.49 seconds
Started Jul 06 05:58:28 PM PDT 24
Finished Jul 06 06:01:17 PM PDT 24
Peak memory 199996 kb
Host smart-43e2d223-a182-4f3f-94bc-13b12ddd90a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044743277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1044743277
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3635053967
Short name T1001
Test name
Test status
Simulation time 2633544569 ps
CPU time 9.28 seconds
Started Jul 06 05:58:24 PM PDT 24
Finished Jul 06 05:58:34 PM PDT 24
Peak memory 199160 kb
Host smart-ed522534-3e0b-4b85-8cc0-a0dbcf6284f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3635053967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3635053967
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2337163412
Short name T414
Test name
Test status
Simulation time 12857799853 ps
CPU time 17.33 seconds
Started Jul 06 05:58:26 PM PDT 24
Finished Jul 06 05:58:44 PM PDT 24
Peak memory 199612 kb
Host smart-7b589a9c-24e7-4a37-abdc-f749f7ff67e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337163412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2337163412
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2309117860
Short name T687
Test name
Test status
Simulation time 35037501540 ps
CPU time 12.49 seconds
Started Jul 06 05:58:27 PM PDT 24
Finished Jul 06 05:58:40 PM PDT 24
Peak memory 196436 kb
Host smart-eb917f8f-2971-45bb-92ce-5799356b4fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309117860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2309117860
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.744204825
Short name T442
Test name
Test status
Simulation time 5384222862 ps
CPU time 13.8 seconds
Started Jul 06 05:58:21 PM PDT 24
Finished Jul 06 05:58:35 PM PDT 24
Peak memory 199812 kb
Host smart-63fad8ee-5152-4465-b84c-6ad1a70783c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744204825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.744204825
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.65506942
Short name T709
Test name
Test status
Simulation time 109435361299 ps
CPU time 173.85 seconds
Started Jul 06 05:58:27 PM PDT 24
Finished Jul 06 06:01:21 PM PDT 24
Peak memory 199000 kb
Host smart-022aff98-7c0d-447d-a51b-fd64609a8247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65506942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.65506942
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1792661277
Short name T795
Test name
Test status
Simulation time 30069430319 ps
CPU time 105.81 seconds
Started Jul 06 05:58:35 PM PDT 24
Finished Jul 06 06:00:21 PM PDT 24
Peak memory 216440 kb
Host smart-076bd06b-a8f1-464c-967d-6e7040b7ab8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792661277 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1792661277
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.401258354
Short name T753
Test name
Test status
Simulation time 833813172 ps
CPU time 2.8 seconds
Started Jul 06 05:58:29 PM PDT 24
Finished Jul 06 05:58:32 PM PDT 24
Peak memory 199496 kb
Host smart-6266bae0-2d76-4e83-9a32-a1fb92f2156e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401258354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.401258354
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.636615018
Short name T494
Test name
Test status
Simulation time 42406703816 ps
CPU time 65.63 seconds
Started Jul 06 05:58:24 PM PDT 24
Finished Jul 06 05:59:30 PM PDT 24
Peak memory 199804 kb
Host smart-5d75ce32-38bf-47dc-9a51-ee690b2dcaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636615018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.636615018
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1998131206
Short name T221
Test name
Test status
Simulation time 10134578091 ps
CPU time 12.49 seconds
Started Jul 06 06:02:17 PM PDT 24
Finished Jul 06 06:02:29 PM PDT 24
Peak memory 200020 kb
Host smart-262d49d1-44a3-4953-ae71-40f7bc72ffa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998131206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1998131206
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.79541899
Short name T328
Test name
Test status
Simulation time 90534611798 ps
CPU time 141.42 seconds
Started Jul 06 06:02:18 PM PDT 24
Finished Jul 06 06:04:40 PM PDT 24
Peak memory 199952 kb
Host smart-99e7d736-6260-4e3c-bcdf-24d22d42eb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79541899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.79541899
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2483626748
Short name T850
Test name
Test status
Simulation time 16808553231 ps
CPU time 38.44 seconds
Started Jul 06 06:02:16 PM PDT 24
Finished Jul 06 06:02:54 PM PDT 24
Peak memory 199952 kb
Host smart-9664a9fd-9780-46fe-89b7-4952e782799d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483626748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2483626748
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2816035879
Short name T239
Test name
Test status
Simulation time 121441275100 ps
CPU time 199 seconds
Started Jul 06 06:02:17 PM PDT 24
Finished Jul 06 06:05:37 PM PDT 24
Peak memory 199984 kb
Host smart-594d5649-6afa-49bb-8602-f60b184617fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816035879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2816035879
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3846033645
Short name T292
Test name
Test status
Simulation time 36372915499 ps
CPU time 50.13 seconds
Started Jul 06 06:02:15 PM PDT 24
Finished Jul 06 06:03:06 PM PDT 24
Peak memory 200012 kb
Host smart-fb5be80d-72c4-455a-99ec-4759cd4a05b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846033645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3846033645
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.627375152
Short name T385
Test name
Test status
Simulation time 16954314612 ps
CPU time 14.17 seconds
Started Jul 06 06:02:17 PM PDT 24
Finished Jul 06 06:02:31 PM PDT 24
Peak memory 199912 kb
Host smart-9a8ab298-e279-4d46-b5a7-eac2a6e40c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627375152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.627375152
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.423599158
Short name T187
Test name
Test status
Simulation time 49731549579 ps
CPU time 78.95 seconds
Started Jul 06 06:02:15 PM PDT 24
Finished Jul 06 06:03:34 PM PDT 24
Peak memory 199948 kb
Host smart-1161f026-dc85-4d9e-b0cf-3df568d9ea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423599158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.423599158
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2440682
Short name T616
Test name
Test status
Simulation time 49708683 ps
CPU time 0.56 seconds
Started Jul 06 05:58:35 PM PDT 24
Finished Jul 06 05:58:37 PM PDT 24
Peak memory 195564 kb
Host smart-033a4897-f100-4417-8895-0d9a87118028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2440682
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.529664222
Short name T989
Test name
Test status
Simulation time 162212069736 ps
CPU time 125.56 seconds
Started Jul 06 05:58:34 PM PDT 24
Finished Jul 06 06:00:41 PM PDT 24
Peak memory 199992 kb
Host smart-4a3e879b-8577-45d0-800f-faf15df5dc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529664222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.529664222
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2443250791
Short name T882
Test name
Test status
Simulation time 117246462764 ps
CPU time 204.83 seconds
Started Jul 06 05:58:35 PM PDT 24
Finished Jul 06 06:02:00 PM PDT 24
Peak memory 199900 kb
Host smart-704af6f4-577e-455f-91d1-52212f1161d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443250791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2443250791
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3460497054
Short name T348
Test name
Test status
Simulation time 37895854814 ps
CPU time 33.22 seconds
Started Jul 06 05:58:32 PM PDT 24
Finished Jul 06 05:59:06 PM PDT 24
Peak memory 199968 kb
Host smart-1279cc16-f6d7-4dba-995b-d74bb82e4f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460497054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3460497054
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.987523183
Short name T405
Test name
Test status
Simulation time 21650463197 ps
CPU time 34.32 seconds
Started Jul 06 05:58:31 PM PDT 24
Finished Jul 06 05:59:06 PM PDT 24
Peak memory 199952 kb
Host smart-09ae8b71-bac6-4c54-8d1e-7b5697ba28fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987523183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.987523183
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3863020797
Short name T1090
Test name
Test status
Simulation time 110361521957 ps
CPU time 1204.88 seconds
Started Jul 06 05:58:32 PM PDT 24
Finished Jul 06 06:18:37 PM PDT 24
Peak memory 199924 kb
Host smart-af7f223f-0bd6-4188-a314-7bd3f5a6c579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3863020797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3863020797
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3836552120
Short name T727
Test name
Test status
Simulation time 7339458088 ps
CPU time 5.04 seconds
Started Jul 06 05:58:33 PM PDT 24
Finished Jul 06 05:58:38 PM PDT 24
Peak memory 198384 kb
Host smart-88990e1a-0357-42f7-9459-5ec4237ab601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836552120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3836552120
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2710527348
Short name T378
Test name
Test status
Simulation time 19288881770 ps
CPU time 13.43 seconds
Started Jul 06 05:58:33 PM PDT 24
Finished Jul 06 05:58:47 PM PDT 24
Peak memory 194472 kb
Host smart-1fa79193-2440-4269-8c92-5c6eb90bea79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710527348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2710527348
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2475182744
Short name T931
Test name
Test status
Simulation time 9455120127 ps
CPU time 267.9 seconds
Started Jul 06 05:58:34 PM PDT 24
Finished Jul 06 06:03:02 PM PDT 24
Peak memory 200004 kb
Host smart-ff8392e5-790c-4333-aa5f-a465bf6b8e39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475182744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2475182744
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.599257742
Short name T1173
Test name
Test status
Simulation time 3927711055 ps
CPU time 13.47 seconds
Started Jul 06 05:58:33 PM PDT 24
Finished Jul 06 05:58:47 PM PDT 24
Peak memory 198188 kb
Host smart-84faae56-7e7a-4491-9429-f90cbfdcf527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599257742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.599257742
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.564363540
Short name T505
Test name
Test status
Simulation time 20469060132 ps
CPU time 8.78 seconds
Started Jul 06 05:58:36 PM PDT 24
Finished Jul 06 05:58:45 PM PDT 24
Peak memory 199972 kb
Host smart-cd7276ef-175b-429f-bc5d-bef3ff4caaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564363540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.564363540
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3928723779
Short name T720
Test name
Test status
Simulation time 5265107025 ps
CPU time 9.12 seconds
Started Jul 06 05:58:32 PM PDT 24
Finished Jul 06 05:58:41 PM PDT 24
Peak memory 196260 kb
Host smart-00d1da40-b503-46f0-8d8c-25da269f284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928723779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3928723779
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3907078456
Short name T926
Test name
Test status
Simulation time 5448181133 ps
CPU time 17.65 seconds
Started Jul 06 05:58:34 PM PDT 24
Finished Jul 06 05:58:53 PM PDT 24
Peak memory 199736 kb
Host smart-c9d01615-e2c2-4b60-b6f1-8e1dca3c1c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907078456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3907078456
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3586885451
Short name T643
Test name
Test status
Simulation time 305912219194 ps
CPU time 1502.54 seconds
Started Jul 06 05:58:36 PM PDT 24
Finished Jul 06 06:23:39 PM PDT 24
Peak memory 199888 kb
Host smart-9d561dc2-1e25-445a-aca9-45ef30f1e71a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586885451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3586885451
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3727068471
Short name T1010
Test name
Test status
Simulation time 948375268877 ps
CPU time 1375.11 seconds
Started Jul 06 05:58:33 PM PDT 24
Finished Jul 06 06:21:28 PM PDT 24
Peak memory 228788 kb
Host smart-395921ac-980d-43bd-9d63-c19abaa91e93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727068471 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3727068471
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.134259702
Short name T835
Test name
Test status
Simulation time 1845724187 ps
CPU time 1.77 seconds
Started Jul 06 05:58:31 PM PDT 24
Finished Jul 06 05:58:33 PM PDT 24
Peak memory 198816 kb
Host smart-c69c2a56-d4e3-42ee-8466-8b1e9434869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134259702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.134259702
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.871241476
Short name T626
Test name
Test status
Simulation time 54656973268 ps
CPU time 15.66 seconds
Started Jul 06 05:58:35 PM PDT 24
Finished Jul 06 05:58:51 PM PDT 24
Peak memory 199940 kb
Host smart-98b3d03a-be41-4491-9695-0cd8fe4d58fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871241476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.871241476
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.452703074
Short name T525
Test name
Test status
Simulation time 201584629715 ps
CPU time 27.78 seconds
Started Jul 06 06:02:16 PM PDT 24
Finished Jul 06 06:02:44 PM PDT 24
Peak memory 199952 kb
Host smart-b3ce3b78-55a9-4045-a7bd-35ce93874702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452703074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.452703074
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.816162407
Short name T322
Test name
Test status
Simulation time 172135635443 ps
CPU time 260.63 seconds
Started Jul 06 06:02:15 PM PDT 24
Finished Jul 06 06:06:36 PM PDT 24
Peak memory 199916 kb
Host smart-b6e1e19f-2551-4381-82e3-c1dcf732f740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816162407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.816162407
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1405288794
Short name T641
Test name
Test status
Simulation time 17203708917 ps
CPU time 22.57 seconds
Started Jul 06 06:02:16 PM PDT 24
Finished Jul 06 06:02:38 PM PDT 24
Peak memory 199776 kb
Host smart-6f1331da-aaaf-4f7c-bf06-ebbdced6a7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405288794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1405288794
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2529947035
Short name T590
Test name
Test status
Simulation time 25996270922 ps
CPU time 20.69 seconds
Started Jul 06 06:02:23 PM PDT 24
Finished Jul 06 06:02:44 PM PDT 24
Peak memory 199988 kb
Host smart-ddb84b5e-d029-4e7a-bb7d-bee0b4c66ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529947035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2529947035
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.502729657
Short name T660
Test name
Test status
Simulation time 128264099143 ps
CPU time 106.58 seconds
Started Jul 06 06:02:21 PM PDT 24
Finished Jul 06 06:04:08 PM PDT 24
Peak memory 200004 kb
Host smart-fbb22f60-681e-45d1-be7e-916c90b1aac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502729657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.502729657
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.4120146276
Short name T693
Test name
Test status
Simulation time 55214126409 ps
CPU time 25.01 seconds
Started Jul 06 06:02:22 PM PDT 24
Finished Jul 06 06:02:47 PM PDT 24
Peak memory 199988 kb
Host smart-dd80cb4f-4b51-4bce-9ea1-7473f7d9a3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120146276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4120146276
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2370307662
Short name T1151
Test name
Test status
Simulation time 68160111390 ps
CPU time 79.32 seconds
Started Jul 06 06:02:20 PM PDT 24
Finished Jul 06 06:03:39 PM PDT 24
Peak memory 199988 kb
Host smart-f9a1cc17-2007-47ab-9172-20dc08457461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370307662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2370307662
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2663372029
Short name T498
Test name
Test status
Simulation time 86122038319 ps
CPU time 40.63 seconds
Started Jul 06 06:02:21 PM PDT 24
Finished Jul 06 06:03:02 PM PDT 24
Peak memory 199912 kb
Host smart-75eae7db-0302-4abd-be05-1f25679be6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663372029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2663372029
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3626810403
Short name T996
Test name
Test status
Simulation time 104706325545 ps
CPU time 27.22 seconds
Started Jul 06 06:02:24 PM PDT 24
Finished Jul 06 06:02:52 PM PDT 24
Peak memory 199924 kb
Host smart-bccade2a-e550-4f02-86cf-5828cec89de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626810403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3626810403
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1781788756
Short name T18
Test name
Test status
Simulation time 14024969 ps
CPU time 0.54 seconds
Started Jul 06 05:58:38 PM PDT 24
Finished Jul 06 05:58:39 PM PDT 24
Peak memory 195336 kb
Host smart-79a2e52c-d550-4af3-868f-6e5f002354eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781788756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1781788756
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1395576858
Short name T168
Test name
Test status
Simulation time 56090559573 ps
CPU time 18.06 seconds
Started Jul 06 05:58:32 PM PDT 24
Finished Jul 06 05:58:50 PM PDT 24
Peak memory 199944 kb
Host smart-b15b1e98-4af6-4b53-9345-fd66526175c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395576858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1395576858
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.925231605
Short name T1031
Test name
Test status
Simulation time 115747957624 ps
CPU time 91.32 seconds
Started Jul 06 05:58:34 PM PDT 24
Finished Jul 06 06:00:06 PM PDT 24
Peak memory 199908 kb
Host smart-b8a367ac-a1f6-4f94-8b91-bc827d5d0044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925231605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.925231605
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1429690273
Short name T133
Test name
Test status
Simulation time 29978364291 ps
CPU time 13.08 seconds
Started Jul 06 05:58:35 PM PDT 24
Finished Jul 06 05:58:49 PM PDT 24
Peak memory 199992 kb
Host smart-1bff874d-c719-49fd-89a4-fd31a5fea95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429690273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1429690273
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2444794540
Short name T992
Test name
Test status
Simulation time 30924173205 ps
CPU time 43.9 seconds
Started Jul 06 05:58:33 PM PDT 24
Finished Jul 06 05:59:17 PM PDT 24
Peak memory 199484 kb
Host smart-f3a43b9c-4dd3-4ce6-98a9-873fa7062a7d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444794540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2444794540
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.4272055476
Short name T279
Test name
Test status
Simulation time 61347694909 ps
CPU time 506.44 seconds
Started Jul 06 05:58:36 PM PDT 24
Finished Jul 06 06:07:03 PM PDT 24
Peak memory 199920 kb
Host smart-deb76e6e-26af-49df-9124-9b64404366ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272055476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.4272055476
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3305294547
Short name T666
Test name
Test status
Simulation time 5832244159 ps
CPU time 2.53 seconds
Started Jul 06 05:58:39 PM PDT 24
Finished Jul 06 05:58:42 PM PDT 24
Peak memory 195824 kb
Host smart-3677432a-e1ea-4fb8-86a1-4a55c847daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305294547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3305294547
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1292130478
Short name T62
Test name
Test status
Simulation time 38212514872 ps
CPU time 29.34 seconds
Started Jul 06 05:58:32 PM PDT 24
Finished Jul 06 05:59:01 PM PDT 24
Peak memory 199480 kb
Host smart-6e399a70-f43c-4338-9f7a-d1327e2a840a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292130478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1292130478
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.209031448
Short name T725
Test name
Test status
Simulation time 20045349916 ps
CPU time 621.3 seconds
Started Jul 06 05:58:39 PM PDT 24
Finished Jul 06 06:09:00 PM PDT 24
Peak memory 200004 kb
Host smart-4f959661-0852-4c65-8eed-29124cdb6fdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209031448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.209031448
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1569669788
Short name T857
Test name
Test status
Simulation time 3277576343 ps
CPU time 25.98 seconds
Started Jul 06 05:58:36 PM PDT 24
Finished Jul 06 05:59:03 PM PDT 24
Peak memory 199208 kb
Host smart-76ae2d7b-abb1-4e0d-8c6d-3dff7638c132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1569669788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1569669788
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.4193921555
Short name T794
Test name
Test status
Simulation time 19814893139 ps
CPU time 15.74 seconds
Started Jul 06 05:58:38 PM PDT 24
Finished Jul 06 05:58:54 PM PDT 24
Peak memory 199836 kb
Host smart-caa423a9-883b-4c98-98c4-ecaf327490cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193921555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.4193921555
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.278142574
Short name T657
Test name
Test status
Simulation time 718872483 ps
CPU time 0.87 seconds
Started Jul 06 05:58:32 PM PDT 24
Finished Jul 06 05:58:33 PM PDT 24
Peak memory 195404 kb
Host smart-efe5b55a-c3b5-4cc6-a908-ad2a26e16593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278142574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.278142574
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2532535704
Short name T393
Test name
Test status
Simulation time 642785661 ps
CPU time 1.21 seconds
Started Jul 06 05:58:34 PM PDT 24
Finished Jul 06 05:58:36 PM PDT 24
Peak memory 198632 kb
Host smart-70a0ec08-b371-42f2-b68d-858b2a28ab07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532535704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2532535704
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.700776289
Short name T524
Test name
Test status
Simulation time 350115564580 ps
CPU time 999.4 seconds
Started Jul 06 05:58:36 PM PDT 24
Finished Jul 06 06:15:16 PM PDT 24
Peak memory 200036 kb
Host smart-fa6a1b55-60d4-4232-8e7f-be7bcd9bd526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700776289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.700776289
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.4027101767
Short name T1138
Test name
Test status
Simulation time 31898065899 ps
CPU time 108.54 seconds
Started Jul 06 05:58:41 PM PDT 24
Finished Jul 06 06:00:30 PM PDT 24
Peak memory 216644 kb
Host smart-8d5505d1-0c69-42b8-9468-012b6c2baca0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027101767 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.4027101767
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.24353449
Short name T318
Test name
Test status
Simulation time 409658536 ps
CPU time 1.72 seconds
Started Jul 06 05:58:37 PM PDT 24
Finished Jul 06 05:58:39 PM PDT 24
Peak memory 198596 kb
Host smart-599d8640-4d25-4231-b252-5b3848e59d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24353449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.24353449
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3734961527
Short name T460
Test name
Test status
Simulation time 58963070743 ps
CPU time 49.81 seconds
Started Jul 06 05:58:36 PM PDT 24
Finished Jul 06 05:59:26 PM PDT 24
Peak memory 200024 kb
Host smart-c70422b1-916c-400d-96dd-a4bea624a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734961527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3734961527
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2318105224
Short name T345
Test name
Test status
Simulation time 31442985748 ps
CPU time 16.79 seconds
Started Jul 06 06:02:20 PM PDT 24
Finished Jul 06 06:02:38 PM PDT 24
Peak memory 199940 kb
Host smart-efdf2b66-871f-4535-9e3d-b4a4ac4ea8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318105224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2318105224
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3503867782
Short name T679
Test name
Test status
Simulation time 24366908981 ps
CPU time 37.72 seconds
Started Jul 06 06:02:22 PM PDT 24
Finished Jul 06 06:03:00 PM PDT 24
Peak memory 199860 kb
Host smart-fb88c0f2-e9bb-4d95-864e-0134d8e2fed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503867782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3503867782
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.4097866450
Short name T577
Test name
Test status
Simulation time 160102808644 ps
CPU time 68.7 seconds
Started Jul 06 06:02:20 PM PDT 24
Finished Jul 06 06:03:29 PM PDT 24
Peak memory 199920 kb
Host smart-b81d9a68-5f00-4ca1-a885-f5bf5a573f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097866450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.4097866450
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.990669695
Short name T499
Test name
Test status
Simulation time 152270344372 ps
CPU time 59.79 seconds
Started Jul 06 06:02:20 PM PDT 24
Finished Jul 06 06:03:20 PM PDT 24
Peak memory 199952 kb
Host smart-15cf0e12-4029-412d-a9b9-d1fc882be664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990669695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.990669695
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1629031914
Short name T375
Test name
Test status
Simulation time 7413595713 ps
CPU time 15.09 seconds
Started Jul 06 06:02:24 PM PDT 24
Finished Jul 06 06:02:39 PM PDT 24
Peak memory 199968 kb
Host smart-eae89c01-ae90-4e2d-a760-b5c19065b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629031914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1629031914
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3076364714
Short name T905
Test name
Test status
Simulation time 140579137652 ps
CPU time 217.73 seconds
Started Jul 06 06:02:20 PM PDT 24
Finished Jul 06 06:05:58 PM PDT 24
Peak memory 199944 kb
Host smart-c5433c8f-0bad-49ce-bf53-70680c91356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076364714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3076364714
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1219826903
Short name T289
Test name
Test status
Simulation time 12552924112 ps
CPU time 24.81 seconds
Started Jul 06 06:02:25 PM PDT 24
Finished Jul 06 06:02:50 PM PDT 24
Peak memory 199920 kb
Host smart-8b86c9e8-4d0a-48ce-883a-fa874ce76fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219826903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1219826903
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.84442857
Short name T403
Test name
Test status
Simulation time 17562443321 ps
CPU time 27.45 seconds
Started Jul 06 06:02:27 PM PDT 24
Finished Jul 06 06:02:55 PM PDT 24
Peak memory 199996 kb
Host smart-d1a6a87c-b28c-4ace-b392-46ffa97ce580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84442857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.84442857
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3733595164
Short name T818
Test name
Test status
Simulation time 81167481178 ps
CPU time 105.85 seconds
Started Jul 06 06:02:27 PM PDT 24
Finished Jul 06 06:04:13 PM PDT 24
Peak memory 200020 kb
Host smart-441f271c-68c4-4505-b024-36ceb4965751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733595164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3733595164
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.55752863
Short name T816
Test name
Test status
Simulation time 15613562 ps
CPU time 0.54 seconds
Started Jul 06 05:58:42 PM PDT 24
Finished Jul 06 05:58:42 PM PDT 24
Peak memory 194576 kb
Host smart-369243e8-6f13-426d-b25a-4078490d0546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55752863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.55752863
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1766165031
Short name T502
Test name
Test status
Simulation time 79491887548 ps
CPU time 143.05 seconds
Started Jul 06 05:58:38 PM PDT 24
Finished Jul 06 06:01:02 PM PDT 24
Peak memory 199904 kb
Host smart-c8def7c5-9d8a-4991-93ab-d7de8f61ac07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766165031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1766165031
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.851133571
Short name T625
Test name
Test status
Simulation time 80167490416 ps
CPU time 172.33 seconds
Started Jul 06 05:58:37 PM PDT 24
Finished Jul 06 06:01:30 PM PDT 24
Peak memory 199728 kb
Host smart-a06c1e65-eb58-403d-9767-bd1b907f2271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851133571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.851133571
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1214053885
Short name T235
Test name
Test status
Simulation time 19906518866 ps
CPU time 29.09 seconds
Started Jul 06 05:58:42 PM PDT 24
Finished Jul 06 05:59:11 PM PDT 24
Peak memory 199892 kb
Host smart-2f78d756-3a0e-4b32-b22b-7d5780a9bade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214053885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1214053885
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1994877905
Short name T1097
Test name
Test status
Simulation time 54277333824 ps
CPU time 102.77 seconds
Started Jul 06 05:58:42 PM PDT 24
Finished Jul 06 06:00:25 PM PDT 24
Peak memory 199940 kb
Host smart-3aa39cfb-cf38-4e47-970b-e4bc22d06d6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994877905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1994877905
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_loopback.396986424
Short name T585
Test name
Test status
Simulation time 3086204134 ps
CPU time 1.11 seconds
Started Jul 06 05:58:42 PM PDT 24
Finished Jul 06 05:58:44 PM PDT 24
Peak memory 198216 kb
Host smart-3e7e020d-6e0c-4cc1-904b-08913eea15ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396986424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.396986424
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3602661277
Short name T852
Test name
Test status
Simulation time 58592193802 ps
CPU time 46.69 seconds
Started Jul 06 05:58:41 PM PDT 24
Finished Jul 06 05:59:28 PM PDT 24
Peak memory 200092 kb
Host smart-355132d6-cd25-41af-ab5a-a32e2d417ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602661277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3602661277
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1322184737
Short name T1145
Test name
Test status
Simulation time 15834927556 ps
CPU time 204.14 seconds
Started Jul 06 05:58:44 PM PDT 24
Finished Jul 06 06:02:09 PM PDT 24
Peak memory 199956 kb
Host smart-74536024-f830-4839-896f-a6d2102e57ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1322184737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1322184737
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4022705618
Short name T776
Test name
Test status
Simulation time 3674171235 ps
CPU time 29.6 seconds
Started Jul 06 05:58:38 PM PDT 24
Finished Jul 06 05:59:08 PM PDT 24
Peak memory 198056 kb
Host smart-72f4b875-ba15-44dd-95b0-0c72366f1de3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022705618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4022705618
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3511171458
Short name T422
Test name
Test status
Simulation time 11236488186 ps
CPU time 19.27 seconds
Started Jul 06 05:58:40 PM PDT 24
Finished Jul 06 05:58:59 PM PDT 24
Peak memory 199960 kb
Host smart-7061a2ac-4f28-485c-bee9-72efbd4b3741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511171458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3511171458
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4176266149
Short name T576
Test name
Test status
Simulation time 1006339825 ps
CPU time 2.23 seconds
Started Jul 06 05:58:44 PM PDT 24
Finished Jul 06 05:58:47 PM PDT 24
Peak memory 195416 kb
Host smart-5947079b-0969-4d90-8c5c-56b456c69ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176266149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4176266149
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.815484928
Short name T1050
Test name
Test status
Simulation time 5594628818 ps
CPU time 4.75 seconds
Started Jul 06 05:58:41 PM PDT 24
Finished Jul 06 05:58:46 PM PDT 24
Peak memory 199844 kb
Host smart-eb53cff5-10ce-4395-a494-1a9433f8e67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815484928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.815484928
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3312267756
Short name T412
Test name
Test status
Simulation time 153042751906 ps
CPU time 499.07 seconds
Started Jul 06 05:58:43 PM PDT 24
Finished Jul 06 06:07:03 PM PDT 24
Peak memory 199976 kb
Host smart-ab35c2e4-9a68-4919-af09-2df0407e5117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312267756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3312267756
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.16869326
Short name T288
Test name
Test status
Simulation time 60778704031 ps
CPU time 397.41 seconds
Started Jul 06 05:58:42 PM PDT 24
Finished Jul 06 06:05:20 PM PDT 24
Peak memory 216520 kb
Host smart-99055ddf-69eb-4547-a65a-b334cd6f0e54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869326 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.16869326
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2076785700
Short name T1153
Test name
Test status
Simulation time 902401203 ps
CPU time 3.21 seconds
Started Jul 06 05:58:43 PM PDT 24
Finished Jul 06 05:58:47 PM PDT 24
Peak memory 199596 kb
Host smart-e49ace16-9ac1-4e29-a635-a2f27b36500f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076785700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2076785700
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2784735648
Short name T485
Test name
Test status
Simulation time 19314217471 ps
CPU time 16.78 seconds
Started Jul 06 05:58:40 PM PDT 24
Finished Jul 06 05:58:57 PM PDT 24
Peak memory 199976 kb
Host smart-614065f3-3502-40b6-a2d8-586cd45d857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784735648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2784735648
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.4082388292
Short name T552
Test name
Test status
Simulation time 17138847862 ps
CPU time 38.04 seconds
Started Jul 06 06:02:27 PM PDT 24
Finished Jul 06 06:03:06 PM PDT 24
Peak memory 200008 kb
Host smart-88e14f94-35b0-491d-b745-16bb237e74a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082388292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.4082388292
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1759988674
Short name T1125
Test name
Test status
Simulation time 102387133936 ps
CPU time 175.11 seconds
Started Jul 06 06:02:25 PM PDT 24
Finished Jul 06 06:05:20 PM PDT 24
Peak memory 199920 kb
Host smart-cbeca32d-7ecc-498d-8d7c-6c5fc86089ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759988674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1759988674
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.904615111
Short name T808
Test name
Test status
Simulation time 53899246535 ps
CPU time 77.83 seconds
Started Jul 06 06:02:28 PM PDT 24
Finished Jul 06 06:03:46 PM PDT 24
Peak memory 199932 kb
Host smart-b5eed661-005f-4299-806a-4f39e53f4400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904615111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.904615111
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2010979969
Short name T902
Test name
Test status
Simulation time 33955669339 ps
CPU time 14.34 seconds
Started Jul 06 06:02:25 PM PDT 24
Finished Jul 06 06:02:40 PM PDT 24
Peak memory 199848 kb
Host smart-b83425dc-78ea-4427-92d4-c838a0e03d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010979969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2010979969
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2991668147
Short name T868
Test name
Test status
Simulation time 123715154580 ps
CPU time 238.22 seconds
Started Jul 06 06:02:28 PM PDT 24
Finished Jul 06 06:06:27 PM PDT 24
Peak memory 199852 kb
Host smart-eae4b803-aa22-412e-b9ee-2b1adaaf0822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991668147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2991668147
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1987427897
Short name T879
Test name
Test status
Simulation time 92563678603 ps
CPU time 41.86 seconds
Started Jul 06 06:02:26 PM PDT 24
Finished Jul 06 06:03:08 PM PDT 24
Peak memory 199748 kb
Host smart-f26d4edb-af8a-460d-8dcc-36bc66621620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987427897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1987427897
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3908203151
Short name T928
Test name
Test status
Simulation time 83588437381 ps
CPU time 129.6 seconds
Started Jul 06 06:02:26 PM PDT 24
Finished Jul 06 06:04:36 PM PDT 24
Peak memory 199944 kb
Host smart-01e06c1d-07d1-40f0-b973-0b737eabe0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908203151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3908203151
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3979044141
Short name T675
Test name
Test status
Simulation time 15244038863 ps
CPU time 6.23 seconds
Started Jul 06 06:02:27 PM PDT 24
Finished Jul 06 06:02:33 PM PDT 24
Peak memory 199864 kb
Host smart-c976581e-09f2-4d0d-a196-002dcd7397b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979044141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3979044141
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1824432030
Short name T714
Test name
Test status
Simulation time 26596944965 ps
CPU time 50.1 seconds
Started Jul 06 06:02:29 PM PDT 24
Finished Jul 06 06:03:19 PM PDT 24
Peak memory 199940 kb
Host smart-991f1090-10a9-410d-8dd5-9198cde5b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824432030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1824432030
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.211082761
Short name T169
Test name
Test status
Simulation time 153652259669 ps
CPU time 57.15 seconds
Started Jul 06 06:02:30 PM PDT 24
Finished Jul 06 06:03:28 PM PDT 24
Peak memory 199936 kb
Host smart-089e414a-78e7-46e8-b062-170823c44749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211082761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.211082761
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1382985165
Short name T426
Test name
Test status
Simulation time 49075673 ps
CPU time 0.54 seconds
Started Jul 06 05:58:46 PM PDT 24
Finished Jul 06 05:58:46 PM PDT 24
Peak memory 195252 kb
Host smart-10b01417-18d6-487c-8f98-b5c420b92257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382985165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1382985165
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1916219928
Short name T915
Test name
Test status
Simulation time 107704701867 ps
CPU time 172.37 seconds
Started Jul 06 05:58:44 PM PDT 24
Finished Jul 06 06:01:37 PM PDT 24
Peak memory 199880 kb
Host smart-c2ad589d-f7fa-4c8b-9901-37905e789637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916219928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1916219928
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1426965277
Short name T674
Test name
Test status
Simulation time 87046768034 ps
CPU time 34.28 seconds
Started Jul 06 05:58:43 PM PDT 24
Finished Jul 06 05:59:17 PM PDT 24
Peak memory 199776 kb
Host smart-0d2c44d7-bb74-4d25-9fb0-de62c0b33f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426965277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1426965277
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.75475923
Short name T536
Test name
Test status
Simulation time 82100411937 ps
CPU time 124.03 seconds
Started Jul 06 05:58:44 PM PDT 24
Finished Jul 06 06:00:48 PM PDT 24
Peak memory 199996 kb
Host smart-06df1d71-37ac-4dce-b473-b699f8fc73b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75475923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.75475923
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3505730620
Short name T549
Test name
Test status
Simulation time 25888588247 ps
CPU time 7.46 seconds
Started Jul 06 05:58:44 PM PDT 24
Finished Jul 06 05:58:52 PM PDT 24
Peak memory 199948 kb
Host smart-aa1f0816-a196-4da5-9726-415482c1e3d4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505730620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3505730620
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.4105982947
Short name T881
Test name
Test status
Simulation time 36227631844 ps
CPU time 87.88 seconds
Started Jul 06 05:58:46 PM PDT 24
Finished Jul 06 06:00:15 PM PDT 24
Peak memory 199956 kb
Host smart-821e5b0b-42f1-4323-88cb-1fc223725c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4105982947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.4105982947
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3267081632
Short name T951
Test name
Test status
Simulation time 3682712596 ps
CPU time 2.8 seconds
Started Jul 06 05:58:49 PM PDT 24
Finished Jul 06 05:58:52 PM PDT 24
Peak memory 198764 kb
Host smart-b03a8c2c-3e7c-48a3-9df6-52cb455822a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267081632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3267081632
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3213799510
Short name T264
Test name
Test status
Simulation time 39682050388 ps
CPU time 90.19 seconds
Started Jul 06 05:58:42 PM PDT 24
Finished Jul 06 06:00:13 PM PDT 24
Peak memory 200084 kb
Host smart-f2463e50-0125-4cfc-9da8-1445030d6105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213799510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3213799510
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.159775286
Short name T1074
Test name
Test status
Simulation time 17555763885 ps
CPU time 229.93 seconds
Started Jul 06 05:58:47 PM PDT 24
Finished Jul 06 06:02:38 PM PDT 24
Peak memory 199964 kb
Host smart-9102754d-d0f7-457c-a6f8-b0a571e6f436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159775286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.159775286
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1497202150
Short name T1120
Test name
Test status
Simulation time 2244706024 ps
CPU time 2.81 seconds
Started Jul 06 05:58:42 PM PDT 24
Finished Jul 06 05:58:45 PM PDT 24
Peak memory 198224 kb
Host smart-dc805890-336d-40c4-b36c-0be2a1d95633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497202150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1497202150
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3923429073
Short name T147
Test name
Test status
Simulation time 204877629267 ps
CPU time 66.5 seconds
Started Jul 06 05:58:44 PM PDT 24
Finished Jul 06 05:59:51 PM PDT 24
Peak memory 199872 kb
Host smart-57db32e6-dcae-498c-8660-a48605813dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923429073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3923429073
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.4120636387
Short name T744
Test name
Test status
Simulation time 4495434385 ps
CPU time 1.13 seconds
Started Jul 06 05:58:42 PM PDT 24
Finished Jul 06 05:58:44 PM PDT 24
Peak memory 196168 kb
Host smart-7207a3d5-a989-472c-b7c4-b6ea4098b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120636387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.4120636387
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2039977074
Short name T1171
Test name
Test status
Simulation time 5902693574 ps
CPU time 19.76 seconds
Started Jul 06 05:58:44 PM PDT 24
Finished Jul 06 05:59:04 PM PDT 24
Peak memory 199924 kb
Host smart-62b9f4a8-4e2a-4ba5-a21b-69e6ba2ffef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039977074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2039977074
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3262397381
Short name T1075
Test name
Test status
Simulation time 408652337955 ps
CPU time 44.56 seconds
Started Jul 06 05:58:46 PM PDT 24
Finished Jul 06 05:59:31 PM PDT 24
Peak memory 199948 kb
Host smart-6852fb9f-88f5-420e-bb65-6c7879a57128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262397381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3262397381
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.914092664
Short name T24
Test name
Test status
Simulation time 28588408065 ps
CPU time 168.2 seconds
Started Jul 06 05:58:49 PM PDT 24
Finished Jul 06 06:01:37 PM PDT 24
Peak memory 210744 kb
Host smart-c7149d2b-9d8a-4472-98cb-6e832a12ec08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914092664 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.914092664
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1095595745
Short name T369
Test name
Test status
Simulation time 725137468 ps
CPU time 2.05 seconds
Started Jul 06 05:58:43 PM PDT 24
Finished Jul 06 05:58:45 PM PDT 24
Peak memory 198172 kb
Host smart-9f36e672-b4a4-4d1e-9527-9bd002b037b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095595745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1095595745
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.648557393
Short name T908
Test name
Test status
Simulation time 114516502836 ps
CPU time 100.88 seconds
Started Jul 06 05:58:42 PM PDT 24
Finished Jul 06 06:00:23 PM PDT 24
Peak memory 199940 kb
Host smart-c03040de-6136-4519-8a63-13aed2a5c01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648557393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.648557393
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3522697222
Short name T958
Test name
Test status
Simulation time 4770547440 ps
CPU time 8.23 seconds
Started Jul 06 06:02:30 PM PDT 24
Finished Jul 06 06:02:38 PM PDT 24
Peak memory 198572 kb
Host smart-b321f240-a77b-43c1-b3a3-509a7605d736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522697222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3522697222
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.51756311
Short name T189
Test name
Test status
Simulation time 19828256777 ps
CPU time 31.77 seconds
Started Jul 06 06:02:32 PM PDT 24
Finished Jul 06 06:03:04 PM PDT 24
Peak memory 199920 kb
Host smart-3f1fa5b8-da01-4e92-887b-c54e9d34b731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51756311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.51756311
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3626659067
Short name T343
Test name
Test status
Simulation time 113276456230 ps
CPU time 175.16 seconds
Started Jul 06 06:02:35 PM PDT 24
Finished Jul 06 06:05:30 PM PDT 24
Peak memory 199904 kb
Host smart-8c74d6d8-8a71-4150-aae6-531156b18268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626659067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3626659067
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3813500825
Short name T470
Test name
Test status
Simulation time 236242285119 ps
CPU time 96.67 seconds
Started Jul 06 06:02:31 PM PDT 24
Finished Jul 06 06:04:08 PM PDT 24
Peak memory 199912 kb
Host smart-79706670-97d6-4c7a-a9b9-4335c443e0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813500825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3813500825
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3492079433
Short name T893
Test name
Test status
Simulation time 56593811883 ps
CPU time 22.76 seconds
Started Jul 06 06:02:31 PM PDT 24
Finished Jul 06 06:02:54 PM PDT 24
Peak memory 199892 kb
Host smart-111a5393-a3ad-44a8-b8f0-0041765e51b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492079433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3492079433
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.809963097
Short name T1094
Test name
Test status
Simulation time 25987853334 ps
CPU time 34.99 seconds
Started Jul 06 06:02:32 PM PDT 24
Finished Jul 06 06:03:07 PM PDT 24
Peak memory 199808 kb
Host smart-6e7a7b32-54cd-4668-80fd-963d944ac103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809963097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.809963097
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3358984905
Short name T1109
Test name
Test status
Simulation time 18852738894 ps
CPU time 9.37 seconds
Started Jul 06 06:02:33 PM PDT 24
Finished Jul 06 06:02:43 PM PDT 24
Peak memory 199704 kb
Host smart-d1f8b4f1-b948-4e85-9bf4-674b6a1c049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358984905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3358984905
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.728852789
Short name T1014
Test name
Test status
Simulation time 60598138005 ps
CPU time 27.14 seconds
Started Jul 06 06:02:30 PM PDT 24
Finished Jul 06 06:02:57 PM PDT 24
Peak memory 199924 kb
Host smart-f45db991-8da3-436f-aabc-ad9d91cb5284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728852789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.728852789
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3641512925
Short name T1129
Test name
Test status
Simulation time 13276800 ps
CPU time 0.56 seconds
Started Jul 06 05:58:51 PM PDT 24
Finished Jul 06 05:58:51 PM PDT 24
Peak memory 195284 kb
Host smart-7e2be667-a298-4576-bb83-ee935832f268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641512925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3641512925
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3898765179
Short name T431
Test name
Test status
Simulation time 33973552377 ps
CPU time 52.09 seconds
Started Jul 06 05:58:47 PM PDT 24
Finished Jul 06 05:59:39 PM PDT 24
Peak memory 199924 kb
Host smart-9751654e-c71c-4d4c-8ca0-88e59ec2ebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898765179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3898765179
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1812276643
Short name T826
Test name
Test status
Simulation time 229641488351 ps
CPU time 58.98 seconds
Started Jul 06 05:58:50 PM PDT 24
Finished Jul 06 05:59:49 PM PDT 24
Peak memory 199904 kb
Host smart-d3ed8040-705f-4d73-8e2a-95dd87116344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812276643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1812276643
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3654533622
Short name T872
Test name
Test status
Simulation time 97189640037 ps
CPU time 442.85 seconds
Started Jul 06 05:58:45 PM PDT 24
Finished Jul 06 06:06:08 PM PDT 24
Peak memory 200008 kb
Host smart-d8b45df5-6afc-400f-81d0-38e79a129c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654533622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3654533622
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1234578417
Short name T557
Test name
Test status
Simulation time 173124314003 ps
CPU time 78.78 seconds
Started Jul 06 05:58:45 PM PDT 24
Finished Jul 06 06:00:04 PM PDT 24
Peak memory 199840 kb
Host smart-e32ad3a3-925a-4f93-abd2-388afece60ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234578417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1234578417
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2128975678
Short name T416
Test name
Test status
Simulation time 175113219455 ps
CPU time 377.31 seconds
Started Jul 06 05:58:49 PM PDT 24
Finished Jul 06 06:05:07 PM PDT 24
Peak memory 199916 kb
Host smart-f63abeec-95f0-4461-8977-f4f822563751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128975678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2128975678
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1151567962
Short name T1006
Test name
Test status
Simulation time 9874916862 ps
CPU time 20.27 seconds
Started Jul 06 05:58:49 PM PDT 24
Finished Jul 06 05:59:10 PM PDT 24
Peak memory 199944 kb
Host smart-331f8e89-61c9-4fab-b3da-925bc2cfc726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151567962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1151567962
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.24253511
Short name T811
Test name
Test status
Simulation time 78563850544 ps
CPU time 17.36 seconds
Started Jul 06 05:58:47 PM PDT 24
Finished Jul 06 05:59:05 PM PDT 24
Peak memory 200076 kb
Host smart-0119e070-a88b-4d05-bfd6-c36bc256abbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24253511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.24253511
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1361243438
Short name T80
Test name
Test status
Simulation time 3711670879 ps
CPU time 54.81 seconds
Started Jul 06 05:58:50 PM PDT 24
Finished Jul 06 05:59:45 PM PDT 24
Peak memory 200004 kb
Host smart-5f9c22f4-e883-45de-94af-3499d3b04a1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361243438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1361243438
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.731984204
Short name T354
Test name
Test status
Simulation time 2136408692 ps
CPU time 3.58 seconds
Started Jul 06 05:58:45 PM PDT 24
Finished Jul 06 05:58:49 PM PDT 24
Peak memory 198040 kb
Host smart-d472e207-ae9f-4a4d-8d01-96b5c378cd2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731984204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.731984204
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3363168935
Short name T734
Test name
Test status
Simulation time 88579387430 ps
CPU time 183.05 seconds
Started Jul 06 05:58:53 PM PDT 24
Finished Jul 06 06:01:56 PM PDT 24
Peak memory 200024 kb
Host smart-c206ded7-1b60-4478-99e1-ef655c2f56f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363168935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3363168935
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1907208607
Short name T16
Test name
Test status
Simulation time 6778034593 ps
CPU time 1.19 seconds
Started Jul 06 05:58:50 PM PDT 24
Finished Jul 06 05:58:52 PM PDT 24
Peak memory 196064 kb
Host smart-5c339701-edd9-4c54-9739-305141e04832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907208607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1907208607
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3894717713
Short name T1116
Test name
Test status
Simulation time 737528068 ps
CPU time 1.81 seconds
Started Jul 06 05:58:46 PM PDT 24
Finished Jul 06 05:58:49 PM PDT 24
Peak memory 199548 kb
Host smart-cf92ffb0-8fc0-4e93-98ad-295a334e39f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894717713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3894717713
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.378492624
Short name T295
Test name
Test status
Simulation time 509911984959 ps
CPU time 213.6 seconds
Started Jul 06 05:58:50 PM PDT 24
Finished Jul 06 06:02:24 PM PDT 24
Peak memory 216544 kb
Host smart-2f0420ba-f6ee-4e40-a62c-6270e8573778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378492624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.378492624
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3837116577
Short name T595
Test name
Test status
Simulation time 53489480399 ps
CPU time 162.83 seconds
Started Jul 06 05:58:55 PM PDT 24
Finished Jul 06 06:01:38 PM PDT 24
Peak memory 216524 kb
Host smart-8bb38600-9fb8-4de2-a4ac-3f7f529ae797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837116577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3837116577
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3631255500
Short name T389
Test name
Test status
Simulation time 840800113 ps
CPU time 3.72 seconds
Started Jul 06 05:58:55 PM PDT 24
Finished Jul 06 05:58:59 PM PDT 24
Peak memory 198448 kb
Host smart-abc0d499-bfea-46c6-9f66-7a594f1be769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631255500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3631255500
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2129443001
Short name T420
Test name
Test status
Simulation time 36132769435 ps
CPU time 60.4 seconds
Started Jul 06 05:58:47 PM PDT 24
Finished Jul 06 05:59:47 PM PDT 24
Peak memory 199892 kb
Host smart-acaf9535-c518-4411-89b3-785242d84daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129443001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2129443001
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1355880772
Short name T542
Test name
Test status
Simulation time 47150289726 ps
CPU time 74.84 seconds
Started Jul 06 06:02:31 PM PDT 24
Finished Jul 06 06:03:46 PM PDT 24
Peak memory 199992 kb
Host smart-d510fd57-2393-46e6-9605-abd4c71435ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355880772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1355880772
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2192051201
Short name T1160
Test name
Test status
Simulation time 37670584761 ps
CPU time 15.49 seconds
Started Jul 06 06:02:31 PM PDT 24
Finished Jul 06 06:02:46 PM PDT 24
Peak memory 199980 kb
Host smart-8657ee6f-ab24-4473-8d48-559dc5115da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192051201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2192051201
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2044907429
Short name T272
Test name
Test status
Simulation time 105568218562 ps
CPU time 45.92 seconds
Started Jul 06 06:02:30 PM PDT 24
Finished Jul 06 06:03:17 PM PDT 24
Peak memory 199972 kb
Host smart-c256948c-5076-4221-9d59-cebc0eb2a330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044907429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2044907429
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.113472778
Short name T223
Test name
Test status
Simulation time 116035865208 ps
CPU time 103.43 seconds
Started Jul 06 06:02:30 PM PDT 24
Finished Jul 06 06:04:13 PM PDT 24
Peak memory 199964 kb
Host smart-9a87c0a8-e38a-4827-a562-72372bf40f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113472778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.113472778
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1584101730
Short name T535
Test name
Test status
Simulation time 13647075379 ps
CPU time 20.69 seconds
Started Jul 06 06:02:33 PM PDT 24
Finished Jul 06 06:02:54 PM PDT 24
Peak memory 199628 kb
Host smart-6343cbdd-2b18-4bd7-9ed8-ad8dd2a9b43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584101730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1584101730
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2548692707
Short name T968
Test name
Test status
Simulation time 3516447287 ps
CPU time 3.65 seconds
Started Jul 06 06:02:31 PM PDT 24
Finished Jul 06 06:02:35 PM PDT 24
Peak memory 199964 kb
Host smart-8e0f47a0-5ef5-4338-a1d2-90c7f3f48b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548692707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2548692707
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1003081003
Short name T913
Test name
Test status
Simulation time 68907077639 ps
CPU time 52.2 seconds
Started Jul 06 06:02:34 PM PDT 24
Finished Jul 06 06:03:26 PM PDT 24
Peak memory 199860 kb
Host smart-8ebe30e5-afe4-4c1c-81b8-6e465221ecc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003081003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1003081003
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2520530285
Short name T614
Test name
Test status
Simulation time 19404999096 ps
CPU time 37.44 seconds
Started Jul 06 06:02:35 PM PDT 24
Finished Jul 06 06:03:13 PM PDT 24
Peak memory 199928 kb
Host smart-5625027b-d92c-4031-b40d-695a2518453e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520530285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2520530285
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.770344503
Short name T812
Test name
Test status
Simulation time 60659018392 ps
CPU time 8.04 seconds
Started Jul 06 06:02:31 PM PDT 24
Finished Jul 06 06:02:39 PM PDT 24
Peak memory 199992 kb
Host smart-dba59ada-b312-4a99-b3cf-f70712a49b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770344503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.770344503
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3278553960
Short name T654
Test name
Test status
Simulation time 20336871 ps
CPU time 0.58 seconds
Started Jul 06 05:58:56 PM PDT 24
Finished Jul 06 05:58:57 PM PDT 24
Peak memory 195568 kb
Host smart-b30bc087-ad5f-4967-a8d2-9603d95e42bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278553960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3278553960
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2240447520
Short name T917
Test name
Test status
Simulation time 56860672072 ps
CPU time 65.1 seconds
Started Jul 06 05:58:50 PM PDT 24
Finished Jul 06 05:59:56 PM PDT 24
Peak memory 199956 kb
Host smart-e715bdb9-87e9-4df9-84d9-b580ef292a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240447520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2240447520
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3331760883
Short name T627
Test name
Test status
Simulation time 154949895333 ps
CPU time 64.12 seconds
Started Jul 06 05:58:50 PM PDT 24
Finished Jul 06 05:59:55 PM PDT 24
Peak memory 199852 kb
Host smart-0d97a3f6-7d31-43bc-8edd-cf8216c4f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331760883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3331760883
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3126117810
Short name T280
Test name
Test status
Simulation time 278860902926 ps
CPU time 383.33 seconds
Started Jul 06 05:58:50 PM PDT 24
Finished Jul 06 06:05:13 PM PDT 24
Peak memory 199948 kb
Host smart-d787e6de-f792-4f7d-ae14-2c4d15df86b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126117810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3126117810
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.193432753
Short name T885
Test name
Test status
Simulation time 31880781351 ps
CPU time 22.44 seconds
Started Jul 06 05:58:50 PM PDT 24
Finished Jul 06 05:59:13 PM PDT 24
Peak memory 199328 kb
Host smart-3c7ec775-63d0-410e-8751-60f0dab49249
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193432753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.193432753
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2166555256
Short name T984
Test name
Test status
Simulation time 169384049289 ps
CPU time 511.87 seconds
Started Jul 06 05:58:57 PM PDT 24
Finished Jul 06 06:07:29 PM PDT 24
Peak memory 199880 kb
Host smart-bddf3af0-4ec4-40a3-ad09-16bca2990f10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166555256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2166555256
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3695414788
Short name T1069
Test name
Test status
Simulation time 4236119302 ps
CPU time 10.43 seconds
Started Jul 06 05:58:56 PM PDT 24
Finished Jul 06 05:59:07 PM PDT 24
Peak memory 198864 kb
Host smart-4204ee01-474b-4623-ae8f-8e91354bd2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695414788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3695414788
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1651323838
Short name T303
Test name
Test status
Simulation time 125421862940 ps
CPU time 53 seconds
Started Jul 06 05:58:51 PM PDT 24
Finished Jul 06 05:59:44 PM PDT 24
Peak memory 208316 kb
Host smart-5c39dc68-6031-4a7c-9109-9ee507243de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651323838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1651323838
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.4077235070
Short name T326
Test name
Test status
Simulation time 22188462360 ps
CPU time 944.27 seconds
Started Jul 06 05:58:56 PM PDT 24
Finished Jul 06 06:14:40 PM PDT 24
Peak memory 199856 kb
Host smart-890f4144-2044-4578-bb12-f4f88f4e592a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077235070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.4077235070
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.680253252
Short name T683
Test name
Test status
Simulation time 2013034319 ps
CPU time 6.73 seconds
Started Jul 06 05:58:52 PM PDT 24
Finished Jul 06 05:58:59 PM PDT 24
Peak memory 198044 kb
Host smart-2afc4d2e-6433-4b6d-898b-db6211deb950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=680253252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.680253252
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3012534827
Short name T613
Test name
Test status
Simulation time 27707206117 ps
CPU time 50.12 seconds
Started Jul 06 05:58:57 PM PDT 24
Finished Jul 06 05:59:47 PM PDT 24
Peak memory 199952 kb
Host smart-c8d9bf73-9102-45c5-8c36-2109c1185849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012534827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3012534827
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2119953959
Short name T1083
Test name
Test status
Simulation time 1453786583 ps
CPU time 2.9 seconds
Started Jul 06 05:58:59 PM PDT 24
Finished Jul 06 05:59:03 PM PDT 24
Peak memory 195432 kb
Host smart-e234dcbe-d918-4e54-b06d-48338e4f6c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119953959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2119953959
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3727147632
Short name T371
Test name
Test status
Simulation time 509976971 ps
CPU time 1.86 seconds
Started Jul 06 05:58:50 PM PDT 24
Finished Jul 06 05:58:52 PM PDT 24
Peak memory 198840 kb
Host smart-e37bd7cd-642a-4933-aa52-006145861b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727147632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3727147632
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2410708969
Short name T122
Test name
Test status
Simulation time 5029823636 ps
CPU time 8.73 seconds
Started Jul 06 05:58:59 PM PDT 24
Finished Jul 06 05:59:09 PM PDT 24
Peak memory 199924 kb
Host smart-f65c005c-248a-4ce4-a292-a4eb75ac1d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410708969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2410708969
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1537197176
Short name T564
Test name
Test status
Simulation time 52790606434 ps
CPU time 466.07 seconds
Started Jul 06 05:58:59 PM PDT 24
Finished Jul 06 06:06:45 PM PDT 24
Peak memory 215800 kb
Host smart-710333e2-1c38-432c-9b8d-762d87a00532
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537197176 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1537197176
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2522169959
Short name T620
Test name
Test status
Simulation time 1056352742 ps
CPU time 2.59 seconds
Started Jul 06 05:59:01 PM PDT 24
Finished Jul 06 05:59:04 PM PDT 24
Peak memory 198484 kb
Host smart-21e5c135-3518-4f7e-a2a0-33d38dcfba43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522169959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2522169959
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3455065131
Short name T275
Test name
Test status
Simulation time 82747689990 ps
CPU time 170.94 seconds
Started Jul 06 05:58:52 PM PDT 24
Finished Jul 06 06:01:44 PM PDT 24
Peak memory 199996 kb
Host smart-d53ef41d-1b4a-46b8-813e-f40a85c8166b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455065131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3455065131
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1470034299
Short name T159
Test name
Test status
Simulation time 98779139617 ps
CPU time 45.65 seconds
Started Jul 06 06:02:31 PM PDT 24
Finished Jul 06 06:03:17 PM PDT 24
Peak memory 200004 kb
Host smart-2f3a8b4f-9320-4365-9e73-e8d803076a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470034299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1470034299
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1072796749
Short name T954
Test name
Test status
Simulation time 16805820147 ps
CPU time 26.96 seconds
Started Jul 06 06:02:33 PM PDT 24
Finished Jul 06 06:03:01 PM PDT 24
Peak memory 199988 kb
Host smart-79796627-3514-4e49-953f-e3a2fb00e745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072796749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1072796749
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1402493361
Short name T579
Test name
Test status
Simulation time 79014367564 ps
CPU time 42.58 seconds
Started Jul 06 06:02:37 PM PDT 24
Finished Jul 06 06:03:19 PM PDT 24
Peak memory 199828 kb
Host smart-77427953-6bd4-49fd-be4e-ed9b5d47cc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402493361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1402493361
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2839636224
Short name T1169
Test name
Test status
Simulation time 47595723634 ps
CPU time 49.61 seconds
Started Jul 06 06:02:35 PM PDT 24
Finished Jul 06 06:03:25 PM PDT 24
Peak memory 199976 kb
Host smart-9cd6bfd2-579d-49f1-a45e-623d4afa7b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839636224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2839636224
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3283921599
Short name T349
Test name
Test status
Simulation time 29805693602 ps
CPU time 13.49 seconds
Started Jul 06 06:02:36 PM PDT 24
Finished Jul 06 06:02:49 PM PDT 24
Peak memory 199980 kb
Host smart-88fff811-a4ea-4e95-abbc-1d64559be6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283921599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3283921599
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3333242479
Short name T40
Test name
Test status
Simulation time 73213109979 ps
CPU time 119.99 seconds
Started Jul 06 06:02:36 PM PDT 24
Finished Jul 06 06:04:37 PM PDT 24
Peak memory 199940 kb
Host smart-bc97a87e-ecfc-4ef5-88a4-ce59eb372faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333242479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3333242479
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1458584459
Short name T662
Test name
Test status
Simulation time 128097210107 ps
CPU time 338.85 seconds
Started Jul 06 06:02:36 PM PDT 24
Finished Jul 06 06:08:15 PM PDT 24
Peak memory 199924 kb
Host smart-34d0532a-d034-4d7a-a0d0-497679cb9a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458584459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1458584459
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.217754938
Short name T1066
Test name
Test status
Simulation time 93943952464 ps
CPU time 365.91 seconds
Started Jul 06 06:02:37 PM PDT 24
Finished Jul 06 06:08:43 PM PDT 24
Peak memory 199904 kb
Host smart-fd57da10-c52b-4fb4-a188-722f45b17951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217754938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.217754938
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1332997724
Short name T759
Test name
Test status
Simulation time 10990732 ps
CPU time 0.58 seconds
Started Jul 06 05:57:03 PM PDT 24
Finished Jul 06 05:57:04 PM PDT 24
Peak memory 194212 kb
Host smart-41ffe218-4d69-41d8-a126-6529fc746c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332997724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1332997724
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2398420248
Short name T462
Test name
Test status
Simulation time 17791830549 ps
CPU time 29.87 seconds
Started Jul 06 05:56:52 PM PDT 24
Finished Jul 06 05:57:22 PM PDT 24
Peak memory 199952 kb
Host smart-90a7bf1d-afe7-4765-91aa-d6f0500138dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398420248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2398420248
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2817015064
Short name T1100
Test name
Test status
Simulation time 97612040854 ps
CPU time 146.11 seconds
Started Jul 06 05:56:51 PM PDT 24
Finished Jul 06 05:59:17 PM PDT 24
Peak memory 199920 kb
Host smart-8dd1f9d8-7afb-4916-8ba1-a099a487c3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817015064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2817015064
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2524608794
Short name T205
Test name
Test status
Simulation time 145285194355 ps
CPU time 237.81 seconds
Started Jul 06 05:57:00 PM PDT 24
Finished Jul 06 06:00:58 PM PDT 24
Peak memory 199912 kb
Host smart-79e39a0c-d26b-48b4-ab6e-befa25621d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524608794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2524608794
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3014497390
Short name T1017
Test name
Test status
Simulation time 19237682115 ps
CPU time 17.27 seconds
Started Jul 06 05:56:56 PM PDT 24
Finished Jul 06 05:57:14 PM PDT 24
Peak memory 197632 kb
Host smart-8db5d8fa-f9ec-4ee5-b9b0-6c8387c10c97
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014497390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3014497390
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.705056123
Short name T946
Test name
Test status
Simulation time 124859162042 ps
CPU time 687.75 seconds
Started Jul 06 05:56:55 PM PDT 24
Finished Jul 06 06:08:23 PM PDT 24
Peak memory 199860 kb
Host smart-0326d93d-fd77-45ad-a8e8-fca4bf05e5ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705056123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.705056123
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3832059666
Short name T1034
Test name
Test status
Simulation time 6043178038 ps
CPU time 9.14 seconds
Started Jul 06 05:56:57 PM PDT 24
Finished Jul 06 05:57:06 PM PDT 24
Peak memory 199284 kb
Host smart-d07a1e24-b35c-4641-bfa4-9d9378f81975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832059666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3832059666
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2120747175
Short name T1170
Test name
Test status
Simulation time 117454901089 ps
CPU time 111.27 seconds
Started Jul 06 05:56:55 PM PDT 24
Finished Jul 06 05:58:47 PM PDT 24
Peak memory 200140 kb
Host smart-f97dd484-d4ba-44ff-9efc-c0f2bde77008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120747175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2120747175
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.758736620
Short name T491
Test name
Test status
Simulation time 9674840627 ps
CPU time 529.88 seconds
Started Jul 06 05:56:56 PM PDT 24
Finished Jul 06 06:05:46 PM PDT 24
Peak memory 199936 kb
Host smart-41a065c9-17ea-4497-9990-d0bcdced3814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758736620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.758736620
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.170352425
Short name T756
Test name
Test status
Simulation time 5199036322 ps
CPU time 11.44 seconds
Started Jul 06 05:56:56 PM PDT 24
Finished Jul 06 05:57:08 PM PDT 24
Peak memory 197896 kb
Host smart-5a466bb5-fb1f-4fe2-936e-fc596e7bc807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170352425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.170352425
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1658894844
Short name T941
Test name
Test status
Simulation time 14060610466 ps
CPU time 12.63 seconds
Started Jul 06 05:56:57 PM PDT 24
Finished Jul 06 05:57:10 PM PDT 24
Peak memory 199912 kb
Host smart-dce5f31b-7039-44a2-a621-36da08bde317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658894844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1658894844
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1315895552
Short name T418
Test name
Test status
Simulation time 46050250469 ps
CPU time 16.71 seconds
Started Jul 06 05:56:55 PM PDT 24
Finished Jul 06 05:57:12 PM PDT 24
Peak memory 195988 kb
Host smart-f62a65ba-ffd2-4161-b18a-dd2f9ddd8bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315895552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1315895552
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2198346620
Short name T22
Test name
Test status
Simulation time 32624046 ps
CPU time 0.78 seconds
Started Jul 06 05:56:57 PM PDT 24
Finished Jul 06 05:56:58 PM PDT 24
Peak memory 218344 kb
Host smart-bec6f2d1-c00d-40b4-a064-1d8c2e2c53b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198346620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2198346620
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2231519617
Short name T34
Test name
Test status
Simulation time 633062502 ps
CPU time 2.03 seconds
Started Jul 06 05:56:53 PM PDT 24
Finished Jul 06 05:56:55 PM PDT 24
Peak memory 199620 kb
Host smart-ad41f937-7c89-4fd6-b19e-8c4e95400825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231519617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2231519617
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1863998145
Short name T285
Test name
Test status
Simulation time 44510436698 ps
CPU time 85.7 seconds
Started Jul 06 05:56:55 PM PDT 24
Finished Jul 06 05:58:21 PM PDT 24
Peak memory 199956 kb
Host smart-c105d74c-e2c8-4f31-8603-7d82bd2bba73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863998145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1863998145
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.257523249
Short name T1167
Test name
Test status
Simulation time 1294774892983 ps
CPU time 867.53 seconds
Started Jul 06 05:56:56 PM PDT 24
Finished Jul 06 06:11:24 PM PDT 24
Peak memory 224948 kb
Host smart-35732443-7a43-4d14-b655-4365eecc1527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257523249 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.257523249
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2923475024
Short name T562
Test name
Test status
Simulation time 1295003400 ps
CPU time 2.66 seconds
Started Jul 06 05:57:00 PM PDT 24
Finished Jul 06 05:57:03 PM PDT 24
Peak memory 198500 kb
Host smart-200cfcd3-fde3-4205-8471-dce2fb2bd965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923475024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2923475024
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1587331099
Short name T311
Test name
Test status
Simulation time 76240969826 ps
CPU time 105.32 seconds
Started Jul 06 05:56:52 PM PDT 24
Finished Jul 06 05:58:38 PM PDT 24
Peak memory 199936 kb
Host smart-a686549c-6038-4a35-a1d3-f39607b3e502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587331099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1587331099
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.601319986
Short name T1132
Test name
Test status
Simulation time 39214526 ps
CPU time 0.55 seconds
Started Jul 06 05:58:59 PM PDT 24
Finished Jul 06 05:59:00 PM PDT 24
Peak memory 195248 kb
Host smart-d9629457-af26-487e-9407-474ec7e3f53e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601319986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.601319986
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.370601886
Short name T32
Test name
Test status
Simulation time 40254751283 ps
CPU time 67.18 seconds
Started Jul 06 05:59:01 PM PDT 24
Finished Jul 06 06:00:08 PM PDT 24
Peak memory 199904 kb
Host smart-65fca975-defe-4df3-b642-4ce32f72e968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370601886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.370601886
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.4133461008
Short name T706
Test name
Test status
Simulation time 87447954425 ps
CPU time 33.46 seconds
Started Jul 06 05:58:56 PM PDT 24
Finished Jul 06 05:59:30 PM PDT 24
Peak memory 199932 kb
Host smart-a7c6b2eb-3834-49aa-b0c6-61825e322fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133461008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4133461008
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3758405472
Short name T341
Test name
Test status
Simulation time 16322333533 ps
CPU time 23.03 seconds
Started Jul 06 05:58:57 PM PDT 24
Finished Jul 06 05:59:20 PM PDT 24
Peak memory 198832 kb
Host smart-b7626578-cc88-46be-894b-d883e8767178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758405472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3758405472
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2484905370
Short name T873
Test name
Test status
Simulation time 64633027324 ps
CPU time 30.33 seconds
Started Jul 06 05:58:58 PM PDT 24
Finished Jul 06 05:59:28 PM PDT 24
Peak memory 199944 kb
Host smart-0a21f417-492e-4aaf-bb79-942c65d9b5f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484905370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2484905370
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.354312568
Short name T515
Test name
Test status
Simulation time 136645181461 ps
CPU time 836.89 seconds
Started Jul 06 05:59:02 PM PDT 24
Finished Jul 06 06:12:59 PM PDT 24
Peak memory 199932 kb
Host smart-a9e77ea2-3cf1-4b34-827f-ed0c8a9472d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354312568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.354312568
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.766121583
Short name T689
Test name
Test status
Simulation time 3890535214 ps
CPU time 10.05 seconds
Started Jul 06 05:59:01 PM PDT 24
Finished Jul 06 05:59:12 PM PDT 24
Peak memory 199520 kb
Host smart-63a7253f-c3e6-4612-bbcc-f1910b031e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766121583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.766121583
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2734200665
Short name T309
Test name
Test status
Simulation time 68708796478 ps
CPU time 76.36 seconds
Started Jul 06 05:58:56 PM PDT 24
Finished Jul 06 06:00:13 PM PDT 24
Peak memory 200172 kb
Host smart-47fbe6da-554b-4ccf-b0dd-4db7b5e7bf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734200665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2734200665
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.4114071458
Short name T920
Test name
Test status
Simulation time 14027773685 ps
CPU time 532.95 seconds
Started Jul 06 05:59:01 PM PDT 24
Finished Jul 06 06:07:55 PM PDT 24
Peak memory 199952 kb
Host smart-3c2f0df2-4030-4bef-ba4d-059ff72a6cf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4114071458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.4114071458
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2772487477
Short name T1078
Test name
Test status
Simulation time 6717797957 ps
CPU time 32.25 seconds
Started Jul 06 05:59:00 PM PDT 24
Finished Jul 06 05:59:32 PM PDT 24
Peak memory 198824 kb
Host smart-fdad11be-aa67-4049-8844-a0a61f48963e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772487477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2772487477
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.404758702
Short name T151
Test name
Test status
Simulation time 120285132319 ps
CPU time 43.69 seconds
Started Jul 06 05:59:00 PM PDT 24
Finished Jul 06 05:59:44 PM PDT 24
Peak memory 200016 kb
Host smart-fabccb5e-208c-4b21-b709-f578c16dd164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404758702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.404758702
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.223741239
Short name T308
Test name
Test status
Simulation time 3606617253 ps
CPU time 2.16 seconds
Started Jul 06 05:59:03 PM PDT 24
Finished Jul 06 05:59:05 PM PDT 24
Peak memory 196068 kb
Host smart-542b4c94-0d61-4f35-be10-cd9367b5928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223741239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.223741239
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.4258436514
Short name T752
Test name
Test status
Simulation time 11596039854 ps
CPU time 17.14 seconds
Started Jul 06 05:58:57 PM PDT 24
Finished Jul 06 05:59:14 PM PDT 24
Peak memory 199896 kb
Host smart-7cbe4c89-e92c-41ed-bf3f-c9e7d6bd0e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258436514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.4258436514
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.217686941
Short name T1122
Test name
Test status
Simulation time 192483702036 ps
CPU time 92.71 seconds
Started Jul 06 05:58:59 PM PDT 24
Finished Jul 06 06:00:32 PM PDT 24
Peak memory 199908 kb
Host smart-e170730c-c86c-48a0-a0b1-c897ebccf7e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217686941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.217686941
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.453615971
Short name T828
Test name
Test status
Simulation time 47595721984 ps
CPU time 692.62 seconds
Started Jul 06 05:59:01 PM PDT 24
Finished Jul 06 06:10:34 PM PDT 24
Peak memory 224824 kb
Host smart-c307fb6e-9855-46e0-adfc-5a2837005331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453615971 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.453615971
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1443385580
Short name T1087
Test name
Test status
Simulation time 1840812527 ps
CPU time 1.77 seconds
Started Jul 06 05:59:00 PM PDT 24
Finished Jul 06 05:59:02 PM PDT 24
Peak memory 198492 kb
Host smart-db4d7958-8a56-43c6-af16-09792c7ffe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443385580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1443385580
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3110984677
Short name T332
Test name
Test status
Simulation time 82967861719 ps
CPU time 38.15 seconds
Started Jul 06 05:58:57 PM PDT 24
Finished Jul 06 05:59:36 PM PDT 24
Peak memory 199976 kb
Host smart-afef5b62-e607-4164-b021-0c0756643eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110984677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3110984677
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.154011280
Short name T617
Test name
Test status
Simulation time 26554699 ps
CPU time 0.54 seconds
Started Jul 06 05:59:07 PM PDT 24
Finished Jul 06 05:59:08 PM PDT 24
Peak memory 194292 kb
Host smart-e53de79d-142c-4c54-af6e-e514df91b986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154011280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.154011280
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1026054598
Short name T735
Test name
Test status
Simulation time 261934888648 ps
CPU time 100.44 seconds
Started Jul 06 05:58:59 PM PDT 24
Finished Jul 06 06:00:40 PM PDT 24
Peak memory 199976 kb
Host smart-3e034498-7053-4448-808f-b349a0fa1479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026054598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1026054598
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3126782460
Short name T181
Test name
Test status
Simulation time 77539630884 ps
CPU time 32.94 seconds
Started Jul 06 05:59:01 PM PDT 24
Finished Jul 06 05:59:34 PM PDT 24
Peak memory 199904 kb
Host smart-218d802b-6ce9-48e5-a62d-f75d786be923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126782460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3126782460
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1882966797
Short name T860
Test name
Test status
Simulation time 95647020226 ps
CPU time 165.98 seconds
Started Jul 06 05:59:01 PM PDT 24
Finished Jul 06 06:01:47 PM PDT 24
Peak memory 199984 kb
Host smart-dcbc159d-4a0f-490d-b553-a7bc28fa2c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882966797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1882966797
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.877839813
Short name T1046
Test name
Test status
Simulation time 8516798150 ps
CPU time 8.69 seconds
Started Jul 06 05:59:02 PM PDT 24
Finished Jul 06 05:59:11 PM PDT 24
Peak memory 200024 kb
Host smart-76b1fcea-ed6d-4cee-afbd-5fc649f23642
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877839813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.877839813
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2558020029
Short name T608
Test name
Test status
Simulation time 89889107759 ps
CPU time 264.6 seconds
Started Jul 06 05:59:05 PM PDT 24
Finished Jul 06 06:03:30 PM PDT 24
Peak memory 199996 kb
Host smart-944559f9-ef6d-4e57-9947-93f3e64dc6d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558020029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2558020029
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1603402014
Short name T551
Test name
Test status
Simulation time 8466901595 ps
CPU time 16.93 seconds
Started Jul 06 05:59:04 PM PDT 24
Finished Jul 06 05:59:21 PM PDT 24
Peak memory 199192 kb
Host smart-734c13ec-f2f3-47c1-bbb0-88daa9530ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603402014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1603402014
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.332956015
Short name T298
Test name
Test status
Simulation time 113851574714 ps
CPU time 196.36 seconds
Started Jul 06 05:58:59 PM PDT 24
Finished Jul 06 06:02:16 PM PDT 24
Peak memory 199768 kb
Host smart-24af25bd-035c-4948-8c26-ff49d0ff2cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332956015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.332956015
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2420095337
Short name T1114
Test name
Test status
Simulation time 6599238212 ps
CPU time 421.81 seconds
Started Jul 06 05:59:04 PM PDT 24
Finished Jul 06 06:06:06 PM PDT 24
Peak memory 199948 kb
Host smart-c3761006-3e67-4725-8e01-000c63932811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420095337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2420095337
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.315473647
Short name T13
Test name
Test status
Simulation time 3259828890 ps
CPU time 21.51 seconds
Started Jul 06 05:59:01 PM PDT 24
Finished Jul 06 05:59:23 PM PDT 24
Peak memory 198080 kb
Host smart-bb7d6909-9486-4fbf-a723-99db80e99a54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315473647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.315473647
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.807263088
Short name T351
Test name
Test status
Simulation time 5361908904 ps
CPU time 13.52 seconds
Started Jul 06 05:59:07 PM PDT 24
Finished Jul 06 05:59:20 PM PDT 24
Peak memory 199836 kb
Host smart-8a5515a0-cda5-4533-9d8f-ac43641adbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807263088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.807263088
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1915040970
Short name T764
Test name
Test status
Simulation time 1678565804 ps
CPU time 3.19 seconds
Started Jul 06 05:59:01 PM PDT 24
Finished Jul 06 05:59:04 PM PDT 24
Peak memory 195588 kb
Host smart-34f64a5a-5bbc-4c55-8fef-c2c2f3ee695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915040970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1915040970
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1941891755
Short name T410
Test name
Test status
Simulation time 720041551 ps
CPU time 1.69 seconds
Started Jul 06 05:59:00 PM PDT 24
Finished Jul 06 05:59:02 PM PDT 24
Peak memory 198544 kb
Host smart-fb30da73-2e86-44a9-8888-b19fafad7855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941891755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1941891755
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1759232123
Short name T676
Test name
Test status
Simulation time 45275251533 ps
CPU time 26.65 seconds
Started Jul 06 05:59:06 PM PDT 24
Finished Jul 06 05:59:33 PM PDT 24
Peak memory 199924 kb
Host smart-a4e592bb-cf29-4af8-b8c4-cefdf020949d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759232123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1759232123
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2875016576
Short name T176
Test name
Test status
Simulation time 365826827228 ps
CPU time 1465.69 seconds
Started Jul 06 05:59:05 PM PDT 24
Finished Jul 06 06:23:31 PM PDT 24
Peak memory 228476 kb
Host smart-4f1135c8-fca2-4a70-bcc4-acfc41e7f967
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875016576 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2875016576
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2942857176
Short name T428
Test name
Test status
Simulation time 1267740295 ps
CPU time 4.91 seconds
Started Jul 06 05:59:06 PM PDT 24
Finished Jul 06 05:59:11 PM PDT 24
Peak memory 198860 kb
Host smart-0522cf12-1280-41de-bad1-a8d94c8bd00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942857176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2942857176
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3117739347
Short name T441
Test name
Test status
Simulation time 13037291304 ps
CPU time 7.2 seconds
Started Jul 06 05:59:01 PM PDT 24
Finished Jul 06 05:59:09 PM PDT 24
Peak memory 199900 kb
Host smart-fc56444d-5afa-4b4f-8a20-6fe96ca10e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117739347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3117739347
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3160124817
Short name T810
Test name
Test status
Simulation time 11986351 ps
CPU time 0.57 seconds
Started Jul 06 05:59:17 PM PDT 24
Finished Jul 06 05:59:18 PM PDT 24
Peak memory 195600 kb
Host smart-dd54a32e-0f87-4d88-8aba-9ef16708b412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160124817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3160124817
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3194001427
Short name T1110
Test name
Test status
Simulation time 214587252564 ps
CPU time 98.32 seconds
Started Jul 06 05:59:05 PM PDT 24
Finished Jul 06 06:00:43 PM PDT 24
Peak memory 199980 kb
Host smart-8fcb5f9e-937f-491f-afb4-2ebcb0ed95ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194001427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3194001427
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.4090092807
Short name T545
Test name
Test status
Simulation time 192914528512 ps
CPU time 191.93 seconds
Started Jul 06 05:59:11 PM PDT 24
Finished Jul 06 06:02:24 PM PDT 24
Peak memory 199952 kb
Host smart-c4edfca2-25ad-48a9-8148-1024acde0dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090092807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4090092807
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2006137620
Short name T950
Test name
Test status
Simulation time 82349595002 ps
CPU time 39.36 seconds
Started Jul 06 05:59:12 PM PDT 24
Finished Jul 06 05:59:52 PM PDT 24
Peak memory 199900 kb
Host smart-bf9f9cc0-0231-4bd7-be63-589a158652bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006137620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2006137620
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3000997491
Short name T127
Test name
Test status
Simulation time 22414018630 ps
CPU time 15.92 seconds
Started Jul 06 05:59:11 PM PDT 24
Finished Jul 06 05:59:27 PM PDT 24
Peak memory 198648 kb
Host smart-6c09af93-4958-4908-917a-a2303cbff801
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000997491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3000997491
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2156925821
Short name T39
Test name
Test status
Simulation time 124476132206 ps
CPU time 225.49 seconds
Started Jul 06 05:59:12 PM PDT 24
Finished Jul 06 06:02:58 PM PDT 24
Peak memory 200012 kb
Host smart-17d31b74-9c0f-4634-816d-f6a59ac60f33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156925821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2156925821
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.657301542
Short name T967
Test name
Test status
Simulation time 6966284905 ps
CPU time 10.52 seconds
Started Jul 06 05:59:09 PM PDT 24
Finished Jul 06 05:59:20 PM PDT 24
Peak memory 199904 kb
Host smart-999d76b8-c17b-467f-abd6-af46681313d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657301542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.657301542
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1138773216
Short name T575
Test name
Test status
Simulation time 9464610925 ps
CPU time 14.51 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 05:59:35 PM PDT 24
Peak memory 194576 kb
Host smart-09d18c0b-86f4-48cd-aa6d-3c1678fe5cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138773216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1138773216
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.4255313115
Short name T570
Test name
Test status
Simulation time 15300565531 ps
CPU time 218.94 seconds
Started Jul 06 05:59:12 PM PDT 24
Finished Jul 06 06:02:51 PM PDT 24
Peak memory 199948 kb
Host smart-7d315888-91df-4a95-b544-8fc54d78bf47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4255313115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4255313115
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.311399285
Short name T1023
Test name
Test status
Simulation time 3284766527 ps
CPU time 22.69 seconds
Started Jul 06 05:59:11 PM PDT 24
Finished Jul 06 05:59:34 PM PDT 24
Peak memory 198256 kb
Host smart-e567134a-d73e-4b82-80be-9e2653cba2ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311399285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.311399285
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3781183111
Short name T172
Test name
Test status
Simulation time 187202213721 ps
CPU time 158.64 seconds
Started Jul 06 05:59:13 PM PDT 24
Finished Jul 06 06:01:52 PM PDT 24
Peak memory 199900 kb
Host smart-d6ea8215-3081-4245-8315-03062b05b69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781183111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3781183111
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3786640637
Short name T686
Test name
Test status
Simulation time 3546649197 ps
CPU time 3.33 seconds
Started Jul 06 05:59:10 PM PDT 24
Finished Jul 06 05:59:13 PM PDT 24
Peak memory 196480 kb
Host smart-8f968dae-98a1-4209-84fe-4372ff0f0b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786640637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3786640637
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.715706626
Short name T864
Test name
Test status
Simulation time 742462237 ps
CPU time 1.69 seconds
Started Jul 06 05:59:08 PM PDT 24
Finished Jul 06 05:59:10 PM PDT 24
Peak memory 198892 kb
Host smart-d319d57d-3713-4b69-b7ab-0e99033f4f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715706626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.715706626
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1527502442
Short name T1149
Test name
Test status
Simulation time 611599115285 ps
CPU time 1483.71 seconds
Started Jul 06 05:59:11 PM PDT 24
Finished Jul 06 06:23:55 PM PDT 24
Peak memory 208384 kb
Host smart-3f275ab2-bded-46cf-af18-ac5435d14c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527502442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1527502442
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3016549283
Short name T898
Test name
Test status
Simulation time 21528042851 ps
CPU time 682.34 seconds
Started Jul 06 05:59:11 PM PDT 24
Finished Jul 06 06:10:34 PM PDT 24
Peak memory 216284 kb
Host smart-2d9dd837-ade6-4502-b274-6827476f4578
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016549283 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3016549283
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.4268538446
Short name T738
Test name
Test status
Simulation time 910881822 ps
CPU time 1.22 seconds
Started Jul 06 05:59:11 PM PDT 24
Finished Jul 06 05:59:13 PM PDT 24
Peak memory 198708 kb
Host smart-fb8f27be-0953-444a-b653-0cc56f635092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268538446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4268538446
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1694100099
Short name T274
Test name
Test status
Simulation time 74067278882 ps
CPU time 109.16 seconds
Started Jul 06 05:59:08 PM PDT 24
Finished Jul 06 06:00:57 PM PDT 24
Peak memory 199996 kb
Host smart-6b1b5eb3-8205-4854-bf75-82824f1f6c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694100099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1694100099
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2176244123
Short name T1040
Test name
Test status
Simulation time 44375838 ps
CPU time 0.56 seconds
Started Jul 06 05:59:15 PM PDT 24
Finished Jul 06 05:59:16 PM PDT 24
Peak memory 195316 kb
Host smart-601a8235-7628-436d-b51b-b6176d4d25de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176244123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2176244123
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.976527806
Short name T805
Test name
Test status
Simulation time 19884828549 ps
CPU time 31.38 seconds
Started Jul 06 05:59:15 PM PDT 24
Finished Jul 06 05:59:47 PM PDT 24
Peak memory 200020 kb
Host smart-e3a53f8b-3ebf-4c75-bf2c-3f07b47d8b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976527806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.976527806
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3623255177
Short name T947
Test name
Test status
Simulation time 21617061553 ps
CPU time 35.54 seconds
Started Jul 06 05:59:15 PM PDT 24
Finished Jul 06 05:59:51 PM PDT 24
Peak memory 200008 kb
Host smart-4ed8333b-fe9d-47c5-bc53-27b701b84cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623255177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3623255177
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.159081788
Short name T1178
Test name
Test status
Simulation time 22408697069 ps
CPU time 39.12 seconds
Started Jul 06 05:59:18 PM PDT 24
Finished Jul 06 05:59:57 PM PDT 24
Peak memory 199992 kb
Host smart-a4ef67ac-9fcf-4343-a419-221874a81280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159081788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.159081788
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3111224318
Short name T482
Test name
Test status
Simulation time 58199604538 ps
CPU time 43.11 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 06:00:03 PM PDT 24
Peak memory 199964 kb
Host smart-fc09f5b7-03ff-458f-84cf-7b334ac96e9c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111224318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3111224318
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3133504995
Short name T407
Test name
Test status
Simulation time 262444855716 ps
CPU time 293.04 seconds
Started Jul 06 05:59:15 PM PDT 24
Finished Jul 06 06:04:08 PM PDT 24
Peak memory 199980 kb
Host smart-bda01065-2dc4-40a2-85c0-d03bd8054d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133504995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3133504995
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.923399842
Short name T655
Test name
Test status
Simulation time 2555392424 ps
CPU time 3.12 seconds
Started Jul 06 05:59:17 PM PDT 24
Finished Jul 06 05:59:20 PM PDT 24
Peak memory 198868 kb
Host smart-7bdf252e-85a0-45ad-ae0c-5eaff9f44d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923399842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.923399842
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3811712579
Short name T330
Test name
Test status
Simulation time 91984096391 ps
CPU time 34.09 seconds
Started Jul 06 06:00:15 PM PDT 24
Finished Jul 06 06:00:49 PM PDT 24
Peak memory 200124 kb
Host smart-72e66654-9833-44ac-8297-a020c8c5481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811712579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3811712579
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2710162065
Short name T754
Test name
Test status
Simulation time 24368564030 ps
CPU time 1379.31 seconds
Started Jul 06 05:59:14 PM PDT 24
Finished Jul 06 06:22:14 PM PDT 24
Peak memory 199864 kb
Host smart-7a9b23cc-587f-4c76-a787-09390591b8c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2710162065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2710162065
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.767695165
Short name T987
Test name
Test status
Simulation time 5895119315 ps
CPU time 13.67 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 05:59:34 PM PDT 24
Peak memory 198808 kb
Host smart-c251a2ca-50bf-4ff8-b40d-032a3c57b01b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767695165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.767695165
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3491633326
Short name T942
Test name
Test status
Simulation time 111505183241 ps
CPU time 170.13 seconds
Started Jul 06 05:59:17 PM PDT 24
Finished Jul 06 06:02:07 PM PDT 24
Peak memory 199960 kb
Host smart-f47355d0-be8c-4f85-b63c-70b661b875e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491633326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3491633326
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3332819253
Short name T320
Test name
Test status
Simulation time 5041782774 ps
CPU time 0.98 seconds
Started Jul 06 05:59:16 PM PDT 24
Finished Jul 06 05:59:17 PM PDT 24
Peak memory 196248 kb
Host smart-84e16ad3-d007-43b2-9529-f27829f4dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332819253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3332819253
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1421444100
Short name T463
Test name
Test status
Simulation time 678940641 ps
CPU time 2.17 seconds
Started Jul 06 05:59:10 PM PDT 24
Finished Jul 06 05:59:13 PM PDT 24
Peak memory 199276 kb
Host smart-3a059c91-cf88-4079-a741-78f8376de689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421444100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1421444100
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.473698860
Short name T266
Test name
Test status
Simulation time 224592296743 ps
CPU time 1163.04 seconds
Started Jul 06 05:59:16 PM PDT 24
Finished Jul 06 06:18:39 PM PDT 24
Peak memory 208380 kb
Host smart-21967ecd-fc44-494b-8cc6-d63536d08844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473698860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.473698860
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.840538301
Short name T799
Test name
Test status
Simulation time 239445857412 ps
CPU time 742.07 seconds
Started Jul 06 05:59:15 PM PDT 24
Finished Jul 06 06:11:38 PM PDT 24
Peak memory 230736 kb
Host smart-e0637a60-2bbf-4dca-bd01-01b8fbf75971
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840538301 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.840538301
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2447184686
Short name T757
Test name
Test status
Simulation time 7069358429 ps
CPU time 13.93 seconds
Started Jul 06 05:59:14 PM PDT 24
Finished Jul 06 05:59:28 PM PDT 24
Peak memory 199808 kb
Host smart-4ca325bb-b7fc-406c-a3df-072096701120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447184686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2447184686
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3819315858
Short name T282
Test name
Test status
Simulation time 428199905625 ps
CPU time 49.23 seconds
Started Jul 06 05:59:15 PM PDT 24
Finished Jul 06 06:00:04 PM PDT 24
Peak memory 199924 kb
Host smart-f43e5037-ab21-4100-b8e2-0256331bc2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819315858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3819315858
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1697934040
Short name T619
Test name
Test status
Simulation time 12553655 ps
CPU time 0.56 seconds
Started Jul 06 05:59:21 PM PDT 24
Finished Jul 06 05:59:22 PM PDT 24
Peak memory 195328 kb
Host smart-22d158c5-1303-446b-a23a-d5be2a63bf6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697934040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1697934040
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1539617387
Short name T1044
Test name
Test status
Simulation time 160445710511 ps
CPU time 20.78 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 05:59:41 PM PDT 24
Peak memory 199996 kb
Host smart-953a49cc-df4e-4113-b9fd-83a04f421122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539617387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1539617387
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.807094454
Short name T138
Test name
Test status
Simulation time 26511016808 ps
CPU time 43.95 seconds
Started Jul 06 05:59:18 PM PDT 24
Finished Jul 06 06:00:02 PM PDT 24
Peak memory 199956 kb
Host smart-c83dc2a6-0a53-4ea5-bfeb-1722207396e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807094454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.807094454
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3192001852
Short name T681
Test name
Test status
Simulation time 46456505992 ps
CPU time 81.15 seconds
Started Jul 06 05:59:18 PM PDT 24
Finished Jul 06 06:00:39 PM PDT 24
Peak memory 199924 kb
Host smart-1c1e9b1f-ff4d-439a-a1dc-f8b64b42a346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192001852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3192001852
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2169616717
Short name T910
Test name
Test status
Simulation time 209088126305 ps
CPU time 339.62 seconds
Started Jul 06 05:59:21 PM PDT 24
Finished Jul 06 06:05:01 PM PDT 24
Peak memory 199964 kb
Host smart-1f81c5e6-f9e0-4e9b-b6a7-23af0904accc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169616717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2169616717
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1188895142
Short name T1086
Test name
Test status
Simulation time 192132987283 ps
CPU time 417.58 seconds
Started Jul 06 05:59:19 PM PDT 24
Finished Jul 06 06:06:17 PM PDT 24
Peak memory 199992 kb
Host smart-4fdb3919-e5cb-4c02-8abb-6477879c43a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188895142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1188895142
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4045291463
Short name T352
Test name
Test status
Simulation time 2181694246 ps
CPU time 4.04 seconds
Started Jul 06 05:59:21 PM PDT 24
Finished Jul 06 05:59:25 PM PDT 24
Peak memory 198688 kb
Host smart-b41ef36a-c472-4ded-bf60-daff9624b0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045291463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4045291463
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.144357391
Short name T829
Test name
Test status
Simulation time 150715198003 ps
CPU time 21.4 seconds
Started Jul 06 05:59:21 PM PDT 24
Finished Jul 06 05:59:43 PM PDT 24
Peak memory 199772 kb
Host smart-be0a05e4-0fd5-4e33-b0c5-1a113b910f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144357391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.144357391
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.116911920
Short name T862
Test name
Test status
Simulation time 27880034949 ps
CPU time 89.55 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 06:00:50 PM PDT 24
Peak memory 199984 kb
Host smart-b01a7fd4-cd91-4481-baec-208178987bad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116911920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.116911920
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2323144021
Short name T743
Test name
Test status
Simulation time 6164172380 ps
CPU time 47.31 seconds
Started Jul 06 05:59:22 PM PDT 24
Finished Jul 06 06:00:09 PM PDT 24
Peak memory 197956 kb
Host smart-c9b34fbf-6507-4a30-a957-b7d15332a1f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323144021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2323144021
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4086171583
Short name T847
Test name
Test status
Simulation time 233544827910 ps
CPU time 289.21 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 06:04:10 PM PDT 24
Peak memory 200012 kb
Host smart-862338f1-983c-40f4-b72a-d316aeb7924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086171583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4086171583
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2235344522
Short name T707
Test name
Test status
Simulation time 87505875023 ps
CPU time 27.33 seconds
Started Jul 06 05:59:19 PM PDT 24
Finished Jul 06 05:59:47 PM PDT 24
Peak memory 195760 kb
Host smart-0d41516e-979e-4f23-901b-7b74114e746b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235344522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2235344522
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1395965587
Short name T721
Test name
Test status
Simulation time 6090644971 ps
CPU time 21.64 seconds
Started Jul 06 05:59:14 PM PDT 24
Finished Jul 06 05:59:36 PM PDT 24
Peak memory 199892 kb
Host smart-b77e655c-dcd7-45b6-95fa-1352a3262fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395965587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1395965587
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3826911152
Short name T640
Test name
Test status
Simulation time 118802883738 ps
CPU time 71.37 seconds
Started Jul 06 05:59:22 PM PDT 24
Finished Jul 06 06:00:33 PM PDT 24
Peak memory 199924 kb
Host smart-9cd1647f-465b-4fc5-89c3-6a52c02af14e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826911152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3826911152
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1364941307
Short name T867
Test name
Test status
Simulation time 57038143173 ps
CPU time 1575.2 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 06:25:36 PM PDT 24
Peak memory 216464 kb
Host smart-38091f99-87ee-4d2c-9be1-0e496c8b6b0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364941307 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1364941307
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.946913411
Short name T715
Test name
Test status
Simulation time 1102394249 ps
CPU time 2.79 seconds
Started Jul 06 05:59:22 PM PDT 24
Finished Jul 06 05:59:25 PM PDT 24
Peak memory 199608 kb
Host smart-d759f0e2-3dba-4c70-9ee4-e80d23c0274e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946913411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.946913411
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1589522770
Short name T475
Test name
Test status
Simulation time 343795455587 ps
CPU time 50.41 seconds
Started Jul 06 05:59:15 PM PDT 24
Finished Jul 06 06:00:06 PM PDT 24
Peak memory 199900 kb
Host smart-f0fce539-2196-4787-bc35-5ee6060ae5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589522770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1589522770
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3991182016
Short name T711
Test name
Test status
Simulation time 32973824 ps
CPU time 0.56 seconds
Started Jul 06 05:59:25 PM PDT 24
Finished Jul 06 05:59:26 PM PDT 24
Peak memory 195264 kb
Host smart-3b6f2a6f-c9b8-4396-9c31-f7f6e6f25394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991182016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3991182016
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1558075787
Short name T886
Test name
Test status
Simulation time 54954214993 ps
CPU time 96.6 seconds
Started Jul 06 05:59:19 PM PDT 24
Finished Jul 06 06:00:56 PM PDT 24
Peak memory 200188 kb
Host smart-ff61e6ba-7432-482c-a1b2-7ad7c62bda94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558075787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1558075787
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2918676238
Short name T802
Test name
Test status
Simulation time 86643727742 ps
CPU time 13.95 seconds
Started Jul 06 05:59:19 PM PDT 24
Finished Jul 06 05:59:33 PM PDT 24
Peak memory 199944 kb
Host smart-adaef67e-729b-4faa-a908-13d7b264f90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918676238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2918676238
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2693810526
Short name T807
Test name
Test status
Simulation time 160431975730 ps
CPU time 142.09 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 06:01:42 PM PDT 24
Peak memory 199924 kb
Host smart-9d81ab7b-12bb-466f-be4b-dfa0004f1c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693810526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2693810526
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1825721043
Short name T961
Test name
Test status
Simulation time 28072934458 ps
CPU time 17.18 seconds
Started Jul 06 05:59:21 PM PDT 24
Finished Jul 06 05:59:39 PM PDT 24
Peak memory 199688 kb
Host smart-d6478ef4-0b80-4a23-8a0c-6f204a40feaa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825721043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1825721043
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1882082625
Short name T1112
Test name
Test status
Simulation time 169270285562 ps
CPU time 282.71 seconds
Started Jul 06 05:59:25 PM PDT 24
Finished Jul 06 06:04:08 PM PDT 24
Peak memory 199944 kb
Host smart-06ff72e0-ef75-451c-b1de-18c0e6406988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882082625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1882082625
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1173501958
Short name T14
Test name
Test status
Simulation time 5753217045 ps
CPU time 4.84 seconds
Started Jul 06 05:59:22 PM PDT 24
Finished Jul 06 05:59:27 PM PDT 24
Peak memory 199732 kb
Host smart-9318ae74-b223-407b-9ee0-b08415bf5c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173501958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1173501958
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1364329595
Short name T325
Test name
Test status
Simulation time 88579035368 ps
CPU time 161.78 seconds
Started Jul 06 05:59:21 PM PDT 24
Finished Jul 06 06:02:03 PM PDT 24
Peak memory 200096 kb
Host smart-6332b52d-0a60-4cd8-97d9-cdc45c0f7f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364329595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1364329595
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1416186967
Short name T603
Test name
Test status
Simulation time 2805626379 ps
CPU time 131.04 seconds
Started Jul 06 05:59:25 PM PDT 24
Finished Jul 06 06:01:37 PM PDT 24
Peak memory 199856 kb
Host smart-465b33e8-e79d-4403-bf33-433a5fb27ea5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416186967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1416186967
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1879130107
Short name T982
Test name
Test status
Simulation time 6559700017 ps
CPU time 60.53 seconds
Started Jul 06 05:59:21 PM PDT 24
Finished Jul 06 06:00:21 PM PDT 24
Peak memory 199200 kb
Host smart-fd571072-e23a-47ec-9626-09b109caae50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879130107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1879130107
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1460814078
Short name T158
Test name
Test status
Simulation time 268354915527 ps
CPU time 153.18 seconds
Started Jul 06 05:59:22 PM PDT 24
Finished Jul 06 06:01:55 PM PDT 24
Peak memory 199984 kb
Host smart-313391a3-2735-44f7-80d9-a636bdbbcb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460814078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1460814078
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.330718782
Short name T358
Test name
Test status
Simulation time 2673892822 ps
CPU time 2.74 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 05:59:23 PM PDT 24
Peak memory 195928 kb
Host smart-2e16c8a6-1f1a-4c05-a1df-c8306e1aaffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330718782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.330718782
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2165046460
Short name T1016
Test name
Test status
Simulation time 316470528 ps
CPU time 1.04 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 05:59:21 PM PDT 24
Peak memory 199052 kb
Host smart-a1f71b5f-6bdf-428b-b08c-ac2a1ce0a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165046460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2165046460
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2702048512
Short name T778
Test name
Test status
Simulation time 314142859880 ps
CPU time 220.52 seconds
Started Jul 06 05:59:26 PM PDT 24
Finished Jul 06 06:03:07 PM PDT 24
Peak memory 199884 kb
Host smart-31386ada-75f3-49b7-9f51-17186ddb8086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702048512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2702048512
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3104345494
Short name T970
Test name
Test status
Simulation time 119636746627 ps
CPU time 518.27 seconds
Started Jul 06 05:59:26 PM PDT 24
Finished Jul 06 06:08:05 PM PDT 24
Peak memory 212068 kb
Host smart-13cd4ede-3977-4285-80bb-1894de6e99ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104345494 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3104345494
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3309404341
Short name T953
Test name
Test status
Simulation time 7200591484 ps
CPU time 7.88 seconds
Started Jul 06 05:59:22 PM PDT 24
Finished Jul 06 05:59:30 PM PDT 24
Peak memory 199400 kb
Host smart-e2ca1ff0-4fee-464d-9106-fe94f0381540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309404341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3309404341
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2807730396
Short name T455
Test name
Test status
Simulation time 158443004062 ps
CPU time 60.26 seconds
Started Jul 06 05:59:20 PM PDT 24
Finished Jul 06 06:00:20 PM PDT 24
Peak memory 199916 kb
Host smart-b177c476-b6ed-44f6-9d3b-27c0da2da316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807730396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2807730396
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1150439681
Short name T379
Test name
Test status
Simulation time 39573819 ps
CPU time 0.55 seconds
Started Jul 06 05:59:32 PM PDT 24
Finished Jul 06 05:59:32 PM PDT 24
Peak memory 195620 kb
Host smart-cfe1b12e-87a0-49b8-a933-f8b091229418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150439681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1150439681
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2486567793
Short name T134
Test name
Test status
Simulation time 169660298973 ps
CPU time 37.49 seconds
Started Jul 06 05:59:26 PM PDT 24
Finished Jul 06 06:00:04 PM PDT 24
Peak memory 199924 kb
Host smart-75bee317-5b9c-4222-af3d-0becf007c862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486567793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2486567793
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.352462439
Short name T1032
Test name
Test status
Simulation time 79977171510 ps
CPU time 98.15 seconds
Started Jul 06 05:59:24 PM PDT 24
Finished Jul 06 06:01:02 PM PDT 24
Peak memory 199924 kb
Host smart-46b583b4-ba72-4f9f-ae39-50cecc5bd70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352462439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.352462439
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3821086224
Short name T1154
Test name
Test status
Simulation time 15060819497 ps
CPU time 16.32 seconds
Started Jul 06 05:59:25 PM PDT 24
Finished Jul 06 05:59:41 PM PDT 24
Peak memory 199960 kb
Host smart-756c54cb-ce77-439b-9105-3877f23766ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821086224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3821086224
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3456869378
Short name T973
Test name
Test status
Simulation time 103475132280 ps
CPU time 153.29 seconds
Started Jul 06 05:59:25 PM PDT 24
Finished Jul 06 06:01:58 PM PDT 24
Peak memory 199984 kb
Host smart-4e3eb7cc-5241-47fc-90ca-70d83ab3d344
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456869378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3456869378
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_loopback.805592608
Short name T390
Test name
Test status
Simulation time 4403816782 ps
CPU time 6.57 seconds
Started Jul 06 05:59:26 PM PDT 24
Finished Jul 06 05:59:33 PM PDT 24
Peak memory 199064 kb
Host smart-c90e1168-8644-4130-b1f1-dfc1fc1af817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805592608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.805592608
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1866084532
Short name T427
Test name
Test status
Simulation time 35200250845 ps
CPU time 14.36 seconds
Started Jul 06 05:59:26 PM PDT 24
Finished Jul 06 05:59:41 PM PDT 24
Peak memory 199840 kb
Host smart-30fe0a62-55d0-4f23-b082-69335e2d0651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866084532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1866084532
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.636657873
Short name T456
Test name
Test status
Simulation time 8313950969 ps
CPU time 40.32 seconds
Started Jul 06 05:59:25 PM PDT 24
Finished Jul 06 06:00:06 PM PDT 24
Peak memory 199932 kb
Host smart-86eb5e5c-ce98-4ce1-914e-9907bcb31712
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=636657873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.636657873
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2568960818
Short name T906
Test name
Test status
Simulation time 3173141002 ps
CPU time 22.47 seconds
Started Jul 06 05:59:25 PM PDT 24
Finished Jul 06 05:59:48 PM PDT 24
Peak memory 198308 kb
Host smart-488d59b1-612b-465b-8717-586314630ecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568960818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2568960818
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3842393906
Short name T1136
Test name
Test status
Simulation time 26998741974 ps
CPU time 47.25 seconds
Started Jul 06 05:59:27 PM PDT 24
Finished Jul 06 06:00:14 PM PDT 24
Peak memory 199908 kb
Host smart-4819836e-f796-4feb-b5e3-152a87553037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842393906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3842393906
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1408733503
Short name T642
Test name
Test status
Simulation time 3387145405 ps
CPU time 6.03 seconds
Started Jul 06 05:59:25 PM PDT 24
Finished Jul 06 05:59:31 PM PDT 24
Peak memory 195968 kb
Host smart-b06b3055-55f6-4feb-aa6f-f8ef830a99a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408733503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1408733503
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3643762504
Short name T566
Test name
Test status
Simulation time 266969020 ps
CPU time 1 seconds
Started Jul 06 05:59:27 PM PDT 24
Finished Jul 06 05:59:28 PM PDT 24
Peak memory 199848 kb
Host smart-f3fe9704-704e-42a0-96bd-e06de1c17ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643762504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3643762504
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1341661206
Short name T612
Test name
Test status
Simulation time 198318596946 ps
CPU time 1050.45 seconds
Started Jul 06 05:59:28 PM PDT 24
Finished Jul 06 06:16:58 PM PDT 24
Peak memory 199996 kb
Host smart-0d0d550c-db03-413b-b0f3-bf18191aed5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341661206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1341661206
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3246615094
Short name T481
Test name
Test status
Simulation time 917360382 ps
CPU time 2.79 seconds
Started Jul 06 05:59:25 PM PDT 24
Finished Jul 06 05:59:28 PM PDT 24
Peak memory 198740 kb
Host smart-863573bf-00e4-41c1-9689-65591c4df2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246615094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3246615094
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.183537197
Short name T787
Test name
Test status
Simulation time 23183844395 ps
CPU time 8.93 seconds
Started Jul 06 05:59:27 PM PDT 24
Finished Jul 06 05:59:36 PM PDT 24
Peak memory 199632 kb
Host smart-3863a7bf-7698-4b97-95c1-69b6e3a4bfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183537197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.183537197
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.4021705394
Short name T1146
Test name
Test status
Simulation time 14293143 ps
CPU time 0.55 seconds
Started Jul 06 05:59:36 PM PDT 24
Finished Jul 06 05:59:37 PM PDT 24
Peak memory 195332 kb
Host smart-0c9ae436-dd70-4e2f-b64c-1fecbe5cd64c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021705394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.4021705394
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.444231592
Short name T312
Test name
Test status
Simulation time 23612443756 ps
CPU time 44.77 seconds
Started Jul 06 05:59:30 PM PDT 24
Finished Jul 06 06:00:16 PM PDT 24
Peak memory 199944 kb
Host smart-4efcdede-6d72-4c61-9ef5-4548c1402999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444231592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.444231592
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2194457138
Short name T170
Test name
Test status
Simulation time 102111448287 ps
CPU time 148.96 seconds
Started Jul 06 05:59:33 PM PDT 24
Finished Jul 06 06:02:03 PM PDT 24
Peak memory 199888 kb
Host smart-456e4f34-a8a2-43a8-9c92-aac2e3b325f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194457138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2194457138
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.754571575
Short name T772
Test name
Test status
Simulation time 127619013794 ps
CPU time 98.22 seconds
Started Jul 06 05:59:30 PM PDT 24
Finished Jul 06 06:01:09 PM PDT 24
Peak memory 199888 kb
Host smart-d689ebf0-e4a8-49d5-a1d6-5368882b207b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754571575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.754571575
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.392043837
Short name T671
Test name
Test status
Simulation time 22478966921 ps
CPU time 16.94 seconds
Started Jul 06 05:59:35 PM PDT 24
Finished Jul 06 05:59:52 PM PDT 24
Peak memory 200020 kb
Host smart-8d414958-62b2-4165-8a4b-6b62f9c24804
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392043837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.392043837
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.419320724
Short name T747
Test name
Test status
Simulation time 198466492880 ps
CPU time 385.4 seconds
Started Jul 06 05:59:38 PM PDT 24
Finished Jul 06 06:06:03 PM PDT 24
Peak memory 199976 kb
Host smart-4b59c635-6fab-4a64-8d6e-abeb3e7c3fe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419320724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.419320724
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3770375320
Short name T514
Test name
Test status
Simulation time 3412101777 ps
CPU time 7.17 seconds
Started Jul 06 05:59:31 PM PDT 24
Finished Jul 06 05:59:38 PM PDT 24
Peak memory 199972 kb
Host smart-9b42be17-90a6-42b1-9917-4b03cc41aa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770375320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3770375320
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1771181956
Short name T83
Test name
Test status
Simulation time 83629977862 ps
CPU time 66.45 seconds
Started Jul 06 05:59:31 PM PDT 24
Finished Jul 06 06:00:38 PM PDT 24
Peak memory 200044 kb
Host smart-ca213a8a-b533-4328-991c-206f4a2be722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771181956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1771181956
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2981695231
Short name T47
Test name
Test status
Simulation time 12654991787 ps
CPU time 168.01 seconds
Started Jul 06 05:59:30 PM PDT 24
Finished Jul 06 06:02:19 PM PDT 24
Peak memory 200012 kb
Host smart-d0105537-5d33-40c1-8c64-50411cabfecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981695231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2981695231
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1954127997
Short name T965
Test name
Test status
Simulation time 6705049032 ps
CPU time 13.8 seconds
Started Jul 06 05:59:31 PM PDT 24
Finished Jul 06 05:59:46 PM PDT 24
Peak memory 197824 kb
Host smart-2fc04666-81c3-4ac2-80c4-a4c05a284094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954127997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1954127997
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2849148018
Short name T533
Test name
Test status
Simulation time 42998675644 ps
CPU time 38.96 seconds
Started Jul 06 05:59:33 PM PDT 24
Finished Jul 06 06:00:12 PM PDT 24
Peak memory 199940 kb
Host smart-4392538a-48fd-4202-b072-586f9f2eb59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849148018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2849148018
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.472872580
Short name T692
Test name
Test status
Simulation time 6782732777 ps
CPU time 11.54 seconds
Started Jul 06 05:59:30 PM PDT 24
Finished Jul 06 05:59:41 PM PDT 24
Peak memory 196444 kb
Host smart-bcba87cc-45b2-4277-9cb3-e3d729f20648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472872580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.472872580
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.973671049
Short name T290
Test name
Test status
Simulation time 663896471 ps
CPU time 2.33 seconds
Started Jul 06 05:59:29 PM PDT 24
Finished Jul 06 05:59:32 PM PDT 24
Peak memory 198852 kb
Host smart-c5369177-4dd9-4fe9-9c21-b1abd5c7fed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973671049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.973671049
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.4098514382
Short name T492
Test name
Test status
Simulation time 66410789079 ps
CPU time 128.39 seconds
Started Jul 06 05:59:36 PM PDT 24
Finished Jul 06 06:01:45 PM PDT 24
Peak memory 199840 kb
Host smart-77bf0010-3606-490a-ab04-05bd61278c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098514382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4098514382
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2792715550
Short name T824
Test name
Test status
Simulation time 896644276 ps
CPU time 2.79 seconds
Started Jul 06 05:59:31 PM PDT 24
Finished Jul 06 05:59:34 PM PDT 24
Peak memory 199664 kb
Host smart-429142a1-fb37-4ead-9736-6cd162342c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792715550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2792715550
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2396831205
Short name T271
Test name
Test status
Simulation time 60638768120 ps
CPU time 92.22 seconds
Started Jul 06 05:59:31 PM PDT 24
Finished Jul 06 06:01:04 PM PDT 24
Peak memory 199940 kb
Host smart-ee7747d8-30fc-4d21-b58a-c75b578ff99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396831205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2396831205
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.187999594
Short name T897
Test name
Test status
Simulation time 29974888 ps
CPU time 0.55 seconds
Started Jul 06 05:59:42 PM PDT 24
Finished Jul 06 05:59:42 PM PDT 24
Peak memory 195312 kb
Host smart-cf97ca4c-61c9-44a0-9d14-1858eeeb9b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187999594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.187999594
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2186257355
Short name T333
Test name
Test status
Simulation time 14952897523 ps
CPU time 29.38 seconds
Started Jul 06 05:59:37 PM PDT 24
Finished Jul 06 06:00:07 PM PDT 24
Peak memory 199920 kb
Host smart-af0f5a50-c302-4e74-afb9-6dbcfe642903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186257355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2186257355
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1455463835
Short name T57
Test name
Test status
Simulation time 30100449169 ps
CPU time 47.29 seconds
Started Jul 06 05:59:37 PM PDT 24
Finished Jul 06 06:00:25 PM PDT 24
Peak memory 199924 kb
Host smart-3cb6d717-cd8f-4291-be43-52259c69f432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455463835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1455463835
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3018620661
Short name T337
Test name
Test status
Simulation time 252030592762 ps
CPU time 392.69 seconds
Started Jul 06 05:59:38 PM PDT 24
Finished Jul 06 06:06:11 PM PDT 24
Peak memory 199992 kb
Host smart-703e66a6-a0e0-42f5-8857-c87b52116498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018620661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3018620661
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3557880013
Short name T630
Test name
Test status
Simulation time 37046522637 ps
CPU time 30.2 seconds
Started Jul 06 05:59:38 PM PDT 24
Finished Jul 06 06:00:08 PM PDT 24
Peak memory 199932 kb
Host smart-eb83a2ed-1831-4314-a850-6e8ed44d4843
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557880013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3557880013
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3411860957
Short name T391
Test name
Test status
Simulation time 152140055336 ps
CPU time 449.9 seconds
Started Jul 06 05:59:41 PM PDT 24
Finished Jul 06 06:07:12 PM PDT 24
Peak memory 199988 kb
Host smart-21e15b9f-3bcc-4856-ab70-2f53bf8f814a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411860957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3411860957
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1064692179
Short name T366
Test name
Test status
Simulation time 11186350655 ps
CPU time 8.58 seconds
Started Jul 06 05:59:43 PM PDT 24
Finished Jul 06 05:59:52 PM PDT 24
Peak memory 199868 kb
Host smart-8d659ae0-2a8c-42a2-98f2-5a7c06af41cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064692179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1064692179
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3320769482
Short name T269
Test name
Test status
Simulation time 32374411706 ps
CPU time 49.49 seconds
Started Jul 06 05:59:36 PM PDT 24
Finished Jul 06 06:00:26 PM PDT 24
Peak memory 199152 kb
Host smart-b805b61b-2562-4501-958e-03f440d45f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320769482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3320769482
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1339719998
Short name T1064
Test name
Test status
Simulation time 13848306177 ps
CPU time 181.95 seconds
Started Jul 06 05:59:42 PM PDT 24
Finished Jul 06 06:02:45 PM PDT 24
Peak memory 199956 kb
Host smart-bd939cb3-8a24-4a21-96ea-e3057a8d5d9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339719998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1339719998
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1345268450
Short name T1072
Test name
Test status
Simulation time 6518331078 ps
CPU time 35.02 seconds
Started Jul 06 05:59:38 PM PDT 24
Finished Jul 06 06:00:13 PM PDT 24
Peak memory 198800 kb
Host smart-cb1c9ed5-2133-4ced-8a4d-bc0b69fdf26f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345268450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1345268450
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.770444473
Short name T952
Test name
Test status
Simulation time 12446734725 ps
CPU time 33.95 seconds
Started Jul 06 05:59:37 PM PDT 24
Finished Jul 06 06:00:12 PM PDT 24
Peak memory 199888 kb
Host smart-ccf5ae91-9676-4c97-b57f-bdc7383443c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770444473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.770444473
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3383217118
Short name T832
Test name
Test status
Simulation time 4480408730 ps
CPU time 2.51 seconds
Started Jul 06 05:59:37 PM PDT 24
Finished Jul 06 05:59:40 PM PDT 24
Peak memory 195988 kb
Host smart-c08ff6e5-ddcf-4214-981b-92e8ff5a06cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383217118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3383217118
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.914036645
Short name T386
Test name
Test status
Simulation time 647300641 ps
CPU time 2.86 seconds
Started Jul 06 05:59:40 PM PDT 24
Finished Jul 06 05:59:43 PM PDT 24
Peak memory 198864 kb
Host smart-a882dcbf-b442-4e5c-94b9-bed203b13181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914036645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.914036645
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3604577309
Short name T628
Test name
Test status
Simulation time 384127408024 ps
CPU time 370.83 seconds
Started Jul 06 05:59:43 PM PDT 24
Finished Jul 06 06:05:54 PM PDT 24
Peak memory 208368 kb
Host smart-eaad0f4a-a65a-4521-bc8f-89bd342594cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604577309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3604577309
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.983816362
Short name T751
Test name
Test status
Simulation time 1569922995118 ps
CPU time 1119.21 seconds
Started Jul 06 05:59:43 PM PDT 24
Finished Jul 06 06:18:22 PM PDT 24
Peak memory 232984 kb
Host smart-4345b13f-afc2-46fe-bb8d-3e1d7ad5ac45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983816362 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.983816362
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.4045724615
Short name T594
Test name
Test status
Simulation time 447928671 ps
CPU time 1.8 seconds
Started Jul 06 05:59:36 PM PDT 24
Finished Jul 06 05:59:38 PM PDT 24
Peak memory 198588 kb
Host smart-afce26d0-c1cc-4466-81f3-08e6b1ed0926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045724615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.4045724615
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3643360791
Short name T1054
Test name
Test status
Simulation time 29443967395 ps
CPU time 23.41 seconds
Started Jul 06 05:59:37 PM PDT 24
Finished Jul 06 06:00:00 PM PDT 24
Peak memory 199980 kb
Host smart-988abf48-c729-4b55-a4c0-4d10f227fe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643360791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3643360791
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1662212850
Short name T615
Test name
Test status
Simulation time 34580796 ps
CPU time 0.56 seconds
Started Jul 06 05:59:48 PM PDT 24
Finished Jul 06 05:59:49 PM PDT 24
Peak memory 194748 kb
Host smart-f8daa8f9-6820-4fdc-a3c3-9bebf1675467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662212850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1662212850
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.435846071
Short name T1121
Test name
Test status
Simulation time 105895363286 ps
CPU time 47.53 seconds
Started Jul 06 05:59:43 PM PDT 24
Finished Jul 06 06:00:31 PM PDT 24
Peak memory 199964 kb
Host smart-4422c143-96b6-4701-b11c-87e5de288082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435846071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.435846071
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1519388690
Short name T1162
Test name
Test status
Simulation time 226749914797 ps
CPU time 29.78 seconds
Started Jul 06 05:59:43 PM PDT 24
Finished Jul 06 06:00:13 PM PDT 24
Peak memory 199884 kb
Host smart-e4b39707-a919-46bf-9bff-9314c11ccd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519388690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1519388690
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1815639454
Short name T889
Test name
Test status
Simulation time 53715561654 ps
CPU time 45.21 seconds
Started Jul 06 05:59:42 PM PDT 24
Finished Jul 06 06:00:27 PM PDT 24
Peak memory 199900 kb
Host smart-f4a5c740-d253-4bd5-bc72-69b33ad4077a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815639454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1815639454
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1937741824
Short name T974
Test name
Test status
Simulation time 134629763584 ps
CPU time 437.45 seconds
Started Jul 06 05:59:45 PM PDT 24
Finished Jul 06 06:07:03 PM PDT 24
Peak memory 200012 kb
Host smart-59466329-0a25-4c9e-9c0a-b3a8fe44b14c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937741824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1937741824
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.415014295
Short name T29
Test name
Test status
Simulation time 132720675071 ps
CPU time 259.04 seconds
Started Jul 06 05:59:48 PM PDT 24
Finished Jul 06 06:04:08 PM PDT 24
Peak memory 199900 kb
Host smart-1880d0c8-63a9-40ae-a4a7-b5a3a8c32340
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415014295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.415014295
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.4262073461
Short name T907
Test name
Test status
Simulation time 1837023490 ps
CPU time 1.55 seconds
Started Jul 06 05:59:46 PM PDT 24
Finished Jul 06 05:59:48 PM PDT 24
Peak memory 199868 kb
Host smart-01d436d8-b9be-4f69-8759-7644a49bdfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262073461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.4262073461
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.689665006
Short name T1177
Test name
Test status
Simulation time 184846291099 ps
CPU time 47.29 seconds
Started Jul 06 05:59:42 PM PDT 24
Finished Jul 06 06:00:30 PM PDT 24
Peak memory 199336 kb
Host smart-22c63e47-14a8-4d9b-acb2-6736e54d0dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689665006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.689665006
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1904688150
Short name T1052
Test name
Test status
Simulation time 24415673837 ps
CPU time 111.21 seconds
Started Jul 06 05:59:47 PM PDT 24
Finished Jul 06 06:01:39 PM PDT 24
Peak memory 200000 kb
Host smart-3b4676db-0e7b-485c-b196-509075c14aba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904688150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1904688150
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.4119553708
Short name T474
Test name
Test status
Simulation time 2531205577 ps
CPU time 5.88 seconds
Started Jul 06 05:59:42 PM PDT 24
Finished Jul 06 05:59:48 PM PDT 24
Peak memory 199292 kb
Host smart-73a143e5-7ba7-487c-b3ae-8327649d9476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4119553708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.4119553708
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.4100619094
Short name T161
Test name
Test status
Simulation time 92832013155 ps
CPU time 35.62 seconds
Started Jul 06 05:59:42 PM PDT 24
Finished Jul 06 06:00:19 PM PDT 24
Peak memory 199836 kb
Host smart-86dfd215-ebf0-48cb-a1e1-0acf650c6f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100619094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.4100619094
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2652342225
Short name T461
Test name
Test status
Simulation time 3892137808 ps
CPU time 2.62 seconds
Started Jul 06 05:59:42 PM PDT 24
Finished Jul 06 05:59:45 PM PDT 24
Peak memory 196432 kb
Host smart-2dca5f94-45fb-4d0b-92cd-300e51b24409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652342225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2652342225
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1626400274
Short name T488
Test name
Test status
Simulation time 896848586 ps
CPU time 1.83 seconds
Started Jul 06 05:59:42 PM PDT 24
Finished Jul 06 05:59:44 PM PDT 24
Peak memory 199852 kb
Host smart-b781495a-6d05-4c87-8b9d-b3b9202f4a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626400274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1626400274
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.7507907
Short name T1082
Test name
Test status
Simulation time 392047231637 ps
CPU time 188.65 seconds
Started Jul 06 05:59:51 PM PDT 24
Finished Jul 06 06:03:00 PM PDT 24
Peak memory 215844 kb
Host smart-b85faef4-4672-4751-8e10-98b3a6d32865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7507907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.7507907
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3237765028
Short name T623
Test name
Test status
Simulation time 80053555266 ps
CPU time 502.45 seconds
Started Jul 06 05:59:48 PM PDT 24
Finished Jul 06 06:08:11 PM PDT 24
Peak memory 216720 kb
Host smart-60091834-d108-42a8-b1b6-aae3e76349b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237765028 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3237765028
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1232304918
Short name T467
Test name
Test status
Simulation time 830944063 ps
CPU time 3.05 seconds
Started Jul 06 05:59:49 PM PDT 24
Finished Jul 06 05:59:52 PM PDT 24
Peak memory 198840 kb
Host smart-a5ae6e2e-18e3-43b3-b9aa-e8a7a3d8b33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232304918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1232304918
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.478502397
Short name T782
Test name
Test status
Simulation time 61765899448 ps
CPU time 22.74 seconds
Started Jul 06 05:59:45 PM PDT 24
Finished Jul 06 06:00:08 PM PDT 24
Peak memory 197908 kb
Host smart-015cabd5-e168-4673-9261-97dc2d01a899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478502397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.478502397
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1632521791
Short name T19
Test name
Test status
Simulation time 14434506 ps
CPU time 0.54 seconds
Started Jul 06 05:57:07 PM PDT 24
Finished Jul 06 05:57:08 PM PDT 24
Peak memory 195540 kb
Host smart-594463a3-378b-4e99-8256-52e13420522d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632521791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1632521791
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2092444183
Short name T471
Test name
Test status
Simulation time 92711203139 ps
CPU time 66.62 seconds
Started Jul 06 05:56:57 PM PDT 24
Finished Jul 06 05:58:04 PM PDT 24
Peak memory 199996 kb
Host smart-cd379921-3f01-4705-af4b-c581485c6375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092444183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2092444183
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1243744234
Short name T1068
Test name
Test status
Simulation time 29371307503 ps
CPU time 39.66 seconds
Started Jul 06 05:56:59 PM PDT 24
Finished Jul 06 05:57:39 PM PDT 24
Peak memory 199916 kb
Host smart-b7f29228-1781-433d-87cf-84d352a6f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243744234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1243744234
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2686080165
Short name T283
Test name
Test status
Simulation time 139476395420 ps
CPU time 56.81 seconds
Started Jul 06 05:57:02 PM PDT 24
Finished Jul 06 05:57:59 PM PDT 24
Peak memory 199988 kb
Host smart-7b18ad4e-adbc-4533-97d6-f0d2bc460119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686080165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2686080165
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3980223101
Short name T900
Test name
Test status
Simulation time 36761433921 ps
CPU time 19.07 seconds
Started Jul 06 05:57:01 PM PDT 24
Finished Jul 06 05:57:20 PM PDT 24
Peak memory 199912 kb
Host smart-464f5847-913f-4d92-bdb7-ec3900d15ac2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980223101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3980223101
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3405062016
Short name T41
Test name
Test status
Simulation time 152948111827 ps
CPU time 1117.71 seconds
Started Jul 06 05:57:01 PM PDT 24
Finished Jul 06 06:15:39 PM PDT 24
Peak memory 199856 kb
Host smart-caa03860-9c5e-4c35-b4a1-d8e40e66e75e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3405062016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3405062016
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3643381828
Short name T509
Test name
Test status
Simulation time 12463082619 ps
CPU time 22.28 seconds
Started Jul 06 05:57:00 PM PDT 24
Finished Jul 06 05:57:22 PM PDT 24
Peak memory 198884 kb
Host smart-603eb0a5-40a8-4757-8cde-56154eaa3c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643381828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3643381828
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1141368750
Short name T673
Test name
Test status
Simulation time 5312848375 ps
CPU time 8.9 seconds
Started Jul 06 05:57:00 PM PDT 24
Finished Jul 06 05:57:09 PM PDT 24
Peak memory 195976 kb
Host smart-ae15a131-c161-4f4a-b6cc-8e2b04862000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141368750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1141368750
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2033298802
Short name T276
Test name
Test status
Simulation time 11957470623 ps
CPU time 151.94 seconds
Started Jul 06 05:57:00 PM PDT 24
Finished Jul 06 05:59:32 PM PDT 24
Peak memory 200004 kb
Host smart-32c07961-70eb-4a4c-818f-cf1517726ea0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033298802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2033298802
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.442386227
Short name T365
Test name
Test status
Simulation time 2834393234 ps
CPU time 15.59 seconds
Started Jul 06 05:57:01 PM PDT 24
Finished Jul 06 05:57:17 PM PDT 24
Peak memory 197992 kb
Host smart-03d63009-a0af-42ef-97dc-6459209b0817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442386227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.442386227
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.854615678
Short name T1123
Test name
Test status
Simulation time 144731697747 ps
CPU time 67.69 seconds
Started Jul 06 05:57:00 PM PDT 24
Finished Jul 06 05:58:08 PM PDT 24
Peak memory 199956 kb
Host smart-f948ff5c-37ed-4c99-90a0-55a552715fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854615678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.854615678
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.15769159
Short name T571
Test name
Test status
Simulation time 38004204583 ps
CPU time 51.58 seconds
Started Jul 06 05:56:58 PM PDT 24
Finished Jul 06 05:57:50 PM PDT 24
Peak memory 195952 kb
Host smart-55cea015-6102-4fe7-92f0-1cc81488a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15769159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.15769159
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.462186443
Short name T107
Test name
Test status
Simulation time 321402506 ps
CPU time 0.82 seconds
Started Jul 06 05:57:05 PM PDT 24
Finished Jul 06 05:57:06 PM PDT 24
Peak memory 218348 kb
Host smart-8e9603e5-eea2-42d3-b58d-f928a7477de4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462186443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.462186443
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3867173417
Short name T465
Test name
Test status
Simulation time 447151043 ps
CPU time 2.37 seconds
Started Jul 06 05:56:56 PM PDT 24
Finished Jul 06 05:56:59 PM PDT 24
Peak memory 198848 kb
Host smart-d7d3029c-aad0-4dab-a9b3-5cb8d00a3087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867173417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3867173417
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2040085227
Short name T1000
Test name
Test status
Simulation time 382056711231 ps
CPU time 209.09 seconds
Started Jul 06 05:57:00 PM PDT 24
Finished Jul 06 06:00:29 PM PDT 24
Peak memory 199940 kb
Host smart-7c781322-a679-4666-871d-28ab64ede9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040085227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2040085227
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.359143173
Short name T1091
Test name
Test status
Simulation time 813334802 ps
CPU time 2.33 seconds
Started Jul 06 05:56:59 PM PDT 24
Finished Jul 06 05:57:02 PM PDT 24
Peak memory 199676 kb
Host smart-2dd09d2a-a86d-4e78-b572-ce869b93c4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359143173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.359143173
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3473750118
Short name T769
Test name
Test status
Simulation time 125412065827 ps
CPU time 62.9 seconds
Started Jul 06 05:56:56 PM PDT 24
Finished Jul 06 05:57:59 PM PDT 24
Peak memory 199848 kb
Host smart-e6aab5e2-5851-4540-87b3-125fba1a566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473750118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3473750118
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2717576467
Short name T1157
Test name
Test status
Simulation time 26120674 ps
CPU time 0.58 seconds
Started Jul 06 05:59:55 PM PDT 24
Finished Jul 06 05:59:56 PM PDT 24
Peak memory 195588 kb
Host smart-eb5fa4d3-110f-4da2-855b-401525569951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717576467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2717576467
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3841621716
Short name T1126
Test name
Test status
Simulation time 147689103039 ps
CPU time 107.91 seconds
Started Jul 06 05:59:51 PM PDT 24
Finished Jul 06 06:01:40 PM PDT 24
Peak memory 199960 kb
Host smart-b7447979-42d6-4578-aabb-fcf65cede564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841621716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3841621716
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2992672235
Short name T645
Test name
Test status
Simulation time 13706795135 ps
CPU time 24.34 seconds
Started Jul 06 05:59:47 PM PDT 24
Finished Jul 06 06:00:12 PM PDT 24
Peak memory 199984 kb
Host smart-abaa536e-1f53-4a05-9f06-77075d7d801c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992672235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2992672235
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.477189440
Short name T160
Test name
Test status
Simulation time 87028976097 ps
CPU time 41.11 seconds
Started Jul 06 05:59:49 PM PDT 24
Finished Jul 06 06:00:30 PM PDT 24
Peak memory 199964 kb
Host smart-0edca424-fa0a-4d19-bc66-d7b9928d2d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477189440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.477189440
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.769857979
Short name T79
Test name
Test status
Simulation time 175850358127 ps
CPU time 60.83 seconds
Started Jul 06 05:59:49 PM PDT 24
Finished Jul 06 06:00:50 PM PDT 24
Peak memory 199900 kb
Host smart-15c542fc-e5df-4107-87d6-5e4df49cf4c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769857979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.769857979
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.982887547
Short name T894
Test name
Test status
Simulation time 48647578484 ps
CPU time 365.08 seconds
Started Jul 06 05:59:55 PM PDT 24
Finished Jul 06 06:06:00 PM PDT 24
Peak memory 199844 kb
Host smart-f7d36b74-ad5b-4ce8-b7c6-039b085d8344
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=982887547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.982887547
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2427623782
Short name T780
Test name
Test status
Simulation time 5737729433 ps
CPU time 3.68 seconds
Started Jul 06 05:59:53 PM PDT 24
Finished Jul 06 05:59:57 PM PDT 24
Peak memory 199508 kb
Host smart-3323e8bf-8c3b-4792-8b23-d7e5373ee485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427623782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2427623782
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.329670638
Short name T691
Test name
Test status
Simulation time 73336613280 ps
CPU time 105.97 seconds
Started Jul 06 05:59:49 PM PDT 24
Finished Jul 06 06:01:35 PM PDT 24
Peak memory 199500 kb
Host smart-24577694-cb49-478e-8cf6-4eedc57de530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329670638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.329670638
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2623779189
Short name T971
Test name
Test status
Simulation time 20143279334 ps
CPU time 1035.34 seconds
Started Jul 06 05:59:55 PM PDT 24
Finished Jul 06 06:17:10 PM PDT 24
Peak memory 199992 kb
Host smart-7d758da9-bc6a-4a4e-bb6b-f3eab02f1448
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623779189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2623779189
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.958057876
Short name T411
Test name
Test status
Simulation time 1380049681 ps
CPU time 3.11 seconds
Started Jul 06 05:59:47 PM PDT 24
Finished Jul 06 05:59:51 PM PDT 24
Peak memory 198040 kb
Host smart-d2b86145-4eeb-4ec9-9eae-14227c283ebc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=958057876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.958057876
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3492076667
Short name T960
Test name
Test status
Simulation time 19834895659 ps
CPU time 17.44 seconds
Started Jul 06 05:59:48 PM PDT 24
Finished Jul 06 06:00:06 PM PDT 24
Peak memory 199540 kb
Host smart-1a7838f2-9400-43ca-a8b6-186535c0c52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492076667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3492076667
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2828226827
Short name T501
Test name
Test status
Simulation time 39199922377 ps
CPU time 15.96 seconds
Started Jul 06 05:59:47 PM PDT 24
Finished Jul 06 06:00:04 PM PDT 24
Peak memory 195980 kb
Host smart-c9ee4f3c-366e-4bd2-8e51-04263fa38cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828226827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2828226827
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.481473704
Short name T7
Test name
Test status
Simulation time 5523298172 ps
CPU time 7.52 seconds
Started Jul 06 05:59:48 PM PDT 24
Finished Jul 06 05:59:56 PM PDT 24
Peak memory 199928 kb
Host smart-dba8a012-c642-487d-910e-2e45ede0aa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481473704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.481473704
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.15366800
Short name T1098
Test name
Test status
Simulation time 41843560813 ps
CPU time 78.05 seconds
Started Jul 06 05:59:55 PM PDT 24
Finished Jul 06 06:01:13 PM PDT 24
Peak memory 199948 kb
Host smart-0f35faa3-ee5d-4a40-9743-11f172adc078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15366800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.15366800
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.4113516959
Short name T866
Test name
Test status
Simulation time 14547729125 ps
CPU time 168.16 seconds
Started Jul 06 06:00:02 PM PDT 24
Finished Jul 06 06:02:50 PM PDT 24
Peak memory 215608 kb
Host smart-04ce8276-7634-401e-b605-a62166a04d22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113516959 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.4113516959
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3901226286
Short name T1148
Test name
Test status
Simulation time 1434348509 ps
CPU time 1.55 seconds
Started Jul 06 05:59:47 PM PDT 24
Finished Jul 06 05:59:49 PM PDT 24
Peak memory 198552 kb
Host smart-a0b683a8-c598-4dd5-95ee-c18aca405b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901226286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3901226286
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2936801285
Short name T1118
Test name
Test status
Simulation time 41657272404 ps
CPU time 16.21 seconds
Started Jul 06 05:59:48 PM PDT 24
Finished Jul 06 06:00:05 PM PDT 24
Peak memory 199904 kb
Host smart-008613b6-7ed8-43cf-9d98-8a89c537fb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936801285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2936801285
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2657287635
Short name T846
Test name
Test status
Simulation time 48294902 ps
CPU time 0.56 seconds
Started Jul 06 06:00:04 PM PDT 24
Finished Jul 06 06:00:05 PM PDT 24
Peak memory 195616 kb
Host smart-73058d4f-483e-4386-94ac-1d7ba8387b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657287635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2657287635
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.15149407
Short name T656
Test name
Test status
Simulation time 35115837182 ps
CPU time 15.06 seconds
Started Jul 06 06:00:01 PM PDT 24
Finished Jul 06 06:00:17 PM PDT 24
Peak memory 199932 kb
Host smart-7b69a79f-e421-43c3-94a6-a977ba97484f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15149407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.15149407
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2994444696
Short name T682
Test name
Test status
Simulation time 123551298725 ps
CPU time 62.52 seconds
Started Jul 06 05:59:55 PM PDT 24
Finished Jul 06 06:00:58 PM PDT 24
Peak memory 199908 kb
Host smart-5e47dac3-c088-45aa-b3cc-f356001e69c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994444696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2994444696
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.414392147
Short name T218
Test name
Test status
Simulation time 50596050406 ps
CPU time 23.19 seconds
Started Jul 06 05:59:53 PM PDT 24
Finished Jul 06 06:00:16 PM PDT 24
Peak memory 199932 kb
Host smart-db5f63c0-a3f2-4bb0-8c8f-95a4394e3c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414392147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.414392147
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1204630575
Short name T529
Test name
Test status
Simulation time 7931412126 ps
CPU time 9.47 seconds
Started Jul 06 05:59:55 PM PDT 24
Finished Jul 06 06:00:04 PM PDT 24
Peak memory 199912 kb
Host smart-8ba70844-c1a0-4f8d-924d-df51740ff7dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204630575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1204630575
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4102908930
Short name T388
Test name
Test status
Simulation time 84179938638 ps
CPU time 453.99 seconds
Started Jul 06 06:00:08 PM PDT 24
Finished Jul 06 06:07:43 PM PDT 24
Peak memory 199968 kb
Host smart-9e3f2213-f28c-4d75-b7fd-29961aa3be25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102908930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4102908930
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2918586998
Short name T601
Test name
Test status
Simulation time 1106721234 ps
CPU time 0.96 seconds
Started Jul 06 06:00:01 PM PDT 24
Finished Jul 06 06:00:02 PM PDT 24
Peak memory 197084 kb
Host smart-d70fff53-32be-44fd-85a4-be6b0fd10e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918586998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2918586998
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1302200714
Short name T578
Test name
Test status
Simulation time 216392571875 ps
CPU time 38.46 seconds
Started Jul 06 06:00:09 PM PDT 24
Finished Jul 06 06:00:48 PM PDT 24
Peak memory 200184 kb
Host smart-9c033606-5d70-4abc-9508-3f8b5135ed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302200714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1302200714
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2896166656
Short name T376
Test name
Test status
Simulation time 11010229207 ps
CPU time 83.84 seconds
Started Jul 06 06:00:03 PM PDT 24
Finished Jul 06 06:01:27 PM PDT 24
Peak memory 199908 kb
Host smart-ef1f7b05-86e9-4302-a3f1-840386f6793c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2896166656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2896166656
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.4179720143
Short name T1065
Test name
Test status
Simulation time 6609949713 ps
CPU time 4.56 seconds
Started Jul 06 05:59:56 PM PDT 24
Finished Jul 06 06:00:01 PM PDT 24
Peak memory 198360 kb
Host smart-034655f6-4688-482c-92e6-1778edb3423c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179720143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.4179720143
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.898407027
Short name T760
Test name
Test status
Simulation time 48811441640 ps
CPU time 42.71 seconds
Started Jul 06 06:00:00 PM PDT 24
Finished Jul 06 06:00:43 PM PDT 24
Peak memory 199896 kb
Host smart-7c24fdee-fda1-4d4e-aec2-8e8a0f298f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898407027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.898407027
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2867120416
Short name T402
Test name
Test status
Simulation time 2923434553 ps
CPU time 4.82 seconds
Started Jul 06 06:00:04 PM PDT 24
Finished Jul 06 06:00:09 PM PDT 24
Peak memory 196432 kb
Host smart-ad58d693-03c5-47bc-93db-8666b4c6c711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867120416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2867120416
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2077638820
Short name T994
Test name
Test status
Simulation time 734828850 ps
CPU time 3.15 seconds
Started Jul 06 05:59:55 PM PDT 24
Finished Jul 06 05:59:58 PM PDT 24
Peak memory 199868 kb
Host smart-1ff2e989-2f93-4ded-a2e8-9e31138c3eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077638820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2077638820
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1977773796
Short name T937
Test name
Test status
Simulation time 172146875487 ps
CPU time 86.75 seconds
Started Jul 06 06:00:03 PM PDT 24
Finished Jul 06 06:01:30 PM PDT 24
Peak memory 199968 kb
Host smart-99135cbf-4d4b-45d9-ab9e-aa951badd6ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977773796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1977773796
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.754258313
Short name T270
Test name
Test status
Simulation time 51047974980 ps
CPU time 446.92 seconds
Started Jul 06 06:00:03 PM PDT 24
Finished Jul 06 06:07:30 PM PDT 24
Peak memory 216684 kb
Host smart-bd40ca8f-8317-4caf-b538-60a2cf07bcde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754258313 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.754258313
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.147061256
Short name T528
Test name
Test status
Simulation time 6362488288 ps
CPU time 21.13 seconds
Started Jul 06 06:00:02 PM PDT 24
Finished Jul 06 06:00:23 PM PDT 24
Peak memory 199344 kb
Host smart-41703c57-d3a0-4ce2-97c0-00818e0eb96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147061256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.147061256
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3947340253
Short name T874
Test name
Test status
Simulation time 36582563410 ps
CPU time 62.94 seconds
Started Jul 06 05:59:54 PM PDT 24
Finished Jul 06 06:00:57 PM PDT 24
Peak memory 199944 kb
Host smart-ef5f27af-dd8a-441d-a964-ea72374cd176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947340253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3947340253
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3281227609
Short name T387
Test name
Test status
Simulation time 11277760 ps
CPU time 0.55 seconds
Started Jul 06 06:00:04 PM PDT 24
Finished Jul 06 06:00:05 PM PDT 24
Peak memory 195232 kb
Host smart-3a8e04ea-a574-4c26-9fa4-a8ab9618c133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281227609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3281227609
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3964660278
Short name T609
Test name
Test status
Simulation time 86580381814 ps
CPU time 37.84 seconds
Started Jul 06 06:00:02 PM PDT 24
Finished Jul 06 06:00:40 PM PDT 24
Peak memory 199928 kb
Host smart-709f467f-ee48-489b-8282-3a82e54ddcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964660278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3964660278
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3737015984
Short name T112
Test name
Test status
Simulation time 53798930225 ps
CPU time 98.33 seconds
Started Jul 06 06:00:09 PM PDT 24
Finished Jul 06 06:01:47 PM PDT 24
Peak memory 199992 kb
Host smart-ccddb029-0c8a-48d2-b4a8-0113b204b870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737015984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3737015984
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.800763841
Short name T232
Test name
Test status
Simulation time 11230600948 ps
CPU time 27.25 seconds
Started Jul 06 06:00:02 PM PDT 24
Finished Jul 06 06:00:30 PM PDT 24
Peak memory 199908 kb
Host smart-2facdae1-3a2f-4e31-9cb1-1a506ad17e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800763841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.800763841
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1786868135
Short name T1035
Test name
Test status
Simulation time 5107372539 ps
CPU time 4.57 seconds
Started Jul 06 06:00:13 PM PDT 24
Finished Jul 06 06:00:18 PM PDT 24
Peak memory 199976 kb
Host smart-585ea8a3-94ac-414f-b285-6c83ee654367
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786868135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1786868135
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3477623550
Short name T559
Test name
Test status
Simulation time 88375872289 ps
CPU time 620.66 seconds
Started Jul 06 06:00:04 PM PDT 24
Finished Jul 06 06:10:25 PM PDT 24
Peak memory 199972 kb
Host smart-86c52b2c-38a3-410b-91a9-fb2f2a56b4a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477623550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3477623550
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1348239909
Short name T373
Test name
Test status
Simulation time 11210497742 ps
CPU time 12.16 seconds
Started Jul 06 06:00:02 PM PDT 24
Finished Jul 06 06:00:15 PM PDT 24
Peak memory 198732 kb
Host smart-5ee5ad3b-d9ac-40bd-997c-b22730d72c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348239909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1348239909
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3744820020
Short name T1141
Test name
Test status
Simulation time 202401200569 ps
CPU time 82.39 seconds
Started Jul 06 06:00:03 PM PDT 24
Finished Jul 06 06:01:25 PM PDT 24
Peak memory 200128 kb
Host smart-2b91fa4d-b763-4608-adf9-569b4572a82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744820020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3744820020
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2200085388
Short name T459
Test name
Test status
Simulation time 23647520342 ps
CPU time 129.98 seconds
Started Jul 06 06:00:14 PM PDT 24
Finished Jul 06 06:02:25 PM PDT 24
Peak memory 200004 kb
Host smart-46680f69-3f1d-4acd-a43c-53d4ccff2259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200085388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2200085388
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3894170093
Short name T114
Test name
Test status
Simulation time 2487183121 ps
CPU time 14.44 seconds
Started Jul 06 06:00:14 PM PDT 24
Finished Jul 06 06:00:28 PM PDT 24
Peak memory 197576 kb
Host smart-1aae5787-03ab-4a2c-91c2-8232bea224dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894170093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3894170093
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3391070578
Short name T633
Test name
Test status
Simulation time 48157503889 ps
CPU time 17.1 seconds
Started Jul 06 06:00:13 PM PDT 24
Finished Jul 06 06:00:31 PM PDT 24
Peak memory 196768 kb
Host smart-562baca0-8a87-4497-a100-7d7ccaa57f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391070578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3391070578
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3555086225
Short name T834
Test name
Test status
Simulation time 286835587 ps
CPU time 1.53 seconds
Started Jul 06 06:00:08 PM PDT 24
Finished Jul 06 06:00:10 PM PDT 24
Peak memory 199576 kb
Host smart-d7fcb192-ddcb-4960-b7f6-f2746201a064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555086225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3555086225
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2298431508
Short name T124
Test name
Test status
Simulation time 36395267088 ps
CPU time 53.8 seconds
Started Jul 06 06:00:03 PM PDT 24
Finished Jul 06 06:00:57 PM PDT 24
Peak memory 200092 kb
Host smart-4f0e5375-19cf-47e1-bb84-1b762c6defc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298431508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2298431508
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3595830285
Short name T108
Test name
Test status
Simulation time 301917109223 ps
CPU time 920.59 seconds
Started Jul 06 06:00:02 PM PDT 24
Finished Jul 06 06:15:23 PM PDT 24
Peak memory 224960 kb
Host smart-dfb0947c-eb89-4198-8093-fead26434428
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595830285 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3595830285
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3017178477
Short name T985
Test name
Test status
Simulation time 12665870342 ps
CPU time 51.85 seconds
Started Jul 06 06:00:14 PM PDT 24
Finished Jul 06 06:01:06 PM PDT 24
Peak memory 200008 kb
Host smart-74575d4f-df7c-4bbe-9f0f-907e4ce9f33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017178477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3017178477
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.877738443
Short name T440
Test name
Test status
Simulation time 8198539797 ps
CPU time 11.3 seconds
Started Jul 06 06:00:04 PM PDT 24
Finished Jul 06 06:00:16 PM PDT 24
Peak memory 196992 kb
Host smart-a9812c55-750e-4411-a5a7-441736c75ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877738443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.877738443
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3874836757
Short name T458
Test name
Test status
Simulation time 21234931 ps
CPU time 0.55 seconds
Started Jul 06 06:00:08 PM PDT 24
Finished Jul 06 06:00:09 PM PDT 24
Peak memory 194984 kb
Host smart-cf363d7b-e2b9-4432-90b0-2ca9e6e4a1f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874836757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3874836757
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.691210681
Short name T1111
Test name
Test status
Simulation time 18852616800 ps
CPU time 14.55 seconds
Started Jul 06 06:00:07 PM PDT 24
Finished Jul 06 06:00:22 PM PDT 24
Peak memory 199948 kb
Host smart-389bb4d2-a438-4a58-b82f-40042cd2995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691210681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.691210681
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2176992858
Short name T1103
Test name
Test status
Simulation time 88809266084 ps
CPU time 133.49 seconds
Started Jul 06 06:00:07 PM PDT 24
Finished Jul 06 06:02:21 PM PDT 24
Peak memory 199900 kb
Host smart-65ff25c0-d45a-40e3-aee1-866a9cf7483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176992858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2176992858
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3709113966
Short name T921
Test name
Test status
Simulation time 11019778790 ps
CPU time 16.18 seconds
Started Jul 06 06:00:08 PM PDT 24
Finished Jul 06 06:00:24 PM PDT 24
Peak memory 199484 kb
Host smart-bcd39362-5c46-4094-9f9b-ac234d88e282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709113966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3709113966
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3524247972
Short name T384
Test name
Test status
Simulation time 43376954755 ps
CPU time 34.96 seconds
Started Jul 06 06:00:07 PM PDT 24
Finished Jul 06 06:00:43 PM PDT 24
Peak memory 199896 kb
Host smart-054badf8-2ef3-448d-ba84-f8f6991ffce6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524247972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3524247972
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1821152891
Short name T452
Test name
Test status
Simulation time 114016657413 ps
CPU time 119.1 seconds
Started Jul 06 06:00:07 PM PDT 24
Finished Jul 06 06:02:07 PM PDT 24
Peak memory 199956 kb
Host smart-b92d8e4f-ae5f-41b4-8d17-d2bea8260b8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821152891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1821152891
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2219253702
Short name T883
Test name
Test status
Simulation time 1823011295 ps
CPU time 3.51 seconds
Started Jul 06 06:00:09 PM PDT 24
Finished Jul 06 06:00:13 PM PDT 24
Peak memory 197468 kb
Host smart-68a35316-9842-4bff-ace8-4a360591899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219253702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2219253702
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2921270698
Short name T848
Test name
Test status
Simulation time 437644818837 ps
CPU time 69.12 seconds
Started Jul 06 06:00:07 PM PDT 24
Finished Jul 06 06:01:17 PM PDT 24
Peak memory 208384 kb
Host smart-2581681a-cb3e-44b4-a56e-ac6eb97e153b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921270698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2921270698
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.345059974
Short name T791
Test name
Test status
Simulation time 12578053776 ps
CPU time 623.02 seconds
Started Jul 06 06:00:07 PM PDT 24
Finished Jul 06 06:10:30 PM PDT 24
Peak memory 199980 kb
Host smart-ebc58a33-6547-449d-b537-ad17e430972e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=345059974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.345059974
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.4173605825
Short name T395
Test name
Test status
Simulation time 2117997661 ps
CPU time 12.6 seconds
Started Jul 06 06:00:07 PM PDT 24
Finished Jul 06 06:00:20 PM PDT 24
Peak memory 198088 kb
Host smart-150edc3f-9e1c-49cc-9deb-b2f008b345c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173605825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.4173605825
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.395706952
Short name T986
Test name
Test status
Simulation time 384087418440 ps
CPU time 61.78 seconds
Started Jul 06 06:00:09 PM PDT 24
Finished Jul 06 06:01:11 PM PDT 24
Peak memory 199812 kb
Host smart-ef9c841e-2e4f-4eda-bad5-5096e590c92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395706952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.395706952
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1648711500
Short name T819
Test name
Test status
Simulation time 2246521170 ps
CPU time 4.11 seconds
Started Jul 06 06:00:09 PM PDT 24
Finished Jul 06 06:00:13 PM PDT 24
Peak memory 195440 kb
Host smart-a89d9736-b1b5-4d6c-a8b5-6133b32af58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648711500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1648711500
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3255913464
Short name T400
Test name
Test status
Simulation time 552787587 ps
CPU time 2.28 seconds
Started Jul 06 06:00:14 PM PDT 24
Finished Jul 06 06:00:16 PM PDT 24
Peak memory 198628 kb
Host smart-2529a30a-1dad-4c0f-b2bd-177e86658a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255913464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3255913464
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1102947251
Short name T1025
Test name
Test status
Simulation time 435677789243 ps
CPU time 403.5 seconds
Started Jul 06 06:00:14 PM PDT 24
Finished Jul 06 06:06:58 PM PDT 24
Peak memory 199984 kb
Host smart-9a8a7209-b728-4d6a-9dfb-f6438bd17b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102947251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1102947251
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3610972325
Short name T56
Test name
Test status
Simulation time 49945591020 ps
CPU time 267.56 seconds
Started Jul 06 06:00:07 PM PDT 24
Finished Jul 06 06:04:36 PM PDT 24
Peak memory 216536 kb
Host smart-89470af0-893e-4494-a596-bed749caa360
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610972325 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3610972325
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.324908932
Short name T838
Test name
Test status
Simulation time 2580484629 ps
CPU time 2.01 seconds
Started Jul 06 06:00:08 PM PDT 24
Finished Jul 06 06:00:10 PM PDT 24
Peak memory 198228 kb
Host smart-430696e4-8638-49d4-985e-8a89c6dce406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324908932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.324908932
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2522185159
Short name T934
Test name
Test status
Simulation time 4296251608 ps
CPU time 7.49 seconds
Started Jul 06 06:00:03 PM PDT 24
Finished Jul 06 06:00:10 PM PDT 24
Peak memory 199888 kb
Host smart-cb1b4e64-5f34-477b-b86c-9a07036a0d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522185159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2522185159
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.351771626
Short name T360
Test name
Test status
Simulation time 12286927 ps
CPU time 0.57 seconds
Started Jul 06 06:00:17 PM PDT 24
Finished Jul 06 06:00:18 PM PDT 24
Peak memory 195548 kb
Host smart-41308a7f-baa3-4d9a-b55e-1f451f77443a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351771626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.351771626
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1628229738
Short name T962
Test name
Test status
Simulation time 159437572034 ps
CPU time 73.92 seconds
Started Jul 06 06:00:07 PM PDT 24
Finished Jul 06 06:01:21 PM PDT 24
Peak memory 199972 kb
Host smart-98c4c42e-dd95-4365-ba10-7049d886fdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628229738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1628229738
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3399051606
Short name T1007
Test name
Test status
Simulation time 100714994109 ps
CPU time 162.24 seconds
Started Jul 06 06:00:14 PM PDT 24
Finished Jul 06 06:02:57 PM PDT 24
Peak memory 199940 kb
Host smart-d7a1abfa-d8a1-476e-91a6-288afb7b9e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399051606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3399051606
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2340306169
Short name T773
Test name
Test status
Simulation time 98307031213 ps
CPU time 166.83 seconds
Started Jul 06 06:00:13 PM PDT 24
Finished Jul 06 06:03:00 PM PDT 24
Peak memory 199912 kb
Host smart-c92852b6-6aa1-42bc-af20-d813f07b5fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340306169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2340306169
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2236065291
Short name T504
Test name
Test status
Simulation time 21317118314 ps
CPU time 8.06 seconds
Started Jul 06 06:00:13 PM PDT 24
Finished Jul 06 06:00:21 PM PDT 24
Peak memory 199820 kb
Host smart-d8526601-5427-4d55-963e-40ad42223468
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236065291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2236065291
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1609649582
Short name T1056
Test name
Test status
Simulation time 170649662994 ps
CPU time 593.86 seconds
Started Jul 06 06:00:12 PM PDT 24
Finished Jul 06 06:10:06 PM PDT 24
Peak memory 200028 kb
Host smart-709ba15a-0c19-473c-9ce0-2b783b6f25ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1609649582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1609649582
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1873601918
Short name T729
Test name
Test status
Simulation time 5796597316 ps
CPU time 11.37 seconds
Started Jul 06 06:00:11 PM PDT 24
Finished Jul 06 06:00:23 PM PDT 24
Peak memory 198444 kb
Host smart-cfbbc4a1-a1a9-44db-b962-2e476ea016d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873601918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1873601918
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.559823354
Short name T737
Test name
Test status
Simulation time 67989104728 ps
CPU time 25.83 seconds
Started Jul 06 06:00:13 PM PDT 24
Finished Jul 06 06:00:39 PM PDT 24
Peak memory 208456 kb
Host smart-9c5e9e32-a2f5-4bdf-b55c-da31778c2a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559823354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.559823354
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.933896291
Short name T1073
Test name
Test status
Simulation time 14051809778 ps
CPU time 729.92 seconds
Started Jul 06 06:00:13 PM PDT 24
Finished Jul 06 06:12:23 PM PDT 24
Peak memory 199948 kb
Host smart-bdac14ec-b916-42c2-a22b-0d1d1925fad7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933896291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.933896291
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1497256796
Short name T597
Test name
Test status
Simulation time 7604557280 ps
CPU time 16.15 seconds
Started Jul 06 06:00:12 PM PDT 24
Finished Jul 06 06:00:28 PM PDT 24
Peak memory 197840 kb
Host smart-68fa0d0f-28a5-47ec-8da6-ccd7f9c393fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497256796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1497256796
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1503914753
Short name T742
Test name
Test status
Simulation time 92233747588 ps
CPU time 145.54 seconds
Started Jul 06 06:00:13 PM PDT 24
Finished Jul 06 06:02:39 PM PDT 24
Peak memory 199888 kb
Host smart-60f7499c-be66-460b-8c54-2674dbababca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503914753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1503914753
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2068352886
Short name T1092
Test name
Test status
Simulation time 27747419834 ps
CPU time 21.03 seconds
Started Jul 06 06:00:11 PM PDT 24
Finished Jul 06 06:00:33 PM PDT 24
Peak memory 196800 kb
Host smart-c9d14b33-7bfb-415e-bf92-0742c90c3276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068352886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2068352886
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2992727460
Short name T1161
Test name
Test status
Simulation time 333984395 ps
CPU time 1.14 seconds
Started Jul 06 06:00:07 PM PDT 24
Finished Jul 06 06:00:09 PM PDT 24
Peak memory 198540 kb
Host smart-c31431d6-4e77-44a2-9917-55d7b5a02e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992727460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2992727460
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2437531233
Short name T858
Test name
Test status
Simulation time 185160321482 ps
CPU time 255.67 seconds
Started Jul 06 06:00:19 PM PDT 24
Finished Jul 06 06:04:35 PM PDT 24
Peak memory 199980 kb
Host smart-74ac7d26-8d6e-4021-a8a6-892b174b4fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437531233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2437531233
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3217757255
Short name T66
Test name
Test status
Simulation time 178717564061 ps
CPU time 421.76 seconds
Started Jul 06 06:00:11 PM PDT 24
Finished Jul 06 06:07:14 PM PDT 24
Peak memory 211380 kb
Host smart-75826859-5407-4340-8e77-79c156bd9073
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217757255 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3217757255
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2152845820
Short name T634
Test name
Test status
Simulation time 1618578021 ps
CPU time 2.94 seconds
Started Jul 06 06:00:13 PM PDT 24
Finished Jul 06 06:00:16 PM PDT 24
Peak memory 198340 kb
Host smart-f3d637a3-0ad5-4042-8790-4b9ed88cc539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152845820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2152845820
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3937813680
Short name T340
Test name
Test status
Simulation time 15965697627 ps
CPU time 13.11 seconds
Started Jul 06 06:00:08 PM PDT 24
Finished Jul 06 06:00:21 PM PDT 24
Peak memory 199272 kb
Host smart-e18abb97-2b4a-46d0-84fb-a35cf78de0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937813680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3937813680
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3591403430
Short name T17
Test name
Test status
Simulation time 23438872 ps
CPU time 0.54 seconds
Started Jul 06 06:00:23 PM PDT 24
Finished Jul 06 06:00:24 PM PDT 24
Peak memory 195316 kb
Host smart-6051db0d-640d-4e78-80f9-8fe99b673e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591403430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3591403430
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.907671761
Short name T1179
Test name
Test status
Simulation time 139630008434 ps
CPU time 12.51 seconds
Started Jul 06 06:00:19 PM PDT 24
Finished Jul 06 06:00:32 PM PDT 24
Peak memory 199236 kb
Host smart-4a5cea39-7228-4f21-8f3d-4ea824cfabbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907671761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.907671761
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2615540949
Short name T135
Test name
Test status
Simulation time 100947161785 ps
CPU time 147.98 seconds
Started Jul 06 06:00:17 PM PDT 24
Finished Jul 06 06:02:46 PM PDT 24
Peak memory 199820 kb
Host smart-3804f829-2aa2-4927-afba-098ed635c84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615540949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2615540949
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_intr.3661513573
Short name T999
Test name
Test status
Simulation time 13517562992 ps
CPU time 19 seconds
Started Jul 06 06:00:15 PM PDT 24
Finished Jul 06 06:00:35 PM PDT 24
Peak memory 200220 kb
Host smart-efd4842d-1497-40b6-aea1-fcf05e3a3a1d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661513573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3661513573
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3801658459
Short name T451
Test name
Test status
Simulation time 122810932938 ps
CPU time 273.95 seconds
Started Jul 06 06:00:22 PM PDT 24
Finished Jul 06 06:04:56 PM PDT 24
Peak memory 199996 kb
Host smart-b05a44fb-f740-4656-ad5c-9bc8a8e45663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3801658459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3801658459
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2276916868
Short name T1080
Test name
Test status
Simulation time 3726885354 ps
CPU time 2.52 seconds
Started Jul 06 06:00:16 PM PDT 24
Finished Jul 06 06:00:19 PM PDT 24
Peak memory 199856 kb
Host smart-ffad1ec1-c030-4d54-a31b-0f75db1a8e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276916868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2276916868
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.19080473
Short name T765
Test name
Test status
Simulation time 105205486190 ps
CPU time 46.41 seconds
Started Jul 06 06:00:16 PM PDT 24
Finished Jul 06 06:01:02 PM PDT 24
Peak memory 198824 kb
Host smart-684adef8-d252-4d32-83fb-92bc31e938ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19080473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.19080473
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2213632904
Short name T381
Test name
Test status
Simulation time 16232773946 ps
CPU time 229.14 seconds
Started Jul 06 06:00:19 PM PDT 24
Finished Jul 06 06:04:09 PM PDT 24
Peak memory 199928 kb
Host smart-0e91cbc1-5741-46c9-8e80-557030dbf375
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213632904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2213632904
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.225841226
Short name T977
Test name
Test status
Simulation time 5339851602 ps
CPU time 26.05 seconds
Started Jul 06 06:00:15 PM PDT 24
Finished Jul 06 06:00:42 PM PDT 24
Peak memory 198196 kb
Host smart-770cfd0d-eb37-499b-8b51-6812e85355fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225841226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.225841226
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2947780049
Short name T710
Test name
Test status
Simulation time 33372721025 ps
CPU time 53.87 seconds
Started Jul 06 06:00:18 PM PDT 24
Finished Jul 06 06:01:12 PM PDT 24
Peak memory 199936 kb
Host smart-ccfdd83c-ae1c-4d3f-a392-fea7f16ded75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947780049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2947780049
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2368372371
Short name T1164
Test name
Test status
Simulation time 33623446748 ps
CPU time 49.72 seconds
Started Jul 06 06:00:16 PM PDT 24
Finished Jul 06 06:01:06 PM PDT 24
Peak memory 195924 kb
Host smart-bf04ef9a-56a0-488b-b07a-664fc00dd439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368372371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2368372371
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3644383007
Short name T64
Test name
Test status
Simulation time 484739240 ps
CPU time 2.46 seconds
Started Jul 06 06:00:18 PM PDT 24
Finished Jul 06 06:00:21 PM PDT 24
Peak memory 198172 kb
Host smart-e7a690e4-3214-4b8e-89a5-8b7031f09c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644383007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3644383007
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3335641590
Short name T935
Test name
Test status
Simulation time 274955579811 ps
CPU time 460.89 seconds
Started Jul 06 06:00:21 PM PDT 24
Finished Jul 06 06:08:02 PM PDT 24
Peak memory 199944 kb
Host smart-9b2892b7-6bd7-4adf-b9a3-c3249aecb569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335641590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3335641590
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.271712785
Short name T1159
Test name
Test status
Simulation time 144837235781 ps
CPU time 1221.57 seconds
Started Jul 06 06:00:21 PM PDT 24
Finished Jul 06 06:20:43 PM PDT 24
Peak memory 232944 kb
Host smart-2000bb85-efc2-4312-b088-7d3c35954107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271712785 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.271712785
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2051716047
Short name T419
Test name
Test status
Simulation time 1969590161 ps
CPU time 3.19 seconds
Started Jul 06 06:00:19 PM PDT 24
Finished Jul 06 06:00:23 PM PDT 24
Peak memory 198860 kb
Host smart-cbc615c5-4d4b-493b-ad5f-4a82eb89cf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051716047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2051716047
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2844486903
Short name T801
Test name
Test status
Simulation time 38395447469 ps
CPU time 17.85 seconds
Started Jul 06 06:00:17 PM PDT 24
Finished Jul 06 06:00:35 PM PDT 24
Peak memory 199984 kb
Host smart-41bd9768-386b-4394-9143-1adac4b5fed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844486903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2844486903
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2648717952
Short name T372
Test name
Test status
Simulation time 25198287 ps
CPU time 0.57 seconds
Started Jul 06 06:00:27 PM PDT 24
Finished Jul 06 06:00:28 PM PDT 24
Peak memory 195296 kb
Host smart-3974fa84-100f-4b12-b1d1-08eb9cec5dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648717952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2648717952
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.57159842
Short name T319
Test name
Test status
Simulation time 30849962043 ps
CPU time 26.25 seconds
Started Jul 06 06:00:23 PM PDT 24
Finished Jul 06 06:00:50 PM PDT 24
Peak memory 199912 kb
Host smart-8ca03e9a-a418-4dc7-97ab-9c20d3a953a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57159842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.57159842
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2424863389
Short name T703
Test name
Test status
Simulation time 27476818395 ps
CPU time 16.26 seconds
Started Jul 06 06:00:22 PM PDT 24
Finished Jul 06 06:00:39 PM PDT 24
Peak memory 199916 kb
Host smart-a7f6e6fd-1527-4149-b9ad-53a19755c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424863389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2424863389
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.257513207
Short name T199
Test name
Test status
Simulation time 23640480297 ps
CPU time 43.53 seconds
Started Jul 06 06:00:23 PM PDT 24
Finished Jul 06 06:01:07 PM PDT 24
Peak memory 199980 kb
Host smart-a4f88d77-a164-469b-87b7-6b36de562a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257513207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.257513207
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2420898424
Short name T450
Test name
Test status
Simulation time 75105243098 ps
CPU time 39.44 seconds
Started Jul 06 06:00:22 PM PDT 24
Finished Jul 06 06:01:01 PM PDT 24
Peak memory 199968 kb
Host smart-52b8a8b3-4356-4589-8283-61867da1765c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420898424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2420898424
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3513666197
Short name T758
Test name
Test status
Simulation time 60099977306 ps
CPU time 164.75 seconds
Started Jul 06 06:00:25 PM PDT 24
Finished Jul 06 06:03:10 PM PDT 24
Peak memory 200008 kb
Host smart-60c14ab0-6f4d-4c0b-a863-18ae9a8da542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513666197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3513666197
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.29018707
Short name T339
Test name
Test status
Simulation time 6840511270 ps
CPU time 4 seconds
Started Jul 06 06:00:25 PM PDT 24
Finished Jul 06 06:00:29 PM PDT 24
Peak memory 198368 kb
Host smart-0f79c70f-15c6-4d8d-94b3-502489cb65a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29018707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.29018707
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1231763253
Short name T1070
Test name
Test status
Simulation time 16187219701 ps
CPU time 11.67 seconds
Started Jul 06 06:00:21 PM PDT 24
Finished Jul 06 06:00:33 PM PDT 24
Peak memory 194856 kb
Host smart-8d3b801c-f088-4b6d-8232-0922313fbfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231763253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1231763253
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.4249008909
Short name T1077
Test name
Test status
Simulation time 31496774536 ps
CPU time 447.26 seconds
Started Jul 06 06:00:26 PM PDT 24
Finished Jul 06 06:07:53 PM PDT 24
Peak memory 199860 kb
Host smart-b368ed86-7f03-4f71-aaf9-9031102e7969
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249008909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.4249008909
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2715257821
Short name T718
Test name
Test status
Simulation time 4076217881 ps
CPU time 10.32 seconds
Started Jul 06 06:00:23 PM PDT 24
Finished Jul 06 06:00:33 PM PDT 24
Peak memory 198100 kb
Host smart-3f8f9853-290c-436b-adf5-604db1364ea5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715257821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2715257821
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.79496340
Short name T142
Test name
Test status
Simulation time 21492071316 ps
CPU time 25.45 seconds
Started Jul 06 06:00:25 PM PDT 24
Finished Jul 06 06:00:51 PM PDT 24
Peak memory 199860 kb
Host smart-95932b56-0403-4c07-b32a-bb2bddf721b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79496340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.79496340
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2727806053
Short name T1128
Test name
Test status
Simulation time 4678167103 ps
CPU time 1.38 seconds
Started Jul 06 06:00:23 PM PDT 24
Finished Jul 06 06:00:25 PM PDT 24
Peak memory 196372 kb
Host smart-051dbc49-fa36-4ff9-9131-c807a7581345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727806053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2727806053
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3063695442
Short name T430
Test name
Test status
Simulation time 5990890238 ps
CPU time 21.69 seconds
Started Jul 06 06:00:21 PM PDT 24
Finished Jul 06 06:00:43 PM PDT 24
Peak memory 199868 kb
Host smart-5659ee3e-9889-429a-b94a-15f704983805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063695442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3063695442
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.4148512752
Short name T849
Test name
Test status
Simulation time 32901892670 ps
CPU time 48.58 seconds
Started Jul 06 06:00:28 PM PDT 24
Finished Jul 06 06:01:16 PM PDT 24
Peak memory 199812 kb
Host smart-08b78b11-513d-4354-8afd-cf573a0f7ba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148512752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.4148512752
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2500377602
Short name T793
Test name
Test status
Simulation time 83606541746 ps
CPU time 1553.98 seconds
Started Jul 06 06:00:26 PM PDT 24
Finished Jul 06 06:26:20 PM PDT 24
Peak memory 225932 kb
Host smart-985c6bbe-5b69-434e-bee5-69ac1477bd2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500377602 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2500377602
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1635814573
Short name T495
Test name
Test status
Simulation time 2580669492 ps
CPU time 2.92 seconds
Started Jul 06 06:00:28 PM PDT 24
Finished Jul 06 06:00:31 PM PDT 24
Peak memory 199544 kb
Host smart-4424af64-2ea2-4cea-b77c-cf78f7ff9280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635814573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1635814573
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3439974295
Short name T4
Test name
Test status
Simulation time 24927004012 ps
CPU time 47.26 seconds
Started Jul 06 06:00:23 PM PDT 24
Finished Jul 06 06:01:10 PM PDT 24
Peak memory 199972 kb
Host smart-d90fe813-c392-4d16-ab16-9bb0ccbed06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439974295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3439974295
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.91694460
Short name T397
Test name
Test status
Simulation time 12603551 ps
CPU time 0.56 seconds
Started Jul 06 06:00:30 PM PDT 24
Finished Jul 06 06:00:31 PM PDT 24
Peak memory 195276 kb
Host smart-e3e3b04f-52b9-43e8-a22f-a2cc8d7bbdb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91694460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.91694460
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2325870993
Short name T700
Test name
Test status
Simulation time 288990619251 ps
CPU time 86.92 seconds
Started Jul 06 06:00:28 PM PDT 24
Finished Jul 06 06:01:55 PM PDT 24
Peak memory 200008 kb
Host smart-3f23c8f7-60f1-4f87-8fae-48a59e25521f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325870993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2325870993
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2631894085
Short name T792
Test name
Test status
Simulation time 98293012775 ps
CPU time 298.04 seconds
Started Jul 06 06:00:25 PM PDT 24
Finished Jul 06 06:05:23 PM PDT 24
Peak memory 200008 kb
Host smart-410a5aa3-e07d-484b-903d-3abc3e3d1093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631894085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2631894085
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1006611257
Short name T153
Test name
Test status
Simulation time 16240118940 ps
CPU time 27.81 seconds
Started Jul 06 06:00:25 PM PDT 24
Finished Jul 06 06:00:53 PM PDT 24
Peak memory 199868 kb
Host smart-14b373b6-37b8-48c9-ab85-a603635a4f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006611257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1006611257
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.116465295
Short name T635
Test name
Test status
Simulation time 15804287805 ps
CPU time 18.19 seconds
Started Jul 06 06:00:25 PM PDT 24
Finished Jul 06 06:00:44 PM PDT 24
Peak memory 199948 kb
Host smart-6cbfa9f9-045c-4bf0-8905-f5a0440c4ff9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116465295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.116465295
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1749277616
Short name T394
Test name
Test status
Simulation time 123262652343 ps
CPU time 318.97 seconds
Started Jul 06 06:00:31 PM PDT 24
Finished Jul 06 06:05:50 PM PDT 24
Peak memory 199956 kb
Host smart-74358653-d474-4c06-9fef-57c3a47e0802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749277616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1749277616
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3444060803
Short name T1113
Test name
Test status
Simulation time 8342305143 ps
CPU time 8.39 seconds
Started Jul 06 06:00:30 PM PDT 24
Finished Jul 06 06:00:38 PM PDT 24
Peak memory 199848 kb
Host smart-29d7d2f3-3fe7-435d-9780-73a4bed01f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444060803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3444060803
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2549566109
Short name T750
Test name
Test status
Simulation time 70080934561 ps
CPU time 64.73 seconds
Started Jul 06 06:00:26 PM PDT 24
Finished Jul 06 06:01:31 PM PDT 24
Peak memory 198332 kb
Host smart-1b703f42-89e8-49ca-b964-e98cccef3958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549566109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2549566109
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3248457237
Short name T722
Test name
Test status
Simulation time 21612686773 ps
CPU time 1038.71 seconds
Started Jul 06 06:00:31 PM PDT 24
Finished Jul 06 06:17:50 PM PDT 24
Peak memory 199880 kb
Host smart-9f30597a-a0a7-44a6-a37a-437b386353a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248457237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3248457237
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3500412354
Short name T361
Test name
Test status
Simulation time 6849383084 ps
CPU time 59.65 seconds
Started Jul 06 06:00:27 PM PDT 24
Finished Jul 06 06:01:26 PM PDT 24
Peak memory 199156 kb
Host smart-89ce9f29-53a1-4fd3-98a1-833fddccd18a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500412354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3500412354
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3200575347
Short name T1043
Test name
Test status
Simulation time 18861616655 ps
CPU time 32.29 seconds
Started Jul 06 06:00:31 PM PDT 24
Finished Jul 06 06:01:03 PM PDT 24
Peak memory 199932 kb
Host smart-00b71e60-cad7-4a9b-b2a1-40185c3ee095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200575347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3200575347
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4049797465
Short name T415
Test name
Test status
Simulation time 2076003890 ps
CPU time 1.47 seconds
Started Jul 06 06:00:30 PM PDT 24
Finished Jul 06 06:00:31 PM PDT 24
Peak memory 195376 kb
Host smart-15098f95-c95c-407c-ae8c-0ad1b25996e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049797465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4049797465
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1193972293
Short name T327
Test name
Test status
Simulation time 5334791093 ps
CPU time 13.74 seconds
Started Jul 06 06:00:30 PM PDT 24
Finished Jul 06 06:00:44 PM PDT 24
Peak memory 199888 kb
Host smart-7f5bc29e-5b09-4791-b08f-4638e2b8b4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193972293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1193972293
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1357106338
Short name T948
Test name
Test status
Simulation time 87478792598 ps
CPU time 477.8 seconds
Started Jul 06 06:00:28 PM PDT 24
Finished Jul 06 06:08:26 PM PDT 24
Peak memory 199928 kb
Host smart-ef3ab6bb-0a21-46a0-8661-083d803d6f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357106338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1357106338
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1066574887
Short name T33
Test name
Test status
Simulation time 1088151857 ps
CPU time 1.46 seconds
Started Jul 06 06:00:32 PM PDT 24
Finished Jul 06 06:00:34 PM PDT 24
Peak memory 196580 kb
Host smart-84f47eb2-0a60-4950-bd33-e5f375ad66b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066574887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1066574887
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_alert_test.2704408494
Short name T697
Test name
Test status
Simulation time 43840022 ps
CPU time 0.55 seconds
Started Jul 06 06:00:39 PM PDT 24
Finished Jul 06 06:00:40 PM PDT 24
Peak memory 195352 kb
Host smart-da39e886-474a-4125-b67e-228ef6fc2f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704408494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2704408494
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2644892017
Short name T789
Test name
Test status
Simulation time 109438558996 ps
CPU time 42.32 seconds
Started Jul 06 06:00:37 PM PDT 24
Finished Jul 06 06:01:19 PM PDT 24
Peak memory 199908 kb
Host smart-db4dd01b-dbe7-4586-9a7d-5ec5c805e1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644892017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2644892017
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.3412350649
Short name T665
Test name
Test status
Simulation time 105244117047 ps
CPU time 143.21 seconds
Started Jul 06 06:00:37 PM PDT 24
Finished Jul 06 06:03:00 PM PDT 24
Peak memory 199768 kb
Host smart-03f9153f-5b68-4c60-937c-8a611514de79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412350649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3412350649
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.494999481
Short name T978
Test name
Test status
Simulation time 23406112584 ps
CPU time 13.68 seconds
Started Jul 06 06:00:36 PM PDT 24
Finished Jul 06 06:00:50 PM PDT 24
Peak memory 199972 kb
Host smart-6a24d975-ce8b-4204-861f-fa11c88677af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494999481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.494999481
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.401470947
Short name T854
Test name
Test status
Simulation time 20010738232 ps
CPU time 9.23 seconds
Started Jul 06 06:00:35 PM PDT 24
Finished Jul 06 06:00:45 PM PDT 24
Peak memory 197704 kb
Host smart-11818370-9f2f-4f7c-8790-cdb776549e3a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401470947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.401470947
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2686090572
Short name T1131
Test name
Test status
Simulation time 131573231500 ps
CPU time 252.35 seconds
Started Jul 06 06:00:42 PM PDT 24
Finished Jul 06 06:04:55 PM PDT 24
Peak memory 199864 kb
Host smart-6f9466bf-c19b-4375-9768-738557e1b041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2686090572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2686090572
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1342896833
Short name T997
Test name
Test status
Simulation time 6217008131 ps
CPU time 10.43 seconds
Started Jul 06 06:00:42 PM PDT 24
Finished Jul 06 06:00:53 PM PDT 24
Peak memory 196688 kb
Host smart-345b7a75-3b39-4914-9a57-a8fc2b5d4374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342896833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1342896833
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2357034474
Short name T1059
Test name
Test status
Simulation time 134253435899 ps
CPU time 242.49 seconds
Started Jul 06 06:00:41 PM PDT 24
Finished Jul 06 06:04:44 PM PDT 24
Peak memory 208340 kb
Host smart-b914b033-9b7b-43ab-90d5-045eb530fb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357034474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2357034474
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1597258416
Short name T563
Test name
Test status
Simulation time 19901219278 ps
CPU time 1081.82 seconds
Started Jul 06 06:00:42 PM PDT 24
Finished Jul 06 06:18:44 PM PDT 24
Peak memory 199932 kb
Host smart-21248577-4914-455c-9761-34eb0da6539e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597258416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1597258416
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3467318953
Short name T842
Test name
Test status
Simulation time 6094692826 ps
CPU time 27.75 seconds
Started Jul 06 06:00:37 PM PDT 24
Finished Jul 06 06:01:05 PM PDT 24
Peak memory 198772 kb
Host smart-711bc59c-8e5b-4812-8f8b-40ab804058c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3467318953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3467318953
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.4278268371
Short name T313
Test name
Test status
Simulation time 321479156125 ps
CPU time 132.9 seconds
Started Jul 06 06:00:42 PM PDT 24
Finished Jul 06 06:02:55 PM PDT 24
Peak memory 199896 kb
Host smart-ad6fe2ce-085b-4388-ad0e-361d5512022b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278268371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.4278268371
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1736256836
Short name T888
Test name
Test status
Simulation time 2783059519 ps
CPU time 1.04 seconds
Started Jul 06 06:00:40 PM PDT 24
Finished Jul 06 06:00:42 PM PDT 24
Peak memory 195736 kb
Host smart-5fc2de93-80d3-4c0e-beea-2b24c70ff424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736256836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1736256836
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3609213239
Short name T302
Test name
Test status
Simulation time 6100038159 ps
CPU time 7.18 seconds
Started Jul 06 06:00:32 PM PDT 24
Finished Jul 06 06:00:40 PM PDT 24
Peak memory 199876 kb
Host smart-2a8caa06-aa53-4c8b-8c99-186ccf1e8ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609213239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3609213239
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3653538585
Short name T123
Test name
Test status
Simulation time 383713536335 ps
CPU time 327.76 seconds
Started Jul 06 06:00:41 PM PDT 24
Finished Jul 06 06:06:09 PM PDT 24
Peak memory 199992 kb
Host smart-ed373202-def1-4e2a-9815-7e6b9dc8d598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653538585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3653538585
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.222566146
Short name T26
Test name
Test status
Simulation time 38635048280 ps
CPU time 169.3 seconds
Started Jul 06 06:00:41 PM PDT 24
Finished Jul 06 06:03:30 PM PDT 24
Peak memory 208228 kb
Host smart-553dc9ea-e8e2-4c86-a885-577b3ac53f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222566146 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.222566146
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1708319237
Short name T1115
Test name
Test status
Simulation time 594498164 ps
CPU time 1.97 seconds
Started Jul 06 06:00:41 PM PDT 24
Finished Jul 06 06:00:44 PM PDT 24
Peak memory 198268 kb
Host smart-7c54d09e-23a5-4e33-b20f-98c056ff48b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708319237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1708319237
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3217433462
Short name T790
Test name
Test status
Simulation time 56917893754 ps
CPU time 93.79 seconds
Started Jul 06 06:00:53 PM PDT 24
Finished Jul 06 06:02:27 PM PDT 24
Peak memory 199984 kb
Host smart-f1dbbf4c-de4f-467f-b693-083824f76a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217433462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3217433462
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2682376697
Short name T914
Test name
Test status
Simulation time 13025932 ps
CPU time 0.54 seconds
Started Jul 06 06:00:46 PM PDT 24
Finished Jul 06 06:00:47 PM PDT 24
Peak memory 194316 kb
Host smart-2affb843-5b67-4636-88b5-52b145019810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682376697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2682376697
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3161625675
Short name T1143
Test name
Test status
Simulation time 189954111927 ps
CPU time 289.13 seconds
Started Jul 06 06:00:41 PM PDT 24
Finished Jul 06 06:05:30 PM PDT 24
Peak memory 199916 kb
Host smart-f1f9e988-8dfa-4351-b26a-104e5d68fcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161625675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3161625675
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1611102792
Short name T307
Test name
Test status
Simulation time 80215136006 ps
CPU time 91.39 seconds
Started Jul 06 06:00:42 PM PDT 24
Finished Jul 06 06:02:13 PM PDT 24
Peak memory 200016 kb
Host smart-65bc6ee9-f528-40ac-87d9-9ba42a0ebffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611102792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1611102792
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1904792560
Short name T699
Test name
Test status
Simulation time 60442836393 ps
CPU time 48.4 seconds
Started Jul 06 06:00:42 PM PDT 24
Finished Jul 06 06:01:31 PM PDT 24
Peak memory 200012 kb
Host smart-c4111f06-5fb7-4b8a-a161-779585133bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904792560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1904792560
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.681985982
Short name T695
Test name
Test status
Simulation time 27528016055 ps
CPU time 10.74 seconds
Started Jul 06 06:00:42 PM PDT 24
Finished Jul 06 06:00:53 PM PDT 24
Peak memory 198588 kb
Host smart-139f33b2-c779-4b94-934f-7e2bf9a9939d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681985982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.681985982
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1905569290
Short name T717
Test name
Test status
Simulation time 156773908859 ps
CPU time 134.9 seconds
Started Jul 06 06:00:48 PM PDT 24
Finished Jul 06 06:03:03 PM PDT 24
Peak memory 199916 kb
Host smart-f44437a3-2f23-4b9a-883b-11658e438c20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1905569290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1905569290
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3221834119
Short name T943
Test name
Test status
Simulation time 2791066598 ps
CPU time 4.19 seconds
Started Jul 06 06:00:40 PM PDT 24
Finished Jul 06 06:00:45 PM PDT 24
Peak memory 199868 kb
Host smart-5c049cd9-2cf9-4ea5-a646-e95ffce4d397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221834119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3221834119
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2051896660
Short name T870
Test name
Test status
Simulation time 53592784343 ps
CPU time 90.78 seconds
Started Jul 06 06:00:41 PM PDT 24
Finished Jul 06 06:02:13 PM PDT 24
Peak memory 199136 kb
Host smart-09d5e13d-5eb1-401c-8b8c-763eae80e64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051896660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2051896660
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3478725802
Short name T401
Test name
Test status
Simulation time 7062797428 ps
CPU time 306.22 seconds
Started Jul 06 06:00:43 PM PDT 24
Finished Jul 06 06:05:49 PM PDT 24
Peak memory 200024 kb
Host smart-f165636d-276a-4438-983b-f6483732e8e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478725802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3478725802
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1232185684
Short name T806
Test name
Test status
Simulation time 4732317482 ps
CPU time 8.44 seconds
Started Jul 06 06:00:42 PM PDT 24
Finished Jul 06 06:00:51 PM PDT 24
Peak memory 199452 kb
Host smart-eda741fa-2c86-4abb-bb9b-7d7f1f649e70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232185684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1232185684
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.48538537
Short name T157
Test name
Test status
Simulation time 60073848317 ps
CPU time 22.62 seconds
Started Jul 06 06:00:41 PM PDT 24
Finished Jul 06 06:01:04 PM PDT 24
Peak memory 199992 kb
Host smart-5aa2e9f1-b248-4aff-8a35-c53b14314e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48538537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.48538537
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1048387851
Short name T1062
Test name
Test status
Simulation time 40553259950 ps
CPU time 32.62 seconds
Started Jul 06 06:00:40 PM PDT 24
Finished Jul 06 06:01:13 PM PDT 24
Peak memory 195808 kb
Host smart-65c04ba8-c192-4134-94fa-9fda8b4b6c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048387851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1048387851
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2635177271
Short name T449
Test name
Test status
Simulation time 6251120033 ps
CPU time 5.32 seconds
Started Jul 06 06:00:41 PM PDT 24
Finished Jul 06 06:00:46 PM PDT 24
Peak memory 199868 kb
Host smart-7c5b9206-a70b-4378-8efd-6b9c36286421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635177271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2635177271
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.881941027
Short name T167
Test name
Test status
Simulation time 207189563523 ps
CPU time 327.42 seconds
Started Jul 06 06:00:46 PM PDT 24
Finished Jul 06 06:06:14 PM PDT 24
Peak memory 200004 kb
Host smart-bb9874ff-4efc-438a-bec1-6eab413dbc36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881941027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.881941027
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.590060886
Short name T338
Test name
Test status
Simulation time 149504360868 ps
CPU time 798.53 seconds
Started Jul 06 06:00:47 PM PDT 24
Finished Jul 06 06:14:06 PM PDT 24
Peak memory 216452 kb
Host smart-a2f0634e-3a62-4cd9-a6c0-c37e17e022e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590060886 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.590060886
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.10343077
Short name T730
Test name
Test status
Simulation time 861200609 ps
CPU time 3.04 seconds
Started Jul 06 06:00:41 PM PDT 24
Finished Jul 06 06:00:44 PM PDT 24
Peak memory 199548 kb
Host smart-315bc0f7-bd0d-4d61-b05e-862eb7627655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10343077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.10343077
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.760964723
Short name T336
Test name
Test status
Simulation time 13235414702 ps
CPU time 21.47 seconds
Started Jul 06 06:00:41 PM PDT 24
Finished Jul 06 06:01:03 PM PDT 24
Peak memory 199972 kb
Host smart-7f2ab7cb-eaaa-437a-9fa6-d2d81a57d6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760964723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.760964723
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.926621741
Short name T949
Test name
Test status
Simulation time 41300647 ps
CPU time 0.59 seconds
Started Jul 06 05:57:10 PM PDT 24
Finished Jul 06 05:57:11 PM PDT 24
Peak memory 195628 kb
Host smart-3913491f-1672-4adf-853e-9cd09f4df83c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926621741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.926621741
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3941883377
Short name T399
Test name
Test status
Simulation time 158387240702 ps
CPU time 47.3 seconds
Started Jul 06 05:57:04 PM PDT 24
Finished Jul 06 05:57:51 PM PDT 24
Peak memory 199940 kb
Host smart-ce85b9a0-e69e-4c14-b099-1dbebc933c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941883377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3941883377
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.134155645
Short name T109
Test name
Test status
Simulation time 177714854763 ps
CPU time 127.69 seconds
Started Jul 06 05:57:05 PM PDT 24
Finished Jul 06 05:59:13 PM PDT 24
Peak memory 199976 kb
Host smart-610f1915-e3f4-4125-8cd6-bac761bc273c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134155645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.134155645
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3901098959
Short name T1079
Test name
Test status
Simulation time 145544931154 ps
CPU time 97.91 seconds
Started Jul 06 05:57:05 PM PDT 24
Finished Jul 06 05:58:44 PM PDT 24
Peak memory 199988 kb
Host smart-f315eadb-6940-4386-8661-931cfd5e72a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901098959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3901098959
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.617619847
Short name T472
Test name
Test status
Simulation time 96412353082 ps
CPU time 353.98 seconds
Started Jul 06 05:57:07 PM PDT 24
Finished Jul 06 06:03:01 PM PDT 24
Peak memory 200012 kb
Host smart-bdae73e0-50e8-437a-8a2b-2c35296cfec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617619847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.617619847
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.714203843
Short name T357
Test name
Test status
Simulation time 5338813479 ps
CPU time 16.82 seconds
Started Jul 06 05:57:04 PM PDT 24
Finished Jul 06 05:57:21 PM PDT 24
Peak memory 198556 kb
Host smart-df75c824-d588-49c7-be14-40542ac75ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714203843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.714203843
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2295669305
Short name T599
Test name
Test status
Simulation time 22281666810 ps
CPU time 39.4 seconds
Started Jul 06 05:57:05 PM PDT 24
Finished Jul 06 05:57:44 PM PDT 24
Peak memory 200108 kb
Host smart-cc3a8cb6-3c3b-4982-8709-c909cac1fd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295669305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2295669305
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.452124585
Short name T507
Test name
Test status
Simulation time 7844706130 ps
CPU time 435.07 seconds
Started Jul 06 05:57:05 PM PDT 24
Finished Jul 06 06:04:21 PM PDT 24
Peak memory 200020 kb
Host smart-7a0275fd-8638-47dd-93d5-707dd55e9205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=452124585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.452124585
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.313135054
Short name T496
Test name
Test status
Simulation time 2942332872 ps
CPU time 5.09 seconds
Started Jul 06 05:57:05 PM PDT 24
Finished Jul 06 05:57:11 PM PDT 24
Peak memory 198848 kb
Host smart-9a5424a5-3f84-4d8d-85a4-c90d6bc24094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313135054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.313135054
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.443599233
Short name T713
Test name
Test status
Simulation time 40526030463 ps
CPU time 13.65 seconds
Started Jul 06 05:57:08 PM PDT 24
Finished Jul 06 05:57:22 PM PDT 24
Peak memory 198588 kb
Host smart-68e25f8a-e7e6-4032-a1cb-210cb040d7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443599233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.443599233
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2042558743
Short name T844
Test name
Test status
Simulation time 2881418186 ps
CPU time 1.5 seconds
Started Jul 06 05:57:09 PM PDT 24
Finished Jul 06 05:57:11 PM PDT 24
Peak memory 195984 kb
Host smart-52edc3f5-c0ea-48d5-8e2e-9a9d4f0e2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042558743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2042558743
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1198714263
Short name T1124
Test name
Test status
Simulation time 937142823 ps
CPU time 2.62 seconds
Started Jul 06 05:57:05 PM PDT 24
Finished Jul 06 05:57:08 PM PDT 24
Peak memory 198336 kb
Host smart-213aeaeb-eaf9-46d4-b95f-5320dc22eff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198714263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1198714263
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1839311740
Short name T724
Test name
Test status
Simulation time 359235107843 ps
CPU time 394.11 seconds
Started Jul 06 05:57:03 PM PDT 24
Finished Jul 06 06:03:38 PM PDT 24
Peak memory 200004 kb
Host smart-57c75f06-c707-4aa9-b561-4fe64ab49752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839311740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1839311740
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2821195065
Short name T1174
Test name
Test status
Simulation time 41700028109 ps
CPU time 186.26 seconds
Started Jul 06 05:57:08 PM PDT 24
Finished Jul 06 06:00:15 PM PDT 24
Peak memory 215912 kb
Host smart-b5c40860-ff7b-4e07-8b58-86974f9cea3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821195065 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2821195065
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2258296799
Short name T684
Test name
Test status
Simulation time 1854130903 ps
CPU time 1.67 seconds
Started Jul 06 05:57:09 PM PDT 24
Finished Jul 06 05:57:11 PM PDT 24
Peak memory 198400 kb
Host smart-ad3abadb-c19f-4f49-a0c2-4e295d50d048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258296799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2258296799
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2660023549
Short name T745
Test name
Test status
Simulation time 20453359859 ps
CPU time 27.82 seconds
Started Jul 06 05:57:07 PM PDT 24
Finished Jul 06 05:57:35 PM PDT 24
Peak memory 199956 kb
Host smart-9277860f-0919-458a-b056-78219b629920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660023549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2660023549
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1209330215
Short name T912
Test name
Test status
Simulation time 44721367115 ps
CPU time 526.23 seconds
Started Jul 06 06:00:47 PM PDT 24
Finished Jul 06 06:09:33 PM PDT 24
Peak memory 216668 kb
Host smart-8aef61d7-867b-4fcb-92fc-9e7e2143d9e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209330215 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1209330215
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2088396932
Short name T661
Test name
Test status
Simulation time 42389087794 ps
CPU time 80.89 seconds
Started Jul 06 06:00:47 PM PDT 24
Finished Jul 06 06:02:08 PM PDT 24
Peak memory 199840 kb
Host smart-5bf821e2-d7bd-4a75-aa04-e1b6c88961d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088396932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2088396932
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2463385283
Short name T152
Test name
Test status
Simulation time 39445686141 ps
CPU time 60.34 seconds
Started Jul 06 06:00:45 PM PDT 24
Finished Jul 06 06:01:46 PM PDT 24
Peak memory 199932 kb
Host smart-24738910-1845-4016-93f2-58c089ee73d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463385283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2463385283
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3691685484
Short name T768
Test name
Test status
Simulation time 601202170138 ps
CPU time 670.27 seconds
Started Jul 06 06:00:47 PM PDT 24
Finished Jul 06 06:11:57 PM PDT 24
Peak memory 216436 kb
Host smart-f611528b-8631-4519-bbcd-f6f36f63d77b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691685484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3691685484
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.488071159
Short name T236
Test name
Test status
Simulation time 143926737145 ps
CPU time 45.47 seconds
Started Jul 06 06:00:46 PM PDT 24
Finished Jul 06 06:01:32 PM PDT 24
Peak memory 199992 kb
Host smart-86969f14-60d8-485f-bf6c-675555956ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488071159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.488071159
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1641627461
Short name T694
Test name
Test status
Simulation time 80617385379 ps
CPU time 534.24 seconds
Started Jul 06 06:00:47 PM PDT 24
Finished Jul 06 06:09:41 PM PDT 24
Peak memory 216496 kb
Host smart-095a327e-0df6-452c-a29c-b74f334190a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641627461 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1641627461
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2167172624
Short name T861
Test name
Test status
Simulation time 82432926402 ps
CPU time 33.11 seconds
Started Jul 06 06:00:45 PM PDT 24
Finished Jul 06 06:01:19 PM PDT 24
Peak memory 199876 kb
Host smart-683b02e1-41ce-4034-b641-830189eaf615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167172624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2167172624
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.662458093
Short name T652
Test name
Test status
Simulation time 89722522303 ps
CPU time 252.56 seconds
Started Jul 06 06:00:47 PM PDT 24
Finished Jul 06 06:05:00 PM PDT 24
Peak memory 214832 kb
Host smart-3b6b4f42-2d73-40ac-b410-9999c4564450
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662458093 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.662458093
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.4163519478
Short name T508
Test name
Test status
Simulation time 108913573349 ps
CPU time 40.34 seconds
Started Jul 06 06:00:52 PM PDT 24
Finished Jul 06 06:01:32 PM PDT 24
Peak memory 199916 kb
Host smart-7f099c2e-96da-4d03-b446-d966db4de97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163519478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.4163519478
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1085050368
Short name T190
Test name
Test status
Simulation time 28328432412 ps
CPU time 46.03 seconds
Started Jul 06 06:00:54 PM PDT 24
Finished Jul 06 06:01:41 PM PDT 24
Peak memory 200000 kb
Host smart-c4c46f43-c2ff-4a63-a5f7-f9a3db31fb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085050368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1085050368
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3688322102
Short name T701
Test name
Test status
Simulation time 56106566788 ps
CPU time 64.21 seconds
Started Jul 06 06:00:53 PM PDT 24
Finished Jul 06 06:01:57 PM PDT 24
Peak memory 199980 kb
Host smart-cfef6dc0-527f-4a68-8b68-21056fd41f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688322102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3688322102
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3211710596
Short name T55
Test name
Test status
Simulation time 275747996098 ps
CPU time 778.7 seconds
Started Jul 06 06:00:50 PM PDT 24
Finished Jul 06 06:13:50 PM PDT 24
Peak memory 230520 kb
Host smart-2bdcf844-2212-4920-b2f8-b98f68ec5bdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211710596 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3211710596
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.4263588357
Short name T163
Test name
Test status
Simulation time 919691988465 ps
CPU time 712.96 seconds
Started Jul 06 06:00:50 PM PDT 24
Finished Jul 06 06:12:44 PM PDT 24
Peak memory 224936 kb
Host smart-220f4a62-edd8-4e09-a958-0aaf50ee046c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263588357 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.4263588357
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1027617959
Short name T154
Test name
Test status
Simulation time 38441794706 ps
CPU time 12.7 seconds
Started Jul 06 06:00:51 PM PDT 24
Finished Jul 06 06:01:04 PM PDT 24
Peak memory 199932 kb
Host smart-ede5f8ea-60d8-4f49-8c0d-065000470d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027617959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1027617959
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1261020837
Short name T523
Test name
Test status
Simulation time 99427621005 ps
CPU time 558.97 seconds
Started Jul 06 06:00:52 PM PDT 24
Finished Jul 06 06:10:11 PM PDT 24
Peak memory 224836 kb
Host smart-1da2cc52-4608-44cd-a36b-05c02175764d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261020837 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1261020837
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.4069180265
Short name T606
Test name
Test status
Simulation time 32774355 ps
CPU time 0.58 seconds
Started Jul 06 05:57:11 PM PDT 24
Finished Jul 06 05:57:12 PM PDT 24
Peak memory 195264 kb
Host smart-08d76951-6720-4f2e-bba4-2fcde593e7ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069180265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.4069180265
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1183019721
Short name T425
Test name
Test status
Simulation time 24411082119 ps
CPU time 37.88 seconds
Started Jul 06 05:57:07 PM PDT 24
Finished Jul 06 05:57:46 PM PDT 24
Peak memory 199980 kb
Host smart-a9f07ab6-2616-4bb0-a65d-ec237e1c3f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183019721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1183019721
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.876175947
Short name T539
Test name
Test status
Simulation time 238880738779 ps
CPU time 71.82 seconds
Started Jul 06 05:57:05 PM PDT 24
Finished Jul 06 05:58:17 PM PDT 24
Peak memory 199952 kb
Host smart-f760034d-f9f8-4c5a-8e02-60278c533854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876175947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.876175947
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.301747523
Short name T837
Test name
Test status
Simulation time 123481285252 ps
CPU time 54.06 seconds
Started Jul 06 05:57:08 PM PDT 24
Finished Jul 06 05:58:03 PM PDT 24
Peak memory 200256 kb
Host smart-a0f777fe-130b-49fe-9d8b-519fb62ac460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301747523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.301747523
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2982063817
Short name T12
Test name
Test status
Simulation time 55961851720 ps
CPU time 26.49 seconds
Started Jul 06 05:57:08 PM PDT 24
Finished Jul 06 05:57:35 PM PDT 24
Peak memory 199996 kb
Host smart-8b95cee3-1755-4cfe-a289-6ac8c0445d07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982063817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2982063817
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1196452744
Short name T638
Test name
Test status
Simulation time 105143876551 ps
CPU time 330.51 seconds
Started Jul 06 05:57:10 PM PDT 24
Finished Jul 06 06:02:41 PM PDT 24
Peak memory 199984 kb
Host smart-1a9a0efb-45c8-4d3e-85de-3f33958010a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1196452744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1196452744
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1362792588
Short name T1047
Test name
Test status
Simulation time 599469687 ps
CPU time 0.68 seconds
Started Jul 06 05:57:24 PM PDT 24
Finished Jul 06 05:57:25 PM PDT 24
Peak memory 195528 kb
Host smart-55575cf3-3f1f-468f-ac01-394cca7a33ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362792588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1362792588
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.829239355
Short name T1048
Test name
Test status
Simulation time 151334771475 ps
CPU time 77.35 seconds
Started Jul 06 05:57:10 PM PDT 24
Finished Jul 06 05:58:28 PM PDT 24
Peak memory 198716 kb
Host smart-7c518ae0-4b6e-42ad-bb96-68b65980aa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829239355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.829239355
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.4044976477
Short name T797
Test name
Test status
Simulation time 19024618917 ps
CPU time 239.74 seconds
Started Jul 06 05:57:09 PM PDT 24
Finished Jul 06 06:01:09 PM PDT 24
Peak memory 199940 kb
Host smart-2870ba9d-1f88-4d07-856d-b440ab0e2608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044976477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4044976477
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.904250405
Short name T896
Test name
Test status
Simulation time 7067326077 ps
CPU time 35.4 seconds
Started Jul 06 05:57:09 PM PDT 24
Finished Jul 06 05:57:45 PM PDT 24
Peak memory 198172 kb
Host smart-83a700ae-ea60-4dbe-894c-478a7a8ed2df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=904250405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.904250405
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2296903904
Short name T1057
Test name
Test status
Simulation time 61310768760 ps
CPU time 14.81 seconds
Started Jul 06 05:57:12 PM PDT 24
Finished Jul 06 05:57:27 PM PDT 24
Peak memory 198204 kb
Host smart-4a643b47-48f3-424f-806d-07f4260d5865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296903904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2296903904
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1414643488
Short name T553
Test name
Test status
Simulation time 3454671374 ps
CPU time 1.85 seconds
Started Jul 06 05:57:09 PM PDT 24
Finished Jul 06 05:57:11 PM PDT 24
Peak memory 196000 kb
Host smart-fcd75516-1699-4c38-b9eb-931b3667bcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414643488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1414643488
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.304305786
Short name T547
Test name
Test status
Simulation time 6337250844 ps
CPU time 21.02 seconds
Started Jul 06 05:57:04 PM PDT 24
Finished Jul 06 05:57:25 PM PDT 24
Peak memory 199516 kb
Host smart-276b6644-a4c3-4712-a8c9-14e1986dd503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304305786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.304305786
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.162727655
Short name T1022
Test name
Test status
Simulation time 72817027874 ps
CPU time 197.44 seconds
Started Jul 06 05:57:12 PM PDT 24
Finished Jul 06 06:00:30 PM PDT 24
Peak memory 216436 kb
Host smart-061466c4-e3ff-4e75-a0eb-35fad853f35b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162727655 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.162727655
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.367119871
Short name T28
Test name
Test status
Simulation time 500480513 ps
CPU time 1.08 seconds
Started Jul 06 05:57:09 PM PDT 24
Finished Jul 06 05:57:10 PM PDT 24
Peak memory 197536 kb
Host smart-4ff58fab-4309-432a-8a45-f68d118e32d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367119871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.367119871
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.642762094
Short name T317
Test name
Test status
Simulation time 113886569939 ps
CPU time 158.55 seconds
Started Jul 06 05:57:04 PM PDT 24
Finished Jul 06 05:59:42 PM PDT 24
Peak memory 199940 kb
Host smart-351fb84d-ee4b-488f-b9d1-fbe454e56b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642762094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.642762094
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.591251228
Short name T521
Test name
Test status
Simulation time 165634294035 ps
CPU time 169.68 seconds
Started Jul 06 06:00:51 PM PDT 24
Finished Jul 06 06:03:41 PM PDT 24
Peak memory 199928 kb
Host smart-2f2b968b-5c73-4959-88a7-19732d4f3741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591251228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.591251228
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.564894160
Short name T23
Test name
Test status
Simulation time 16575504333 ps
CPU time 199.65 seconds
Started Jul 06 06:00:51 PM PDT 24
Finished Jul 06 06:04:11 PM PDT 24
Peak memory 216008 kb
Host smart-ea82267d-74e0-48a2-8f77-bfa1503a5757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564894160 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.564894160
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3688607971
Short name T583
Test name
Test status
Simulation time 213951778521 ps
CPU time 149.37 seconds
Started Jul 06 06:00:54 PM PDT 24
Finished Jul 06 06:03:23 PM PDT 24
Peak memory 199996 kb
Host smart-a3c1682e-3498-441d-9639-6367361afe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688607971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3688607971
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2957868811
Short name T944
Test name
Test status
Simulation time 42105146468 ps
CPU time 533.99 seconds
Started Jul 06 06:00:53 PM PDT 24
Finished Jul 06 06:09:47 PM PDT 24
Peak memory 227652 kb
Host smart-85d82fe5-c667-45e4-b5d1-e29aca46c563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957868811 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2957868811
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2650259658
Short name T1152
Test name
Test status
Simulation time 88113891373 ps
CPU time 256.3 seconds
Started Jul 06 06:00:52 PM PDT 24
Finished Jul 06 06:05:08 PM PDT 24
Peak memory 200048 kb
Host smart-b2e42fe9-1a4b-4d9e-8778-4e573d997c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650259658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2650259658
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1710521608
Short name T117
Test name
Test status
Simulation time 25127553508 ps
CPU time 141.21 seconds
Started Jul 06 06:00:53 PM PDT 24
Finished Jul 06 06:03:15 PM PDT 24
Peak memory 208320 kb
Host smart-3b69d49f-2f45-4ce2-9d66-e2b811896b35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710521608 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1710521608
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2412442311
Short name T186
Test name
Test status
Simulation time 161548834077 ps
CPU time 65.22 seconds
Started Jul 06 06:00:53 PM PDT 24
Finished Jul 06 06:01:58 PM PDT 24
Peak memory 199948 kb
Host smart-ea8a728c-8534-4ac7-ab3b-7f3ff1154501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412442311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2412442311
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3163138622
Short name T1002
Test name
Test status
Simulation time 114848483089 ps
CPU time 48.43 seconds
Started Jul 06 06:00:52 PM PDT 24
Finished Jul 06 06:01:41 PM PDT 24
Peak memory 200032 kb
Host smart-6b4d3ee9-053c-4e41-abbb-6f1661db383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163138622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3163138622
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1705931020
Short name T678
Test name
Test status
Simulation time 25092419069 ps
CPU time 218.98 seconds
Started Jul 06 06:00:51 PM PDT 24
Finished Jul 06 06:04:30 PM PDT 24
Peak memory 216728 kb
Host smart-53b8b341-2b32-4d5c-b922-c0b6618c693a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705931020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1705931020
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3350006957
Short name T1038
Test name
Test status
Simulation time 72811479766 ps
CPU time 30.08 seconds
Started Jul 06 06:00:50 PM PDT 24
Finished Jul 06 06:01:20 PM PDT 24
Peak memory 199960 kb
Host smart-6aa982bf-67bd-4739-847c-269ddf479db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350006957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3350006957
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3254265180
Short name T588
Test name
Test status
Simulation time 24022464725 ps
CPU time 595.8 seconds
Started Jul 06 06:00:53 PM PDT 24
Finished Jul 06 06:10:49 PM PDT 24
Peak memory 208348 kb
Host smart-16413bd4-b505-4661-bfd4-a516f140ad0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254265180 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3254265180
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3030373008
Short name T59
Test name
Test status
Simulation time 12139519609 ps
CPU time 19.72 seconds
Started Jul 06 06:00:53 PM PDT 24
Finished Jul 06 06:01:13 PM PDT 24
Peak memory 199864 kb
Host smart-2d75366d-fb73-4d14-b6ad-a52186093e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030373008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3030373008
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3730616014
Short name T1093
Test name
Test status
Simulation time 11492137106 ps
CPU time 131.74 seconds
Started Jul 06 06:00:55 PM PDT 24
Finished Jul 06 06:03:07 PM PDT 24
Peak memory 216528 kb
Host smart-d86fc782-bf35-4d0e-9eb0-5bdf2e1d292f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730616014 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3730616014
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3300787383
Short name T396
Test name
Test status
Simulation time 100321268948 ps
CPU time 9.45 seconds
Started Jul 06 06:01:00 PM PDT 24
Finished Jul 06 06:01:10 PM PDT 24
Peak memory 199696 kb
Host smart-2312a10b-0f3e-49a8-ace0-17adf14cc17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300787383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3300787383
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.236718763
Short name T903
Test name
Test status
Simulation time 68283395094 ps
CPU time 439.62 seconds
Started Jul 06 06:00:56 PM PDT 24
Finished Jul 06 06:08:15 PM PDT 24
Peak memory 226772 kb
Host smart-491f7a17-8d34-412b-becb-de425ddb92e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236718763 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.236718763
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1942221254
Short name T219
Test name
Test status
Simulation time 72372915987 ps
CPU time 97.1 seconds
Started Jul 06 06:00:56 PM PDT 24
Finished Jul 06 06:02:33 PM PDT 24
Peak memory 199928 kb
Host smart-b0ca66b4-1e21-4f9b-9611-6f029615d824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942221254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1942221254
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2327794500
Short name T980
Test name
Test status
Simulation time 18463793166 ps
CPU time 255.79 seconds
Started Jul 06 06:00:57 PM PDT 24
Finished Jul 06 06:05:13 PM PDT 24
Peak memory 208476 kb
Host smart-0a28f643-c848-42fa-a2cb-042586861814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327794500 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2327794500
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.311581366
Short name T1085
Test name
Test status
Simulation time 15361768 ps
CPU time 0.55 seconds
Started Jul 06 05:57:10 PM PDT 24
Finished Jul 06 05:57:11 PM PDT 24
Peak memory 195332 kb
Host smart-b2a71795-ee1a-4fce-bc4b-1733094bc0cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311581366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.311581366
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3480996848
Short name T1030
Test name
Test status
Simulation time 60550826743 ps
CPU time 99.35 seconds
Started Jul 06 05:57:09 PM PDT 24
Finished Jul 06 05:58:49 PM PDT 24
Peak memory 199976 kb
Host smart-987ca0f4-4e67-4fa5-aede-3f549dd1649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480996848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3480996848
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1261004637
Short name T740
Test name
Test status
Simulation time 166938848268 ps
CPU time 84.28 seconds
Started Jul 06 05:57:08 PM PDT 24
Finished Jul 06 05:58:33 PM PDT 24
Peak memory 200004 kb
Host smart-a210c5bd-bb85-422c-b9c7-8a68543a6e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261004637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1261004637
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4278313564
Short name T209
Test name
Test status
Simulation time 105553611088 ps
CPU time 120.04 seconds
Started Jul 06 05:57:09 PM PDT 24
Finished Jul 06 05:59:09 PM PDT 24
Peak memory 200008 kb
Host smart-2aea4c60-cbe2-422e-afc8-adf59385f104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278313564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4278313564
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.570941583
Short name T321
Test name
Test status
Simulation time 176689947673 ps
CPU time 340.68 seconds
Started Jul 06 05:57:24 PM PDT 24
Finished Jul 06 06:03:05 PM PDT 24
Peak memory 199820 kb
Host smart-2f3125dd-2f21-4a13-a2e9-8d21aad8d02a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570941583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.570941583
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1638716932
Short name T476
Test name
Test status
Simulation time 60671050508 ps
CPU time 405.24 seconds
Started Jul 06 05:57:12 PM PDT 24
Finished Jul 06 06:03:58 PM PDT 24
Peak memory 199952 kb
Host smart-48114e98-ab1a-46d2-ae70-d19378e596ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638716932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1638716932
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1961990934
Short name T368
Test name
Test status
Simulation time 1749405226 ps
CPU time 3.62 seconds
Started Jul 06 05:57:24 PM PDT 24
Finished Jul 06 05:57:28 PM PDT 24
Peak memory 196000 kb
Host smart-b804a955-c550-4a61-bafc-05985a404722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961990934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1961990934
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.450249761
Short name T297
Test name
Test status
Simulation time 106521700412 ps
CPU time 41.92 seconds
Started Jul 06 05:57:23 PM PDT 24
Finished Jul 06 05:58:05 PM PDT 24
Peak memory 199896 kb
Host smart-9d37980b-e405-46c5-8e0f-2cc4aa1be2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450249761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.450249761
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3256961570
Short name T534
Test name
Test status
Simulation time 21719175234 ps
CPU time 323.9 seconds
Started Jul 06 05:57:11 PM PDT 24
Finished Jul 06 06:02:35 PM PDT 24
Peak memory 200172 kb
Host smart-0b8eece3-49c8-4599-8cc8-b3716429882e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256961570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3256961570
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.495491462
Short name T963
Test name
Test status
Simulation time 1964838236 ps
CPU time 1.69 seconds
Started Jul 06 05:57:24 PM PDT 24
Finished Jul 06 05:57:26 PM PDT 24
Peak memory 197856 kb
Host smart-17125400-d882-4e7d-85f7-25e2508ec496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=495491462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.495491462
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1963969807
Short name T473
Test name
Test status
Simulation time 18036864401 ps
CPU time 38.87 seconds
Started Jul 06 05:57:23 PM PDT 24
Finished Jul 06 05:58:02 PM PDT 24
Peak memory 199908 kb
Host smart-0174a142-42bf-47ff-a2f1-c9eeee0d32a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963969807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1963969807
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3235378015
Short name T587
Test name
Test status
Simulation time 1502656876 ps
CPU time 1.88 seconds
Started Jul 06 05:57:11 PM PDT 24
Finished Jul 06 05:57:14 PM PDT 24
Peak memory 195532 kb
Host smart-262410bd-07b9-4f33-bc04-274e36bacf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235378015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3235378015
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2401586058
Short name T766
Test name
Test status
Simulation time 6247930653 ps
CPU time 9.81 seconds
Started Jul 06 05:57:08 PM PDT 24
Finished Jul 06 05:57:19 PM PDT 24
Peak memory 199736 kb
Host smart-2c3a0cd3-3051-46c6-91e9-236d0b746ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401586058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2401586058
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2586256646
Short name T277
Test name
Test status
Simulation time 167115424354 ps
CPU time 69.88 seconds
Started Jul 06 05:57:12 PM PDT 24
Finished Jul 06 05:58:22 PM PDT 24
Peak memory 199900 kb
Host smart-4ad81191-c8a3-46e2-96a8-9578f59bbb33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586256646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2586256646
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3323744958
Short name T911
Test name
Test status
Simulation time 1091040291743 ps
CPU time 1055.63 seconds
Started Jul 06 05:57:08 PM PDT 24
Finished Jul 06 06:14:44 PM PDT 24
Peak memory 228992 kb
Host smart-6a372932-7076-47a0-a261-08e394b0aa6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323744958 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3323744958
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.4019795132
Short name T417
Test name
Test status
Simulation time 949116009 ps
CPU time 2.26 seconds
Started Jul 06 05:57:09 PM PDT 24
Finished Jul 06 05:57:11 PM PDT 24
Peak memory 198328 kb
Host smart-a4311477-301d-4975-8736-abe1322ddefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019795132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.4019795132
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.698111292
Short name T658
Test name
Test status
Simulation time 15876375577 ps
CPU time 22.82 seconds
Started Jul 06 05:57:08 PM PDT 24
Finished Jul 06 05:57:32 PM PDT 24
Peak memory 199976 kb
Host smart-68bc6635-7339-4005-b4a5-c06cfca684d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698111292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.698111292
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2093471626
Short name T649
Test name
Test status
Simulation time 126424842311 ps
CPU time 182.4 seconds
Started Jul 06 06:00:56 PM PDT 24
Finished Jul 06 06:03:59 PM PDT 24
Peak memory 199912 kb
Host smart-be54ee30-9e82-45f6-9289-922273167d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093471626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2093471626
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1994654409
Short name T1180
Test name
Test status
Simulation time 41498932904 ps
CPU time 311.12 seconds
Started Jul 06 06:00:55 PM PDT 24
Finished Jul 06 06:06:06 PM PDT 24
Peak memory 208320 kb
Host smart-d7d3db96-c66b-477f-b6ab-38ca9e79eca2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994654409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1994654409
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.107899999
Short name T541
Test name
Test status
Simulation time 155885715303 ps
CPU time 139.01 seconds
Started Jul 06 06:00:55 PM PDT 24
Finished Jul 06 06:03:14 PM PDT 24
Peak memory 199960 kb
Host smart-19c46050-1dfb-460d-9b05-17804db8c6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107899999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.107899999
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.4024350421
Short name T841
Test name
Test status
Simulation time 87210862752 ps
CPU time 812.06 seconds
Started Jul 06 06:00:55 PM PDT 24
Finished Jul 06 06:14:27 PM PDT 24
Peak memory 216384 kb
Host smart-df49d759-2038-4af4-bff1-20179d62a5ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024350421 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.4024350421
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3046995135
Short name T1176
Test name
Test status
Simulation time 70903983420 ps
CPU time 19.32 seconds
Started Jul 06 06:00:55 PM PDT 24
Finished Jul 06 06:01:14 PM PDT 24
Peak memory 198548 kb
Host smart-f457b3a5-d32c-4d2c-bcde-0de6243a6d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046995135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3046995135
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2372409626
Short name T956
Test name
Test status
Simulation time 62820750825 ps
CPU time 780.23 seconds
Started Jul 06 06:00:55 PM PDT 24
Finished Jul 06 06:13:56 PM PDT 24
Peak memory 216420 kb
Host smart-07e66133-1043-48c2-8294-0209e2493d70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372409626 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2372409626
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.4102868082
Short name T180
Test name
Test status
Simulation time 22671279059 ps
CPU time 25.97 seconds
Started Jul 06 06:00:54 PM PDT 24
Finished Jul 06 06:01:20 PM PDT 24
Peak memory 199880 kb
Host smart-6354993c-e0be-42b6-a76d-a6d5da7f2c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102868082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.4102868082
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.399985546
Short name T116
Test name
Test status
Simulation time 93383151970 ps
CPU time 1235.88 seconds
Started Jul 06 06:01:07 PM PDT 24
Finished Jul 06 06:21:43 PM PDT 24
Peak memory 227748 kb
Host smart-0364b9e6-e8c4-4adc-9fe4-73aedcfad9b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399985546 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.399985546
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3171006538
Short name T58
Test name
Test status
Simulation time 71026664290 ps
CPU time 28.26 seconds
Started Jul 06 06:01:00 PM PDT 24
Finished Jul 06 06:01:28 PM PDT 24
Peak memory 199916 kb
Host smart-8dea5dc1-3a5c-4339-bd4c-cc5893f56bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171006538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3171006538
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3432871117
Short name T1096
Test name
Test status
Simulation time 140019852661 ps
CPU time 724.63 seconds
Started Jul 06 06:01:00 PM PDT 24
Finished Jul 06 06:13:05 PM PDT 24
Peak memory 224884 kb
Host smart-53278790-83ea-4f13-ae94-7fc3490bbeeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432871117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3432871117
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2475544154
Short name T733
Test name
Test status
Simulation time 39503250969 ps
CPU time 32.41 seconds
Started Jul 06 06:01:01 PM PDT 24
Finished Jul 06 06:01:33 PM PDT 24
Peak memory 199932 kb
Host smart-6071fa98-2e88-46ae-979c-e772a0d348cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475544154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2475544154
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3760375667
Short name T1105
Test name
Test status
Simulation time 66108604099 ps
CPU time 581.47 seconds
Started Jul 06 06:01:01 PM PDT 24
Finished Jul 06 06:10:42 PM PDT 24
Peak memory 224932 kb
Host smart-c58e8cba-52b0-4e13-a48e-6fec7b146afa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760375667 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3760375667
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.4061007850
Short name T503
Test name
Test status
Simulation time 40711294991 ps
CPU time 23.11 seconds
Started Jul 06 06:01:00 PM PDT 24
Finished Jul 06 06:01:23 PM PDT 24
Peak memory 199948 kb
Host smart-74b90b70-b7e4-4cb2-a0ec-b2c63b781dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061007850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.4061007850
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.109775488
Short name T120
Test name
Test status
Simulation time 23562637379 ps
CPU time 212.31 seconds
Started Jul 06 06:01:02 PM PDT 24
Finished Jul 06 06:04:34 PM PDT 24
Peak memory 215552 kb
Host smart-27537405-b9b0-4a72-923b-2140eef69fed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109775488 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.109775488
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.601122452
Short name T755
Test name
Test status
Simulation time 24555227476 ps
CPU time 13.12 seconds
Started Jul 06 06:01:01 PM PDT 24
Finished Jul 06 06:01:14 PM PDT 24
Peak memory 199944 kb
Host smart-c24f7779-6b97-4861-901d-6dfe8d3dc14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601122452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.601122452
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.214128003
Short name T878
Test name
Test status
Simulation time 132363206353 ps
CPU time 613.93 seconds
Started Jul 06 06:00:59 PM PDT 24
Finished Jul 06 06:11:13 PM PDT 24
Peak memory 216724 kb
Host smart-5419ea79-47b5-4e75-80b4-9ad06b1d7cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214128003 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.214128003
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2689106704
Short name T149
Test name
Test status
Simulation time 11948678752 ps
CPU time 158.79 seconds
Started Jul 06 06:01:04 PM PDT 24
Finished Jul 06 06:03:44 PM PDT 24
Peak memory 209480 kb
Host smart-a88c6e7b-6b86-42f4-9bba-b10d131ad36d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689106704 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2689106704
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2871156377
Short name T195
Test name
Test status
Simulation time 56304413227 ps
CPU time 25.34 seconds
Started Jul 06 06:01:05 PM PDT 24
Finished Jul 06 06:01:31 PM PDT 24
Peak memory 199912 kb
Host smart-72ed9251-c09e-43e4-881f-60b4b2a8a00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871156377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2871156377
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2674587934
Short name T823
Test name
Test status
Simulation time 43080512446 ps
CPU time 393.76 seconds
Started Jul 06 06:01:06 PM PDT 24
Finished Jul 06 06:07:40 PM PDT 24
Peak memory 215852 kb
Host smart-6bd236c8-33ae-4296-8686-e477059a94c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674587934 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2674587934
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1273658049
Short name T429
Test name
Test status
Simulation time 26770044 ps
CPU time 0.55 seconds
Started Jul 06 05:57:14 PM PDT 24
Finished Jul 06 05:57:14 PM PDT 24
Peak memory 195332 kb
Host smart-cd2a1352-48ac-40c8-8acf-cdd886f5da6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273658049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1273658049
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3701660175
Short name T137
Test name
Test status
Simulation time 96898201125 ps
CPU time 36.12 seconds
Started Jul 06 05:57:12 PM PDT 24
Finished Jul 06 05:57:49 PM PDT 24
Peak memory 199896 kb
Host smart-71187177-d086-4b05-8e64-646f1de5771a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701660175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3701660175
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1115004702
Short name T817
Test name
Test status
Simulation time 197846613561 ps
CPU time 864.88 seconds
Started Jul 06 05:57:23 PM PDT 24
Finished Jul 06 06:11:48 PM PDT 24
Peak memory 199692 kb
Host smart-ead1edfb-b4dc-41eb-b516-971ce50b9574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115004702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1115004702
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3884064195
Short name T537
Test name
Test status
Simulation time 35827624693 ps
CPU time 8.66 seconds
Started Jul 06 05:57:24 PM PDT 24
Finished Jul 06 05:57:33 PM PDT 24
Peak memory 199836 kb
Host smart-5c536da9-9217-490c-8831-1d59c2cb27ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884064195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3884064195
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.29796486
Short name T767
Test name
Test status
Simulation time 17729846192 ps
CPU time 15.52 seconds
Started Jul 06 05:57:16 PM PDT 24
Finished Jul 06 05:57:32 PM PDT 24
Peak memory 199972 kb
Host smart-ca631ddf-fd5f-4e45-8b91-bd7ea2b9ef0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29796486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.29796486
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.151066419
Short name T517
Test name
Test status
Simulation time 88455524919 ps
CPU time 387.92 seconds
Started Jul 06 05:57:14 PM PDT 24
Finished Jul 06 06:03:42 PM PDT 24
Peak memory 199876 kb
Host smart-a1b077d9-b05b-4301-b1e5-c0f556a758b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151066419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.151066419
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1055882490
Short name T398
Test name
Test status
Simulation time 7625644261 ps
CPU time 12.43 seconds
Started Jul 06 05:57:15 PM PDT 24
Finished Jul 06 05:57:28 PM PDT 24
Peak memory 199992 kb
Host smart-cbe794db-2224-4c56-9265-ed54e28ed22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055882490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1055882490
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2527836741
Short name T593
Test name
Test status
Simulation time 212064282961 ps
CPU time 147.63 seconds
Started Jul 06 05:57:16 PM PDT 24
Finished Jul 06 05:59:44 PM PDT 24
Peak memory 199196 kb
Host smart-ab86ddbc-2f61-4255-affb-15508a6299be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527836741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2527836741
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.279138207
Short name T940
Test name
Test status
Simulation time 21085558495 ps
CPU time 147.1 seconds
Started Jul 06 05:57:14 PM PDT 24
Finished Jul 06 05:59:42 PM PDT 24
Peak memory 199996 kb
Host smart-6d9781b6-4e5c-49b0-a8ac-3c1583acd757
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279138207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.279138207
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3066553282
Short name T610
Test name
Test status
Simulation time 4417385825 ps
CPU time 8.04 seconds
Started Jul 06 05:57:24 PM PDT 24
Finished Jul 06 05:57:32 PM PDT 24
Peak memory 199068 kb
Host smart-792fa410-a52a-4a20-a7b1-b62875be53fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066553282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3066553282
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1804037322
Short name T531
Test name
Test status
Simulation time 19058700553 ps
CPU time 15.68 seconds
Started Jul 06 05:57:14 PM PDT 24
Finished Jul 06 05:57:31 PM PDT 24
Peak memory 199912 kb
Host smart-be201913-ed92-4641-b817-5266ba83a7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804037322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1804037322
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3019613419
Short name T293
Test name
Test status
Simulation time 7315069660 ps
CPU time 10.84 seconds
Started Jul 06 05:57:13 PM PDT 24
Finished Jul 06 05:57:24 PM PDT 24
Peak memory 196076 kb
Host smart-3ff4ad03-48b9-4cce-afb0-fce6edbebbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019613419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3019613419
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1074661839
Short name T513
Test name
Test status
Simulation time 647499039 ps
CPU time 2.87 seconds
Started Jul 06 05:57:10 PM PDT 24
Finished Jul 06 05:57:13 PM PDT 24
Peak memory 199844 kb
Host smart-b0f80362-ec24-45c6-9bad-0b55c425fa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074661839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1074661839
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2677994146
Short name T250
Test name
Test status
Simulation time 275187829410 ps
CPU time 734.55 seconds
Started Jul 06 05:57:17 PM PDT 24
Finished Jul 06 06:09:32 PM PDT 24
Peak memory 216108 kb
Host smart-293c253f-12a7-4636-b228-ccce346526c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677994146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2677994146
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3203626715
Short name T85
Test name
Test status
Simulation time 39430593430 ps
CPU time 353.84 seconds
Started Jul 06 05:57:18 PM PDT 24
Finished Jul 06 06:03:12 PM PDT 24
Peak memory 216420 kb
Host smart-8f6f79e3-5aa7-4a57-b515-c6a3284ed020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203626715 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3203626715
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.105602287
Short name T785
Test name
Test status
Simulation time 830697305 ps
CPU time 2.43 seconds
Started Jul 06 05:57:17 PM PDT 24
Finished Jul 06 05:57:19 PM PDT 24
Peak memory 198652 kb
Host smart-0699aa70-fe7f-41d3-9b60-f0a36a6cc97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105602287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.105602287
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2065841510
Short name T728
Test name
Test status
Simulation time 16357553240 ps
CPU time 26.67 seconds
Started Jul 06 05:57:12 PM PDT 24
Finished Jul 06 05:57:39 PM PDT 24
Peak memory 199932 kb
Host smart-84ed41fd-6ee1-4d6d-9e4b-177c126fd1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065841510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2065841510
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2168167244
Short name T82
Test name
Test status
Simulation time 46702136083 ps
CPU time 20.55 seconds
Started Jul 06 06:01:07 PM PDT 24
Finished Jul 06 06:01:28 PM PDT 24
Peak memory 199880 kb
Host smart-8aeb396f-0330-41b9-b1d9-1a712bbf8d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168167244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2168167244
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.533484194
Short name T51
Test name
Test status
Simulation time 79962463401 ps
CPU time 1639.83 seconds
Started Jul 06 06:01:05 PM PDT 24
Finished Jul 06 06:28:25 PM PDT 24
Peak memory 216500 kb
Host smart-8a4d7b2a-3d32-448f-88c8-e4f335830fc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533484194 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.533484194
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3948883927
Short name T256
Test name
Test status
Simulation time 31903749909 ps
CPU time 28.53 seconds
Started Jul 06 06:01:05 PM PDT 24
Finished Jul 06 06:01:34 PM PDT 24
Peak memory 199892 kb
Host smart-a1832ff5-74c7-4bb4-b45f-ef12fadc2925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948883927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3948883927
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3373542544
Short name T139
Test name
Test status
Simulation time 123638696502 ps
CPU time 757.89 seconds
Started Jul 06 06:01:06 PM PDT 24
Finished Jul 06 06:13:45 PM PDT 24
Peak memory 225068 kb
Host smart-dbf388e1-5c9c-44c8-9cbe-05db7242004a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373542544 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3373542544
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2745031778
Short name T827
Test name
Test status
Simulation time 14003782592 ps
CPU time 12.69 seconds
Started Jul 06 06:01:07 PM PDT 24
Finished Jul 06 06:01:20 PM PDT 24
Peak memory 199972 kb
Host smart-914d8467-a43d-4ca7-bc1e-8c9e84e1e5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745031778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2745031778
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.4067172041
Short name T955
Test name
Test status
Simulation time 180954525106 ps
CPU time 765.59 seconds
Started Jul 06 06:01:08 PM PDT 24
Finished Jul 06 06:13:54 PM PDT 24
Peak memory 216320 kb
Host smart-855dfe0f-aef0-4c65-9505-28531b30f76b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067172041 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.4067172041
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.658115199
Short name T220
Test name
Test status
Simulation time 26832218835 ps
CPU time 52.45 seconds
Started Jul 06 06:01:09 PM PDT 24
Finished Jul 06 06:02:01 PM PDT 24
Peak memory 199964 kb
Host smart-a98cedd9-7cb3-4963-b24b-b883677d2710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658115199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.658115199
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.4275349938
Short name T544
Test name
Test status
Simulation time 8975886021 ps
CPU time 114.01 seconds
Started Jul 06 06:01:05 PM PDT 24
Finished Jul 06 06:02:59 PM PDT 24
Peak memory 216184 kb
Host smart-3d7751a7-135c-43f0-a8a2-ee30c174e538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275349938 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.4275349938
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2733031533
Short name T1011
Test name
Test status
Simulation time 107327047059 ps
CPU time 41.23 seconds
Started Jul 06 06:01:06 PM PDT 24
Finished Jul 06 06:01:48 PM PDT 24
Peak memory 199916 kb
Host smart-1cb938dc-f897-4c2d-841a-57d4f28988be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733031533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2733031533
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1655866960
Short name T8
Test name
Test status
Simulation time 47445586006 ps
CPU time 205.3 seconds
Started Jul 06 06:01:07 PM PDT 24
Finished Jul 06 06:04:33 PM PDT 24
Peak memory 216460 kb
Host smart-f87a279c-a1ee-49b7-a498-770404faf5f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655866960 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1655866960
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.4219959368
Short name T572
Test name
Test status
Simulation time 13160811620 ps
CPU time 22.71 seconds
Started Jul 06 06:01:06 PM PDT 24
Finished Jul 06 06:01:29 PM PDT 24
Peak memory 199992 kb
Host smart-6221a318-64c8-4c0a-b715-1899164fabbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219959368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.4219959368
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2814177277
Short name T1051
Test name
Test status
Simulation time 291403796194 ps
CPU time 1215.78 seconds
Started Jul 06 06:01:05 PM PDT 24
Finished Jul 06 06:21:21 PM PDT 24
Peak memory 216508 kb
Host smart-b112693c-6a0e-4e28-8cb2-7abc6f25934c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814177277 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2814177277
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1980228162
Short name T770
Test name
Test status
Simulation time 74247214685 ps
CPU time 123.34 seconds
Started Jul 06 06:01:05 PM PDT 24
Finished Jul 06 06:03:08 PM PDT 24
Peak memory 199852 kb
Host smart-9d0beda7-c43c-48a9-a898-e39bc6c08f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980228162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1980228162
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1119318346
Short name T705
Test name
Test status
Simulation time 16800014132 ps
CPU time 125.75 seconds
Started Jul 06 06:01:11 PM PDT 24
Finished Jul 06 06:03:17 PM PDT 24
Peak memory 215900 kb
Host smart-7e0bcadd-a88c-455f-8c4b-234929615f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119318346 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1119318346
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2320610965
Short name T840
Test name
Test status
Simulation time 36704463662 ps
CPU time 57.91 seconds
Started Jul 06 06:01:09 PM PDT 24
Finished Jul 06 06:02:07 PM PDT 24
Peak memory 199936 kb
Host smart-10b968b8-252c-487f-bf5a-c7034e89c0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320610965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2320610965
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1798940016
Short name T814
Test name
Test status
Simulation time 138396114405 ps
CPU time 649.86 seconds
Started Jul 06 06:01:09 PM PDT 24
Finished Jul 06 06:11:59 PM PDT 24
Peak memory 216532 kb
Host smart-ae668493-dfed-4fa9-8fb1-3c3fb634c49a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798940016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1798940016
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.361304768
Short name T237
Test name
Test status
Simulation time 32237555471 ps
CPU time 13.85 seconds
Started Jul 06 06:01:11 PM PDT 24
Finished Jul 06 06:01:25 PM PDT 24
Peak memory 199420 kb
Host smart-eff5f10e-93d7-466c-a0f5-91653276375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361304768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.361304768
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3452328125
Short name T532
Test name
Test status
Simulation time 21650925054 ps
CPU time 32.16 seconds
Started Jul 06 06:01:12 PM PDT 24
Finished Jul 06 06:01:44 PM PDT 24
Peak memory 200004 kb
Host smart-392f1cef-f6ed-4054-b159-0828ab9f5a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452328125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3452328125
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2558945410
Short name T895
Test name
Test status
Simulation time 43615636916 ps
CPU time 702.45 seconds
Started Jul 06 06:01:17 PM PDT 24
Finished Jul 06 06:13:00 PM PDT 24
Peak memory 216436 kb
Host smart-57e7b14d-b9ea-4cfe-a5f0-0f9b63c29189
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558945410 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2558945410
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1395637773
Short name T644
Test name
Test status
Simulation time 40342732 ps
CPU time 0.56 seconds
Started Jul 06 05:57:14 PM PDT 24
Finished Jul 06 05:57:15 PM PDT 24
Peak memory 194724 kb
Host smart-5f236620-85c3-4814-b8db-097d139039a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395637773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1395637773
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.940337492
Short name T1108
Test name
Test status
Simulation time 52710447434 ps
CPU time 35.56 seconds
Started Jul 06 05:57:14 PM PDT 24
Finished Jul 06 05:57:51 PM PDT 24
Peak memory 199908 kb
Host smart-277e77ec-40f3-432e-8b59-162238072778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940337492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.940337492
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1068894868
Short name T558
Test name
Test status
Simulation time 28994841439 ps
CPU time 67.3 seconds
Started Jul 06 05:57:14 PM PDT 24
Finished Jul 06 05:58:21 PM PDT 24
Peak memory 199944 kb
Host smart-6774b7b5-9ada-4475-b6d0-1598850fd0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068894868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1068894868
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.206924341
Short name T469
Test name
Test status
Simulation time 108777263026 ps
CPU time 21.11 seconds
Started Jul 06 05:57:15 PM PDT 24
Finished Jul 06 05:57:36 PM PDT 24
Peak memory 199976 kb
Host smart-0855ee96-1b5f-4c6c-bc18-628930e899cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206924341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.206924341
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2399959751
Short name T1135
Test name
Test status
Simulation time 12739270776 ps
CPU time 7.65 seconds
Started Jul 06 05:57:16 PM PDT 24
Finished Jul 06 05:57:23 PM PDT 24
Peak memory 199976 kb
Host smart-b15b0d62-2bad-4ec9-a7b3-90e449d6fc0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399959751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2399959751
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.369021478
Short name T726
Test name
Test status
Simulation time 126470116604 ps
CPU time 312.56 seconds
Started Jul 06 05:57:13 PM PDT 24
Finished Jul 06 06:02:26 PM PDT 24
Peak memory 199988 kb
Host smart-2416fcd3-64bb-4cc3-9ee7-e2e0468de5bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369021478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.369021478
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3588155320
Short name T719
Test name
Test status
Simulation time 10556368928 ps
CPU time 17.9 seconds
Started Jul 06 05:57:17 PM PDT 24
Finished Jul 06 05:57:35 PM PDT 24
Peak memory 199572 kb
Host smart-450e7c87-de1e-4282-bbb2-a8ea28fdcdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588155320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3588155320
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3810011090
Short name T1013
Test name
Test status
Simulation time 63798961626 ps
CPU time 46.79 seconds
Started Jul 06 05:57:14 PM PDT 24
Finished Jul 06 05:58:02 PM PDT 24
Peak memory 200184 kb
Host smart-9ca168ff-7abe-49d5-99be-a6d527925bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810011090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3810011090
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3797763568
Short name T454
Test name
Test status
Simulation time 29599789146 ps
CPU time 212.17 seconds
Started Jul 06 05:57:12 PM PDT 24
Finished Jul 06 06:00:45 PM PDT 24
Peak memory 200004 kb
Host smart-58c38815-857d-4af7-92c7-65c8c020d0c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797763568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3797763568
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2676285287
Short name T115
Test name
Test status
Simulation time 1775263943 ps
CPU time 8.65 seconds
Started Jul 06 05:57:13 PM PDT 24
Finished Jul 06 05:57:22 PM PDT 24
Peak memory 198124 kb
Host smart-f979133b-d88b-403a-bf0c-2df83b853cf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676285287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2676285287
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2829308502
Short name T432
Test name
Test status
Simulation time 126993937104 ps
CPU time 54.7 seconds
Started Jul 06 05:57:17 PM PDT 24
Finished Jul 06 05:58:12 PM PDT 24
Peak memory 199908 kb
Host smart-305b1835-4ddd-4571-80da-5c4d76eb4ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829308502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2829308502
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1676361319
Short name T457
Test name
Test status
Simulation time 4722992418 ps
CPU time 2.3 seconds
Started Jul 06 05:57:14 PM PDT 24
Finished Jul 06 05:57:16 PM PDT 24
Peak memory 196804 kb
Host smart-6148c995-c1d2-4335-989a-5ae08e145d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676361319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1676361319
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1483193117
Short name T560
Test name
Test status
Simulation time 449433936 ps
CPU time 1.98 seconds
Started Jul 06 05:57:13 PM PDT 24
Finished Jul 06 05:57:15 PM PDT 24
Peak memory 199764 kb
Host smart-ea762d51-02e3-43bd-a4e3-c70b0482f495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483193117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1483193117
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3023468011
Short name T622
Test name
Test status
Simulation time 59693440670 ps
CPU time 91.74 seconds
Started Jul 06 05:57:15 PM PDT 24
Finished Jul 06 05:58:47 PM PDT 24
Peak memory 199920 kb
Host smart-1036403e-4cbd-46f4-b59e-a273755cc6a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023468011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3023468011
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2716758696
Short name T27
Test name
Test status
Simulation time 14530241753 ps
CPU time 395.63 seconds
Started Jul 06 05:57:14 PM PDT 24
Finished Jul 06 06:03:50 PM PDT 24
Peak memory 215592 kb
Host smart-12fca0ce-50dd-47c5-8ee0-807bcc255383
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716758696 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2716758696
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3464370061
Short name T301
Test name
Test status
Simulation time 1180709955 ps
CPU time 4.29 seconds
Started Jul 06 05:57:13 PM PDT 24
Finished Jul 06 05:57:17 PM PDT 24
Peak memory 198988 kb
Host smart-8a672198-1d3b-4145-be87-2111cfb55a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464370061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3464370061
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3111403569
Short name T526
Test name
Test status
Simulation time 41732745153 ps
CPU time 60.56 seconds
Started Jul 06 05:57:15 PM PDT 24
Finished Jul 06 05:58:16 PM PDT 24
Peak memory 199972 kb
Host smart-19247898-b661-4b94-92fd-f2e02709a3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111403569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3111403569
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3866979259
Short name T226
Test name
Test status
Simulation time 53825983236 ps
CPU time 20.79 seconds
Started Jul 06 06:01:10 PM PDT 24
Finished Jul 06 06:01:31 PM PDT 24
Peak memory 199856 kb
Host smart-7333d601-e9a0-42fb-9012-da09ba262691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866979259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3866979259
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.407792241
Short name T216
Test name
Test status
Simulation time 301971366064 ps
CPU time 42.72 seconds
Started Jul 06 06:01:10 PM PDT 24
Finished Jul 06 06:01:53 PM PDT 24
Peak memory 199908 kb
Host smart-41c69e4e-d408-47ad-9945-df6d73a9861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407792241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.407792241
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3896056874
Short name T1015
Test name
Test status
Simulation time 109285770471 ps
CPU time 383.57 seconds
Started Jul 06 06:01:10 PM PDT 24
Finished Jul 06 06:07:34 PM PDT 24
Peak memory 210672 kb
Host smart-87957f44-457b-406e-b509-0392b84bfb02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896056874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3896056874
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2368292236
Short name T225
Test name
Test status
Simulation time 73113718749 ps
CPU time 132.74 seconds
Started Jul 06 06:01:18 PM PDT 24
Finished Jul 06 06:03:31 PM PDT 24
Peak memory 199956 kb
Host smart-1a8dd7db-90ac-4847-8ea2-189849fe41bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368292236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2368292236
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2273655910
Short name T52
Test name
Test status
Simulation time 109716789946 ps
CPU time 454.63 seconds
Started Jul 06 06:01:11 PM PDT 24
Finished Jul 06 06:08:46 PM PDT 24
Peak memory 216476 kb
Host smart-8ffa570c-23a6-4553-953d-53866a8f2c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273655910 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2273655910
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.752152348
Short name T129
Test name
Test status
Simulation time 33030560899 ps
CPU time 622.58 seconds
Started Jul 06 06:01:17 PM PDT 24
Finished Jul 06 06:11:39 PM PDT 24
Peak memory 216676 kb
Host smart-5ae0f962-53c5-404a-a393-7055de4f41b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752152348 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.752152348
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.12992321
Short name T240
Test name
Test status
Simulation time 55326622448 ps
CPU time 43.84 seconds
Started Jul 06 06:01:17 PM PDT 24
Finished Jul 06 06:02:01 PM PDT 24
Peak memory 199896 kb
Host smart-f685ca07-d6b3-4013-af90-49864ffb989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12992321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.12992321
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.4012986003
Short name T696
Test name
Test status
Simulation time 831848529207 ps
CPU time 1066.2 seconds
Started Jul 06 06:01:18 PM PDT 24
Finished Jul 06 06:19:04 PM PDT 24
Peak memory 232968 kb
Host smart-d44bb546-2ec3-4380-b9bb-fd384df9ca55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012986003 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.4012986003
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2151861402
Short name T444
Test name
Test status
Simulation time 48977644313 ps
CPU time 80.19 seconds
Started Jul 06 06:01:18 PM PDT 24
Finished Jul 06 06:02:39 PM PDT 24
Peak memory 199940 kb
Host smart-4c31d446-14cd-4518-ac18-0111ca6e679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151861402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2151861402
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2778792405
Short name T1147
Test name
Test status
Simulation time 86455917951 ps
CPU time 388.35 seconds
Started Jul 06 06:01:17 PM PDT 24
Finished Jul 06 06:07:46 PM PDT 24
Peak memory 215040 kb
Host smart-458954b4-243b-44ec-bd4b-10c1ca5cd540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778792405 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2778792405
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3283741149
Short name T569
Test name
Test status
Simulation time 23899661858 ps
CPU time 42.55 seconds
Started Jul 06 06:01:17 PM PDT 24
Finished Jul 06 06:01:59 PM PDT 24
Peak memory 199920 kb
Host smart-99505c43-d29d-4386-8d7c-e5610d5233e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283741149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3283741149
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.142545675
Short name T54
Test name
Test status
Simulation time 316765979012 ps
CPU time 1177.47 seconds
Started Jul 06 06:01:17 PM PDT 24
Finished Jul 06 06:20:55 PM PDT 24
Peak memory 224832 kb
Host smart-6b3eebb8-53dc-41b2-909c-ee663c3a4df4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142545675 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.142545675
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2127398290
Short name T918
Test name
Test status
Simulation time 38494711824 ps
CPU time 61.22 seconds
Started Jul 06 06:01:17 PM PDT 24
Finished Jul 06 06:02:19 PM PDT 24
Peak memory 200008 kb
Host smart-a1cfcc7a-e4d0-42e4-be9d-669bb16d5f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127398290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2127398290
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.831424415
Short name T231
Test name
Test status
Simulation time 542648126624 ps
CPU time 664.71 seconds
Started Jul 06 06:01:19 PM PDT 24
Finished Jul 06 06:12:24 PM PDT 24
Peak memory 230452 kb
Host smart-a31f26f3-aa47-46ec-96a3-a80a7b0f678a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831424415 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.831424415
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.753302424
Short name T1026
Test name
Test status
Simulation time 22804763263 ps
CPU time 19.58 seconds
Started Jul 06 06:01:18 PM PDT 24
Finished Jul 06 06:01:38 PM PDT 24
Peak memory 199932 kb
Host smart-dcff99e8-a626-4d67-9049-1db12314d95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753302424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.753302424
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1438567727
Short name T49
Test name
Test status
Simulation time 92782546361 ps
CPU time 349.41 seconds
Started Jul 06 06:01:17 PM PDT 24
Finished Jul 06 06:07:06 PM PDT 24
Peak memory 216652 kb
Host smart-50708ac5-926d-42e7-8e01-12fe14698137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438567727 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1438567727
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.390441790
Short name T35
Test name
Test status
Simulation time 157333273334 ps
CPU time 60.38 seconds
Started Jul 06 06:01:20 PM PDT 24
Finished Jul 06 06:02:21 PM PDT 24
Peak memory 199852 kb
Host smart-ed7a6cec-f8f1-416d-8585-3cc849187e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390441790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.390441790
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.989916307
Short name T923
Test name
Test status
Simulation time 30102874906 ps
CPU time 375.21 seconds
Started Jul 06 06:01:21 PM PDT 24
Finished Jul 06 06:07:36 PM PDT 24
Peak memory 216528 kb
Host smart-5d52e802-fb8b-4fdd-b590-e48cf69e3b99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989916307 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.989916307
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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