Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	122036	1			T1	2		T2	1447		T3	490
all_values[1]	122036	1			T1	2		T2	1447		T3	490
all_values[2]	122036	1			T1	2		T2	1447		T3	490
all_values[3]	122036	1			T1	2		T2	1447		T3	490
all_values[4]	122036	1			T1	2		T2	1447		T3	490
all_values[5]	122036	1			T1	2		T2	1447		T3	490
all_values[6]	122036	1			T1	2		T2	1447		T3	490
all_values[7]	122036	1			T1	2		T2	1447		T3	490
all_values[8]	122036	1			T1	2		T2	1447		T3	490

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

559987

1

T1

18

T2

7412

T3

2172

auto[1]

538337

1

T2

5611

T3

2238

T4

314

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

998570

1

T1

13

T2

12096

T3

4096

auto[1]

99754

1

T1

5

T2

927

T3

314

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	34035	1			T2	449		T3	194		T4	43
all_values[0]	auto[0]	auto[1]	25583	1			T1	2		T2	1		T3	123
all_values[0]	auto[1]	auto[0]	37545	1			T2	535		T3	138		T4	27
all_values[0]	auto[1]	auto[1]	24873	1			T2	462		T3	35		T4	4
all_values[1]	auto[0]	auto[0]	61955	1			T1	2		T2	742		T3	170
all_values[1]	auto[0]	auto[1]	1524	1			T3	3		T9	10		T42	2
all_values[1]	auto[1]	auto[0]	56754	1			T2	705		T3	317		T4	51
all_values[1]	auto[1]	auto[1]	1803	1			T4	2		T8	33		T12	2
all_values[2]	auto[0]	auto[0]	57475	1			T1	1		T2	794		T3	245
all_values[2]	auto[0]	auto[1]	2946	1			T1	1		T2	10		T3	3
all_values[2]	auto[1]	auto[0]	59097	1			T2	643		T3	226		T4	31
all_values[2]	auto[1]	auto[1]	2518	1			T3	16		T4	5		T5	3
all_values[3]	auto[0]	auto[0]	61633	1			T1	2		T2	790		T3	283
all_values[3]	auto[0]	auto[1]	317	1			T9	1		T23	2		T19	3
all_values[3]	auto[1]	auto[0]	59808	1			T2	657		T3	207		T4	34
all_values[3]	auto[1]	auto[1]	278	1			T12	1		T14	1		T190	3
all_values[4]	auto[0]	auto[0]	64690	1			T1	2		T2	790		T3	337
all_values[4]	auto[0]	auto[1]	459	1			T17	2		T18	1		T19	16
all_values[4]	auto[1]	auto[0]	56471	1			T2	657		T3	153		T4	49
all_values[4]	auto[1]	auto[1]	416	1			T23	1		T18	14		T21	7
all_values[5]	auto[0]	auto[0]	61619	1			T1	2		T2	1149		T3	193
all_values[5]	auto[0]	auto[1]	185	1			T35	3		T134	2		T117	1
all_values[5]	auto[1]	auto[0]	60050	1			T2	298		T3	297		T4	37
all_values[5]	auto[1]	auto[1]	182	1			T35	2		T95	2		T134	4
all_values[6]	auto[0]	auto[0]	63020	1			T1	2		T2	706		T3	206
all_values[6]	auto[0]	auto[1]	188	1			T17	3		T95	2		T134	4
all_values[6]	auto[1]	auto[0]	58638	1			T2	741		T3	284		T4	12
all_values[6]	auto[1]	auto[1]	190	1			T35	2		T95	2		T134	2
all_values[7]	auto[0]	auto[0]	59813	1			T1	2		T2	983		T3	287
all_values[7]	auto[0]	auto[1]	393	1			T9	3		T20	5		T35	2
all_values[7]	auto[1]	auto[0]	61486	1			T2	464		T3	203		T4	34
all_values[7]	auto[1]	auto[1]	344	1			T147	1		T17	3		T19	3
all_values[8]	auto[0]	auto[0]	44429	1			T2	544		T3	37		T4	50
all_values[8]	auto[0]	auto[1]	19723	1			T1	2		T2	454		T3	91
all_values[8]	auto[1]	auto[0]	40052	1			T2	449		T3	319		T4	21
all_values[8]	auto[1]	auto[1]	17832	1			T3	43		T4	7		T5	2