Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2270	1			T1	1		T4	2		T5	2
auto[BaudRate115200]	2190	1			T2	4		T3	2		T4	5
auto[BaudRate230400]	2093	1			T3	4		T4	2		T5	4
auto[BaudRate128Kbps]	2080	1			T1	1		T3	1		T5	1
auto[BaudRate256Kbps]	2325	1			T3	2		T4	12		T5	1
auto[BaudRate1Mbps]	1969	1			T2	2		T3	1		T4	9
auto[BaudRate1p5Mbps]	1434	1			T8	2		T9	8		T44	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1758	1			T7	6		T46	9		T13	10
freqs[25]	1323	1			T6	6		T41	2		T34	7
freqs[48]	567	1			T9	64		T143	9		T232	7
freqs[50]	653	1			T2	6		T8	9		T23	147
freqs[100]	1485	1			T47	9		T123	12		T264	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	274	1			T7	1		T14	2		T51	3
auto[BaudRate9600]	freqs[25]	205	1			T6	1		T20	3		T16	10
auto[BaudRate9600]	freqs[48]	61	1			T9	5		T143	1		T308	1
auto[BaudRate9600]	freqs[50]	81	1			T8	3		T23	24		T300	1
auto[BaudRate9600]	freqs[100]	203	1			T123	1		T309	1		T263	5
auto[BaudRate115200]	freqs[24]	279	1			T46	2		T13	1		T14	1
auto[BaudRate115200]	freqs[25]	158	1			T34	1		T20	1		T310	1
auto[BaudRate115200]	freqs[48]	69	1			T9	12		T143	2		T311	9
auto[BaudRate115200]	freqs[50]	115	1			T2	4		T23	19		T312	6
auto[BaudRate115200]	freqs[100]	220	1			T47	2		T123	2		T263	11
auto[BaudRate230400]	freqs[24]	280	1			T46	4		T13	2		T14	1
auto[BaudRate230400]	freqs[25]	199	1			T6	1		T34	1		T20	1
auto[BaudRate230400]	freqs[48]	88	1			T9	10		T143	1		T232	2
auto[BaudRate230400]	freqs[50]	60	1			T8	2		T23	14		T312	3
auto[BaudRate230400]	freqs[100]	220	1			T47	1		T123	1		T263	10
auto[BaudRate128Kbps]	freqs[24]	236	1			T46	1		T13	4		T14	2
auto[BaudRate128Kbps]	freqs[25]	187	1			T6	1		T41	1		T34	1
auto[BaudRate128Kbps]	freqs[48]	88	1			T9	12		T143	1		T232	3
auto[BaudRate128Kbps]	freqs[50]	112	1			T23	34		T256	2		T313	12
auto[BaudRate128Kbps]	freqs[100]	222	1			T47	2		T123	1		T263	19
auto[BaudRate256Kbps]	freqs[24]	270	1			T7	3		T46	1		T13	2
auto[BaudRate256Kbps]	freqs[25]	216	1			T6	2		T41	1		T34	3
auto[BaudRate256Kbps]	freqs[48]	98	1			T9	11		T143	2		T232	1
auto[BaudRate256Kbps]	freqs[50]	76	1			T8	2		T23	23		T313	3
auto[BaudRate256Kbps]	freqs[100]	213	1			T47	1		T123	1		T264	1
auto[BaudRate1Mbps]	freqs[24]	291	1			T7	2		T46	1		T14	2
auto[BaudRate1Mbps]	freqs[25]	224	1			T6	1		T34	1		T20	1
auto[BaudRate1Mbps]	freqs[48]	63	1			T9	6		T143	1		T232	1
auto[BaudRate1Mbps]	freqs[50]	109	1			T2	2		T23	23		T300	1
auto[BaudRate1Mbps]	freqs[100]	223	1			T47	2		T123	3		T264	3
auto[BaudRate1p5Mbps]	freqs[25]	134	1			T20	1		T268	2		T314	3
auto[BaudRate1p5Mbps]	freqs[48]	100	1			T9	8		T143	1		T308	3
auto[BaudRate1p5Mbps]	freqs[50]	100	1			T8	2		T23	10		T300	1
auto[BaudRate1p5Mbps]	freqs[100]	184	1			T47	1		T123	3		T264	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded