Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	33731864	1			T2	496626		T3	180620		T4	84824
all_levels[1]	194937	1			T2	237		T3	256		T4	4414
all_levels[2]	2504	1			T4	15		T5	2		T8	14
all_levels[3]	1179	1			T5	2		T8	7		T9	2
all_levels[4]	794	1			T4	1		T5	1		T8	2
all_levels[5]	623	1			T8	2		T44	1		T12	2
all_levels[6]	501	1			T5	4		T44	2		T129	1
all_levels[7]	378	1			T12	2		T25	2		T13	2
all_levels[8]	336	1			T9	1		T46	1		T12	1
all_levels[9]	272	1			T4	1		T5	1		T9	1
all_levels[10]	248	1			T4	1		T12	2		T129	1
all_levels[11]	224	1			T5	1		T9	2		T25	1
all_levels[12]	182	1			T8	1		T42	1		T46	1
all_levels[13]	177	1			T4	1		T8	2		T46	2
all_levels[14]	148	1			T6	4		T9	1		T23	1
all_levels[15]	130	1			T46	1		T13	1		T140	2
all_levels[16]	111	1			T9	1		T14	3		T23	1
all_levels[17]	113	1			T46	1		T25	1		T13	2
all_levels[18]	85	1			T9	2		T46	1		T129	1
all_levels[19]	105	1			T141	1		T14	1		T128	1
all_levels[20]	84	1			T13	1		T48	1		T142	1
all_levels[21]	80	1			T141	1		T143	1		T56	1
all_levels[22]	67	1			T9	2		T46	1		T130	1
all_levels[23]	68	1			T17	1		T143	2		T53	1
all_levels[24]	60	1			T42	1		T13	1		T128	1
all_levels[25]	58	1			T141	1		T144	3		T145	1
all_levels[26]	56	1			T126	1		T56	1		T146	3
all_levels[27]	49	1			T9	1		T147	1		T13	1
all_levels[28]	46	1			T129	2		T13	1		T148	1
all_levels[29]	47	1			T46	1		T14	1		T59	1
all_levels[30]	50	1			T130	1		T51	1		T52	1
all_levels[31]	34	1			T23	1		T59	1		T40	1
all_levels[32]	32	1			T9	1		T143	2		T146	1
all_levels[33]	32	1			T9	1		T13	1		T126	1
all_levels[34]	37	1			T48	1		T14	1		T126	1
all_levels[35]	25	1			T8	1		T149	1		T150	2
all_levels[36]	26	1			T151	3		T125	4		T152	1
all_levels[37]	29	1			T9	1		T153	1		T40	1
all_levels[38]	25	1			T13	2		T119	2		T64	1
all_levels[39]	19	1			T4	1		T152	1		T36	1
all_levels[40]	21	1			T144	1		T148	1		T154	1
all_levels[41]	24	1			T143	1		T35	1		T59	1
all_levels[42]	21	1			T126	1		T155	1		T156	1
all_levels[43]	16	1			T58	1		T59	1		T157	1
all_levels[44]	11	1			T158	1		T159	1		T160	1
all_levels[45]	15	1			T141	1		T152	3		T131	1
all_levels[46]	14	1			T42	1		T127	1		T161	1
all_levels[47]	19	1			T129	2		T13	1		T14	1
all_levels[48]	12	1			T162	1		T163	1		T164	1
all_levels[49]	21	1			T165	1		T23	1		T163	1
all_levels[50]	20	1			T46	1		T13	1		T126	1
all_levels[51]	11	1			T46	1		T77	1		T166	2
all_levels[52]	16	1			T46	1		T56	1		T167	1
all_levels[53]	7	1			T141	1		T168	1		T110	1
all_levels[54]	16	1			T58	2		T146	1		T158	1
all_levels[55]	9	1			T169	1		T170	1		T171	1
all_levels[56]	8	1			T129	2		T172	1		T173	1
all_levels[57]	12	1			T129	1		T36	1		T158	1
all_levels[58]	7	1			T174	1		T175	1		T176	1
all_levels[59]	5	1			T177	2		T178	1		T179	1
all_levels[60]	9	1			T152	2		T148	1		T158	1
all_levels[61]	9	1			T17	1		T180	1		T181	2
all_levels[62]	7	1			T130	1		T127	1		T158	2
all_levels[63]	2	1			T182	1		T183	1		-	-
all_levels[64]	111	1			T9	1		T13	1		T141	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33931293

1

T2

496863

T3

180876

T4

89258

auto[1]

4965

1

T6

6

T9

15

T10

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[29]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[47] , all_levels[48]]	[auto[1]]	--	--	2
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[61] , all_levels[62] , all_levels[63]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	33727356	1			T2	496626		T3	180620		T4	84824
all_levels[0]	auto[1]	4508	1			T6	3		T9	13		T10	1
all_levels[1]	auto[0]	194857	1			T2	237		T3	256		T4	4414
all_levels[1]	auto[1]	80	1			T9	1		T127	1		T152	1
all_levels[2]	auto[0]	2478	1			T4	15		T5	2		T8	14
all_levels[2]	auto[1]	26	1			T130	1		T36	2		T39	2
all_levels[3]	auto[0]	1159	1			T5	2		T8	7		T9	2
all_levels[3]	auto[1]	20	1			T14	1		T144	1		T56	2
all_levels[4]	auto[0]	773	1			T4	1		T5	1		T8	2
all_levels[4]	auto[1]	21	1			T157	1		T184	2		T185	2
all_levels[5]	auto[0]	598	1			T8	2		T44	1		T12	1
all_levels[5]	auto[1]	25	1			T12	1		T77	1		T186	1
all_levels[6]	auto[0]	481	1			T5	4		T44	2		T129	1
all_levels[6]	auto[1]	20	1			T130	1		T60	2		T187	1
all_levels[7]	auto[0]	370	1			T12	2		T25	2		T13	2
all_levels[7]	auto[1]	8	1			T188	1		T146	1		T189	1
all_levels[8]	auto[0]	326	1			T9	1		T46	1		T12	1
all_levels[8]	auto[1]	10	1			T129	1		T72	1		T78	1
all_levels[9]	auto[0]	257	1			T4	1		T5	1		T9	1
all_levels[9]	auto[1]	15	1			T190	1		T157	2		T191	3
all_levels[10]	auto[0]	219	1			T4	1		T12	2		T129	1
all_levels[10]	auto[1]	29	1			T192	2		T23	10		T77	1
all_levels[11]	auto[0]	217	1			T5	1		T9	2		T25	1
all_levels[11]	auto[1]	7	1			T193	1		T194	2		T167	1
all_levels[12]	auto[0]	175	1			T8	1		T42	1		T46	1
all_levels[12]	auto[1]	7	1			T195	1		T196	1		T197	1
all_levels[13]	auto[0]	168	1			T4	1		T8	2		T46	2
all_levels[13]	auto[1]	9	1			T163	1		T77	3		T198	2
all_levels[14]	auto[0]	136	1			T6	1		T9	1		T23	1
all_levels[14]	auto[1]	12	1			T6	3		T193	1		T199	1
all_levels[15]	auto[0]	116	1			T46	1		T13	1		T140	1
all_levels[15]	auto[1]	14	1			T140	1		T23	1		T146	1
all_levels[16]	auto[0]	106	1			T9	1		T14	1		T23	1
all_levels[16]	auto[1]	5	1			T14	2		T200	1		T201	1
all_levels[17]	auto[0]	103	1			T46	1		T25	1		T13	2
all_levels[17]	auto[1]	10	1			T202	2		T203	1		T204	1
all_levels[18]	auto[0]	80	1			T9	2		T46	1		T129	1
all_levels[18]	auto[1]	5	1			T205	1		T206	1		T207	1
all_levels[19]	auto[0]	96	1			T141	1		T14	1		T128	1
all_levels[19]	auto[1]	9	1			T193	1		T159	1		T208	1
all_levels[20]	auto[0]	77	1			T13	1		T48	1		T142	1
all_levels[20]	auto[1]	7	1			T58	2		T209	1		T210	2
all_levels[21]	auto[0]	74	1			T141	1		T143	1		T56	1
all_levels[21]	auto[1]	6	1			T211	1		T212	1		T213	1
all_levels[22]	auto[0]	64	1			T9	1		T46	1		T130	1
all_levels[22]	auto[1]	3	1			T9	1		T214	1		T215	1
all_levels[23]	auto[0]	61	1			T17	1		T143	2		T53	1
all_levels[23]	auto[1]	7	1			T216	2		T217	1		T218	1
all_levels[24]	auto[0]	53	1			T42	1		T13	1		T128	1
all_levels[24]	auto[1]	7	1			T17	1		T219	1		T220	3
all_levels[25]	auto[0]	53	1			T141	1		T144	1		T145	1
all_levels[25]	auto[1]	5	1			T144	2		T221	3		-	-
all_levels[26]	auto[0]	50	1			T126	1		T56	1		T146	2
all_levels[26]	auto[1]	6	1			T146	1		T222	4		T170	1
all_levels[27]	auto[0]	44	1			T9	1		T147	1		T13	1
all_levels[27]	auto[1]	5	1			T223	3		T224	1		T225	1
all_levels[28]	auto[0]	44	1			T129	2		T13	1		T148	1
all_levels[28]	auto[1]	2	1			T209	1		T154	1		-	-
all_levels[29]	auto[0]	47	1			T46	1		T14	1		T59	1
all_levels[30]	auto[0]	43	1			T130	1		T51	1		T52	1
all_levels[30]	auto[1]	7	1			T226	1		T227	1		T223	1
all_levels[31]	auto[0]	29	1			T23	1		T59	1		T40	1
all_levels[31]	auto[1]	5	1			T168	1		T228	1		T229	1
all_levels[32]	auto[0]	27	1			T9	1		T143	2		T146	1
all_levels[32]	auto[1]	5	1			T149	4		T230	1		-	-
all_levels[33]	auto[0]	29	1			T9	1		T13	1		T126	1
all_levels[33]	auto[1]	3	1			T159	1		T231	2		-	-
all_levels[34]	auto[0]	30	1			T48	1		T14	1		T126	1
all_levels[34]	auto[1]	7	1			T232	1		T233	1		T234	3
all_levels[35]	auto[0]	24	1			T8	1		T149	1		T150	2
all_levels[35]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[36]	auto[0]	19	1			T151	1		T125	1		T152	1
all_levels[36]	auto[1]	7	1			T151	2		T125	3		T236	1
all_levels[37]	auto[0]	28	1			T9	1		T153	1		T40	1
all_levels[37]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[38]	auto[0]	22	1			T13	2		T119	1		T64	1
all_levels[38]	auto[1]	3	1			T119	1		T238	1		T239	1
all_levels[39]	auto[0]	19	1			T4	1		T152	1		T36	1
all_levels[40]	auto[0]	20	1			T144	1		T148	1		T154	1
all_levels[40]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[41]	auto[0]	20	1			T143	1		T35	1		T59	1
all_levels[41]	auto[1]	4	1			T208	2		T241	1		T179	1
all_levels[42]	auto[0]	19	1			T126	1		T155	1		T156	1
all_levels[42]	auto[1]	2	1			T242	2		-	-		-	-
all_levels[43]	auto[0]	16	1			T58	1		T59	1		T157	1
all_levels[44]	auto[0]	10	1			T158	1		T159	1		T160	1
all_levels[44]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[45]	auto[0]	12	1			T141	1		T152	1		T131	1
all_levels[45]	auto[1]	3	1			T152	2		T244	1		-	-
all_levels[46]	auto[0]	13	1			T42	1		T127	1		T161	1
all_levels[46]	auto[1]	1	1			T72	1		-	-		-	-
all_levels[47]	auto[0]	19	1			T129	2		T13	1		T14	1
all_levels[48]	auto[0]	12	1			T162	1		T163	1		T164	1
all_levels[49]	auto[0]	20	1			T165	1		T23	1		T163	1
all_levels[49]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[50]	auto[0]	17	1			T46	1		T13	1		T126	1
all_levels[50]	auto[1]	3	1			T246	1		T247	1		T248	1
all_levels[51]	auto[0]	10	1			T46	1		T77	1		T166	1
all_levels[51]	auto[1]	1	1			T166	1		-	-		-	-
all_levels[52]	auto[0]	16	1			T46	1		T56	1		T167	1
all_levels[53]	auto[0]	6	1			T141	1		T168	1		T110	1
all_levels[53]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[54]	auto[0]	14	1			T58	2		T146	1		T158	1
all_levels[54]	auto[1]	2	1			T250	2		-	-		-	-
all_levels[55]	auto[0]	9	1			T169	1		T170	1		T171	1
all_levels[56]	auto[0]	7	1			T129	1		T172	1		T173	1
all_levels[56]	auto[1]	1	1			T129	1		-	-		-	-
all_levels[57]	auto[0]	9	1			T129	1		T36	1		T158	1
all_levels[57]	auto[1]	3	1			T251	3		-	-		-	-
all_levels[58]	auto[0]	5	1			T174	1		T175	1		T176	1
all_levels[58]	auto[1]	2	1			T252	2		-	-		-	-
all_levels[59]	auto[0]	5	1			T177	2		T178	1		T179	1
all_levels[60]	auto[0]	7	1			T152	1		T148	1		T158	1
all_levels[60]	auto[1]	2	1			T152	1		T253	1		-	-
all_levels[61]	auto[0]	9	1			T17	1		T180	1		T181	2
all_levels[62]	auto[0]	7	1			T130	1		T127	1		T158	2
all_levels[63]	auto[0]	2	1			T182	1		T183	1		-	-
all_levels[64]	auto[0]	101	1			T9	1		T13	1		T141	1
all_levels[64]	auto[1]	10	1			T14	1		T190	1		T56	1